1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVALID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
60 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
63 #define HNS3_RESET_WAIT_MS 100
64 #define HNS3_RESET_WAIT_CNT 200
67 HNS3_VECTOR0_EVENT_RST,
68 HNS3_VECTOR0_EVENT_MBX,
69 HNS3_VECTOR0_EVENT_ERR,
70 HNS3_VECTOR0_EVENT_OTHER,
73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
80 static int hns3_add_mc_addr(struct hns3_hw *hw,
81 struct rte_ether_addr *mac_addr);
82 static int hns3_remove_mc_addr(struct hns3_hw *hw,
83 struct rte_ether_addr *mac_addr);
86 hns3_pf_disable_irq0(struct hns3_hw *hw)
88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
92 hns3_pf_enable_irq0(struct hns3_hw *hw)
94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
97 static enum hns3_evt_cause
98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
100 struct hns3_hw *hw = &hns->hw;
101 uint32_t vector0_int_stats;
102 uint32_t cmdq_src_val;
103 uint32_t hw_err_src_reg;
105 enum hns3_evt_cause ret;
107 /* fetch the events from their corresponding regs */
108 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
109 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
110 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
113 * Assumption: If by any chance reset and mailbox events are reported
114 * together then we will only process reset event and defer the
115 * processing of the mailbox events. Since, we would have not cleared
116 * RX CMDQ event this time we would receive again another interrupt
117 * from H/W just for the mailbox.
119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
120 rte_atomic16_set(&hw->reset.disable_cmd, 1);
121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
124 hw->reset.stats.imp_cnt++;
125 hns3_warn(hw, "IMP reset detected, clear reset status");
127 hns3_schedule_delayed_reset(hns);
128 hns3_warn(hw, "IMP reset detected, don't clear reset status");
131 ret = HNS3_VECTOR0_EVENT_RST;
136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
137 rte_atomic16_set(&hw->reset.disable_cmd, 1);
138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
141 hw->reset.stats.global_cnt++;
142 hns3_warn(hw, "Global reset detected, clear reset status");
144 hns3_schedule_delayed_reset(hns);
145 hns3_warn(hw, "Global reset detected, don't clear reset status");
148 ret = HNS3_VECTOR0_EVENT_RST;
152 /* check for vector0 msix event source */
153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
154 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
155 val = vector0_int_stats | hw_err_src_reg;
156 ret = HNS3_VECTOR0_EVENT_ERR;
160 /* check for vector0 mailbox(=CMDQ RX) event source */
161 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
162 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
164 ret = HNS3_VECTOR0_EVENT_MBX;
168 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
169 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
170 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
171 val = vector0_int_stats;
172 ret = HNS3_VECTOR0_EVENT_OTHER;
181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
183 if (event_type == HNS3_VECTOR0_EVENT_RST)
184 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
185 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
186 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
190 hns3_clear_all_event_cause(struct hns3_hw *hw)
192 uint32_t vector0_int_stats;
193 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
196 hns3_warn(hw, "Probe during IMP reset interrupt");
198 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
199 hns3_warn(hw, "Probe during Global reset interrupt");
201 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
202 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
203 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
204 BIT(HNS3_VECTOR0_CORERESET_INT_B));
205 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
209 hns3_interrupt_handler(void *param)
211 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
212 struct hns3_adapter *hns = dev->data->dev_private;
213 struct hns3_hw *hw = &hns->hw;
214 enum hns3_evt_cause event_cause;
215 uint32_t clearval = 0;
217 /* Disable interrupt */
218 hns3_pf_disable_irq0(hw);
220 event_cause = hns3_check_event_cause(hns, &clearval);
222 /* vector 0 interrupt is shared with reset and mailbox source events. */
223 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
224 hns3_warn(hw, "Received err interrupt");
225 hns3_handle_msix_error(hns, &hw->reset.request);
226 hns3_handle_ras_error(hns, &hw->reset.request);
227 hns3_schedule_reset(hns);
228 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
229 hns3_warn(hw, "Received reset interrupt");
230 hns3_schedule_reset(hns);
231 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
232 hns3_dev_handle_mbx_msg(hw);
234 hns3_err(hw, "Received unknown event");
236 hns3_clear_event_cause(hw, event_cause, clearval);
237 /* Enable interrupt if it is not cause by reset */
238 hns3_pf_enable_irq0(hw);
242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
244 #define HNS3_VLAN_ID_OFFSET_STEP 160
245 #define HNS3_VLAN_BYTE_SIZE 8
246 struct hns3_vlan_filter_pf_cfg_cmd *req;
247 struct hns3_hw *hw = &hns->hw;
248 uint8_t vlan_offset_byte_val;
249 struct hns3_cmd_desc desc;
250 uint8_t vlan_offset_byte;
251 uint8_t vlan_offset_base;
254 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
256 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
257 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
259 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
261 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
262 req->vlan_offset = vlan_offset_base;
263 req->vlan_cfg = on ? 0 : 1;
264 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
266 ret = hns3_cmd_send(hw, &desc, 1);
268 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
277 struct hns3_user_vlan_table *vlan_entry;
278 struct hns3_pf *pf = &hns->pf;
280 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
281 if (vlan_entry->vlan_id == vlan_id) {
282 if (vlan_entry->hd_tbl_status)
283 hns3_set_port_vlan_filter(hns, vlan_id, 0);
284 LIST_REMOVE(vlan_entry, next);
285 rte_free(vlan_entry);
292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
295 struct hns3_user_vlan_table *vlan_entry;
296 struct hns3_hw *hw = &hns->hw;
297 struct hns3_pf *pf = &hns->pf;
299 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
300 if (vlan_entry->vlan_id == vlan_id)
304 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
305 if (vlan_entry == NULL) {
306 hns3_err(hw, "Failed to malloc hns3 vlan table");
310 vlan_entry->hd_tbl_status = writen_to_tbl;
311 vlan_entry->vlan_id = vlan_id;
313 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
317 hns3_restore_vlan_table(struct hns3_adapter *hns)
319 struct hns3_user_vlan_table *vlan_entry;
320 struct hns3_hw *hw = &hns->hw;
321 struct hns3_pf *pf = &hns->pf;
325 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
326 return hns3_vlan_pvid_configure(hns,
327 hw->port_base_vlan_cfg.pvid, 1);
329 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
330 if (vlan_entry->hd_tbl_status) {
331 vlan_id = vlan_entry->vlan_id;
332 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
344 struct hns3_hw *hw = &hns->hw;
345 bool writen_to_tbl = false;
349 * When vlan filter is enabled, hardware regards packets without vlan
350 * as packets with vlan 0. So, to receive packets without vlan, vlan id
351 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
353 if (on == 0 && vlan_id == 0)
357 * When port base vlan enabled, we use port base vlan as the vlan
358 * filter condition. In this case, we don't update vlan filter table
359 * when user add new vlan or remove exist vlan, just update the
360 * vlan list. The vlan id in vlan list will be writen in vlan filter
361 * table until port base vlan disabled
363 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
364 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
365 writen_to_tbl = true;
370 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
372 hns3_rm_dev_vlan_table(hns, vlan_id);
378 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
380 struct hns3_adapter *hns = dev->data->dev_private;
381 struct hns3_hw *hw = &hns->hw;
384 rte_spinlock_lock(&hw->lock);
385 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
386 rte_spinlock_unlock(&hw->lock);
391 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
394 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
395 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
396 struct hns3_hw *hw = &hns->hw;
397 struct hns3_cmd_desc desc;
400 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
401 vlan_type != ETH_VLAN_TYPE_OUTER)) {
402 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
406 if (tpid != RTE_ETHER_TYPE_VLAN) {
407 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
411 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
412 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
414 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
415 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
416 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
417 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
418 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
419 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
420 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
421 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
424 ret = hns3_cmd_send(hw, &desc, 1);
426 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
433 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
434 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
435 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
437 ret = hns3_cmd_send(hw, &desc, 1);
439 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
445 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
448 struct hns3_adapter *hns = dev->data->dev_private;
449 struct hns3_hw *hw = &hns->hw;
452 rte_spinlock_lock(&hw->lock);
453 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
454 rte_spinlock_unlock(&hw->lock);
459 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
460 struct hns3_rx_vtag_cfg *vcfg)
462 struct hns3_vport_vtag_rx_cfg_cmd *req;
463 struct hns3_hw *hw = &hns->hw;
464 struct hns3_cmd_desc desc;
469 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
471 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
472 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
473 vcfg->strip_tag1_en ? 1 : 0);
474 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
475 vcfg->strip_tag2_en ? 1 : 0);
476 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
477 vcfg->vlan1_vlan_prionly ? 1 : 0);
478 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
479 vcfg->vlan2_vlan_prionly ? 1 : 0);
481 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
482 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
483 vcfg->strip_tag1_discard_en ? 1 : 0);
484 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
485 vcfg->strip_tag2_discard_en ? 1 : 0);
487 * In current version VF is not supported when PF is driven by DPDK
488 * driver, just need to configure parameters for PF vport.
490 vport_id = HNS3_PF_FUNC_ID;
491 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
492 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
493 req->vf_bitmap[req->vf_offset] = bitmap;
495 ret = hns3_cmd_send(hw, &desc, 1);
497 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
502 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
503 struct hns3_rx_vtag_cfg *vcfg)
505 struct hns3_pf *pf = &hns->pf;
506 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
510 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
511 struct hns3_tx_vtag_cfg *vcfg)
513 struct hns3_pf *pf = &hns->pf;
514 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
518 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
520 struct hns3_rx_vtag_cfg rxvlan_cfg;
521 struct hns3_hw *hw = &hns->hw;
524 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
525 rxvlan_cfg.strip_tag1_en = false;
526 rxvlan_cfg.strip_tag2_en = enable;
527 rxvlan_cfg.strip_tag2_discard_en = false;
529 rxvlan_cfg.strip_tag1_en = enable;
530 rxvlan_cfg.strip_tag2_en = true;
531 rxvlan_cfg.strip_tag2_discard_en = true;
534 rxvlan_cfg.strip_tag1_discard_en = false;
535 rxvlan_cfg.vlan1_vlan_prionly = false;
536 rxvlan_cfg.vlan2_vlan_prionly = false;
537 rxvlan_cfg.rx_vlan_offload_en = enable;
539 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
541 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
545 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
551 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
552 uint8_t fe_type, bool filter_en, uint8_t vf_id)
554 struct hns3_vlan_filter_ctrl_cmd *req;
555 struct hns3_cmd_desc desc;
558 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
560 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
561 req->vlan_type = vlan_type;
562 req->vlan_fe = filter_en ? fe_type : 0;
565 ret = hns3_cmd_send(hw, &desc, 1);
567 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
573 hns3_vlan_filter_init(struct hns3_adapter *hns)
575 struct hns3_hw *hw = &hns->hw;
578 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
579 HNS3_FILTER_FE_EGRESS, false,
582 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
586 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
587 HNS3_FILTER_FE_INGRESS, false,
590 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
596 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
598 struct hns3_hw *hw = &hns->hw;
601 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
602 HNS3_FILTER_FE_INGRESS, enable,
605 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
606 enable ? "enable" : "disable", ret);
612 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
614 struct hns3_adapter *hns = dev->data->dev_private;
615 struct hns3_hw *hw = &hns->hw;
616 struct rte_eth_rxmode *rxmode;
617 unsigned int tmp_mask;
621 rte_spinlock_lock(&hw->lock);
622 rxmode = &dev->data->dev_conf.rxmode;
623 tmp_mask = (unsigned int)mask;
624 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
625 /* ignore vlan filter configuration during promiscuous mode */
626 if (!dev->data->promiscuous) {
627 /* Enable or disable VLAN filter */
628 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
631 ret = hns3_enable_vlan_filter(hns, enable);
633 rte_spinlock_unlock(&hw->lock);
634 hns3_err(hw, "failed to %s rx filter, ret = %d",
635 enable ? "enable" : "disable", ret);
641 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
642 /* Enable or disable VLAN stripping */
643 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
646 ret = hns3_en_hw_strip_rxvtag(hns, enable);
648 rte_spinlock_unlock(&hw->lock);
649 hns3_err(hw, "failed to %s rx strip, ret = %d",
650 enable ? "enable" : "disable", ret);
655 rte_spinlock_unlock(&hw->lock);
661 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
662 struct hns3_tx_vtag_cfg *vcfg)
664 struct hns3_vport_vtag_tx_cfg_cmd *req;
665 struct hns3_cmd_desc desc;
666 struct hns3_hw *hw = &hns->hw;
671 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
673 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
674 req->def_vlan_tag1 = vcfg->default_tag1;
675 req->def_vlan_tag2 = vcfg->default_tag2;
676 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
677 vcfg->accept_tag1 ? 1 : 0);
678 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
679 vcfg->accept_untag1 ? 1 : 0);
680 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
681 vcfg->accept_tag2 ? 1 : 0);
682 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
683 vcfg->accept_untag2 ? 1 : 0);
684 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
685 vcfg->insert_tag1_en ? 1 : 0);
686 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
687 vcfg->insert_tag2_en ? 1 : 0);
688 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
690 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
691 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
692 vcfg->tag_shift_mode_en ? 1 : 0);
695 * In current version VF is not supported when PF is driven by DPDK
696 * driver, just need to configure parameters for PF vport.
698 vport_id = HNS3_PF_FUNC_ID;
699 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
700 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
701 req->vf_bitmap[req->vf_offset] = bitmap;
703 ret = hns3_cmd_send(hw, &desc, 1);
705 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
711 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
714 struct hns3_hw *hw = &hns->hw;
715 struct hns3_tx_vtag_cfg txvlan_cfg;
718 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
719 txvlan_cfg.accept_tag1 = true;
720 txvlan_cfg.insert_tag1_en = false;
721 txvlan_cfg.default_tag1 = 0;
723 txvlan_cfg.accept_tag1 =
724 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
725 txvlan_cfg.insert_tag1_en = true;
726 txvlan_cfg.default_tag1 = pvid;
729 txvlan_cfg.accept_untag1 = true;
730 txvlan_cfg.accept_tag2 = true;
731 txvlan_cfg.accept_untag2 = true;
732 txvlan_cfg.insert_tag2_en = false;
733 txvlan_cfg.default_tag2 = 0;
734 txvlan_cfg.tag_shift_mode_en = true;
736 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
738 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
743 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
749 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
751 struct hns3_user_vlan_table *vlan_entry;
752 struct hns3_pf *pf = &hns->pf;
754 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
755 if (vlan_entry->hd_tbl_status) {
756 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
757 vlan_entry->hd_tbl_status = false;
762 vlan_entry = LIST_FIRST(&pf->vlan_list);
764 LIST_REMOVE(vlan_entry, next);
765 rte_free(vlan_entry);
766 vlan_entry = LIST_FIRST(&pf->vlan_list);
772 hns3_add_all_vlan_table(struct hns3_adapter *hns)
774 struct hns3_user_vlan_table *vlan_entry;
775 struct hns3_pf *pf = &hns->pf;
777 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
778 if (!vlan_entry->hd_tbl_status) {
779 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
780 vlan_entry->hd_tbl_status = true;
786 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
788 struct hns3_hw *hw = &hns->hw;
791 hns3_rm_all_vlan_table(hns, true);
792 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
793 ret = hns3_set_port_vlan_filter(hns,
794 hw->port_base_vlan_cfg.pvid, 0);
796 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
804 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
805 uint16_t port_base_vlan_state, uint16_t new_pvid)
807 struct hns3_hw *hw = &hns->hw;
811 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
812 old_pvid = hw->port_base_vlan_cfg.pvid;
813 if (old_pvid != HNS3_INVALID_PVID) {
814 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
816 hns3_err(hw, "failed to remove old pvid %u, "
817 "ret = %d", old_pvid, ret);
822 hns3_rm_all_vlan_table(hns, false);
823 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
825 hns3_err(hw, "failed to add new pvid %u, ret = %d",
830 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
832 hns3_err(hw, "failed to remove pvid %u, ret = %d",
837 hns3_add_all_vlan_table(hns);
843 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
845 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
846 struct hns3_rx_vtag_cfg rx_vlan_cfg;
850 rx_strip_en = old_cfg->rx_vlan_offload_en;
852 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
853 rx_vlan_cfg.strip_tag2_en = true;
854 rx_vlan_cfg.strip_tag2_discard_en = true;
856 rx_vlan_cfg.strip_tag1_en = false;
857 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
858 rx_vlan_cfg.strip_tag2_discard_en = false;
860 rx_vlan_cfg.strip_tag1_discard_en = false;
861 rx_vlan_cfg.vlan1_vlan_prionly = false;
862 rx_vlan_cfg.vlan2_vlan_prionly = false;
863 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
865 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
869 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
874 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
876 struct hns3_hw *hw = &hns->hw;
877 uint16_t port_base_vlan_state;
880 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
881 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
882 hns3_warn(hw, "Invalid operation! As current pvid set "
883 "is %u, disable pvid %u is invalid",
884 hw->port_base_vlan_cfg.pvid, pvid);
888 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
889 HNS3_PORT_BASE_VLAN_DISABLE;
890 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
892 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
897 ret = hns3_en_pvid_strip(hns, on);
899 hns3_err(hw, "failed to config rx vlan strip for pvid, "
904 if (pvid == HNS3_INVALID_PVID)
906 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
908 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
914 hw->port_base_vlan_cfg.state = port_base_vlan_state;
915 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
920 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
922 struct hns3_adapter *hns = dev->data->dev_private;
923 struct hns3_hw *hw = &hns->hw;
924 bool pvid_en_state_change;
928 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
929 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
930 RTE_ETHER_MAX_VLAN_ID);
935 * If PVID configuration state change, should refresh the PVID
936 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
938 pvid_state = hw->port_base_vlan_cfg.state;
939 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
940 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
941 pvid_en_state_change = false;
943 pvid_en_state_change = true;
945 rte_spinlock_lock(&hw->lock);
946 ret = hns3_vlan_pvid_configure(hns, pvid, on);
947 rte_spinlock_unlock(&hw->lock);
951 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
952 * need be processed by PMD driver.
954 if (pvid_en_state_change &&
955 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
956 hns3_update_all_queues_pvid_proc_en(hw);
962 hns3_default_vlan_config(struct hns3_adapter *hns)
964 struct hns3_hw *hw = &hns->hw;
968 * When vlan filter is enabled, hardware regards packets without vlan
969 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
970 * table, packets without vlan won't be received. So, add vlan 0 as
973 ret = hns3_vlan_filter_configure(hns, 0, 1);
975 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
980 hns3_init_vlan_config(struct hns3_adapter *hns)
982 struct hns3_hw *hw = &hns->hw;
986 * This function can be called in the initialization and reset process,
987 * when in reset process, it means that hardware had been reseted
988 * successfully and we need to restore the hardware configuration to
989 * ensure that the hardware configuration remains unchanged before and
992 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
993 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
994 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
997 ret = hns3_vlan_filter_init(hns);
999 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1003 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1004 RTE_ETHER_TYPE_VLAN);
1006 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1011 * When in the reinit dev stage of the reset process, the following
1012 * vlan-related configurations may differ from those at initialization,
1013 * we will restore configurations to hardware in hns3_restore_vlan_table
1014 * and hns3_restore_vlan_conf later.
1016 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1017 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1019 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1023 ret = hns3_en_hw_strip_rxvtag(hns, false);
1025 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1031 return hns3_default_vlan_config(hns);
1035 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1037 struct hns3_pf *pf = &hns->pf;
1038 struct hns3_hw *hw = &hns->hw;
1043 if (!hw->data->promiscuous) {
1044 /* restore vlan filter states */
1045 offloads = hw->data->dev_conf.rxmode.offloads;
1046 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1047 ret = hns3_enable_vlan_filter(hns, enable);
1049 hns3_err(hw, "failed to restore vlan rx filter conf, "
1055 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1057 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1061 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1063 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1069 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1071 struct hns3_adapter *hns = dev->data->dev_private;
1072 struct rte_eth_dev_data *data = dev->data;
1073 struct rte_eth_txmode *txmode;
1074 struct hns3_hw *hw = &hns->hw;
1078 txmode = &data->dev_conf.txmode;
1079 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1081 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1082 "configuration is not supported! Ignore these two "
1083 "parameters: hw_vlan_reject_tagged(%d), "
1084 "hw_vlan_reject_untagged(%d)",
1085 txmode->hw_vlan_reject_tagged,
1086 txmode->hw_vlan_reject_untagged);
1088 /* Apply vlan offload setting */
1089 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1090 ret = hns3_vlan_offload_set(dev, mask);
1092 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1098 * If pvid config is not set in rte_eth_conf, driver needn't to set
1099 * VLAN pvid related configuration to hardware.
1101 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1104 /* Apply pvid setting */
1105 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1106 txmode->hw_vlan_insert_pvid);
1108 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1115 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1116 unsigned int tso_mss_max)
1118 struct hns3_cfg_tso_status_cmd *req;
1119 struct hns3_cmd_desc desc;
1122 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1124 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1127 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1129 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1132 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1134 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1136 return hns3_cmd_send(hw, &desc, 1);
1140 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1141 uint16_t *allocated_size, bool is_alloc)
1143 struct hns3_umv_spc_alc_cmd *req;
1144 struct hns3_cmd_desc desc;
1147 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1148 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1149 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1150 req->space_size = rte_cpu_to_le_32(space_size);
1152 ret = hns3_cmd_send(hw, &desc, 1);
1154 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1155 is_alloc ? "allocate" : "free", ret);
1159 if (is_alloc && allocated_size)
1160 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1166 hns3_init_umv_space(struct hns3_hw *hw)
1168 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169 struct hns3_pf *pf = &hns->pf;
1170 uint16_t allocated_size = 0;
1173 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1178 if (allocated_size < pf->wanted_umv_size)
1179 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1180 pf->wanted_umv_size, allocated_size);
1182 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1183 pf->wanted_umv_size;
1184 pf->used_umv_size = 0;
1189 hns3_uninit_umv_space(struct hns3_hw *hw)
1191 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1192 struct hns3_pf *pf = &hns->pf;
1195 if (pf->max_umv_size == 0)
1198 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1202 pf->max_umv_size = 0;
1208 hns3_is_umv_space_full(struct hns3_hw *hw)
1210 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1211 struct hns3_pf *pf = &hns->pf;
1214 is_full = (pf->used_umv_size >= pf->max_umv_size);
1220 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1222 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1223 struct hns3_pf *pf = &hns->pf;
1226 if (pf->used_umv_size > 0)
1227 pf->used_umv_size--;
1229 pf->used_umv_size++;
1233 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1234 const uint8_t *addr, bool is_mc)
1236 const unsigned char *mac_addr = addr;
1237 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1238 ((uint32_t)mac_addr[2] << 16) |
1239 ((uint32_t)mac_addr[1] << 8) |
1240 (uint32_t)mac_addr[0];
1241 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1243 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1245 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1246 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1247 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1250 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1251 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1255 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1257 enum hns3_mac_vlan_tbl_opcode op)
1260 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1265 if (op == HNS3_MAC_VLAN_ADD) {
1266 if (resp_code == 0 || resp_code == 1) {
1268 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1269 hns3_err(hw, "add mac addr failed for uc_overflow");
1271 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1272 hns3_err(hw, "add mac addr failed for mc_overflow");
1276 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1279 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1280 if (resp_code == 0) {
1282 } else if (resp_code == 1) {
1283 hns3_dbg(hw, "remove mac addr failed for miss");
1287 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1290 } else if (op == HNS3_MAC_VLAN_LKUP) {
1291 if (resp_code == 0) {
1293 } else if (resp_code == 1) {
1294 hns3_dbg(hw, "lookup mac addr failed for miss");
1298 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1303 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1310 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1311 struct hns3_mac_vlan_tbl_entry_cmd *req,
1312 struct hns3_cmd_desc *desc, bool is_mc)
1318 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1320 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1321 memcpy(desc[0].data, req,
1322 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1325 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1326 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1328 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1330 memcpy(desc[0].data, req,
1331 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1332 ret = hns3_cmd_send(hw, desc, 1);
1335 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1339 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1340 retval = rte_le_to_cpu_16(desc[0].retval);
1342 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343 HNS3_MAC_VLAN_LKUP);
1347 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1348 struct hns3_mac_vlan_tbl_entry_cmd *req,
1349 struct hns3_cmd_desc *mc_desc)
1356 if (mc_desc == NULL) {
1357 struct hns3_cmd_desc desc;
1359 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1360 memcpy(desc.data, req,
1361 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362 ret = hns3_cmd_send(hw, &desc, 1);
1363 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1364 retval = rte_le_to_cpu_16(desc.retval);
1366 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1369 hns3_cmd_reuse_desc(&mc_desc[0], false);
1370 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371 hns3_cmd_reuse_desc(&mc_desc[1], false);
1372 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1373 hns3_cmd_reuse_desc(&mc_desc[2], false);
1374 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1375 memcpy(mc_desc[0].data, req,
1376 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1377 mc_desc[0].retval = 0;
1378 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1380 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1382 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1387 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1395 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1396 struct hns3_mac_vlan_tbl_entry_cmd *req)
1398 struct hns3_cmd_desc desc;
1403 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1405 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1407 ret = hns3_cmd_send(hw, &desc, 1);
1409 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1412 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1413 retval = rte_le_to_cpu_16(desc.retval);
1415 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1416 HNS3_MAC_VLAN_REMOVE);
1420 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1422 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1423 struct hns3_mac_vlan_tbl_entry_cmd req;
1424 struct hns3_pf *pf = &hns->pf;
1425 struct hns3_cmd_desc desc[3];
1426 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1427 uint16_t egress_port = 0;
1431 /* check if mac addr is valid */
1432 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1433 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1435 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1440 memset(&req, 0, sizeof(req));
1443 * In current version VF is not supported when PF is driven by DPDK
1444 * driver, just need to configure parameters for PF vport.
1446 vf_id = HNS3_PF_FUNC_ID;
1447 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1448 HNS3_MAC_EPORT_VFID_S, vf_id);
1450 req.egress_port = rte_cpu_to_le_16(egress_port);
1452 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1455 * Lookup the mac address in the mac_vlan table, and add
1456 * it if the entry is inexistent. Repeated unicast entry
1457 * is not allowed in the mac vlan table.
1459 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1460 if (ret == -ENOENT) {
1461 if (!hns3_is_umv_space_full(hw)) {
1462 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1464 hns3_update_umv_space(hw, false);
1468 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1473 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1475 /* check if we just hit the duplicate */
1477 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1481 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1488 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1490 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1491 struct rte_ether_addr *addr;
1495 for (i = 0; i < hw->mc_addrs_num; i++) {
1496 addr = &hw->mc_addrs[i];
1497 /* Check if there are duplicate addresses */
1498 if (rte_is_same_ether_addr(addr, mac_addr)) {
1499 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1501 hns3_err(hw, "failed to add mc mac addr, same addrs"
1502 "(%s) is added by the set_mc_mac_addr_list "
1508 ret = hns3_add_mc_addr(hw, mac_addr);
1510 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1519 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1521 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1524 ret = hns3_remove_mc_addr(hw, mac_addr);
1526 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1528 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1535 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1536 uint32_t idx, __rte_unused uint32_t pool)
1538 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1542 rte_spinlock_lock(&hw->lock);
1545 * In hns3 network engine adding UC and MC mac address with different
1546 * commands with firmware. We need to determine whether the input
1547 * address is a UC or a MC address to call different commands.
1548 * By the way, it is recommended calling the API function named
1549 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1550 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1551 * may affect the specifications of UC mac addresses.
1553 if (rte_is_multicast_ether_addr(mac_addr))
1554 ret = hns3_add_mc_addr_common(hw, mac_addr);
1556 ret = hns3_add_uc_addr_common(hw, mac_addr);
1559 rte_spinlock_unlock(&hw->lock);
1560 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1568 hw->mac.default_addr_setted = true;
1569 rte_spinlock_unlock(&hw->lock);
1575 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1577 struct hns3_mac_vlan_tbl_entry_cmd req;
1578 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1581 /* check if mac addr is valid */
1582 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1583 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1585 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1590 memset(&req, 0, sizeof(req));
1591 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1592 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1593 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1594 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1597 hns3_update_umv_space(hw, true);
1603 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1605 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 /* index will be checked by upper level rte interface */
1607 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1608 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611 rte_spinlock_lock(&hw->lock);
1613 if (rte_is_multicast_ether_addr(mac_addr))
1614 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1616 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1617 rte_spinlock_unlock(&hw->lock);
1619 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1621 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1627 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1628 struct rte_ether_addr *mac_addr)
1630 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631 struct rte_ether_addr *oaddr;
1632 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1633 bool default_addr_setted;
1634 bool rm_succes = false;
1638 * It has been guaranteed that input parameter named mac_addr is valid
1639 * address in the rte layer of DPDK framework.
1641 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1642 default_addr_setted = hw->mac.default_addr_setted;
1643 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1646 rte_spinlock_lock(&hw->lock);
1647 if (default_addr_setted) {
1648 ret = hns3_remove_uc_addr_common(hw, oaddr);
1650 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1652 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1659 ret = hns3_add_uc_addr_common(hw, mac_addr);
1661 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1664 goto err_add_uc_addr;
1667 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1669 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1670 goto err_pause_addr_cfg;
1673 rte_ether_addr_copy(mac_addr,
1674 (struct rte_ether_addr *)hw->mac.mac_addr);
1675 hw->mac.default_addr_setted = true;
1676 rte_spinlock_unlock(&hw->lock);
1681 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1683 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686 "Failed to roll back to del setted mac addr(%s): %d",
1692 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1694 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1697 "Failed to restore old uc mac addr(%s): %d",
1699 hw->mac.default_addr_setted = false;
1702 rte_spinlock_unlock(&hw->lock);
1708 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1710 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1711 struct hns3_hw *hw = &hns->hw;
1712 struct rte_ether_addr *addr;
1717 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1718 addr = &hw->data->mac_addrs[i];
1719 if (rte_is_zero_ether_addr(addr))
1721 if (rte_is_multicast_ether_addr(addr))
1722 ret = del ? hns3_remove_mc_addr(hw, addr) :
1723 hns3_add_mc_addr(hw, addr);
1725 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1726 hns3_add_uc_addr_common(hw, addr);
1730 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1732 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1733 "ret = %d.", del ? "remove" : "restore",
1741 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1743 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1747 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1748 word_num = vfid / 32;
1749 bit_num = vfid % 32;
1751 desc[1].data[word_num] &=
1752 rte_cpu_to_le_32(~(1UL << bit_num));
1754 desc[1].data[word_num] |=
1755 rte_cpu_to_le_32(1UL << bit_num);
1757 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1758 bit_num = vfid % 32;
1760 desc[2].data[word_num] &=
1761 rte_cpu_to_le_32(~(1UL << bit_num));
1763 desc[2].data[word_num] |=
1764 rte_cpu_to_le_32(1UL << bit_num);
1769 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1771 struct hns3_mac_vlan_tbl_entry_cmd req;
1772 struct hns3_cmd_desc desc[3];
1773 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1777 /* Check if mac addr is valid */
1778 if (!rte_is_multicast_ether_addr(mac_addr)) {
1779 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1786 memset(&req, 0, sizeof(req));
1787 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1788 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1789 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1791 /* This mac addr do not exist, add new entry for it */
1792 memset(desc[0].data, 0, sizeof(desc[0].data));
1793 memset(desc[1].data, 0, sizeof(desc[0].data));
1794 memset(desc[2].data, 0, sizeof(desc[0].data));
1798 * In current version VF is not supported when PF is driven by DPDK
1799 * driver, just need to configure parameters for PF vport.
1801 vf_id = HNS3_PF_FUNC_ID;
1802 hns3_update_desc_vfid(desc, vf_id, false);
1803 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1806 hns3_err(hw, "mc mac vlan table is full");
1807 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1809 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1816 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1818 struct hns3_mac_vlan_tbl_entry_cmd req;
1819 struct hns3_cmd_desc desc[3];
1820 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824 /* Check if mac addr is valid */
1825 if (!rte_is_multicast_ether_addr(mac_addr)) {
1826 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1828 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1833 memset(&req, 0, sizeof(req));
1834 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1835 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1836 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1839 * This mac addr exist, remove this handle's VFID for it.
1840 * In current version VF is not supported when PF is driven by
1841 * DPDK driver, just need to configure parameters for PF vport.
1843 vf_id = HNS3_PF_FUNC_ID;
1844 hns3_update_desc_vfid(desc, vf_id, true);
1846 /* All the vfid is zero, so need to delete this entry */
1847 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1848 } else if (ret == -ENOENT) {
1849 /* This mac addr doesn't exist. */
1854 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1856 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1863 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1864 struct rte_ether_addr *mc_addr_set,
1865 uint32_t nb_mc_addr)
1867 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1868 struct rte_ether_addr *addr;
1872 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1873 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1874 "invalid. valid range: 0~%d",
1875 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1879 /* Check if input mac addresses are valid */
1880 for (i = 0; i < nb_mc_addr; i++) {
1881 addr = &mc_addr_set[i];
1882 if (!rte_is_multicast_ether_addr(addr)) {
1883 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1886 "failed to set mc mac addr, addr(%s) invalid.",
1891 /* Check if there are duplicate addresses */
1892 for (j = i + 1; j < nb_mc_addr; j++) {
1893 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1894 rte_ether_format_addr(mac_str,
1895 RTE_ETHER_ADDR_FMT_SIZE,
1897 hns3_err(hw, "failed to set mc mac addr, "
1898 "addrs invalid. two same addrs(%s).",
1905 * Check if there are duplicate addresses between mac_addrs
1908 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1909 if (rte_is_same_ether_addr(addr,
1910 &hw->data->mac_addrs[j])) {
1911 rte_ether_format_addr(mac_str,
1912 RTE_ETHER_ADDR_FMT_SIZE,
1914 hns3_err(hw, "failed to set mc mac addr, "
1915 "addrs invalid. addrs(%s) has already "
1916 "configured in mac_addr add API",
1927 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1928 struct rte_ether_addr *mc_addr_set,
1930 struct rte_ether_addr *reserved_addr_list,
1931 int *reserved_addr_num,
1932 struct rte_ether_addr *add_addr_list,
1934 struct rte_ether_addr *rm_addr_list,
1937 struct rte_ether_addr *addr;
1938 int current_addr_num;
1939 int reserved_num = 0;
1947 /* Calculate the mc mac address list that should be removed */
1948 current_addr_num = hw->mc_addrs_num;
1949 for (i = 0; i < current_addr_num; i++) {
1950 addr = &hw->mc_addrs[i];
1952 for (j = 0; j < mc_addr_num; j++) {
1953 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1960 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1963 rte_ether_addr_copy(addr,
1964 &reserved_addr_list[reserved_num]);
1969 /* Calculate the mc mac address list that should be added */
1970 for (i = 0; i < mc_addr_num; i++) {
1971 addr = &mc_addr_set[i];
1973 for (j = 0; j < current_addr_num; j++) {
1974 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1981 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1986 /* Reorder the mc mac address list maintained by driver */
1987 for (i = 0; i < reserved_num; i++)
1988 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1990 for (i = 0; i < rm_num; i++) {
1991 num = reserved_num + i;
1992 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1995 *reserved_addr_num = reserved_num;
1996 *add_addr_num = add_num;
1997 *rm_addr_num = rm_num;
2001 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2002 struct rte_ether_addr *mc_addr_set,
2003 uint32_t nb_mc_addr)
2005 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2007 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2008 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2009 struct rte_ether_addr *addr;
2010 int reserved_addr_num;
2018 /* Check if input parameters are valid */
2019 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2023 rte_spinlock_lock(&hw->lock);
2026 * Calculate the mc mac address lists those should be removed and be
2027 * added, Reorder the mc mac address list maintained by driver.
2029 mc_addr_num = (int)nb_mc_addr;
2030 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2031 reserved_addr_list, &reserved_addr_num,
2032 add_addr_list, &add_addr_num,
2033 rm_addr_list, &rm_addr_num);
2035 /* Remove mc mac addresses */
2036 for (i = 0; i < rm_addr_num; i++) {
2037 num = rm_addr_num - i - 1;
2038 addr = &rm_addr_list[num];
2039 ret = hns3_remove_mc_addr(hw, addr);
2041 rte_spinlock_unlock(&hw->lock);
2047 /* Add mc mac addresses */
2048 for (i = 0; i < add_addr_num; i++) {
2049 addr = &add_addr_list[i];
2050 ret = hns3_add_mc_addr(hw, addr);
2052 rte_spinlock_unlock(&hw->lock);
2056 num = reserved_addr_num + i;
2057 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2060 rte_spinlock_unlock(&hw->lock);
2066 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2068 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2069 struct hns3_hw *hw = &hns->hw;
2070 struct rte_ether_addr *addr;
2075 for (i = 0; i < hw->mc_addrs_num; i++) {
2076 addr = &hw->mc_addrs[i];
2077 if (!rte_is_multicast_ether_addr(addr))
2080 ret = hns3_remove_mc_addr(hw, addr);
2082 ret = hns3_add_mc_addr(hw, addr);
2085 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2087 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2088 del ? "Remove" : "Restore", mac_str, ret);
2095 hns3_check_mq_mode(struct rte_eth_dev *dev)
2097 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2098 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2099 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2102 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2107 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2108 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2110 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2111 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2112 "rx_mq_mode = %d", rx_mq_mode);
2116 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2117 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2118 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2119 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2120 rx_mq_mode, tx_mq_mode);
2124 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2125 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2126 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2127 dcb_rx_conf->nb_tcs, pf->tc_max);
2131 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2132 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2133 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2134 "nb_tcs(%d) != %d or %d in rx direction.",
2135 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2139 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2140 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2141 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2145 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2146 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2147 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2148 "is not equal to one in tx direction.",
2149 i, dcb_rx_conf->dcb_tc[i]);
2152 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2153 max_tc = dcb_rx_conf->dcb_tc[i];
2156 num_tc = max_tc + 1;
2157 if (num_tc > dcb_rx_conf->nb_tcs) {
2158 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2159 num_tc, dcb_rx_conf->nb_tcs);
2168 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2170 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172 if (!hns3_dev_dcb_supported(hw)) {
2173 hns3_err(hw, "this port does not support dcb configurations.");
2177 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2178 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2182 /* Check multiple queue mode */
2183 return hns3_check_mq_mode(dev);
2187 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2188 enum hns3_ring_type queue_type, uint16_t queue_id)
2190 struct hns3_cmd_desc desc;
2191 struct hns3_ctrl_vector_chain_cmd *req =
2192 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2193 enum hns3_cmd_status status;
2194 enum hns3_opcode_type op;
2195 uint16_t tqp_type_and_id = 0;
2200 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2201 hns3_cmd_setup_basic_desc(&desc, op, false);
2202 req->int_vector_id = vector_id;
2204 if (queue_type == HNS3_RING_TYPE_RX)
2205 gl = HNS3_RING_GL_RX;
2207 gl = HNS3_RING_GL_TX;
2211 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2213 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2214 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2216 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2217 req->int_cause_num = 1;
2218 op_str = mmap ? "Map" : "Unmap";
2219 status = hns3_cmd_send(hw, &desc, 1);
2221 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2222 op_str, queue_id, req->int_vector_id, status);
2230 hns3_init_ring_with_vector(struct hns3_hw *hw)
2237 * In hns3 network engine, vector 0 is always the misc interrupt of this
2238 * function, vector 1~N can be used respectively for the queues of the
2239 * function. Tx and Rx queues with the same number share the interrupt
2240 * vector. In the initialization clearing the all hardware mapping
2241 * relationship configurations between queues and interrupt vectors is
2242 * needed, so some error caused by the residual configurations, such as
2243 * the unexpected Tx interrupt, can be avoid.
2245 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2246 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2247 vec = vec - 1; /* the last interrupt is reserved */
2248 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2249 for (i = 0; i < hw->intr_tqps_num; i++) {
2251 * Set gap limiter/rate limiter/quanity limiter algorithm
2252 * configuration for interrupt coalesce of queue's interrupt.
2254 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2255 HNS3_TQP_INTR_GL_DEFAULT);
2256 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2257 HNS3_TQP_INTR_GL_DEFAULT);
2258 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2259 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2261 ret = hns3_bind_ring_with_vector(hw, vec, false,
2262 HNS3_RING_TYPE_TX, i);
2264 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2265 "vector: %d, ret=%d", i, vec, ret);
2269 ret = hns3_bind_ring_with_vector(hw, vec, false,
2270 HNS3_RING_TYPE_RX, i);
2272 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2273 "vector: %d, ret=%d", i, vec, ret);
2282 hns3_dev_configure(struct rte_eth_dev *dev)
2284 struct hns3_adapter *hns = dev->data->dev_private;
2285 struct rte_eth_conf *conf = &dev->data->dev_conf;
2286 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2287 struct hns3_hw *hw = &hns->hw;
2288 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2289 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2290 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2291 struct rte_eth_rss_conf rss_conf;
2297 * Hardware does not support individually enable/disable/reset the Tx or
2298 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2299 * and Rx queues at the same time. When the numbers of Tx queues
2300 * allocated by upper applications are not equal to the numbers of Rx
2301 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2302 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2303 * these fake queues are imperceptible, and can not be used by upper
2306 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2308 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2312 hw->adapter_state = HNS3_NIC_CONFIGURING;
2313 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2314 hns3_err(hw, "setting link speed/duplex not supported");
2319 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2320 ret = hns3_check_dcb_cfg(dev);
2325 /* When RSS is not configured, redirect the packet queue 0 */
2326 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2327 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2328 rss_conf = conf->rx_adv_conf.rss_conf;
2329 hw->rss_dis_flag = false;
2330 if (rss_conf.rss_key == NULL) {
2331 rss_conf.rss_key = rss_cfg->key;
2332 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2335 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2341 * If jumbo frames are enabled, MTU needs to be refreshed
2342 * according to the maximum RX packet length.
2344 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2346 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2347 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2348 * can safely assign to "uint16_t" type variable.
2350 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2351 ret = hns3_dev_mtu_set(dev, mtu);
2354 dev->data->mtu = mtu;
2357 ret = hns3_dev_configure_vlan(dev);
2361 /* config hardware GRO */
2362 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2363 ret = hns3_config_gro(hw, gro_en);
2367 hns->rx_simple_allowed = true;
2368 hns->rx_vec_allowed = true;
2369 hns->tx_simple_allowed = true;
2370 hns->tx_vec_allowed = true;
2372 hns3_init_rx_ptype_tble(dev);
2373 hw->adapter_state = HNS3_NIC_CONFIGURED;
2378 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2379 hw->adapter_state = HNS3_NIC_INITIALIZED;
2385 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2387 struct hns3_config_max_frm_size_cmd *req;
2388 struct hns3_cmd_desc desc;
2390 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2392 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2393 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2394 req->min_frm_size = RTE_ETHER_MIN_LEN;
2396 return hns3_cmd_send(hw, &desc, 1);
2400 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2404 ret = hns3_set_mac_mtu(hw, mps);
2406 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2410 ret = hns3_buffer_alloc(hw);
2412 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2418 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2420 struct hns3_adapter *hns = dev->data->dev_private;
2421 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2422 struct hns3_hw *hw = &hns->hw;
2423 bool is_jumbo_frame;
2426 if (dev->data->dev_started) {
2427 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2428 "before configuration", dev->data->port_id);
2432 rte_spinlock_lock(&hw->lock);
2433 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2434 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2437 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2438 * assign to "uint16_t" type variable.
2440 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2442 rte_spinlock_unlock(&hw->lock);
2443 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2444 dev->data->port_id, mtu, ret);
2447 hns->pf.mps = (uint16_t)frame_size;
2449 dev->data->dev_conf.rxmode.offloads |=
2450 DEV_RX_OFFLOAD_JUMBO_FRAME;
2452 dev->data->dev_conf.rxmode.offloads &=
2453 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2454 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2455 rte_spinlock_unlock(&hw->lock);
2461 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2463 struct hns3_adapter *hns = eth_dev->data->dev_private;
2464 struct hns3_hw *hw = &hns->hw;
2465 uint16_t queue_num = hw->tqps_num;
2468 * In interrupt mode, 'max_rx_queues' is set based on the number of
2469 * MSI-X interrupt resources of the hardware.
2471 if (hw->data->dev_conf.intr_conf.rxq == 1)
2472 queue_num = hw->intr_tqps_num;
2474 info->max_rx_queues = queue_num;
2475 info->max_tx_queues = hw->tqps_num;
2476 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2477 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2478 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2479 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2480 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2481 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2482 DEV_RX_OFFLOAD_TCP_CKSUM |
2483 DEV_RX_OFFLOAD_UDP_CKSUM |
2484 DEV_RX_OFFLOAD_SCTP_CKSUM |
2485 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2486 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2487 DEV_RX_OFFLOAD_KEEP_CRC |
2488 DEV_RX_OFFLOAD_SCATTER |
2489 DEV_RX_OFFLOAD_VLAN_STRIP |
2490 DEV_RX_OFFLOAD_VLAN_FILTER |
2491 DEV_RX_OFFLOAD_JUMBO_FRAME |
2492 DEV_RX_OFFLOAD_RSS_HASH |
2493 DEV_RX_OFFLOAD_TCP_LRO);
2494 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2495 DEV_TX_OFFLOAD_IPV4_CKSUM |
2496 DEV_TX_OFFLOAD_TCP_CKSUM |
2497 DEV_TX_OFFLOAD_UDP_CKSUM |
2498 DEV_TX_OFFLOAD_SCTP_CKSUM |
2499 DEV_TX_OFFLOAD_MULTI_SEGS |
2500 DEV_TX_OFFLOAD_TCP_TSO |
2501 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2502 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2503 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2504 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2505 hns3_txvlan_cap_get(hw));
2507 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2508 .nb_max = HNS3_MAX_RING_DESC,
2509 .nb_min = HNS3_MIN_RING_DESC,
2510 .nb_align = HNS3_ALIGN_RING_DESC,
2513 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2514 .nb_max = HNS3_MAX_RING_DESC,
2515 .nb_min = HNS3_MIN_RING_DESC,
2516 .nb_align = HNS3_ALIGN_RING_DESC,
2517 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2518 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2521 info->default_rxconf = (struct rte_eth_rxconf) {
2522 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2524 * If there are no available Rx buffer descriptors, incoming
2525 * packets are always dropped by hardware based on hns3 network
2531 info->default_txconf = (struct rte_eth_txconf) {
2532 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2536 info->vmdq_queue_num = 0;
2538 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2539 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2540 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2542 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2543 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2544 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2545 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2546 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2547 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2553 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2556 struct hns3_adapter *hns = eth_dev->data->dev_private;
2557 struct hns3_hw *hw = &hns->hw;
2558 uint32_t version = hw->fw_version;
2561 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2562 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2563 HNS3_FW_VERSION_BYTE3_S),
2564 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2565 HNS3_FW_VERSION_BYTE2_S),
2566 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2567 HNS3_FW_VERSION_BYTE1_S),
2568 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2569 HNS3_FW_VERSION_BYTE0_S));
2570 ret += 1; /* add the size of '\0' */
2571 if (fw_size < (uint32_t)ret)
2578 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2579 __rte_unused int wait_to_complete)
2581 struct hns3_adapter *hns = eth_dev->data->dev_private;
2582 struct hns3_hw *hw = &hns->hw;
2583 struct hns3_mac *mac = &hw->mac;
2584 struct rte_eth_link new_link;
2586 if (!hns3_is_reset_pending(hns)) {
2587 hns3_update_speed_duplex(eth_dev);
2588 hns3_update_link_status(hw);
2591 memset(&new_link, 0, sizeof(new_link));
2592 switch (mac->link_speed) {
2593 case ETH_SPEED_NUM_10M:
2594 case ETH_SPEED_NUM_100M:
2595 case ETH_SPEED_NUM_1G:
2596 case ETH_SPEED_NUM_10G:
2597 case ETH_SPEED_NUM_25G:
2598 case ETH_SPEED_NUM_40G:
2599 case ETH_SPEED_NUM_50G:
2600 case ETH_SPEED_NUM_100G:
2601 case ETH_SPEED_NUM_200G:
2602 new_link.link_speed = mac->link_speed;
2605 new_link.link_speed = ETH_SPEED_NUM_100M;
2609 new_link.link_duplex = mac->link_duplex;
2610 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2611 new_link.link_autoneg =
2612 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2614 return rte_eth_linkstatus_set(eth_dev, &new_link);
2618 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2620 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2621 struct hns3_pf *pf = &hns->pf;
2623 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2626 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2632 hns3_query_function_status(struct hns3_hw *hw)
2634 #define HNS3_QUERY_MAX_CNT 10
2635 #define HNS3_QUERY_SLEEP_MSCOEND 1
2636 struct hns3_func_status_cmd *req;
2637 struct hns3_cmd_desc desc;
2641 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2642 req = (struct hns3_func_status_cmd *)desc.data;
2645 ret = hns3_cmd_send(hw, &desc, 1);
2647 PMD_INIT_LOG(ERR, "query function status failed %d",
2652 /* Check pf reset is done */
2656 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2657 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2659 return hns3_parse_func_status(hw, req);
2663 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2665 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2666 struct hns3_pf *pf = &hns->pf;
2668 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2670 * The total_tqps_num obtained from firmware is maximum tqp
2671 * numbers of this port, which should be used for PF and VFs.
2672 * There is no need for pf to have so many tqp numbers in
2673 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2674 * coming from config file, is assigned to maximum queue number
2675 * for the PF of this port by user. So users can modify the
2676 * maximum queue number of PF according to their own application
2677 * scenarios, which is more flexible to use. In addition, many
2678 * memories can be saved due to allocating queue statistics
2679 * room according to the actual number of queues required. The
2680 * maximum queue number of PF for network engine with
2681 * revision_id greater than 0x30 is assigned by config file.
2683 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2684 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2685 "must be greater than 0.",
2686 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2690 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2691 hw->total_tqps_num);
2694 * Due to the limitation on the number of PF interrupts
2695 * available, the maximum queue number assigned to PF on
2696 * the network engine with revision_id 0x21 is 64.
2698 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2699 HNS3_MAX_TQP_NUM_HIP08_PF);
2706 hns3_query_pf_resource(struct hns3_hw *hw)
2708 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2709 struct hns3_pf *pf = &hns->pf;
2710 struct hns3_pf_res_cmd *req;
2711 struct hns3_cmd_desc desc;
2714 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2715 ret = hns3_cmd_send(hw, &desc, 1);
2717 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2721 req = (struct hns3_pf_res_cmd *)desc.data;
2722 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2723 rte_le_to_cpu_16(req->ext_tqp_num);
2724 ret = hns3_get_pf_max_tqp_num(hw);
2728 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2729 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2731 if (req->tx_buf_size)
2733 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2735 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2737 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2739 if (req->dv_buf_size)
2741 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2743 pf->dv_buf_size = HNS3_DEFAULT_DV;
2745 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2748 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2749 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2755 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2757 struct hns3_cfg_param_cmd *req;
2758 uint64_t mac_addr_tmp_high;
2759 uint8_t ext_rss_size_max;
2760 uint64_t mac_addr_tmp;
2763 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2765 /* get the configuration */
2766 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2767 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2768 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2769 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2770 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2771 HNS3_CFG_TQP_DESC_N_M,
2772 HNS3_CFG_TQP_DESC_N_S);
2774 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2775 HNS3_CFG_PHY_ADDR_M,
2776 HNS3_CFG_PHY_ADDR_S);
2777 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2778 HNS3_CFG_MEDIA_TP_M,
2779 HNS3_CFG_MEDIA_TP_S);
2780 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2781 HNS3_CFG_RX_BUF_LEN_M,
2782 HNS3_CFG_RX_BUF_LEN_S);
2783 /* get mac address */
2784 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2785 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2786 HNS3_CFG_MAC_ADDR_H_M,
2787 HNS3_CFG_MAC_ADDR_H_S);
2789 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2791 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2792 HNS3_CFG_DEFAULT_SPEED_M,
2793 HNS3_CFG_DEFAULT_SPEED_S);
2794 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2795 HNS3_CFG_RSS_SIZE_M,
2796 HNS3_CFG_RSS_SIZE_S);
2798 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2799 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2801 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2802 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2804 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2805 HNS3_CFG_SPEED_ABILITY_M,
2806 HNS3_CFG_SPEED_ABILITY_S);
2807 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2808 HNS3_CFG_UMV_TBL_SPACE_M,
2809 HNS3_CFG_UMV_TBL_SPACE_S);
2810 if (!cfg->umv_space)
2811 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2813 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2814 HNS3_CFG_EXT_RSS_SIZE_M,
2815 HNS3_CFG_EXT_RSS_SIZE_S);
2818 * Field ext_rss_size_max obtained from firmware will be more flexible
2819 * for future changes and expansions, which is an exponent of 2, instead
2820 * of reading out directly. If this field is not zero, hns3 PF PMD
2821 * driver uses it as rss_size_max under one TC. Device, whose revision
2822 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2823 * maximum number of queues supported under a TC through this field.
2825 if (ext_rss_size_max)
2826 cfg->rss_size_max = 1U << ext_rss_size_max;
2829 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2830 * @hw: pointer to struct hns3_hw
2831 * @hcfg: the config structure to be getted
2834 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2836 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2837 struct hns3_cfg_param_cmd *req;
2842 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2844 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2845 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2847 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2848 i * HNS3_CFG_RD_LEN_BYTES);
2849 /* Len should be divided by 4 when send to hardware */
2850 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2851 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2852 req->offset = rte_cpu_to_le_32(offset);
2855 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2857 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2861 hns3_parse_cfg(hcfg, desc);
2867 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2869 switch (speed_cmd) {
2870 case HNS3_CFG_SPEED_10M:
2871 *speed = ETH_SPEED_NUM_10M;
2873 case HNS3_CFG_SPEED_100M:
2874 *speed = ETH_SPEED_NUM_100M;
2876 case HNS3_CFG_SPEED_1G:
2877 *speed = ETH_SPEED_NUM_1G;
2879 case HNS3_CFG_SPEED_10G:
2880 *speed = ETH_SPEED_NUM_10G;
2882 case HNS3_CFG_SPEED_25G:
2883 *speed = ETH_SPEED_NUM_25G;
2885 case HNS3_CFG_SPEED_40G:
2886 *speed = ETH_SPEED_NUM_40G;
2888 case HNS3_CFG_SPEED_50G:
2889 *speed = ETH_SPEED_NUM_50G;
2891 case HNS3_CFG_SPEED_100G:
2892 *speed = ETH_SPEED_NUM_100G;
2894 case HNS3_CFG_SPEED_200G:
2895 *speed = ETH_SPEED_NUM_200G;
2905 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2907 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2908 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2909 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2910 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2914 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2916 struct hns3_dev_specs_0_cmd *req0;
2918 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2920 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2921 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2922 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2923 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2927 hns3_query_dev_specifications(struct hns3_hw *hw)
2929 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2933 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2934 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2936 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2938 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2940 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2944 hns3_parse_dev_specifications(hw, desc);
2950 hns3_get_capability(struct hns3_hw *hw)
2952 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2953 struct rte_pci_device *pci_dev;
2954 struct hns3_pf *pf = &hns->pf;
2955 struct rte_eth_dev *eth_dev;
2960 eth_dev = &rte_eth_devices[hw->data->port_id];
2961 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2962 device_id = pci_dev->id.device_id;
2964 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2965 device_id == HNS3_DEV_ID_50GE_RDMA ||
2966 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2967 device_id == HNS3_DEV_ID_200G_RDMA)
2968 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2970 /* Get PCI revision id */
2971 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2972 HNS3_PCI_REVISION_ID);
2973 if (ret != HNS3_PCI_REVISION_ID_LEN) {
2974 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2978 hw->revision = revision;
2980 if (revision < PCI_REVISION_ID_HIP09_A) {
2981 hns3_set_default_dev_specifications(hw);
2982 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2983 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2984 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2985 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2986 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2987 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2988 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2992 ret = hns3_query_dev_specifications(hw);
2995 "failed to query dev specifications, ret = %d",
3000 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3001 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
3002 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3003 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3004 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3005 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3006 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3012 hns3_get_board_configuration(struct hns3_hw *hw)
3014 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3015 struct hns3_pf *pf = &hns->pf;
3016 struct hns3_cfg cfg;
3019 ret = hns3_get_board_cfg(hw, &cfg);
3021 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3025 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3026 !hns3_dev_copper_supported(hw)) {
3027 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3031 hw->mac.media_type = cfg.media_type;
3032 hw->rss_size_max = cfg.rss_size_max;
3033 hw->rss_dis_flag = false;
3034 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3035 hw->mac.phy_addr = cfg.phy_addr;
3036 hw->mac.default_addr_setted = false;
3037 hw->num_tx_desc = cfg.tqp_desc_num;
3038 hw->num_rx_desc = cfg.tqp_desc_num;
3039 hw->dcb_info.num_pg = 1;
3040 hw->dcb_info.hw_pfc_map = 0;
3042 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3044 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
3045 cfg.default_speed, ret);
3049 pf->tc_max = cfg.tc_num;
3050 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3051 PMD_INIT_LOG(WARNING,
3052 "Get TC num(%u) from flash, set TC num to 1",
3057 /* Dev does not support DCB */
3058 if (!hns3_dev_dcb_supported(hw)) {
3062 pf->pfc_max = pf->tc_max;
3064 hw->dcb_info.num_tc = 1;
3065 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3066 hw->tqps_num / hw->dcb_info.num_tc);
3067 hns3_set_bit(hw->hw_tc_map, 0, 1);
3068 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3070 pf->wanted_umv_size = cfg.umv_space;
3076 hns3_get_configuration(struct hns3_hw *hw)
3080 ret = hns3_query_function_status(hw);
3082 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3086 /* Get device capability */
3087 ret = hns3_get_capability(hw);
3089 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3093 /* Get pf resource */
3094 ret = hns3_query_pf_resource(hw);
3096 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3100 ret = hns3_get_board_configuration(hw);
3102 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3108 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3109 uint16_t tqp_vid, bool is_pf)
3111 struct hns3_tqp_map_cmd *req;
3112 struct hns3_cmd_desc desc;
3115 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3117 req = (struct hns3_tqp_map_cmd *)desc.data;
3118 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3119 req->tqp_vf = func_id;
3120 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3122 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3123 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3125 ret = hns3_cmd_send(hw, &desc, 1);
3127 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3133 hns3_map_tqp(struct hns3_hw *hw)
3139 * In current version, VF is not supported when PF is driven by DPDK
3140 * driver, so we assign total tqps_num tqps allocated to this port
3143 for (i = 0; i < hw->total_tqps_num; i++) {
3144 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3153 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3155 struct hns3_config_mac_speed_dup_cmd *req;
3156 struct hns3_cmd_desc desc;
3159 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3161 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3163 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3166 case ETH_SPEED_NUM_10M:
3167 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3168 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3170 case ETH_SPEED_NUM_100M:
3171 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3172 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3174 case ETH_SPEED_NUM_1G:
3175 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3176 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3178 case ETH_SPEED_NUM_10G:
3179 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3180 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3182 case ETH_SPEED_NUM_25G:
3183 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3184 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3186 case ETH_SPEED_NUM_40G:
3187 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3188 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3190 case ETH_SPEED_NUM_50G:
3191 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3192 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3194 case ETH_SPEED_NUM_100G:
3195 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3196 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3198 case ETH_SPEED_NUM_200G:
3199 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3200 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3203 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3207 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3209 ret = hns3_cmd_send(hw, &desc, 1);
3211 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3217 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3219 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3220 struct hns3_pf *pf = &hns->pf;
3221 struct hns3_priv_buf *priv;
3222 uint32_t i, total_size;
3224 total_size = pf->pkt_buf_size;
3226 /* alloc tx buffer for all enabled tc */
3227 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3228 priv = &buf_alloc->priv_buf[i];
3230 if (hw->hw_tc_map & BIT(i)) {
3231 if (total_size < pf->tx_buf_size)
3234 priv->tx_buf_size = pf->tx_buf_size;
3236 priv->tx_buf_size = 0;
3238 total_size -= priv->tx_buf_size;
3245 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3247 /* TX buffer size is unit by 128 byte */
3248 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3249 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3250 struct hns3_tx_buff_alloc_cmd *req;
3251 struct hns3_cmd_desc desc;
3256 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3258 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3259 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3260 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3262 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3263 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3264 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3267 ret = hns3_cmd_send(hw, &desc, 1);
3269 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3275 hns3_get_tc_num(struct hns3_hw *hw)
3280 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3281 if (hw->hw_tc_map & BIT(i))
3287 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3289 struct hns3_priv_buf *priv;
3290 uint32_t rx_priv = 0;
3293 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3294 priv = &buf_alloc->priv_buf[i];
3296 rx_priv += priv->buf_size;
3302 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3304 uint32_t total_tx_size = 0;
3307 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3308 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3310 return total_tx_size;
3313 /* Get the number of pfc enabled TCs, which have private buffer */
3315 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3317 struct hns3_priv_buf *priv;
3321 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3322 priv = &buf_alloc->priv_buf[i];
3323 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3330 /* Get the number of pfc disabled TCs, which have private buffer */
3332 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3333 struct hns3_pkt_buf_alloc *buf_alloc)
3335 struct hns3_priv_buf *priv;
3339 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3340 priv = &buf_alloc->priv_buf[i];
3341 if (hw->hw_tc_map & BIT(i) &&
3342 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3350 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3353 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3354 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3355 struct hns3_pf *pf = &hns->pf;
3356 uint32_t shared_buf, aligned_mps;
3361 tc_num = hns3_get_tc_num(hw);
3362 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3364 if (hns3_dev_dcb_supported(hw))
3365 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3368 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3371 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3372 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3373 HNS3_BUF_SIZE_UNIT);
3375 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3376 if (rx_all < rx_priv + shared_std)
3379 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3380 buf_alloc->s_buf.buf_size = shared_buf;
3381 if (hns3_dev_dcb_supported(hw)) {
3382 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3383 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3384 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3385 HNS3_BUF_SIZE_UNIT);
3387 buf_alloc->s_buf.self.high =
3388 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3389 buf_alloc->s_buf.self.low = aligned_mps;
3392 if (hns3_dev_dcb_supported(hw)) {
3393 hi_thrd = shared_buf - pf->dv_buf_size;
3395 if (tc_num <= NEED_RESERVE_TC_NUM)
3396 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3400 hi_thrd = hi_thrd / tc_num;
3402 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3403 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3404 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3406 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3407 lo_thrd = aligned_mps;
3410 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3411 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3412 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3419 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3420 struct hns3_pkt_buf_alloc *buf_alloc)
3422 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3423 struct hns3_pf *pf = &hns->pf;
3424 struct hns3_priv_buf *priv;
3425 uint32_t aligned_mps;
3429 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3430 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3432 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3433 priv = &buf_alloc->priv_buf[i];
3440 if (!(hw->hw_tc_map & BIT(i)))
3444 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3445 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3446 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3447 HNS3_BUF_SIZE_UNIT);
3450 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3454 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3457 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3461 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3462 struct hns3_pkt_buf_alloc *buf_alloc)
3464 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3465 struct hns3_pf *pf = &hns->pf;
3466 struct hns3_priv_buf *priv;
3467 int no_pfc_priv_num;
3472 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3473 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3475 /* let the last to be cleared first */
3476 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3477 priv = &buf_alloc->priv_buf[i];
3478 mask = BIT((uint8_t)i);
3480 if (hw->hw_tc_map & mask &&
3481 !(hw->dcb_info.hw_pfc_map & mask)) {
3482 /* Clear the no pfc TC private buffer */
3490 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3491 no_pfc_priv_num == 0)
3495 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3499 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3500 struct hns3_pkt_buf_alloc *buf_alloc)
3502 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3503 struct hns3_pf *pf = &hns->pf;
3504 struct hns3_priv_buf *priv;
3510 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3511 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3513 /* let the last to be cleared first */
3514 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3515 priv = &buf_alloc->priv_buf[i];
3516 mask = BIT((uint8_t)i);
3518 if (hw->hw_tc_map & mask &&
3519 hw->dcb_info.hw_pfc_map & mask) {
3520 /* Reduce the number of pfc TC with private buffer */
3527 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3532 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3536 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3537 struct hns3_pkt_buf_alloc *buf_alloc)
3539 #define COMPENSATE_BUFFER 0x3C00
3540 #define COMPENSATE_HALF_MPS_NUM 5
3541 #define PRIV_WL_GAP 0x1800
3542 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3543 struct hns3_pf *pf = &hns->pf;
3544 uint32_t tc_num = hns3_get_tc_num(hw);
3545 uint32_t half_mps = pf->mps >> 1;
3546 struct hns3_priv_buf *priv;
3547 uint32_t min_rx_priv;
3551 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3553 rx_priv = rx_priv / tc_num;
3555 if (tc_num <= NEED_RESERVE_TC_NUM)
3556 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3559 * Minimum value of private buffer in rx direction (min_rx_priv) is
3560 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3561 * buffer if rx_priv is greater than min_rx_priv.
3563 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3564 COMPENSATE_HALF_MPS_NUM * half_mps;
3565 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3566 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3568 if (rx_priv < min_rx_priv)
3571 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3572 priv = &buf_alloc->priv_buf[i];
3579 if (!(hw->hw_tc_map & BIT(i)))
3583 priv->buf_size = rx_priv;
3584 priv->wl.high = rx_priv - pf->dv_buf_size;
3585 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3588 buf_alloc->s_buf.buf_size = 0;
3594 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3595 * @hw: pointer to struct hns3_hw
3596 * @buf_alloc: pointer to buffer calculation data
3597 * @return: 0: calculate sucessful, negative: fail
3600 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3602 /* When DCB is not supported, rx private buffer is not allocated. */
3603 if (!hns3_dev_dcb_supported(hw)) {
3604 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3605 struct hns3_pf *pf = &hns->pf;
3606 uint32_t rx_all = pf->pkt_buf_size;
3608 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3609 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3616 * Try to allocate privated packet buffer for all TCs without share
3619 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3623 * Try to allocate privated packet buffer for all TCs with share
3626 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3630 * For different application scenes, the enabled port number, TC number
3631 * and no_drop TC number are different. In order to obtain the better
3632 * performance, software could allocate the buffer size and configure
3633 * the waterline by tring to decrease the private buffer size according
3634 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3637 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3640 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3643 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3650 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3652 struct hns3_rx_priv_buff_cmd *req;
3653 struct hns3_cmd_desc desc;
3658 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3659 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3661 /* Alloc private buffer TCs */
3662 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3663 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3666 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3667 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3670 buf_size = buf_alloc->s_buf.buf_size;
3671 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3672 (1 << HNS3_TC0_PRI_BUF_EN_B));
3674 ret = hns3_cmd_send(hw, &desc, 1);
3676 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3682 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3684 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3685 struct hns3_rx_priv_wl_buf *req;
3686 struct hns3_priv_buf *priv;
3687 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3691 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3692 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3694 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3696 /* The first descriptor set the NEXT bit to 1 */
3698 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3700 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3702 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3703 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3705 priv = &buf_alloc->priv_buf[idx];
3706 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3708 req->tc_wl[j].high |=
3709 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3710 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3712 req->tc_wl[j].low |=
3713 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3717 /* Send 2 descriptor at one time */
3718 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3720 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3726 hns3_common_thrd_config(struct hns3_hw *hw,
3727 struct hns3_pkt_buf_alloc *buf_alloc)
3729 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3730 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3731 struct hns3_rx_com_thrd *req;
3732 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3733 struct hns3_tc_thrd *tc;
3738 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3739 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3741 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3743 /* The first descriptor set the NEXT bit to 1 */
3745 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3747 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3749 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3750 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3751 tc = &s_buf->tc_thrd[tc_idx];
3753 req->com_thrd[j].high =
3754 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3755 req->com_thrd[j].high |=
3756 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3757 req->com_thrd[j].low =
3758 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3759 req->com_thrd[j].low |=
3760 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3764 /* Send 2 descriptors at one time */
3765 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3767 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3773 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3775 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3776 struct hns3_rx_com_wl *req;
3777 struct hns3_cmd_desc desc;
3780 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3782 req = (struct hns3_rx_com_wl *)desc.data;
3783 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3784 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3786 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3787 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3789 ret = hns3_cmd_send(hw, &desc, 1);
3791 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3797 hns3_buffer_alloc(struct hns3_hw *hw)
3799 struct hns3_pkt_buf_alloc pkt_buf;
3802 memset(&pkt_buf, 0, sizeof(pkt_buf));
3803 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3806 "could not calc tx buffer size for all TCs %d",
3811 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3813 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3817 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3820 "could not calc rx priv buffer size for all TCs %d",
3825 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3827 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3831 if (hns3_dev_dcb_supported(hw)) {
3832 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3835 "could not configure rx private waterline %d",
3840 ret = hns3_common_thrd_config(hw, &pkt_buf);
3843 "could not configure common threshold %d",
3849 ret = hns3_common_wl_config(hw, &pkt_buf);
3851 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3858 hns3_mac_init(struct hns3_hw *hw)
3860 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3861 struct hns3_mac *mac = &hw->mac;
3862 struct hns3_pf *pf = &hns->pf;
3865 pf->support_sfp_query = true;
3866 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3867 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3869 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3873 mac->link_status = ETH_LINK_DOWN;
3875 return hns3_config_mtu(hw, pf->mps);
3879 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3881 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3882 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3883 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3884 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3889 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3894 switch (resp_code) {
3895 case HNS3_ETHERTYPE_SUCCESS_ADD:
3896 case HNS3_ETHERTYPE_ALREADY_ADD:
3899 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3901 "add mac ethertype failed for manager table overflow.");
3902 return_status = -EIO;
3904 case HNS3_ETHERTYPE_KEY_CONFLICT:
3905 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3906 return_status = -EIO;
3910 "add mac ethertype failed for undefined, code=%d.",
3912 return_status = -EIO;
3916 return return_status;
3920 hns3_add_mgr_tbl(struct hns3_hw *hw,
3921 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3923 struct hns3_cmd_desc desc;
3928 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3929 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3931 ret = hns3_cmd_send(hw, &desc, 1);
3934 "add mac ethertype failed for cmd_send, ret =%d.",
3939 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3940 retval = rte_le_to_cpu_16(desc.retval);
3942 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3946 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3947 int *table_item_num)
3949 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3952 * In current version, we add one item in management table as below:
3953 * 0x0180C200000E -- LLDP MC address
3956 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3957 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3958 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3959 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3960 tbl->i_port_bitmap = 0x1;
3961 *table_item_num = 1;
3965 hns3_init_mgr_tbl(struct hns3_hw *hw)
3967 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3968 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3973 memset(mgr_table, 0, sizeof(mgr_table));
3974 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3975 for (i = 0; i < table_item_num; i++) {
3976 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3978 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3988 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3989 bool en_mc, bool en_bc, int vport_id)
3994 memset(param, 0, sizeof(struct hns3_promisc_param));
3996 param->enable = HNS3_PROMISC_EN_UC;
3998 param->enable |= HNS3_PROMISC_EN_MC;
4000 param->enable |= HNS3_PROMISC_EN_BC;
4001 param->vf_id = vport_id;
4005 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4007 struct hns3_promisc_cfg_cmd *req;
4008 struct hns3_cmd_desc desc;
4011 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4013 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4014 req->vf_id = param->vf_id;
4015 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4016 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4018 ret = hns3_cmd_send(hw, &desc, 1);
4020 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4026 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4028 struct hns3_promisc_param param;
4029 bool en_bc_pmc = true;
4033 * In current version VF is not supported when PF is driven by DPDK
4034 * driver, just need to configure parameters for PF vport.
4036 vf_id = HNS3_PF_FUNC_ID;
4038 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4039 return hns3_cmd_set_promisc_mode(hw, ¶m);
4043 hns3_promisc_init(struct hns3_hw *hw)
4045 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4046 struct hns3_pf *pf = &hns->pf;
4047 struct hns3_promisc_param param;
4051 ret = hns3_set_promisc_mode(hw, false, false);
4053 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4058 * In current version VFs are not supported when PF is driven by DPDK
4059 * driver. After PF has been taken over by DPDK, the original VF will
4060 * be invalid. So, there is a possibility of entry residues. It should
4061 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4064 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4065 hns3_promisc_param_init(¶m, false, false, false, func_id);
4066 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4068 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4069 " ret = %d", func_id, ret);
4078 hns3_promisc_uninit(struct hns3_hw *hw)
4080 struct hns3_promisc_param param;
4084 func_id = HNS3_PF_FUNC_ID;
4087 * In current version VFs are not supported when PF is driven by
4088 * DPDK driver, and VFs' promisc mode status has been cleared during
4089 * init and their status will not change. So just clear PF's promisc
4090 * mode status during uninit.
4092 hns3_promisc_param_init(¶m, false, false, false, func_id);
4093 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4095 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4096 " uninit, ret = %d", ret);
4100 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4102 bool allmulti = dev->data->all_multicast ? true : false;
4103 struct hns3_adapter *hns = dev->data->dev_private;
4104 struct hns3_hw *hw = &hns->hw;
4109 rte_spinlock_lock(&hw->lock);
4110 ret = hns3_set_promisc_mode(hw, true, true);
4112 rte_spinlock_unlock(&hw->lock);
4113 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4119 * When promiscuous mode was enabled, disable the vlan filter to let
4120 * all packets coming in in the receiving direction.
4122 offloads = dev->data->dev_conf.rxmode.offloads;
4123 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4124 ret = hns3_enable_vlan_filter(hns, false);
4126 hns3_err(hw, "failed to enable promiscuous mode due to "
4127 "failure to disable vlan filter, ret = %d",
4129 err = hns3_set_promisc_mode(hw, false, allmulti);
4131 hns3_err(hw, "failed to restore promiscuous "
4132 "status after disable vlan filter "
4133 "failed during enabling promiscuous "
4134 "mode, ret = %d", ret);
4138 rte_spinlock_unlock(&hw->lock);
4144 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4146 bool allmulti = dev->data->all_multicast ? true : false;
4147 struct hns3_adapter *hns = dev->data->dev_private;
4148 struct hns3_hw *hw = &hns->hw;
4153 /* If now in all_multicast mode, must remain in all_multicast mode. */
4154 rte_spinlock_lock(&hw->lock);
4155 ret = hns3_set_promisc_mode(hw, false, allmulti);
4157 rte_spinlock_unlock(&hw->lock);
4158 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4162 /* when promiscuous mode was disabled, restore the vlan filter status */
4163 offloads = dev->data->dev_conf.rxmode.offloads;
4164 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4165 ret = hns3_enable_vlan_filter(hns, true);
4167 hns3_err(hw, "failed to disable promiscuous mode due to"
4168 " failure to restore vlan filter, ret = %d",
4170 err = hns3_set_promisc_mode(hw, true, true);
4172 hns3_err(hw, "failed to restore promiscuous "
4173 "status after enabling vlan filter "
4174 "failed during disabling promiscuous "
4175 "mode, ret = %d", ret);
4178 rte_spinlock_unlock(&hw->lock);
4184 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4186 struct hns3_adapter *hns = dev->data->dev_private;
4187 struct hns3_hw *hw = &hns->hw;
4190 if (dev->data->promiscuous)
4193 rte_spinlock_lock(&hw->lock);
4194 ret = hns3_set_promisc_mode(hw, false, true);
4195 rte_spinlock_unlock(&hw->lock);
4197 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4204 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4206 struct hns3_adapter *hns = dev->data->dev_private;
4207 struct hns3_hw *hw = &hns->hw;
4210 /* If now in promiscuous mode, must remain in all_multicast mode. */
4211 if (dev->data->promiscuous)
4214 rte_spinlock_lock(&hw->lock);
4215 ret = hns3_set_promisc_mode(hw, false, false);
4216 rte_spinlock_unlock(&hw->lock);
4218 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4225 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4227 struct hns3_hw *hw = &hns->hw;
4228 bool allmulti = hw->data->all_multicast ? true : false;
4231 if (hw->data->promiscuous) {
4232 ret = hns3_set_promisc_mode(hw, true, true);
4234 hns3_err(hw, "failed to restore promiscuous mode, "
4239 ret = hns3_set_promisc_mode(hw, false, allmulti);
4241 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4247 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4249 struct hns3_sfp_speed_cmd *resp;
4250 struct hns3_cmd_desc desc;
4253 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4254 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4255 ret = hns3_cmd_send(hw, &desc, 1);
4256 if (ret == -EOPNOTSUPP) {
4257 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4260 hns3_err(hw, "get sfp speed failed %d", ret);
4264 *speed = resp->sfp_speed;
4270 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4272 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4273 duplex = ETH_LINK_FULL_DUPLEX;
4279 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4281 struct hns3_mac *mac = &hw->mac;
4284 duplex = hns3_check_speed_dup(duplex, speed);
4285 if (mac->link_speed == speed && mac->link_duplex == duplex)
4288 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4292 mac->link_speed = speed;
4293 mac->link_duplex = duplex;
4299 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4301 struct hns3_adapter *hns = eth_dev->data->dev_private;
4302 struct hns3_hw *hw = &hns->hw;
4303 struct hns3_pf *pf = &hns->pf;
4307 /* If IMP do not support get SFP/qSFP speed, return directly */
4308 if (!pf->support_sfp_query)
4311 ret = hns3_get_sfp_speed(hw, &speed);
4312 if (ret == -EOPNOTSUPP) {
4313 pf->support_sfp_query = false;
4318 if (speed == ETH_SPEED_NUM_NONE)
4319 return 0; /* do nothing if no SFP */
4321 /* Config full duplex for SFP */
4322 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4326 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4328 struct hns3_config_mac_mode_cmd *req;
4329 struct hns3_cmd_desc desc;
4330 uint32_t loop_en = 0;
4334 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4336 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4339 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4340 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4341 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4342 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4343 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4344 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4345 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4346 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4347 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4348 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4351 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4352 * when receiving frames. Otherwise, CRC will be stripped.
4354 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4355 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4357 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4358 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4359 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4360 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4361 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4363 ret = hns3_cmd_send(hw, &desc, 1);
4365 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4371 hns3_get_mac_link_status(struct hns3_hw *hw)
4373 struct hns3_link_status_cmd *req;
4374 struct hns3_cmd_desc desc;
4378 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4379 ret = hns3_cmd_send(hw, &desc, 1);
4381 hns3_err(hw, "get link status cmd failed %d", ret);
4382 return ETH_LINK_DOWN;
4385 req = (struct hns3_link_status_cmd *)desc.data;
4386 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4388 return !!link_status;
4392 hns3_update_link_status(struct hns3_hw *hw)
4396 state = hns3_get_mac_link_status(hw);
4397 if (state != hw->mac.link_status) {
4398 hw->mac.link_status = state;
4399 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4404 hns3_service_handler(void *param)
4406 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4407 struct hns3_adapter *hns = eth_dev->data->dev_private;
4408 struct hns3_hw *hw = &hns->hw;
4410 if (!hns3_is_reset_pending(hns)) {
4411 hns3_update_speed_duplex(eth_dev);
4412 hns3_update_link_status(hw);
4414 hns3_warn(hw, "Cancel the query when reset is pending");
4416 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4420 hns3_init_hardware(struct hns3_adapter *hns)
4422 struct hns3_hw *hw = &hns->hw;
4425 ret = hns3_map_tqp(hw);
4427 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4431 ret = hns3_init_umv_space(hw);
4433 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4437 ret = hns3_mac_init(hw);
4439 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4443 ret = hns3_init_mgr_tbl(hw);
4445 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4449 ret = hns3_promisc_init(hw);
4451 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4456 ret = hns3_init_vlan_config(hns);
4458 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4462 ret = hns3_dcb_init(hw);
4464 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4468 ret = hns3_init_fd_config(hns);
4470 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4474 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4476 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4480 ret = hns3_config_gro(hw, false);
4482 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4487 * In the initialization clearing the all hardware mapping relationship
4488 * configurations between queues and interrupt vectors is needed, so
4489 * some error caused by the residual configurations, such as the
4490 * unexpected interrupt, can be avoid.
4492 ret = hns3_init_ring_with_vector(hw);
4494 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4501 hns3_uninit_umv_space(hw);
4506 hns3_clear_hw(struct hns3_hw *hw)
4508 struct hns3_cmd_desc desc;
4511 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4513 ret = hns3_cmd_send(hw, &desc, 1);
4514 if (ret && ret != -EOPNOTSUPP)
4521 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4526 * The new firmware support report more hardware error types by
4527 * msix mode. These errors are defined as RAS errors in hardware
4528 * and belong to a different type from the MSI-x errors processed
4529 * by the network driver.
4531 * Network driver should open the new error report on initialition
4533 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4534 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4535 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4539 hns3_init_pf(struct rte_eth_dev *eth_dev)
4541 struct rte_device *dev = eth_dev->device;
4542 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4543 struct hns3_adapter *hns = eth_dev->data->dev_private;
4544 struct hns3_hw *hw = &hns->hw;
4547 PMD_INIT_FUNC_TRACE();
4549 /* Get hardware io base address from pcie BAR2 IO space */
4550 hw->io_base = pci_dev->mem_resource[2].addr;
4552 /* Firmware command queue initialize */
4553 ret = hns3_cmd_init_queue(hw);
4555 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4556 goto err_cmd_init_queue;
4559 hns3_clear_all_event_cause(hw);
4561 /* Firmware command initialize */
4562 ret = hns3_cmd_init(hw);
4564 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4569 * To ensure that the hardware environment is clean during
4570 * initialization, the driver actively clear the hardware environment
4571 * during initialization, including PF and corresponding VFs' vlan, mac,
4572 * flow table configurations, etc.
4574 ret = hns3_clear_hw(hw);
4576 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4580 hns3_config_all_msix_error(hw, true);
4582 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4583 hns3_interrupt_handler,
4586 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4587 goto err_intr_callback_register;
4590 /* Enable interrupt */
4591 rte_intr_enable(&pci_dev->intr_handle);
4592 hns3_pf_enable_irq0(hw);
4594 /* Get configuration */
4595 ret = hns3_get_configuration(hw);
4597 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4598 goto err_get_config;
4601 ret = hns3_tqp_stats_init(hw);
4603 goto err_get_config;
4605 ret = hns3_init_hardware(hns);
4607 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4611 /* Initialize flow director filter list & hash */
4612 ret = hns3_fdir_filter_init(hns);
4614 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4618 hns3_set_default_rss_args(hw);
4620 ret = hns3_enable_hw_error_intr(hns, true);
4622 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4624 goto err_enable_intr;
4630 hns3_fdir_filter_uninit(hns);
4632 hns3_uninit_umv_space(hw);
4634 hns3_tqp_stats_uninit(hw);
4636 hns3_pf_disable_irq0(hw);
4637 rte_intr_disable(&pci_dev->intr_handle);
4638 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4640 err_intr_callback_register:
4642 hns3_cmd_uninit(hw);
4643 hns3_cmd_destroy_queue(hw);
4651 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4653 struct hns3_adapter *hns = eth_dev->data->dev_private;
4654 struct rte_device *dev = eth_dev->device;
4655 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4656 struct hns3_hw *hw = &hns->hw;
4658 PMD_INIT_FUNC_TRACE();
4660 hns3_enable_hw_error_intr(hns, false);
4661 hns3_rss_uninit(hns);
4662 (void)hns3_config_gro(hw, false);
4663 hns3_promisc_uninit(hw);
4664 hns3_fdir_filter_uninit(hns);
4665 hns3_uninit_umv_space(hw);
4666 hns3_tqp_stats_uninit(hw);
4667 hns3_pf_disable_irq0(hw);
4668 rte_intr_disable(&pci_dev->intr_handle);
4669 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4671 hns3_config_all_msix_error(hw, false);
4672 hns3_cmd_uninit(hw);
4673 hns3_cmd_destroy_queue(hw);
4678 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4680 struct hns3_hw *hw = &hns->hw;
4683 ret = hns3_dcb_cfg_update(hns);
4688 ret = hns3_start_queues(hns, reset_queue);
4690 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4695 ret = hns3_cfg_mac_mode(hw, true);
4697 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4698 goto err_config_mac_mode;
4702 err_config_mac_mode:
4703 hns3_stop_queues(hns, true);
4708 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4710 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4711 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4712 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4714 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4715 uint32_t intr_vector;
4719 if (dev->data->dev_conf.intr_conf.rxq == 0)
4722 /* disable uio/vfio intr/eventfd mapping */
4723 rte_intr_disable(intr_handle);
4725 /* check and configure queue intr-vector mapping */
4726 if (rte_intr_cap_multiple(intr_handle) ||
4727 !RTE_ETH_DEV_SRIOV(dev).active) {
4728 intr_vector = hw->used_rx_queues;
4729 /* creates event fd for each intr vector when MSIX is used */
4730 if (rte_intr_efd_enable(intr_handle, intr_vector))
4733 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4734 intr_handle->intr_vec =
4735 rte_zmalloc("intr_vec",
4736 hw->used_rx_queues * sizeof(int), 0);
4737 if (intr_handle->intr_vec == NULL) {
4738 hns3_err(hw, "Failed to allocate %d rx_queues"
4739 " intr_vec", hw->used_rx_queues);
4741 goto alloc_intr_vec_error;
4745 if (rte_intr_allow_others(intr_handle)) {
4746 vec = RTE_INTR_VEC_RXTX_OFFSET;
4747 base = RTE_INTR_VEC_RXTX_OFFSET;
4749 if (rte_intr_dp_is_en(intr_handle)) {
4750 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4751 ret = hns3_bind_ring_with_vector(hw, vec, true,
4755 goto bind_vector_error;
4756 intr_handle->intr_vec[q_id] = vec;
4757 if (vec < base + intr_handle->nb_efd - 1)
4761 rte_intr_enable(intr_handle);
4765 rte_intr_efd_disable(intr_handle);
4766 if (intr_handle->intr_vec) {
4767 free(intr_handle->intr_vec);
4768 intr_handle->intr_vec = NULL;
4771 alloc_intr_vec_error:
4772 rte_intr_efd_disable(intr_handle);
4777 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4779 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4780 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4781 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4785 if (dev->data->dev_conf.intr_conf.rxq == 0)
4788 if (rte_intr_dp_is_en(intr_handle)) {
4789 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4790 ret = hns3_bind_ring_with_vector(hw,
4791 intr_handle->intr_vec[q_id], true,
4792 HNS3_RING_TYPE_RX, q_id);
4802 hns3_restore_filter(struct rte_eth_dev *dev)
4804 hns3_restore_rss_filter(dev);
4808 hns3_dev_start(struct rte_eth_dev *dev)
4810 struct hns3_adapter *hns = dev->data->dev_private;
4811 struct hns3_hw *hw = &hns->hw;
4814 PMD_INIT_FUNC_TRACE();
4815 if (rte_atomic16_read(&hw->reset.resetting))
4818 rte_spinlock_lock(&hw->lock);
4819 hw->adapter_state = HNS3_NIC_STARTING;
4821 ret = hns3_do_start(hns, true);
4823 hw->adapter_state = HNS3_NIC_CONFIGURED;
4824 rte_spinlock_unlock(&hw->lock);
4827 ret = hns3_map_rx_interrupt(dev);
4829 hw->adapter_state = HNS3_NIC_CONFIGURED;
4830 rte_spinlock_unlock(&hw->lock);
4834 hw->adapter_state = HNS3_NIC_STARTED;
4835 rte_spinlock_unlock(&hw->lock);
4837 hns3_rx_scattered_calc(dev);
4838 hns3_set_rxtx_function(dev);
4839 hns3_mp_req_start_rxtx(dev);
4840 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4842 hns3_restore_filter(dev);
4844 /* Enable interrupt of all rx queues before enabling queues */
4845 hns3_dev_all_rx_queue_intr_enable(hw, true);
4847 * When finished the initialization, enable queues to receive/transmit
4850 hns3_enable_all_queues(hw, true);
4852 hns3_info(hw, "hns3 dev start successful!");
4857 hns3_do_stop(struct hns3_adapter *hns)
4859 struct hns3_hw *hw = &hns->hw;
4863 ret = hns3_cfg_mac_mode(hw, false);
4866 hw->mac.link_status = ETH_LINK_DOWN;
4868 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4869 hns3_configure_all_mac_addr(hns, true);
4872 reset_queue = false;
4873 hw->mac.default_addr_setted = false;
4874 return hns3_stop_queues(hns, reset_queue);
4878 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4880 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4881 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4882 struct hns3_adapter *hns = dev->data->dev_private;
4883 struct hns3_hw *hw = &hns->hw;
4884 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4885 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4888 if (dev->data->dev_conf.intr_conf.rxq == 0)
4891 /* unmap the ring with vector */
4892 if (rte_intr_allow_others(intr_handle)) {
4893 vec = RTE_INTR_VEC_RXTX_OFFSET;
4894 base = RTE_INTR_VEC_RXTX_OFFSET;
4896 if (rte_intr_dp_is_en(intr_handle)) {
4897 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4898 (void)hns3_bind_ring_with_vector(hw, vec, false,
4901 if (vec < base + intr_handle->nb_efd - 1)
4905 /* Clean datapath event and queue/vec mapping */
4906 rte_intr_efd_disable(intr_handle);
4907 if (intr_handle->intr_vec) {
4908 rte_free(intr_handle->intr_vec);
4909 intr_handle->intr_vec = NULL;
4914 hns3_dev_stop(struct rte_eth_dev *dev)
4916 struct hns3_adapter *hns = dev->data->dev_private;
4917 struct hns3_hw *hw = &hns->hw;
4919 PMD_INIT_FUNC_TRACE();
4921 hw->adapter_state = HNS3_NIC_STOPPING;
4922 hns3_set_rxtx_function(dev);
4924 /* Disable datapath on secondary process. */
4925 hns3_mp_req_stop_rxtx(dev);
4926 /* Prevent crashes when queues are still in use. */
4927 rte_delay_ms(hw->tqps_num);
4929 rte_spinlock_lock(&hw->lock);
4930 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4932 hns3_unmap_rx_interrupt(dev);
4933 hns3_dev_release_mbufs(hns);
4934 hw->adapter_state = HNS3_NIC_CONFIGURED;
4936 hns3_rx_scattered_reset(dev);
4937 rte_eal_alarm_cancel(hns3_service_handler, dev);
4938 rte_spinlock_unlock(&hw->lock);
4942 hns3_dev_close(struct rte_eth_dev *eth_dev)
4944 struct hns3_adapter *hns = eth_dev->data->dev_private;
4945 struct hns3_hw *hw = &hns->hw;
4947 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4948 rte_free(eth_dev->process_private);
4949 eth_dev->process_private = NULL;
4953 if (hw->adapter_state == HNS3_NIC_STARTED)
4954 hns3_dev_stop(eth_dev);
4956 hw->adapter_state = HNS3_NIC_CLOSING;
4957 hns3_reset_abort(hns);
4958 hw->adapter_state = HNS3_NIC_CLOSED;
4960 hns3_configure_all_mc_mac_addr(hns, true);
4961 hns3_remove_all_vlan_table(hns);
4962 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4963 hns3_uninit_pf(eth_dev);
4964 hns3_free_all_queues(eth_dev);
4965 rte_free(hw->reset.wait_data);
4966 rte_free(eth_dev->process_private);
4967 eth_dev->process_private = NULL;
4968 hns3_mp_uninit_primary();
4969 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4975 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4977 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4980 fc_conf->pause_time = pf->pause_time;
4982 /* return fc current mode */
4983 switch (hw->current_mode) {
4985 fc_conf->mode = RTE_FC_FULL;
4987 case HNS3_FC_TX_PAUSE:
4988 fc_conf->mode = RTE_FC_TX_PAUSE;
4990 case HNS3_FC_RX_PAUSE:
4991 fc_conf->mode = RTE_FC_RX_PAUSE;
4995 fc_conf->mode = RTE_FC_NONE;
5003 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5007 hw->requested_mode = HNS3_FC_NONE;
5009 case RTE_FC_RX_PAUSE:
5010 hw->requested_mode = HNS3_FC_RX_PAUSE;
5012 case RTE_FC_TX_PAUSE:
5013 hw->requested_mode = HNS3_FC_TX_PAUSE;
5016 hw->requested_mode = HNS3_FC_FULL;
5019 hw->requested_mode = HNS3_FC_NONE;
5020 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5021 "configured to RTE_FC_NONE", mode);
5027 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5029 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5033 if (fc_conf->high_water || fc_conf->low_water ||
5034 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5035 hns3_err(hw, "Unsupported flow control settings specified, "
5036 "high_water(%u), low_water(%u), send_xon(%u) and "
5037 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5038 fc_conf->high_water, fc_conf->low_water,
5039 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5042 if (fc_conf->autoneg) {
5043 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5046 if (!fc_conf->pause_time) {
5047 hns3_err(hw, "Invalid pause time %d setting.",
5048 fc_conf->pause_time);
5052 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5053 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5054 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5055 "current_fc_status = %d", hw->current_fc_status);
5059 hns3_get_fc_mode(hw, fc_conf->mode);
5060 if (hw->requested_mode == hw->current_mode &&
5061 pf->pause_time == fc_conf->pause_time)
5064 rte_spinlock_lock(&hw->lock);
5065 ret = hns3_fc_enable(dev, fc_conf);
5066 rte_spinlock_unlock(&hw->lock);
5072 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5073 struct rte_eth_pfc_conf *pfc_conf)
5075 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5080 if (!hns3_dev_dcb_supported(hw)) {
5081 hns3_err(hw, "This port does not support dcb configurations.");
5085 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5086 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5087 hns3_err(hw, "Unsupported flow control settings specified, "
5088 "high_water(%u), low_water(%u), send_xon(%u) and "
5089 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5090 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5091 pfc_conf->fc.send_xon,
5092 pfc_conf->fc.mac_ctrl_frame_fwd);
5095 if (pfc_conf->fc.autoneg) {
5096 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5099 if (pfc_conf->fc.pause_time == 0) {
5100 hns3_err(hw, "Invalid pause time %d setting.",
5101 pfc_conf->fc.pause_time);
5105 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5106 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5107 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5108 "current_fc_status = %d", hw->current_fc_status);
5112 priority = pfc_conf->priority;
5113 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5114 if (hw->dcb_info.pfc_en & BIT(priority) &&
5115 hw->requested_mode == hw->current_mode &&
5116 pfc_conf->fc.pause_time == pf->pause_time)
5119 rte_spinlock_lock(&hw->lock);
5120 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5121 rte_spinlock_unlock(&hw->lock);
5127 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5129 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5131 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5134 rte_spinlock_lock(&hw->lock);
5135 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5136 dcb_info->nb_tcs = pf->local_max_tc;
5138 dcb_info->nb_tcs = 1;
5140 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5141 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5142 for (i = 0; i < dcb_info->nb_tcs; i++)
5143 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5145 for (i = 0; i < hw->num_tc; i++) {
5146 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5147 dcb_info->tc_queue.tc_txq[0][i].base =
5148 hw->tc_queue[i].tqp_offset;
5149 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5150 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5151 hw->tc_queue[i].tqp_count;
5153 rte_spinlock_unlock(&hw->lock);
5159 hns3_reinit_dev(struct hns3_adapter *hns)
5161 struct hns3_hw *hw = &hns->hw;
5164 ret = hns3_cmd_init(hw);
5166 hns3_err(hw, "Failed to init cmd: %d", ret);
5170 ret = hns3_reset_all_queues(hns);
5172 hns3_err(hw, "Failed to reset all queues: %d", ret);
5176 ret = hns3_init_hardware(hns);
5178 hns3_err(hw, "Failed to init hardware: %d", ret);
5182 ret = hns3_enable_hw_error_intr(hns, true);
5184 hns3_err(hw, "fail to enable hw error interrupts: %d",
5188 hns3_info(hw, "Reset done, driver initialization finished.");
5194 is_pf_reset_done(struct hns3_hw *hw)
5196 uint32_t val, reg, reg_bit;
5198 switch (hw->reset.level) {
5199 case HNS3_IMP_RESET:
5200 reg = HNS3_GLOBAL_RESET_REG;
5201 reg_bit = HNS3_IMP_RESET_BIT;
5203 case HNS3_GLOBAL_RESET:
5204 reg = HNS3_GLOBAL_RESET_REG;
5205 reg_bit = HNS3_GLOBAL_RESET_BIT;
5207 case HNS3_FUNC_RESET:
5208 reg = HNS3_FUN_RST_ING;
5209 reg_bit = HNS3_FUN_RST_ING_B;
5211 case HNS3_FLR_RESET:
5213 hns3_err(hw, "Wait for unsupported reset level: %d",
5217 val = hns3_read_dev(hw, reg);
5218 if (hns3_get_bit(val, reg_bit))
5225 hns3_is_reset_pending(struct hns3_adapter *hns)
5227 struct hns3_hw *hw = &hns->hw;
5228 enum hns3_reset_level reset;
5230 hns3_check_event_cause(hns, NULL);
5231 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5232 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5233 hns3_warn(hw, "High level reset %d is pending", reset);
5236 reset = hns3_get_reset_level(hns, &hw->reset.request);
5237 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5238 hns3_warn(hw, "High level reset %d is request", reset);
5245 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5247 struct hns3_hw *hw = &hns->hw;
5248 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5251 if (wait_data->result == HNS3_WAIT_SUCCESS)
5253 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5254 gettimeofday(&tv, NULL);
5255 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5256 tv.tv_sec, tv.tv_usec);
5258 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5261 wait_data->hns = hns;
5262 wait_data->check_completion = is_pf_reset_done;
5263 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5264 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5265 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5266 wait_data->count = HNS3_RESET_WAIT_CNT;
5267 wait_data->result = HNS3_WAIT_REQUEST;
5268 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5273 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5275 struct hns3_cmd_desc desc;
5276 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5278 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5279 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5280 req->fun_reset_vfid = func_id;
5282 return hns3_cmd_send(hw, &desc, 1);
5286 hns3_imp_reset_cmd(struct hns3_hw *hw)
5288 struct hns3_cmd_desc desc;
5290 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5291 desc.data[0] = 0xeedd;
5293 return hns3_cmd_send(hw, &desc, 1);
5297 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5299 struct hns3_hw *hw = &hns->hw;
5303 gettimeofday(&tv, NULL);
5304 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5305 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5306 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5307 tv.tv_sec, tv.tv_usec);
5311 switch (reset_level) {
5312 case HNS3_IMP_RESET:
5313 hns3_imp_reset_cmd(hw);
5314 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5315 tv.tv_sec, tv.tv_usec);
5317 case HNS3_GLOBAL_RESET:
5318 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5319 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5320 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5321 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5322 tv.tv_sec, tv.tv_usec);
5324 case HNS3_FUNC_RESET:
5325 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5326 tv.tv_sec, tv.tv_usec);
5327 /* schedule again to check later */
5328 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5329 hns3_schedule_reset(hns);
5332 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5335 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5338 static enum hns3_reset_level
5339 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5341 struct hns3_hw *hw = &hns->hw;
5342 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5344 /* Return the highest priority reset level amongst all */
5345 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5346 reset_level = HNS3_IMP_RESET;
5347 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5348 reset_level = HNS3_GLOBAL_RESET;
5349 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5350 reset_level = HNS3_FUNC_RESET;
5351 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5352 reset_level = HNS3_FLR_RESET;
5354 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5355 return HNS3_NONE_RESET;
5361 hns3_record_imp_error(struct hns3_adapter *hns)
5363 struct hns3_hw *hw = &hns->hw;
5366 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5367 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5368 hns3_warn(hw, "Detected IMP RD poison!");
5369 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5370 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5371 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5374 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5375 hns3_warn(hw, "Detected IMP CMDQ error!");
5376 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5377 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5378 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5383 hns3_prepare_reset(struct hns3_adapter *hns)
5385 struct hns3_hw *hw = &hns->hw;
5389 switch (hw->reset.level) {
5390 case HNS3_FUNC_RESET:
5391 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5396 * After performaning pf reset, it is not necessary to do the
5397 * mailbox handling or send any command to firmware, because
5398 * any mailbox handling or command to firmware is only valid
5399 * after hns3_cmd_init is called.
5401 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5402 hw->reset.stats.request_cnt++;
5404 case HNS3_IMP_RESET:
5405 hns3_record_imp_error(hns);
5406 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5407 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5408 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5417 hns3_set_rst_done(struct hns3_hw *hw)
5419 struct hns3_pf_rst_done_cmd *req;
5420 struct hns3_cmd_desc desc;
5422 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5423 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5424 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5425 return hns3_cmd_send(hw, &desc, 1);
5429 hns3_stop_service(struct hns3_adapter *hns)
5431 struct hns3_hw *hw = &hns->hw;
5432 struct rte_eth_dev *eth_dev;
5434 eth_dev = &rte_eth_devices[hw->data->port_id];
5435 if (hw->adapter_state == HNS3_NIC_STARTED)
5436 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5437 hw->mac.link_status = ETH_LINK_DOWN;
5439 hns3_set_rxtx_function(eth_dev);
5441 /* Disable datapath on secondary process. */
5442 hns3_mp_req_stop_rxtx(eth_dev);
5443 rte_delay_ms(hw->tqps_num);
5445 rte_spinlock_lock(&hw->lock);
5446 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5447 hw->adapter_state == HNS3_NIC_STOPPING) {
5449 hw->reset.mbuf_deferred_free = true;
5451 hw->reset.mbuf_deferred_free = false;
5454 * It is cumbersome for hardware to pick-and-choose entries for deletion
5455 * from table space. Hence, for function reset software intervention is
5456 * required to delete the entries
5458 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5459 hns3_configure_all_mc_mac_addr(hns, true);
5460 rte_spinlock_unlock(&hw->lock);
5466 hns3_start_service(struct hns3_adapter *hns)
5468 struct hns3_hw *hw = &hns->hw;
5469 struct rte_eth_dev *eth_dev;
5471 if (hw->reset.level == HNS3_IMP_RESET ||
5472 hw->reset.level == HNS3_GLOBAL_RESET)
5473 hns3_set_rst_done(hw);
5474 eth_dev = &rte_eth_devices[hw->data->port_id];
5475 hns3_set_rxtx_function(eth_dev);
5476 hns3_mp_req_start_rxtx(eth_dev);
5477 if (hw->adapter_state == HNS3_NIC_STARTED) {
5478 hns3_service_handler(eth_dev);
5480 /* Enable interrupt of all rx queues before enabling queues */
5481 hns3_dev_all_rx_queue_intr_enable(hw, true);
5483 * When finished the initialization, enable queues to receive
5484 * and transmit packets.
5486 hns3_enable_all_queues(hw, true);
5493 hns3_restore_conf(struct hns3_adapter *hns)
5495 struct hns3_hw *hw = &hns->hw;
5498 ret = hns3_configure_all_mac_addr(hns, false);
5502 ret = hns3_configure_all_mc_mac_addr(hns, false);
5506 ret = hns3_dev_promisc_restore(hns);
5510 ret = hns3_restore_vlan_table(hns);
5514 ret = hns3_restore_vlan_conf(hns);
5518 ret = hns3_restore_all_fdir_filter(hns);
5522 ret = hns3_restore_rx_interrupt(hw);
5526 ret = hns3_restore_gro_conf(hw);
5530 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5531 ret = hns3_do_start(hns, false);
5534 hns3_info(hw, "hns3 dev restart successful!");
5535 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5536 hw->adapter_state = HNS3_NIC_CONFIGURED;
5540 hns3_configure_all_mc_mac_addr(hns, true);
5542 hns3_configure_all_mac_addr(hns, true);
5547 hns3_reset_service(void *param)
5549 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5550 struct hns3_hw *hw = &hns->hw;
5551 enum hns3_reset_level reset_level;
5552 struct timeval tv_delta;
5553 struct timeval tv_start;
5559 * The interrupt is not triggered within the delay time.
5560 * The interrupt may have been lost. It is necessary to handle
5561 * the interrupt to recover from the error.
5563 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5564 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5565 hns3_err(hw, "Handling interrupts in delayed tasks");
5566 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5567 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5568 if (reset_level == HNS3_NONE_RESET) {
5569 hns3_err(hw, "No reset level is set, try IMP reset");
5570 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5573 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5576 * Check if there is any ongoing reset in the hardware. This status can
5577 * be checked from reset_pending. If there is then, we need to wait for
5578 * hardware to complete reset.
5579 * a. If we are able to figure out in reasonable time that hardware
5580 * has fully resetted then, we can proceed with driver, client
5582 * b. else, we can come back later to check this status so re-sched
5585 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5586 if (reset_level != HNS3_NONE_RESET) {
5587 gettimeofday(&tv_start, NULL);
5588 ret = hns3_reset_process(hns, reset_level);
5589 gettimeofday(&tv, NULL);
5590 timersub(&tv, &tv_start, &tv_delta);
5591 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5592 tv_delta.tv_usec / USEC_PER_MSEC;
5593 if (msec > HNS3_RESET_PROCESS_MS)
5594 hns3_err(hw, "%d handle long time delta %" PRIx64
5595 " ms time=%ld.%.6ld",
5596 hw->reset.level, msec,
5597 tv.tv_sec, tv.tv_usec);
5602 /* Check if we got any *new* reset requests to be honored */
5603 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5604 if (reset_level != HNS3_NONE_RESET)
5605 hns3_msix_process(hns, reset_level);
5608 static const struct eth_dev_ops hns3_eth_dev_ops = {
5609 .dev_configure = hns3_dev_configure,
5610 .dev_start = hns3_dev_start,
5611 .dev_stop = hns3_dev_stop,
5612 .dev_close = hns3_dev_close,
5613 .promiscuous_enable = hns3_dev_promiscuous_enable,
5614 .promiscuous_disable = hns3_dev_promiscuous_disable,
5615 .allmulticast_enable = hns3_dev_allmulticast_enable,
5616 .allmulticast_disable = hns3_dev_allmulticast_disable,
5617 .mtu_set = hns3_dev_mtu_set,
5618 .stats_get = hns3_stats_get,
5619 .stats_reset = hns3_stats_reset,
5620 .xstats_get = hns3_dev_xstats_get,
5621 .xstats_get_names = hns3_dev_xstats_get_names,
5622 .xstats_reset = hns3_dev_xstats_reset,
5623 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5624 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5625 .dev_infos_get = hns3_dev_infos_get,
5626 .fw_version_get = hns3_fw_version_get,
5627 .rx_queue_setup = hns3_rx_queue_setup,
5628 .tx_queue_setup = hns3_tx_queue_setup,
5629 .rx_queue_release = hns3_dev_rx_queue_release,
5630 .tx_queue_release = hns3_dev_tx_queue_release,
5631 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5632 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5633 .rxq_info_get = hns3_rxq_info_get,
5634 .txq_info_get = hns3_txq_info_get,
5635 .rx_burst_mode_get = hns3_rx_burst_mode_get,
5636 .tx_burst_mode_get = hns3_tx_burst_mode_get,
5637 .flow_ctrl_get = hns3_flow_ctrl_get,
5638 .flow_ctrl_set = hns3_flow_ctrl_set,
5639 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5640 .mac_addr_add = hns3_add_mac_addr,
5641 .mac_addr_remove = hns3_remove_mac_addr,
5642 .mac_addr_set = hns3_set_default_mac_addr,
5643 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5644 .link_update = hns3_dev_link_update,
5645 .rss_hash_update = hns3_dev_rss_hash_update,
5646 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5647 .reta_update = hns3_dev_rss_reta_update,
5648 .reta_query = hns3_dev_rss_reta_query,
5649 .filter_ctrl = hns3_dev_filter_ctrl,
5650 .vlan_filter_set = hns3_vlan_filter_set,
5651 .vlan_tpid_set = hns3_vlan_tpid_set,
5652 .vlan_offload_set = hns3_vlan_offload_set,
5653 .vlan_pvid_set = hns3_vlan_pvid_set,
5654 .get_reg = hns3_get_regs,
5655 .get_dcb_info = hns3_get_dcb_info,
5656 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5659 static const struct hns3_reset_ops hns3_reset_ops = {
5660 .reset_service = hns3_reset_service,
5661 .stop_service = hns3_stop_service,
5662 .prepare_reset = hns3_prepare_reset,
5663 .wait_hardware_ready = hns3_wait_hardware_ready,
5664 .reinit_dev = hns3_reinit_dev,
5665 .restore_conf = hns3_restore_conf,
5666 .start_service = hns3_start_service,
5670 hns3_dev_init(struct rte_eth_dev *eth_dev)
5672 struct hns3_adapter *hns = eth_dev->data->dev_private;
5673 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
5674 struct rte_ether_addr *eth_addr;
5675 struct hns3_hw *hw = &hns->hw;
5678 PMD_INIT_FUNC_TRACE();
5680 eth_dev->process_private = (struct hns3_process_private *)
5681 rte_zmalloc_socket("hns3_filter_list",
5682 sizeof(struct hns3_process_private),
5683 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5684 if (eth_dev->process_private == NULL) {
5685 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5688 /* initialize flow filter lists */
5689 hns3_filterlist_init(eth_dev);
5691 hns3_set_rxtx_function(eth_dev);
5692 eth_dev->dev_ops = &hns3_eth_dev_ops;
5693 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5694 ret = hns3_mp_init_secondary();
5696 PMD_INIT_LOG(ERR, "Failed to init for secondary "
5697 "process, ret = %d", ret);
5698 goto err_mp_init_secondary;
5701 hw->secondary_cnt++;
5705 ret = hns3_mp_init_primary();
5708 "Failed to init for primary process, ret = %d",
5710 goto err_mp_init_primary;
5713 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5715 hw->data = eth_dev->data;
5718 * Set default max packet size according to the mtu
5719 * default vale in DPDK frame.
5721 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5723 ret = hns3_reset_init(hw);
5725 goto err_init_reset;
5726 hw->reset.ops = &hns3_reset_ops;
5728 ret = hns3_init_pf(eth_dev);
5730 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5734 /* Allocate memory for storing MAC addresses */
5735 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5736 sizeof(struct rte_ether_addr) *
5737 HNS3_UC_MACADDR_NUM, 0);
5738 if (eth_dev->data->mac_addrs == NULL) {
5739 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5740 "to store MAC addresses",
5741 sizeof(struct rte_ether_addr) *
5742 HNS3_UC_MACADDR_NUM);
5744 goto err_rte_zmalloc;
5747 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
5748 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
5749 rte_eth_random_addr(hw->mac.mac_addr);
5750 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
5751 (struct rte_ether_addr *)hw->mac.mac_addr);
5752 hns3_warn(hw, "default mac_addr from firmware is an invalid "
5753 "unicast address, using random MAC address %s",
5756 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5757 ð_dev->data->mac_addrs[0]);
5759 hw->adapter_state = HNS3_NIC_INITIALIZED;
5761 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5762 hns3_err(hw, "Reschedule reset service after dev_init");
5763 hns3_schedule_reset(hns);
5765 /* IMP will wait ready flag before reset */
5766 hns3_notify_reset_ready(hw, false);
5769 hns3_info(hw, "hns3 dev initialization successful!");
5773 hns3_uninit_pf(eth_dev);
5776 rte_free(hw->reset.wait_data);
5779 hns3_mp_uninit_primary();
5781 err_mp_init_primary:
5782 err_mp_init_secondary:
5783 eth_dev->dev_ops = NULL;
5784 eth_dev->rx_pkt_burst = NULL;
5785 eth_dev->tx_pkt_burst = NULL;
5786 eth_dev->tx_pkt_prepare = NULL;
5787 rte_free(eth_dev->process_private);
5788 eth_dev->process_private = NULL;
5793 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5795 struct hns3_adapter *hns = eth_dev->data->dev_private;
5796 struct hns3_hw *hw = &hns->hw;
5798 PMD_INIT_FUNC_TRACE();
5800 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5803 eth_dev->dev_ops = NULL;
5804 eth_dev->rx_pkt_burst = NULL;
5805 eth_dev->tx_pkt_burst = NULL;
5806 eth_dev->tx_pkt_prepare = NULL;
5807 if (hw->adapter_state < HNS3_NIC_CLOSING)
5808 hns3_dev_close(eth_dev);
5810 hw->adapter_state = HNS3_NIC_REMOVED;
5815 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5816 struct rte_pci_device *pci_dev)
5818 return rte_eth_dev_pci_generic_probe(pci_dev,
5819 sizeof(struct hns3_adapter),
5824 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5826 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5829 static const struct rte_pci_id pci_id_hns3_map[] = {
5830 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5831 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5832 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5833 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5834 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5835 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5836 { .vendor_id = 0, /* sentinel */ },
5839 static struct rte_pci_driver rte_hns3_pmd = {
5840 .id_table = pci_id_hns3_map,
5841 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5842 .probe = eth_hns3_pci_probe,
5843 .remove = eth_hns3_pci_remove,
5846 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5847 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5848 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5849 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5850 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);