drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, the PF-related vf_id is 0, just need to configure parameters
 478          * for vport_id 0.
 479          */
 480         vport_id = 0;
 481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 483         req->vf_bitmap[req->vf_offset] = bitmap;
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 488         return ret;
 489 }
 490
 491 static void
 492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_rx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 497 }
 498
 499 static void
 500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 501                            struct hns3_tx_vtag_cfg *vcfg)
 502 {
 503         struct hns3_pf *pf = &hns->pf;
 504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 505 }
 506
 507 static int
 508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 509 {
 510         struct hns3_rx_vtag_cfg rxvlan_cfg;
 511         struct hns3_pf *pf = &hns->pf;
 512         struct hns3_hw *hw = &hns->hw;
 513         int ret;
 514
 515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 516                 rxvlan_cfg.strip_tag1_en = false;
 517                 rxvlan_cfg.strip_tag2_en = enable;
 518         } else {
 519                 rxvlan_cfg.strip_tag1_en = enable;
 520                 rxvlan_cfg.strip_tag2_en = true;
 521         }
 522
 523         rxvlan_cfg.vlan1_vlan_prionly = false;
 524         rxvlan_cfg.vlan2_vlan_prionly = false;
 525         rxvlan_cfg.rx_vlan_offload_en = enable;
 526
 527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 528         if (ret) {
 529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 530                 return ret;
 531         }
 532
 533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 541 {
 542         struct hns3_vlan_filter_ctrl_cmd *req;
 543         struct hns3_cmd_desc desc;
 544         int ret;
 545
 546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 547
 548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 549         req->vlan_type = vlan_type;
 550         req->vlan_fe = filter_en ? fe_type : 0;
 551         req->vf_id = vf_id;
 552
 553         ret = hns3_cmd_send(hw, &desc, 1);
 554         if (ret)
 555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 556
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 562 {
 563         struct hns3_hw *hw = &hns->hw;
 564         int ret;
 565
 566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 567                                         HNS3_FILTER_FE_EGRESS, false, 0);
 568         if (ret) {
 569                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 575         if (ret)
 576                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 577
 578         return ret;
 579 }
 580
 581 static int
 582 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 583 {
 584         struct hns3_adapter *hns = dev->data->dev_private;
 585         struct hns3_hw *hw = &hns->hw;
 586         struct rte_eth_rxmode *rxmode;
 587         unsigned int tmp_mask;
 588         bool enable;
 589         int ret = 0;
 590
 591         rte_spinlock_lock(&hw->lock);
 592         rxmode = &dev->data->dev_conf.rxmode;
 593         tmp_mask = (unsigned int)mask;
 594         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 595                 /* Enable or disable VLAN stripping */
 596                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 597                     true : false;
 598
 599                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 600                 if (ret) {
 601                         rte_spinlock_unlock(&hw->lock);
 602                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 603                         return ret;
 604                 }
 605         }
 606
 607         rte_spinlock_unlock(&hw->lock);
 608
 609         return ret;
 610 }
 611
 612 static int
 613 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 614                              struct hns3_tx_vtag_cfg *vcfg)
 615 {
 616         struct hns3_vport_vtag_tx_cfg_cmd *req;
 617         struct hns3_cmd_desc desc;
 618         struct hns3_hw *hw = &hns->hw;
 619         uint16_t vport_id;
 620         uint8_t bitmap;
 621         int ret;
 622
 623         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 624
 625         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 626         req->def_vlan_tag1 = vcfg->default_tag1;
 627         req->def_vlan_tag2 = vcfg->default_tag2;
 628         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 629                      vcfg->accept_tag1 ? 1 : 0);
 630         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 631                      vcfg->accept_untag1 ? 1 : 0);
 632         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 633                      vcfg->accept_tag2 ? 1 : 0);
 634         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 635                      vcfg->accept_untag2 ? 1 : 0);
 636         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 637                      vcfg->insert_tag1_en ? 1 : 0);
 638         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 639                      vcfg->insert_tag2_en ? 1 : 0);
 640         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 641
 642         /*
 643          * In current version VF is not supported when PF is driven by DPDK
 644          * driver, the PF-related vf_id is 0, just need to configure parameters
 645          * for vport_id 0.
 646          */
 647         vport_id = 0;
 648         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 649         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 650         req->vf_bitmap[req->vf_offset] = bitmap;
 651
 652         ret = hns3_cmd_send(hw, &desc, 1);
 653         if (ret)
 654                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 655
 656         return ret;
 657 }
 658
 659 static int
 660 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 661                      uint16_t pvid)
 662 {
 663         struct hns3_hw *hw = &hns->hw;
 664         struct hns3_tx_vtag_cfg txvlan_cfg;
 665         int ret;
 666
 667         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 668                 txvlan_cfg.accept_tag1 = true;
 669                 txvlan_cfg.insert_tag1_en = false;
 670                 txvlan_cfg.default_tag1 = 0;
 671         } else {
 672                 txvlan_cfg.accept_tag1 = false;
 673                 txvlan_cfg.insert_tag1_en = true;
 674                 txvlan_cfg.default_tag1 = pvid;
 675         }
 676
 677         txvlan_cfg.accept_untag1 = true;
 678         txvlan_cfg.accept_tag2 = true;
 679         txvlan_cfg.accept_untag2 = true;
 680         txvlan_cfg.insert_tag2_en = false;
 681         txvlan_cfg.default_tag2 = 0;
 682
 683         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 684         if (ret) {
 685                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 686                          ret);
 687                 return ret;
 688         }
 689
 690         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 691         return ret;
 692 }
 693
 694 static void
 695 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 696 {
 697         struct hns3_pf *pf = &hns->pf;
 698
 699         pf->port_base_vlan_cfg.state = on ?
 700             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 701
 702         pf->port_base_vlan_cfg.pvid = pvid;
 703 }
 704
 705 static void
 706 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 707 {
 708         struct hns3_user_vlan_table *vlan_entry;
 709         struct hns3_pf *pf = &hns->pf;
 710
 711         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 712                 if (vlan_entry->hd_tbl_status)
 713                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 714
 715                 vlan_entry->hd_tbl_status = false;
 716         }
 717
 718         if (is_del_list) {
 719                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 720                 while (vlan_entry) {
 721                         LIST_REMOVE(vlan_entry, next);
 722                         rte_free(vlan_entry);
 723                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 724                 }
 725         }
 726 }
 727
 728 static void
 729 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 730 {
 731         struct hns3_user_vlan_table *vlan_entry;
 732         struct hns3_pf *pf = &hns->pf;
 733
 734         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 735                 if (!vlan_entry->hd_tbl_status)
 736                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 737
 738                 vlan_entry->hd_tbl_status = true;
 739         }
 740 }
 741
 742 static void
 743 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 744 {
 745         struct hns3_hw *hw = &hns->hw;
 746         struct hns3_pf *pf = &hns->pf;
 747         int ret;
 748
 749         hns3_rm_all_vlan_table(hns, true);
 750         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 751                 ret = hns3_set_port_vlan_filter(hns,
 752                                                 pf->port_base_vlan_cfg.pvid, 0);
 753                 if (ret) {
 754                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 755                                  ret);
 756                         return;
 757                 }
 758         }
 759 }
 760
 761 static int
 762 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 763                                 uint16_t port_base_vlan_state,
 764                                 uint16_t new_pvid, uint16_t old_pvid)
 765 {
 766         struct hns3_pf *pf = &hns->pf;
 767         struct hns3_hw *hw = &hns->hw;
 768         int ret = 0;
 769
 770         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 771                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 772                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 773                         if (ret) {
 774                                 hns3_err(hw,
 775                                          "Failed to clear clear old pvid filter, ret =%d",
 776                                          ret);
 777                                 return ret;
 778                         }
 779                 }
 780
 781                 hns3_rm_all_vlan_table(hns, false);
 782                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 783         }
 784
 785         if (new_pvid != 0) {
 786                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 787                 if (ret) {
 788                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 789                                  ret);
 790                         return ret;
 791                 }
 792         }
 793
 794         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 795                 hns3_add_all_vlan_table(hns);
 796
 797         return ret;
 798 }
 799
 800 static int
 801 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 802 {
 803         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 804         struct hns3_hw *hw = &hns->hw;
 805         bool rx_strip_en;
 806         int ret;
 807
 808         rx_strip_en = on ? true : false;
 809         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 810         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 811         rx_vlan_cfg.vlan1_vlan_prionly = false;
 812         rx_vlan_cfg.vlan2_vlan_prionly = false;
 813         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 814
 815         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 816         if (ret) {
 817                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 818                 return ret;
 819         }
 820
 821         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 822         return ret;
 823 }
 824
 825 static int
 826 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 827 {
 828         struct hns3_pf *pf = &hns->pf;
 829         struct hns3_hw *hw = &hns->hw;
 830         uint16_t port_base_vlan_state;
 831         uint16_t old_pvid;
 832         int ret;
 833
 834         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 835                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 836                         hns3_warn(hw, "Invalid operation! As current pvid set "
 837                                   "is %u, disable pvid %u is invalid",
 838                                   pf->port_base_vlan_cfg.pvid, pvid);
 839                 return 0;
 840         }
 841
 842         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 843                                     HNS3_PORT_BASE_VLAN_DISABLE;
 844         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 845         if (ret) {
 846                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 847                 return ret;
 848         }
 849
 850         ret = hns3_en_rx_strip_all(hns, on);
 851         if (ret) {
 852                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 853                 return ret;
 854         }
 855
 856         if (pvid == HNS3_INVLID_PVID)
 857                 goto out;
 858         old_pvid = pf->port_base_vlan_cfg.pvid;
 859         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 860                                               old_pvid);
 861         if (ret) {
 862                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 863                          ret);
 864                 return ret;
 865         }
 866
 867 out:
 868         hns3_store_port_base_vlan_info(hns, pvid, on);
 869         return ret;
 870 }
 871
 872 static int
 873 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 874 {
 875         struct hns3_adapter *hns = dev->data->dev_private;
 876         struct hns3_hw *hw = &hns->hw;
 877         int ret;
 878
 879         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 880                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 881                          RTE_ETHER_MAX_VLAN_ID);
 882                 return -EINVAL;
 883         }
 884
 885         rte_spinlock_lock(&hw->lock);
 886         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 887         rte_spinlock_unlock(&hw->lock);
 888         return ret;
 889 }
 890
 891 static void
 892 init_port_base_vlan_info(struct hns3_hw *hw)
 893 {
 894         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 895         struct hns3_pf *pf = &hns->pf;
 896
 897         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 898         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 899 }
 900
 901 static int
 902 hns3_default_vlan_config(struct hns3_adapter *hns)
 903 {
 904         struct hns3_hw *hw = &hns->hw;
 905         int ret;
 906
 907         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 908         if (ret)
 909                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 910         return ret;
 911 }
 912
 913 static int
 914 hns3_init_vlan_config(struct hns3_adapter *hns)
 915 {
 916         struct hns3_hw *hw = &hns->hw;
 917         int ret;
 918
 919         /*
 920          * This function can be called in the initialization and reset process,
 921          * when in reset process, it means that hardware had been reseted
 922          * successfully and we need to restore the hardware configuration to
 923          * ensure that the hardware configuration remains unchanged before and
 924          * after reset.
 925          */
 926         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 927                 init_port_base_vlan_info(hw);
 928
 929         ret = hns3_enable_vlan_filter(hns, true);
 930         if (ret) {
 931                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 932                 return ret;
 933         }
 934
 935         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 936                                        RTE_ETHER_TYPE_VLAN);
 937         if (ret) {
 938                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 939                 return ret;
 940         }
 941
 942         /*
 943          * When in the reinit dev stage of the reset process, the following
 944          * vlan-related configurations may differ from those at initialization,
 945          * we will restore configurations to hardware in hns3_restore_vlan_table
 946          * and hns3_restore_vlan_conf later.
 947          */
 948         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 949                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 950                 if (ret) {
 951                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 952                         return ret;
 953                 }
 954
 955                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 956                 if (ret) {
 957                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 958                                  ret);
 959                         return ret;
 960                 }
 961         }
 962
 963         return hns3_default_vlan_config(hns);
 964 }
 965
 966 static int
 967 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 968 {
 969         struct hns3_pf *pf = &hns->pf;
 970         struct hns3_hw *hw = &hns->hw;
 971         int ret;
 972
 973         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 974         if (ret) {
 975                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 976                 return ret;
 977         }
 978
 979         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 980         if (ret)
 981                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 982
 983         return ret;
 984 }
 985
 986 static int
 987 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 988 {
 989         struct hns3_adapter *hns = dev->data->dev_private;
 990         struct rte_eth_dev_data *data = dev->data;
 991         struct rte_eth_txmode *txmode;
 992         struct hns3_hw *hw = &hns->hw;
 993         int ret;
 994
 995         txmode = &data->dev_conf.txmode;
 996         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 997                 hns3_warn(hw,
 998                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 999                           "configuration is not supported! Ignore these two "
1000                           "parameters: hw_vlan_reject_tagged(%d), "
1001                           "hw_vlan_reject_untagged(%d)",
1002                           txmode->hw_vlan_reject_tagged,
1003                           txmode->hw_vlan_reject_untagged);
1004
1005         /* Apply vlan offload setting */
1006         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1007         if (ret) {
1008                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1009                 return ret;
1010         }
1011
1012         /* Apply pvid setting */
1013         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1014                                  txmode->hw_vlan_insert_pvid);
1015         if (ret)
1016                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1017                          txmode->pvid, ret);
1018
1019         return ret;
1020 }
1021
1022 static int
1023 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1024                 unsigned int tso_mss_max)
1025 {
1026         struct hns3_cfg_tso_status_cmd *req;
1027         struct hns3_cmd_desc desc;
1028         uint16_t tso_mss;
1029
1030         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1031
1032         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1033
1034         tso_mss = 0;
1035         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1036                        tso_mss_min);
1037         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1038
1039         tso_mss = 0;
1040         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1041                        tso_mss_max);
1042         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1043
1044         return hns3_cmd_send(hw, &desc, 1);
1045 }
1046
1047 int
1048 hns3_config_gro(struct hns3_hw *hw, bool en)
1049 {
1050         struct hns3_cfg_gro_status_cmd *req;
1051         struct hns3_cmd_desc desc;
1052         int ret;
1053
1054         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1055         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1056
1057         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1058
1059         ret = hns3_cmd_send(hw, &desc, 1);
1060         if (ret)
1061                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1062
1063         return ret;
1064 }
1065
1066 static int
1067 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1068                    uint16_t *allocated_size, bool is_alloc)
1069 {
1070         struct hns3_umv_spc_alc_cmd *req;
1071         struct hns3_cmd_desc desc;
1072         int ret;
1073
1074         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1075         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1076         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1077         req->space_size = rte_cpu_to_le_32(space_size);
1078
1079         ret = hns3_cmd_send(hw, &desc, 1);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1082                              is_alloc ? "allocate" : "free", ret);
1083                 return ret;
1084         }
1085
1086         if (is_alloc && allocated_size)
1087                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1088
1089         return 0;
1090 }
1091
1092 static int
1093 hns3_init_umv_space(struct hns3_hw *hw)
1094 {
1095         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1096         struct hns3_pf *pf = &hns->pf;
1097         uint16_t allocated_size = 0;
1098         int ret;
1099
1100         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1101                                  true);
1102         if (ret)
1103                 return ret;
1104
1105         if (allocated_size < pf->wanted_umv_size)
1106                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1107                              pf->wanted_umv_size, allocated_size);
1108
1109         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1110                                                 pf->wanted_umv_size;
1111         pf->used_umv_size = 0;
1112         return 0;
1113 }
1114
1115 static int
1116 hns3_uninit_umv_space(struct hns3_hw *hw)
1117 {
1118         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1119         struct hns3_pf *pf = &hns->pf;
1120         int ret;
1121
1122         if (pf->max_umv_size == 0)
1123                 return 0;
1124
1125         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1126         if (ret)
1127                 return ret;
1128
1129         pf->max_umv_size = 0;
1130
1131         return 0;
1132 }
1133
1134 static bool
1135 hns3_is_umv_space_full(struct hns3_hw *hw)
1136 {
1137         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1138         struct hns3_pf *pf = &hns->pf;
1139         bool is_full;
1140
1141         is_full = (pf->used_umv_size >= pf->max_umv_size);
1142
1143         return is_full;
1144 }
1145
1146 static void
1147 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1148 {
1149         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1150         struct hns3_pf *pf = &hns->pf;
1151
1152         if (is_free) {
1153                 if (pf->used_umv_size > 0)
1154                         pf->used_umv_size--;
1155         } else
1156                 pf->used_umv_size++;
1157 }
1158
1159 static void
1160 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1161                       const uint8_t *addr, bool is_mc)
1162 {
1163         const unsigned char *mac_addr = addr;
1164         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1165                             ((uint32_t)mac_addr[2] << 16) |
1166                             ((uint32_t)mac_addr[1] << 8) |
1167                             (uint32_t)mac_addr[0];
1168         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1169
1170         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1171         if (is_mc) {
1172                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1173                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1174                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1175         }
1176
1177         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1178         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1179 }
1180
1181 static int
1182 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1183                              uint8_t resp_code,
1184                              enum hns3_mac_vlan_tbl_opcode op)
1185 {
1186         if (cmdq_resp) {
1187                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1188                          cmdq_resp);
1189                 return -EIO;
1190         }
1191
1192         if (op == HNS3_MAC_VLAN_ADD) {
1193                 if (resp_code == 0 || resp_code == 1) {
1194                         return 0;
1195                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1196                         hns3_err(hw, "add mac addr failed for uc_overflow");
1197                         return -ENOSPC;
1198                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1199                         hns3_err(hw, "add mac addr failed for mc_overflow");
1200                         return -ENOSPC;
1201                 }
1202
1203                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "remove mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         } else if (op == HNS3_MAC_VLAN_LKUP) {
1218                 if (resp_code == 0) {
1219                         return 0;
1220                 } else if (resp_code == 1) {
1221                         hns3_dbg(hw, "lookup mac addr failed for miss");
1222                         return -ENOENT;
1223                 }
1224
1225                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1226                          resp_code);
1227                 return -EIO;
1228         }
1229
1230         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1231                  op);
1232
1233         return -EINVAL;
1234 }
1235
1236 static int
1237 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1238                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1239                          struct hns3_cmd_desc *desc, bool is_mc)
1240 {
1241         uint8_t resp_code;
1242         uint16_t retval;
1243         int ret;
1244
1245         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1246         if (is_mc) {
1247                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1248                 memcpy(desc[0].data, req,
1249                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1250                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1251                                           true);
1252                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1253                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1254                                           true);
1255                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1256         } else {
1257                 memcpy(desc[0].data, req,
1258                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1259                 ret = hns3_cmd_send(hw, desc, 1);
1260         }
1261         if (ret) {
1262                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1263                          ret);
1264                 return ret;
1265         }
1266         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1267         retval = rte_le_to_cpu_16(desc[0].retval);
1268
1269         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1270                                             HNS3_MAC_VLAN_LKUP);
1271 }
1272
1273 static int
1274 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1275                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1276                       struct hns3_cmd_desc *mc_desc)
1277 {
1278         uint8_t resp_code;
1279         uint16_t retval;
1280         int cfg_status;
1281         int ret;
1282
1283         if (mc_desc == NULL) {
1284                 struct hns3_cmd_desc desc;
1285
1286                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1287                 memcpy(desc.data, req,
1288                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1289                 ret = hns3_cmd_send(hw, &desc, 1);
1290                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1291                 retval = rte_le_to_cpu_16(desc.retval);
1292
1293                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1294                                                           HNS3_MAC_VLAN_ADD);
1295         } else {
1296                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1297                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1299                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1301                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1302                 memcpy(mc_desc[0].data, req,
1303                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1304                 mc_desc[0].retval = 0;
1305                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1306                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1307                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1308
1309                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1310                                                           HNS3_MAC_VLAN_ADD);
1311         }
1312
1313         if (ret) {
1314                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1315                 return ret;
1316         }
1317
1318         return cfg_status;
1319 }
1320
1321 static int
1322 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1323                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1324 {
1325         struct hns3_cmd_desc desc;
1326         uint8_t resp_code;
1327         uint16_t retval;
1328         int ret;
1329
1330         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1331
1332         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1333
1334         ret = hns3_cmd_send(hw, &desc, 1);
1335         if (ret) {
1336                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1337                 return ret;
1338         }
1339         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1340         retval = rte_le_to_cpu_16(desc.retval);
1341
1342         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343                                             HNS3_MAC_VLAN_REMOVE);
1344 }
1345
1346 static int
1347 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1348 {
1349         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1350         struct hns3_mac_vlan_tbl_entry_cmd req;
1351         struct hns3_pf *pf = &hns->pf;
1352         struct hns3_cmd_desc desc;
1353         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1354         uint16_t egress_port = 0;
1355         uint8_t vf_id;
1356         int ret;
1357
1358         /* check if mac addr is valid */
1359         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1360                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1361                                       mac_addr);
1362                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1363                          mac_str);
1364                 return -EINVAL;
1365         }
1366
1367         memset(&req, 0, sizeof(req));
1368
1369         /*
1370          * In current version VF is not supported when PF is driven by DPDK
1371          * driver, the PF-related vf_id is 0, just need to configure parameters
1372          * for vf_id 0.
1373          */
1374         vf_id = 0;
1375         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1376                        HNS3_MAC_EPORT_VFID_S, vf_id);
1377
1378         req.egress_port = rte_cpu_to_le_16(egress_port);
1379
1380         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1381
1382         /*
1383          * Lookup the mac address in the mac_vlan table, and add
1384          * it if the entry is inexistent. Repeated unicast entry
1385          * is not allowed in the mac vlan table.
1386          */
1387         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1388         if (ret == -ENOENT) {
1389                 if (!hns3_is_umv_space_full(hw)) {
1390                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1391                         if (!ret)
1392                                 hns3_update_umv_space(hw, false);
1393                         return ret;
1394                 }
1395
1396                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1397
1398                 return -ENOSPC;
1399         }
1400
1401         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1402
1403         /* check if we just hit the duplicate */
1404         if (ret == 0) {
1405                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1406                 return 0;
1407         }
1408
1409         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1410                  mac_str);
1411
1412         return ret;
1413 }
1414
1415 static int
1416 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1417 {
1418         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1419         struct rte_ether_addr *addr;
1420         int ret;
1421         int i;
1422
1423         for (i = 0; i < hw->mc_addrs_num; i++) {
1424                 addr = &hw->mc_addrs[i];
1425                 /* Check if there are duplicate addresses */
1426                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1427                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1428                                               addr);
1429                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1430                                  "(%s) is added by the set_mc_mac_addr_list "
1431                                  "API", mac_str);
1432                         return -EINVAL;
1433                 }
1434         }
1435
1436         ret = hns3_add_mc_addr(hw, mac_addr);
1437         if (ret) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1441                          mac_str, ret);
1442         }
1443         return ret;
1444 }
1445
1446 static int
1447 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1448 {
1449         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1450         int ret;
1451
1452         ret = hns3_remove_mc_addr(hw, mac_addr);
1453         if (ret) {
1454                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1455                                       mac_addr);
1456                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1457                          mac_str, ret);
1458         }
1459         return ret;
1460 }
1461
1462 static int
1463 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1464                   uint32_t idx, __rte_unused uint32_t pool)
1465 {
1466         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1468         int ret;
1469
1470         rte_spinlock_lock(&hw->lock);
1471
1472         /*
1473          * In hns3 network engine adding UC and MC mac address with different
1474          * commands with firmware. We need to determine whether the input
1475          * address is a UC or a MC address to call different commands.
1476          * By the way, it is recommended calling the API function named
1477          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1478          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1479          * may affect the specifications of UC mac addresses.
1480          */
1481         if (rte_is_multicast_ether_addr(mac_addr))
1482                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1483         else
1484                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1485
1486         if (ret) {
1487                 rte_spinlock_unlock(&hw->lock);
1488                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1489                                       mac_addr);
1490                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1491                          ret);
1492                 return ret;
1493         }
1494
1495         if (idx == 0)
1496                 hw->mac.default_addr_setted = true;
1497         rte_spinlock_unlock(&hw->lock);
1498
1499         return ret;
1500 }
1501
1502 static int
1503 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1504 {
1505         struct hns3_mac_vlan_tbl_entry_cmd req;
1506         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1507         int ret;
1508
1509         /* check if mac addr is valid */
1510         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1511                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                       mac_addr);
1513                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1514                          mac_str);
1515                 return -EINVAL;
1516         }
1517
1518         memset(&req, 0, sizeof(req));
1519         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1520         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1521         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1522         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1523                 return 0;
1524         else if (ret == 0)
1525                 hns3_update_umv_space(hw, true);
1526
1527         return ret;
1528 }
1529
1530 static void
1531 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1532 {
1533         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         /* index will be checked by upper level rte interface */
1535         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1536         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1537         int ret;
1538
1539         rte_spinlock_lock(&hw->lock);
1540
1541         if (rte_is_multicast_ether_addr(mac_addr))
1542                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1543         else
1544                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1545         rte_spinlock_unlock(&hw->lock);
1546         if (ret) {
1547                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1548                                       mac_addr);
1549                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1550                          ret);
1551         }
1552 }
1553
1554 static int
1555 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1556                           struct rte_ether_addr *mac_addr)
1557 {
1558         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1559         struct rte_ether_addr *oaddr;
1560         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1561         bool default_addr_setted;
1562         bool rm_succes = false;
1563         int ret, ret_val;
1564
1565         /*
1566          * It has been guaranteed that input parameter named mac_addr is valid
1567          * address in the rte layer of DPDK framework.
1568          */
1569         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1570         default_addr_setted = hw->mac.default_addr_setted;
1571         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1572                 return 0;
1573
1574         rte_spinlock_lock(&hw->lock);
1575         if (default_addr_setted) {
1576                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1577                 if (ret) {
1578                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1579                                               oaddr);
1580                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1581                                   mac_str, ret);
1582                         rm_succes = false;
1583                 } else
1584                         rm_succes = true;
1585         }
1586
1587         ret = hns3_add_uc_addr_common(hw, mac_addr);
1588         if (ret) {
1589                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1590                                       mac_addr);
1591                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1592                 goto err_add_uc_addr;
1593         }
1594
1595         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1596         if (ret) {
1597                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1598                 goto err_pause_addr_cfg;
1599         }
1600
1601         rte_ether_addr_copy(mac_addr,
1602                             (struct rte_ether_addr *)hw->mac.mac_addr);
1603         hw->mac.default_addr_setted = true;
1604         rte_spinlock_unlock(&hw->lock);
1605
1606         return 0;
1607
1608 err_pause_addr_cfg:
1609         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1610         if (ret_val) {
1611                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1612                                       mac_addr);
1613                 hns3_warn(hw,
1614                           "Failed to roll back to del setted mac addr(%s): %d",
1615                           mac_str, ret_val);
1616         }
1617
1618 err_add_uc_addr:
1619         if (rm_succes) {
1620                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1621                 if (ret_val) {
1622                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1623                                               oaddr);
1624                         hns3_warn(hw,
1625                                   "Failed to restore old uc mac addr(%s): %d",
1626                                   mac_str, ret_val);
1627                         hw->mac.default_addr_setted = false;
1628                 }
1629         }
1630         rte_spinlock_unlock(&hw->lock);
1631
1632         return ret;
1633 }
1634
1635 static int
1636 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1637 {
1638         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1639         struct hns3_hw *hw = &hns->hw;
1640         struct rte_ether_addr *addr;
1641         int err = 0;
1642         int ret;
1643         int i;
1644
1645         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1646                 addr = &hw->data->mac_addrs[i];
1647                 if (rte_is_zero_ether_addr(addr))
1648                         continue;
1649                 if (rte_is_multicast_ether_addr(addr))
1650                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1651                               hns3_add_mc_addr(hw, addr);
1652                 else
1653                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1654                               hns3_add_uc_addr_common(hw, addr);
1655
1656                 if (ret) {
1657                         err = ret;
1658                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1659                                               addr);
1660                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1661                                  "ret = %d.", del ? "remove" : "restore",
1662                                  mac_str, i, ret);
1663                 }
1664         }
1665         return err;
1666 }
1667
1668 static void
1669 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1670 {
1671 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1672         uint8_t word_num;
1673         uint8_t bit_num;
1674
1675         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1676                 word_num = vfid / 32;
1677                 bit_num = vfid % 32;
1678                 if (clr)
1679                         desc[1].data[word_num] &=
1680                             rte_cpu_to_le_32(~(1UL << bit_num));
1681                 else
1682                         desc[1].data[word_num] |=
1683                             rte_cpu_to_le_32(1UL << bit_num);
1684         } else {
1685                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1686                 bit_num = vfid % 32;
1687                 if (clr)
1688                         desc[2].data[word_num] &=
1689                             rte_cpu_to_le_32(~(1UL << bit_num));
1690                 else
1691                         desc[2].data[word_num] |=
1692                             rte_cpu_to_le_32(1UL << bit_num);
1693         }
1694 }
1695
1696 static int
1697 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1698 {
1699         struct hns3_mac_vlan_tbl_entry_cmd req;
1700         struct hns3_cmd_desc desc[3];
1701         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1702         uint8_t vf_id;
1703         int ret;
1704
1705         /* Check if mac addr is valid */
1706         if (!rte_is_multicast_ether_addr(mac_addr)) {
1707                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1708                                       mac_addr);
1709                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1710                          mac_str);
1711                 return -EINVAL;
1712         }
1713
1714         memset(&req, 0, sizeof(req));
1715         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1716         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1717         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1718         if (ret) {
1719                 /* This mac addr do not exist, add new entry for it */
1720                 memset(desc[0].data, 0, sizeof(desc[0].data));
1721                 memset(desc[1].data, 0, sizeof(desc[0].data));
1722                 memset(desc[2].data, 0, sizeof(desc[0].data));
1723         }
1724
1725         /*
1726          * In current version VF is not supported when PF is driven by DPDK
1727          * driver, the PF-related vf_id is 0, just need to configure parameters
1728          * for vf_id 0.
1729          */
1730         vf_id = 0;
1731         hns3_update_desc_vfid(desc, vf_id, false);
1732         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1733         if (ret) {
1734                 if (ret == -ENOSPC)
1735                         hns3_err(hw, "mc mac vlan table is full");
1736                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1737                                       mac_addr);
1738                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1739         }
1740
1741         return ret;
1742 }
1743
1744 static int
1745 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1746 {
1747         struct hns3_mac_vlan_tbl_entry_cmd req;
1748         struct hns3_cmd_desc desc[3];
1749         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1750         uint8_t vf_id;
1751         int ret;
1752
1753         /* Check if mac addr is valid */
1754         if (!rte_is_multicast_ether_addr(mac_addr)) {
1755                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1756                                       mac_addr);
1757                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1758                          mac_str);
1759                 return -EINVAL;
1760         }
1761
1762         memset(&req, 0, sizeof(req));
1763         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1764         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1765         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1766         if (ret == 0) {
1767                 /*
1768                  * This mac addr exist, remove this handle's VFID for it.
1769                  * In current version VF is not supported when PF is driven by
1770                  * DPDK driver, the PF-related vf_id is 0, just need to
1771                  * configure parameters for vf_id 0.
1772                  */
1773                 vf_id = 0;
1774                 hns3_update_desc_vfid(desc, vf_id, true);
1775
1776                 /* All the vfid is zero, so need to delete this entry */
1777                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1778         } else if (ret == -ENOENT) {
1779                 /* This mac addr doesn't exist. */
1780                 return 0;
1781         }
1782
1783         if (ret) {
1784                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1785                                       mac_addr);
1786                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1787         }
1788
1789         return ret;
1790 }
1791
1792 static int
1793 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1794                            struct rte_ether_addr *mc_addr_set,
1795                            uint32_t nb_mc_addr)
1796 {
1797         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1798         struct rte_ether_addr *addr;
1799         uint32_t i;
1800         uint32_t j;
1801
1802         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1803                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1804                          "invalid. valid range: 0~%d",
1805                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1806                 return -EINVAL;
1807         }
1808
1809         /* Check if input mac addresses are valid */
1810         for (i = 0; i < nb_mc_addr; i++) {
1811                 addr = &mc_addr_set[i];
1812                 if (!rte_is_multicast_ether_addr(addr)) {
1813                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                               addr);
1815                         hns3_err(hw,
1816                                  "failed to set mc mac addr, addr(%s) invalid.",
1817                                  mac_str);
1818                         return -EINVAL;
1819                 }
1820
1821                 /* Check if there are duplicate addresses */
1822                 for (j = i + 1; j < nb_mc_addr; j++) {
1823                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1824                                 rte_ether_format_addr(mac_str,
1825                                                       RTE_ETHER_ADDR_FMT_SIZE,
1826                                                       addr);
1827                                 hns3_err(hw, "failed to set mc mac addr, "
1828                                          "addrs invalid. two same addrs(%s).",
1829                                          mac_str);
1830                                 return -EINVAL;
1831                         }
1832                 }
1833
1834                 /*
1835                  * Check if there are duplicate addresses between mac_addrs
1836                  * and mc_addr_set
1837                  */
1838                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1839                         if (rte_is_same_ether_addr(addr,
1840                                                    &hw->data->mac_addrs[j])) {
1841                                 rte_ether_format_addr(mac_str,
1842                                                       RTE_ETHER_ADDR_FMT_SIZE,
1843                                                       addr);
1844                                 hns3_err(hw, "failed to set mc mac addr, "
1845                                          "addrs invalid. addrs(%s) has already "
1846                                          "configured in mac_addr add API",
1847                                          mac_str);
1848                                 return -EINVAL;
1849                         }
1850                 }
1851         }
1852
1853         return 0;
1854 }
1855
1856 static void
1857 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1858                            struct rte_ether_addr *mc_addr_set,
1859                            int mc_addr_num,
1860                            struct rte_ether_addr *reserved_addr_list,
1861                            int *reserved_addr_num,
1862                            struct rte_ether_addr *add_addr_list,
1863                            int *add_addr_num,
1864                            struct rte_ether_addr *rm_addr_list,
1865                            int *rm_addr_num)
1866 {
1867         struct rte_ether_addr *addr;
1868         int current_addr_num;
1869         int reserved_num = 0;
1870         int add_num = 0;
1871         int rm_num = 0;
1872         int num;
1873         int i;
1874         int j;
1875         bool same_addr;
1876
1877         /* Calculate the mc mac address list that should be removed */
1878         current_addr_num = hw->mc_addrs_num;
1879         for (i = 0; i < current_addr_num; i++) {
1880                 addr = &hw->mc_addrs[i];
1881                 same_addr = false;
1882                 for (j = 0; j < mc_addr_num; j++) {
1883                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1884                                 same_addr = true;
1885                                 break;
1886                         }
1887                 }
1888
1889                 if (!same_addr) {
1890                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1891                         rm_num++;
1892                 } else {
1893                         rte_ether_addr_copy(addr,
1894                                             &reserved_addr_list[reserved_num]);
1895                         reserved_num++;
1896                 }
1897         }
1898
1899         /* Calculate the mc mac address list that should be added */
1900         for (i = 0; i < mc_addr_num; i++) {
1901                 addr = &mc_addr_set[i];
1902                 same_addr = false;
1903                 for (j = 0; j < current_addr_num; j++) {
1904                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1905                                 same_addr = true;
1906                                 break;
1907                         }
1908                 }
1909
1910                 if (!same_addr) {
1911                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1912                         add_num++;
1913                 }
1914         }
1915
1916         /* Reorder the mc mac address list maintained by driver */
1917         for (i = 0; i < reserved_num; i++)
1918                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1919
1920         for (i = 0; i < rm_num; i++) {
1921                 num = reserved_num + i;
1922                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1923         }
1924
1925         *reserved_addr_num = reserved_num;
1926         *add_addr_num = add_num;
1927         *rm_addr_num = rm_num;
1928 }
1929
1930 static int
1931 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1932                           struct rte_ether_addr *mc_addr_set,
1933                           uint32_t nb_mc_addr)
1934 {
1935         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1937         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1938         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1939         struct rte_ether_addr *addr;
1940         int reserved_addr_num;
1941         int add_addr_num;
1942         int rm_addr_num;
1943         int mc_addr_num;
1944         int num;
1945         int ret;
1946         int i;
1947
1948         /* Check if input parameters are valid */
1949         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1950         if (ret)
1951                 return ret;
1952
1953         rte_spinlock_lock(&hw->lock);
1954
1955         /*
1956          * Calculate the mc mac address lists those should be removed and be
1957          * added, Reorder the mc mac address list maintained by driver.
1958          */
1959         mc_addr_num = (int)nb_mc_addr;
1960         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1961                                    reserved_addr_list, &reserved_addr_num,
1962                                    add_addr_list, &add_addr_num,
1963                                    rm_addr_list, &rm_addr_num);
1964
1965         /* Remove mc mac addresses */
1966         for (i = 0; i < rm_addr_num; i++) {
1967                 num = rm_addr_num - i - 1;
1968                 addr = &rm_addr_list[num];
1969                 ret = hns3_remove_mc_addr(hw, addr);
1970                 if (ret) {
1971                         rte_spinlock_unlock(&hw->lock);
1972                         return ret;
1973                 }
1974                 hw->mc_addrs_num--;
1975         }
1976
1977         /* Add mc mac addresses */
1978         for (i = 0; i < add_addr_num; i++) {
1979                 addr = &add_addr_list[i];
1980                 ret = hns3_add_mc_addr(hw, addr);
1981                 if (ret) {
1982                         rte_spinlock_unlock(&hw->lock);
1983                         return ret;
1984                 }
1985
1986                 num = reserved_addr_num + i;
1987                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1988                 hw->mc_addrs_num++;
1989         }
1990         rte_spinlock_unlock(&hw->lock);
1991
1992         return 0;
1993 }
1994
1995 static int
1996 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1997 {
1998         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1999         struct hns3_hw *hw = &hns->hw;
2000         struct rte_ether_addr *addr;
2001         int err = 0;
2002         int ret;
2003         int i;
2004
2005         for (i = 0; i < hw->mc_addrs_num; i++) {
2006                 addr = &hw->mc_addrs[i];
2007                 if (!rte_is_multicast_ether_addr(addr))
2008                         continue;
2009                 if (del)
2010                         ret = hns3_remove_mc_addr(hw, addr);
2011                 else
2012                         ret = hns3_add_mc_addr(hw, addr);
2013                 if (ret) {
2014                         err = ret;
2015                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2016                                               addr);
2017                         hns3_dbg(hw, "%s mc mac addr: %s failed",
2018                                  del ? "Remove" : "Restore", mac_str);
2019                 }
2020         }
2021         return err;
2022 }
2023
2024 static int
2025 hns3_check_mq_mode(struct rte_eth_dev *dev)
2026 {
2027         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2028         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2031         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2032         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2033         uint8_t num_tc;
2034         int max_tc = 0;
2035         int i;
2036
2037         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2038         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2039
2040         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2041                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2042                          "rx_mq_mode = %d", rx_mq_mode);
2043                 return -EINVAL;
2044         }
2045
2046         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2047             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2048                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2049                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2050                          rx_mq_mode, tx_mq_mode);
2051                 return -EINVAL;
2052         }
2053
2054         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2055                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2056                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2057                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2058                         return -EINVAL;
2059                 }
2060
2061                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2062                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2063                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2064                                  "nb_tcs(%d) != %d or %d in rx direction.",
2065                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2066                         return -EINVAL;
2067                 }
2068
2069                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2070                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2071                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2072                         return -EINVAL;
2073                 }
2074
2075                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2076                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2077                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2078                                          "is not equal to one in tx direction.",
2079                                          i, dcb_rx_conf->dcb_tc[i]);
2080                                 return -EINVAL;
2081                         }
2082                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2083                                 max_tc = dcb_rx_conf->dcb_tc[i];
2084                 }
2085
2086                 num_tc = max_tc + 1;
2087                 if (num_tc > dcb_rx_conf->nb_tcs) {
2088                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2089                                  num_tc, dcb_rx_conf->nb_tcs);
2090                         return -EINVAL;
2091                 }
2092         }
2093
2094         return 0;
2095 }
2096
2097 static int
2098 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2099 {
2100         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101
2102         if (!hns3_dev_dcb_supported(hw)) {
2103                 hns3_err(hw, "this port does not support dcb configurations.");
2104                 return -EOPNOTSUPP;
2105         }
2106
2107         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2108                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2109                 return -EOPNOTSUPP;
2110         }
2111
2112         /* Check multiple queue mode */
2113         return hns3_check_mq_mode(dev);
2114 }
2115
2116 static int
2117 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2118                            enum hns3_ring_type queue_type, uint16_t queue_id)
2119 {
2120         struct hns3_cmd_desc desc;
2121         struct hns3_ctrl_vector_chain_cmd *req =
2122                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2123         enum hns3_cmd_status status;
2124         enum hns3_opcode_type op;
2125         uint16_t tqp_type_and_id = 0;
2126         const char *op_str;
2127         uint16_t type;
2128         uint16_t gl;
2129
2130         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2131         hns3_cmd_setup_basic_desc(&desc, op, false);
2132         req->int_vector_id = vector_id;
2133
2134         if (queue_type == HNS3_RING_TYPE_RX)
2135                 gl = HNS3_RING_GL_RX;
2136         else
2137                 gl = HNS3_RING_GL_TX;
2138
2139         type = queue_type;
2140
2141         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2142                        type);
2143         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2144         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2145                        gl);
2146         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2147         req->int_cause_num = 1;
2148         op_str = mmap ? "Map" : "Unmap";
2149         status = hns3_cmd_send(hw, &desc, 1);
2150         if (status) {
2151                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2152                          op_str, queue_id, req->int_vector_id, status);
2153                 return status;
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int
2160 hns3_init_ring_with_vector(struct hns3_hw *hw)
2161 {
2162         uint8_t vec;
2163         int ret;
2164         int i;
2165
2166         /*
2167          * In hns3 network engine, vector 0 is always the misc interrupt of this
2168          * function, vector 1~N can be used respectively for the queues of the
2169          * function. Tx and Rx queues with the same number share the interrupt
2170          * vector. In the initialization clearing the all hardware mapping
2171          * relationship configurations between queues and interrupt vectors is
2172          * needed, so some error caused by the residual configurations, such as
2173          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2174          * constraints in hns3 hardware engine, we have to implement clearing
2175          * the mapping relationship configurations by binding all queues to the
2176          * last interrupt vector and reserving the last interrupt vector. This
2177          * method results in a decrease of the maximum queues when upper
2178          * applications call the rte_eth_dev_configure API function to enable
2179          * Rx interrupt.
2180          */
2181         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2182         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2183         for (i = 0; i < hw->intr_tqps_num; i++) {
2184                 /*
2185                  * Set gap limiter and rate limiter configuration of queue's
2186                  * interrupt.
2187                  */
2188                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2189                                        HNS3_TQP_INTR_GL_DEFAULT);
2190                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2191                                        HNS3_TQP_INTR_GL_DEFAULT);
2192                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2193
2194                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2195                                                  HNS3_RING_TYPE_TX, i);
2196                 if (ret) {
2197                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2198                                           "vector: %d, ret=%d", i, vec, ret);
2199                         return ret;
2200                 }
2201
2202                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2203                                                  HNS3_RING_TYPE_RX, i);
2204                 if (ret) {
2205                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2206                                           "vector: %d, ret=%d", i, vec, ret);
2207                         return ret;
2208                 }
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int
2215 hns3_dev_configure(struct rte_eth_dev *dev)
2216 {
2217         struct hns3_adapter *hns = dev->data->dev_private;
2218         struct rte_eth_conf *conf = &dev->data->dev_conf;
2219         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2220         struct hns3_hw *hw = &hns->hw;
2221         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2222         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2223         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2224         struct rte_eth_rss_conf rss_conf;
2225         uint16_t mtu;
2226         int ret;
2227
2228         /*
2229          * Hardware does not support individually enable/disable/reset the Tx or
2230          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2231          * and Rx queues at the same time. When the numbers of Tx queues
2232          * allocated by upper applications are not equal to the numbers of Rx
2233          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2234          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2235          * these fake queues are imperceptible, and can not be used by upper
2236          * applications.
2237          */
2238         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2239         if (ret) {
2240                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2241                 return ret;
2242         }
2243
2244         hw->adapter_state = HNS3_NIC_CONFIGURING;
2245         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2246                 hns3_err(hw, "setting link speed/duplex not supported");
2247                 ret = -EINVAL;
2248                 goto cfg_err;
2249         }
2250
2251         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2252                 ret = hns3_check_dcb_cfg(dev);
2253                 if (ret)
2254                         goto cfg_err;
2255         }
2256
2257         /* When RSS is not configured, redirect the packet queue 0 */
2258         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2259                 rss_conf = conf->rx_adv_conf.rss_conf;
2260                 if (rss_conf.rss_key == NULL) {
2261                         rss_conf.rss_key = rss_cfg->key;
2262                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2263                 }
2264
2265                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2266                 if (ret)
2267                         goto cfg_err;
2268         }
2269
2270         /*
2271          * If jumbo frames are enabled, MTU needs to be refreshed
2272          * according to the maximum RX packet length.
2273          */
2274         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2275                 /*
2276                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2277                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2278                  * can safely assign to "uint16_t" type variable.
2279                  */
2280                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2281                 ret = hns3_dev_mtu_set(dev, mtu);
2282                 if (ret)
2283                         goto cfg_err;
2284                 dev->data->mtu = mtu;
2285         }
2286
2287         ret = hns3_dev_configure_vlan(dev);
2288         if (ret)
2289                 goto cfg_err;
2290
2291         hw->adapter_state = HNS3_NIC_CONFIGURED;
2292
2293         return 0;
2294
2295 cfg_err:
2296         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2297         hw->adapter_state = HNS3_NIC_INITIALIZED;
2298
2299         return ret;
2300 }
2301
2302 static int
2303 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2304 {
2305         struct hns3_config_max_frm_size_cmd *req;
2306         struct hns3_cmd_desc desc;
2307
2308         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2309
2310         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2311         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2312         req->min_frm_size = RTE_ETHER_MIN_LEN;
2313
2314         return hns3_cmd_send(hw, &desc, 1);
2315 }
2316
2317 static int
2318 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2319 {
2320         int ret;
2321
2322         ret = hns3_set_mac_mtu(hw, mps);
2323         if (ret) {
2324                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2325                 return ret;
2326         }
2327
2328         ret = hns3_buffer_alloc(hw);
2329         if (ret)
2330                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2331
2332         return ret;
2333 }
2334
2335 static int
2336 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2337 {
2338         struct hns3_adapter *hns = dev->data->dev_private;
2339         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2340         struct hns3_hw *hw = &hns->hw;
2341         bool is_jumbo_frame;
2342         int ret;
2343
2344         if (dev->data->dev_started) {
2345                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2346                          "before configuration", dev->data->port_id);
2347                 return -EBUSY;
2348         }
2349
2350         rte_spinlock_lock(&hw->lock);
2351         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2352         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2353
2354         /*
2355          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2356          * assign to "uint16_t" type variable.
2357          */
2358         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2359         if (ret) {
2360                 rte_spinlock_unlock(&hw->lock);
2361                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2362                          dev->data->port_id, mtu, ret);
2363                 return ret;
2364         }
2365         hns->pf.mps = (uint16_t)frame_size;
2366         if (is_jumbo_frame)
2367                 dev->data->dev_conf.rxmode.offloads |=
2368                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2369         else
2370                 dev->data->dev_conf.rxmode.offloads &=
2371                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2372         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2373         rte_spinlock_unlock(&hw->lock);
2374
2375         return 0;
2376 }
2377
2378 static int
2379 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2380 {
2381         struct hns3_adapter *hns = eth_dev->data->dev_private;
2382         struct hns3_hw *hw = &hns->hw;
2383         uint16_t queue_num = hw->tqps_num;
2384
2385         /*
2386          * In interrupt mode, 'max_rx_queues' is set based on the number of
2387          * MSI-X interrupt resources of the hardware.
2388          */
2389         if (hw->data->dev_conf.intr_conf.rxq == 1)
2390                 queue_num = hw->intr_tqps_num;
2391
2392         info->max_rx_queues = queue_num;
2393         info->max_tx_queues = hw->tqps_num;
2394         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2395         info->min_rx_bufsize = hw->rx_buf_len;
2396         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2397         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2398         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2399                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2400                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2401                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2402                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2403                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2404                                  DEV_RX_OFFLOAD_KEEP_CRC |
2405                                  DEV_RX_OFFLOAD_SCATTER |
2406                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2407                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2408                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2409                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2410                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2411                                  DEV_RX_OFFLOAD_RSS_HASH);
2412         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2413         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2414                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2415                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2416                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2417                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2418                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2419                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2420                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2421                                  DEV_TX_OFFLOAD_TCP_TSO |
2422                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2423                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2424                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2425                                  info->tx_queue_offload_capa);
2426
2427         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2428                 .nb_max = HNS3_MAX_RING_DESC,
2429                 .nb_min = HNS3_MIN_RING_DESC,
2430                 .nb_align = HNS3_ALIGN_RING_DESC,
2431         };
2432
2433         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2434                 .nb_max = HNS3_MAX_RING_DESC,
2435                 .nb_min = HNS3_MIN_RING_DESC,
2436                 .nb_align = HNS3_ALIGN_RING_DESC,
2437         };
2438
2439         info->vmdq_queue_num = 0;
2440
2441         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2442         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2443         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2444
2445         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2446         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2447         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2448         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2449         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2450         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2451
2452         return 0;
2453 }
2454
2455 static int
2456 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2457                     size_t fw_size)
2458 {
2459         struct hns3_adapter *hns = eth_dev->data->dev_private;
2460         struct hns3_hw *hw = &hns->hw;
2461         int ret;
2462
2463         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2464         ret += 1; /* add the size of '\0' */
2465         if (fw_size < (uint32_t)ret)
2466                 return ret;
2467         else
2468                 return 0;
2469 }
2470
2471 static int
2472 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2473                      __rte_unused int wait_to_complete)
2474 {
2475         struct hns3_adapter *hns = eth_dev->data->dev_private;
2476         struct hns3_hw *hw = &hns->hw;
2477         struct hns3_mac *mac = &hw->mac;
2478         struct rte_eth_link new_link;
2479
2480         if (!hns3_is_reset_pending(hns)) {
2481                 hns3_update_speed_duplex(eth_dev);
2482                 hns3_update_link_status(hw);
2483         }
2484
2485         memset(&new_link, 0, sizeof(new_link));
2486         switch (mac->link_speed) {
2487         case ETH_SPEED_NUM_10M:
2488         case ETH_SPEED_NUM_100M:
2489         case ETH_SPEED_NUM_1G:
2490         case ETH_SPEED_NUM_10G:
2491         case ETH_SPEED_NUM_25G:
2492         case ETH_SPEED_NUM_40G:
2493         case ETH_SPEED_NUM_50G:
2494         case ETH_SPEED_NUM_100G:
2495                 new_link.link_speed = mac->link_speed;
2496                 break;
2497         default:
2498                 new_link.link_speed = ETH_SPEED_NUM_100M;
2499                 break;
2500         }
2501
2502         new_link.link_duplex = mac->link_duplex;
2503         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2504         new_link.link_autoneg =
2505             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2506
2507         return rte_eth_linkstatus_set(eth_dev, &new_link);
2508 }
2509
2510 static int
2511 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2512 {
2513         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2514         struct hns3_pf *pf = &hns->pf;
2515
2516         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2517                 return -EINVAL;
2518
2519         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2520
2521         return 0;
2522 }
2523
2524 static int
2525 hns3_query_function_status(struct hns3_hw *hw)
2526 {
2527 #define HNS3_QUERY_MAX_CNT              10
2528 #define HNS3_QUERY_SLEEP_MSCOEND        1
2529         struct hns3_func_status_cmd *req;
2530         struct hns3_cmd_desc desc;
2531         int timeout = 0;
2532         int ret;
2533
2534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2535         req = (struct hns3_func_status_cmd *)desc.data;
2536
2537         do {
2538                 ret = hns3_cmd_send(hw, &desc, 1);
2539                 if (ret) {
2540                         PMD_INIT_LOG(ERR, "query function status failed %d",
2541                                      ret);
2542                         return ret;
2543                 }
2544
2545                 /* Check pf reset is done */
2546                 if (req->pf_state)
2547                         break;
2548
2549                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2550         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2551
2552         return hns3_parse_func_status(hw, req);
2553 }
2554
2555 static int
2556 hns3_query_pf_resource(struct hns3_hw *hw)
2557 {
2558         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2559         struct hns3_pf *pf = &hns->pf;
2560         struct hns3_pf_res_cmd *req;
2561         struct hns3_cmd_desc desc;
2562         uint16_t num_msi;
2563         int ret;
2564
2565         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2566         ret = hns3_cmd_send(hw, &desc, 1);
2567         if (ret) {
2568                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2569                 return ret;
2570         }
2571
2572         req = (struct hns3_pf_res_cmd *)desc.data;
2573         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2574         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2575         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2576         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2577
2578         if (req->tx_buf_size)
2579                 pf->tx_buf_size =
2580                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2581         else
2582                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2583
2584         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2585
2586         if (req->dv_buf_size)
2587                 pf->dv_buf_size =
2588                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2589         else
2590                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2591
2592         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2593
2594         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2595                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2596         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2597
2598         return 0;
2599 }
2600
2601 static void
2602 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2603 {
2604         struct hns3_cfg_param_cmd *req;
2605         uint64_t mac_addr_tmp_high;
2606         uint64_t mac_addr_tmp;
2607         uint32_t i;
2608
2609         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2610
2611         /* get the configuration */
2612         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2613                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2614         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2615                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2616         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2617                                            HNS3_CFG_TQP_DESC_N_M,
2618                                            HNS3_CFG_TQP_DESC_N_S);
2619
2620         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2621                                        HNS3_CFG_PHY_ADDR_M,
2622                                        HNS3_CFG_PHY_ADDR_S);
2623         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2624                                          HNS3_CFG_MEDIA_TP_M,
2625                                          HNS3_CFG_MEDIA_TP_S);
2626         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2627                                          HNS3_CFG_RX_BUF_LEN_M,
2628                                          HNS3_CFG_RX_BUF_LEN_S);
2629         /* get mac address */
2630         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2631         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2632                                            HNS3_CFG_MAC_ADDR_H_M,
2633                                            HNS3_CFG_MAC_ADDR_H_S);
2634
2635         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2636
2637         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2638                                             HNS3_CFG_DEFAULT_SPEED_M,
2639                                             HNS3_CFG_DEFAULT_SPEED_S);
2640         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2641                                            HNS3_CFG_RSS_SIZE_M,
2642                                            HNS3_CFG_RSS_SIZE_S);
2643
2644         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2645                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2646
2647         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2648         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2649
2650         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2651                                             HNS3_CFG_SPEED_ABILITY_M,
2652                                             HNS3_CFG_SPEED_ABILITY_S);
2653         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2654                                         HNS3_CFG_UMV_TBL_SPACE_M,
2655                                         HNS3_CFG_UMV_TBL_SPACE_S);
2656         if (!cfg->umv_space)
2657                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2658 }
2659
2660 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2661  * @hw: pointer to struct hns3_hw
2662  * @hcfg: the config structure to be getted
2663  */
2664 static int
2665 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2666 {
2667         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2668         struct hns3_cfg_param_cmd *req;
2669         uint32_t offset;
2670         uint32_t i;
2671         int ret;
2672
2673         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2674                 offset = 0;
2675                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2676                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2677                                           true);
2678                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2679                                i * HNS3_CFG_RD_LEN_BYTES);
2680                 /* Len should be divided by 4 when send to hardware */
2681                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2682                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2683                 req->offset = rte_cpu_to_le_32(offset);
2684         }
2685
2686         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2687         if (ret) {
2688                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2689                 return ret;
2690         }
2691
2692         hns3_parse_cfg(hcfg, desc);
2693
2694         return 0;
2695 }
2696
2697 static int
2698 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2699 {
2700         switch (speed_cmd) {
2701         case HNS3_CFG_SPEED_10M:
2702                 *speed = ETH_SPEED_NUM_10M;
2703                 break;
2704         case HNS3_CFG_SPEED_100M:
2705                 *speed = ETH_SPEED_NUM_100M;
2706                 break;
2707         case HNS3_CFG_SPEED_1G:
2708                 *speed = ETH_SPEED_NUM_1G;
2709                 break;
2710         case HNS3_CFG_SPEED_10G:
2711                 *speed = ETH_SPEED_NUM_10G;
2712                 break;
2713         case HNS3_CFG_SPEED_25G:
2714                 *speed = ETH_SPEED_NUM_25G;
2715                 break;
2716         case HNS3_CFG_SPEED_40G:
2717                 *speed = ETH_SPEED_NUM_40G;
2718                 break;
2719         case HNS3_CFG_SPEED_50G:
2720                 *speed = ETH_SPEED_NUM_50G;
2721                 break;
2722         case HNS3_CFG_SPEED_100G:
2723                 *speed = ETH_SPEED_NUM_100G;
2724                 break;
2725         default:
2726                 return -EINVAL;
2727         }
2728
2729         return 0;
2730 }
2731
2732 static int
2733 hns3_get_board_configuration(struct hns3_hw *hw)
2734 {
2735         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2736         struct hns3_pf *pf = &hns->pf;
2737         struct hns3_cfg cfg;
2738         int ret;
2739
2740         ret = hns3_get_board_cfg(hw, &cfg);
2741         if (ret) {
2742                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2743                 return ret;
2744         }
2745
2746         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2747                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2748                 return -EOPNOTSUPP;
2749         }
2750
2751         hw->mac.media_type = cfg.media_type;
2752         hw->rss_size_max = cfg.rss_size_max;
2753         hw->rss_dis_flag = false;
2754         hw->rx_buf_len = cfg.rx_buf_len;
2755         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2756         hw->mac.phy_addr = cfg.phy_addr;
2757         hw->mac.default_addr_setted = false;
2758         hw->num_tx_desc = cfg.tqp_desc_num;
2759         hw->num_rx_desc = cfg.tqp_desc_num;
2760         hw->dcb_info.num_pg = 1;
2761         hw->dcb_info.hw_pfc_map = 0;
2762
2763         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2764         if (ret) {
2765                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2766                              cfg.default_speed, ret);
2767                 return ret;
2768         }
2769
2770         pf->tc_max = cfg.tc_num;
2771         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2772                 PMD_INIT_LOG(WARNING,
2773                              "Get TC num(%u) from flash, set TC num to 1",
2774                              pf->tc_max);
2775                 pf->tc_max = 1;
2776         }
2777
2778         /* Dev does not support DCB */
2779         if (!hns3_dev_dcb_supported(hw)) {
2780                 pf->tc_max = 1;
2781                 pf->pfc_max = 0;
2782         } else
2783                 pf->pfc_max = pf->tc_max;
2784
2785         hw->dcb_info.num_tc = 1;
2786         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2787                                      hw->tqps_num / hw->dcb_info.num_tc);
2788         hns3_set_bit(hw->hw_tc_map, 0, 1);
2789         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2790
2791         pf->wanted_umv_size = cfg.umv_space;
2792
2793         return ret;
2794 }
2795
2796 static int
2797 hns3_get_configuration(struct hns3_hw *hw)
2798 {
2799         int ret;
2800
2801         ret = hns3_query_function_status(hw);
2802         if (ret) {
2803                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2804                 return ret;
2805         }
2806
2807         /* Get pf resource */
2808         ret = hns3_query_pf_resource(hw);
2809         if (ret) {
2810                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2811                 return ret;
2812         }
2813
2814         ret = hns3_get_board_configuration(hw);
2815         if (ret)
2816                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2817
2818         return ret;
2819 }
2820
2821 static int
2822 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2823                       uint16_t tqp_vid, bool is_pf)
2824 {
2825         struct hns3_tqp_map_cmd *req;
2826         struct hns3_cmd_desc desc;
2827         int ret;
2828
2829         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2830
2831         req = (struct hns3_tqp_map_cmd *)desc.data;
2832         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2833         req->tqp_vf = func_id;
2834         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2835         if (!is_pf)
2836                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2837         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2838
2839         ret = hns3_cmd_send(hw, &desc, 1);
2840         if (ret)
2841                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2842
2843         return ret;
2844 }
2845
2846 static int
2847 hns3_map_tqp(struct hns3_hw *hw)
2848 {
2849         uint16_t tqps_num = hw->total_tqps_num;
2850         uint16_t func_id;
2851         uint16_t tqp_id;
2852         bool is_pf;
2853         int num;
2854         int ret;
2855         int i;
2856
2857         /*
2858          * In current version VF is not supported when PF is driven by DPDK
2859          * driver, so we allocate tqps to PF as much as possible.
2860          */
2861         tqp_id = 0;
2862         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2863         for (func_id = 0; func_id < num; func_id++) {
2864                 is_pf = func_id == 0 ? true : false;
2865                 for (i = 0;
2866                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2867                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2868                                                     is_pf);
2869                         if (ret)
2870                                 return ret;
2871                 }
2872         }
2873
2874         return 0;
2875 }
2876
2877 static int
2878 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2879 {
2880         struct hns3_config_mac_speed_dup_cmd *req;
2881         struct hns3_cmd_desc desc;
2882         int ret;
2883
2884         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2885
2886         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2887
2888         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2889
2890         switch (speed) {
2891         case ETH_SPEED_NUM_10M:
2892                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2893                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2894                 break;
2895         case ETH_SPEED_NUM_100M:
2896                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2897                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2898                 break;
2899         case ETH_SPEED_NUM_1G:
2900                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2901                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2902                 break;
2903         case ETH_SPEED_NUM_10G:
2904                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2905                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2906                 break;
2907         case ETH_SPEED_NUM_25G:
2908                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2909                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2910                 break;
2911         case ETH_SPEED_NUM_40G:
2912                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2913                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2914                 break;
2915         case ETH_SPEED_NUM_50G:
2916                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2917                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2918                 break;
2919         case ETH_SPEED_NUM_100G:
2920                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2921                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2922                 break;
2923         default:
2924                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2925                 return -EINVAL;
2926         }
2927
2928         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2929
2930         ret = hns3_cmd_send(hw, &desc, 1);
2931         if (ret)
2932                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2933
2934         return ret;
2935 }
2936
2937 static int
2938 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2939 {
2940         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2941         struct hns3_pf *pf = &hns->pf;
2942         struct hns3_priv_buf *priv;
2943         uint32_t i, total_size;
2944
2945         total_size = pf->pkt_buf_size;
2946
2947         /* alloc tx buffer for all enabled tc */
2948         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2949                 priv = &buf_alloc->priv_buf[i];
2950
2951                 if (hw->hw_tc_map & BIT(i)) {
2952                         if (total_size < pf->tx_buf_size)
2953                                 return -ENOMEM;
2954
2955                         priv->tx_buf_size = pf->tx_buf_size;
2956                 } else
2957                         priv->tx_buf_size = 0;
2958
2959                 total_size -= priv->tx_buf_size;
2960         }
2961
2962         return 0;
2963 }
2964
2965 static int
2966 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2967 {
2968 /* TX buffer size is unit by 128 byte */
2969 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2970 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2971         struct hns3_tx_buff_alloc_cmd *req;
2972         struct hns3_cmd_desc desc;
2973         uint32_t buf_size;
2974         uint32_t i;
2975         int ret;
2976
2977         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2978
2979         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2980         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2981                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2982
2983                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2984                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2985                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2986         }
2987
2988         ret = hns3_cmd_send(hw, &desc, 1);
2989         if (ret)
2990                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2991
2992         return ret;
2993 }
2994
2995 static int
2996 hns3_get_tc_num(struct hns3_hw *hw)
2997 {
2998         int cnt = 0;
2999         uint8_t i;
3000
3001         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3002                 if (hw->hw_tc_map & BIT(i))
3003                         cnt++;
3004         return cnt;
3005 }
3006
3007 static uint32_t
3008 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3009 {
3010         struct hns3_priv_buf *priv;
3011         uint32_t rx_priv = 0;
3012         int i;
3013
3014         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3015                 priv = &buf_alloc->priv_buf[i];
3016                 if (priv->enable)
3017                         rx_priv += priv->buf_size;
3018         }
3019         return rx_priv;
3020 }
3021
3022 static uint32_t
3023 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3024 {
3025         uint32_t total_tx_size = 0;
3026         uint32_t i;
3027
3028         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3029                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3030
3031         return total_tx_size;
3032 }
3033
3034 /* Get the number of pfc enabled TCs, which have private buffer */
3035 static int
3036 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3037 {
3038         struct hns3_priv_buf *priv;
3039         int cnt = 0;
3040         uint8_t i;
3041
3042         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3043                 priv = &buf_alloc->priv_buf[i];
3044                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3045                         cnt++;
3046         }
3047
3048         return cnt;
3049 }
3050
3051 /* Get the number of pfc disabled TCs, which have private buffer */
3052 static int
3053 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3054                          struct hns3_pkt_buf_alloc *buf_alloc)
3055 {
3056         struct hns3_priv_buf *priv;
3057         int cnt = 0;
3058         uint8_t i;
3059
3060         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3061                 priv = &buf_alloc->priv_buf[i];
3062                 if (hw->hw_tc_map & BIT(i) &&
3063                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3064                         cnt++;
3065         }
3066
3067         return cnt;
3068 }
3069
3070 static bool
3071 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3072                   uint32_t rx_all)
3073 {
3074         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3075         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3076         struct hns3_pf *pf = &hns->pf;
3077         uint32_t shared_buf, aligned_mps;
3078         uint32_t rx_priv;
3079         uint8_t tc_num;
3080         uint8_t i;
3081
3082         tc_num = hns3_get_tc_num(hw);
3083         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3084
3085         if (hns3_dev_dcb_supported(hw))
3086                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3087                                         pf->dv_buf_size;
3088         else
3089                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3090                                         + pf->dv_buf_size;
3091
3092         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3093         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3094                              HNS3_BUF_SIZE_UNIT);
3095
3096         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3097         if (rx_all < rx_priv + shared_std)
3098                 return false;
3099
3100         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3101         buf_alloc->s_buf.buf_size = shared_buf;
3102         if (hns3_dev_dcb_supported(hw)) {
3103                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3104                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3105                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3106                                   HNS3_BUF_SIZE_UNIT);
3107         } else {
3108                 buf_alloc->s_buf.self.high =
3109                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3110                 buf_alloc->s_buf.self.low = aligned_mps;
3111         }
3112
3113         if (hns3_dev_dcb_supported(hw)) {
3114                 hi_thrd = shared_buf - pf->dv_buf_size;
3115
3116                 if (tc_num <= NEED_RESERVE_TC_NUM)
3117                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3118                                         / BUF_MAX_PERCENT;
3119
3120                 if (tc_num)
3121                         hi_thrd = hi_thrd / tc_num;
3122
3123                 hi_thrd = max_t(uint32_t, hi_thrd,
3124                                 HNS3_BUF_MUL_BY * aligned_mps);
3125                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3126                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3127         } else {
3128                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3129                 lo_thrd = aligned_mps;
3130         }
3131
3132         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3133                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3134                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3135         }
3136
3137         return true;
3138 }
3139
3140 static bool
3141 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3142                      struct hns3_pkt_buf_alloc *buf_alloc)
3143 {
3144         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3145         struct hns3_pf *pf = &hns->pf;
3146         struct hns3_priv_buf *priv;
3147         uint32_t aligned_mps;
3148         uint32_t rx_all;
3149         uint8_t i;
3150
3151         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3152         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3153
3154         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3155                 priv = &buf_alloc->priv_buf[i];
3156
3157                 priv->enable = 0;
3158                 priv->wl.low = 0;
3159                 priv->wl.high = 0;
3160                 priv->buf_size = 0;
3161
3162                 if (!(hw->hw_tc_map & BIT(i)))
3163                         continue;
3164
3165                 priv->enable = 1;
3166                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3167                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3168                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3169                                                 HNS3_BUF_SIZE_UNIT);
3170                 } else {
3171                         priv->wl.low = 0;
3172                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3173                                         aligned_mps;
3174                 }
3175
3176                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3177         }
3178
3179         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3180 }
3181
3182 static bool
3183 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3184                              struct hns3_pkt_buf_alloc *buf_alloc)
3185 {
3186         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3187         struct hns3_pf *pf = &hns->pf;
3188         struct hns3_priv_buf *priv;
3189         int no_pfc_priv_num;
3190         uint32_t rx_all;
3191         uint8_t mask;
3192         int i;
3193
3194         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3195         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3196
3197         /* let the last to be cleared first */
3198         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3199                 priv = &buf_alloc->priv_buf[i];
3200                 mask = BIT((uint8_t)i);
3201
3202                 if (hw->hw_tc_map & mask &&
3203                     !(hw->dcb_info.hw_pfc_map & mask)) {
3204                         /* Clear the no pfc TC private buffer */
3205                         priv->wl.low = 0;
3206                         priv->wl.high = 0;
3207                         priv->buf_size = 0;
3208                         priv->enable = 0;
3209                         no_pfc_priv_num--;
3210                 }
3211
3212                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3213                     no_pfc_priv_num == 0)
3214                         break;
3215         }
3216
3217         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3218 }
3219
3220 static bool
3221 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3222                            struct hns3_pkt_buf_alloc *buf_alloc)
3223 {
3224         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3225         struct hns3_pf *pf = &hns->pf;
3226         struct hns3_priv_buf *priv;
3227         uint32_t rx_all;
3228         int pfc_priv_num;
3229         uint8_t mask;
3230         int i;
3231
3232         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3233         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3234
3235         /* let the last to be cleared first */
3236         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3237                 priv = &buf_alloc->priv_buf[i];
3238                 mask = BIT((uint8_t)i);
3239
3240                 if (hw->hw_tc_map & mask &&
3241                     hw->dcb_info.hw_pfc_map & mask) {
3242                         /* Reduce the number of pfc TC with private buffer */
3243                         priv->wl.low = 0;
3244                         priv->enable = 0;
3245                         priv->wl.high = 0;
3246                         priv->buf_size = 0;
3247                         pfc_priv_num--;
3248                 }
3249                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3250                     pfc_priv_num == 0)
3251                         break;
3252         }
3253
3254         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3255 }
3256
3257 static bool
3258 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3259                           struct hns3_pkt_buf_alloc *buf_alloc)
3260 {
3261 #define COMPENSATE_BUFFER       0x3C00
3262 #define COMPENSATE_HALF_MPS_NUM 5
3263 #define PRIV_WL_GAP             0x1800
3264         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3265         struct hns3_pf *pf = &hns->pf;
3266         uint32_t tc_num = hns3_get_tc_num(hw);
3267         uint32_t half_mps = pf->mps >> 1;
3268         struct hns3_priv_buf *priv;
3269         uint32_t min_rx_priv;
3270         uint32_t rx_priv;
3271         uint8_t i;
3272
3273         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3274         if (tc_num)
3275                 rx_priv = rx_priv / tc_num;
3276
3277         if (tc_num <= NEED_RESERVE_TC_NUM)
3278                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3279
3280         /*
3281          * Minimum value of private buffer in rx direction (min_rx_priv) is
3282          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3283          * buffer if rx_priv is greater than min_rx_priv.
3284          */
3285         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3286                         COMPENSATE_HALF_MPS_NUM * half_mps;
3287         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3288         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3289
3290         if (rx_priv < min_rx_priv)
3291                 return false;
3292
3293         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3294                 priv = &buf_alloc->priv_buf[i];
3295
3296                 priv->enable = 0;
3297                 priv->wl.low = 0;
3298                 priv->wl.high = 0;
3299                 priv->buf_size = 0;
3300
3301                 if (!(hw->hw_tc_map & BIT(i)))
3302                         continue;
3303
3304                 priv->enable = 1;
3305                 priv->buf_size = rx_priv;
3306                 priv->wl.high = rx_priv - pf->dv_buf_size;
3307                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3308         }
3309
3310         buf_alloc->s_buf.buf_size = 0;
3311
3312         return true;
3313 }
3314
3315 /*
3316  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3317  * @hw: pointer to struct hns3_hw
3318  * @buf_alloc: pointer to buffer calculation data
3319  * @return: 0: calculate sucessful, negative: fail
3320  */
3321 static int
3322 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3323 {
3324         /* When DCB is not supported, rx private buffer is not allocated. */
3325         if (!hns3_dev_dcb_supported(hw)) {
3326                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3327                 struct hns3_pf *pf = &hns->pf;
3328                 uint32_t rx_all = pf->pkt_buf_size;
3329
3330                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3331                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3332                         return -ENOMEM;
3333
3334                 return 0;
3335         }
3336
3337         /*
3338          * Try to allocate privated packet buffer for all TCs without share
3339          * buffer.
3340          */
3341         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3342                 return 0;
3343
3344         /*
3345          * Try to allocate privated packet buffer for all TCs with share
3346          * buffer.
3347          */
3348         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3349                 return 0;
3350
3351         /*
3352          * For different application scenes, the enabled port number, TC number
3353          * and no_drop TC number are different. In order to obtain the better
3354          * performance, software could allocate the buffer size and configure
3355          * the waterline by tring to decrease the private buffer size according
3356          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3357          * enabled tc.
3358          */
3359         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3360                 return 0;
3361
3362         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3363                 return 0;
3364
3365         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3366                 return 0;
3367
3368         return -ENOMEM;
3369 }
3370
3371 static int
3372 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3373 {
3374         struct hns3_rx_priv_buff_cmd *req;
3375         struct hns3_cmd_desc desc;
3376         uint32_t buf_size;
3377         int ret;
3378         int i;
3379
3380         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3381         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3382
3383         /* Alloc private buffer TCs */
3384         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3385                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3386
3387                 req->buf_num[i] =
3388                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3389                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3390         }
3391
3392         buf_size = buf_alloc->s_buf.buf_size;
3393         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3394                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3395
3396         ret = hns3_cmd_send(hw, &desc, 1);
3397         if (ret)
3398                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3399
3400         return ret;
3401 }
3402
3403 static int
3404 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3405 {
3406 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3407         struct hns3_rx_priv_wl_buf *req;
3408         struct hns3_priv_buf *priv;
3409         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3410         int i, j;
3411         int ret;
3412
3413         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3414                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3415                                           false);
3416                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3417
3418                 /* The first descriptor set the NEXT bit to 1 */
3419                 if (i == 0)
3420                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3421                 else
3422                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3423
3424                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3425                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3426
3427                         priv = &buf_alloc->priv_buf[idx];
3428                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3429                                                         HNS3_BUF_UNIT_S);
3430                         req->tc_wl[j].high |=
3431                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3432                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3433                                                         HNS3_BUF_UNIT_S);
3434                         req->tc_wl[j].low |=
3435                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3436                 }
3437         }
3438
3439         /* Send 2 descriptor at one time */
3440         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3441         if (ret)
3442                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3443                              ret);
3444         return ret;
3445 }
3446
3447 static int
3448 hns3_common_thrd_config(struct hns3_hw *hw,
3449                         struct hns3_pkt_buf_alloc *buf_alloc)
3450 {
3451 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3452         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3453         struct hns3_rx_com_thrd *req;
3454         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3455         struct hns3_tc_thrd *tc;
3456         int tc_idx;
3457         int i, j;
3458         int ret;
3459
3460         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3461                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3462                                           false);
3463                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3464
3465                 /* The first descriptor set the NEXT bit to 1 */
3466                 if (i == 0)
3467                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3468                 else
3469                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3470
3471                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3472                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3473                         tc = &s_buf->tc_thrd[tc_idx];
3474
3475                         req->com_thrd[j].high =
3476                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3477                         req->com_thrd[j].high |=
3478                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3479                         req->com_thrd[j].low =
3480                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3481                         req->com_thrd[j].low |=
3482                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3483                 }
3484         }
3485
3486         /* Send 2 descriptors at one time */
3487         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3488         if (ret)
3489                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3490
3491         return ret;
3492 }
3493
3494 static int
3495 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3496 {
3497         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3498         struct hns3_rx_com_wl *req;
3499         struct hns3_cmd_desc desc;
3500         int ret;
3501
3502         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3503
3504         req = (struct hns3_rx_com_wl *)desc.data;
3505         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3506         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3507
3508         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3509         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3510
3511         ret = hns3_cmd_send(hw, &desc, 1);
3512         if (ret)
3513                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3514
3515         return ret;
3516 }
3517
3518 int
3519 hns3_buffer_alloc(struct hns3_hw *hw)
3520 {
3521         struct hns3_pkt_buf_alloc pkt_buf;
3522         int ret;
3523
3524         memset(&pkt_buf, 0, sizeof(pkt_buf));
3525         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3526         if (ret) {
3527                 PMD_INIT_LOG(ERR,
3528                              "could not calc tx buffer size for all TCs %d",
3529                              ret);
3530                 return ret;
3531         }
3532
3533         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3534         if (ret) {
3535                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3536                 return ret;
3537         }
3538
3539         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3540         if (ret) {
3541                 PMD_INIT_LOG(ERR,
3542                              "could not calc rx priv buffer size for all TCs %d",
3543                              ret);
3544                 return ret;
3545         }
3546
3547         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3548         if (ret) {
3549                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3550                 return ret;
3551         }
3552
3553         if (hns3_dev_dcb_supported(hw)) {
3554                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3555                 if (ret) {
3556                         PMD_INIT_LOG(ERR,
3557                                      "could not configure rx private waterline %d",
3558                                      ret);
3559                         return ret;
3560                 }
3561
3562                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3563                 if (ret) {
3564                         PMD_INIT_LOG(ERR,
3565                                      "could not configure common threshold %d",
3566                                      ret);
3567                         return ret;
3568                 }
3569         }
3570
3571         ret = hns3_common_wl_config(hw, &pkt_buf);
3572         if (ret)
3573                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3574                              ret);
3575
3576         return ret;
3577 }
3578
3579 static int
3580 hns3_mac_init(struct hns3_hw *hw)
3581 {
3582         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3583         struct hns3_mac *mac = &hw->mac;
3584         struct hns3_pf *pf = &hns->pf;
3585         int ret;
3586
3587         pf->support_sfp_query = true;
3588         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3589         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3590         if (ret) {
3591                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3592                 return ret;
3593         }
3594
3595         mac->link_status = ETH_LINK_DOWN;
3596
3597         return hns3_config_mtu(hw, pf->mps);
3598 }
3599
3600 static int
3601 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3602 {
3603 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3604 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3605 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3606 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3607         int return_status;
3608
3609         if (cmdq_resp) {
3610                 PMD_INIT_LOG(ERR,
3611                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3612                              cmdq_resp);
3613                 return -EIO;
3614         }
3615
3616         switch (resp_code) {
3617         case HNS3_ETHERTYPE_SUCCESS_ADD:
3618         case HNS3_ETHERTYPE_ALREADY_ADD:
3619                 return_status = 0;
3620                 break;
3621         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3622                 PMD_INIT_LOG(ERR,
3623                              "add mac ethertype failed for manager table overflow.");
3624                 return_status = -EIO;
3625                 break;
3626         case HNS3_ETHERTYPE_KEY_CONFLICT:
3627                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3628                 return_status = -EIO;
3629                 break;
3630         default:
3631                 PMD_INIT_LOG(ERR,
3632                              "add mac ethertype failed for undefined, code=%d.",
3633                              resp_code);
3634                 return_status = -EIO;
3635                 break;
3636         }
3637
3638         return return_status;
3639 }
3640
3641 static int
3642 hns3_add_mgr_tbl(struct hns3_hw *hw,
3643                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3644 {
3645         struct hns3_cmd_desc desc;
3646         uint8_t resp_code;
3647         uint16_t retval;
3648         int ret;
3649
3650         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3651         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3652
3653         ret = hns3_cmd_send(hw, &desc, 1);
3654         if (ret) {
3655                 PMD_INIT_LOG(ERR,
3656                              "add mac ethertype failed for cmd_send, ret =%d.",
3657                              ret);
3658                 return ret;
3659         }
3660
3661         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3662         retval = rte_le_to_cpu_16(desc.retval);
3663
3664         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3665 }
3666
3667 static void
3668 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3669                      int *table_item_num)
3670 {
3671         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3672
3673         /*
3674          * In current version, we add one item in management table as below:
3675          * 0x0180C200000E -- LLDP MC address
3676          */
3677         tbl = mgr_table;
3678         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3679         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3680         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3681         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3682         tbl->i_port_bitmap = 0x1;
3683         *table_item_num = 1;
3684 }
3685
3686 static int
3687 hns3_init_mgr_tbl(struct hns3_hw *hw)
3688 {
3689 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3690         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3691         int table_item_num;
3692         int ret;
3693         int i;
3694
3695         memset(mgr_table, 0, sizeof(mgr_table));
3696         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3697         for (i = 0; i < table_item_num; i++) {
3698                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3699                 if (ret) {
3700                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3701                                      ret);
3702                         return ret;
3703                 }
3704         }
3705
3706         return 0;
3707 }
3708
3709 static void
3710 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3711                         bool en_mc, bool en_bc, int vport_id)
3712 {
3713         if (!param)
3714                 return;
3715
3716         memset(param, 0, sizeof(struct hns3_promisc_param));
3717         if (en_uc)
3718                 param->enable = HNS3_PROMISC_EN_UC;
3719         if (en_mc)
3720                 param->enable |= HNS3_PROMISC_EN_MC;
3721         if (en_bc)
3722                 param->enable |= HNS3_PROMISC_EN_BC;
3723         param->vf_id = vport_id;
3724 }
3725
3726 static int
3727 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3728 {
3729         struct hns3_promisc_cfg_cmd *req;
3730         struct hns3_cmd_desc desc;
3731         int ret;
3732
3733         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3734
3735         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3736         req->vf_id = param->vf_id;
3737         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3738             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3739
3740         ret = hns3_cmd_send(hw, &desc, 1);
3741         if (ret)
3742                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3743
3744         return ret;
3745 }
3746
3747 static int
3748 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3749 {
3750         struct hns3_promisc_param param;
3751         bool en_bc_pmc = true;
3752         uint8_t vf_id;
3753
3754         /*
3755          * In current version VF is not supported when PF is driven by DPDK
3756          * driver, the PF-related vf_id is 0, just need to configure parameters
3757          * for vf_id 0.
3758          */
3759         vf_id = 0;
3760
3761         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3762         return hns3_cmd_set_promisc_mode(hw, &param);
3763 }
3764
3765 static int
3766 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3767 {
3768         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3769         struct hns3_pf *pf = &hns->pf;
3770         struct hns3_promisc_param param;
3771         uint16_t func_id;
3772         int ret;
3773
3774         /* func_id 0 is denoted PF, the VFs start from 1 */
3775         for (func_id = 1; func_id < pf->func_num; func_id++) {
3776                 hns3_promisc_param_init(&param, false, false, false, func_id);
3777                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3778                 if (ret)
3779                         return ret;
3780         }
3781
3782         return 0;
3783 }
3784
3785 static int
3786 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3787 {
3788         struct hns3_adapter *hns = dev->data->dev_private;
3789         struct hns3_hw *hw = &hns->hw;
3790         int ret;
3791
3792         rte_spinlock_lock(&hw->lock);
3793         ret = hns3_set_promisc_mode(hw, true, true);
3794         rte_spinlock_unlock(&hw->lock);
3795         if (ret)
3796                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3797                          ret);
3798
3799         return ret;
3800 }
3801
3802 static int
3803 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3804 {
3805         bool allmulti = dev->data->all_multicast ? true : false;
3806         struct hns3_adapter *hns = dev->data->dev_private;
3807         struct hns3_hw *hw = &hns->hw;
3808         int ret;
3809
3810         /* If now in all_multicast mode, must remain in all_multicast mode. */
3811         rte_spinlock_lock(&hw->lock);
3812         ret = hns3_set_promisc_mode(hw, false, allmulti);
3813         rte_spinlock_unlock(&hw->lock);
3814         if (ret)
3815                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3816                          ret);
3817
3818         return ret;
3819 }
3820
3821 static int
3822 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3823 {
3824         struct hns3_adapter *hns = dev->data->dev_private;
3825         struct hns3_hw *hw = &hns->hw;
3826         int ret;
3827
3828         if (dev->data->promiscuous)
3829                 return 0;
3830
3831         rte_spinlock_lock(&hw->lock);
3832         ret = hns3_set_promisc_mode(hw, false, true);
3833         rte_spinlock_unlock(&hw->lock);
3834         if (ret)
3835                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3836                          ret);
3837
3838         return ret;
3839 }
3840
3841 static int
3842 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3843 {
3844         struct hns3_adapter *hns = dev->data->dev_private;
3845         struct hns3_hw *hw = &hns->hw;
3846         int ret;
3847
3848         /* If now in promiscuous mode, must remain in all_multicast mode. */
3849         if (dev->data->promiscuous)
3850                 return 0;
3851
3852         rte_spinlock_lock(&hw->lock);
3853         ret = hns3_set_promisc_mode(hw, false, false);
3854         rte_spinlock_unlock(&hw->lock);
3855         if (ret)
3856                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3857                          ret);
3858
3859         return ret;
3860 }
3861
3862 static int
3863 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3864 {
3865         struct hns3_hw *hw = &hns->hw;
3866         bool allmulti = hw->data->all_multicast ? true : false;
3867
3868         if (hw->data->promiscuous)
3869                 return hns3_set_promisc_mode(hw, true, true);
3870
3871         return hns3_set_promisc_mode(hw, false, allmulti);
3872 }
3873
3874 static int
3875 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3876 {
3877         struct hns3_sfp_speed_cmd *resp;
3878         struct hns3_cmd_desc desc;
3879         int ret;
3880
3881         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3882         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3883         ret = hns3_cmd_send(hw, &desc, 1);
3884         if (ret == -EOPNOTSUPP) {
3885                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3886                 return ret;
3887         } else if (ret) {
3888                 hns3_err(hw, "get sfp speed failed %d", ret);
3889                 return ret;
3890         }
3891
3892         *speed = resp->sfp_speed;
3893
3894         return 0;
3895 }
3896
3897 static uint8_t
3898 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3899 {
3900         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3901                 duplex = ETH_LINK_FULL_DUPLEX;
3902
3903         return duplex;
3904 }
3905
3906 static int
3907 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3908 {
3909         struct hns3_mac *mac = &hw->mac;
3910         int ret;
3911
3912         duplex = hns3_check_speed_dup(duplex, speed);
3913         if (mac->link_speed == speed && mac->link_duplex == duplex)
3914                 return 0;
3915
3916         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3917         if (ret)
3918                 return ret;
3919
3920         mac->link_speed = speed;
3921         mac->link_duplex = duplex;
3922
3923         return 0;
3924 }
3925
3926 static int
3927 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3928 {
3929         struct hns3_adapter *hns = eth_dev->data->dev_private;
3930         struct hns3_hw *hw = &hns->hw;
3931         struct hns3_pf *pf = &hns->pf;
3932         uint32_t speed;
3933         int ret;
3934
3935         /* If IMP do not support get SFP/qSFP speed, return directly */
3936         if (!pf->support_sfp_query)
3937                 return 0;
3938
3939         ret = hns3_get_sfp_speed(hw, &speed);
3940         if (ret == -EOPNOTSUPP) {
3941                 pf->support_sfp_query = false;
3942                 return ret;
3943         } else if (ret)
3944                 return ret;
3945
3946         if (speed == ETH_SPEED_NUM_NONE)
3947                 return 0; /* do nothing if no SFP */
3948
3949         /* Config full duplex for SFP */
3950         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3951 }
3952
3953 static int
3954 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3955 {
3956         struct hns3_config_mac_mode_cmd *req;
3957         struct hns3_cmd_desc desc;
3958         uint32_t loop_en = 0;
3959         uint8_t val = 0;
3960         int ret;
3961
3962         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3963
3964         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3965         if (enable)
3966                 val = 1;
3967         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3968         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3969         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3970         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3971         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3972         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3973         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3974         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3975         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3976         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3977         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3978         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3979         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3980         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3981         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3982
3983         ret = hns3_cmd_send(hw, &desc, 1);
3984         if (ret)
3985                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3986
3987         return ret;
3988 }
3989
3990 static int
3991 hns3_get_mac_link_status(struct hns3_hw *hw)
3992 {
3993         struct hns3_link_status_cmd *req;
3994         struct hns3_cmd_desc desc;
3995         int link_status;
3996         int ret;
3997
3998         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3999         ret = hns3_cmd_send(hw, &desc, 1);
4000         if (ret) {
4001                 hns3_err(hw, "get link status cmd failed %d", ret);
4002                 return ETH_LINK_DOWN;
4003         }
4004
4005         req = (struct hns3_link_status_cmd *)desc.data;
4006         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4007
4008         return !!link_status;
4009 }
4010
4011 void
4012 hns3_update_link_status(struct hns3_hw *hw)
4013 {
4014         int state;
4015
4016         state = hns3_get_mac_link_status(hw);
4017         if (state != hw->mac.link_status) {
4018                 hw->mac.link_status = state;
4019                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4020         }
4021 }
4022
4023 static void
4024 hns3_service_handler(void *param)
4025 {
4026         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4027         struct hns3_adapter *hns = eth_dev->data->dev_private;
4028         struct hns3_hw *hw = &hns->hw;
4029
4030         if (!hns3_is_reset_pending(hns)) {
4031                 hns3_update_speed_duplex(eth_dev);
4032                 hns3_update_link_status(hw);
4033         } else
4034                 hns3_warn(hw, "Cancel the query when reset is pending");
4035
4036         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4037 }
4038
4039 static int
4040 hns3_init_hardware(struct hns3_adapter *hns)
4041 {
4042         struct hns3_hw *hw = &hns->hw;
4043         int ret;
4044
4045         ret = hns3_map_tqp(hw);
4046         if (ret) {
4047                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4048                 return ret;
4049         }
4050
4051         ret = hns3_init_umv_space(hw);
4052         if (ret) {
4053                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4054                 return ret;
4055         }
4056
4057         ret = hns3_mac_init(hw);
4058         if (ret) {
4059                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4060                 goto err_mac_init;
4061         }
4062
4063         ret = hns3_init_mgr_tbl(hw);
4064         if (ret) {
4065                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4066                 goto err_mac_init;
4067         }
4068
4069         ret = hns3_set_promisc_mode(hw, false, false);
4070         if (ret) {
4071                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4072                 goto err_mac_init;
4073         }
4074
4075         ret = hns3_clear_all_vfs_promisc_mode(hw);
4076         if (ret) {
4077                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4078                              ret);
4079                 goto err_mac_init;
4080         }
4081
4082         ret = hns3_init_vlan_config(hns);
4083         if (ret) {
4084                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4085                 goto err_mac_init;
4086         }
4087
4088         ret = hns3_dcb_init(hw);
4089         if (ret) {
4090                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4091                 goto err_mac_init;
4092         }
4093
4094         ret = hns3_init_fd_config(hns);
4095         if (ret) {
4096                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4097                 goto err_mac_init;
4098         }
4099
4100         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4101         if (ret) {
4102                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4103                 goto err_mac_init;
4104         }
4105
4106         ret = hns3_config_gro(hw, false);
4107         if (ret) {
4108                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4109                 goto err_mac_init;
4110         }
4111
4112         /*
4113          * In the initialization clearing the all hardware mapping relationship
4114          * configurations between queues and interrupt vectors is needed, so
4115          * some error caused by the residual configurations, such as the
4116          * unexpected interrupt, can be avoid.
4117          */
4118         ret = hns3_init_ring_with_vector(hw);
4119         if (ret) {
4120                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4121                 goto err_mac_init;
4122         }
4123
4124         return 0;
4125
4126 err_mac_init:
4127         hns3_uninit_umv_space(hw);
4128         return ret;
4129 }
4130
4131 static int
4132 hns3_init_pf(struct rte_eth_dev *eth_dev)
4133 {
4134         struct rte_device *dev = eth_dev->device;
4135         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4136         struct hns3_adapter *hns = eth_dev->data->dev_private;
4137         struct hns3_hw *hw = &hns->hw;
4138         int ret;
4139
4140         PMD_INIT_FUNC_TRACE();
4141
4142         /* Get hardware io base address from pcie BAR2 IO space */
4143         hw->io_base = pci_dev->mem_resource[2].addr;
4144
4145         /* Firmware command queue initialize */
4146         ret = hns3_cmd_init_queue(hw);
4147         if (ret) {
4148                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4149                 goto err_cmd_init_queue;
4150         }
4151
4152         hns3_clear_all_event_cause(hw);
4153
4154         /* Firmware command initialize */
4155         ret = hns3_cmd_init(hw);
4156         if (ret) {
4157                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4158                 goto err_cmd_init;
4159         }
4160
4161         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4162                                          hns3_interrupt_handler,
4163                                          eth_dev);
4164         if (ret) {
4165                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4166                 goto err_intr_callback_register;
4167         }
4168
4169         /* Enable interrupt */
4170         rte_intr_enable(&pci_dev->intr_handle);
4171         hns3_pf_enable_irq0(hw);
4172
4173         /* Get configuration */
4174         ret = hns3_get_configuration(hw);
4175         if (ret) {
4176                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4177                 goto err_get_config;
4178         }
4179
4180         ret = hns3_init_hardware(hns);
4181         if (ret) {
4182                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4183                 goto err_get_config;
4184         }
4185
4186         /* Initialize flow director filter list & hash */
4187         ret = hns3_fdir_filter_init(hns);
4188         if (ret) {
4189                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4190                 goto err_hw_init;
4191         }
4192
4193         hns3_set_default_rss_args(hw);
4194
4195         ret = hns3_enable_hw_error_intr(hns, true);
4196         if (ret) {
4197                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4198                              ret);
4199                 goto err_fdir;
4200         }
4201
4202         return 0;
4203
4204 err_fdir:
4205         hns3_fdir_filter_uninit(hns);
4206 err_hw_init:
4207         hns3_uninit_umv_space(hw);
4208
4209 err_get_config:
4210         hns3_pf_disable_irq0(hw);
4211         rte_intr_disable(&pci_dev->intr_handle);
4212         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4213                              eth_dev);
4214 err_intr_callback_register:
4215 err_cmd_init:
4216         hns3_cmd_uninit(hw);
4217         hns3_cmd_destroy_queue(hw);
4218 err_cmd_init_queue:
4219         hw->io_base = NULL;
4220
4221         return ret;
4222 }
4223
4224 static void
4225 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4226 {
4227         struct hns3_adapter *hns = eth_dev->data->dev_private;
4228         struct rte_device *dev = eth_dev->device;
4229         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4230         struct hns3_hw *hw = &hns->hw;
4231
4232         PMD_INIT_FUNC_TRACE();
4233
4234         hns3_enable_hw_error_intr(hns, false);
4235         hns3_rss_uninit(hns);
4236         hns3_fdir_filter_uninit(hns);
4237         hns3_uninit_umv_space(hw);
4238         hns3_pf_disable_irq0(hw);
4239         rte_intr_disable(&pci_dev->intr_handle);
4240         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4241                              eth_dev);
4242         hns3_cmd_uninit(hw);
4243         hns3_cmd_destroy_queue(hw);
4244         hw->io_base = NULL;
4245 }
4246
4247 static int
4248 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4249 {
4250         struct hns3_hw *hw = &hns->hw;
4251         int ret;
4252
4253         ret = hns3_dcb_cfg_update(hns);
4254         if (ret)
4255                 return ret;
4256
4257         /* Enable queues */
4258         ret = hns3_start_queues(hns, reset_queue);
4259         if (ret) {
4260                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4261                 return ret;
4262         }
4263
4264         /* Enable MAC */
4265         ret = hns3_cfg_mac_mode(hw, true);
4266         if (ret) {
4267                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4268                 goto err_config_mac_mode;
4269         }
4270         return 0;
4271
4272 err_config_mac_mode:
4273         hns3_stop_queues(hns, true);
4274         return ret;
4275 }
4276
4277 static int
4278 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4279 {
4280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4282         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4283         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4284         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4285         uint32_t intr_vector;
4286         uint16_t q_id;
4287         int ret;
4288
4289         if (dev->data->dev_conf.intr_conf.rxq == 0)
4290                 return 0;
4291
4292         /* disable uio/vfio intr/eventfd mapping */
4293         rte_intr_disable(intr_handle);
4294
4295         /* check and configure queue intr-vector mapping */
4296         if (rte_intr_cap_multiple(intr_handle) ||
4297             !RTE_ETH_DEV_SRIOV(dev).active) {
4298                 intr_vector = hw->used_rx_queues;
4299                 /* creates event fd for each intr vector when MSIX is used */
4300                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4301                         return -EINVAL;
4302         }
4303         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4304                 intr_handle->intr_vec =
4305                         rte_zmalloc("intr_vec",
4306                                     hw->used_rx_queues * sizeof(int), 0);
4307                 if (intr_handle->intr_vec == NULL) {
4308                         hns3_err(hw, "Failed to allocate %d rx_queues"
4309                                      " intr_vec", hw->used_rx_queues);
4310                         ret = -ENOMEM;
4311                         goto alloc_intr_vec_error;
4312                 }
4313         }
4314
4315         if (rte_intr_allow_others(intr_handle)) {
4316                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4317                 base = RTE_INTR_VEC_RXTX_OFFSET;
4318         }
4319         if (rte_intr_dp_is_en(intr_handle)) {
4320                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4321                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4322                                                          HNS3_RING_TYPE_RX,
4323                                                          q_id);
4324                         if (ret)
4325                                 goto bind_vector_error;
4326                         intr_handle->intr_vec[q_id] = vec;
4327                         if (vec < base + intr_handle->nb_efd - 1)
4328                                 vec++;
4329                 }
4330         }
4331         rte_intr_enable(intr_handle);
4332         return 0;
4333
4334 bind_vector_error:
4335         rte_intr_efd_disable(intr_handle);
4336         if (intr_handle->intr_vec) {
4337                 free(intr_handle->intr_vec);
4338                 intr_handle->intr_vec = NULL;
4339         }
4340         return ret;
4341 alloc_intr_vec_error:
4342         rte_intr_efd_disable(intr_handle);
4343         return ret;
4344 }
4345
4346 static int
4347 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4348 {
4349         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4350         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4351         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4352         uint16_t q_id;
4353         int ret;
4354
4355         if (dev->data->dev_conf.intr_conf.rxq == 0)
4356                 return 0;
4357
4358         if (rte_intr_dp_is_en(intr_handle)) {
4359                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4360                         ret = hns3_bind_ring_with_vector(hw,
4361                                         intr_handle->intr_vec[q_id], true,
4362                                         HNS3_RING_TYPE_RX, q_id);
4363                         if (ret)
4364                                 return ret;
4365                 }
4366         }
4367
4368         return 0;
4369 }
4370
4371 static void
4372 hns3_restore_filter(struct rte_eth_dev *dev)
4373 {
4374         hns3_restore_rss_filter(dev);
4375 }
4376
4377 static int
4378 hns3_dev_start(struct rte_eth_dev *dev)
4379 {
4380         struct hns3_adapter *hns = dev->data->dev_private;
4381         struct hns3_hw *hw = &hns->hw;
4382         int ret;
4383
4384         PMD_INIT_FUNC_TRACE();
4385         if (rte_atomic16_read(&hw->reset.resetting))
4386                 return -EBUSY;
4387
4388         rte_spinlock_lock(&hw->lock);
4389         hw->adapter_state = HNS3_NIC_STARTING;
4390
4391         ret = hns3_do_start(hns, true);
4392         if (ret) {
4393                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4394                 rte_spinlock_unlock(&hw->lock);
4395                 return ret;
4396         }
4397         ret = hns3_map_rx_interrupt(dev);
4398         if (ret) {
4399                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4400                 rte_spinlock_unlock(&hw->lock);
4401                 return ret;
4402         }
4403
4404         hw->adapter_state = HNS3_NIC_STARTED;
4405         rte_spinlock_unlock(&hw->lock);
4406
4407         hns3_set_rxtx_function(dev);
4408         hns3_mp_req_start_rxtx(dev);
4409         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4410
4411         hns3_restore_filter(dev);
4412
4413         /* Enable interrupt of all rx queues before enabling queues */
4414         hns3_dev_all_rx_queue_intr_enable(hw, true);
4415         /*
4416          * When finished the initialization, enable queues to receive/transmit
4417          * packets.
4418          */
4419         hns3_enable_all_queues(hw, true);
4420
4421         hns3_info(hw, "hns3 dev start successful!");
4422         return 0;
4423 }
4424
4425 static int
4426 hns3_do_stop(struct hns3_adapter *hns)
4427 {
4428         struct hns3_hw *hw = &hns->hw;
4429         bool reset_queue;
4430         int ret;
4431
4432         ret = hns3_cfg_mac_mode(hw, false);
4433         if (ret)
4434                 return ret;
4435         hw->mac.link_status = ETH_LINK_DOWN;
4436
4437         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4438                 hns3_configure_all_mac_addr(hns, true);
4439                 reset_queue = true;
4440         } else
4441                 reset_queue = false;
4442         hw->mac.default_addr_setted = false;
4443         return hns3_stop_queues(hns, reset_queue);
4444 }
4445
4446 static void
4447 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4448 {
4449         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4450         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4451         struct hns3_adapter *hns = dev->data->dev_private;
4452         struct hns3_hw *hw = &hns->hw;
4453         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4454         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4455         uint16_t q_id;
4456
4457         if (dev->data->dev_conf.intr_conf.rxq == 0)
4458                 return;
4459
4460         /* unmap the ring with vector */
4461         if (rte_intr_allow_others(intr_handle)) {
4462                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4463                 base = RTE_INTR_VEC_RXTX_OFFSET;
4464         }
4465         if (rte_intr_dp_is_en(intr_handle)) {
4466                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4467                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4468                                                          HNS3_RING_TYPE_RX,
4469                                                          q_id);
4470                         if (vec < base + intr_handle->nb_efd - 1)
4471                                 vec++;
4472                 }
4473         }
4474         /* Clean datapath event and queue/vec mapping */
4475         rte_intr_efd_disable(intr_handle);
4476         if (intr_handle->intr_vec) {
4477                 rte_free(intr_handle->intr_vec);
4478                 intr_handle->intr_vec = NULL;
4479         }
4480 }
4481
4482 static void
4483 hns3_dev_stop(struct rte_eth_dev *dev)
4484 {
4485         struct hns3_adapter *hns = dev->data->dev_private;
4486         struct hns3_hw *hw = &hns->hw;
4487
4488         PMD_INIT_FUNC_TRACE();
4489
4490         hw->adapter_state = HNS3_NIC_STOPPING;
4491         hns3_set_rxtx_function(dev);
4492         rte_wmb();
4493         /* Disable datapath on secondary process. */
4494         hns3_mp_req_stop_rxtx(dev);
4495         /* Prevent crashes when queues are still in use. */
4496         rte_delay_ms(hw->tqps_num);
4497
4498         rte_spinlock_lock(&hw->lock);
4499         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4500                 hns3_do_stop(hns);
4501                 hns3_unmap_rx_interrupt(dev);
4502                 hns3_dev_release_mbufs(hns);
4503                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4504         }
4505         rte_eal_alarm_cancel(hns3_service_handler, dev);
4506         rte_spinlock_unlock(&hw->lock);
4507 }
4508
4509 static void
4510 hns3_dev_close(struct rte_eth_dev *eth_dev)
4511 {
4512         struct hns3_adapter *hns = eth_dev->data->dev_private;
4513         struct hns3_hw *hw = &hns->hw;
4514
4515         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4516                 rte_free(eth_dev->process_private);
4517                 eth_dev->process_private = NULL;
4518                 return;
4519         }
4520
4521         if (hw->adapter_state == HNS3_NIC_STARTED)
4522                 hns3_dev_stop(eth_dev);
4523
4524         hw->adapter_state = HNS3_NIC_CLOSING;
4525         hns3_reset_abort(hns);
4526         hw->adapter_state = HNS3_NIC_CLOSED;
4527
4528         hns3_configure_all_mc_mac_addr(hns, true);
4529         hns3_remove_all_vlan_table(hns);
4530         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4531         hns3_uninit_pf(eth_dev);
4532         hns3_free_all_queues(eth_dev);
4533         rte_free(hw->reset.wait_data);
4534         rte_free(eth_dev->process_private);
4535         eth_dev->process_private = NULL;
4536         hns3_mp_uninit_primary();
4537         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4538 }
4539
4540 static int
4541 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4542 {
4543         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4545
4546         fc_conf->pause_time = pf->pause_time;
4547
4548         /* return fc current mode */
4549         switch (hw->current_mode) {
4550         case HNS3_FC_FULL:
4551                 fc_conf->mode = RTE_FC_FULL;
4552                 break;
4553         case HNS3_FC_TX_PAUSE:
4554                 fc_conf->mode = RTE_FC_TX_PAUSE;
4555                 break;
4556         case HNS3_FC_RX_PAUSE:
4557                 fc_conf->mode = RTE_FC_RX_PAUSE;
4558                 break;
4559         case HNS3_FC_NONE:
4560         default:
4561                 fc_conf->mode = RTE_FC_NONE;
4562                 break;
4563         }
4564
4565         return 0;
4566 }
4567
4568 static void
4569 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4570 {
4571         switch (mode) {
4572         case RTE_FC_NONE:
4573                 hw->requested_mode = HNS3_FC_NONE;
4574                 break;
4575         case RTE_FC_RX_PAUSE:
4576                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4577                 break;
4578         case RTE_FC_TX_PAUSE:
4579                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4580                 break;
4581         case RTE_FC_FULL:
4582                 hw->requested_mode = HNS3_FC_FULL;
4583                 break;
4584         default:
4585                 hw->requested_mode = HNS3_FC_NONE;
4586                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4587                           "configured to RTE_FC_NONE", mode);
4588                 break;
4589         }
4590 }
4591
4592 static int
4593 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4594 {
4595         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4596         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4597         int ret;
4598
4599         if (fc_conf->high_water || fc_conf->low_water ||
4600             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4601                 hns3_err(hw, "Unsupported flow control settings specified, "
4602                          "high_water(%u), low_water(%u), send_xon(%u) and "
4603                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4604                          fc_conf->high_water, fc_conf->low_water,
4605                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4606                 return -EINVAL;
4607         }
4608         if (fc_conf->autoneg) {
4609                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4610                 return -EINVAL;
4611         }
4612         if (!fc_conf->pause_time) {
4613                 hns3_err(hw, "Invalid pause time %d setting.",
4614                          fc_conf->pause_time);
4615                 return -EINVAL;
4616         }
4617
4618         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4619             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4620                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4621                          "current_fc_status = %d", hw->current_fc_status);
4622                 return -EOPNOTSUPP;
4623         }
4624
4625         hns3_get_fc_mode(hw, fc_conf->mode);
4626         if (hw->requested_mode == hw->current_mode &&
4627             pf->pause_time == fc_conf->pause_time)
4628                 return 0;
4629
4630         rte_spinlock_lock(&hw->lock);
4631         ret = hns3_fc_enable(dev, fc_conf);
4632         rte_spinlock_unlock(&hw->lock);
4633
4634         return ret;
4635 }
4636
4637 static int
4638 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4639                             struct rte_eth_pfc_conf *pfc_conf)
4640 {
4641         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4643         uint8_t priority;
4644         int ret;
4645
4646         if (!hns3_dev_dcb_supported(hw)) {
4647                 hns3_err(hw, "This port does not support dcb configurations.");
4648                 return -EOPNOTSUPP;
4649         }
4650
4651         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4652             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4653                 hns3_err(hw, "Unsupported flow control settings specified, "
4654                          "high_water(%u), low_water(%u), send_xon(%u) and "
4655                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4656                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4657                          pfc_conf->fc.send_xon,
4658                          pfc_conf->fc.mac_ctrl_frame_fwd);
4659                 return -EINVAL;
4660         }
4661         if (pfc_conf->fc.autoneg) {
4662                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4663                 return -EINVAL;
4664         }
4665         if (pfc_conf->fc.pause_time == 0) {
4666                 hns3_err(hw, "Invalid pause time %d setting.",
4667                          pfc_conf->fc.pause_time);
4668                 return -EINVAL;
4669         }
4670
4671         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4672             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4673                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4674                              "current_fc_status = %d", hw->current_fc_status);
4675                 return -EOPNOTSUPP;
4676         }
4677
4678         priority = pfc_conf->priority;
4679         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4680         if (hw->dcb_info.pfc_en & BIT(priority) &&
4681             hw->requested_mode == hw->current_mode &&
4682             pfc_conf->fc.pause_time == pf->pause_time)
4683                 return 0;
4684
4685         rte_spinlock_lock(&hw->lock);
4686         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4687         rte_spinlock_unlock(&hw->lock);
4688
4689         return ret;
4690 }
4691
4692 static int
4693 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4694 {
4695         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4697         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4698         int i;
4699
4700         rte_spinlock_lock(&hw->lock);
4701         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4702                 dcb_info->nb_tcs = pf->local_max_tc;
4703         else
4704                 dcb_info->nb_tcs = 1;
4705
4706         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4707                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4708         for (i = 0; i < dcb_info->nb_tcs; i++)
4709                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4710
4711         for (i = 0; i < hw->num_tc; i++) {
4712                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4713                 dcb_info->tc_queue.tc_txq[0][i].base =
4714                                                 hw->tc_queue[i].tqp_offset;
4715                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4716                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4717                                                 hw->tc_queue[i].tqp_count;
4718         }
4719         rte_spinlock_unlock(&hw->lock);
4720
4721         return 0;
4722 }
4723
4724 static int
4725 hns3_reinit_dev(struct hns3_adapter *hns)
4726 {
4727         struct hns3_hw *hw = &hns->hw;
4728         int ret;
4729
4730         ret = hns3_cmd_init(hw);
4731         if (ret) {
4732                 hns3_err(hw, "Failed to init cmd: %d", ret);
4733                 return ret;
4734         }
4735
4736         ret = hns3_reset_all_queues(hns);
4737         if (ret) {
4738                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4739                 return ret;
4740         }
4741
4742         ret = hns3_init_hardware(hns);
4743         if (ret) {
4744                 hns3_err(hw, "Failed to init hardware: %d", ret);
4745                 return ret;
4746         }
4747
4748         ret = hns3_enable_hw_error_intr(hns, true);
4749         if (ret) {
4750                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4751                              ret);
4752                 return ret;
4753         }
4754         hns3_info(hw, "Reset done, driver initialization finished.");
4755
4756         return 0;
4757 }
4758
4759 static bool
4760 is_pf_reset_done(struct hns3_hw *hw)
4761 {
4762         uint32_t val, reg, reg_bit;
4763
4764         switch (hw->reset.level) {
4765         case HNS3_IMP_RESET:
4766                 reg = HNS3_GLOBAL_RESET_REG;
4767                 reg_bit = HNS3_IMP_RESET_BIT;
4768                 break;
4769         case HNS3_GLOBAL_RESET:
4770                 reg = HNS3_GLOBAL_RESET_REG;
4771                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4772                 break;
4773         case HNS3_FUNC_RESET:
4774                 reg = HNS3_FUN_RST_ING;
4775                 reg_bit = HNS3_FUN_RST_ING_B;
4776                 break;
4777         case HNS3_FLR_RESET:
4778         default:
4779                 hns3_err(hw, "Wait for unsupported reset level: %d",
4780                          hw->reset.level);
4781                 return true;
4782         }
4783         val = hns3_read_dev(hw, reg);
4784         if (hns3_get_bit(val, reg_bit))
4785                 return false;
4786         else
4787                 return true;
4788 }
4789
4790 bool
4791 hns3_is_reset_pending(struct hns3_adapter *hns)
4792 {
4793         struct hns3_hw *hw = &hns->hw;
4794         enum hns3_reset_level reset;
4795
4796         hns3_check_event_cause(hns, NULL);
4797         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4798         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4799                 hns3_warn(hw, "High level reset %d is pending", reset);
4800                 return true;
4801         }
4802         reset = hns3_get_reset_level(hns, &hw->reset.request);
4803         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4804                 hns3_warn(hw, "High level reset %d is request", reset);
4805                 return true;
4806         }
4807         return false;
4808 }
4809
4810 static int
4811 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4812 {
4813         struct hns3_hw *hw = &hns->hw;
4814         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4815         struct timeval tv;
4816
4817         if (wait_data->result == HNS3_WAIT_SUCCESS)
4818                 return 0;
4819         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4820                 gettimeofday(&tv, NULL);
4821                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4822                           tv.tv_sec, tv.tv_usec);
4823                 return -ETIME;
4824         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4825                 return -EAGAIN;
4826
4827         wait_data->hns = hns;
4828         wait_data->check_completion = is_pf_reset_done;
4829         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4830                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4831         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4832         wait_data->count = HNS3_RESET_WAIT_CNT;
4833         wait_data->result = HNS3_WAIT_REQUEST;
4834         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4835         return -EAGAIN;
4836 }
4837
4838 static int
4839 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4840 {
4841         struct hns3_cmd_desc desc;
4842         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4843
4844         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4845         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4846         req->fun_reset_vfid = func_id;
4847
4848         return hns3_cmd_send(hw, &desc, 1);
4849 }
4850
4851 static int
4852 hns3_imp_reset_cmd(struct hns3_hw *hw)
4853 {
4854         struct hns3_cmd_desc desc;
4855
4856         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4857         desc.data[0] = 0xeedd;
4858
4859         return hns3_cmd_send(hw, &desc, 1);
4860 }
4861
4862 static void
4863 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4864 {
4865         struct hns3_hw *hw = &hns->hw;
4866         struct timeval tv;
4867         uint32_t val;
4868
4869         gettimeofday(&tv, NULL);
4870         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4871             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4872                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4873                           tv.tv_sec, tv.tv_usec);
4874                 return;
4875         }
4876
4877         switch (reset_level) {
4878         case HNS3_IMP_RESET:
4879                 hns3_imp_reset_cmd(hw);
4880                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4881                           tv.tv_sec, tv.tv_usec);
4882                 break;
4883         case HNS3_GLOBAL_RESET:
4884                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4885                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4886                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4887                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4888                           tv.tv_sec, tv.tv_usec);
4889                 break;
4890         case HNS3_FUNC_RESET:
4891                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4892                           tv.tv_sec, tv.tv_usec);
4893                 /* schedule again to check later */
4894                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4895                 hns3_schedule_reset(hns);
4896                 break;
4897         default:
4898                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4899                 return;
4900         }
4901         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4902 }
4903
4904 static enum hns3_reset_level
4905 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4906 {
4907         struct hns3_hw *hw = &hns->hw;
4908         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4909
4910         /* Return the highest priority reset level amongst all */
4911         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4912                 reset_level = HNS3_IMP_RESET;
4913         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4914                 reset_level = HNS3_GLOBAL_RESET;
4915         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4916                 reset_level = HNS3_FUNC_RESET;
4917         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4918                 reset_level = HNS3_FLR_RESET;
4919
4920         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4921                 return HNS3_NONE_RESET;
4922
4923         return reset_level;
4924 }
4925
4926 static int
4927 hns3_prepare_reset(struct hns3_adapter *hns)
4928 {
4929         struct hns3_hw *hw = &hns->hw;
4930         uint32_t reg_val;
4931         int ret;
4932
4933         switch (hw->reset.level) {
4934         case HNS3_FUNC_RESET:
4935                 ret = hns3_func_reset_cmd(hw, 0);
4936                 if (ret)
4937                         return ret;
4938
4939                 /*
4940                  * After performaning pf reset, it is not necessary to do the
4941                  * mailbox handling or send any command to firmware, because
4942                  * any mailbox handling or command to firmware is only valid
4943                  * after hns3_cmd_init is called.
4944                  */
4945                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4946                 hw->reset.stats.request_cnt++;
4947                 break;
4948         case HNS3_IMP_RESET:
4949                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4950                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4951                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4952                 break;
4953         default:
4954                 break;
4955         }
4956         return 0;
4957 }
4958
4959 static int
4960 hns3_set_rst_done(struct hns3_hw *hw)
4961 {
4962         struct hns3_pf_rst_done_cmd *req;
4963         struct hns3_cmd_desc desc;
4964
4965         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4966         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4967         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4968         return hns3_cmd_send(hw, &desc, 1);
4969 }
4970
4971 static int
4972 hns3_stop_service(struct hns3_adapter *hns)
4973 {
4974         struct hns3_hw *hw = &hns->hw;
4975         struct rte_eth_dev *eth_dev;
4976
4977         eth_dev = &rte_eth_devices[hw->data->port_id];
4978         if (hw->adapter_state == HNS3_NIC_STARTED)
4979                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4980         hw->mac.link_status = ETH_LINK_DOWN;
4981
4982         hns3_set_rxtx_function(eth_dev);
4983         rte_wmb();
4984         /* Disable datapath on secondary process. */
4985         hns3_mp_req_stop_rxtx(eth_dev);
4986         rte_delay_ms(hw->tqps_num);
4987
4988         rte_spinlock_lock(&hw->lock);
4989         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4990             hw->adapter_state == HNS3_NIC_STOPPING) {
4991                 hns3_do_stop(hns);
4992                 hw->reset.mbuf_deferred_free = true;
4993         } else
4994                 hw->reset.mbuf_deferred_free = false;
4995
4996         /*
4997          * It is cumbersome for hardware to pick-and-choose entries for deletion
4998          * from table space. Hence, for function reset software intervention is
4999          * required to delete the entries
5000          */
5001         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5002                 hns3_configure_all_mc_mac_addr(hns, true);
5003         rte_spinlock_unlock(&hw->lock);
5004
5005         return 0;
5006 }
5007
5008 static int
5009 hns3_start_service(struct hns3_adapter *hns)
5010 {
5011         struct hns3_hw *hw = &hns->hw;
5012         struct rte_eth_dev *eth_dev;
5013
5014         if (hw->reset.level == HNS3_IMP_RESET ||
5015             hw->reset.level == HNS3_GLOBAL_RESET)
5016                 hns3_set_rst_done(hw);
5017         eth_dev = &rte_eth_devices[hw->data->port_id];
5018         hns3_set_rxtx_function(eth_dev);
5019         hns3_mp_req_start_rxtx(eth_dev);
5020         if (hw->adapter_state == HNS3_NIC_STARTED) {
5021                 hns3_service_handler(eth_dev);
5022
5023                 /* Enable interrupt of all rx queues before enabling queues */
5024                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5025                 /*
5026                  * When finished the initialization, enable queues to receive
5027                  * and transmit packets.
5028                  */
5029                 hns3_enable_all_queues(hw, true);
5030         }
5031
5032         return 0;
5033 }
5034
5035 static int
5036 hns3_restore_conf(struct hns3_adapter *hns)
5037 {
5038         struct hns3_hw *hw = &hns->hw;
5039         int ret;
5040
5041         ret = hns3_configure_all_mac_addr(hns, false);
5042         if (ret)
5043                 return ret;
5044
5045         ret = hns3_configure_all_mc_mac_addr(hns, false);
5046         if (ret)
5047                 goto err_mc_mac;
5048
5049         ret = hns3_dev_promisc_restore(hns);
5050         if (ret)
5051                 goto err_promisc;
5052
5053         ret = hns3_restore_vlan_table(hns);
5054         if (ret)
5055                 goto err_promisc;
5056
5057         ret = hns3_restore_vlan_conf(hns);
5058         if (ret)
5059                 goto err_promisc;
5060
5061         ret = hns3_restore_all_fdir_filter(hns);
5062         if (ret)
5063                 goto err_promisc;
5064
5065         ret = hns3_restore_rx_interrupt(hw);
5066         if (ret)
5067                 goto err_promisc;
5068
5069         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5070                 ret = hns3_do_start(hns, false);
5071                 if (ret)
5072                         goto err_promisc;
5073                 hns3_info(hw, "hns3 dev restart successful!");
5074         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5075                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5076         return 0;
5077
5078 err_promisc:
5079         hns3_configure_all_mc_mac_addr(hns, true);
5080 err_mc_mac:
5081         hns3_configure_all_mac_addr(hns, true);
5082         return ret;
5083 }
5084
5085 static void
5086 hns3_reset_service(void *param)
5087 {
5088         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5089         struct hns3_hw *hw = &hns->hw;
5090         enum hns3_reset_level reset_level;
5091         struct timeval tv_delta;
5092         struct timeval tv_start;
5093         struct timeval tv;
5094         uint64_t msec;
5095         int ret;
5096
5097         /*
5098          * The interrupt is not triggered within the delay time.
5099          * The interrupt may have been lost. It is necessary to handle
5100          * the interrupt to recover from the error.
5101          */
5102         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5103                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5104                 hns3_err(hw, "Handling interrupts in delayed tasks");
5105                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5106                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5107                 if (reset_level == HNS3_NONE_RESET) {
5108                         hns3_err(hw, "No reset level is set, try IMP reset");
5109                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5110                 }
5111         }
5112         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5113
5114         /*
5115          * Check if there is any ongoing reset in the hardware. This status can
5116          * be checked from reset_pending. If there is then, we need to wait for
5117          * hardware to complete reset.
5118          *    a. If we are able to figure out in reasonable time that hardware
5119          *       has fully resetted then, we can proceed with driver, client
5120          *       reset.
5121          *    b. else, we can come back later to check this status so re-sched
5122          *       now.
5123          */
5124         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5125         if (reset_level != HNS3_NONE_RESET) {
5126                 gettimeofday(&tv_start, NULL);
5127                 ret = hns3_reset_process(hns, reset_level);
5128                 gettimeofday(&tv, NULL);
5129                 timersub(&tv, &tv_start, &tv_delta);
5130                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5131                        tv_delta.tv_usec / USEC_PER_MSEC;
5132                 if (msec > HNS3_RESET_PROCESS_MS)
5133                         hns3_err(hw, "%d handle long time delta %" PRIx64
5134                                      " ms time=%ld.%.6ld",
5135                                  hw->reset.level, msec,
5136                                  tv.tv_sec, tv.tv_usec);
5137                 if (ret == -EAGAIN)
5138                         return;
5139         }
5140
5141         /* Check if we got any *new* reset requests to be honored */
5142         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5143         if (reset_level != HNS3_NONE_RESET)
5144                 hns3_msix_process(hns, reset_level);
5145 }
5146
5147 static const struct eth_dev_ops hns3_eth_dev_ops = {
5148         .dev_start          = hns3_dev_start,
5149         .dev_stop           = hns3_dev_stop,
5150         .dev_close          = hns3_dev_close,
5151         .promiscuous_enable = hns3_dev_promiscuous_enable,
5152         .promiscuous_disable = hns3_dev_promiscuous_disable,
5153         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5154         .allmulticast_disable = hns3_dev_allmulticast_disable,
5155         .mtu_set            = hns3_dev_mtu_set,
5156         .stats_get          = hns3_stats_get,
5157         .stats_reset        = hns3_stats_reset,
5158         .xstats_get         = hns3_dev_xstats_get,
5159         .xstats_get_names   = hns3_dev_xstats_get_names,
5160         .xstats_reset       = hns3_dev_xstats_reset,
5161         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5162         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5163         .dev_infos_get          = hns3_dev_infos_get,
5164         .fw_version_get         = hns3_fw_version_get,
5165         .rx_queue_setup         = hns3_rx_queue_setup,
5166         .tx_queue_setup         = hns3_tx_queue_setup,
5167         .rx_queue_release       = hns3_dev_rx_queue_release,
5168         .tx_queue_release       = hns3_dev_tx_queue_release,
5169         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5170         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5171         .dev_configure          = hns3_dev_configure,
5172         .flow_ctrl_get          = hns3_flow_ctrl_get,
5173         .flow_ctrl_set          = hns3_flow_ctrl_set,
5174         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5175         .mac_addr_add           = hns3_add_mac_addr,
5176         .mac_addr_remove        = hns3_remove_mac_addr,
5177         .mac_addr_set           = hns3_set_default_mac_addr,
5178         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5179         .link_update            = hns3_dev_link_update,
5180         .rss_hash_update        = hns3_dev_rss_hash_update,
5181         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5182         .reta_update            = hns3_dev_rss_reta_update,
5183         .reta_query             = hns3_dev_rss_reta_query,
5184         .filter_ctrl            = hns3_dev_filter_ctrl,
5185         .vlan_filter_set        = hns3_vlan_filter_set,
5186         .vlan_tpid_set          = hns3_vlan_tpid_set,
5187         .vlan_offload_set       = hns3_vlan_offload_set,
5188         .vlan_pvid_set          = hns3_vlan_pvid_set,
5189         .get_reg                = hns3_get_regs,
5190         .get_dcb_info           = hns3_get_dcb_info,
5191         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5192 };
5193
5194 static const struct hns3_reset_ops hns3_reset_ops = {
5195         .reset_service       = hns3_reset_service,
5196         .stop_service        = hns3_stop_service,
5197         .prepare_reset       = hns3_prepare_reset,
5198         .wait_hardware_ready = hns3_wait_hardware_ready,
5199         .reinit_dev          = hns3_reinit_dev,
5200         .restore_conf        = hns3_restore_conf,
5201         .start_service       = hns3_start_service,
5202 };
5203
5204 static int
5205 hns3_dev_init(struct rte_eth_dev *eth_dev)
5206 {
5207         struct rte_device *dev = eth_dev->device;
5208         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5209         struct hns3_adapter *hns = eth_dev->data->dev_private;
5210         struct hns3_hw *hw = &hns->hw;
5211         uint16_t device_id = pci_dev->id.device_id;
5212         int ret;
5213
5214         PMD_INIT_FUNC_TRACE();
5215         eth_dev->process_private = (struct hns3_process_private *)
5216             rte_zmalloc_socket("hns3_filter_list",
5217                                sizeof(struct hns3_process_private),
5218                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5219         if (eth_dev->process_private == NULL) {
5220                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5221                 return -ENOMEM;
5222         }
5223         /* initialize flow filter lists */
5224         hns3_filterlist_init(eth_dev);
5225
5226         hns3_set_rxtx_function(eth_dev);
5227         eth_dev->dev_ops = &hns3_eth_dev_ops;
5228         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5229                 hns3_mp_init_secondary();
5230                 hw->secondary_cnt++;
5231                 return 0;
5232         }
5233
5234         hns3_mp_init_primary();
5235         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5236
5237         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5238             device_id == HNS3_DEV_ID_50GE_RDMA ||
5239             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5240                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5241
5242         hns->is_vf = false;
5243         hw->data = eth_dev->data;
5244
5245         /*
5246          * Set default max packet size according to the mtu
5247          * default vale in DPDK frame.
5248          */
5249         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5250
5251         ret = hns3_reset_init(hw);
5252         if (ret)
5253                 goto err_init_reset;
5254         hw->reset.ops = &hns3_reset_ops;
5255
5256         ret = hns3_init_pf(eth_dev);
5257         if (ret) {
5258                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5259                 goto err_init_pf;
5260         }
5261
5262         /* Allocate memory for storing MAC addresses */
5263         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5264                                                sizeof(struct rte_ether_addr) *
5265                                                HNS3_UC_MACADDR_NUM, 0);
5266         if (eth_dev->data->mac_addrs == NULL) {
5267                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5268                              "to store MAC addresses",
5269                              sizeof(struct rte_ether_addr) *
5270                              HNS3_UC_MACADDR_NUM);
5271                 ret = -ENOMEM;
5272                 goto err_rte_zmalloc;
5273         }
5274
5275         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5276                             &eth_dev->data->mac_addrs[0]);
5277
5278         hw->adapter_state = HNS3_NIC_INITIALIZED;
5279         /*
5280          * Pass the information to the rte_eth_dev_close() that it should also
5281          * release the private port resources.
5282          */
5283         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5284
5285         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5286                 hns3_err(hw, "Reschedule reset service after dev_init");
5287                 hns3_schedule_reset(hns);
5288         } else {
5289                 /* IMP will wait ready flag before reset */
5290                 hns3_notify_reset_ready(hw, false);
5291         }
5292
5293         hns3_info(hw, "hns3 dev initialization successful!");
5294         return 0;
5295
5296 err_rte_zmalloc:
5297         hns3_uninit_pf(eth_dev);
5298
5299 err_init_pf:
5300         rte_free(hw->reset.wait_data);
5301 err_init_reset:
5302         eth_dev->dev_ops = NULL;
5303         eth_dev->rx_pkt_burst = NULL;
5304         eth_dev->tx_pkt_burst = NULL;
5305         eth_dev->tx_pkt_prepare = NULL;
5306         rte_free(eth_dev->process_private);
5307         eth_dev->process_private = NULL;
5308         return ret;
5309 }
5310
5311 static int
5312 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5313 {
5314         struct hns3_adapter *hns = eth_dev->data->dev_private;
5315         struct hns3_hw *hw = &hns->hw;
5316
5317         PMD_INIT_FUNC_TRACE();
5318
5319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5320                 return -EPERM;
5321
5322         eth_dev->dev_ops = NULL;
5323         eth_dev->rx_pkt_burst = NULL;
5324         eth_dev->tx_pkt_burst = NULL;
5325         eth_dev->tx_pkt_prepare = NULL;
5326         if (hw->adapter_state < HNS3_NIC_CLOSING)
5327                 hns3_dev_close(eth_dev);
5328
5329         hw->adapter_state = HNS3_NIC_REMOVED;
5330         return 0;
5331 }
5332
5333 static int
5334 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5335                    struct rte_pci_device *pci_dev)
5336 {
5337         return rte_eth_dev_pci_generic_probe(pci_dev,
5338                                              sizeof(struct hns3_adapter),
5339                                              hns3_dev_init);
5340 }
5341
5342 static int
5343 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5344 {
5345         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5346 }
5347
5348 static const struct rte_pci_id pci_id_hns3_map[] = {
5349         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5350         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5351         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5352         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5353         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5354         { .vendor_id = 0, /* sentinel */ },
5355 };
5356
5357 static struct rte_pci_driver rte_hns3_pmd = {
5358         .id_table = pci_id_hns3_map,
5359         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5360         .probe = eth_hns3_pci_probe,
5361         .remove = eth_hns3_pci_remove,
5362 };
5363
5364 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5365 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5366 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5367
5368 RTE_INIT(hns3_init_log)
5369 {
5370         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5371         if (hns3_logtype_init >= 0)
5372                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5373         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5374         if (hns3_logtype_driver >= 0)
5375                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5376 }