13ce3243270fba18f52f717b8775a64e70dd22a2
[dpdk.git] / drivers / net / hns3 / hns3_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018-2019 Hisilicon Limited.
3  */
4
5 #include <errno.h>
6 #include <stdarg.h>
7 #include <stdbool.h>
8 #include <stdio.h>
9 #include <stdint.h>
10 #include <inttypes.h>
11 #include <unistd.h>
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
16 #include <rte_dev.h>
17 #include <rte_eal.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
22 #include <rte_io.h>
23 #include <rte_log.h>
24 #include <rte_pci.h>
25
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
31 #include "hns3_dcb.h"
32 #include "hns3_mp.h"
33
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
36
37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
38 #define HNS3_INVLID_PVID                0xFFFF
39
40 #define HNS3_FILTER_TYPE_VF             0
41 #define HNS3_FILTER_TYPE_PORT           1
42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
51
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT           0
54 #define HNS3_CORE_RESET_BIT             1
55 #define HNS3_IMP_RESET_BIT              2
56 #define HNS3_FUN_RST_ING_B              0
57
58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
59
60 #define HNS3_RESET_WAIT_MS      100
61 #define HNS3_RESET_WAIT_CNT     200
62
63 enum hns3_evt_cause {
64         HNS3_VECTOR0_EVENT_RST,
65         HNS3_VECTOR0_EVENT_MBX,
66         HNS3_VECTOR0_EVENT_ERR,
67         HNS3_VECTOR0_EVENT_OTHER,
68 };
69
70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
71                                                  uint64_t *levels);
72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
74                                     int on);
75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
76
77 static int hns3_add_mc_addr(struct hns3_hw *hw,
78                             struct rte_ether_addr *mac_addr);
79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
80                             struct rte_ether_addr *mac_addr);
81
82 static void
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
84 {
85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
86 }
87
88 static void
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
90 {
91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
92 }
93
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
96 {
97         struct hns3_hw *hw = &hns->hw;
98         uint32_t vector0_int_stats;
99         uint32_t cmdq_src_val;
100         uint32_t val;
101         enum hns3_evt_cause ret;
102
103         /* fetch the events from their corresponding regs */
104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
106
107         /*
108          * Assumption: If by any chance reset and mailbox events are reported
109          * together then we will only process reset event and defer the
110          * processing of the mailbox events. Since, we would have not cleared
111          * RX CMDQ event this time we would receive again another interrupt
112          * from H/W just for the mailbox.
113          */
114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
118                 if (clearval) {
119                         hw->reset.stats.imp_cnt++;
120                         hns3_warn(hw, "IMP reset detected, clear reset status");
121                 } else {
122                         hns3_schedule_delayed_reset(hns);
123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
124                 }
125
126                 ret = HNS3_VECTOR0_EVENT_RST;
127                 goto out;
128         }
129
130         /* Global reset */
131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
135                 if (clearval) {
136                         hw->reset.stats.global_cnt++;
137                         hns3_warn(hw, "Global reset detected, clear reset status");
138                 } else {
139                         hns3_schedule_delayed_reset(hns);
140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
141                 }
142
143                 ret = HNS3_VECTOR0_EVENT_RST;
144                 goto out;
145         }
146
147         /* check for vector0 msix event source */
148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149                 val = vector0_int_stats;
150                 ret = HNS3_VECTOR0_EVENT_ERR;
151                 goto out;
152         }
153
154         /* check for vector0 mailbox(=CMDQ RX) event source */
155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
157                 val = cmdq_src_val;
158                 ret = HNS3_VECTOR0_EVENT_MBX;
159                 goto out;
160         }
161
162         if (clearval && (vector0_int_stats || cmdq_src_val))
163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164                           vector0_int_stats, cmdq_src_val);
165         val = vector0_int_stats;
166         ret = HNS3_VECTOR0_EVENT_OTHER;
167 out:
168
169         if (clearval)
170                 *clearval = val;
171         return ret;
172 }
173
174 static void
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
176 {
177         if (event_type == HNS3_VECTOR0_EVENT_RST)
178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
181 }
182
183 static void
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
185 {
186         uint32_t vector0_int_stats;
187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
188
189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190                 hns3_warn(hw, "Probe during IMP reset interrupt");
191
192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193                 hns3_warn(hw, "Probe during Global reset interrupt");
194
195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
200 }
201
202 static void
203 hns3_interrupt_handler(void *param)
204 {
205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206         struct hns3_adapter *hns = dev->data->dev_private;
207         struct hns3_hw *hw = &hns->hw;
208         enum hns3_evt_cause event_cause;
209         uint32_t clearval = 0;
210
211         /* Disable interrupt */
212         hns3_pf_disable_irq0(hw);
213
214         event_cause = hns3_check_event_cause(hns, &clearval);
215
216         /* vector 0 interrupt is shared with reset and mailbox source events. */
217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218                 hns3_handle_msix_error(hns, &hw->reset.request);
219                 hns3_schedule_reset(hns);
220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221                 hns3_schedule_reset(hns);
222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223                 hns3_dev_handle_mbx_msg(hw);
224         else
225                 hns3_err(hw, "Received unknown event");
226
227         hns3_clear_event_cause(hw, event_cause, clearval);
228         /* Enable interrupt if it is not cause by reset */
229         hns3_pf_enable_irq0(hw);
230 }
231
232 static int
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
234 {
235 #define HNS3_VLAN_ID_OFFSET_STEP        160
236 #define HNS3_VLAN_BYTE_SIZE             8
237         struct hns3_vlan_filter_pf_cfg_cmd *req;
238         struct hns3_hw *hw = &hns->hw;
239         uint8_t vlan_offset_byte_val;
240         struct hns3_cmd_desc desc;
241         uint8_t vlan_offset_byte;
242         uint8_t vlan_offset_base;
243         int ret;
244
245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
246
247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
249                            HNS3_VLAN_BYTE_SIZE;
250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
251
252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
253         req->vlan_offset = vlan_offset_base;
254         req->vlan_cfg = on ? 0 : 1;
255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
256
257         ret = hns3_cmd_send(hw, &desc, 1);
258         if (ret)
259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
260                          vlan_id, ret);
261
262         return ret;
263 }
264
265 static void
266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
267 {
268         struct hns3_user_vlan_table *vlan_entry;
269         struct hns3_pf *pf = &hns->pf;
270
271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
272                 if (vlan_entry->vlan_id == vlan_id) {
273                         if (vlan_entry->hd_tbl_status)
274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
275                         LIST_REMOVE(vlan_entry, next);
276                         rte_free(vlan_entry);
277                         break;
278                 }
279         }
280 }
281
282 static void
283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
284                         bool writen_to_tbl)
285 {
286         struct hns3_user_vlan_table *vlan_entry;
287         struct hns3_hw *hw = &hns->hw;
288         struct hns3_pf *pf = &hns->pf;
289
290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
291                 if (vlan_entry->vlan_id == vlan_id)
292                         return;
293         }
294
295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
296         if (vlan_entry == NULL) {
297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
298                 return;
299         }
300
301         vlan_entry->hd_tbl_status = writen_to_tbl;
302         vlan_entry->vlan_id = vlan_id;
303
304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
305 }
306
307 static int
308 hns3_restore_vlan_table(struct hns3_adapter *hns)
309 {
310         struct hns3_user_vlan_table *vlan_entry;
311         struct hns3_hw *hw = &hns->hw;
312         struct hns3_pf *pf = &hns->pf;
313         uint16_t vlan_id;
314         int ret = 0;
315
316         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
317                 return hns3_vlan_pvid_configure(hns,
318                                                 hw->port_base_vlan_cfg.pvid, 1);
319
320         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
321                 if (vlan_entry->hd_tbl_status) {
322                         vlan_id = vlan_entry->vlan_id;
323                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
324                         if (ret)
325                                 break;
326                 }
327         }
328
329         return ret;
330 }
331
332 static int
333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
334 {
335         struct hns3_hw *hw = &hns->hw;
336         bool writen_to_tbl = false;
337         int ret = 0;
338
339         /*
340          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
341          * for normal packet, deleting vlan id 0 is not allowed.
342          */
343         if (on == 0 && vlan_id == 0)
344                 return 0;
345
346         /*
347          * When port base vlan enabled, we use port base vlan as the vlan
348          * filter condition. In this case, we don't update vlan filter table
349          * when user add new vlan or remove exist vlan, just update the
350          * vlan list. The vlan id in vlan list will be writen in vlan filter
351          * table until port base vlan disabled
352          */
353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
354                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
355                 writen_to_tbl = true;
356         }
357
358         if (ret == 0 && vlan_id) {
359                 if (on)
360                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
361                 else
362                         hns3_rm_dev_vlan_table(hns, vlan_id);
363         }
364         return ret;
365 }
366
367 static int
368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
369 {
370         struct hns3_adapter *hns = dev->data->dev_private;
371         struct hns3_hw *hw = &hns->hw;
372         int ret;
373
374         rte_spinlock_lock(&hw->lock);
375         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
376         rte_spinlock_unlock(&hw->lock);
377         return ret;
378 }
379
380 static int
381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
382                          uint16_t tpid)
383 {
384         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
385         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
386         struct hns3_hw *hw = &hns->hw;
387         struct hns3_cmd_desc desc;
388         int ret;
389
390         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
391              vlan_type != ETH_VLAN_TYPE_OUTER)) {
392                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
393                 return -EINVAL;
394         }
395
396         if (tpid != RTE_ETHER_TYPE_VLAN) {
397                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
398                 return -EINVAL;
399         }
400
401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
402         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
403
404         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
405                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
406                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
407         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
408                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
409                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
410                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
411                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
412         }
413
414         ret = hns3_cmd_send(hw, &desc, 1);
415         if (ret) {
416                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
417                          ret);
418                 return ret;
419         }
420
421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
422
423         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
424         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
425         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
426
427         ret = hns3_cmd_send(hw, &desc, 1);
428         if (ret)
429                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
430                          ret);
431         return ret;
432 }
433
434 static int
435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
436                    uint16_t tpid)
437 {
438         struct hns3_adapter *hns = dev->data->dev_private;
439         struct hns3_hw *hw = &hns->hw;
440         int ret;
441
442         rte_spinlock_lock(&hw->lock);
443         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
444         rte_spinlock_unlock(&hw->lock);
445         return ret;
446 }
447
448 static int
449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
450                              struct hns3_rx_vtag_cfg *vcfg)
451 {
452         struct hns3_vport_vtag_rx_cfg_cmd *req;
453         struct hns3_hw *hw = &hns->hw;
454         struct hns3_cmd_desc desc;
455         uint16_t vport_id;
456         uint8_t bitmap;
457         int ret;
458
459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
460
461         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
462         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
463                      vcfg->strip_tag1_en ? 1 : 0);
464         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
465                      vcfg->strip_tag2_en ? 1 : 0);
466         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
467                      vcfg->vlan1_vlan_prionly ? 1 : 0);
468         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
469                      vcfg->vlan2_vlan_prionly ? 1 : 0);
470
471         /*
472          * In current version VF is not supported when PF is driven by DPDK
473          * driver, just need to configure parameters for PF vport.
474          */
475         vport_id = HNS3_PF_FUNC_ID;
476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
478         req->vf_bitmap[req->vf_offset] = bitmap;
479
480         ret = hns3_cmd_send(hw, &desc, 1);
481         if (ret)
482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
483         return ret;
484 }
485
486 static void
487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
488                            struct hns3_rx_vtag_cfg *vcfg)
489 {
490         struct hns3_pf *pf = &hns->pf;
491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
492 }
493
494 static void
495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
496                            struct hns3_tx_vtag_cfg *vcfg)
497 {
498         struct hns3_pf *pf = &hns->pf;
499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
500 }
501
502 static int
503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
504 {
505         struct hns3_rx_vtag_cfg rxvlan_cfg;
506         struct hns3_hw *hw = &hns->hw;
507         int ret;
508
509         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
510                 rxvlan_cfg.strip_tag1_en = false;
511                 rxvlan_cfg.strip_tag2_en = enable;
512         } else {
513                 rxvlan_cfg.strip_tag1_en = enable;
514                 rxvlan_cfg.strip_tag2_en = true;
515         }
516
517         rxvlan_cfg.vlan1_vlan_prionly = false;
518         rxvlan_cfg.vlan2_vlan_prionly = false;
519         rxvlan_cfg.rx_vlan_offload_en = enable;
520
521         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
522         if (ret) {
523                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
524                 return ret;
525         }
526
527         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
528
529         return ret;
530 }
531
532 static int
533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
534                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
535 {
536         struct hns3_vlan_filter_ctrl_cmd *req;
537         struct hns3_cmd_desc desc;
538         int ret;
539
540         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
541
542         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
543         req->vlan_type = vlan_type;
544         req->vlan_fe = filter_en ? fe_type : 0;
545         req->vf_id = vf_id;
546
547         ret = hns3_cmd_send(hw, &desc, 1);
548         if (ret)
549                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
550
551         return ret;
552 }
553
554 static int
555 hns3_vlan_filter_init(struct hns3_adapter *hns)
556 {
557         struct hns3_hw *hw = &hns->hw;
558         int ret;
559
560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
561                                         HNS3_FILTER_FE_EGRESS, false,
562                                         HNS3_PF_FUNC_ID);
563         if (ret) {
564                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
565                 return ret;
566         }
567
568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
569                                         HNS3_FILTER_FE_INGRESS, false,
570                                         HNS3_PF_FUNC_ID);
571         if (ret)
572                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
573
574         return ret;
575 }
576
577 static int
578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
579 {
580         struct hns3_hw *hw = &hns->hw;
581         int ret;
582
583         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
584                                         HNS3_FILTER_FE_INGRESS, enable,
585                                         HNS3_PF_FUNC_ID);
586         if (ret)
587                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
588                          enable ? "enable" : "disable", ret);
589
590         return ret;
591 }
592
593 static int
594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
595 {
596         struct hns3_adapter *hns = dev->data->dev_private;
597         struct hns3_hw *hw = &hns->hw;
598         struct rte_eth_rxmode *rxmode;
599         unsigned int tmp_mask;
600         bool enable;
601         int ret = 0;
602
603         rte_spinlock_lock(&hw->lock);
604         rxmode = &dev->data->dev_conf.rxmode;
605         tmp_mask = (unsigned int)mask;
606         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
607                 /* ignore vlan filter configuration during promiscuous mode */
608                 if (!dev->data->promiscuous) {
609                         /* Enable or disable VLAN filter */
610                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
611                                  true : false;
612
613                         ret = hns3_enable_vlan_filter(hns, enable);
614                         if (ret) {
615                                 rte_spinlock_unlock(&hw->lock);
616                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
617                                          enable ? "enable" : "disable", ret);
618                                 return ret;
619                         }
620                 }
621         }
622
623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
624                 /* Enable or disable VLAN stripping */
625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
626                     true : false;
627
628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
629                 if (ret) {
630                         rte_spinlock_unlock(&hw->lock);
631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
632                                  enable ? "enable" : "disable", ret);
633                         return ret;
634                 }
635         }
636
637         rte_spinlock_unlock(&hw->lock);
638
639         return ret;
640 }
641
642 static int
643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
644                              struct hns3_tx_vtag_cfg *vcfg)
645 {
646         struct hns3_vport_vtag_tx_cfg_cmd *req;
647         struct hns3_cmd_desc desc;
648         struct hns3_hw *hw = &hns->hw;
649         uint16_t vport_id;
650         uint8_t bitmap;
651         int ret;
652
653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
654
655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
656         req->def_vlan_tag1 = vcfg->default_tag1;
657         req->def_vlan_tag2 = vcfg->default_tag2;
658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
659                      vcfg->accept_tag1 ? 1 : 0);
660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
661                      vcfg->accept_untag1 ? 1 : 0);
662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
663                      vcfg->accept_tag2 ? 1 : 0);
664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
665                      vcfg->accept_untag2 ? 1 : 0);
666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
667                      vcfg->insert_tag1_en ? 1 : 0);
668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
669                      vcfg->insert_tag2_en ? 1 : 0);
670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
671
672         /*
673          * In current version VF is not supported when PF is driven by DPDK
674          * driver, just need to configure parameters for PF vport.
675          */
676         vport_id = HNS3_PF_FUNC_ID;
677         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
678         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
679         req->vf_bitmap[req->vf_offset] = bitmap;
680
681         ret = hns3_cmd_send(hw, &desc, 1);
682         if (ret)
683                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
684
685         return ret;
686 }
687
688 static int
689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
690                      uint16_t pvid)
691 {
692         struct hns3_hw *hw = &hns->hw;
693         struct hns3_tx_vtag_cfg txvlan_cfg;
694         int ret;
695
696         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
697                 txvlan_cfg.accept_tag1 = true;
698                 txvlan_cfg.insert_tag1_en = false;
699                 txvlan_cfg.default_tag1 = 0;
700         } else {
701                 txvlan_cfg.accept_tag1 = false;
702                 txvlan_cfg.insert_tag1_en = true;
703                 txvlan_cfg.default_tag1 = pvid;
704         }
705
706         txvlan_cfg.accept_untag1 = true;
707         txvlan_cfg.accept_tag2 = true;
708         txvlan_cfg.accept_untag2 = true;
709         txvlan_cfg.insert_tag2_en = false;
710         txvlan_cfg.default_tag2 = 0;
711
712         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
713         if (ret) {
714                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
715                          ret);
716                 return ret;
717         }
718
719         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
720         return ret;
721 }
722
723 static void
724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
725 {
726         struct hns3_hw *hw = &hns->hw;
727
728         hw->port_base_vlan_cfg.state = on ?
729             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
730
731         hw->port_base_vlan_cfg.pvid = pvid;
732 }
733
734 static void
735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
736 {
737         struct hns3_user_vlan_table *vlan_entry;
738         struct hns3_pf *pf = &hns->pf;
739
740         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
741                 if (vlan_entry->hd_tbl_status)
742                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
743
744                 vlan_entry->hd_tbl_status = false;
745         }
746
747         if (is_del_list) {
748                 vlan_entry = LIST_FIRST(&pf->vlan_list);
749                 while (vlan_entry) {
750                         LIST_REMOVE(vlan_entry, next);
751                         rte_free(vlan_entry);
752                         vlan_entry = LIST_FIRST(&pf->vlan_list);
753                 }
754         }
755 }
756
757 static void
758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
759 {
760         struct hns3_user_vlan_table *vlan_entry;
761         struct hns3_pf *pf = &hns->pf;
762
763         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
764                 if (!vlan_entry->hd_tbl_status)
765                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
766
767                 vlan_entry->hd_tbl_status = true;
768         }
769 }
770
771 static void
772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
773 {
774         struct hns3_hw *hw = &hns->hw;
775         int ret;
776
777         hns3_rm_all_vlan_table(hns, true);
778         if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
779                 ret = hns3_set_port_vlan_filter(hns,
780                                                 hw->port_base_vlan_cfg.pvid, 0);
781                 if (ret) {
782                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
783                                  ret);
784                         return;
785                 }
786         }
787 }
788
789 static int
790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
791                                 uint16_t port_base_vlan_state,
792                                 uint16_t new_pvid, uint16_t old_pvid)
793 {
794         struct hns3_hw *hw = &hns->hw;
795         int ret = 0;
796
797         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
798                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
799                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
800                         if (ret) {
801                                 hns3_err(hw,
802                                          "Failed to clear clear old pvid filter, ret =%d",
803                                          ret);
804                                 return ret;
805                         }
806                 }
807
808                 hns3_rm_all_vlan_table(hns, false);
809                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
810         }
811
812         if (new_pvid != 0) {
813                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
814                 if (ret) {
815                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
816                                  ret);
817                         return ret;
818                 }
819         }
820
821         if (new_pvid == hw->port_base_vlan_cfg.pvid)
822                 hns3_add_all_vlan_table(hns);
823
824         return ret;
825 }
826
827 static int
828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
829 {
830         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
831         struct hns3_rx_vtag_cfg rx_vlan_cfg;
832         bool rx_strip_en;
833         int ret;
834
835         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
836         if (on) {
837                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
838                 rx_vlan_cfg.strip_tag2_en = true;
839         } else {
840                 rx_vlan_cfg.strip_tag1_en = false;
841                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
842         }
843         rx_vlan_cfg.vlan1_vlan_prionly = false;
844         rx_vlan_cfg.vlan2_vlan_prionly = false;
845         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
846
847         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
848         if (ret)
849                 return ret;
850
851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
852         return ret;
853 }
854
855 static int
856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
857 {
858         struct hns3_hw *hw = &hns->hw;
859         uint16_t port_base_vlan_state;
860         uint16_t old_pvid;
861         int ret;
862
863         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
864                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
865                         hns3_warn(hw, "Invalid operation! As current pvid set "
866                                   "is %u, disable pvid %u is invalid",
867                                   hw->port_base_vlan_cfg.pvid, pvid);
868                 return 0;
869         }
870
871         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
872                                     HNS3_PORT_BASE_VLAN_DISABLE;
873         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
874         if (ret) {
875                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
876                          ret);
877                 return ret;
878         }
879
880         ret = hns3_en_pvid_strip(hns, on);
881         if (ret) {
882                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
883                          "ret = %d", ret);
884                 return ret;
885         }
886
887         if (pvid == HNS3_INVLID_PVID)
888                 goto out;
889         old_pvid = hw->port_base_vlan_cfg.pvid;
890         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
891                                               old_pvid);
892         if (ret) {
893                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
894                          ret);
895                 return ret;
896         }
897
898 out:
899         hns3_store_port_base_vlan_info(hns, pvid, on);
900         return ret;
901 }
902
903 static int
904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
905 {
906         struct hns3_adapter *hns = dev->data->dev_private;
907         struct hns3_hw *hw = &hns->hw;
908         bool pvid_en_state_change;
909         uint16_t pvid_state;
910         int ret;
911
912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
914                          RTE_ETHER_MAX_VLAN_ID);
915                 return -EINVAL;
916         }
917
918         /*
919          * If PVID configuration state change, should refresh the PVID
920          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
921          */
922         pvid_state = hw->port_base_vlan_cfg.state;
923         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
924             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
925                 pvid_en_state_change = false;
926         else
927                 pvid_en_state_change = true;
928
929         rte_spinlock_lock(&hw->lock);
930         ret = hns3_vlan_pvid_configure(hns, pvid, on);
931         rte_spinlock_unlock(&hw->lock);
932         if (ret)
933                 return ret;
934
935         if (pvid_en_state_change)
936                 hns3_update_all_queues_pvid_state(hw);
937
938         return 0;
939 }
940
941 static void
942 init_port_base_vlan_info(struct hns3_hw *hw)
943 {
944         hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
945         hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
946 }
947
948 static int
949 hns3_default_vlan_config(struct hns3_adapter *hns)
950 {
951         struct hns3_hw *hw = &hns->hw;
952         int ret;
953
954         ret = hns3_set_port_vlan_filter(hns, 0, 1);
955         if (ret)
956                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
957         return ret;
958 }
959
960 static int
961 hns3_init_vlan_config(struct hns3_adapter *hns)
962 {
963         struct hns3_hw *hw = &hns->hw;
964         int ret;
965
966         /*
967          * This function can be called in the initialization and reset process,
968          * when in reset process, it means that hardware had been reseted
969          * successfully and we need to restore the hardware configuration to
970          * ensure that the hardware configuration remains unchanged before and
971          * after reset.
972          */
973         if (rte_atomic16_read(&hw->reset.resetting) == 0)
974                 init_port_base_vlan_info(hw);
975
976         ret = hns3_vlan_filter_init(hns);
977         if (ret) {
978                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
979                 return ret;
980         }
981
982         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
983                                        RTE_ETHER_TYPE_VLAN);
984         if (ret) {
985                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
986                 return ret;
987         }
988
989         /*
990          * When in the reinit dev stage of the reset process, the following
991          * vlan-related configurations may differ from those at initialization,
992          * we will restore configurations to hardware in hns3_restore_vlan_table
993          * and hns3_restore_vlan_conf later.
994          */
995         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
996                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
997                 if (ret) {
998                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
999                         return ret;
1000                 }
1001
1002                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1003                 if (ret) {
1004                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1005                                  ret);
1006                         return ret;
1007                 }
1008         }
1009
1010         return hns3_default_vlan_config(hns);
1011 }
1012
1013 static int
1014 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1015 {
1016         struct hns3_pf *pf = &hns->pf;
1017         struct hns3_hw *hw = &hns->hw;
1018         uint64_t offloads;
1019         bool enable;
1020         int ret;
1021
1022         if (!hw->data->promiscuous) {
1023                 /* restore vlan filter states */
1024                 offloads = hw->data->dev_conf.rxmode.offloads;
1025                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1026                 ret = hns3_enable_vlan_filter(hns, enable);
1027                 if (ret) {
1028                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1029                                  "ret = %d", ret);
1030                         return ret;
1031                 }
1032         }
1033
1034         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1035         if (ret) {
1036                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1037                 return ret;
1038         }
1039
1040         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1041         if (ret)
1042                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1043
1044         return ret;
1045 }
1046
1047 static int
1048 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1049 {
1050         struct hns3_adapter *hns = dev->data->dev_private;
1051         struct rte_eth_dev_data *data = dev->data;
1052         struct rte_eth_txmode *txmode;
1053         struct hns3_hw *hw = &hns->hw;
1054         int mask;
1055         int ret;
1056
1057         txmode = &data->dev_conf.txmode;
1058         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1059                 hns3_warn(hw,
1060                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1061                           "configuration is not supported! Ignore these two "
1062                           "parameters: hw_vlan_reject_tagged(%d), "
1063                           "hw_vlan_reject_untagged(%d)",
1064                           txmode->hw_vlan_reject_tagged,
1065                           txmode->hw_vlan_reject_untagged);
1066
1067         /* Apply vlan offload setting */
1068         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1069         ret = hns3_vlan_offload_set(dev, mask);
1070         if (ret) {
1071                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1072                          ret);
1073                 return ret;
1074         }
1075
1076         /*
1077          * If pvid config is not set in rte_eth_conf, driver needn't to set
1078          * VLAN pvid related configuration to hardware.
1079          */
1080         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1081                 return 0;
1082
1083         /* Apply pvid setting */
1084         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1085                                  txmode->hw_vlan_insert_pvid);
1086         if (ret)
1087                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1088                          txmode->pvid, ret);
1089
1090         return ret;
1091 }
1092
1093 static int
1094 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1095                 unsigned int tso_mss_max)
1096 {
1097         struct hns3_cfg_tso_status_cmd *req;
1098         struct hns3_cmd_desc desc;
1099         uint16_t tso_mss;
1100
1101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1102
1103         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1104
1105         tso_mss = 0;
1106         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1107                        tso_mss_min);
1108         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1109
1110         tso_mss = 0;
1111         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1112                        tso_mss_max);
1113         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1114
1115         return hns3_cmd_send(hw, &desc, 1);
1116 }
1117
1118 static int
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120                    uint16_t *allocated_size, bool is_alloc)
1121 {
1122         struct hns3_umv_spc_alc_cmd *req;
1123         struct hns3_cmd_desc desc;
1124         int ret;
1125
1126         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129         req->space_size = rte_cpu_to_le_32(space_size);
1130
1131         ret = hns3_cmd_send(hw, &desc, 1);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134                              is_alloc ? "allocate" : "free", ret);
1135                 return ret;
1136         }
1137
1138         if (is_alloc && allocated_size)
1139                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1140
1141         return 0;
1142 }
1143
1144 static int
1145 hns3_init_umv_space(struct hns3_hw *hw)
1146 {
1147         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148         struct hns3_pf *pf = &hns->pf;
1149         uint16_t allocated_size = 0;
1150         int ret;
1151
1152         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1153                                  true);
1154         if (ret)
1155                 return ret;
1156
1157         if (allocated_size < pf->wanted_umv_size)
1158                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159                              pf->wanted_umv_size, allocated_size);
1160
1161         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162                                                 pf->wanted_umv_size;
1163         pf->used_umv_size = 0;
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         int ret;
1173
1174         if (pf->max_umv_size == 0)
1175                 return 0;
1176
1177         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1178         if (ret)
1179                 return ret;
1180
1181         pf->max_umv_size = 0;
1182
1183         return 0;
1184 }
1185
1186 static bool
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1188 {
1189         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190         struct hns3_pf *pf = &hns->pf;
1191         bool is_full;
1192
1193         is_full = (pf->used_umv_size >= pf->max_umv_size);
1194
1195         return is_full;
1196 }
1197
1198 static void
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1200 {
1201         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202         struct hns3_pf *pf = &hns->pf;
1203
1204         if (is_free) {
1205                 if (pf->used_umv_size > 0)
1206                         pf->used_umv_size--;
1207         } else
1208                 pf->used_umv_size++;
1209 }
1210
1211 static void
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213                       const uint8_t *addr, bool is_mc)
1214 {
1215         const unsigned char *mac_addr = addr;
1216         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217                             ((uint32_t)mac_addr[2] << 16) |
1218                             ((uint32_t)mac_addr[1] << 8) |
1219                             (uint32_t)mac_addr[0];
1220         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1221
1222         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1223         if (is_mc) {
1224                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1227         }
1228
1229         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1231 }
1232
1233 static int
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1235                              uint8_t resp_code,
1236                              enum hns3_mac_vlan_tbl_opcode op)
1237 {
1238         if (cmdq_resp) {
1239                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1240                          cmdq_resp);
1241                 return -EIO;
1242         }
1243
1244         if (op == HNS3_MAC_VLAN_ADD) {
1245                 if (resp_code == 0 || resp_code == 1) {
1246                         return 0;
1247                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248                         hns3_err(hw, "add mac addr failed for uc_overflow");
1249                         return -ENOSPC;
1250                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251                         hns3_err(hw, "add mac addr failed for mc_overflow");
1252                         return -ENOSPC;
1253                 }
1254
1255                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1256                          resp_code);
1257                 return -EIO;
1258         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259                 if (resp_code == 0) {
1260                         return 0;
1261                 } else if (resp_code == 1) {
1262                         hns3_dbg(hw, "remove mac addr failed for miss");
1263                         return -ENOENT;
1264                 }
1265
1266                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1267                          resp_code);
1268                 return -EIO;
1269         } else if (op == HNS3_MAC_VLAN_LKUP) {
1270                 if (resp_code == 0) {
1271                         return 0;
1272                 } else if (resp_code == 1) {
1273                         hns3_dbg(hw, "lookup mac addr failed for miss");
1274                         return -ENOENT;
1275                 }
1276
1277                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1278                          resp_code);
1279                 return -EIO;
1280         }
1281
1282         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1283                  op);
1284
1285         return -EINVAL;
1286 }
1287
1288 static int
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1291                          struct hns3_cmd_desc *desc, bool is_mc)
1292 {
1293         uint8_t resp_code;
1294         uint16_t retval;
1295         int ret;
1296
1297         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1298         if (is_mc) {
1299                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 memcpy(desc[0].data, req,
1301                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1303                                           true);
1304                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1306                                           true);
1307                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1308         } else {
1309                 memcpy(desc[0].data, req,
1310                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311                 ret = hns3_cmd_send(hw, desc, 1);
1312         }
1313         if (ret) {
1314                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1315                          ret);
1316                 return ret;
1317         }
1318         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319         retval = rte_le_to_cpu_16(desc[0].retval);
1320
1321         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322                                             HNS3_MAC_VLAN_LKUP);
1323 }
1324
1325 static int
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1328                       struct hns3_cmd_desc *mc_desc)
1329 {
1330         uint8_t resp_code;
1331         uint16_t retval;
1332         int cfg_status;
1333         int ret;
1334
1335         if (mc_desc == NULL) {
1336                 struct hns3_cmd_desc desc;
1337
1338                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339                 memcpy(desc.data, req,
1340                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341                 ret = hns3_cmd_send(hw, &desc, 1);
1342                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343                 retval = rte_le_to_cpu_16(desc.retval);
1344
1345                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1346                                                           HNS3_MAC_VLAN_ADD);
1347         } else {
1348                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354                 memcpy(mc_desc[0].data, req,
1355                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356                 mc_desc[0].retval = 0;
1357                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1360
1361                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1362                                                           HNS3_MAC_VLAN_ADD);
1363         }
1364
1365         if (ret) {
1366                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1367                 return ret;
1368         }
1369
1370         return cfg_status;
1371 }
1372
1373 static int
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1376 {
1377         struct hns3_cmd_desc desc;
1378         uint8_t resp_code;
1379         uint16_t retval;
1380         int ret;
1381
1382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1383
1384         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1385
1386         ret = hns3_cmd_send(hw, &desc, 1);
1387         if (ret) {
1388                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1389                 return ret;
1390         }
1391         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392         retval = rte_le_to_cpu_16(desc.retval);
1393
1394         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395                                             HNS3_MAC_VLAN_REMOVE);
1396 }
1397
1398 static int
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1400 {
1401         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402         struct hns3_mac_vlan_tbl_entry_cmd req;
1403         struct hns3_pf *pf = &hns->pf;
1404         struct hns3_cmd_desc desc;
1405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406         uint16_t egress_port = 0;
1407         uint8_t vf_id;
1408         int ret;
1409
1410         /* check if mac addr is valid */
1411         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1413                                       mac_addr);
1414                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1415                          mac_str);
1416                 return -EINVAL;
1417         }
1418
1419         memset(&req, 0, sizeof(req));
1420
1421         /*
1422          * In current version VF is not supported when PF is driven by DPDK
1423          * driver, just need to configure parameters for PF vport.
1424          */
1425         vf_id = HNS3_PF_FUNC_ID;
1426         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427                        HNS3_MAC_EPORT_VFID_S, vf_id);
1428
1429         req.egress_port = rte_cpu_to_le_16(egress_port);
1430
1431         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1432
1433         /*
1434          * Lookup the mac address in the mac_vlan table, and add
1435          * it if the entry is inexistent. Repeated unicast entry
1436          * is not allowed in the mac vlan table.
1437          */
1438         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439         if (ret == -ENOENT) {
1440                 if (!hns3_is_umv_space_full(hw)) {
1441                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1442                         if (!ret)
1443                                 hns3_update_umv_space(hw, false);
1444                         return ret;
1445                 }
1446
1447                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1448
1449                 return -ENOSPC;
1450         }
1451
1452         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1453
1454         /* check if we just hit the duplicate */
1455         if (ret == 0) {
1456                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1457                 return 0;
1458         }
1459
1460         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1461                  mac_str);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1468 {
1469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470         struct rte_ether_addr *addr;
1471         int ret;
1472         int i;
1473
1474         for (i = 0; i < hw->mc_addrs_num; i++) {
1475                 addr = &hw->mc_addrs[i];
1476                 /* Check if there are duplicate addresses */
1477                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                               addr);
1480                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1481                                  "(%s) is added by the set_mc_mac_addr_list "
1482                                  "API", mac_str);
1483                         return -EINVAL;
1484                 }
1485         }
1486
1487         ret = hns3_add_mc_addr(hw, mac_addr);
1488         if (ret) {
1489                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490                                       mac_addr);
1491                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1492                          mac_str, ret);
1493         }
1494         return ret;
1495 }
1496
1497 static int
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1499 {
1500         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1501         int ret;
1502
1503         ret = hns3_remove_mc_addr(hw, mac_addr);
1504         if (ret) {
1505                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1506                                       mac_addr);
1507                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1508                          mac_str, ret);
1509         }
1510         return ret;
1511 }
1512
1513 static int
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515                   uint32_t idx, __rte_unused uint32_t pool)
1516 {
1517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519         int ret;
1520
1521         rte_spinlock_lock(&hw->lock);
1522
1523         /*
1524          * In hns3 network engine adding UC and MC mac address with different
1525          * commands with firmware. We need to determine whether the input
1526          * address is a UC or a MC address to call different commands.
1527          * By the way, it is recommended calling the API function named
1528          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530          * may affect the specifications of UC mac addresses.
1531          */
1532         if (rte_is_multicast_ether_addr(mac_addr))
1533                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1534         else
1535                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1536
1537         if (ret) {
1538                 rte_spinlock_unlock(&hw->lock);
1539                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540                                       mac_addr);
1541                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1542                          ret);
1543                 return ret;
1544         }
1545
1546         if (idx == 0)
1547                 hw->mac.default_addr_setted = true;
1548         rte_spinlock_unlock(&hw->lock);
1549
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1555 {
1556         struct hns3_mac_vlan_tbl_entry_cmd req;
1557         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1558         int ret;
1559
1560         /* check if mac addr is valid */
1561         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1563                                       mac_addr);
1564                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1565                          mac_str);
1566                 return -EINVAL;
1567         }
1568
1569         memset(&req, 0, sizeof(req));
1570         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1574                 return 0;
1575         else if (ret == 0)
1576                 hns3_update_umv_space(hw, true);
1577
1578         return ret;
1579 }
1580
1581 static void
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1583 {
1584         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         /* index will be checked by upper level rte interface */
1586         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         if (rte_is_multicast_ether_addr(mac_addr))
1593                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1594         else
1595                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596         rte_spinlock_unlock(&hw->lock);
1597         if (ret) {
1598                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                       mac_addr);
1600                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1601                          ret);
1602         }
1603 }
1604
1605 static int
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607                           struct rte_ether_addr *mac_addr)
1608 {
1609         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct rte_ether_addr *oaddr;
1611         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612         bool default_addr_setted;
1613         bool rm_succes = false;
1614         int ret, ret_val;
1615
1616         /*
1617          * It has been guaranteed that input parameter named mac_addr is valid
1618          * address in the rte layer of DPDK framework.
1619          */
1620         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621         default_addr_setted = hw->mac.default_addr_setted;
1622         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1623                 return 0;
1624
1625         rte_spinlock_lock(&hw->lock);
1626         if (default_addr_setted) {
1627                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1628                 if (ret) {
1629                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                               oaddr);
1631                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1632                                   mac_str, ret);
1633                         rm_succes = false;
1634                 } else
1635                         rm_succes = true;
1636         }
1637
1638         ret = hns3_add_uc_addr_common(hw, mac_addr);
1639         if (ret) {
1640                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1641                                       mac_addr);
1642                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643                 goto err_add_uc_addr;
1644         }
1645
1646         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1647         if (ret) {
1648                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649                 goto err_pause_addr_cfg;
1650         }
1651
1652         rte_ether_addr_copy(mac_addr,
1653                             (struct rte_ether_addr *)hw->mac.mac_addr);
1654         hw->mac.default_addr_setted = true;
1655         rte_spinlock_unlock(&hw->lock);
1656
1657         return 0;
1658
1659 err_pause_addr_cfg:
1660         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1661         if (ret_val) {
1662                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663                                       mac_addr);
1664                 hns3_warn(hw,
1665                           "Failed to roll back to del setted mac addr(%s): %d",
1666                           mac_str, ret_val);
1667         }
1668
1669 err_add_uc_addr:
1670         if (rm_succes) {
1671                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1672                 if (ret_val) {
1673                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674                                               oaddr);
1675                         hns3_warn(hw,
1676                                   "Failed to restore old uc mac addr(%s): %d",
1677                                   mac_str, ret_val);
1678                         hw->mac.default_addr_setted = false;
1679                 }
1680         }
1681         rte_spinlock_unlock(&hw->lock);
1682
1683         return ret;
1684 }
1685
1686 static int
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1688 {
1689         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690         struct hns3_hw *hw = &hns->hw;
1691         struct rte_ether_addr *addr;
1692         int err = 0;
1693         int ret;
1694         int i;
1695
1696         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697                 addr = &hw->data->mac_addrs[i];
1698                 if (rte_is_zero_ether_addr(addr))
1699                         continue;
1700                 if (rte_is_multicast_ether_addr(addr))
1701                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1702                               hns3_add_mc_addr(hw, addr);
1703                 else
1704                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705                               hns3_add_uc_addr_common(hw, addr);
1706
1707                 if (ret) {
1708                         err = ret;
1709                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                               addr);
1711                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712                                  "ret = %d.", del ? "remove" : "restore",
1713                                  mac_str, i, ret);
1714                 }
1715         }
1716         return err;
1717 }
1718
1719 static void
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1721 {
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1723         uint8_t word_num;
1724         uint8_t bit_num;
1725
1726         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727                 word_num = vfid / 32;
1728                 bit_num = vfid % 32;
1729                 if (clr)
1730                         desc[1].data[word_num] &=
1731                             rte_cpu_to_le_32(~(1UL << bit_num));
1732                 else
1733                         desc[1].data[word_num] |=
1734                             rte_cpu_to_le_32(1UL << bit_num);
1735         } else {
1736                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737                 bit_num = vfid % 32;
1738                 if (clr)
1739                         desc[2].data[word_num] &=
1740                             rte_cpu_to_le_32(~(1UL << bit_num));
1741                 else
1742                         desc[2].data[word_num] |=
1743                             rte_cpu_to_le_32(1UL << bit_num);
1744         }
1745 }
1746
1747 static int
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_mac_vlan_tbl_entry_cmd req;
1751         struct hns3_cmd_desc desc[3];
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         uint8_t vf_id;
1754         int ret;
1755
1756         /* Check if mac addr is valid */
1757         if (!rte_is_multicast_ether_addr(mac_addr)) {
1758                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1759                                       mac_addr);
1760                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1761                          mac_str);
1762                 return -EINVAL;
1763         }
1764
1765         memset(&req, 0, sizeof(req));
1766         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1769         if (ret) {
1770                 /* This mac addr do not exist, add new entry for it */
1771                 memset(desc[0].data, 0, sizeof(desc[0].data));
1772                 memset(desc[1].data, 0, sizeof(desc[0].data));
1773                 memset(desc[2].data, 0, sizeof(desc[0].data));
1774         }
1775
1776         /*
1777          * In current version VF is not supported when PF is driven by DPDK
1778          * driver, just need to configure parameters for PF vport.
1779          */
1780         vf_id = HNS3_PF_FUNC_ID;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, just need to configure parameters for PF vport.
1821                  */
1822                 vf_id = HNS3_PF_FUNC_ID;
1823                 hns3_update_desc_vfid(desc, vf_id, true);
1824
1825                 /* All the vfid is zero, so need to delete this entry */
1826                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827         } else if (ret == -ENOENT) {
1828                 /* This mac addr doesn't exist. */
1829                 return 0;
1830         }
1831
1832         if (ret) {
1833                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1834                                       mac_addr);
1835                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1836         }
1837
1838         return ret;
1839 }
1840
1841 static int
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843                            struct rte_ether_addr *mc_addr_set,
1844                            uint32_t nb_mc_addr)
1845 {
1846         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847         struct rte_ether_addr *addr;
1848         uint32_t i;
1849         uint32_t j;
1850
1851         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853                          "invalid. valid range: 0~%d",
1854                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1855                 return -EINVAL;
1856         }
1857
1858         /* Check if input mac addresses are valid */
1859         for (i = 0; i < nb_mc_addr; i++) {
1860                 addr = &mc_addr_set[i];
1861                 if (!rte_is_multicast_ether_addr(addr)) {
1862                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1863                                               addr);
1864                         hns3_err(hw,
1865                                  "failed to set mc mac addr, addr(%s) invalid.",
1866                                  mac_str);
1867                         return -EINVAL;
1868                 }
1869
1870                 /* Check if there are duplicate addresses */
1871                 for (j = i + 1; j < nb_mc_addr; j++) {
1872                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873                                 rte_ether_format_addr(mac_str,
1874                                                       RTE_ETHER_ADDR_FMT_SIZE,
1875                                                       addr);
1876                                 hns3_err(hw, "failed to set mc mac addr, "
1877                                          "addrs invalid. two same addrs(%s).",
1878                                          mac_str);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882
1883                 /*
1884                  * Check if there are duplicate addresses between mac_addrs
1885                  * and mc_addr_set
1886                  */
1887                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888                         if (rte_is_same_ether_addr(addr,
1889                                                    &hw->data->mac_addrs[j])) {
1890                                 rte_ether_format_addr(mac_str,
1891                                                       RTE_ETHER_ADDR_FMT_SIZE,
1892                                                       addr);
1893                                 hns3_err(hw, "failed to set mc mac addr, "
1894                                          "addrs invalid. addrs(%s) has already "
1895                                          "configured in mac_addr add API",
1896                                          mac_str);
1897                                 return -EINVAL;
1898                         }
1899                 }
1900         }
1901
1902         return 0;
1903 }
1904
1905 static void
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907                            struct rte_ether_addr *mc_addr_set,
1908                            int mc_addr_num,
1909                            struct rte_ether_addr *reserved_addr_list,
1910                            int *reserved_addr_num,
1911                            struct rte_ether_addr *add_addr_list,
1912                            int *add_addr_num,
1913                            struct rte_ether_addr *rm_addr_list,
1914                            int *rm_addr_num)
1915 {
1916         struct rte_ether_addr *addr;
1917         int current_addr_num;
1918         int reserved_num = 0;
1919         int add_num = 0;
1920         int rm_num = 0;
1921         int num;
1922         int i;
1923         int j;
1924         bool same_addr;
1925
1926         /* Calculate the mc mac address list that should be removed */
1927         current_addr_num = hw->mc_addrs_num;
1928         for (i = 0; i < current_addr_num; i++) {
1929                 addr = &hw->mc_addrs[i];
1930                 same_addr = false;
1931                 for (j = 0; j < mc_addr_num; j++) {
1932                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1933                                 same_addr = true;
1934                                 break;
1935                         }
1936                 }
1937
1938                 if (!same_addr) {
1939                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1940                         rm_num++;
1941                 } else {
1942                         rte_ether_addr_copy(addr,
1943                                             &reserved_addr_list[reserved_num]);
1944                         reserved_num++;
1945                 }
1946         }
1947
1948         /* Calculate the mc mac address list that should be added */
1949         for (i = 0; i < mc_addr_num; i++) {
1950                 addr = &mc_addr_set[i];
1951                 same_addr = false;
1952                 for (j = 0; j < current_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1961                         add_num++;
1962                 }
1963         }
1964
1965         /* Reorder the mc mac address list maintained by driver */
1966         for (i = 0; i < reserved_num; i++)
1967                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1968
1969         for (i = 0; i < rm_num; i++) {
1970                 num = reserved_num + i;
1971                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1972         }
1973
1974         *reserved_addr_num = reserved_num;
1975         *add_addr_num = add_num;
1976         *rm_addr_num = rm_num;
1977 }
1978
1979 static int
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981                           struct rte_ether_addr *mc_addr_set,
1982                           uint32_t nb_mc_addr)
1983 {
1984         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr *addr;
1989         int reserved_addr_num;
1990         int add_addr_num;
1991         int rm_addr_num;
1992         int mc_addr_num;
1993         int num;
1994         int ret;
1995         int i;
1996
1997         /* Check if input parameters are valid */
1998         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1999         if (ret)
2000                 return ret;
2001
2002         rte_spinlock_lock(&hw->lock);
2003
2004         /*
2005          * Calculate the mc mac address lists those should be removed and be
2006          * added, Reorder the mc mac address list maintained by driver.
2007          */
2008         mc_addr_num = (int)nb_mc_addr;
2009         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010                                    reserved_addr_list, &reserved_addr_num,
2011                                    add_addr_list, &add_addr_num,
2012                                    rm_addr_list, &rm_addr_num);
2013
2014         /* Remove mc mac addresses */
2015         for (i = 0; i < rm_addr_num; i++) {
2016                 num = rm_addr_num - i - 1;
2017                 addr = &rm_addr_list[num];
2018                 ret = hns3_remove_mc_addr(hw, addr);
2019                 if (ret) {
2020                         rte_spinlock_unlock(&hw->lock);
2021                         return ret;
2022                 }
2023                 hw->mc_addrs_num--;
2024         }
2025
2026         /* Add mc mac addresses */
2027         for (i = 0; i < add_addr_num; i++) {
2028                 addr = &add_addr_list[i];
2029                 ret = hns3_add_mc_addr(hw, addr);
2030                 if (ret) {
2031                         rte_spinlock_unlock(&hw->lock);
2032                         return ret;
2033                 }
2034
2035                 num = reserved_addr_num + i;
2036                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2037                 hw->mc_addrs_num++;
2038         }
2039         rte_spinlock_unlock(&hw->lock);
2040
2041         return 0;
2042 }
2043
2044 static int
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2046 {
2047         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048         struct hns3_hw *hw = &hns->hw;
2049         struct rte_ether_addr *addr;
2050         int err = 0;
2051         int ret;
2052         int i;
2053
2054         for (i = 0; i < hw->mc_addrs_num; i++) {
2055                 addr = &hw->mc_addrs[i];
2056                 if (!rte_is_multicast_ether_addr(addr))
2057                         continue;
2058                 if (del)
2059                         ret = hns3_remove_mc_addr(hw, addr);
2060                 else
2061                         ret = hns3_add_mc_addr(hw, addr);
2062                 if (ret) {
2063                         err = ret;
2064                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2065                                               addr);
2066                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067                                  del ? "Remove" : "Restore", mac_str, ret);
2068                 }
2069         }
2070         return err;
2071 }
2072
2073 static int
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2075 {
2076         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2082         uint8_t num_tc;
2083         int max_tc = 0;
2084         int i;
2085
2086         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2088
2089         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091                          "rx_mq_mode = %d", rx_mq_mode);
2092                 return -EINVAL;
2093         }
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099                          rx_mq_mode, tx_mq_mode);
2100                 return -EINVAL;
2101         }
2102
2103         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2107                         return -EINVAL;
2108                 }
2109
2110                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113                                  "nb_tcs(%d) != %d or %d in rx direction.",
2114                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2115                         return -EINVAL;
2116                 }
2117
2118                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2121                         return -EINVAL;
2122                 }
2123
2124                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127                                          "is not equal to one in tx direction.",
2128                                          i, dcb_rx_conf->dcb_tc[i]);
2129                                 return -EINVAL;
2130                         }
2131                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132                                 max_tc = dcb_rx_conf->dcb_tc[i];
2133                 }
2134
2135                 num_tc = max_tc + 1;
2136                 if (num_tc > dcb_rx_conf->nb_tcs) {
2137                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138                                  num_tc, dcb_rx_conf->nb_tcs);
2139                         return -EINVAL;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2148 {
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         if (!hns3_dev_dcb_supported(hw)) {
2152                 hns3_err(hw, "this port does not support dcb configurations.");
2153                 return -EOPNOTSUPP;
2154         }
2155
2156         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2158                 return -EOPNOTSUPP;
2159         }
2160
2161         /* Check multiple queue mode */
2162         return hns3_check_mq_mode(dev);
2163 }
2164
2165 static int
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167                            enum hns3_ring_type queue_type, uint16_t queue_id)
2168 {
2169         struct hns3_cmd_desc desc;
2170         struct hns3_ctrl_vector_chain_cmd *req =
2171                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172         enum hns3_cmd_status status;
2173         enum hns3_opcode_type op;
2174         uint16_t tqp_type_and_id = 0;
2175         const char *op_str;
2176         uint16_t type;
2177         uint16_t gl;
2178
2179         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180         hns3_cmd_setup_basic_desc(&desc, op, false);
2181         req->int_vector_id = vector_id;
2182
2183         if (queue_type == HNS3_RING_TYPE_RX)
2184                 gl = HNS3_RING_GL_RX;
2185         else
2186                 gl = HNS3_RING_GL_TX;
2187
2188         type = queue_type;
2189
2190         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2191                        type);
2192         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2194                        gl);
2195         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196         req->int_cause_num = 1;
2197         op_str = mmap ? "Map" : "Unmap";
2198         status = hns3_cmd_send(hw, &desc, 1);
2199         if (status) {
2200                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201                          op_str, queue_id, req->int_vector_id, status);
2202                 return status;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2210 {
2211         uint8_t vec;
2212         int ret;
2213         int i;
2214
2215         /*
2216          * In hns3 network engine, vector 0 is always the misc interrupt of this
2217          * function, vector 1~N can be used respectively for the queues of the
2218          * function. Tx and Rx queues with the same number share the interrupt
2219          * vector. In the initialization clearing the all hardware mapping
2220          * relationship configurations between queues and interrupt vectors is
2221          * needed, so some error caused by the residual configurations, such as
2222          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2223          * constraints in hns3 hardware engine, we have to implement clearing
2224          * the mapping relationship configurations by binding all queues to the
2225          * last interrupt vector and reserving the last interrupt vector. This
2226          * method results in a decrease of the maximum queues when upper
2227          * applications call the rte_eth_dev_configure API function to enable
2228          * Rx interrupt.
2229          */
2230         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2231         /* vec - 1: the last interrupt is reserved */
2232         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2233         for (i = 0; i < hw->intr_tqps_num; i++) {
2234                 /*
2235                  * Set gap limiter and rate limiter configuration of queue's
2236                  * interrupt.
2237                  */
2238                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239                                        HNS3_TQP_INTR_GL_DEFAULT);
2240                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241                                        HNS3_TQP_INTR_GL_DEFAULT);
2242                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2243
2244                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245                                                  HNS3_RING_TYPE_TX, i);
2246                 if (ret) {
2247                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248                                           "vector: %d, ret=%d", i, vec, ret);
2249                         return ret;
2250                 }
2251
2252                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253                                                  HNS3_RING_TYPE_RX, i);
2254                 if (ret) {
2255                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256                                           "vector: %d, ret=%d", i, vec, ret);
2257                         return ret;
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2266 {
2267         struct hns3_adapter *hns = dev->data->dev_private;
2268         struct rte_eth_conf *conf = &dev->data->dev_conf;
2269         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270         struct hns3_hw *hw = &hns->hw;
2271         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274         struct rte_eth_rss_conf rss_conf;
2275         uint16_t mtu;
2276         bool gro_en;
2277         int ret;
2278
2279         /*
2280          * Hardware does not support individually enable/disable/reset the Tx or
2281          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2282          * and Rx queues at the same time. When the numbers of Tx queues
2283          * allocated by upper applications are not equal to the numbers of Rx
2284          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2285          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2286          * these fake queues are imperceptible, and can not be used by upper
2287          * applications.
2288          */
2289         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2290         if (ret) {
2291                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2292                 return ret;
2293         }
2294
2295         hw->adapter_state = HNS3_NIC_CONFIGURING;
2296         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2297                 hns3_err(hw, "setting link speed/duplex not supported");
2298                 ret = -EINVAL;
2299                 goto cfg_err;
2300         }
2301
2302         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2303                 ret = hns3_check_dcb_cfg(dev);
2304                 if (ret)
2305                         goto cfg_err;
2306         }
2307
2308         /* When RSS is not configured, redirect the packet queue 0 */
2309         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2310                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2311                 rss_conf = conf->rx_adv_conf.rss_conf;
2312                 if (rss_conf.rss_key == NULL) {
2313                         rss_conf.rss_key = rss_cfg->key;
2314                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2315                 }
2316
2317                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2318                 if (ret)
2319                         goto cfg_err;
2320         }
2321
2322         /*
2323          * If jumbo frames are enabled, MTU needs to be refreshed
2324          * according to the maximum RX packet length.
2325          */
2326         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2327                 /*
2328                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2329                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2330                  * can safely assign to "uint16_t" type variable.
2331                  */
2332                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2333                 ret = hns3_dev_mtu_set(dev, mtu);
2334                 if (ret)
2335                         goto cfg_err;
2336                 dev->data->mtu = mtu;
2337         }
2338
2339         ret = hns3_dev_configure_vlan(dev);
2340         if (ret)
2341                 goto cfg_err;
2342
2343         /* config hardware GRO */
2344         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2345         ret = hns3_config_gro(hw, gro_en);
2346         if (ret)
2347                 goto cfg_err;
2348
2349         hw->adapter_state = HNS3_NIC_CONFIGURED;
2350
2351         return 0;
2352
2353 cfg_err:
2354         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2355         hw->adapter_state = HNS3_NIC_INITIALIZED;
2356
2357         return ret;
2358 }
2359
2360 static int
2361 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2362 {
2363         struct hns3_config_max_frm_size_cmd *req;
2364         struct hns3_cmd_desc desc;
2365
2366         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2367
2368         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2369         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2370         req->min_frm_size = RTE_ETHER_MIN_LEN;
2371
2372         return hns3_cmd_send(hw, &desc, 1);
2373 }
2374
2375 static int
2376 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2377 {
2378         int ret;
2379
2380         ret = hns3_set_mac_mtu(hw, mps);
2381         if (ret) {
2382                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2383                 return ret;
2384         }
2385
2386         ret = hns3_buffer_alloc(hw);
2387         if (ret)
2388                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2389
2390         return ret;
2391 }
2392
2393 static int
2394 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2395 {
2396         struct hns3_adapter *hns = dev->data->dev_private;
2397         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2398         struct hns3_hw *hw = &hns->hw;
2399         bool is_jumbo_frame;
2400         int ret;
2401
2402         if (dev->data->dev_started) {
2403                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2404                          "before configuration", dev->data->port_id);
2405                 return -EBUSY;
2406         }
2407
2408         rte_spinlock_lock(&hw->lock);
2409         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2410         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2411
2412         /*
2413          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2414          * assign to "uint16_t" type variable.
2415          */
2416         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2417         if (ret) {
2418                 rte_spinlock_unlock(&hw->lock);
2419                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2420                          dev->data->port_id, mtu, ret);
2421                 return ret;
2422         }
2423         hns->pf.mps = (uint16_t)frame_size;
2424         if (is_jumbo_frame)
2425                 dev->data->dev_conf.rxmode.offloads |=
2426                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2427         else
2428                 dev->data->dev_conf.rxmode.offloads &=
2429                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2430         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2431         rte_spinlock_unlock(&hw->lock);
2432
2433         return 0;
2434 }
2435
2436 static int
2437 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2438 {
2439         struct hns3_adapter *hns = eth_dev->data->dev_private;
2440         struct hns3_hw *hw = &hns->hw;
2441         uint16_t queue_num = hw->tqps_num;
2442
2443         /*
2444          * In interrupt mode, 'max_rx_queues' is set based on the number of
2445          * MSI-X interrupt resources of the hardware.
2446          */
2447         if (hw->data->dev_conf.intr_conf.rxq == 1)
2448                 queue_num = hw->intr_tqps_num;
2449
2450         info->max_rx_queues = queue_num;
2451         info->max_tx_queues = hw->tqps_num;
2452         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2453         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2454         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2455         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2456         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2457         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2458                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2459                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2460                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2461                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2462                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2463                                  DEV_RX_OFFLOAD_KEEP_CRC |
2464                                  DEV_RX_OFFLOAD_SCATTER |
2465                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2466                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2467                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2468                                  DEV_RX_OFFLOAD_RSS_HASH |
2469                                  DEV_RX_OFFLOAD_TCP_LRO);
2470         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2471         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2472                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2473                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2474                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2475                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2476                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2477                                  DEV_TX_OFFLOAD_TCP_TSO |
2478                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2479                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2480                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2481                                  info->tx_queue_offload_capa |
2482                                  hns3_txvlan_cap_get(hw));
2483
2484         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2485                 .nb_max = HNS3_MAX_RING_DESC,
2486                 .nb_min = HNS3_MIN_RING_DESC,
2487                 .nb_align = HNS3_ALIGN_RING_DESC,
2488         };
2489
2490         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2491                 .nb_max = HNS3_MAX_RING_DESC,
2492                 .nb_min = HNS3_MIN_RING_DESC,
2493                 .nb_align = HNS3_ALIGN_RING_DESC,
2494                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2495                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
2496         };
2497
2498         info->vmdq_queue_num = 0;
2499
2500         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2501         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2502         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2503
2504         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2505         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2506         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2507         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2508         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2509         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2510
2511         return 0;
2512 }
2513
2514 static int
2515 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2516                     size_t fw_size)
2517 {
2518         struct hns3_adapter *hns = eth_dev->data->dev_private;
2519         struct hns3_hw *hw = &hns->hw;
2520         uint32_t version = hw->fw_version;
2521         int ret;
2522
2523         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2524                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2525                                       HNS3_FW_VERSION_BYTE3_S),
2526                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2527                                       HNS3_FW_VERSION_BYTE2_S),
2528                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2529                                       HNS3_FW_VERSION_BYTE1_S),
2530                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2531                                       HNS3_FW_VERSION_BYTE0_S));
2532         ret += 1; /* add the size of '\0' */
2533         if (fw_size < (uint32_t)ret)
2534                 return ret;
2535         else
2536                 return 0;
2537 }
2538
2539 static int
2540 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2541                      __rte_unused int wait_to_complete)
2542 {
2543         struct hns3_adapter *hns = eth_dev->data->dev_private;
2544         struct hns3_hw *hw = &hns->hw;
2545         struct hns3_mac *mac = &hw->mac;
2546         struct rte_eth_link new_link;
2547
2548         if (!hns3_is_reset_pending(hns)) {
2549                 hns3_update_speed_duplex(eth_dev);
2550                 hns3_update_link_status(hw);
2551         }
2552
2553         memset(&new_link, 0, sizeof(new_link));
2554         switch (mac->link_speed) {
2555         case ETH_SPEED_NUM_10M:
2556         case ETH_SPEED_NUM_100M:
2557         case ETH_SPEED_NUM_1G:
2558         case ETH_SPEED_NUM_10G:
2559         case ETH_SPEED_NUM_25G:
2560         case ETH_SPEED_NUM_40G:
2561         case ETH_SPEED_NUM_50G:
2562         case ETH_SPEED_NUM_100G:
2563                 new_link.link_speed = mac->link_speed;
2564                 break;
2565         default:
2566                 new_link.link_speed = ETH_SPEED_NUM_100M;
2567                 break;
2568         }
2569
2570         new_link.link_duplex = mac->link_duplex;
2571         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2572         new_link.link_autoneg =
2573             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2574
2575         return rte_eth_linkstatus_set(eth_dev, &new_link);
2576 }
2577
2578 static int
2579 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2580 {
2581         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2582         struct hns3_pf *pf = &hns->pf;
2583
2584         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2585                 return -EINVAL;
2586
2587         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2588
2589         return 0;
2590 }
2591
2592 static int
2593 hns3_query_function_status(struct hns3_hw *hw)
2594 {
2595 #define HNS3_QUERY_MAX_CNT              10
2596 #define HNS3_QUERY_SLEEP_MSCOEND        1
2597         struct hns3_func_status_cmd *req;
2598         struct hns3_cmd_desc desc;
2599         int timeout = 0;
2600         int ret;
2601
2602         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2603         req = (struct hns3_func_status_cmd *)desc.data;
2604
2605         do {
2606                 ret = hns3_cmd_send(hw, &desc, 1);
2607                 if (ret) {
2608                         PMD_INIT_LOG(ERR, "query function status failed %d",
2609                                      ret);
2610                         return ret;
2611                 }
2612
2613                 /* Check pf reset is done */
2614                 if (req->pf_state)
2615                         break;
2616
2617                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2618         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2619
2620         return hns3_parse_func_status(hw, req);
2621 }
2622
2623 static int
2624 hns3_query_pf_resource(struct hns3_hw *hw)
2625 {
2626         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2627         struct hns3_pf *pf = &hns->pf;
2628         struct hns3_pf_res_cmd *req;
2629         struct hns3_cmd_desc desc;
2630         int ret;
2631
2632         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2633         ret = hns3_cmd_send(hw, &desc, 1);
2634         if (ret) {
2635                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2636                 return ret;
2637         }
2638
2639         req = (struct hns3_pf_res_cmd *)desc.data;
2640         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2641         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2642         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2643         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2644
2645         if (req->tx_buf_size)
2646                 pf->tx_buf_size =
2647                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2648         else
2649                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2650
2651         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2652
2653         if (req->dv_buf_size)
2654                 pf->dv_buf_size =
2655                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2656         else
2657                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2658
2659         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2660
2661         hw->num_msi =
2662             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2663                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2664
2665         return 0;
2666 }
2667
2668 static void
2669 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2670 {
2671         struct hns3_cfg_param_cmd *req;
2672         uint64_t mac_addr_tmp_high;
2673         uint64_t mac_addr_tmp;
2674         uint32_t i;
2675
2676         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2677
2678         /* get the configuration */
2679         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2680                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2681         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2682                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2683         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2684                                            HNS3_CFG_TQP_DESC_N_M,
2685                                            HNS3_CFG_TQP_DESC_N_S);
2686
2687         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2688                                        HNS3_CFG_PHY_ADDR_M,
2689                                        HNS3_CFG_PHY_ADDR_S);
2690         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2691                                          HNS3_CFG_MEDIA_TP_M,
2692                                          HNS3_CFG_MEDIA_TP_S);
2693         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2694                                          HNS3_CFG_RX_BUF_LEN_M,
2695                                          HNS3_CFG_RX_BUF_LEN_S);
2696         /* get mac address */
2697         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2698         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2699                                            HNS3_CFG_MAC_ADDR_H_M,
2700                                            HNS3_CFG_MAC_ADDR_H_S);
2701
2702         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2703
2704         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2705                                             HNS3_CFG_DEFAULT_SPEED_M,
2706                                             HNS3_CFG_DEFAULT_SPEED_S);
2707         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2708                                            HNS3_CFG_RSS_SIZE_M,
2709                                            HNS3_CFG_RSS_SIZE_S);
2710
2711         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2712                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2713
2714         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2715         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2716
2717         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2718                                             HNS3_CFG_SPEED_ABILITY_M,
2719                                             HNS3_CFG_SPEED_ABILITY_S);
2720         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2721                                         HNS3_CFG_UMV_TBL_SPACE_M,
2722                                         HNS3_CFG_UMV_TBL_SPACE_S);
2723         if (!cfg->umv_space)
2724                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2725 }
2726
2727 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2728  * @hw: pointer to struct hns3_hw
2729  * @hcfg: the config structure to be getted
2730  */
2731 static int
2732 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2733 {
2734         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2735         struct hns3_cfg_param_cmd *req;
2736         uint32_t offset;
2737         uint32_t i;
2738         int ret;
2739
2740         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2741                 offset = 0;
2742                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2743                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2744                                           true);
2745                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2746                                i * HNS3_CFG_RD_LEN_BYTES);
2747                 /* Len should be divided by 4 when send to hardware */
2748                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2749                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2750                 req->offset = rte_cpu_to_le_32(offset);
2751         }
2752
2753         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2754         if (ret) {
2755                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2756                 return ret;
2757         }
2758
2759         hns3_parse_cfg(hcfg, desc);
2760
2761         return 0;
2762 }
2763
2764 static int
2765 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2766 {
2767         switch (speed_cmd) {
2768         case HNS3_CFG_SPEED_10M:
2769                 *speed = ETH_SPEED_NUM_10M;
2770                 break;
2771         case HNS3_CFG_SPEED_100M:
2772                 *speed = ETH_SPEED_NUM_100M;
2773                 break;
2774         case HNS3_CFG_SPEED_1G:
2775                 *speed = ETH_SPEED_NUM_1G;
2776                 break;
2777         case HNS3_CFG_SPEED_10G:
2778                 *speed = ETH_SPEED_NUM_10G;
2779                 break;
2780         case HNS3_CFG_SPEED_25G:
2781                 *speed = ETH_SPEED_NUM_25G;
2782                 break;
2783         case HNS3_CFG_SPEED_40G:
2784                 *speed = ETH_SPEED_NUM_40G;
2785                 break;
2786         case HNS3_CFG_SPEED_50G:
2787                 *speed = ETH_SPEED_NUM_50G;
2788                 break;
2789         case HNS3_CFG_SPEED_100G:
2790                 *speed = ETH_SPEED_NUM_100G;
2791                 break;
2792         default:
2793                 return -EINVAL;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 hns3_get_capability(struct hns3_hw *hw)
2801 {
2802         struct rte_pci_device *pci_dev;
2803         struct rte_eth_dev *eth_dev;
2804         uint16_t device_id;
2805         uint8_t revision;
2806         int ret;
2807
2808         eth_dev = &rte_eth_devices[hw->data->port_id];
2809         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2810         device_id = pci_dev->id.device_id;
2811
2812         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2813             device_id == HNS3_DEV_ID_50GE_RDMA ||
2814             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
2815                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2816
2817         /* Get PCI revision id */
2818         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2819                                   HNS3_PCI_REVISION_ID);
2820         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2821                 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
2822                 return -EIO;
2823         }
2824         hw->revision = revision;
2825
2826         return 0;
2827 }
2828
2829 static int
2830 hns3_get_board_configuration(struct hns3_hw *hw)
2831 {
2832         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2833         struct hns3_pf *pf = &hns->pf;
2834         struct hns3_cfg cfg;
2835         int ret;
2836
2837         ret = hns3_get_board_cfg(hw, &cfg);
2838         if (ret) {
2839                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2840                 return ret;
2841         }
2842
2843         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2844                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2845                 return -EOPNOTSUPP;
2846         }
2847
2848         hw->mac.media_type = cfg.media_type;
2849         hw->rss_size_max = cfg.rss_size_max;
2850         hw->rss_dis_flag = false;
2851         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2852         hw->mac.phy_addr = cfg.phy_addr;
2853         hw->mac.default_addr_setted = false;
2854         hw->num_tx_desc = cfg.tqp_desc_num;
2855         hw->num_rx_desc = cfg.tqp_desc_num;
2856         hw->dcb_info.num_pg = 1;
2857         hw->dcb_info.hw_pfc_map = 0;
2858
2859         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2860         if (ret) {
2861                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2862                              cfg.default_speed, ret);
2863                 return ret;
2864         }
2865
2866         pf->tc_max = cfg.tc_num;
2867         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2868                 PMD_INIT_LOG(WARNING,
2869                              "Get TC num(%u) from flash, set TC num to 1",
2870                              pf->tc_max);
2871                 pf->tc_max = 1;
2872         }
2873
2874         /* Dev does not support DCB */
2875         if (!hns3_dev_dcb_supported(hw)) {
2876                 pf->tc_max = 1;
2877                 pf->pfc_max = 0;
2878         } else
2879                 pf->pfc_max = pf->tc_max;
2880
2881         hw->dcb_info.num_tc = 1;
2882         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2883                                      hw->tqps_num / hw->dcb_info.num_tc);
2884         hns3_set_bit(hw->hw_tc_map, 0, 1);
2885         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2886
2887         pf->wanted_umv_size = cfg.umv_space;
2888
2889         return ret;
2890 }
2891
2892 static int
2893 hns3_get_configuration(struct hns3_hw *hw)
2894 {
2895         int ret;
2896
2897         ret = hns3_query_function_status(hw);
2898         if (ret) {
2899                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2900                 return ret;
2901         }
2902
2903         /* Get device capability */
2904         ret = hns3_get_capability(hw);
2905         if (ret) {
2906                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2907                 return ret;
2908         }
2909
2910         /* Get pf resource */
2911         ret = hns3_query_pf_resource(hw);
2912         if (ret) {
2913                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2914                 return ret;
2915         }
2916
2917         ret = hns3_get_board_configuration(hw);
2918         if (ret)
2919                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2920
2921         return ret;
2922 }
2923
2924 static int
2925 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2926                       uint16_t tqp_vid, bool is_pf)
2927 {
2928         struct hns3_tqp_map_cmd *req;
2929         struct hns3_cmd_desc desc;
2930         int ret;
2931
2932         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2933
2934         req = (struct hns3_tqp_map_cmd *)desc.data;
2935         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2936         req->tqp_vf = func_id;
2937         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2938         if (!is_pf)
2939                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2940         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2941
2942         ret = hns3_cmd_send(hw, &desc, 1);
2943         if (ret)
2944                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2945
2946         return ret;
2947 }
2948
2949 static int
2950 hns3_map_tqp(struct hns3_hw *hw)
2951 {
2952         uint16_t tqps_num = hw->total_tqps_num;
2953         uint16_t func_id;
2954         uint16_t tqp_id;
2955         bool is_pf;
2956         int num;
2957         int ret;
2958         int i;
2959
2960         /*
2961          * In current version VF is not supported when PF is driven by DPDK
2962          * driver, so we allocate tqps to PF as much as possible.
2963          */
2964         tqp_id = 0;
2965         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2966         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2967                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2968                 for (i = 0;
2969                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2970                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2971                                                     is_pf);
2972                         if (ret)
2973                                 return ret;
2974                 }
2975         }
2976
2977         return 0;
2978 }
2979
2980 static int
2981 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2982 {
2983         struct hns3_config_mac_speed_dup_cmd *req;
2984         struct hns3_cmd_desc desc;
2985         int ret;
2986
2987         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2988
2989         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2990
2991         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2992
2993         switch (speed) {
2994         case ETH_SPEED_NUM_10M:
2995                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2996                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2997                 break;
2998         case ETH_SPEED_NUM_100M:
2999                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3000                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3001                 break;
3002         case ETH_SPEED_NUM_1G:
3003                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3004                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3005                 break;
3006         case ETH_SPEED_NUM_10G:
3007                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3008                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3009                 break;
3010         case ETH_SPEED_NUM_25G:
3011                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3012                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3013                 break;
3014         case ETH_SPEED_NUM_40G:
3015                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3016                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3017                 break;
3018         case ETH_SPEED_NUM_50G:
3019                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3020                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3021                 break;
3022         case ETH_SPEED_NUM_100G:
3023                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3024                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3025                 break;
3026         default:
3027                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3028                 return -EINVAL;
3029         }
3030
3031         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3032
3033         ret = hns3_cmd_send(hw, &desc, 1);
3034         if (ret)
3035                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3036
3037         return ret;
3038 }
3039
3040 static int
3041 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3042 {
3043         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3044         struct hns3_pf *pf = &hns->pf;
3045         struct hns3_priv_buf *priv;
3046         uint32_t i, total_size;
3047
3048         total_size = pf->pkt_buf_size;
3049
3050         /* alloc tx buffer for all enabled tc */
3051         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3052                 priv = &buf_alloc->priv_buf[i];
3053
3054                 if (hw->hw_tc_map & BIT(i)) {
3055                         if (total_size < pf->tx_buf_size)
3056                                 return -ENOMEM;
3057
3058                         priv->tx_buf_size = pf->tx_buf_size;
3059                 } else
3060                         priv->tx_buf_size = 0;
3061
3062                 total_size -= priv->tx_buf_size;
3063         }
3064
3065         return 0;
3066 }
3067
3068 static int
3069 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3070 {
3071 /* TX buffer size is unit by 128 byte */
3072 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3073 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3074         struct hns3_tx_buff_alloc_cmd *req;
3075         struct hns3_cmd_desc desc;
3076         uint32_t buf_size;
3077         uint32_t i;
3078         int ret;
3079
3080         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3081
3082         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3083         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3084                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3085
3086                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3087                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3088                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3089         }
3090
3091         ret = hns3_cmd_send(hw, &desc, 1);
3092         if (ret)
3093                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3094
3095         return ret;
3096 }
3097
3098 static int
3099 hns3_get_tc_num(struct hns3_hw *hw)
3100 {
3101         int cnt = 0;
3102         uint8_t i;
3103
3104         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3105                 if (hw->hw_tc_map & BIT(i))
3106                         cnt++;
3107         return cnt;
3108 }
3109
3110 static uint32_t
3111 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3112 {
3113         struct hns3_priv_buf *priv;
3114         uint32_t rx_priv = 0;
3115         int i;
3116
3117         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3118                 priv = &buf_alloc->priv_buf[i];
3119                 if (priv->enable)
3120                         rx_priv += priv->buf_size;
3121         }
3122         return rx_priv;
3123 }
3124
3125 static uint32_t
3126 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3127 {
3128         uint32_t total_tx_size = 0;
3129         uint32_t i;
3130
3131         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3132                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3133
3134         return total_tx_size;
3135 }
3136
3137 /* Get the number of pfc enabled TCs, which have private buffer */
3138 static int
3139 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3140 {
3141         struct hns3_priv_buf *priv;
3142         int cnt = 0;
3143         uint8_t i;
3144
3145         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3146                 priv = &buf_alloc->priv_buf[i];
3147                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3148                         cnt++;
3149         }
3150
3151         return cnt;
3152 }
3153
3154 /* Get the number of pfc disabled TCs, which have private buffer */
3155 static int
3156 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3157                          struct hns3_pkt_buf_alloc *buf_alloc)
3158 {
3159         struct hns3_priv_buf *priv;
3160         int cnt = 0;
3161         uint8_t i;
3162
3163         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3164                 priv = &buf_alloc->priv_buf[i];
3165                 if (hw->hw_tc_map & BIT(i) &&
3166                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3167                         cnt++;
3168         }
3169
3170         return cnt;
3171 }
3172
3173 static bool
3174 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3175                   uint32_t rx_all)
3176 {
3177         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3178         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3179         struct hns3_pf *pf = &hns->pf;
3180         uint32_t shared_buf, aligned_mps;
3181         uint32_t rx_priv;
3182         uint8_t tc_num;
3183         uint8_t i;
3184
3185         tc_num = hns3_get_tc_num(hw);
3186         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3187
3188         if (hns3_dev_dcb_supported(hw))
3189                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3190                                         pf->dv_buf_size;
3191         else
3192                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3193                                         + pf->dv_buf_size;
3194
3195         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3196         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3197                              HNS3_BUF_SIZE_UNIT);
3198
3199         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3200         if (rx_all < rx_priv + shared_std)
3201                 return false;
3202
3203         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3204         buf_alloc->s_buf.buf_size = shared_buf;
3205         if (hns3_dev_dcb_supported(hw)) {
3206                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3207                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3208                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3209                                   HNS3_BUF_SIZE_UNIT);
3210         } else {
3211                 buf_alloc->s_buf.self.high =
3212                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3213                 buf_alloc->s_buf.self.low = aligned_mps;
3214         }
3215
3216         if (hns3_dev_dcb_supported(hw)) {
3217                 hi_thrd = shared_buf - pf->dv_buf_size;
3218
3219                 if (tc_num <= NEED_RESERVE_TC_NUM)
3220                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3221                                         / BUF_MAX_PERCENT;
3222
3223                 if (tc_num)
3224                         hi_thrd = hi_thrd / tc_num;
3225
3226                 hi_thrd = max_t(uint32_t, hi_thrd,
3227                                 HNS3_BUF_MUL_BY * aligned_mps);
3228                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3229                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3230         } else {
3231                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3232                 lo_thrd = aligned_mps;
3233         }
3234
3235         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3236                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3237                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3238         }
3239
3240         return true;
3241 }
3242
3243 static bool
3244 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3245                      struct hns3_pkt_buf_alloc *buf_alloc)
3246 {
3247         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3248         struct hns3_pf *pf = &hns->pf;
3249         struct hns3_priv_buf *priv;
3250         uint32_t aligned_mps;
3251         uint32_t rx_all;
3252         uint8_t i;
3253
3254         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3255         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3256
3257         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3258                 priv = &buf_alloc->priv_buf[i];
3259
3260                 priv->enable = 0;
3261                 priv->wl.low = 0;
3262                 priv->wl.high = 0;
3263                 priv->buf_size = 0;
3264
3265                 if (!(hw->hw_tc_map & BIT(i)))
3266                         continue;
3267
3268                 priv->enable = 1;
3269                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3270                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3271                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3272                                                 HNS3_BUF_SIZE_UNIT);
3273                 } else {
3274                         priv->wl.low = 0;
3275                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3276                                         aligned_mps;
3277                 }
3278
3279                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3280         }
3281
3282         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3283 }
3284
3285 static bool
3286 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3287                              struct hns3_pkt_buf_alloc *buf_alloc)
3288 {
3289         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3290         struct hns3_pf *pf = &hns->pf;
3291         struct hns3_priv_buf *priv;
3292         int no_pfc_priv_num;
3293         uint32_t rx_all;
3294         uint8_t mask;
3295         int i;
3296
3297         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3298         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3299
3300         /* let the last to be cleared first */
3301         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3302                 priv = &buf_alloc->priv_buf[i];
3303                 mask = BIT((uint8_t)i);
3304
3305                 if (hw->hw_tc_map & mask &&
3306                     !(hw->dcb_info.hw_pfc_map & mask)) {
3307                         /* Clear the no pfc TC private buffer */
3308                         priv->wl.low = 0;
3309                         priv->wl.high = 0;
3310                         priv->buf_size = 0;
3311                         priv->enable = 0;
3312                         no_pfc_priv_num--;
3313                 }
3314
3315                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3316                     no_pfc_priv_num == 0)
3317                         break;
3318         }
3319
3320         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3321 }
3322
3323 static bool
3324 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3325                            struct hns3_pkt_buf_alloc *buf_alloc)
3326 {
3327         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3328         struct hns3_pf *pf = &hns->pf;
3329         struct hns3_priv_buf *priv;
3330         uint32_t rx_all;
3331         int pfc_priv_num;
3332         uint8_t mask;
3333         int i;
3334
3335         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3336         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3337
3338         /* let the last to be cleared first */
3339         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3340                 priv = &buf_alloc->priv_buf[i];
3341                 mask = BIT((uint8_t)i);
3342
3343                 if (hw->hw_tc_map & mask &&
3344                     hw->dcb_info.hw_pfc_map & mask) {
3345                         /* Reduce the number of pfc TC with private buffer */
3346                         priv->wl.low = 0;
3347                         priv->enable = 0;
3348                         priv->wl.high = 0;
3349                         priv->buf_size = 0;
3350                         pfc_priv_num--;
3351                 }
3352                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3353                     pfc_priv_num == 0)
3354                         break;
3355         }
3356
3357         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3358 }
3359
3360 static bool
3361 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3362                           struct hns3_pkt_buf_alloc *buf_alloc)
3363 {
3364 #define COMPENSATE_BUFFER       0x3C00
3365 #define COMPENSATE_HALF_MPS_NUM 5
3366 #define PRIV_WL_GAP             0x1800
3367         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3368         struct hns3_pf *pf = &hns->pf;
3369         uint32_t tc_num = hns3_get_tc_num(hw);
3370         uint32_t half_mps = pf->mps >> 1;
3371         struct hns3_priv_buf *priv;
3372         uint32_t min_rx_priv;
3373         uint32_t rx_priv;
3374         uint8_t i;
3375
3376         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3377         if (tc_num)
3378                 rx_priv = rx_priv / tc_num;
3379
3380         if (tc_num <= NEED_RESERVE_TC_NUM)
3381                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3382
3383         /*
3384          * Minimum value of private buffer in rx direction (min_rx_priv) is
3385          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3386          * buffer if rx_priv is greater than min_rx_priv.
3387          */
3388         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3389                         COMPENSATE_HALF_MPS_NUM * half_mps;
3390         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3391         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3392
3393         if (rx_priv < min_rx_priv)
3394                 return false;
3395
3396         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3397                 priv = &buf_alloc->priv_buf[i];
3398
3399                 priv->enable = 0;
3400                 priv->wl.low = 0;
3401                 priv->wl.high = 0;
3402                 priv->buf_size = 0;
3403
3404                 if (!(hw->hw_tc_map & BIT(i)))
3405                         continue;
3406
3407                 priv->enable = 1;
3408                 priv->buf_size = rx_priv;
3409                 priv->wl.high = rx_priv - pf->dv_buf_size;
3410                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3411         }
3412
3413         buf_alloc->s_buf.buf_size = 0;
3414
3415         return true;
3416 }
3417
3418 /*
3419  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3420  * @hw: pointer to struct hns3_hw
3421  * @buf_alloc: pointer to buffer calculation data
3422  * @return: 0: calculate sucessful, negative: fail
3423  */
3424 static int
3425 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3426 {
3427         /* When DCB is not supported, rx private buffer is not allocated. */
3428         if (!hns3_dev_dcb_supported(hw)) {
3429                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3430                 struct hns3_pf *pf = &hns->pf;
3431                 uint32_t rx_all = pf->pkt_buf_size;
3432
3433                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3434                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3435                         return -ENOMEM;
3436
3437                 return 0;
3438         }
3439
3440         /*
3441          * Try to allocate privated packet buffer for all TCs without share
3442          * buffer.
3443          */
3444         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3445                 return 0;
3446
3447         /*
3448          * Try to allocate privated packet buffer for all TCs with share
3449          * buffer.
3450          */
3451         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3452                 return 0;
3453
3454         /*
3455          * For different application scenes, the enabled port number, TC number
3456          * and no_drop TC number are different. In order to obtain the better
3457          * performance, software could allocate the buffer size and configure
3458          * the waterline by tring to decrease the private buffer size according
3459          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3460          * enabled tc.
3461          */
3462         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3463                 return 0;
3464
3465         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3466                 return 0;
3467
3468         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3469                 return 0;
3470
3471         return -ENOMEM;
3472 }
3473
3474 static int
3475 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3476 {
3477         struct hns3_rx_priv_buff_cmd *req;
3478         struct hns3_cmd_desc desc;
3479         uint32_t buf_size;
3480         int ret;
3481         int i;
3482
3483         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3484         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3485
3486         /* Alloc private buffer TCs */
3487         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3488                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3489
3490                 req->buf_num[i] =
3491                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3492                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3493         }
3494
3495         buf_size = buf_alloc->s_buf.buf_size;
3496         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3497                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3498
3499         ret = hns3_cmd_send(hw, &desc, 1);
3500         if (ret)
3501                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3502
3503         return ret;
3504 }
3505
3506 static int
3507 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3508 {
3509 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3510         struct hns3_rx_priv_wl_buf *req;
3511         struct hns3_priv_buf *priv;
3512         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3513         int i, j;
3514         int ret;
3515
3516         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3517                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3518                                           false);
3519                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3520
3521                 /* The first descriptor set the NEXT bit to 1 */
3522                 if (i == 0)
3523                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3524                 else
3525                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3526
3527                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3528                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3529
3530                         priv = &buf_alloc->priv_buf[idx];
3531                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3532                                                         HNS3_BUF_UNIT_S);
3533                         req->tc_wl[j].high |=
3534                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3535                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3536                                                         HNS3_BUF_UNIT_S);
3537                         req->tc_wl[j].low |=
3538                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3539                 }
3540         }
3541
3542         /* Send 2 descriptor at one time */
3543         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3544         if (ret)
3545                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3546                              ret);
3547         return ret;
3548 }
3549
3550 static int
3551 hns3_common_thrd_config(struct hns3_hw *hw,
3552                         struct hns3_pkt_buf_alloc *buf_alloc)
3553 {
3554 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3555         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3556         struct hns3_rx_com_thrd *req;
3557         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3558         struct hns3_tc_thrd *tc;
3559         int tc_idx;
3560         int i, j;
3561         int ret;
3562
3563         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3564                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3565                                           false);
3566                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3567
3568                 /* The first descriptor set the NEXT bit to 1 */
3569                 if (i == 0)
3570                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3571                 else
3572                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3573
3574                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3575                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3576                         tc = &s_buf->tc_thrd[tc_idx];
3577
3578                         req->com_thrd[j].high =
3579                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3580                         req->com_thrd[j].high |=
3581                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3582                         req->com_thrd[j].low =
3583                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3584                         req->com_thrd[j].low |=
3585                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3586                 }
3587         }
3588
3589         /* Send 2 descriptors at one time */
3590         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3591         if (ret)
3592                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3593
3594         return ret;
3595 }
3596
3597 static int
3598 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3599 {
3600         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3601         struct hns3_rx_com_wl *req;
3602         struct hns3_cmd_desc desc;
3603         int ret;
3604
3605         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3606
3607         req = (struct hns3_rx_com_wl *)desc.data;
3608         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3609         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3610
3611         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3612         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3613
3614         ret = hns3_cmd_send(hw, &desc, 1);
3615         if (ret)
3616                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3617
3618         return ret;
3619 }
3620
3621 int
3622 hns3_buffer_alloc(struct hns3_hw *hw)
3623 {
3624         struct hns3_pkt_buf_alloc pkt_buf;
3625         int ret;
3626
3627         memset(&pkt_buf, 0, sizeof(pkt_buf));
3628         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3629         if (ret) {
3630                 PMD_INIT_LOG(ERR,
3631                              "could not calc tx buffer size for all TCs %d",
3632                              ret);
3633                 return ret;
3634         }
3635
3636         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3637         if (ret) {
3638                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3639                 return ret;
3640         }
3641
3642         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3643         if (ret) {
3644                 PMD_INIT_LOG(ERR,
3645                              "could not calc rx priv buffer size for all TCs %d",
3646                              ret);
3647                 return ret;
3648         }
3649
3650         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3651         if (ret) {
3652                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3653                 return ret;
3654         }
3655
3656         if (hns3_dev_dcb_supported(hw)) {
3657                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3658                 if (ret) {
3659                         PMD_INIT_LOG(ERR,
3660                                      "could not configure rx private waterline %d",
3661                                      ret);
3662                         return ret;
3663                 }
3664
3665                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3666                 if (ret) {
3667                         PMD_INIT_LOG(ERR,
3668                                      "could not configure common threshold %d",
3669                                      ret);
3670                         return ret;
3671                 }
3672         }
3673
3674         ret = hns3_common_wl_config(hw, &pkt_buf);
3675         if (ret)
3676                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3677                              ret);
3678
3679         return ret;
3680 }
3681
3682 static int
3683 hns3_mac_init(struct hns3_hw *hw)
3684 {
3685         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3686         struct hns3_mac *mac = &hw->mac;
3687         struct hns3_pf *pf = &hns->pf;
3688         int ret;
3689
3690         pf->support_sfp_query = true;
3691         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3692         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3693         if (ret) {
3694                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3695                 return ret;
3696         }
3697
3698         mac->link_status = ETH_LINK_DOWN;
3699
3700         return hns3_config_mtu(hw, pf->mps);
3701 }
3702
3703 static int
3704 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3705 {
3706 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3707 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3708 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3709 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3710         int return_status;
3711
3712         if (cmdq_resp) {
3713                 PMD_INIT_LOG(ERR,
3714                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3715                              cmdq_resp);
3716                 return -EIO;
3717         }
3718
3719         switch (resp_code) {
3720         case HNS3_ETHERTYPE_SUCCESS_ADD:
3721         case HNS3_ETHERTYPE_ALREADY_ADD:
3722                 return_status = 0;
3723                 break;
3724         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3725                 PMD_INIT_LOG(ERR,
3726                              "add mac ethertype failed for manager table overflow.");
3727                 return_status = -EIO;
3728                 break;
3729         case HNS3_ETHERTYPE_KEY_CONFLICT:
3730                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3731                 return_status = -EIO;
3732                 break;
3733         default:
3734                 PMD_INIT_LOG(ERR,
3735                              "add mac ethertype failed for undefined, code=%d.",
3736                              resp_code);
3737                 return_status = -EIO;
3738                 break;
3739         }
3740
3741         return return_status;
3742 }
3743
3744 static int
3745 hns3_add_mgr_tbl(struct hns3_hw *hw,
3746                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3747 {
3748         struct hns3_cmd_desc desc;
3749         uint8_t resp_code;
3750         uint16_t retval;
3751         int ret;
3752
3753         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3754         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3755
3756         ret = hns3_cmd_send(hw, &desc, 1);
3757         if (ret) {
3758                 PMD_INIT_LOG(ERR,
3759                              "add mac ethertype failed for cmd_send, ret =%d.",
3760                              ret);
3761                 return ret;
3762         }
3763
3764         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3765         retval = rte_le_to_cpu_16(desc.retval);
3766
3767         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3768 }
3769
3770 static void
3771 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3772                      int *table_item_num)
3773 {
3774         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3775
3776         /*
3777          * In current version, we add one item in management table as below:
3778          * 0x0180C200000E -- LLDP MC address
3779          */
3780         tbl = mgr_table;
3781         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3782         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3783         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3784         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3785         tbl->i_port_bitmap = 0x1;
3786         *table_item_num = 1;
3787 }
3788
3789 static int
3790 hns3_init_mgr_tbl(struct hns3_hw *hw)
3791 {
3792 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3793         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3794         int table_item_num;
3795         int ret;
3796         int i;
3797
3798         memset(mgr_table, 0, sizeof(mgr_table));
3799         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3800         for (i = 0; i < table_item_num; i++) {
3801                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3802                 if (ret) {
3803                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3804                                      ret);
3805                         return ret;
3806                 }
3807         }
3808
3809         return 0;
3810 }
3811
3812 static void
3813 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3814                         bool en_mc, bool en_bc, int vport_id)
3815 {
3816         if (!param)
3817                 return;
3818
3819         memset(param, 0, sizeof(struct hns3_promisc_param));
3820         if (en_uc)
3821                 param->enable = HNS3_PROMISC_EN_UC;
3822         if (en_mc)
3823                 param->enable |= HNS3_PROMISC_EN_MC;
3824         if (en_bc)
3825                 param->enable |= HNS3_PROMISC_EN_BC;
3826         param->vf_id = vport_id;
3827 }
3828
3829 static int
3830 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3831 {
3832         struct hns3_promisc_cfg_cmd *req;
3833         struct hns3_cmd_desc desc;
3834         int ret;
3835
3836         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3837
3838         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3839         req->vf_id = param->vf_id;
3840         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3841             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3842
3843         ret = hns3_cmd_send(hw, &desc, 1);
3844         if (ret)
3845                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3846
3847         return ret;
3848 }
3849
3850 static int
3851 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3852 {
3853         struct hns3_promisc_param param;
3854         bool en_bc_pmc = true;
3855         uint8_t vf_id;
3856
3857         /*
3858          * In current version VF is not supported when PF is driven by DPDK
3859          * driver, just need to configure parameters for PF vport.
3860          */
3861         vf_id = HNS3_PF_FUNC_ID;
3862
3863         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3864         return hns3_cmd_set_promisc_mode(hw, &param);
3865 }
3866
3867 static int
3868 hns3_promisc_init(struct hns3_hw *hw)
3869 {
3870         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3871         struct hns3_pf *pf = &hns->pf;
3872         struct hns3_promisc_param param;
3873         uint16_t func_id;
3874         int ret;
3875
3876         ret = hns3_set_promisc_mode(hw, false, false);
3877         if (ret) {
3878                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3879                 return ret;
3880         }
3881
3882         /*
3883          * In current version VFs are not supported when PF is driven by DPDK
3884          * driver. After PF has been taken over by DPDK, the original VF will
3885          * be invalid. So, there is a possibility of entry residues. It should
3886          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3887          * during init.
3888          */
3889         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3890                 hns3_promisc_param_init(&param, false, false, false, func_id);
3891                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3892                 if (ret) {
3893                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3894                                         " ret = %d", func_id, ret);
3895                         return ret;
3896                 }
3897         }
3898
3899         return 0;
3900 }
3901
3902 static void
3903 hns3_promisc_uninit(struct hns3_hw *hw)
3904 {
3905         struct hns3_promisc_param param;
3906         uint16_t func_id;
3907         int ret;
3908
3909         func_id = HNS3_PF_FUNC_ID;
3910
3911         /*
3912          * In current version VFs are not supported when PF is driven by
3913          * DPDK driver, and VFs' promisc mode status has been cleared during
3914          * init and their status will not change. So just clear PF's promisc
3915          * mode status during uninit.
3916          */
3917         hns3_promisc_param_init(&param, false, false, false, func_id);
3918         ret = hns3_cmd_set_promisc_mode(hw, &param);
3919         if (ret)
3920                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3921                                 " uninit, ret = %d", ret);
3922 }
3923
3924 static int
3925 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3926 {
3927         bool allmulti = dev->data->all_multicast ? true : false;
3928         struct hns3_adapter *hns = dev->data->dev_private;
3929         struct hns3_hw *hw = &hns->hw;
3930         uint64_t offloads;
3931         int err;
3932         int ret;
3933
3934         rte_spinlock_lock(&hw->lock);
3935         ret = hns3_set_promisc_mode(hw, true, true);
3936         if (ret) {
3937                 rte_spinlock_unlock(&hw->lock);
3938                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3939                          ret);
3940                 return ret;
3941         }
3942
3943         /*
3944          * When promiscuous mode was enabled, disable the vlan filter to let
3945          * all packets coming in in the receiving direction.
3946          */
3947         offloads = dev->data->dev_conf.rxmode.offloads;
3948         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3949                 ret = hns3_enable_vlan_filter(hns, false);
3950                 if (ret) {
3951                         hns3_err(hw, "failed to enable promiscuous mode due to "
3952                                      "failure to disable vlan filter, ret = %d",
3953                                  ret);
3954                         err = hns3_set_promisc_mode(hw, false, allmulti);
3955                         if (err)
3956                                 hns3_err(hw, "failed to restore promiscuous "
3957                                          "status after disable vlan filter "
3958                                          "failed during enabling promiscuous "
3959                                          "mode, ret = %d", ret);
3960                 }
3961         }
3962
3963         rte_spinlock_unlock(&hw->lock);
3964
3965         return ret;
3966 }
3967
3968 static int
3969 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3970 {
3971         bool allmulti = dev->data->all_multicast ? true : false;
3972         struct hns3_adapter *hns = dev->data->dev_private;
3973         struct hns3_hw *hw = &hns->hw;
3974         uint64_t offloads;
3975         int err;
3976         int ret;
3977
3978         /* If now in all_multicast mode, must remain in all_multicast mode. */
3979         rte_spinlock_lock(&hw->lock);
3980         ret = hns3_set_promisc_mode(hw, false, allmulti);
3981         if (ret) {
3982                 rte_spinlock_unlock(&hw->lock);
3983                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3984                          ret);
3985                 return ret;
3986         }
3987         /* when promiscuous mode was disabled, restore the vlan filter status */
3988         offloads = dev->data->dev_conf.rxmode.offloads;
3989         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3990                 ret = hns3_enable_vlan_filter(hns, true);
3991                 if (ret) {
3992                         hns3_err(hw, "failed to disable promiscuous mode due to"
3993                                  " failure to restore vlan filter, ret = %d",
3994                                  ret);
3995                         err = hns3_set_promisc_mode(hw, true, true);
3996                         if (err)
3997                                 hns3_err(hw, "failed to restore promiscuous "
3998                                          "status after enabling vlan filter "
3999                                          "failed during disabling promiscuous "
4000                                          "mode, ret = %d", ret);
4001                 }
4002         }
4003         rte_spinlock_unlock(&hw->lock);
4004
4005         return ret;
4006 }
4007
4008 static int
4009 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4010 {
4011         struct hns3_adapter *hns = dev->data->dev_private;
4012         struct hns3_hw *hw = &hns->hw;
4013         int ret;
4014
4015         if (dev->data->promiscuous)
4016                 return 0;
4017
4018         rte_spinlock_lock(&hw->lock);
4019         ret = hns3_set_promisc_mode(hw, false, true);
4020         rte_spinlock_unlock(&hw->lock);
4021         if (ret)
4022                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4023                          ret);
4024
4025         return ret;
4026 }
4027
4028 static int
4029 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4030 {
4031         struct hns3_adapter *hns = dev->data->dev_private;
4032         struct hns3_hw *hw = &hns->hw;
4033         int ret;
4034
4035         /* If now in promiscuous mode, must remain in all_multicast mode. */
4036         if (dev->data->promiscuous)
4037                 return 0;
4038
4039         rte_spinlock_lock(&hw->lock);
4040         ret = hns3_set_promisc_mode(hw, false, false);
4041         rte_spinlock_unlock(&hw->lock);
4042         if (ret)
4043                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4044                          ret);
4045
4046         return ret;
4047 }
4048
4049 static int
4050 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4051 {
4052         struct hns3_hw *hw = &hns->hw;
4053         bool allmulti = hw->data->all_multicast ? true : false;
4054         int ret;
4055
4056         if (hw->data->promiscuous) {
4057                 ret = hns3_set_promisc_mode(hw, true, true);
4058                 if (ret)
4059                         hns3_err(hw, "failed to restore promiscuous mode, "
4060                                  "ret = %d", ret);
4061                 return ret;
4062         }
4063
4064         ret = hns3_set_promisc_mode(hw, false, allmulti);
4065         if (ret)
4066                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4067                          ret);
4068         return ret;
4069 }
4070
4071 static int
4072 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4073 {
4074         struct hns3_sfp_speed_cmd *resp;
4075         struct hns3_cmd_desc desc;
4076         int ret;
4077
4078         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4079         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4080         ret = hns3_cmd_send(hw, &desc, 1);
4081         if (ret == -EOPNOTSUPP) {
4082                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4083                 return ret;
4084         } else if (ret) {
4085                 hns3_err(hw, "get sfp speed failed %d", ret);
4086                 return ret;
4087         }
4088
4089         *speed = resp->sfp_speed;
4090
4091         return 0;
4092 }
4093
4094 static uint8_t
4095 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4096 {
4097         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4098                 duplex = ETH_LINK_FULL_DUPLEX;
4099
4100         return duplex;
4101 }
4102
4103 static int
4104 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4105 {
4106         struct hns3_mac *mac = &hw->mac;
4107         int ret;
4108
4109         duplex = hns3_check_speed_dup(duplex, speed);
4110         if (mac->link_speed == speed && mac->link_duplex == duplex)
4111                 return 0;
4112
4113         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4114         if (ret)
4115                 return ret;
4116
4117         mac->link_speed = speed;
4118         mac->link_duplex = duplex;
4119
4120         return 0;
4121 }
4122
4123 static int
4124 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4125 {
4126         struct hns3_adapter *hns = eth_dev->data->dev_private;
4127         struct hns3_hw *hw = &hns->hw;
4128         struct hns3_pf *pf = &hns->pf;
4129         uint32_t speed;
4130         int ret;
4131
4132         /* If IMP do not support get SFP/qSFP speed, return directly */
4133         if (!pf->support_sfp_query)
4134                 return 0;
4135
4136         ret = hns3_get_sfp_speed(hw, &speed);
4137         if (ret == -EOPNOTSUPP) {
4138                 pf->support_sfp_query = false;
4139                 return ret;
4140         } else if (ret)
4141                 return ret;
4142
4143         if (speed == ETH_SPEED_NUM_NONE)
4144                 return 0; /* do nothing if no SFP */
4145
4146         /* Config full duplex for SFP */
4147         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4148 }
4149
4150 static int
4151 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4152 {
4153         struct hns3_config_mac_mode_cmd *req;
4154         struct hns3_cmd_desc desc;
4155         uint32_t loop_en = 0;
4156         uint8_t val = 0;
4157         int ret;
4158
4159         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4160
4161         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4162         if (enable)
4163                 val = 1;
4164         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4165         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4166         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4167         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4168         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4169         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4170         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4171         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4172         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4173         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4174         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4175         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4176         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4177         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4178         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4179
4180         ret = hns3_cmd_send(hw, &desc, 1);
4181         if (ret)
4182                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4183
4184         return ret;
4185 }
4186
4187 static int
4188 hns3_get_mac_link_status(struct hns3_hw *hw)
4189 {
4190         struct hns3_link_status_cmd *req;
4191         struct hns3_cmd_desc desc;
4192         int link_status;
4193         int ret;
4194
4195         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4196         ret = hns3_cmd_send(hw, &desc, 1);
4197         if (ret) {
4198                 hns3_err(hw, "get link status cmd failed %d", ret);
4199                 return ETH_LINK_DOWN;
4200         }
4201
4202         req = (struct hns3_link_status_cmd *)desc.data;
4203         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4204
4205         return !!link_status;
4206 }
4207
4208 void
4209 hns3_update_link_status(struct hns3_hw *hw)
4210 {
4211         int state;
4212
4213         state = hns3_get_mac_link_status(hw);
4214         if (state != hw->mac.link_status) {
4215                 hw->mac.link_status = state;
4216                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4217         }
4218 }
4219
4220 static void
4221 hns3_service_handler(void *param)
4222 {
4223         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4224         struct hns3_adapter *hns = eth_dev->data->dev_private;
4225         struct hns3_hw *hw = &hns->hw;
4226
4227         if (!hns3_is_reset_pending(hns)) {
4228                 hns3_update_speed_duplex(eth_dev);
4229                 hns3_update_link_status(hw);
4230         } else
4231                 hns3_warn(hw, "Cancel the query when reset is pending");
4232
4233         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4234 }
4235
4236 static int
4237 hns3_init_hardware(struct hns3_adapter *hns)
4238 {
4239         struct hns3_hw *hw = &hns->hw;
4240         int ret;
4241
4242         ret = hns3_map_tqp(hw);
4243         if (ret) {
4244                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4245                 return ret;
4246         }
4247
4248         ret = hns3_init_umv_space(hw);
4249         if (ret) {
4250                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4251                 return ret;
4252         }
4253
4254         ret = hns3_mac_init(hw);
4255         if (ret) {
4256                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4257                 goto err_mac_init;
4258         }
4259
4260         ret = hns3_init_mgr_tbl(hw);
4261         if (ret) {
4262                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4263                 goto err_mac_init;
4264         }
4265
4266         ret = hns3_promisc_init(hw);
4267         if (ret) {
4268                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4269                              ret);
4270                 goto err_mac_init;
4271         }
4272
4273         ret = hns3_init_vlan_config(hns);
4274         if (ret) {
4275                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4276                 goto err_mac_init;
4277         }
4278
4279         ret = hns3_dcb_init(hw);
4280         if (ret) {
4281                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4282                 goto err_mac_init;
4283         }
4284
4285         ret = hns3_init_fd_config(hns);
4286         if (ret) {
4287                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4288                 goto err_mac_init;
4289         }
4290
4291         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4292         if (ret) {
4293                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4294                 goto err_mac_init;
4295         }
4296
4297         ret = hns3_config_gro(hw, false);
4298         if (ret) {
4299                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4300                 goto err_mac_init;
4301         }
4302
4303         /*
4304          * In the initialization clearing the all hardware mapping relationship
4305          * configurations between queues and interrupt vectors is needed, so
4306          * some error caused by the residual configurations, such as the
4307          * unexpected interrupt, can be avoid.
4308          */
4309         ret = hns3_init_ring_with_vector(hw);
4310         if (ret) {
4311                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4312                 goto err_mac_init;
4313         }
4314
4315         return 0;
4316
4317 err_mac_init:
4318         hns3_uninit_umv_space(hw);
4319         return ret;
4320 }
4321
4322 static int
4323 hns3_clear_hw(struct hns3_hw *hw)
4324 {
4325         struct hns3_cmd_desc desc;
4326         int ret;
4327
4328         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4329
4330         ret = hns3_cmd_send(hw, &desc, 1);
4331         if (ret && ret != -EOPNOTSUPP)
4332                 return ret;
4333
4334         return 0;
4335 }
4336
4337 static int
4338 hns3_init_pf(struct rte_eth_dev *eth_dev)
4339 {
4340         struct rte_device *dev = eth_dev->device;
4341         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4342         struct hns3_adapter *hns = eth_dev->data->dev_private;
4343         struct hns3_hw *hw = &hns->hw;
4344         int ret;
4345
4346         PMD_INIT_FUNC_TRACE();
4347
4348         /* Get hardware io base address from pcie BAR2 IO space */
4349         hw->io_base = pci_dev->mem_resource[2].addr;
4350
4351         /* Firmware command queue initialize */
4352         ret = hns3_cmd_init_queue(hw);
4353         if (ret) {
4354                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4355                 goto err_cmd_init_queue;
4356         }
4357
4358         hns3_clear_all_event_cause(hw);
4359
4360         /* Firmware command initialize */
4361         ret = hns3_cmd_init(hw);
4362         if (ret) {
4363                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4364                 goto err_cmd_init;
4365         }
4366
4367         /*
4368          * To ensure that the hardware environment is clean during
4369          * initialization, the driver actively clear the hardware environment
4370          * during initialization, including PF and corresponding VFs' vlan, mac,
4371          * flow table configurations, etc.
4372          */
4373         ret = hns3_clear_hw(hw);
4374         if (ret) {
4375                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4376                 goto err_cmd_init;
4377         }
4378
4379         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4380                                          hns3_interrupt_handler,
4381                                          eth_dev);
4382         if (ret) {
4383                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4384                 goto err_intr_callback_register;
4385         }
4386
4387         /* Enable interrupt */
4388         rte_intr_enable(&pci_dev->intr_handle);
4389         hns3_pf_enable_irq0(hw);
4390
4391         /* Get configuration */
4392         ret = hns3_get_configuration(hw);
4393         if (ret) {
4394                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4395                 goto err_get_config;
4396         }
4397
4398         ret = hns3_init_hardware(hns);
4399         if (ret) {
4400                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4401                 goto err_get_config;
4402         }
4403
4404         /* Initialize flow director filter list & hash */
4405         ret = hns3_fdir_filter_init(hns);
4406         if (ret) {
4407                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4408                 goto err_hw_init;
4409         }
4410
4411         hns3_set_default_rss_args(hw);
4412
4413         ret = hns3_enable_hw_error_intr(hns, true);
4414         if (ret) {
4415                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4416                              ret);
4417                 goto err_fdir;
4418         }
4419
4420         return 0;
4421
4422 err_fdir:
4423         hns3_fdir_filter_uninit(hns);
4424 err_hw_init:
4425         hns3_uninit_umv_space(hw);
4426
4427 err_get_config:
4428         hns3_pf_disable_irq0(hw);
4429         rte_intr_disable(&pci_dev->intr_handle);
4430         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4431                              eth_dev);
4432 err_intr_callback_register:
4433 err_cmd_init:
4434         hns3_cmd_uninit(hw);
4435         hns3_cmd_destroy_queue(hw);
4436 err_cmd_init_queue:
4437         hw->io_base = NULL;
4438
4439         return ret;
4440 }
4441
4442 static void
4443 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4444 {
4445         struct hns3_adapter *hns = eth_dev->data->dev_private;
4446         struct rte_device *dev = eth_dev->device;
4447         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4448         struct hns3_hw *hw = &hns->hw;
4449
4450         PMD_INIT_FUNC_TRACE();
4451
4452         hns3_enable_hw_error_intr(hns, false);
4453         hns3_rss_uninit(hns);
4454         (void)hns3_config_gro(hw, false);
4455         hns3_promisc_uninit(hw);
4456         hns3_fdir_filter_uninit(hns);
4457         hns3_uninit_umv_space(hw);
4458         hns3_pf_disable_irq0(hw);
4459         rte_intr_disable(&pci_dev->intr_handle);
4460         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4461                              eth_dev);
4462         hns3_cmd_uninit(hw);
4463         hns3_cmd_destroy_queue(hw);
4464         hw->io_base = NULL;
4465 }
4466
4467 static int
4468 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4469 {
4470         struct hns3_hw *hw = &hns->hw;
4471         int ret;
4472
4473         ret = hns3_dcb_cfg_update(hns);
4474         if (ret)
4475                 return ret;
4476
4477         /* Enable queues */
4478         ret = hns3_start_queues(hns, reset_queue);
4479         if (ret) {
4480                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4481                 return ret;
4482         }
4483
4484         /* Enable MAC */
4485         ret = hns3_cfg_mac_mode(hw, true);
4486         if (ret) {
4487                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4488                 goto err_config_mac_mode;
4489         }
4490         return 0;
4491
4492 err_config_mac_mode:
4493         hns3_stop_queues(hns, true);
4494         return ret;
4495 }
4496
4497 static int
4498 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4499 {
4500         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4501         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4502         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4503         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4504         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4505         uint32_t intr_vector;
4506         uint16_t q_id;
4507         int ret;
4508
4509         if (dev->data->dev_conf.intr_conf.rxq == 0)
4510                 return 0;
4511
4512         /* disable uio/vfio intr/eventfd mapping */
4513         rte_intr_disable(intr_handle);
4514
4515         /* check and configure queue intr-vector mapping */
4516         if (rte_intr_cap_multiple(intr_handle) ||
4517             !RTE_ETH_DEV_SRIOV(dev).active) {
4518                 intr_vector = hw->used_rx_queues;
4519                 /* creates event fd for each intr vector when MSIX is used */
4520                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4521                         return -EINVAL;
4522         }
4523         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4524                 intr_handle->intr_vec =
4525                         rte_zmalloc("intr_vec",
4526                                     hw->used_rx_queues * sizeof(int), 0);
4527                 if (intr_handle->intr_vec == NULL) {
4528                         hns3_err(hw, "Failed to allocate %d rx_queues"
4529                                      " intr_vec", hw->used_rx_queues);
4530                         ret = -ENOMEM;
4531                         goto alloc_intr_vec_error;
4532                 }
4533         }
4534
4535         if (rte_intr_allow_others(intr_handle)) {
4536                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4537                 base = RTE_INTR_VEC_RXTX_OFFSET;
4538         }
4539         if (rte_intr_dp_is_en(intr_handle)) {
4540                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4541                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4542                                                          HNS3_RING_TYPE_RX,
4543                                                          q_id);
4544                         if (ret)
4545                                 goto bind_vector_error;
4546                         intr_handle->intr_vec[q_id] = vec;
4547                         if (vec < base + intr_handle->nb_efd - 1)
4548                                 vec++;
4549                 }
4550         }
4551         rte_intr_enable(intr_handle);
4552         return 0;
4553
4554 bind_vector_error:
4555         rte_intr_efd_disable(intr_handle);
4556         if (intr_handle->intr_vec) {
4557                 free(intr_handle->intr_vec);
4558                 intr_handle->intr_vec = NULL;
4559         }
4560         return ret;
4561 alloc_intr_vec_error:
4562         rte_intr_efd_disable(intr_handle);
4563         return ret;
4564 }
4565
4566 static int
4567 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4568 {
4569         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4570         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4571         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4572         uint16_t q_id;
4573         int ret;
4574
4575         if (dev->data->dev_conf.intr_conf.rxq == 0)
4576                 return 0;
4577
4578         if (rte_intr_dp_is_en(intr_handle)) {
4579                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4580                         ret = hns3_bind_ring_with_vector(hw,
4581                                         intr_handle->intr_vec[q_id], true,
4582                                         HNS3_RING_TYPE_RX, q_id);
4583                         if (ret)
4584                                 return ret;
4585                 }
4586         }
4587
4588         return 0;
4589 }
4590
4591 static void
4592 hns3_restore_filter(struct rte_eth_dev *dev)
4593 {
4594         hns3_restore_rss_filter(dev);
4595 }
4596
4597 static int
4598 hns3_dev_start(struct rte_eth_dev *dev)
4599 {
4600         struct hns3_adapter *hns = dev->data->dev_private;
4601         struct hns3_hw *hw = &hns->hw;
4602         int ret;
4603
4604         PMD_INIT_FUNC_TRACE();
4605         if (rte_atomic16_read(&hw->reset.resetting))
4606                 return -EBUSY;
4607
4608         rte_spinlock_lock(&hw->lock);
4609         hw->adapter_state = HNS3_NIC_STARTING;
4610
4611         ret = hns3_do_start(hns, true);
4612         if (ret) {
4613                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4614                 rte_spinlock_unlock(&hw->lock);
4615                 return ret;
4616         }
4617         ret = hns3_map_rx_interrupt(dev);
4618         if (ret) {
4619                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4620                 rte_spinlock_unlock(&hw->lock);
4621                 return ret;
4622         }
4623
4624         hw->adapter_state = HNS3_NIC_STARTED;
4625         rte_spinlock_unlock(&hw->lock);
4626
4627         hns3_set_rxtx_function(dev);
4628         hns3_mp_req_start_rxtx(dev);
4629         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4630
4631         hns3_restore_filter(dev);
4632
4633         /* Enable interrupt of all rx queues before enabling queues */
4634         hns3_dev_all_rx_queue_intr_enable(hw, true);
4635         /*
4636          * When finished the initialization, enable queues to receive/transmit
4637          * packets.
4638          */
4639         hns3_enable_all_queues(hw, true);
4640
4641         hns3_info(hw, "hns3 dev start successful!");
4642         return 0;
4643 }
4644
4645 static int
4646 hns3_do_stop(struct hns3_adapter *hns)
4647 {
4648         struct hns3_hw *hw = &hns->hw;
4649         bool reset_queue;
4650         int ret;
4651
4652         ret = hns3_cfg_mac_mode(hw, false);
4653         if (ret)
4654                 return ret;
4655         hw->mac.link_status = ETH_LINK_DOWN;
4656
4657         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4658                 hns3_configure_all_mac_addr(hns, true);
4659                 reset_queue = true;
4660         } else
4661                 reset_queue = false;
4662         hw->mac.default_addr_setted = false;
4663         return hns3_stop_queues(hns, reset_queue);
4664 }
4665
4666 static void
4667 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4668 {
4669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4671         struct hns3_adapter *hns = dev->data->dev_private;
4672         struct hns3_hw *hw = &hns->hw;
4673         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4674         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4675         uint16_t q_id;
4676
4677         if (dev->data->dev_conf.intr_conf.rxq == 0)
4678                 return;
4679
4680         /* unmap the ring with vector */
4681         if (rte_intr_allow_others(intr_handle)) {
4682                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4683                 base = RTE_INTR_VEC_RXTX_OFFSET;
4684         }
4685         if (rte_intr_dp_is_en(intr_handle)) {
4686                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4687                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4688                                                          HNS3_RING_TYPE_RX,
4689                                                          q_id);
4690                         if (vec < base + intr_handle->nb_efd - 1)
4691                                 vec++;
4692                 }
4693         }
4694         /* Clean datapath event and queue/vec mapping */
4695         rte_intr_efd_disable(intr_handle);
4696         if (intr_handle->intr_vec) {
4697                 rte_free(intr_handle->intr_vec);
4698                 intr_handle->intr_vec = NULL;
4699         }
4700 }
4701
4702 static void
4703 hns3_dev_stop(struct rte_eth_dev *dev)
4704 {
4705         struct hns3_adapter *hns = dev->data->dev_private;
4706         struct hns3_hw *hw = &hns->hw;
4707
4708         PMD_INIT_FUNC_TRACE();
4709
4710         hw->adapter_state = HNS3_NIC_STOPPING;
4711         hns3_set_rxtx_function(dev);
4712         rte_wmb();
4713         /* Disable datapath on secondary process. */
4714         hns3_mp_req_stop_rxtx(dev);
4715         /* Prevent crashes when queues are still in use. */
4716         rte_delay_ms(hw->tqps_num);
4717
4718         rte_spinlock_lock(&hw->lock);
4719         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4720                 hns3_do_stop(hns);
4721                 hns3_unmap_rx_interrupt(dev);
4722                 hns3_dev_release_mbufs(hns);
4723                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4724         }
4725         rte_eal_alarm_cancel(hns3_service_handler, dev);
4726         rte_spinlock_unlock(&hw->lock);
4727 }
4728
4729 static void
4730 hns3_dev_close(struct rte_eth_dev *eth_dev)
4731 {
4732         struct hns3_adapter *hns = eth_dev->data->dev_private;
4733         struct hns3_hw *hw = &hns->hw;
4734
4735         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4736                 rte_free(eth_dev->process_private);
4737                 eth_dev->process_private = NULL;
4738                 return;
4739         }
4740
4741         if (hw->adapter_state == HNS3_NIC_STARTED)
4742                 hns3_dev_stop(eth_dev);
4743
4744         hw->adapter_state = HNS3_NIC_CLOSING;
4745         hns3_reset_abort(hns);
4746         hw->adapter_state = HNS3_NIC_CLOSED;
4747
4748         hns3_configure_all_mc_mac_addr(hns, true);
4749         hns3_remove_all_vlan_table(hns);
4750         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4751         hns3_uninit_pf(eth_dev);
4752         hns3_free_all_queues(eth_dev);
4753         rte_free(hw->reset.wait_data);
4754         rte_free(eth_dev->process_private);
4755         eth_dev->process_private = NULL;
4756         hns3_mp_uninit_primary();
4757         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4758 }
4759
4760 static int
4761 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4762 {
4763         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4765
4766         fc_conf->pause_time = pf->pause_time;
4767
4768         /* return fc current mode */
4769         switch (hw->current_mode) {
4770         case HNS3_FC_FULL:
4771                 fc_conf->mode = RTE_FC_FULL;
4772                 break;
4773         case HNS3_FC_TX_PAUSE:
4774                 fc_conf->mode = RTE_FC_TX_PAUSE;
4775                 break;
4776         case HNS3_FC_RX_PAUSE:
4777                 fc_conf->mode = RTE_FC_RX_PAUSE;
4778                 break;
4779         case HNS3_FC_NONE:
4780         default:
4781                 fc_conf->mode = RTE_FC_NONE;
4782                 break;
4783         }
4784
4785         return 0;
4786 }
4787
4788 static void
4789 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4790 {
4791         switch (mode) {
4792         case RTE_FC_NONE:
4793                 hw->requested_mode = HNS3_FC_NONE;
4794                 break;
4795         case RTE_FC_RX_PAUSE:
4796                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4797                 break;
4798         case RTE_FC_TX_PAUSE:
4799                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4800                 break;
4801         case RTE_FC_FULL:
4802                 hw->requested_mode = HNS3_FC_FULL;
4803                 break;
4804         default:
4805                 hw->requested_mode = HNS3_FC_NONE;
4806                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4807                           "configured to RTE_FC_NONE", mode);
4808                 break;
4809         }
4810 }
4811
4812 static int
4813 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4814 {
4815         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4817         int ret;
4818
4819         if (fc_conf->high_water || fc_conf->low_water ||
4820             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4821                 hns3_err(hw, "Unsupported flow control settings specified, "
4822                          "high_water(%u), low_water(%u), send_xon(%u) and "
4823                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4824                          fc_conf->high_water, fc_conf->low_water,
4825                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4826                 return -EINVAL;
4827         }
4828         if (fc_conf->autoneg) {
4829                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4830                 return -EINVAL;
4831         }
4832         if (!fc_conf->pause_time) {
4833                 hns3_err(hw, "Invalid pause time %d setting.",
4834                          fc_conf->pause_time);
4835                 return -EINVAL;
4836         }
4837
4838         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4839             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4840                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4841                          "current_fc_status = %d", hw->current_fc_status);
4842                 return -EOPNOTSUPP;
4843         }
4844
4845         hns3_get_fc_mode(hw, fc_conf->mode);
4846         if (hw->requested_mode == hw->current_mode &&
4847             pf->pause_time == fc_conf->pause_time)
4848                 return 0;
4849
4850         rte_spinlock_lock(&hw->lock);
4851         ret = hns3_fc_enable(dev, fc_conf);
4852         rte_spinlock_unlock(&hw->lock);
4853
4854         return ret;
4855 }
4856
4857 static int
4858 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4859                             struct rte_eth_pfc_conf *pfc_conf)
4860 {
4861         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4863         uint8_t priority;
4864         int ret;
4865
4866         if (!hns3_dev_dcb_supported(hw)) {
4867                 hns3_err(hw, "This port does not support dcb configurations.");
4868                 return -EOPNOTSUPP;
4869         }
4870
4871         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4872             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4873                 hns3_err(hw, "Unsupported flow control settings specified, "
4874                          "high_water(%u), low_water(%u), send_xon(%u) and "
4875                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4876                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4877                          pfc_conf->fc.send_xon,
4878                          pfc_conf->fc.mac_ctrl_frame_fwd);
4879                 return -EINVAL;
4880         }
4881         if (pfc_conf->fc.autoneg) {
4882                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4883                 return -EINVAL;
4884         }
4885         if (pfc_conf->fc.pause_time == 0) {
4886                 hns3_err(hw, "Invalid pause time %d setting.",
4887                          pfc_conf->fc.pause_time);
4888                 return -EINVAL;
4889         }
4890
4891         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4892             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4893                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4894                              "current_fc_status = %d", hw->current_fc_status);
4895                 return -EOPNOTSUPP;
4896         }
4897
4898         priority = pfc_conf->priority;
4899         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4900         if (hw->dcb_info.pfc_en & BIT(priority) &&
4901             hw->requested_mode == hw->current_mode &&
4902             pfc_conf->fc.pause_time == pf->pause_time)
4903                 return 0;
4904
4905         rte_spinlock_lock(&hw->lock);
4906         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4907         rte_spinlock_unlock(&hw->lock);
4908
4909         return ret;
4910 }
4911
4912 static int
4913 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4914 {
4915         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4916         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4917         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4918         int i;
4919
4920         rte_spinlock_lock(&hw->lock);
4921         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4922                 dcb_info->nb_tcs = pf->local_max_tc;
4923         else
4924                 dcb_info->nb_tcs = 1;
4925
4926         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4927                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4928         for (i = 0; i < dcb_info->nb_tcs; i++)
4929                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4930
4931         for (i = 0; i < hw->num_tc; i++) {
4932                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4933                 dcb_info->tc_queue.tc_txq[0][i].base =
4934                                                 hw->tc_queue[i].tqp_offset;
4935                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4936                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4937                                                 hw->tc_queue[i].tqp_count;
4938         }
4939         rte_spinlock_unlock(&hw->lock);
4940
4941         return 0;
4942 }
4943
4944 static int
4945 hns3_reinit_dev(struct hns3_adapter *hns)
4946 {
4947         struct hns3_hw *hw = &hns->hw;
4948         int ret;
4949
4950         ret = hns3_cmd_init(hw);
4951         if (ret) {
4952                 hns3_err(hw, "Failed to init cmd: %d", ret);
4953                 return ret;
4954         }
4955
4956         ret = hns3_reset_all_queues(hns);
4957         if (ret) {
4958                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4959                 return ret;
4960         }
4961
4962         ret = hns3_init_hardware(hns);
4963         if (ret) {
4964                 hns3_err(hw, "Failed to init hardware: %d", ret);
4965                 return ret;
4966         }
4967
4968         ret = hns3_enable_hw_error_intr(hns, true);
4969         if (ret) {
4970                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4971                              ret);
4972                 return ret;
4973         }
4974         hns3_info(hw, "Reset done, driver initialization finished.");
4975
4976         return 0;
4977 }
4978
4979 static bool
4980 is_pf_reset_done(struct hns3_hw *hw)
4981 {
4982         uint32_t val, reg, reg_bit;
4983
4984         switch (hw->reset.level) {
4985         case HNS3_IMP_RESET:
4986                 reg = HNS3_GLOBAL_RESET_REG;
4987                 reg_bit = HNS3_IMP_RESET_BIT;
4988                 break;
4989         case HNS3_GLOBAL_RESET:
4990                 reg = HNS3_GLOBAL_RESET_REG;
4991                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4992                 break;
4993         case HNS3_FUNC_RESET:
4994                 reg = HNS3_FUN_RST_ING;
4995                 reg_bit = HNS3_FUN_RST_ING_B;
4996                 break;
4997         case HNS3_FLR_RESET:
4998         default:
4999                 hns3_err(hw, "Wait for unsupported reset level: %d",
5000                          hw->reset.level);
5001                 return true;
5002         }
5003         val = hns3_read_dev(hw, reg);
5004         if (hns3_get_bit(val, reg_bit))
5005                 return false;
5006         else
5007                 return true;
5008 }
5009
5010 bool
5011 hns3_is_reset_pending(struct hns3_adapter *hns)
5012 {
5013         struct hns3_hw *hw = &hns->hw;
5014         enum hns3_reset_level reset;
5015
5016         hns3_check_event_cause(hns, NULL);
5017         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5018         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5019                 hns3_warn(hw, "High level reset %d is pending", reset);
5020                 return true;
5021         }
5022         reset = hns3_get_reset_level(hns, &hw->reset.request);
5023         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5024                 hns3_warn(hw, "High level reset %d is request", reset);
5025                 return true;
5026         }
5027         return false;
5028 }
5029
5030 static int
5031 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5032 {
5033         struct hns3_hw *hw = &hns->hw;
5034         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5035         struct timeval tv;
5036
5037         if (wait_data->result == HNS3_WAIT_SUCCESS)
5038                 return 0;
5039         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5040                 gettimeofday(&tv, NULL);
5041                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5042                           tv.tv_sec, tv.tv_usec);
5043                 return -ETIME;
5044         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5045                 return -EAGAIN;
5046
5047         wait_data->hns = hns;
5048         wait_data->check_completion = is_pf_reset_done;
5049         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5050                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5051         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5052         wait_data->count = HNS3_RESET_WAIT_CNT;
5053         wait_data->result = HNS3_WAIT_REQUEST;
5054         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5055         return -EAGAIN;
5056 }
5057
5058 static int
5059 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5060 {
5061         struct hns3_cmd_desc desc;
5062         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5063
5064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5065         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5066         req->fun_reset_vfid = func_id;
5067
5068         return hns3_cmd_send(hw, &desc, 1);
5069 }
5070
5071 static int
5072 hns3_imp_reset_cmd(struct hns3_hw *hw)
5073 {
5074         struct hns3_cmd_desc desc;
5075
5076         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5077         desc.data[0] = 0xeedd;
5078
5079         return hns3_cmd_send(hw, &desc, 1);
5080 }
5081
5082 static void
5083 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5084 {
5085         struct hns3_hw *hw = &hns->hw;
5086         struct timeval tv;
5087         uint32_t val;
5088
5089         gettimeofday(&tv, NULL);
5090         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5091             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5092                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5093                           tv.tv_sec, tv.tv_usec);
5094                 return;
5095         }
5096
5097         switch (reset_level) {
5098         case HNS3_IMP_RESET:
5099                 hns3_imp_reset_cmd(hw);
5100                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5101                           tv.tv_sec, tv.tv_usec);
5102                 break;
5103         case HNS3_GLOBAL_RESET:
5104                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5105                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5106                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5107                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5108                           tv.tv_sec, tv.tv_usec);
5109                 break;
5110         case HNS3_FUNC_RESET:
5111                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5112                           tv.tv_sec, tv.tv_usec);
5113                 /* schedule again to check later */
5114                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5115                 hns3_schedule_reset(hns);
5116                 break;
5117         default:
5118                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5119                 return;
5120         }
5121         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5122 }
5123
5124 static enum hns3_reset_level
5125 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5126 {
5127         struct hns3_hw *hw = &hns->hw;
5128         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5129
5130         /* Return the highest priority reset level amongst all */
5131         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5132                 reset_level = HNS3_IMP_RESET;
5133         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5134                 reset_level = HNS3_GLOBAL_RESET;
5135         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5136                 reset_level = HNS3_FUNC_RESET;
5137         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5138                 reset_level = HNS3_FLR_RESET;
5139
5140         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5141                 return HNS3_NONE_RESET;
5142
5143         return reset_level;
5144 }
5145
5146 static int
5147 hns3_prepare_reset(struct hns3_adapter *hns)
5148 {
5149         struct hns3_hw *hw = &hns->hw;
5150         uint32_t reg_val;
5151         int ret;
5152
5153         switch (hw->reset.level) {
5154         case HNS3_FUNC_RESET:
5155                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5156                 if (ret)
5157                         return ret;
5158
5159                 /*
5160                  * After performaning pf reset, it is not necessary to do the
5161                  * mailbox handling or send any command to firmware, because
5162                  * any mailbox handling or command to firmware is only valid
5163                  * after hns3_cmd_init is called.
5164                  */
5165                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5166                 hw->reset.stats.request_cnt++;
5167                 break;
5168         case HNS3_IMP_RESET:
5169                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5170                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5171                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5172                 break;
5173         default:
5174                 break;
5175         }
5176         return 0;
5177 }
5178
5179 static int
5180 hns3_set_rst_done(struct hns3_hw *hw)
5181 {
5182         struct hns3_pf_rst_done_cmd *req;
5183         struct hns3_cmd_desc desc;
5184
5185         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5186         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5187         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5188         return hns3_cmd_send(hw, &desc, 1);
5189 }
5190
5191 static int
5192 hns3_stop_service(struct hns3_adapter *hns)
5193 {
5194         struct hns3_hw *hw = &hns->hw;
5195         struct rte_eth_dev *eth_dev;
5196
5197         eth_dev = &rte_eth_devices[hw->data->port_id];
5198         if (hw->adapter_state == HNS3_NIC_STARTED)
5199                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5200         hw->mac.link_status = ETH_LINK_DOWN;
5201
5202         hns3_set_rxtx_function(eth_dev);
5203         rte_wmb();
5204         /* Disable datapath on secondary process. */
5205         hns3_mp_req_stop_rxtx(eth_dev);
5206         rte_delay_ms(hw->tqps_num);
5207
5208         rte_spinlock_lock(&hw->lock);
5209         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5210             hw->adapter_state == HNS3_NIC_STOPPING) {
5211                 hns3_do_stop(hns);
5212                 hw->reset.mbuf_deferred_free = true;
5213         } else
5214                 hw->reset.mbuf_deferred_free = false;
5215
5216         /*
5217          * It is cumbersome for hardware to pick-and-choose entries for deletion
5218          * from table space. Hence, for function reset software intervention is
5219          * required to delete the entries
5220          */
5221         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5222                 hns3_configure_all_mc_mac_addr(hns, true);
5223         rte_spinlock_unlock(&hw->lock);
5224
5225         return 0;
5226 }
5227
5228 static int
5229 hns3_start_service(struct hns3_adapter *hns)
5230 {
5231         struct hns3_hw *hw = &hns->hw;
5232         struct rte_eth_dev *eth_dev;
5233
5234         if (hw->reset.level == HNS3_IMP_RESET ||
5235             hw->reset.level == HNS3_GLOBAL_RESET)
5236                 hns3_set_rst_done(hw);
5237         eth_dev = &rte_eth_devices[hw->data->port_id];
5238         hns3_set_rxtx_function(eth_dev);
5239         hns3_mp_req_start_rxtx(eth_dev);
5240         if (hw->adapter_state == HNS3_NIC_STARTED) {
5241                 hns3_service_handler(eth_dev);
5242
5243                 /* Enable interrupt of all rx queues before enabling queues */
5244                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5245                 /*
5246                  * When finished the initialization, enable queues to receive
5247                  * and transmit packets.
5248                  */
5249                 hns3_enable_all_queues(hw, true);
5250         }
5251
5252         return 0;
5253 }
5254
5255 static int
5256 hns3_restore_conf(struct hns3_adapter *hns)
5257 {
5258         struct hns3_hw *hw = &hns->hw;
5259         int ret;
5260
5261         ret = hns3_configure_all_mac_addr(hns, false);
5262         if (ret)
5263                 return ret;
5264
5265         ret = hns3_configure_all_mc_mac_addr(hns, false);
5266         if (ret)
5267                 goto err_mc_mac;
5268
5269         ret = hns3_dev_promisc_restore(hns);
5270         if (ret)
5271                 goto err_promisc;
5272
5273         ret = hns3_restore_vlan_table(hns);
5274         if (ret)
5275                 goto err_promisc;
5276
5277         ret = hns3_restore_vlan_conf(hns);
5278         if (ret)
5279                 goto err_promisc;
5280
5281         ret = hns3_restore_all_fdir_filter(hns);
5282         if (ret)
5283                 goto err_promisc;
5284
5285         ret = hns3_restore_rx_interrupt(hw);
5286         if (ret)
5287                 goto err_promisc;
5288
5289         ret = hns3_restore_gro_conf(hw);
5290         if (ret)
5291                 goto err_promisc;
5292
5293         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5294                 ret = hns3_do_start(hns, false);
5295                 if (ret)
5296                         goto err_promisc;
5297                 hns3_info(hw, "hns3 dev restart successful!");
5298         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5299                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5300         return 0;
5301
5302 err_promisc:
5303         hns3_configure_all_mc_mac_addr(hns, true);
5304 err_mc_mac:
5305         hns3_configure_all_mac_addr(hns, true);
5306         return ret;
5307 }
5308
5309 static void
5310 hns3_reset_service(void *param)
5311 {
5312         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5313         struct hns3_hw *hw = &hns->hw;
5314         enum hns3_reset_level reset_level;
5315         struct timeval tv_delta;
5316         struct timeval tv_start;
5317         struct timeval tv;
5318         uint64_t msec;
5319         int ret;
5320
5321         /*
5322          * The interrupt is not triggered within the delay time.
5323          * The interrupt may have been lost. It is necessary to handle
5324          * the interrupt to recover from the error.
5325          */
5326         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5327                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5328                 hns3_err(hw, "Handling interrupts in delayed tasks");
5329                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5330                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5331                 if (reset_level == HNS3_NONE_RESET) {
5332                         hns3_err(hw, "No reset level is set, try IMP reset");
5333                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5334                 }
5335         }
5336         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5337
5338         /*
5339          * Check if there is any ongoing reset in the hardware. This status can
5340          * be checked from reset_pending. If there is then, we need to wait for
5341          * hardware to complete reset.
5342          *    a. If we are able to figure out in reasonable time that hardware
5343          *       has fully resetted then, we can proceed with driver, client
5344          *       reset.
5345          *    b. else, we can come back later to check this status so re-sched
5346          *       now.
5347          */
5348         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5349         if (reset_level != HNS3_NONE_RESET) {
5350                 gettimeofday(&tv_start, NULL);
5351                 ret = hns3_reset_process(hns, reset_level);
5352                 gettimeofday(&tv, NULL);
5353                 timersub(&tv, &tv_start, &tv_delta);
5354                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5355                        tv_delta.tv_usec / USEC_PER_MSEC;
5356                 if (msec > HNS3_RESET_PROCESS_MS)
5357                         hns3_err(hw, "%d handle long time delta %" PRIx64
5358                                      " ms time=%ld.%.6ld",
5359                                  hw->reset.level, msec,
5360                                  tv.tv_sec, tv.tv_usec);
5361                 if (ret == -EAGAIN)
5362                         return;
5363         }
5364
5365         /* Check if we got any *new* reset requests to be honored */
5366         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5367         if (reset_level != HNS3_NONE_RESET)
5368                 hns3_msix_process(hns, reset_level);
5369 }
5370
5371 static const struct eth_dev_ops hns3_eth_dev_ops = {
5372         .dev_start          = hns3_dev_start,
5373         .dev_stop           = hns3_dev_stop,
5374         .dev_close          = hns3_dev_close,
5375         .promiscuous_enable = hns3_dev_promiscuous_enable,
5376         .promiscuous_disable = hns3_dev_promiscuous_disable,
5377         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5378         .allmulticast_disable = hns3_dev_allmulticast_disable,
5379         .mtu_set            = hns3_dev_mtu_set,
5380         .stats_get          = hns3_stats_get,
5381         .stats_reset        = hns3_stats_reset,
5382         .xstats_get         = hns3_dev_xstats_get,
5383         .xstats_get_names   = hns3_dev_xstats_get_names,
5384         .xstats_reset       = hns3_dev_xstats_reset,
5385         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5386         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5387         .dev_infos_get          = hns3_dev_infos_get,
5388         .fw_version_get         = hns3_fw_version_get,
5389         .rx_queue_setup         = hns3_rx_queue_setup,
5390         .tx_queue_setup         = hns3_tx_queue_setup,
5391         .rx_queue_release       = hns3_dev_rx_queue_release,
5392         .tx_queue_release       = hns3_dev_tx_queue_release,
5393         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5394         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5395         .dev_configure          = hns3_dev_configure,
5396         .flow_ctrl_get          = hns3_flow_ctrl_get,
5397         .flow_ctrl_set          = hns3_flow_ctrl_set,
5398         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5399         .mac_addr_add           = hns3_add_mac_addr,
5400         .mac_addr_remove        = hns3_remove_mac_addr,
5401         .mac_addr_set           = hns3_set_default_mac_addr,
5402         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5403         .link_update            = hns3_dev_link_update,
5404         .rss_hash_update        = hns3_dev_rss_hash_update,
5405         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5406         .reta_update            = hns3_dev_rss_reta_update,
5407         .reta_query             = hns3_dev_rss_reta_query,
5408         .filter_ctrl            = hns3_dev_filter_ctrl,
5409         .vlan_filter_set        = hns3_vlan_filter_set,
5410         .vlan_tpid_set          = hns3_vlan_tpid_set,
5411         .vlan_offload_set       = hns3_vlan_offload_set,
5412         .vlan_pvid_set          = hns3_vlan_pvid_set,
5413         .get_reg                = hns3_get_regs,
5414         .get_dcb_info           = hns3_get_dcb_info,
5415         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5416 };
5417
5418 static const struct hns3_reset_ops hns3_reset_ops = {
5419         .reset_service       = hns3_reset_service,
5420         .stop_service        = hns3_stop_service,
5421         .prepare_reset       = hns3_prepare_reset,
5422         .wait_hardware_ready = hns3_wait_hardware_ready,
5423         .reinit_dev          = hns3_reinit_dev,
5424         .restore_conf        = hns3_restore_conf,
5425         .start_service       = hns3_start_service,
5426 };
5427
5428 static int
5429 hns3_dev_init(struct rte_eth_dev *eth_dev)
5430 {
5431         struct hns3_adapter *hns = eth_dev->data->dev_private;
5432         struct hns3_hw *hw = &hns->hw;
5433         int ret;
5434
5435         PMD_INIT_FUNC_TRACE();
5436
5437         eth_dev->process_private = (struct hns3_process_private *)
5438             rte_zmalloc_socket("hns3_filter_list",
5439                                sizeof(struct hns3_process_private),
5440                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5441         if (eth_dev->process_private == NULL) {
5442                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5443                 return -ENOMEM;
5444         }
5445         /* initialize flow filter lists */
5446         hns3_filterlist_init(eth_dev);
5447
5448         hns3_set_rxtx_function(eth_dev);
5449         eth_dev->dev_ops = &hns3_eth_dev_ops;
5450         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5451                 hns3_mp_init_secondary();
5452                 hw->secondary_cnt++;
5453                 return 0;
5454         }
5455
5456         hns3_mp_init_primary();
5457         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5458         hns->is_vf = false;
5459         hw->data = eth_dev->data;
5460
5461         /*
5462          * Set default max packet size according to the mtu
5463          * default vale in DPDK frame.
5464          */
5465         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5466
5467         ret = hns3_reset_init(hw);
5468         if (ret)
5469                 goto err_init_reset;
5470         hw->reset.ops = &hns3_reset_ops;
5471
5472         ret = hns3_init_pf(eth_dev);
5473         if (ret) {
5474                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5475                 goto err_init_pf;
5476         }
5477
5478         /* Allocate memory for storing MAC addresses */
5479         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5480                                                sizeof(struct rte_ether_addr) *
5481                                                HNS3_UC_MACADDR_NUM, 0);
5482         if (eth_dev->data->mac_addrs == NULL) {
5483                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5484                              "to store MAC addresses",
5485                              sizeof(struct rte_ether_addr) *
5486                              HNS3_UC_MACADDR_NUM);
5487                 ret = -ENOMEM;
5488                 goto err_rte_zmalloc;
5489         }
5490
5491         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5492                             &eth_dev->data->mac_addrs[0]);
5493
5494         hw->adapter_state = HNS3_NIC_INITIALIZED;
5495         /*
5496          * Pass the information to the rte_eth_dev_close() that it should also
5497          * release the private port resources.
5498          */
5499         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5500
5501         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5502                 hns3_err(hw, "Reschedule reset service after dev_init");
5503                 hns3_schedule_reset(hns);
5504         } else {
5505                 /* IMP will wait ready flag before reset */
5506                 hns3_notify_reset_ready(hw, false);
5507         }
5508
5509         hns3_info(hw, "hns3 dev initialization successful!");
5510         return 0;
5511
5512 err_rte_zmalloc:
5513         hns3_uninit_pf(eth_dev);
5514
5515 err_init_pf:
5516         rte_free(hw->reset.wait_data);
5517 err_init_reset:
5518         eth_dev->dev_ops = NULL;
5519         eth_dev->rx_pkt_burst = NULL;
5520         eth_dev->tx_pkt_burst = NULL;
5521         eth_dev->tx_pkt_prepare = NULL;
5522         rte_free(eth_dev->process_private);
5523         eth_dev->process_private = NULL;
5524         return ret;
5525 }
5526
5527 static int
5528 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5529 {
5530         struct hns3_adapter *hns = eth_dev->data->dev_private;
5531         struct hns3_hw *hw = &hns->hw;
5532
5533         PMD_INIT_FUNC_TRACE();
5534
5535         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5536                 return -EPERM;
5537
5538         eth_dev->dev_ops = NULL;
5539         eth_dev->rx_pkt_burst = NULL;
5540         eth_dev->tx_pkt_burst = NULL;
5541         eth_dev->tx_pkt_prepare = NULL;
5542         if (hw->adapter_state < HNS3_NIC_CLOSING)
5543                 hns3_dev_close(eth_dev);
5544
5545         hw->adapter_state = HNS3_NIC_REMOVED;
5546         return 0;
5547 }
5548
5549 static int
5550 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5551                    struct rte_pci_device *pci_dev)
5552 {
5553         return rte_eth_dev_pci_generic_probe(pci_dev,
5554                                              sizeof(struct hns3_adapter),
5555                                              hns3_dev_init);
5556 }
5557
5558 static int
5559 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5560 {
5561         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5562 }
5563
5564 static const struct rte_pci_id pci_id_hns3_map[] = {
5565         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5566         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5567         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5568         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5569         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5570         { .vendor_id = 0, /* sentinel */ },
5571 };
5572
5573 static struct rte_pci_driver rte_hns3_pmd = {
5574         .id_table = pci_id_hns3_map,
5575         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5576         .probe = eth_hns3_pci_probe,
5577         .remove = eth_hns3_pci_remove,
5578 };
5579
5580 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5581 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5582 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5583 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5584 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);