net/hns3: fix VLAN PVID when configuring device
[dpdk.git] / drivers / net / hns3 / hns3_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018-2019 Hisilicon Limited.
3  */
4
5 #include <errno.h>
6 #include <stdarg.h>
7 #include <stdbool.h>
8 #include <stdio.h>
9 #include <stdint.h>
10 #include <inttypes.h>
11 #include <unistd.h>
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
16 #include <rte_dev.h>
17 #include <rte_eal.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
22 #include <rte_io.h>
23 #include <rte_log.h>
24 #include <rte_pci.h>
25
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
31 #include "hns3_dcb.h"
32 #include "hns3_mp.h"
33
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
36
37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
40 #define HNS3_INVLID_PVID                0xFFFF
41
42 #define HNS3_FILTER_TYPE_VF             0
43 #define HNS3_FILTER_TYPE_PORT           1
44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
53
54 /* Reset related Registers */
55 #define HNS3_GLOBAL_RESET_BIT           0
56 #define HNS3_CORE_RESET_BIT             1
57 #define HNS3_IMP_RESET_BIT              2
58 #define HNS3_FUN_RST_ING_B              0
59
60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
61
62 #define HNS3_RESET_WAIT_MS      100
63 #define HNS3_RESET_WAIT_CNT     200
64
65 int hns3_logtype_init;
66 int hns3_logtype_driver;
67
68 enum hns3_evt_cause {
69         HNS3_VECTOR0_EVENT_RST,
70         HNS3_VECTOR0_EVENT_MBX,
71         HNS3_VECTOR0_EVENT_ERR,
72         HNS3_VECTOR0_EVENT_OTHER,
73 };
74
75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
76                                                  uint64_t *levels);
77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
79                                     int on);
80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
81
82 static int hns3_add_mc_addr(struct hns3_hw *hw,
83                             struct rte_ether_addr *mac_addr);
84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
85                             struct rte_ether_addr *mac_addr);
86
87 static void
88 hns3_pf_disable_irq0(struct hns3_hw *hw)
89 {
90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
91 }
92
93 static void
94 hns3_pf_enable_irq0(struct hns3_hw *hw)
95 {
96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
97 }
98
99 static enum hns3_evt_cause
100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
101 {
102         struct hns3_hw *hw = &hns->hw;
103         uint32_t vector0_int_stats;
104         uint32_t cmdq_src_val;
105         uint32_t val;
106         enum hns3_evt_cause ret;
107
108         /* fetch the events from their corresponding regs */
109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
111
112         /*
113          * Assumption: If by any chance reset and mailbox events are reported
114          * together then we will only process reset event and defer the
115          * processing of the mailbox events. Since, we would have not cleared
116          * RX CMDQ event this time we would receive again another interrupt
117          * from H/W just for the mailbox.
118          */
119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
123                 if (clearval) {
124                         hw->reset.stats.imp_cnt++;
125                         hns3_warn(hw, "IMP reset detected, clear reset status");
126                 } else {
127                         hns3_schedule_delayed_reset(hns);
128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
129                 }
130
131                 ret = HNS3_VECTOR0_EVENT_RST;
132                 goto out;
133         }
134
135         /* Global reset */
136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
140                 if (clearval) {
141                         hw->reset.stats.global_cnt++;
142                         hns3_warn(hw, "Global reset detected, clear reset status");
143                 } else {
144                         hns3_schedule_delayed_reset(hns);
145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
146                 }
147
148                 ret = HNS3_VECTOR0_EVENT_RST;
149                 goto out;
150         }
151
152         /* check for vector0 msix event source */
153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
154                 val = vector0_int_stats;
155                 ret = HNS3_VECTOR0_EVENT_ERR;
156                 goto out;
157         }
158
159         /* check for vector0 mailbox(=CMDQ RX) event source */
160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
162                 val = cmdq_src_val;
163                 ret = HNS3_VECTOR0_EVENT_MBX;
164                 goto out;
165         }
166
167         if (clearval && (vector0_int_stats || cmdq_src_val))
168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
169                           vector0_int_stats, cmdq_src_val);
170         val = vector0_int_stats;
171         ret = HNS3_VECTOR0_EVENT_OTHER;
172 out:
173
174         if (clearval)
175                 *clearval = val;
176         return ret;
177 }
178
179 static void
180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
181 {
182         if (event_type == HNS3_VECTOR0_EVENT_RST)
183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
186 }
187
188 static void
189 hns3_clear_all_event_cause(struct hns3_hw *hw)
190 {
191         uint32_t vector0_int_stats;
192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
193
194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
195                 hns3_warn(hw, "Probe during IMP reset interrupt");
196
197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
198                 hns3_warn(hw, "Probe during Global reset interrupt");
199
200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
205 }
206
207 static void
208 hns3_interrupt_handler(void *param)
209 {
210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
211         struct hns3_adapter *hns = dev->data->dev_private;
212         struct hns3_hw *hw = &hns->hw;
213         enum hns3_evt_cause event_cause;
214         uint32_t clearval = 0;
215
216         /* Disable interrupt */
217         hns3_pf_disable_irq0(hw);
218
219         event_cause = hns3_check_event_cause(hns, &clearval);
220
221         /* vector 0 interrupt is shared with reset and mailbox source events. */
222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
223                 hns3_handle_msix_error(hns, &hw->reset.request);
224                 hns3_schedule_reset(hns);
225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
226                 hns3_schedule_reset(hns);
227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
228                 hns3_dev_handle_mbx_msg(hw);
229         else
230                 hns3_err(hw, "Received unknown event");
231
232         hns3_clear_event_cause(hw, event_cause, clearval);
233         /* Enable interrupt if it is not cause by reset */
234         hns3_pf_enable_irq0(hw);
235 }
236
237 static int
238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
239 {
240 #define HNS3_VLAN_ID_OFFSET_STEP        160
241 #define HNS3_VLAN_BYTE_SIZE             8
242         struct hns3_vlan_filter_pf_cfg_cmd *req;
243         struct hns3_hw *hw = &hns->hw;
244         uint8_t vlan_offset_byte_val;
245         struct hns3_cmd_desc desc;
246         uint8_t vlan_offset_byte;
247         uint8_t vlan_offset_base;
248         int ret;
249
250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
251
252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
254                            HNS3_VLAN_BYTE_SIZE;
255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
256
257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
258         req->vlan_offset = vlan_offset_base;
259         req->vlan_cfg = on ? 0 : 1;
260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
261
262         ret = hns3_cmd_send(hw, &desc, 1);
263         if (ret)
264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
265                          vlan_id, ret);
266
267         return ret;
268 }
269
270 static void
271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
272 {
273         struct hns3_user_vlan_table *vlan_entry;
274         struct hns3_pf *pf = &hns->pf;
275
276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
277                 if (vlan_entry->vlan_id == vlan_id) {
278                         if (vlan_entry->hd_tbl_status)
279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
280                         LIST_REMOVE(vlan_entry, next);
281                         rte_free(vlan_entry);
282                         break;
283                 }
284         }
285 }
286
287 static void
288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
289                         bool writen_to_tbl)
290 {
291         struct hns3_user_vlan_table *vlan_entry;
292         struct hns3_hw *hw = &hns->hw;
293         struct hns3_pf *pf = &hns->pf;
294
295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
296                 if (vlan_entry->vlan_id == vlan_id)
297                         return;
298         }
299
300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
301         if (vlan_entry == NULL) {
302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
303                 return;
304         }
305
306         vlan_entry->hd_tbl_status = writen_to_tbl;
307         vlan_entry->vlan_id = vlan_id;
308
309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
310 }
311
312 static int
313 hns3_restore_vlan_table(struct hns3_adapter *hns)
314 {
315         struct hns3_user_vlan_table *vlan_entry;
316         struct hns3_pf *pf = &hns->pf;
317         uint16_t vlan_id;
318         int ret = 0;
319
320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
321                 return hns3_vlan_pvid_configure(hns,
322                                                 pf->port_base_vlan_cfg.pvid, 1);
323
324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
325                 if (vlan_entry->hd_tbl_status) {
326                         vlan_id = vlan_entry->vlan_id;
327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
328                         if (ret)
329                                 break;
330                 }
331         }
332
333         return ret;
334 }
335
336 static int
337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
338 {
339         struct hns3_pf *pf = &hns->pf;
340         bool writen_to_tbl = false;
341         int ret = 0;
342
343         /*
344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
345          * for normal packet, deleting vlan id 0 is not allowed.
346          */
347         if (on == 0 && vlan_id == 0)
348                 return 0;
349
350         /*
351          * When port base vlan enabled, we use port base vlan as the vlan
352          * filter condition. In this case, we don't update vlan filter table
353          * when user add new vlan or remove exist vlan, just update the
354          * vlan list. The vlan id in vlan list will be writen in vlan filter
355          * table until port base vlan disabled
356          */
357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
359                 writen_to_tbl = true;
360         }
361
362         if (ret == 0 && vlan_id) {
363                 if (on)
364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
365                 else
366                         hns3_rm_dev_vlan_table(hns, vlan_id);
367         }
368         return ret;
369 }
370
371 static int
372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
373 {
374         struct hns3_adapter *hns = dev->data->dev_private;
375         struct hns3_hw *hw = &hns->hw;
376         int ret;
377
378         rte_spinlock_lock(&hw->lock);
379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
380         rte_spinlock_unlock(&hw->lock);
381         return ret;
382 }
383
384 static int
385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
386                          uint16_t tpid)
387 {
388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
390         struct hns3_hw *hw = &hns->hw;
391         struct hns3_cmd_desc desc;
392         int ret;
393
394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
397                 return -EINVAL;
398         }
399
400         if (tpid != RTE_ETHER_TYPE_VLAN) {
401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
402                 return -EINVAL;
403         }
404
405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
407
408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
416         }
417
418         ret = hns3_cmd_send(hw, &desc, 1);
419         if (ret) {
420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
421                          ret);
422                 return ret;
423         }
424
425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
426
427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
430
431         ret = hns3_cmd_send(hw, &desc, 1);
432         if (ret)
433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
434                          ret);
435         return ret;
436 }
437
438 static int
439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
440                    uint16_t tpid)
441 {
442         struct hns3_adapter *hns = dev->data->dev_private;
443         struct hns3_hw *hw = &hns->hw;
444         int ret;
445
446         rte_spinlock_lock(&hw->lock);
447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
448         rte_spinlock_unlock(&hw->lock);
449         return ret;
450 }
451
452 static int
453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
454                              struct hns3_rx_vtag_cfg *vcfg)
455 {
456         struct hns3_vport_vtag_rx_cfg_cmd *req;
457         struct hns3_hw *hw = &hns->hw;
458         struct hns3_cmd_desc desc;
459         uint16_t vport_id;
460         uint8_t bitmap;
461         int ret;
462
463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
464
465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
467                      vcfg->strip_tag1_en ? 1 : 0);
468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
469                      vcfg->strip_tag2_en ? 1 : 0);
470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
474
475         /*
476          * In current version VF is not supported when PF is driven by DPDK
477          * driver, the PF-related vf_id is 0, just need to configure parameters
478          * for vport_id 0.
479          */
480         vport_id = 0;
481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
483         req->vf_bitmap[req->vf_offset] = bitmap;
484
485         ret = hns3_cmd_send(hw, &desc, 1);
486         if (ret)
487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
488         return ret;
489 }
490
491 static void
492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
493                            struct hns3_rx_vtag_cfg *vcfg)
494 {
495         struct hns3_pf *pf = &hns->pf;
496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
497 }
498
499 static void
500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
501                            struct hns3_tx_vtag_cfg *vcfg)
502 {
503         struct hns3_pf *pf = &hns->pf;
504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
505 }
506
507 static int
508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
509 {
510         struct hns3_rx_vtag_cfg rxvlan_cfg;
511         struct hns3_pf *pf = &hns->pf;
512         struct hns3_hw *hw = &hns->hw;
513         int ret;
514
515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
516                 rxvlan_cfg.strip_tag1_en = false;
517                 rxvlan_cfg.strip_tag2_en = enable;
518         } else {
519                 rxvlan_cfg.strip_tag1_en = enable;
520                 rxvlan_cfg.strip_tag2_en = true;
521         }
522
523         rxvlan_cfg.vlan1_vlan_prionly = false;
524         rxvlan_cfg.vlan2_vlan_prionly = false;
525         rxvlan_cfg.rx_vlan_offload_en = enable;
526
527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
528         if (ret) {
529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
530                 return ret;
531         }
532
533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
534
535         return ret;
536 }
537
538 static int
539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
541 {
542         struct hns3_vlan_filter_ctrl_cmd *req;
543         struct hns3_cmd_desc desc;
544         int ret;
545
546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
547
548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
549         req->vlan_type = vlan_type;
550         req->vlan_fe = filter_en ? fe_type : 0;
551         req->vf_id = vf_id;
552
553         ret = hns3_cmd_send(hw, &desc, 1);
554         if (ret)
555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
556
557         return ret;
558 }
559
560 static int
561 hns3_vlan_filter_init(struct hns3_adapter *hns)
562 {
563         struct hns3_hw *hw = &hns->hw;
564         int ret;
565
566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
567                                         HNS3_FILTER_FE_EGRESS, false, 0);
568         if (ret) {
569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
570                 return ret;
571         }
572
573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
574                                         HNS3_FILTER_FE_INGRESS, false, 0);
575         if (ret)
576                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
577
578         return ret;
579 }
580
581 static int
582 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
583 {
584         struct hns3_hw *hw = &hns->hw;
585         int ret;
586
587         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
588                                         HNS3_FILTER_FE_INGRESS, enable, 0);
589         if (ret)
590                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
591                          enable ? "enable" : "disable", ret);
592
593         return ret;
594 }
595
596 static int
597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
598 {
599         struct hns3_adapter *hns = dev->data->dev_private;
600         struct hns3_hw *hw = &hns->hw;
601         struct rte_eth_rxmode *rxmode;
602         unsigned int tmp_mask;
603         bool enable;
604         int ret = 0;
605
606         rte_spinlock_lock(&hw->lock);
607         rxmode = &dev->data->dev_conf.rxmode;
608         tmp_mask = (unsigned int)mask;
609         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
610                 /* ignore vlan filter configuration during promiscuous mode */
611                 if (!dev->data->promiscuous) {
612                         /* Enable or disable VLAN filter */
613                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
614                                  true : false;
615
616                         ret = hns3_enable_vlan_filter(hns, enable);
617                         if (ret) {
618                                 rte_spinlock_unlock(&hw->lock);
619                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
620                                          enable ? "enable" : "disable", ret);
621                                 return ret;
622                         }
623                 }
624         }
625
626         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
627                 /* Enable or disable VLAN stripping */
628                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
629                     true : false;
630
631                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
632                 if (ret) {
633                         rte_spinlock_unlock(&hw->lock);
634                         hns3_err(hw, "failed to %s rx strip, ret = %d",
635                                  enable ? "enable" : "disable", ret);
636                         return ret;
637                 }
638         }
639
640         rte_spinlock_unlock(&hw->lock);
641
642         return ret;
643 }
644
645 static int
646 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
647                              struct hns3_tx_vtag_cfg *vcfg)
648 {
649         struct hns3_vport_vtag_tx_cfg_cmd *req;
650         struct hns3_cmd_desc desc;
651         struct hns3_hw *hw = &hns->hw;
652         uint16_t vport_id;
653         uint8_t bitmap;
654         int ret;
655
656         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
657
658         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
659         req->def_vlan_tag1 = vcfg->default_tag1;
660         req->def_vlan_tag2 = vcfg->default_tag2;
661         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
662                      vcfg->accept_tag1 ? 1 : 0);
663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
664                      vcfg->accept_untag1 ? 1 : 0);
665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
666                      vcfg->accept_tag2 ? 1 : 0);
667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
668                      vcfg->accept_untag2 ? 1 : 0);
669         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
670                      vcfg->insert_tag1_en ? 1 : 0);
671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
672                      vcfg->insert_tag2_en ? 1 : 0);
673         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
674
675         /*
676          * In current version VF is not supported when PF is driven by DPDK
677          * driver, the PF-related vf_id is 0, just need to configure parameters
678          * for vport_id 0.
679          */
680         vport_id = 0;
681         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
682         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
683         req->vf_bitmap[req->vf_offset] = bitmap;
684
685         ret = hns3_cmd_send(hw, &desc, 1);
686         if (ret)
687                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
688
689         return ret;
690 }
691
692 static int
693 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
694                      uint16_t pvid)
695 {
696         struct hns3_hw *hw = &hns->hw;
697         struct hns3_tx_vtag_cfg txvlan_cfg;
698         int ret;
699
700         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
701                 txvlan_cfg.accept_tag1 = true;
702                 txvlan_cfg.insert_tag1_en = false;
703                 txvlan_cfg.default_tag1 = 0;
704         } else {
705                 txvlan_cfg.accept_tag1 = false;
706                 txvlan_cfg.insert_tag1_en = true;
707                 txvlan_cfg.default_tag1 = pvid;
708         }
709
710         txvlan_cfg.accept_untag1 = true;
711         txvlan_cfg.accept_tag2 = true;
712         txvlan_cfg.accept_untag2 = true;
713         txvlan_cfg.insert_tag2_en = false;
714         txvlan_cfg.default_tag2 = 0;
715
716         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
717         if (ret) {
718                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
719                          ret);
720                 return ret;
721         }
722
723         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
724         return ret;
725 }
726
727 static void
728 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
729 {
730         struct hns3_pf *pf = &hns->pf;
731
732         pf->port_base_vlan_cfg.state = on ?
733             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
734
735         pf->port_base_vlan_cfg.pvid = pvid;
736 }
737
738 static void
739 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
740 {
741         struct hns3_user_vlan_table *vlan_entry;
742         struct hns3_pf *pf = &hns->pf;
743
744         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
745                 if (vlan_entry->hd_tbl_status)
746                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
747
748                 vlan_entry->hd_tbl_status = false;
749         }
750
751         if (is_del_list) {
752                 vlan_entry = LIST_FIRST(&pf->vlan_list);
753                 while (vlan_entry) {
754                         LIST_REMOVE(vlan_entry, next);
755                         rte_free(vlan_entry);
756                         vlan_entry = LIST_FIRST(&pf->vlan_list);
757                 }
758         }
759 }
760
761 static void
762 hns3_add_all_vlan_table(struct hns3_adapter *hns)
763 {
764         struct hns3_user_vlan_table *vlan_entry;
765         struct hns3_pf *pf = &hns->pf;
766
767         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
768                 if (!vlan_entry->hd_tbl_status)
769                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
770
771                 vlan_entry->hd_tbl_status = true;
772         }
773 }
774
775 static void
776 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
777 {
778         struct hns3_hw *hw = &hns->hw;
779         struct hns3_pf *pf = &hns->pf;
780         int ret;
781
782         hns3_rm_all_vlan_table(hns, true);
783         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
784                 ret = hns3_set_port_vlan_filter(hns,
785                                                 pf->port_base_vlan_cfg.pvid, 0);
786                 if (ret) {
787                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
788                                  ret);
789                         return;
790                 }
791         }
792 }
793
794 static int
795 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
796                                 uint16_t port_base_vlan_state,
797                                 uint16_t new_pvid, uint16_t old_pvid)
798 {
799         struct hns3_pf *pf = &hns->pf;
800         struct hns3_hw *hw = &hns->hw;
801         int ret = 0;
802
803         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
804                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
805                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
806                         if (ret) {
807                                 hns3_err(hw,
808                                          "Failed to clear clear old pvid filter, ret =%d",
809                                          ret);
810                                 return ret;
811                         }
812                 }
813
814                 hns3_rm_all_vlan_table(hns, false);
815                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
816         }
817
818         if (new_pvid != 0) {
819                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
820                 if (ret) {
821                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
822                                  ret);
823                         return ret;
824                 }
825         }
826
827         if (new_pvid == pf->port_base_vlan_cfg.pvid)
828                 hns3_add_all_vlan_table(hns);
829
830         return ret;
831 }
832
833 static int
834 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
835 {
836         struct hns3_rx_vtag_cfg rx_vlan_cfg;
837         struct hns3_hw *hw = &hns->hw;
838         bool rx_strip_en;
839         int ret;
840
841         rx_strip_en = on ? true : false;
842         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
843         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
844         rx_vlan_cfg.vlan1_vlan_prionly = false;
845         rx_vlan_cfg.vlan2_vlan_prionly = false;
846         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
847
848         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
849         if (ret) {
850                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
851                 return ret;
852         }
853
854         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
855         return ret;
856 }
857
858 static int
859 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
860 {
861         struct hns3_pf *pf = &hns->pf;
862         struct hns3_hw *hw = &hns->hw;
863         uint16_t port_base_vlan_state;
864         uint16_t old_pvid;
865         int ret;
866
867         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
868                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
869                         hns3_warn(hw, "Invalid operation! As current pvid set "
870                                   "is %u, disable pvid %u is invalid",
871                                   pf->port_base_vlan_cfg.pvid, pvid);
872                 return 0;
873         }
874
875         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
876                                     HNS3_PORT_BASE_VLAN_DISABLE;
877         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
878         if (ret) {
879                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
880                 return ret;
881         }
882
883         ret = hns3_en_rx_strip_all(hns, on);
884         if (ret) {
885                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
886                 return ret;
887         }
888
889         if (pvid == HNS3_INVLID_PVID)
890                 goto out;
891         old_pvid = pf->port_base_vlan_cfg.pvid;
892         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
893                                               old_pvid);
894         if (ret) {
895                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
896                          ret);
897                 return ret;
898         }
899
900 out:
901         hns3_store_port_base_vlan_info(hns, pvid, on);
902         return ret;
903 }
904
905 static int
906 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
907 {
908         struct hns3_adapter *hns = dev->data->dev_private;
909         struct hns3_hw *hw = &hns->hw;
910         int ret;
911
912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
914                          RTE_ETHER_MAX_VLAN_ID);
915                 return -EINVAL;
916         }
917
918         rte_spinlock_lock(&hw->lock);
919         ret = hns3_vlan_pvid_configure(hns, pvid, on);
920         rte_spinlock_unlock(&hw->lock);
921         return ret;
922 }
923
924 static void
925 init_port_base_vlan_info(struct hns3_hw *hw)
926 {
927         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
928         struct hns3_pf *pf = &hns->pf;
929
930         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
931         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
932 }
933
934 static int
935 hns3_default_vlan_config(struct hns3_adapter *hns)
936 {
937         struct hns3_hw *hw = &hns->hw;
938         int ret;
939
940         ret = hns3_set_port_vlan_filter(hns, 0, 1);
941         if (ret)
942                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
943         return ret;
944 }
945
946 static int
947 hns3_init_vlan_config(struct hns3_adapter *hns)
948 {
949         struct hns3_hw *hw = &hns->hw;
950         int ret;
951
952         /*
953          * This function can be called in the initialization and reset process,
954          * when in reset process, it means that hardware had been reseted
955          * successfully and we need to restore the hardware configuration to
956          * ensure that the hardware configuration remains unchanged before and
957          * after reset.
958          */
959         if (rte_atomic16_read(&hw->reset.resetting) == 0)
960                 init_port_base_vlan_info(hw);
961
962         ret = hns3_vlan_filter_init(hns);
963         if (ret) {
964                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
965                 return ret;
966         }
967
968         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
969                                        RTE_ETHER_TYPE_VLAN);
970         if (ret) {
971                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
972                 return ret;
973         }
974
975         /*
976          * When in the reinit dev stage of the reset process, the following
977          * vlan-related configurations may differ from those at initialization,
978          * we will restore configurations to hardware in hns3_restore_vlan_table
979          * and hns3_restore_vlan_conf later.
980          */
981         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
982                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
983                 if (ret) {
984                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
985                         return ret;
986                 }
987
988                 ret = hns3_en_hw_strip_rxvtag(hns, false);
989                 if (ret) {
990                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
991                                  ret);
992                         return ret;
993                 }
994         }
995
996         return hns3_default_vlan_config(hns);
997 }
998
999 static int
1000 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1001 {
1002         struct hns3_pf *pf = &hns->pf;
1003         struct hns3_hw *hw = &hns->hw;
1004         uint64_t offloads;
1005         bool enable;
1006         int ret;
1007
1008         if (!hw->data->promiscuous) {
1009                 /* restore vlan filter states */
1010                 offloads = hw->data->dev_conf.rxmode.offloads;
1011                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1012                 ret = hns3_enable_vlan_filter(hns, enable);
1013                 if (ret) {
1014                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1015                                  "ret = %d", ret);
1016                         return ret;
1017                 }
1018         }
1019
1020         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1021         if (ret) {
1022                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1023                 return ret;
1024         }
1025
1026         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1027         if (ret)
1028                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1029
1030         return ret;
1031 }
1032
1033 static int
1034 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1035 {
1036         struct hns3_adapter *hns = dev->data->dev_private;
1037         struct rte_eth_dev_data *data = dev->data;
1038         struct rte_eth_txmode *txmode;
1039         struct hns3_hw *hw = &hns->hw;
1040         int mask;
1041         int ret;
1042
1043         txmode = &data->dev_conf.txmode;
1044         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1045                 hns3_warn(hw,
1046                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1047                           "configuration is not supported! Ignore these two "
1048                           "parameters: hw_vlan_reject_tagged(%d), "
1049                           "hw_vlan_reject_untagged(%d)",
1050                           txmode->hw_vlan_reject_tagged,
1051                           txmode->hw_vlan_reject_untagged);
1052
1053         /* Apply vlan offload setting */
1054         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1055         ret = hns3_vlan_offload_set(dev, mask);
1056         if (ret) {
1057                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1058                          ret);
1059                 return ret;
1060         }
1061
1062         /*
1063          * If pvid config is not set in rte_eth_conf, driver needn't to set
1064          * VLAN pvid related configuration to hardware.
1065          */
1066         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1067                 return 0;
1068
1069         /* Apply pvid setting */
1070         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1071                                  txmode->hw_vlan_insert_pvid);
1072         if (ret)
1073                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1074                          txmode->pvid, ret);
1075
1076         return ret;
1077 }
1078
1079 static int
1080 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1081                 unsigned int tso_mss_max)
1082 {
1083         struct hns3_cfg_tso_status_cmd *req;
1084         struct hns3_cmd_desc desc;
1085         uint16_t tso_mss;
1086
1087         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1088
1089         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1090
1091         tso_mss = 0;
1092         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1093                        tso_mss_min);
1094         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1095
1096         tso_mss = 0;
1097         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1098                        tso_mss_max);
1099         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1100
1101         return hns3_cmd_send(hw, &desc, 1);
1102 }
1103
1104 int
1105 hns3_config_gro(struct hns3_hw *hw, bool en)
1106 {
1107         struct hns3_cfg_gro_status_cmd *req;
1108         struct hns3_cmd_desc desc;
1109         int ret;
1110
1111         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1112         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1113
1114         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1115
1116         ret = hns3_cmd_send(hw, &desc, 1);
1117         if (ret)
1118                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1119
1120         return ret;
1121 }
1122
1123 static int
1124 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1125                    uint16_t *allocated_size, bool is_alloc)
1126 {
1127         struct hns3_umv_spc_alc_cmd *req;
1128         struct hns3_cmd_desc desc;
1129         int ret;
1130
1131         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1132         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1133         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1134         req->space_size = rte_cpu_to_le_32(space_size);
1135
1136         ret = hns3_cmd_send(hw, &desc, 1);
1137         if (ret) {
1138                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1139                              is_alloc ? "allocate" : "free", ret);
1140                 return ret;
1141         }
1142
1143         if (is_alloc && allocated_size)
1144                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1145
1146         return 0;
1147 }
1148
1149 static int
1150 hns3_init_umv_space(struct hns3_hw *hw)
1151 {
1152         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1153         struct hns3_pf *pf = &hns->pf;
1154         uint16_t allocated_size = 0;
1155         int ret;
1156
1157         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1158                                  true);
1159         if (ret)
1160                 return ret;
1161
1162         if (allocated_size < pf->wanted_umv_size)
1163                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1164                              pf->wanted_umv_size, allocated_size);
1165
1166         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1167                                                 pf->wanted_umv_size;
1168         pf->used_umv_size = 0;
1169         return 0;
1170 }
1171
1172 static int
1173 hns3_uninit_umv_space(struct hns3_hw *hw)
1174 {
1175         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1176         struct hns3_pf *pf = &hns->pf;
1177         int ret;
1178
1179         if (pf->max_umv_size == 0)
1180                 return 0;
1181
1182         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1183         if (ret)
1184                 return ret;
1185
1186         pf->max_umv_size = 0;
1187
1188         return 0;
1189 }
1190
1191 static bool
1192 hns3_is_umv_space_full(struct hns3_hw *hw)
1193 {
1194         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1195         struct hns3_pf *pf = &hns->pf;
1196         bool is_full;
1197
1198         is_full = (pf->used_umv_size >= pf->max_umv_size);
1199
1200         return is_full;
1201 }
1202
1203 static void
1204 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1205 {
1206         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1207         struct hns3_pf *pf = &hns->pf;
1208
1209         if (is_free) {
1210                 if (pf->used_umv_size > 0)
1211                         pf->used_umv_size--;
1212         } else
1213                 pf->used_umv_size++;
1214 }
1215
1216 static void
1217 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1218                       const uint8_t *addr, bool is_mc)
1219 {
1220         const unsigned char *mac_addr = addr;
1221         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1222                             ((uint32_t)mac_addr[2] << 16) |
1223                             ((uint32_t)mac_addr[1] << 8) |
1224                             (uint32_t)mac_addr[0];
1225         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1226
1227         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1228         if (is_mc) {
1229                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1230                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1231                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1232         }
1233
1234         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1235         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1236 }
1237
1238 static int
1239 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1240                              uint8_t resp_code,
1241                              enum hns3_mac_vlan_tbl_opcode op)
1242 {
1243         if (cmdq_resp) {
1244                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1245                          cmdq_resp);
1246                 return -EIO;
1247         }
1248
1249         if (op == HNS3_MAC_VLAN_ADD) {
1250                 if (resp_code == 0 || resp_code == 1) {
1251                         return 0;
1252                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1253                         hns3_err(hw, "add mac addr failed for uc_overflow");
1254                         return -ENOSPC;
1255                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1256                         hns3_err(hw, "add mac addr failed for mc_overflow");
1257                         return -ENOSPC;
1258                 }
1259
1260                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1261                          resp_code);
1262                 return -EIO;
1263         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1264                 if (resp_code == 0) {
1265                         return 0;
1266                 } else if (resp_code == 1) {
1267                         hns3_dbg(hw, "remove mac addr failed for miss");
1268                         return -ENOENT;
1269                 }
1270
1271                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1272                          resp_code);
1273                 return -EIO;
1274         } else if (op == HNS3_MAC_VLAN_LKUP) {
1275                 if (resp_code == 0) {
1276                         return 0;
1277                 } else if (resp_code == 1) {
1278                         hns3_dbg(hw, "lookup mac addr failed for miss");
1279                         return -ENOENT;
1280                 }
1281
1282                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1283                          resp_code);
1284                 return -EIO;
1285         }
1286
1287         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1288                  op);
1289
1290         return -EINVAL;
1291 }
1292
1293 static int
1294 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1295                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1296                          struct hns3_cmd_desc *desc, bool is_mc)
1297 {
1298         uint8_t resp_code;
1299         uint16_t retval;
1300         int ret;
1301
1302         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1303         if (is_mc) {
1304                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305                 memcpy(desc[0].data, req,
1306                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1307                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1308                                           true);
1309                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1310                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1311                                           true);
1312                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1313         } else {
1314                 memcpy(desc[0].data, req,
1315                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1316                 ret = hns3_cmd_send(hw, desc, 1);
1317         }
1318         if (ret) {
1319                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1320                          ret);
1321                 return ret;
1322         }
1323         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1324         retval = rte_le_to_cpu_16(desc[0].retval);
1325
1326         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1327                                             HNS3_MAC_VLAN_LKUP);
1328 }
1329
1330 static int
1331 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1332                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1333                       struct hns3_cmd_desc *mc_desc)
1334 {
1335         uint8_t resp_code;
1336         uint16_t retval;
1337         int cfg_status;
1338         int ret;
1339
1340         if (mc_desc == NULL) {
1341                 struct hns3_cmd_desc desc;
1342
1343                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1344                 memcpy(desc.data, req,
1345                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1346                 ret = hns3_cmd_send(hw, &desc, 1);
1347                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1348                 retval = rte_le_to_cpu_16(desc.retval);
1349
1350                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1351                                                           HNS3_MAC_VLAN_ADD);
1352         } else {
1353                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1354                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1355                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1356                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1357                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1358                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1359                 memcpy(mc_desc[0].data, req,
1360                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1361                 mc_desc[0].retval = 0;
1362                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1363                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1364                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1365
1366                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1367                                                           HNS3_MAC_VLAN_ADD);
1368         }
1369
1370         if (ret) {
1371                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1372                 return ret;
1373         }
1374
1375         return cfg_status;
1376 }
1377
1378 static int
1379 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1380                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1381 {
1382         struct hns3_cmd_desc desc;
1383         uint8_t resp_code;
1384         uint16_t retval;
1385         int ret;
1386
1387         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1388
1389         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1390
1391         ret = hns3_cmd_send(hw, &desc, 1);
1392         if (ret) {
1393                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1394                 return ret;
1395         }
1396         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1397         retval = rte_le_to_cpu_16(desc.retval);
1398
1399         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1400                                             HNS3_MAC_VLAN_REMOVE);
1401 }
1402
1403 static int
1404 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1405 {
1406         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1407         struct hns3_mac_vlan_tbl_entry_cmd req;
1408         struct hns3_pf *pf = &hns->pf;
1409         struct hns3_cmd_desc desc;
1410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1411         uint16_t egress_port = 0;
1412         uint8_t vf_id;
1413         int ret;
1414
1415         /* check if mac addr is valid */
1416         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1417                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1418                                       mac_addr);
1419                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1420                          mac_str);
1421                 return -EINVAL;
1422         }
1423
1424         memset(&req, 0, sizeof(req));
1425
1426         /*
1427          * In current version VF is not supported when PF is driven by DPDK
1428          * driver, the PF-related vf_id is 0, just need to configure parameters
1429          * for vf_id 0.
1430          */
1431         vf_id = 0;
1432         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1433                        HNS3_MAC_EPORT_VFID_S, vf_id);
1434
1435         req.egress_port = rte_cpu_to_le_16(egress_port);
1436
1437         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1438
1439         /*
1440          * Lookup the mac address in the mac_vlan table, and add
1441          * it if the entry is inexistent. Repeated unicast entry
1442          * is not allowed in the mac vlan table.
1443          */
1444         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1445         if (ret == -ENOENT) {
1446                 if (!hns3_is_umv_space_full(hw)) {
1447                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1448                         if (!ret)
1449                                 hns3_update_umv_space(hw, false);
1450                         return ret;
1451                 }
1452
1453                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1454
1455                 return -ENOSPC;
1456         }
1457
1458         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1459
1460         /* check if we just hit the duplicate */
1461         if (ret == 0) {
1462                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1463                 return 0;
1464         }
1465
1466         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1467                  mac_str);
1468
1469         return ret;
1470 }
1471
1472 static int
1473 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1474 {
1475         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1476         struct rte_ether_addr *addr;
1477         int ret;
1478         int i;
1479
1480         for (i = 0; i < hw->mc_addrs_num; i++) {
1481                 addr = &hw->mc_addrs[i];
1482                 /* Check if there are duplicate addresses */
1483                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1484                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485                                               addr);
1486                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1487                                  "(%s) is added by the set_mc_mac_addr_list "
1488                                  "API", mac_str);
1489                         return -EINVAL;
1490                 }
1491         }
1492
1493         ret = hns3_add_mc_addr(hw, mac_addr);
1494         if (ret) {
1495                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1496                                       mac_addr);
1497                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1498                          mac_str, ret);
1499         }
1500         return ret;
1501 }
1502
1503 static int
1504 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1505 {
1506         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1507         int ret;
1508
1509         ret = hns3_remove_mc_addr(hw, mac_addr);
1510         if (ret) {
1511                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                       mac_addr);
1513                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1514                          mac_str, ret);
1515         }
1516         return ret;
1517 }
1518
1519 static int
1520 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1521                   uint32_t idx, __rte_unused uint32_t pool)
1522 {
1523         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1525         int ret;
1526
1527         rte_spinlock_lock(&hw->lock);
1528
1529         /*
1530          * In hns3 network engine adding UC and MC mac address with different
1531          * commands with firmware. We need to determine whether the input
1532          * address is a UC or a MC address to call different commands.
1533          * By the way, it is recommended calling the API function named
1534          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1535          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1536          * may affect the specifications of UC mac addresses.
1537          */
1538         if (rte_is_multicast_ether_addr(mac_addr))
1539                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1540         else
1541                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1542
1543         if (ret) {
1544                 rte_spinlock_unlock(&hw->lock);
1545                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                       mac_addr);
1547                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1548                          ret);
1549                 return ret;
1550         }
1551
1552         if (idx == 0)
1553                 hw->mac.default_addr_setted = true;
1554         rte_spinlock_unlock(&hw->lock);
1555
1556         return ret;
1557 }
1558
1559 static int
1560 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1561 {
1562         struct hns3_mac_vlan_tbl_entry_cmd req;
1563         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1564         int ret;
1565
1566         /* check if mac addr is valid */
1567         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1568                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1569                                       mac_addr);
1570                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1571                          mac_str);
1572                 return -EINVAL;
1573         }
1574
1575         memset(&req, 0, sizeof(req));
1576         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1577         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1578         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1579         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1580                 return 0;
1581         else if (ret == 0)
1582                 hns3_update_umv_space(hw, true);
1583
1584         return ret;
1585 }
1586
1587 static void
1588 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1589 {
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         /* index will be checked by upper level rte interface */
1592         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1593         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1594         int ret;
1595
1596         rte_spinlock_lock(&hw->lock);
1597
1598         if (rte_is_multicast_ether_addr(mac_addr))
1599                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1600         else
1601                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1602         rte_spinlock_unlock(&hw->lock);
1603         if (ret) {
1604                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1605                                       mac_addr);
1606                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1607                          ret);
1608         }
1609 }
1610
1611 static int
1612 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1613                           struct rte_ether_addr *mac_addr)
1614 {
1615         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         struct rte_ether_addr *oaddr;
1617         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1618         bool default_addr_setted;
1619         bool rm_succes = false;
1620         int ret, ret_val;
1621
1622         /*
1623          * It has been guaranteed that input parameter named mac_addr is valid
1624          * address in the rte layer of DPDK framework.
1625          */
1626         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1627         default_addr_setted = hw->mac.default_addr_setted;
1628         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1629                 return 0;
1630
1631         rte_spinlock_lock(&hw->lock);
1632         if (default_addr_setted) {
1633                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1634                 if (ret) {
1635                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636                                               oaddr);
1637                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1638                                   mac_str, ret);
1639                         rm_succes = false;
1640                 } else
1641                         rm_succes = true;
1642         }
1643
1644         ret = hns3_add_uc_addr_common(hw, mac_addr);
1645         if (ret) {
1646                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1649                 goto err_add_uc_addr;
1650         }
1651
1652         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1653         if (ret) {
1654                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1655                 goto err_pause_addr_cfg;
1656         }
1657
1658         rte_ether_addr_copy(mac_addr,
1659                             (struct rte_ether_addr *)hw->mac.mac_addr);
1660         hw->mac.default_addr_setted = true;
1661         rte_spinlock_unlock(&hw->lock);
1662
1663         return 0;
1664
1665 err_pause_addr_cfg:
1666         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1667         if (ret_val) {
1668                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1669                                       mac_addr);
1670                 hns3_warn(hw,
1671                           "Failed to roll back to del setted mac addr(%s): %d",
1672                           mac_str, ret_val);
1673         }
1674
1675 err_add_uc_addr:
1676         if (rm_succes) {
1677                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1678                 if (ret_val) {
1679                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                               oaddr);
1681                         hns3_warn(hw,
1682                                   "Failed to restore old uc mac addr(%s): %d",
1683                                   mac_str, ret_val);
1684                         hw->mac.default_addr_setted = false;
1685                 }
1686         }
1687         rte_spinlock_unlock(&hw->lock);
1688
1689         return ret;
1690 }
1691
1692 static int
1693 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1694 {
1695         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1696         struct hns3_hw *hw = &hns->hw;
1697         struct rte_ether_addr *addr;
1698         int err = 0;
1699         int ret;
1700         int i;
1701
1702         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1703                 addr = &hw->data->mac_addrs[i];
1704                 if (rte_is_zero_ether_addr(addr))
1705                         continue;
1706                 if (rte_is_multicast_ether_addr(addr))
1707                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1708                               hns3_add_mc_addr(hw, addr);
1709                 else
1710                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1711                               hns3_add_uc_addr_common(hw, addr);
1712
1713                 if (ret) {
1714                         err = ret;
1715                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1716                                               addr);
1717                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1718                                  "ret = %d.", del ? "remove" : "restore",
1719                                  mac_str, i, ret);
1720                 }
1721         }
1722         return err;
1723 }
1724
1725 static void
1726 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1727 {
1728 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1729         uint8_t word_num;
1730         uint8_t bit_num;
1731
1732         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1733                 word_num = vfid / 32;
1734                 bit_num = vfid % 32;
1735                 if (clr)
1736                         desc[1].data[word_num] &=
1737                             rte_cpu_to_le_32(~(1UL << bit_num));
1738                 else
1739                         desc[1].data[word_num] |=
1740                             rte_cpu_to_le_32(1UL << bit_num);
1741         } else {
1742                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1743                 bit_num = vfid % 32;
1744                 if (clr)
1745                         desc[2].data[word_num] &=
1746                             rte_cpu_to_le_32(~(1UL << bit_num));
1747                 else
1748                         desc[2].data[word_num] |=
1749                             rte_cpu_to_le_32(1UL << bit_num);
1750         }
1751 }
1752
1753 static int
1754 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1755 {
1756         struct hns3_mac_vlan_tbl_entry_cmd req;
1757         struct hns3_cmd_desc desc[3];
1758         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759         uint8_t vf_id;
1760         int ret;
1761
1762         /* Check if mac addr is valid */
1763         if (!rte_is_multicast_ether_addr(mac_addr)) {
1764                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1765                                       mac_addr);
1766                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1767                          mac_str);
1768                 return -EINVAL;
1769         }
1770
1771         memset(&req, 0, sizeof(req));
1772         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1773         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1774         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1775         if (ret) {
1776                 /* This mac addr do not exist, add new entry for it */
1777                 memset(desc[0].data, 0, sizeof(desc[0].data));
1778                 memset(desc[1].data, 0, sizeof(desc[0].data));
1779                 memset(desc[2].data, 0, sizeof(desc[0].data));
1780         }
1781
1782         /*
1783          * In current version VF is not supported when PF is driven by DPDK
1784          * driver, the PF-related vf_id is 0, just need to configure parameters
1785          * for vf_id 0.
1786          */
1787         vf_id = 0;
1788         hns3_update_desc_vfid(desc, vf_id, false);
1789         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1790         if (ret) {
1791                 if (ret == -ENOSPC)
1792                         hns3_err(hw, "mc mac vlan table is full");
1793                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1794                                       mac_addr);
1795                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1796         }
1797
1798         return ret;
1799 }
1800
1801 static int
1802 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1803 {
1804         struct hns3_mac_vlan_tbl_entry_cmd req;
1805         struct hns3_cmd_desc desc[3];
1806         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1807         uint8_t vf_id;
1808         int ret;
1809
1810         /* Check if mac addr is valid */
1811         if (!rte_is_multicast_ether_addr(mac_addr)) {
1812                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1813                                       mac_addr);
1814                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1815                          mac_str);
1816                 return -EINVAL;
1817         }
1818
1819         memset(&req, 0, sizeof(req));
1820         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1821         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1822         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1823         if (ret == 0) {
1824                 /*
1825                  * This mac addr exist, remove this handle's VFID for it.
1826                  * In current version VF is not supported when PF is driven by
1827                  * DPDK driver, the PF-related vf_id is 0, just need to
1828                  * configure parameters for vf_id 0.
1829                  */
1830                 vf_id = 0;
1831                 hns3_update_desc_vfid(desc, vf_id, true);
1832
1833                 /* All the vfid is zero, so need to delete this entry */
1834                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1835         } else if (ret == -ENOENT) {
1836                 /* This mac addr doesn't exist. */
1837                 return 0;
1838         }
1839
1840         if (ret) {
1841                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1842                                       mac_addr);
1843                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1844         }
1845
1846         return ret;
1847 }
1848
1849 static int
1850 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1851                            struct rte_ether_addr *mc_addr_set,
1852                            uint32_t nb_mc_addr)
1853 {
1854         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1855         struct rte_ether_addr *addr;
1856         uint32_t i;
1857         uint32_t j;
1858
1859         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1860                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1861                          "invalid. valid range: 0~%d",
1862                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1863                 return -EINVAL;
1864         }
1865
1866         /* Check if input mac addresses are valid */
1867         for (i = 0; i < nb_mc_addr; i++) {
1868                 addr = &mc_addr_set[i];
1869                 if (!rte_is_multicast_ether_addr(addr)) {
1870                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1871                                               addr);
1872                         hns3_err(hw,
1873                                  "failed to set mc mac addr, addr(%s) invalid.",
1874                                  mac_str);
1875                         return -EINVAL;
1876                 }
1877
1878                 /* Check if there are duplicate addresses */
1879                 for (j = i + 1; j < nb_mc_addr; j++) {
1880                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1881                                 rte_ether_format_addr(mac_str,
1882                                                       RTE_ETHER_ADDR_FMT_SIZE,
1883                                                       addr);
1884                                 hns3_err(hw, "failed to set mc mac addr, "
1885                                          "addrs invalid. two same addrs(%s).",
1886                                          mac_str);
1887                                 return -EINVAL;
1888                         }
1889                 }
1890
1891                 /*
1892                  * Check if there are duplicate addresses between mac_addrs
1893                  * and mc_addr_set
1894                  */
1895                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1896                         if (rte_is_same_ether_addr(addr,
1897                                                    &hw->data->mac_addrs[j])) {
1898                                 rte_ether_format_addr(mac_str,
1899                                                       RTE_ETHER_ADDR_FMT_SIZE,
1900                                                       addr);
1901                                 hns3_err(hw, "failed to set mc mac addr, "
1902                                          "addrs invalid. addrs(%s) has already "
1903                                          "configured in mac_addr add API",
1904                                          mac_str);
1905                                 return -EINVAL;
1906                         }
1907                 }
1908         }
1909
1910         return 0;
1911 }
1912
1913 static void
1914 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1915                            struct rte_ether_addr *mc_addr_set,
1916                            int mc_addr_num,
1917                            struct rte_ether_addr *reserved_addr_list,
1918                            int *reserved_addr_num,
1919                            struct rte_ether_addr *add_addr_list,
1920                            int *add_addr_num,
1921                            struct rte_ether_addr *rm_addr_list,
1922                            int *rm_addr_num)
1923 {
1924         struct rte_ether_addr *addr;
1925         int current_addr_num;
1926         int reserved_num = 0;
1927         int add_num = 0;
1928         int rm_num = 0;
1929         int num;
1930         int i;
1931         int j;
1932         bool same_addr;
1933
1934         /* Calculate the mc mac address list that should be removed */
1935         current_addr_num = hw->mc_addrs_num;
1936         for (i = 0; i < current_addr_num; i++) {
1937                 addr = &hw->mc_addrs[i];
1938                 same_addr = false;
1939                 for (j = 0; j < mc_addr_num; j++) {
1940                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1941                                 same_addr = true;
1942                                 break;
1943                         }
1944                 }
1945
1946                 if (!same_addr) {
1947                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1948                         rm_num++;
1949                 } else {
1950                         rte_ether_addr_copy(addr,
1951                                             &reserved_addr_list[reserved_num]);
1952                         reserved_num++;
1953                 }
1954         }
1955
1956         /* Calculate the mc mac address list that should be added */
1957         for (i = 0; i < mc_addr_num; i++) {
1958                 addr = &mc_addr_set[i];
1959                 same_addr = false;
1960                 for (j = 0; j < current_addr_num; j++) {
1961                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1962                                 same_addr = true;
1963                                 break;
1964                         }
1965                 }
1966
1967                 if (!same_addr) {
1968                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1969                         add_num++;
1970                 }
1971         }
1972
1973         /* Reorder the mc mac address list maintained by driver */
1974         for (i = 0; i < reserved_num; i++)
1975                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1976
1977         for (i = 0; i < rm_num; i++) {
1978                 num = reserved_num + i;
1979                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1980         }
1981
1982         *reserved_addr_num = reserved_num;
1983         *add_addr_num = add_num;
1984         *rm_addr_num = rm_num;
1985 }
1986
1987 static int
1988 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1989                           struct rte_ether_addr *mc_addr_set,
1990                           uint32_t nb_mc_addr)
1991 {
1992         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1994         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1995         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1996         struct rte_ether_addr *addr;
1997         int reserved_addr_num;
1998         int add_addr_num;
1999         int rm_addr_num;
2000         int mc_addr_num;
2001         int num;
2002         int ret;
2003         int i;
2004
2005         /* Check if input parameters are valid */
2006         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2007         if (ret)
2008                 return ret;
2009
2010         rte_spinlock_lock(&hw->lock);
2011
2012         /*
2013          * Calculate the mc mac address lists those should be removed and be
2014          * added, Reorder the mc mac address list maintained by driver.
2015          */
2016         mc_addr_num = (int)nb_mc_addr;
2017         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2018                                    reserved_addr_list, &reserved_addr_num,
2019                                    add_addr_list, &add_addr_num,
2020                                    rm_addr_list, &rm_addr_num);
2021
2022         /* Remove mc mac addresses */
2023         for (i = 0; i < rm_addr_num; i++) {
2024                 num = rm_addr_num - i - 1;
2025                 addr = &rm_addr_list[num];
2026                 ret = hns3_remove_mc_addr(hw, addr);
2027                 if (ret) {
2028                         rte_spinlock_unlock(&hw->lock);
2029                         return ret;
2030                 }
2031                 hw->mc_addrs_num--;
2032         }
2033
2034         /* Add mc mac addresses */
2035         for (i = 0; i < add_addr_num; i++) {
2036                 addr = &add_addr_list[i];
2037                 ret = hns3_add_mc_addr(hw, addr);
2038                 if (ret) {
2039                         rte_spinlock_unlock(&hw->lock);
2040                         return ret;
2041                 }
2042
2043                 num = reserved_addr_num + i;
2044                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2045                 hw->mc_addrs_num++;
2046         }
2047         rte_spinlock_unlock(&hw->lock);
2048
2049         return 0;
2050 }
2051
2052 static int
2053 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2054 {
2055         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2056         struct hns3_hw *hw = &hns->hw;
2057         struct rte_ether_addr *addr;
2058         int err = 0;
2059         int ret;
2060         int i;
2061
2062         for (i = 0; i < hw->mc_addrs_num; i++) {
2063                 addr = &hw->mc_addrs[i];
2064                 if (!rte_is_multicast_ether_addr(addr))
2065                         continue;
2066                 if (del)
2067                         ret = hns3_remove_mc_addr(hw, addr);
2068                 else
2069                         ret = hns3_add_mc_addr(hw, addr);
2070                 if (ret) {
2071                         err = ret;
2072                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2073                                               addr);
2074                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2075                                  del ? "Remove" : "Restore", mac_str, ret);
2076                 }
2077         }
2078         return err;
2079 }
2080
2081 static int
2082 hns3_check_mq_mode(struct rte_eth_dev *dev)
2083 {
2084         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2085         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2086         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2088         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2089         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2090         uint8_t num_tc;
2091         int max_tc = 0;
2092         int i;
2093
2094         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2095         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2096
2097         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2098                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2099                          "rx_mq_mode = %d", rx_mq_mode);
2100                 return -EINVAL;
2101         }
2102
2103         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2104             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2105                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2106                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2107                          rx_mq_mode, tx_mq_mode);
2108                 return -EINVAL;
2109         }
2110
2111         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2112                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2113                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2114                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2115                         return -EINVAL;
2116                 }
2117
2118                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2119                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2120                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2121                                  "nb_tcs(%d) != %d or %d in rx direction.",
2122                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2123                         return -EINVAL;
2124                 }
2125
2126                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2127                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2128                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2129                         return -EINVAL;
2130                 }
2131
2132                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2133                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2134                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2135                                          "is not equal to one in tx direction.",
2136                                          i, dcb_rx_conf->dcb_tc[i]);
2137                                 return -EINVAL;
2138                         }
2139                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2140                                 max_tc = dcb_rx_conf->dcb_tc[i];
2141                 }
2142
2143                 num_tc = max_tc + 1;
2144                 if (num_tc > dcb_rx_conf->nb_tcs) {
2145                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2146                                  num_tc, dcb_rx_conf->nb_tcs);
2147                         return -EINVAL;
2148                 }
2149         }
2150
2151         return 0;
2152 }
2153
2154 static int
2155 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2156 {
2157         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158
2159         if (!hns3_dev_dcb_supported(hw)) {
2160                 hns3_err(hw, "this port does not support dcb configurations.");
2161                 return -EOPNOTSUPP;
2162         }
2163
2164         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2165                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2166                 return -EOPNOTSUPP;
2167         }
2168
2169         /* Check multiple queue mode */
2170         return hns3_check_mq_mode(dev);
2171 }
2172
2173 static int
2174 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2175                            enum hns3_ring_type queue_type, uint16_t queue_id)
2176 {
2177         struct hns3_cmd_desc desc;
2178         struct hns3_ctrl_vector_chain_cmd *req =
2179                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2180         enum hns3_cmd_status status;
2181         enum hns3_opcode_type op;
2182         uint16_t tqp_type_and_id = 0;
2183         const char *op_str;
2184         uint16_t type;
2185         uint16_t gl;
2186
2187         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2188         hns3_cmd_setup_basic_desc(&desc, op, false);
2189         req->int_vector_id = vector_id;
2190
2191         if (queue_type == HNS3_RING_TYPE_RX)
2192                 gl = HNS3_RING_GL_RX;
2193         else
2194                 gl = HNS3_RING_GL_TX;
2195
2196         type = queue_type;
2197
2198         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2199                        type);
2200         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2201         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2202                        gl);
2203         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2204         req->int_cause_num = 1;
2205         op_str = mmap ? "Map" : "Unmap";
2206         status = hns3_cmd_send(hw, &desc, 1);
2207         if (status) {
2208                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2209                          op_str, queue_id, req->int_vector_id, status);
2210                 return status;
2211         }
2212
2213         return 0;
2214 }
2215
2216 static int
2217 hns3_init_ring_with_vector(struct hns3_hw *hw)
2218 {
2219         uint8_t vec;
2220         int ret;
2221         int i;
2222
2223         /*
2224          * In hns3 network engine, vector 0 is always the misc interrupt of this
2225          * function, vector 1~N can be used respectively for the queues of the
2226          * function. Tx and Rx queues with the same number share the interrupt
2227          * vector. In the initialization clearing the all hardware mapping
2228          * relationship configurations between queues and interrupt vectors is
2229          * needed, so some error caused by the residual configurations, such as
2230          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2231          * constraints in hns3 hardware engine, we have to implement clearing
2232          * the mapping relationship configurations by binding all queues to the
2233          * last interrupt vector and reserving the last interrupt vector. This
2234          * method results in a decrease of the maximum queues when upper
2235          * applications call the rte_eth_dev_configure API function to enable
2236          * Rx interrupt.
2237          */
2238         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2239         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2240         for (i = 0; i < hw->intr_tqps_num; i++) {
2241                 /*
2242                  * Set gap limiter and rate limiter configuration of queue's
2243                  * interrupt.
2244                  */
2245                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2246                                        HNS3_TQP_INTR_GL_DEFAULT);
2247                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2248                                        HNS3_TQP_INTR_GL_DEFAULT);
2249                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2250
2251                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2252                                                  HNS3_RING_TYPE_TX, i);
2253                 if (ret) {
2254                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2255                                           "vector: %d, ret=%d", i, vec, ret);
2256                         return ret;
2257                 }
2258
2259                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2260                                                  HNS3_RING_TYPE_RX, i);
2261                 if (ret) {
2262                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2263                                           "vector: %d, ret=%d", i, vec, ret);
2264                         return ret;
2265                 }
2266         }
2267
2268         return 0;
2269 }
2270
2271 static int
2272 hns3_dev_configure(struct rte_eth_dev *dev)
2273 {
2274         struct hns3_adapter *hns = dev->data->dev_private;
2275         struct rte_eth_conf *conf = &dev->data->dev_conf;
2276         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2277         struct hns3_hw *hw = &hns->hw;
2278         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2279         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2280         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2281         struct rte_eth_rss_conf rss_conf;
2282         uint16_t mtu;
2283         int ret;
2284
2285         /*
2286          * Hardware does not support individually enable/disable/reset the Tx or
2287          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2288          * and Rx queues at the same time. When the numbers of Tx queues
2289          * allocated by upper applications are not equal to the numbers of Rx
2290          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2291          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2292          * these fake queues are imperceptible, and can not be used by upper
2293          * applications.
2294          */
2295         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2296         if (ret) {
2297                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2298                 return ret;
2299         }
2300
2301         hw->adapter_state = HNS3_NIC_CONFIGURING;
2302         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2303                 hns3_err(hw, "setting link speed/duplex not supported");
2304                 ret = -EINVAL;
2305                 goto cfg_err;
2306         }
2307
2308         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2309                 ret = hns3_check_dcb_cfg(dev);
2310                 if (ret)
2311                         goto cfg_err;
2312         }
2313
2314         /* When RSS is not configured, redirect the packet queue 0 */
2315         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2316                 rss_conf = conf->rx_adv_conf.rss_conf;
2317                 if (rss_conf.rss_key == NULL) {
2318                         rss_conf.rss_key = rss_cfg->key;
2319                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2320                 }
2321
2322                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2323                 if (ret)
2324                         goto cfg_err;
2325         }
2326
2327         /*
2328          * If jumbo frames are enabled, MTU needs to be refreshed
2329          * according to the maximum RX packet length.
2330          */
2331         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2332                 /*
2333                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2334                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2335                  * can safely assign to "uint16_t" type variable.
2336                  */
2337                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2338                 ret = hns3_dev_mtu_set(dev, mtu);
2339                 if (ret)
2340                         goto cfg_err;
2341                 dev->data->mtu = mtu;
2342         }
2343
2344         ret = hns3_dev_configure_vlan(dev);
2345         if (ret)
2346                 goto cfg_err;
2347
2348         hw->adapter_state = HNS3_NIC_CONFIGURED;
2349
2350         return 0;
2351
2352 cfg_err:
2353         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2354         hw->adapter_state = HNS3_NIC_INITIALIZED;
2355
2356         return ret;
2357 }
2358
2359 static int
2360 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2361 {
2362         struct hns3_config_max_frm_size_cmd *req;
2363         struct hns3_cmd_desc desc;
2364
2365         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2366
2367         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2368         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2369         req->min_frm_size = RTE_ETHER_MIN_LEN;
2370
2371         return hns3_cmd_send(hw, &desc, 1);
2372 }
2373
2374 static int
2375 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2376 {
2377         int ret;
2378
2379         ret = hns3_set_mac_mtu(hw, mps);
2380         if (ret) {
2381                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2382                 return ret;
2383         }
2384
2385         ret = hns3_buffer_alloc(hw);
2386         if (ret)
2387                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2388
2389         return ret;
2390 }
2391
2392 static int
2393 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2394 {
2395         struct hns3_adapter *hns = dev->data->dev_private;
2396         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2397         struct hns3_hw *hw = &hns->hw;
2398         bool is_jumbo_frame;
2399         int ret;
2400
2401         if (dev->data->dev_started) {
2402                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2403                          "before configuration", dev->data->port_id);
2404                 return -EBUSY;
2405         }
2406
2407         rte_spinlock_lock(&hw->lock);
2408         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2409         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2410
2411         /*
2412          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2413          * assign to "uint16_t" type variable.
2414          */
2415         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2416         if (ret) {
2417                 rte_spinlock_unlock(&hw->lock);
2418                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2419                          dev->data->port_id, mtu, ret);
2420                 return ret;
2421         }
2422         hns->pf.mps = (uint16_t)frame_size;
2423         if (is_jumbo_frame)
2424                 dev->data->dev_conf.rxmode.offloads |=
2425                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2426         else
2427                 dev->data->dev_conf.rxmode.offloads &=
2428                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2429         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2430         rte_spinlock_unlock(&hw->lock);
2431
2432         return 0;
2433 }
2434
2435 static int
2436 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2437 {
2438         struct hns3_adapter *hns = eth_dev->data->dev_private;
2439         struct hns3_hw *hw = &hns->hw;
2440         uint16_t queue_num = hw->tqps_num;
2441
2442         /*
2443          * In interrupt mode, 'max_rx_queues' is set based on the number of
2444          * MSI-X interrupt resources of the hardware.
2445          */
2446         if (hw->data->dev_conf.intr_conf.rxq == 1)
2447                 queue_num = hw->intr_tqps_num;
2448
2449         info->max_rx_queues = queue_num;
2450         info->max_tx_queues = hw->tqps_num;
2451         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2452         info->min_rx_bufsize = hw->rx_buf_len;
2453         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2454         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2455         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2456                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2457                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2458                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2459                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2460                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2461                                  DEV_RX_OFFLOAD_KEEP_CRC |
2462                                  DEV_RX_OFFLOAD_SCATTER |
2463                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2464                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2465                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2466                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2467                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2468                                  DEV_RX_OFFLOAD_RSS_HASH);
2469         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2470         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2471                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2472                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2473                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2474                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2475                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2476                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2477                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2478                                  DEV_TX_OFFLOAD_TCP_TSO |
2479                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2480                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2481                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2482                                  info->tx_queue_offload_capa);
2483
2484         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2485                 .nb_max = HNS3_MAX_RING_DESC,
2486                 .nb_min = HNS3_MIN_RING_DESC,
2487                 .nb_align = HNS3_ALIGN_RING_DESC,
2488         };
2489
2490         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2491                 .nb_max = HNS3_MAX_RING_DESC,
2492                 .nb_min = HNS3_MIN_RING_DESC,
2493                 .nb_align = HNS3_ALIGN_RING_DESC,
2494         };
2495
2496         info->vmdq_queue_num = 0;
2497
2498         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2499         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2500         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2501
2502         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2503         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2504         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2505         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2506         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2507         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2508
2509         return 0;
2510 }
2511
2512 static int
2513 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2514                     size_t fw_size)
2515 {
2516         struct hns3_adapter *hns = eth_dev->data->dev_private;
2517         struct hns3_hw *hw = &hns->hw;
2518         uint32_t version = hw->fw_version;
2519         int ret;
2520
2521         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2522                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2523                                       HNS3_FW_VERSION_BYTE3_S),
2524                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2525                                       HNS3_FW_VERSION_BYTE2_S),
2526                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2527                                       HNS3_FW_VERSION_BYTE1_S),
2528                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2529                                       HNS3_FW_VERSION_BYTE0_S));
2530         ret += 1; /* add the size of '\0' */
2531         if (fw_size < (uint32_t)ret)
2532                 return ret;
2533         else
2534                 return 0;
2535 }
2536
2537 static int
2538 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2539                      __rte_unused int wait_to_complete)
2540 {
2541         struct hns3_adapter *hns = eth_dev->data->dev_private;
2542         struct hns3_hw *hw = &hns->hw;
2543         struct hns3_mac *mac = &hw->mac;
2544         struct rte_eth_link new_link;
2545
2546         if (!hns3_is_reset_pending(hns)) {
2547                 hns3_update_speed_duplex(eth_dev);
2548                 hns3_update_link_status(hw);
2549         }
2550
2551         memset(&new_link, 0, sizeof(new_link));
2552         switch (mac->link_speed) {
2553         case ETH_SPEED_NUM_10M:
2554         case ETH_SPEED_NUM_100M:
2555         case ETH_SPEED_NUM_1G:
2556         case ETH_SPEED_NUM_10G:
2557         case ETH_SPEED_NUM_25G:
2558         case ETH_SPEED_NUM_40G:
2559         case ETH_SPEED_NUM_50G:
2560         case ETH_SPEED_NUM_100G:
2561                 new_link.link_speed = mac->link_speed;
2562                 break;
2563         default:
2564                 new_link.link_speed = ETH_SPEED_NUM_100M;
2565                 break;
2566         }
2567
2568         new_link.link_duplex = mac->link_duplex;
2569         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2570         new_link.link_autoneg =
2571             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2572
2573         return rte_eth_linkstatus_set(eth_dev, &new_link);
2574 }
2575
2576 static int
2577 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2578 {
2579         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2580         struct hns3_pf *pf = &hns->pf;
2581
2582         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2583                 return -EINVAL;
2584
2585         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2586
2587         return 0;
2588 }
2589
2590 static int
2591 hns3_query_function_status(struct hns3_hw *hw)
2592 {
2593 #define HNS3_QUERY_MAX_CNT              10
2594 #define HNS3_QUERY_SLEEP_MSCOEND        1
2595         struct hns3_func_status_cmd *req;
2596         struct hns3_cmd_desc desc;
2597         int timeout = 0;
2598         int ret;
2599
2600         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2601         req = (struct hns3_func_status_cmd *)desc.data;
2602
2603         do {
2604                 ret = hns3_cmd_send(hw, &desc, 1);
2605                 if (ret) {
2606                         PMD_INIT_LOG(ERR, "query function status failed %d",
2607                                      ret);
2608                         return ret;
2609                 }
2610
2611                 /* Check pf reset is done */
2612                 if (req->pf_state)
2613                         break;
2614
2615                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2616         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2617
2618         return hns3_parse_func_status(hw, req);
2619 }
2620
2621 static int
2622 hns3_query_pf_resource(struct hns3_hw *hw)
2623 {
2624         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2625         struct hns3_pf *pf = &hns->pf;
2626         struct hns3_pf_res_cmd *req;
2627         struct hns3_cmd_desc desc;
2628         uint16_t num_msi;
2629         int ret;
2630
2631         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2632         ret = hns3_cmd_send(hw, &desc, 1);
2633         if (ret) {
2634                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2635                 return ret;
2636         }
2637
2638         req = (struct hns3_pf_res_cmd *)desc.data;
2639         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2640         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2641         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2642         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2643
2644         if (req->tx_buf_size)
2645                 pf->tx_buf_size =
2646                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2647         else
2648                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2649
2650         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2651
2652         if (req->dv_buf_size)
2653                 pf->dv_buf_size =
2654                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2655         else
2656                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2657
2658         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2659
2660         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2661                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2662         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2663
2664         return 0;
2665 }
2666
2667 static void
2668 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2669 {
2670         struct hns3_cfg_param_cmd *req;
2671         uint64_t mac_addr_tmp_high;
2672         uint64_t mac_addr_tmp;
2673         uint32_t i;
2674
2675         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2676
2677         /* get the configuration */
2678         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2679                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2680         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2681                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2682         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2683                                            HNS3_CFG_TQP_DESC_N_M,
2684                                            HNS3_CFG_TQP_DESC_N_S);
2685
2686         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2687                                        HNS3_CFG_PHY_ADDR_M,
2688                                        HNS3_CFG_PHY_ADDR_S);
2689         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2690                                          HNS3_CFG_MEDIA_TP_M,
2691                                          HNS3_CFG_MEDIA_TP_S);
2692         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2693                                          HNS3_CFG_RX_BUF_LEN_M,
2694                                          HNS3_CFG_RX_BUF_LEN_S);
2695         /* get mac address */
2696         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2697         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2698                                            HNS3_CFG_MAC_ADDR_H_M,
2699                                            HNS3_CFG_MAC_ADDR_H_S);
2700
2701         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2702
2703         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2704                                             HNS3_CFG_DEFAULT_SPEED_M,
2705                                             HNS3_CFG_DEFAULT_SPEED_S);
2706         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2707                                            HNS3_CFG_RSS_SIZE_M,
2708                                            HNS3_CFG_RSS_SIZE_S);
2709
2710         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2711                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2712
2713         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2714         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2715
2716         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2717                                             HNS3_CFG_SPEED_ABILITY_M,
2718                                             HNS3_CFG_SPEED_ABILITY_S);
2719         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2720                                         HNS3_CFG_UMV_TBL_SPACE_M,
2721                                         HNS3_CFG_UMV_TBL_SPACE_S);
2722         if (!cfg->umv_space)
2723                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2724 }
2725
2726 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2727  * @hw: pointer to struct hns3_hw
2728  * @hcfg: the config structure to be getted
2729  */
2730 static int
2731 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2732 {
2733         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2734         struct hns3_cfg_param_cmd *req;
2735         uint32_t offset;
2736         uint32_t i;
2737         int ret;
2738
2739         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2740                 offset = 0;
2741                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2742                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2743                                           true);
2744                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2745                                i * HNS3_CFG_RD_LEN_BYTES);
2746                 /* Len should be divided by 4 when send to hardware */
2747                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2748                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2749                 req->offset = rte_cpu_to_le_32(offset);
2750         }
2751
2752         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2753         if (ret) {
2754                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2755                 return ret;
2756         }
2757
2758         hns3_parse_cfg(hcfg, desc);
2759
2760         return 0;
2761 }
2762
2763 static int
2764 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2765 {
2766         switch (speed_cmd) {
2767         case HNS3_CFG_SPEED_10M:
2768                 *speed = ETH_SPEED_NUM_10M;
2769                 break;
2770         case HNS3_CFG_SPEED_100M:
2771                 *speed = ETH_SPEED_NUM_100M;
2772                 break;
2773         case HNS3_CFG_SPEED_1G:
2774                 *speed = ETH_SPEED_NUM_1G;
2775                 break;
2776         case HNS3_CFG_SPEED_10G:
2777                 *speed = ETH_SPEED_NUM_10G;
2778                 break;
2779         case HNS3_CFG_SPEED_25G:
2780                 *speed = ETH_SPEED_NUM_25G;
2781                 break;
2782         case HNS3_CFG_SPEED_40G:
2783                 *speed = ETH_SPEED_NUM_40G;
2784                 break;
2785         case HNS3_CFG_SPEED_50G:
2786                 *speed = ETH_SPEED_NUM_50G;
2787                 break;
2788         case HNS3_CFG_SPEED_100G:
2789                 *speed = ETH_SPEED_NUM_100G;
2790                 break;
2791         default:
2792                 return -EINVAL;
2793         }
2794
2795         return 0;
2796 }
2797
2798 static int
2799 hns3_get_board_configuration(struct hns3_hw *hw)
2800 {
2801         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2802         struct hns3_pf *pf = &hns->pf;
2803         struct hns3_cfg cfg;
2804         int ret;
2805
2806         ret = hns3_get_board_cfg(hw, &cfg);
2807         if (ret) {
2808                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2809                 return ret;
2810         }
2811
2812         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2813                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2814                 return -EOPNOTSUPP;
2815         }
2816
2817         hw->mac.media_type = cfg.media_type;
2818         hw->rss_size_max = cfg.rss_size_max;
2819         hw->rss_dis_flag = false;
2820         hw->rx_buf_len = cfg.rx_buf_len;
2821         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2822         hw->mac.phy_addr = cfg.phy_addr;
2823         hw->mac.default_addr_setted = false;
2824         hw->num_tx_desc = cfg.tqp_desc_num;
2825         hw->num_rx_desc = cfg.tqp_desc_num;
2826         hw->dcb_info.num_pg = 1;
2827         hw->dcb_info.hw_pfc_map = 0;
2828
2829         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2830         if (ret) {
2831                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2832                              cfg.default_speed, ret);
2833                 return ret;
2834         }
2835
2836         pf->tc_max = cfg.tc_num;
2837         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2838                 PMD_INIT_LOG(WARNING,
2839                              "Get TC num(%u) from flash, set TC num to 1",
2840                              pf->tc_max);
2841                 pf->tc_max = 1;
2842         }
2843
2844         /* Dev does not support DCB */
2845         if (!hns3_dev_dcb_supported(hw)) {
2846                 pf->tc_max = 1;
2847                 pf->pfc_max = 0;
2848         } else
2849                 pf->pfc_max = pf->tc_max;
2850
2851         hw->dcb_info.num_tc = 1;
2852         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2853                                      hw->tqps_num / hw->dcb_info.num_tc);
2854         hns3_set_bit(hw->hw_tc_map, 0, 1);
2855         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2856
2857         pf->wanted_umv_size = cfg.umv_space;
2858
2859         return ret;
2860 }
2861
2862 static int
2863 hns3_get_configuration(struct hns3_hw *hw)
2864 {
2865         int ret;
2866
2867         ret = hns3_query_function_status(hw);
2868         if (ret) {
2869                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2870                 return ret;
2871         }
2872
2873         /* Get pf resource */
2874         ret = hns3_query_pf_resource(hw);
2875         if (ret) {
2876                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2877                 return ret;
2878         }
2879
2880         ret = hns3_get_board_configuration(hw);
2881         if (ret)
2882                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2883
2884         return ret;
2885 }
2886
2887 static int
2888 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2889                       uint16_t tqp_vid, bool is_pf)
2890 {
2891         struct hns3_tqp_map_cmd *req;
2892         struct hns3_cmd_desc desc;
2893         int ret;
2894
2895         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2896
2897         req = (struct hns3_tqp_map_cmd *)desc.data;
2898         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2899         req->tqp_vf = func_id;
2900         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2901         if (!is_pf)
2902                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2903         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2904
2905         ret = hns3_cmd_send(hw, &desc, 1);
2906         if (ret)
2907                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2908
2909         return ret;
2910 }
2911
2912 static int
2913 hns3_map_tqp(struct hns3_hw *hw)
2914 {
2915         uint16_t tqps_num = hw->total_tqps_num;
2916         uint16_t func_id;
2917         uint16_t tqp_id;
2918         bool is_pf;
2919         int num;
2920         int ret;
2921         int i;
2922
2923         /*
2924          * In current version VF is not supported when PF is driven by DPDK
2925          * driver, so we allocate tqps to PF as much as possible.
2926          */
2927         tqp_id = 0;
2928         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2929         for (func_id = 0; func_id < num; func_id++) {
2930                 is_pf = func_id == 0 ? true : false;
2931                 for (i = 0;
2932                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2933                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2934                                                     is_pf);
2935                         if (ret)
2936                                 return ret;
2937                 }
2938         }
2939
2940         return 0;
2941 }
2942
2943 static int
2944 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2945 {
2946         struct hns3_config_mac_speed_dup_cmd *req;
2947         struct hns3_cmd_desc desc;
2948         int ret;
2949
2950         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2951
2952         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2953
2954         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2955
2956         switch (speed) {
2957         case ETH_SPEED_NUM_10M:
2958                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2959                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2960                 break;
2961         case ETH_SPEED_NUM_100M:
2962                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2963                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2964                 break;
2965         case ETH_SPEED_NUM_1G:
2966                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2967                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2968                 break;
2969         case ETH_SPEED_NUM_10G:
2970                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2971                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2972                 break;
2973         case ETH_SPEED_NUM_25G:
2974                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2975                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2976                 break;
2977         case ETH_SPEED_NUM_40G:
2978                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2979                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2980                 break;
2981         case ETH_SPEED_NUM_50G:
2982                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2983                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2984                 break;
2985         case ETH_SPEED_NUM_100G:
2986                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2987                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2988                 break;
2989         default:
2990                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2991                 return -EINVAL;
2992         }
2993
2994         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2995
2996         ret = hns3_cmd_send(hw, &desc, 1);
2997         if (ret)
2998                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2999
3000         return ret;
3001 }
3002
3003 static int
3004 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3005 {
3006         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3007         struct hns3_pf *pf = &hns->pf;
3008         struct hns3_priv_buf *priv;
3009         uint32_t i, total_size;
3010
3011         total_size = pf->pkt_buf_size;
3012
3013         /* alloc tx buffer for all enabled tc */
3014         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3015                 priv = &buf_alloc->priv_buf[i];
3016
3017                 if (hw->hw_tc_map & BIT(i)) {
3018                         if (total_size < pf->tx_buf_size)
3019                                 return -ENOMEM;
3020
3021                         priv->tx_buf_size = pf->tx_buf_size;
3022                 } else
3023                         priv->tx_buf_size = 0;
3024
3025                 total_size -= priv->tx_buf_size;
3026         }
3027
3028         return 0;
3029 }
3030
3031 static int
3032 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3033 {
3034 /* TX buffer size is unit by 128 byte */
3035 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3036 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3037         struct hns3_tx_buff_alloc_cmd *req;
3038         struct hns3_cmd_desc desc;
3039         uint32_t buf_size;
3040         uint32_t i;
3041         int ret;
3042
3043         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3044
3045         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3046         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3047                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3048
3049                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3050                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3051                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3052         }
3053
3054         ret = hns3_cmd_send(hw, &desc, 1);
3055         if (ret)
3056                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3057
3058         return ret;
3059 }
3060
3061 static int
3062 hns3_get_tc_num(struct hns3_hw *hw)
3063 {
3064         int cnt = 0;
3065         uint8_t i;
3066
3067         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3068                 if (hw->hw_tc_map & BIT(i))
3069                         cnt++;
3070         return cnt;
3071 }
3072
3073 static uint32_t
3074 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3075 {
3076         struct hns3_priv_buf *priv;
3077         uint32_t rx_priv = 0;
3078         int i;
3079
3080         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3081                 priv = &buf_alloc->priv_buf[i];
3082                 if (priv->enable)
3083                         rx_priv += priv->buf_size;
3084         }
3085         return rx_priv;
3086 }
3087
3088 static uint32_t
3089 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3090 {
3091         uint32_t total_tx_size = 0;
3092         uint32_t i;
3093
3094         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3095                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3096
3097         return total_tx_size;
3098 }
3099
3100 /* Get the number of pfc enabled TCs, which have private buffer */
3101 static int
3102 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3103 {
3104         struct hns3_priv_buf *priv;
3105         int cnt = 0;
3106         uint8_t i;
3107
3108         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3109                 priv = &buf_alloc->priv_buf[i];
3110                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3111                         cnt++;
3112         }
3113
3114         return cnt;
3115 }
3116
3117 /* Get the number of pfc disabled TCs, which have private buffer */
3118 static int
3119 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3120                          struct hns3_pkt_buf_alloc *buf_alloc)
3121 {
3122         struct hns3_priv_buf *priv;
3123         int cnt = 0;
3124         uint8_t i;
3125
3126         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3127                 priv = &buf_alloc->priv_buf[i];
3128                 if (hw->hw_tc_map & BIT(i) &&
3129                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3130                         cnt++;
3131         }
3132
3133         return cnt;
3134 }
3135
3136 static bool
3137 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3138                   uint32_t rx_all)
3139 {
3140         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3141         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3142         struct hns3_pf *pf = &hns->pf;
3143         uint32_t shared_buf, aligned_mps;
3144         uint32_t rx_priv;
3145         uint8_t tc_num;
3146         uint8_t i;
3147
3148         tc_num = hns3_get_tc_num(hw);
3149         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3150
3151         if (hns3_dev_dcb_supported(hw))
3152                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3153                                         pf->dv_buf_size;
3154         else
3155                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3156                                         + pf->dv_buf_size;
3157
3158         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3159         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3160                              HNS3_BUF_SIZE_UNIT);
3161
3162         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3163         if (rx_all < rx_priv + shared_std)
3164                 return false;
3165
3166         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3167         buf_alloc->s_buf.buf_size = shared_buf;
3168         if (hns3_dev_dcb_supported(hw)) {
3169                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3170                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3171                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3172                                   HNS3_BUF_SIZE_UNIT);
3173         } else {
3174                 buf_alloc->s_buf.self.high =
3175                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3176                 buf_alloc->s_buf.self.low = aligned_mps;
3177         }
3178
3179         if (hns3_dev_dcb_supported(hw)) {
3180                 hi_thrd = shared_buf - pf->dv_buf_size;
3181
3182                 if (tc_num <= NEED_RESERVE_TC_NUM)
3183                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3184                                         / BUF_MAX_PERCENT;
3185
3186                 if (tc_num)
3187                         hi_thrd = hi_thrd / tc_num;
3188
3189                 hi_thrd = max_t(uint32_t, hi_thrd,
3190                                 HNS3_BUF_MUL_BY * aligned_mps);
3191                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3192                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3193         } else {
3194                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3195                 lo_thrd = aligned_mps;
3196         }
3197
3198         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3199                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3200                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3201         }
3202
3203         return true;
3204 }
3205
3206 static bool
3207 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3208                      struct hns3_pkt_buf_alloc *buf_alloc)
3209 {
3210         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3211         struct hns3_pf *pf = &hns->pf;
3212         struct hns3_priv_buf *priv;
3213         uint32_t aligned_mps;
3214         uint32_t rx_all;
3215         uint8_t i;
3216
3217         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3218         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3219
3220         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3221                 priv = &buf_alloc->priv_buf[i];
3222
3223                 priv->enable = 0;
3224                 priv->wl.low = 0;
3225                 priv->wl.high = 0;
3226                 priv->buf_size = 0;
3227
3228                 if (!(hw->hw_tc_map & BIT(i)))
3229                         continue;
3230
3231                 priv->enable = 1;
3232                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3233                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3234                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3235                                                 HNS3_BUF_SIZE_UNIT);
3236                 } else {
3237                         priv->wl.low = 0;
3238                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3239                                         aligned_mps;
3240                 }
3241
3242                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3243         }
3244
3245         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3246 }
3247
3248 static bool
3249 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3250                              struct hns3_pkt_buf_alloc *buf_alloc)
3251 {
3252         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3253         struct hns3_pf *pf = &hns->pf;
3254         struct hns3_priv_buf *priv;
3255         int no_pfc_priv_num;
3256         uint32_t rx_all;
3257         uint8_t mask;
3258         int i;
3259
3260         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3261         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3262
3263         /* let the last to be cleared first */
3264         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3265                 priv = &buf_alloc->priv_buf[i];
3266                 mask = BIT((uint8_t)i);
3267
3268                 if (hw->hw_tc_map & mask &&
3269                     !(hw->dcb_info.hw_pfc_map & mask)) {
3270                         /* Clear the no pfc TC private buffer */
3271                         priv->wl.low = 0;
3272                         priv->wl.high = 0;
3273                         priv->buf_size = 0;
3274                         priv->enable = 0;
3275                         no_pfc_priv_num--;
3276                 }
3277
3278                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3279                     no_pfc_priv_num == 0)
3280                         break;
3281         }
3282
3283         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3284 }
3285
3286 static bool
3287 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3288                            struct hns3_pkt_buf_alloc *buf_alloc)
3289 {
3290         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3291         struct hns3_pf *pf = &hns->pf;
3292         struct hns3_priv_buf *priv;
3293         uint32_t rx_all;
3294         int pfc_priv_num;
3295         uint8_t mask;
3296         int i;
3297
3298         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3299         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3300
3301         /* let the last to be cleared first */
3302         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3303                 priv = &buf_alloc->priv_buf[i];
3304                 mask = BIT((uint8_t)i);
3305
3306                 if (hw->hw_tc_map & mask &&
3307                     hw->dcb_info.hw_pfc_map & mask) {
3308                         /* Reduce the number of pfc TC with private buffer */
3309                         priv->wl.low = 0;
3310                         priv->enable = 0;
3311                         priv->wl.high = 0;
3312                         priv->buf_size = 0;
3313                         pfc_priv_num--;
3314                 }
3315                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3316                     pfc_priv_num == 0)
3317                         break;
3318         }
3319
3320         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3321 }
3322
3323 static bool
3324 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3325                           struct hns3_pkt_buf_alloc *buf_alloc)
3326 {
3327 #define COMPENSATE_BUFFER       0x3C00
3328 #define COMPENSATE_HALF_MPS_NUM 5
3329 #define PRIV_WL_GAP             0x1800
3330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3331         struct hns3_pf *pf = &hns->pf;
3332         uint32_t tc_num = hns3_get_tc_num(hw);
3333         uint32_t half_mps = pf->mps >> 1;
3334         struct hns3_priv_buf *priv;
3335         uint32_t min_rx_priv;
3336         uint32_t rx_priv;
3337         uint8_t i;
3338
3339         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3340         if (tc_num)
3341                 rx_priv = rx_priv / tc_num;
3342
3343         if (tc_num <= NEED_RESERVE_TC_NUM)
3344                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3345
3346         /*
3347          * Minimum value of private buffer in rx direction (min_rx_priv) is
3348          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3349          * buffer if rx_priv is greater than min_rx_priv.
3350          */
3351         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3352                         COMPENSATE_HALF_MPS_NUM * half_mps;
3353         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3354         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3355
3356         if (rx_priv < min_rx_priv)
3357                 return false;
3358
3359         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3360                 priv = &buf_alloc->priv_buf[i];
3361
3362                 priv->enable = 0;
3363                 priv->wl.low = 0;
3364                 priv->wl.high = 0;
3365                 priv->buf_size = 0;
3366
3367                 if (!(hw->hw_tc_map & BIT(i)))
3368                         continue;
3369
3370                 priv->enable = 1;
3371                 priv->buf_size = rx_priv;
3372                 priv->wl.high = rx_priv - pf->dv_buf_size;
3373                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3374         }
3375
3376         buf_alloc->s_buf.buf_size = 0;
3377
3378         return true;
3379 }
3380
3381 /*
3382  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3383  * @hw: pointer to struct hns3_hw
3384  * @buf_alloc: pointer to buffer calculation data
3385  * @return: 0: calculate sucessful, negative: fail
3386  */
3387 static int
3388 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3389 {
3390         /* When DCB is not supported, rx private buffer is not allocated. */
3391         if (!hns3_dev_dcb_supported(hw)) {
3392                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3393                 struct hns3_pf *pf = &hns->pf;
3394                 uint32_t rx_all = pf->pkt_buf_size;
3395
3396                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3397                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3398                         return -ENOMEM;
3399
3400                 return 0;
3401         }
3402
3403         /*
3404          * Try to allocate privated packet buffer for all TCs without share
3405          * buffer.
3406          */
3407         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3408                 return 0;
3409
3410         /*
3411          * Try to allocate privated packet buffer for all TCs with share
3412          * buffer.
3413          */
3414         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3415                 return 0;
3416
3417         /*
3418          * For different application scenes, the enabled port number, TC number
3419          * and no_drop TC number are different. In order to obtain the better
3420          * performance, software could allocate the buffer size and configure
3421          * the waterline by tring to decrease the private buffer size according
3422          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3423          * enabled tc.
3424          */
3425         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3426                 return 0;
3427
3428         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3429                 return 0;
3430
3431         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3432                 return 0;
3433
3434         return -ENOMEM;
3435 }
3436
3437 static int
3438 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3439 {
3440         struct hns3_rx_priv_buff_cmd *req;
3441         struct hns3_cmd_desc desc;
3442         uint32_t buf_size;
3443         int ret;
3444         int i;
3445
3446         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3447         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3448
3449         /* Alloc private buffer TCs */
3450         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3451                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3452
3453                 req->buf_num[i] =
3454                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3455                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3456         }
3457
3458         buf_size = buf_alloc->s_buf.buf_size;
3459         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3460                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3461
3462         ret = hns3_cmd_send(hw, &desc, 1);
3463         if (ret)
3464                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3465
3466         return ret;
3467 }
3468
3469 static int
3470 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3471 {
3472 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3473         struct hns3_rx_priv_wl_buf *req;
3474         struct hns3_priv_buf *priv;
3475         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3476         int i, j;
3477         int ret;
3478
3479         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3480                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3481                                           false);
3482                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3483
3484                 /* The first descriptor set the NEXT bit to 1 */
3485                 if (i == 0)
3486                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3487                 else
3488                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3489
3490                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3491                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3492
3493                         priv = &buf_alloc->priv_buf[idx];
3494                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3495                                                         HNS3_BUF_UNIT_S);
3496                         req->tc_wl[j].high |=
3497                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3498                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3499                                                         HNS3_BUF_UNIT_S);
3500                         req->tc_wl[j].low |=
3501                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3502                 }
3503         }
3504
3505         /* Send 2 descriptor at one time */
3506         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3507         if (ret)
3508                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3509                              ret);
3510         return ret;
3511 }
3512
3513 static int
3514 hns3_common_thrd_config(struct hns3_hw *hw,
3515                         struct hns3_pkt_buf_alloc *buf_alloc)
3516 {
3517 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3518         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3519         struct hns3_rx_com_thrd *req;
3520         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3521         struct hns3_tc_thrd *tc;
3522         int tc_idx;
3523         int i, j;
3524         int ret;
3525
3526         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3527                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3528                                           false);
3529                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3530
3531                 /* The first descriptor set the NEXT bit to 1 */
3532                 if (i == 0)
3533                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3534                 else
3535                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3536
3537                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3538                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3539                         tc = &s_buf->tc_thrd[tc_idx];
3540
3541                         req->com_thrd[j].high =
3542                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3543                         req->com_thrd[j].high |=
3544                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3545                         req->com_thrd[j].low =
3546                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3547                         req->com_thrd[j].low |=
3548                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3549                 }
3550         }
3551
3552         /* Send 2 descriptors at one time */
3553         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3554         if (ret)
3555                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3556
3557         return ret;
3558 }
3559
3560 static int
3561 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3562 {
3563         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3564         struct hns3_rx_com_wl *req;
3565         struct hns3_cmd_desc desc;
3566         int ret;
3567
3568         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3569
3570         req = (struct hns3_rx_com_wl *)desc.data;
3571         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3572         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3573
3574         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3575         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3576
3577         ret = hns3_cmd_send(hw, &desc, 1);
3578         if (ret)
3579                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3580
3581         return ret;
3582 }
3583
3584 int
3585 hns3_buffer_alloc(struct hns3_hw *hw)
3586 {
3587         struct hns3_pkt_buf_alloc pkt_buf;
3588         int ret;
3589
3590         memset(&pkt_buf, 0, sizeof(pkt_buf));
3591         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3592         if (ret) {
3593                 PMD_INIT_LOG(ERR,
3594                              "could not calc tx buffer size for all TCs %d",
3595                              ret);
3596                 return ret;
3597         }
3598
3599         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3600         if (ret) {
3601                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3602                 return ret;
3603         }
3604
3605         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3606         if (ret) {
3607                 PMD_INIT_LOG(ERR,
3608                              "could not calc rx priv buffer size for all TCs %d",
3609                              ret);
3610                 return ret;
3611         }
3612
3613         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3614         if (ret) {
3615                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3616                 return ret;
3617         }
3618
3619         if (hns3_dev_dcb_supported(hw)) {
3620                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3621                 if (ret) {
3622                         PMD_INIT_LOG(ERR,
3623                                      "could not configure rx private waterline %d",
3624                                      ret);
3625                         return ret;
3626                 }
3627
3628                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3629                 if (ret) {
3630                         PMD_INIT_LOG(ERR,
3631                                      "could not configure common threshold %d",
3632                                      ret);
3633                         return ret;
3634                 }
3635         }
3636
3637         ret = hns3_common_wl_config(hw, &pkt_buf);
3638         if (ret)
3639                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3640                              ret);
3641
3642         return ret;
3643 }
3644
3645 static int
3646 hns3_mac_init(struct hns3_hw *hw)
3647 {
3648         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3649         struct hns3_mac *mac = &hw->mac;
3650         struct hns3_pf *pf = &hns->pf;
3651         int ret;
3652
3653         pf->support_sfp_query = true;
3654         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3655         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3656         if (ret) {
3657                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3658                 return ret;
3659         }
3660
3661         mac->link_status = ETH_LINK_DOWN;
3662
3663         return hns3_config_mtu(hw, pf->mps);
3664 }
3665
3666 static int
3667 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3668 {
3669 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3670 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3671 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3672 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3673         int return_status;
3674
3675         if (cmdq_resp) {
3676                 PMD_INIT_LOG(ERR,
3677                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3678                              cmdq_resp);
3679                 return -EIO;
3680         }
3681
3682         switch (resp_code) {
3683         case HNS3_ETHERTYPE_SUCCESS_ADD:
3684         case HNS3_ETHERTYPE_ALREADY_ADD:
3685                 return_status = 0;
3686                 break;
3687         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3688                 PMD_INIT_LOG(ERR,
3689                              "add mac ethertype failed for manager table overflow.");
3690                 return_status = -EIO;
3691                 break;
3692         case HNS3_ETHERTYPE_KEY_CONFLICT:
3693                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3694                 return_status = -EIO;
3695                 break;
3696         default:
3697                 PMD_INIT_LOG(ERR,
3698                              "add mac ethertype failed for undefined, code=%d.",
3699                              resp_code);
3700                 return_status = -EIO;
3701                 break;
3702         }
3703
3704         return return_status;
3705 }
3706
3707 static int
3708 hns3_add_mgr_tbl(struct hns3_hw *hw,
3709                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3710 {
3711         struct hns3_cmd_desc desc;
3712         uint8_t resp_code;
3713         uint16_t retval;
3714         int ret;
3715
3716         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3717         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3718
3719         ret = hns3_cmd_send(hw, &desc, 1);
3720         if (ret) {
3721                 PMD_INIT_LOG(ERR,
3722                              "add mac ethertype failed for cmd_send, ret =%d.",
3723                              ret);
3724                 return ret;
3725         }
3726
3727         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3728         retval = rte_le_to_cpu_16(desc.retval);
3729
3730         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3731 }
3732
3733 static void
3734 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3735                      int *table_item_num)
3736 {
3737         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3738
3739         /*
3740          * In current version, we add one item in management table as below:
3741          * 0x0180C200000E -- LLDP MC address
3742          */
3743         tbl = mgr_table;
3744         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3745         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3746         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3747         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3748         tbl->i_port_bitmap = 0x1;
3749         *table_item_num = 1;
3750 }
3751
3752 static int
3753 hns3_init_mgr_tbl(struct hns3_hw *hw)
3754 {
3755 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3756         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3757         int table_item_num;
3758         int ret;
3759         int i;
3760
3761         memset(mgr_table, 0, sizeof(mgr_table));
3762         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3763         for (i = 0; i < table_item_num; i++) {
3764                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3765                 if (ret) {
3766                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3767                                      ret);
3768                         return ret;
3769                 }
3770         }
3771
3772         return 0;
3773 }
3774
3775 static void
3776 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3777                         bool en_mc, bool en_bc, int vport_id)
3778 {
3779         if (!param)
3780                 return;
3781
3782         memset(param, 0, sizeof(struct hns3_promisc_param));
3783         if (en_uc)
3784                 param->enable = HNS3_PROMISC_EN_UC;
3785         if (en_mc)
3786                 param->enable |= HNS3_PROMISC_EN_MC;
3787         if (en_bc)
3788                 param->enable |= HNS3_PROMISC_EN_BC;
3789         param->vf_id = vport_id;
3790 }
3791
3792 static int
3793 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3794 {
3795         struct hns3_promisc_cfg_cmd *req;
3796         struct hns3_cmd_desc desc;
3797         int ret;
3798
3799         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3800
3801         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3802         req->vf_id = param->vf_id;
3803         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3804             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3805
3806         ret = hns3_cmd_send(hw, &desc, 1);
3807         if (ret)
3808                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3809
3810         return ret;
3811 }
3812
3813 static int
3814 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3815 {
3816         struct hns3_promisc_param param;
3817         bool en_bc_pmc = true;
3818         uint8_t vf_id;
3819
3820         /*
3821          * In current version VF is not supported when PF is driven by DPDK
3822          * driver, the PF-related vf_id is 0, just need to configure parameters
3823          * for vf_id 0.
3824          */
3825         vf_id = 0;
3826
3827         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3828         return hns3_cmd_set_promisc_mode(hw, &param);
3829 }
3830
3831 static int
3832 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3833 {
3834         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3835         struct hns3_pf *pf = &hns->pf;
3836         struct hns3_promisc_param param;
3837         uint16_t func_id;
3838         int ret;
3839
3840         /* func_id 0 is denoted PF, the VFs start from 1 */
3841         for (func_id = 1; func_id < pf->func_num; func_id++) {
3842                 hns3_promisc_param_init(&param, false, false, false, func_id);
3843                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3844                 if (ret)
3845                         return ret;
3846         }
3847
3848         return 0;
3849 }
3850
3851 static int
3852 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3853 {
3854         bool allmulti = dev->data->all_multicast ? true : false;
3855         struct hns3_adapter *hns = dev->data->dev_private;
3856         struct hns3_hw *hw = &hns->hw;
3857         uint64_t offloads;
3858         int err;
3859         int ret;
3860
3861         rte_spinlock_lock(&hw->lock);
3862         ret = hns3_set_promisc_mode(hw, true, true);
3863         if (ret) {
3864                 rte_spinlock_unlock(&hw->lock);
3865                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3866                          ret);
3867                 return ret;
3868         }
3869
3870         /*
3871          * When promiscuous mode was enabled, disable the vlan filter to let
3872          * all packets coming in in the receiving direction.
3873          */
3874         offloads = dev->data->dev_conf.rxmode.offloads;
3875         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3876                 ret = hns3_enable_vlan_filter(hns, false);
3877                 if (ret) {
3878                         hns3_err(hw, "failed to enable promiscuous mode due to "
3879                                      "failure to disable vlan filter, ret = %d",
3880                                  ret);
3881                         err = hns3_set_promisc_mode(hw, false, allmulti);
3882                         if (err)
3883                                 hns3_err(hw, "failed to restore promiscuous "
3884                                          "status after disable vlan filter "
3885                                          "failed during enabling promiscuous "
3886                                          "mode, ret = %d", ret);
3887                 }
3888         }
3889
3890         rte_spinlock_unlock(&hw->lock);
3891
3892         return ret;
3893 }
3894
3895 static int
3896 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3897 {
3898         bool allmulti = dev->data->all_multicast ? true : false;
3899         struct hns3_adapter *hns = dev->data->dev_private;
3900         struct hns3_hw *hw = &hns->hw;
3901         uint64_t offloads;
3902         int err;
3903         int ret;
3904
3905         /* If now in all_multicast mode, must remain in all_multicast mode. */
3906         rte_spinlock_lock(&hw->lock);
3907         ret = hns3_set_promisc_mode(hw, false, allmulti);
3908         if (ret) {
3909                 rte_spinlock_unlock(&hw->lock);
3910                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3911                          ret);
3912                 return ret;
3913         }
3914         /* when promiscuous mode was disabled, restore the vlan filter status */
3915         offloads = dev->data->dev_conf.rxmode.offloads;
3916         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3917                 ret = hns3_enable_vlan_filter(hns, true);
3918                 if (ret) {
3919                         hns3_err(hw, "failed to disable promiscuous mode due to"
3920                                  " failure to restore vlan filter, ret = %d",
3921                                  ret);
3922                         err = hns3_set_promisc_mode(hw, true, true);
3923                         if (err)
3924                                 hns3_err(hw, "failed to restore promiscuous "
3925                                          "status after enabling vlan filter "
3926                                          "failed during disabling promiscuous "
3927                                          "mode, ret = %d", ret);
3928                 }
3929         }
3930         rte_spinlock_unlock(&hw->lock);
3931
3932         return ret;
3933 }
3934
3935 static int
3936 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3937 {
3938         struct hns3_adapter *hns = dev->data->dev_private;
3939         struct hns3_hw *hw = &hns->hw;
3940         int ret;
3941
3942         if (dev->data->promiscuous)
3943                 return 0;
3944
3945         rte_spinlock_lock(&hw->lock);
3946         ret = hns3_set_promisc_mode(hw, false, true);
3947         rte_spinlock_unlock(&hw->lock);
3948         if (ret)
3949                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3950                          ret);
3951
3952         return ret;
3953 }
3954
3955 static int
3956 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3957 {
3958         struct hns3_adapter *hns = dev->data->dev_private;
3959         struct hns3_hw *hw = &hns->hw;
3960         int ret;
3961
3962         /* If now in promiscuous mode, must remain in all_multicast mode. */
3963         if (dev->data->promiscuous)
3964                 return 0;
3965
3966         rte_spinlock_lock(&hw->lock);
3967         ret = hns3_set_promisc_mode(hw, false, false);
3968         rte_spinlock_unlock(&hw->lock);
3969         if (ret)
3970                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
3971                          ret);
3972
3973         return ret;
3974 }
3975
3976 static int
3977 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3978 {
3979         struct hns3_hw *hw = &hns->hw;
3980         bool allmulti = hw->data->all_multicast ? true : false;
3981         int ret;
3982
3983         if (hw->data->promiscuous) {
3984                 ret = hns3_set_promisc_mode(hw, true, true);
3985                 if (ret)
3986                         hns3_err(hw, "failed to restore promiscuous mode, "
3987                                  "ret = %d", ret);
3988                 return ret;
3989         }
3990
3991         ret = hns3_set_promisc_mode(hw, false, allmulti);
3992         if (ret)
3993                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
3994                          ret);
3995         return ret;
3996 }
3997
3998 static int
3999 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4000 {
4001         struct hns3_sfp_speed_cmd *resp;
4002         struct hns3_cmd_desc desc;
4003         int ret;
4004
4005         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4006         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4007         ret = hns3_cmd_send(hw, &desc, 1);
4008         if (ret == -EOPNOTSUPP) {
4009                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4010                 return ret;
4011         } else if (ret) {
4012                 hns3_err(hw, "get sfp speed failed %d", ret);
4013                 return ret;
4014         }
4015
4016         *speed = resp->sfp_speed;
4017
4018         return 0;
4019 }
4020
4021 static uint8_t
4022 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4023 {
4024         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4025                 duplex = ETH_LINK_FULL_DUPLEX;
4026
4027         return duplex;
4028 }
4029
4030 static int
4031 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4032 {
4033         struct hns3_mac *mac = &hw->mac;
4034         int ret;
4035
4036         duplex = hns3_check_speed_dup(duplex, speed);
4037         if (mac->link_speed == speed && mac->link_duplex == duplex)
4038                 return 0;
4039
4040         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4041         if (ret)
4042                 return ret;
4043
4044         mac->link_speed = speed;
4045         mac->link_duplex = duplex;
4046
4047         return 0;
4048 }
4049
4050 static int
4051 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4052 {
4053         struct hns3_adapter *hns = eth_dev->data->dev_private;
4054         struct hns3_hw *hw = &hns->hw;
4055         struct hns3_pf *pf = &hns->pf;
4056         uint32_t speed;
4057         int ret;
4058
4059         /* If IMP do not support get SFP/qSFP speed, return directly */
4060         if (!pf->support_sfp_query)
4061                 return 0;
4062
4063         ret = hns3_get_sfp_speed(hw, &speed);
4064         if (ret == -EOPNOTSUPP) {
4065                 pf->support_sfp_query = false;
4066                 return ret;
4067         } else if (ret)
4068                 return ret;
4069
4070         if (speed == ETH_SPEED_NUM_NONE)
4071                 return 0; /* do nothing if no SFP */
4072
4073         /* Config full duplex for SFP */
4074         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4075 }
4076
4077 static int
4078 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4079 {
4080         struct hns3_config_mac_mode_cmd *req;
4081         struct hns3_cmd_desc desc;
4082         uint32_t loop_en = 0;
4083         uint8_t val = 0;
4084         int ret;
4085
4086         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4087
4088         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4089         if (enable)
4090                 val = 1;
4091         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4092         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4093         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4094         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4095         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4096         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4097         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4098         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4099         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4100         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4101         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4102         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4103         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4104         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4105         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4106
4107         ret = hns3_cmd_send(hw, &desc, 1);
4108         if (ret)
4109                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4110
4111         return ret;
4112 }
4113
4114 static int
4115 hns3_get_mac_link_status(struct hns3_hw *hw)
4116 {
4117         struct hns3_link_status_cmd *req;
4118         struct hns3_cmd_desc desc;
4119         int link_status;
4120         int ret;
4121
4122         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4123         ret = hns3_cmd_send(hw, &desc, 1);
4124         if (ret) {
4125                 hns3_err(hw, "get link status cmd failed %d", ret);
4126                 return ETH_LINK_DOWN;
4127         }
4128
4129         req = (struct hns3_link_status_cmd *)desc.data;
4130         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4131
4132         return !!link_status;
4133 }
4134
4135 void
4136 hns3_update_link_status(struct hns3_hw *hw)
4137 {
4138         int state;
4139
4140         state = hns3_get_mac_link_status(hw);
4141         if (state != hw->mac.link_status) {
4142                 hw->mac.link_status = state;
4143                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4144         }
4145 }
4146
4147 static void
4148 hns3_service_handler(void *param)
4149 {
4150         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4151         struct hns3_adapter *hns = eth_dev->data->dev_private;
4152         struct hns3_hw *hw = &hns->hw;
4153
4154         if (!hns3_is_reset_pending(hns)) {
4155                 hns3_update_speed_duplex(eth_dev);
4156                 hns3_update_link_status(hw);
4157         } else
4158                 hns3_warn(hw, "Cancel the query when reset is pending");
4159
4160         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4161 }
4162
4163 static int
4164 hns3_init_hardware(struct hns3_adapter *hns)
4165 {
4166         struct hns3_hw *hw = &hns->hw;
4167         int ret;
4168
4169         ret = hns3_map_tqp(hw);
4170         if (ret) {
4171                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4172                 return ret;
4173         }
4174
4175         ret = hns3_init_umv_space(hw);
4176         if (ret) {
4177                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4178                 return ret;
4179         }
4180
4181         ret = hns3_mac_init(hw);
4182         if (ret) {
4183                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4184                 goto err_mac_init;
4185         }
4186
4187         ret = hns3_init_mgr_tbl(hw);
4188         if (ret) {
4189                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4190                 goto err_mac_init;
4191         }
4192
4193         ret = hns3_set_promisc_mode(hw, false, false);
4194         if (ret) {
4195                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4196                 goto err_mac_init;
4197         }
4198
4199         ret = hns3_clear_all_vfs_promisc_mode(hw);
4200         if (ret) {
4201                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4202                              ret);
4203                 goto err_mac_init;
4204         }
4205
4206         ret = hns3_init_vlan_config(hns);
4207         if (ret) {
4208                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4209                 goto err_mac_init;
4210         }
4211
4212         ret = hns3_dcb_init(hw);
4213         if (ret) {
4214                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4215                 goto err_mac_init;
4216         }
4217
4218         ret = hns3_init_fd_config(hns);
4219         if (ret) {
4220                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4221                 goto err_mac_init;
4222         }
4223
4224         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4225         if (ret) {
4226                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4227                 goto err_mac_init;
4228         }
4229
4230         ret = hns3_config_gro(hw, false);
4231         if (ret) {
4232                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4233                 goto err_mac_init;
4234         }
4235
4236         /*
4237          * In the initialization clearing the all hardware mapping relationship
4238          * configurations between queues and interrupt vectors is needed, so
4239          * some error caused by the residual configurations, such as the
4240          * unexpected interrupt, can be avoid.
4241          */
4242         ret = hns3_init_ring_with_vector(hw);
4243         if (ret) {
4244                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4245                 goto err_mac_init;
4246         }
4247
4248         return 0;
4249
4250 err_mac_init:
4251         hns3_uninit_umv_space(hw);
4252         return ret;
4253 }
4254
4255 static int
4256 hns3_init_pf(struct rte_eth_dev *eth_dev)
4257 {
4258         struct rte_device *dev = eth_dev->device;
4259         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4260         struct hns3_adapter *hns = eth_dev->data->dev_private;
4261         struct hns3_hw *hw = &hns->hw;
4262         int ret;
4263
4264         PMD_INIT_FUNC_TRACE();
4265
4266         /* Get hardware io base address from pcie BAR2 IO space */
4267         hw->io_base = pci_dev->mem_resource[2].addr;
4268
4269         /* Firmware command queue initialize */
4270         ret = hns3_cmd_init_queue(hw);
4271         if (ret) {
4272                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4273                 goto err_cmd_init_queue;
4274         }
4275
4276         hns3_clear_all_event_cause(hw);
4277
4278         /* Firmware command initialize */
4279         ret = hns3_cmd_init(hw);
4280         if (ret) {
4281                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4282                 goto err_cmd_init;
4283         }
4284
4285         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4286                                          hns3_interrupt_handler,
4287                                          eth_dev);
4288         if (ret) {
4289                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4290                 goto err_intr_callback_register;
4291         }
4292
4293         /* Enable interrupt */
4294         rte_intr_enable(&pci_dev->intr_handle);
4295         hns3_pf_enable_irq0(hw);
4296
4297         /* Get configuration */
4298         ret = hns3_get_configuration(hw);
4299         if (ret) {
4300                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4301                 goto err_get_config;
4302         }
4303
4304         ret = hns3_init_hardware(hns);
4305         if (ret) {
4306                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4307                 goto err_get_config;
4308         }
4309
4310         /* Initialize flow director filter list & hash */
4311         ret = hns3_fdir_filter_init(hns);
4312         if (ret) {
4313                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4314                 goto err_hw_init;
4315         }
4316
4317         hns3_set_default_rss_args(hw);
4318
4319         ret = hns3_enable_hw_error_intr(hns, true);
4320         if (ret) {
4321                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4322                              ret);
4323                 goto err_fdir;
4324         }
4325
4326         return 0;
4327
4328 err_fdir:
4329         hns3_fdir_filter_uninit(hns);
4330 err_hw_init:
4331         hns3_uninit_umv_space(hw);
4332
4333 err_get_config:
4334         hns3_pf_disable_irq0(hw);
4335         rte_intr_disable(&pci_dev->intr_handle);
4336         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4337                              eth_dev);
4338 err_intr_callback_register:
4339 err_cmd_init:
4340         hns3_cmd_uninit(hw);
4341         hns3_cmd_destroy_queue(hw);
4342 err_cmd_init_queue:
4343         hw->io_base = NULL;
4344
4345         return ret;
4346 }
4347
4348 static void
4349 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4350 {
4351         struct hns3_adapter *hns = eth_dev->data->dev_private;
4352         struct rte_device *dev = eth_dev->device;
4353         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4354         struct hns3_hw *hw = &hns->hw;
4355
4356         PMD_INIT_FUNC_TRACE();
4357
4358         hns3_enable_hw_error_intr(hns, false);
4359         hns3_rss_uninit(hns);
4360         hns3_fdir_filter_uninit(hns);
4361         hns3_uninit_umv_space(hw);
4362         hns3_pf_disable_irq0(hw);
4363         rte_intr_disable(&pci_dev->intr_handle);
4364         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4365                              eth_dev);
4366         hns3_cmd_uninit(hw);
4367         hns3_cmd_destroy_queue(hw);
4368         hw->io_base = NULL;
4369 }
4370
4371 static int
4372 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4373 {
4374         struct hns3_hw *hw = &hns->hw;
4375         int ret;
4376
4377         ret = hns3_dcb_cfg_update(hns);
4378         if (ret)
4379                 return ret;
4380
4381         /* Enable queues */
4382         ret = hns3_start_queues(hns, reset_queue);
4383         if (ret) {
4384                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4385                 return ret;
4386         }
4387
4388         /* Enable MAC */
4389         ret = hns3_cfg_mac_mode(hw, true);
4390         if (ret) {
4391                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4392                 goto err_config_mac_mode;
4393         }
4394         return 0;
4395
4396 err_config_mac_mode:
4397         hns3_stop_queues(hns, true);
4398         return ret;
4399 }
4400
4401 static int
4402 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4403 {
4404         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4405         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4406         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4408         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4409         uint32_t intr_vector;
4410         uint16_t q_id;
4411         int ret;
4412
4413         if (dev->data->dev_conf.intr_conf.rxq == 0)
4414                 return 0;
4415
4416         /* disable uio/vfio intr/eventfd mapping */
4417         rte_intr_disable(intr_handle);
4418
4419         /* check and configure queue intr-vector mapping */
4420         if (rte_intr_cap_multiple(intr_handle) ||
4421             !RTE_ETH_DEV_SRIOV(dev).active) {
4422                 intr_vector = hw->used_rx_queues;
4423                 /* creates event fd for each intr vector when MSIX is used */
4424                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4425                         return -EINVAL;
4426         }
4427         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4428                 intr_handle->intr_vec =
4429                         rte_zmalloc("intr_vec",
4430                                     hw->used_rx_queues * sizeof(int), 0);
4431                 if (intr_handle->intr_vec == NULL) {
4432                         hns3_err(hw, "Failed to allocate %d rx_queues"
4433                                      " intr_vec", hw->used_rx_queues);
4434                         ret = -ENOMEM;
4435                         goto alloc_intr_vec_error;
4436                 }
4437         }
4438
4439         if (rte_intr_allow_others(intr_handle)) {
4440                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4441                 base = RTE_INTR_VEC_RXTX_OFFSET;
4442         }
4443         if (rte_intr_dp_is_en(intr_handle)) {
4444                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4445                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4446                                                          HNS3_RING_TYPE_RX,
4447                                                          q_id);
4448                         if (ret)
4449                                 goto bind_vector_error;
4450                         intr_handle->intr_vec[q_id] = vec;
4451                         if (vec < base + intr_handle->nb_efd - 1)
4452                                 vec++;
4453                 }
4454         }
4455         rte_intr_enable(intr_handle);
4456         return 0;
4457
4458 bind_vector_error:
4459         rte_intr_efd_disable(intr_handle);
4460         if (intr_handle->intr_vec) {
4461                 free(intr_handle->intr_vec);
4462                 intr_handle->intr_vec = NULL;
4463         }
4464         return ret;
4465 alloc_intr_vec_error:
4466         rte_intr_efd_disable(intr_handle);
4467         return ret;
4468 }
4469
4470 static int
4471 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4472 {
4473         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4475         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4476         uint16_t q_id;
4477         int ret;
4478
4479         if (dev->data->dev_conf.intr_conf.rxq == 0)
4480                 return 0;
4481
4482         if (rte_intr_dp_is_en(intr_handle)) {
4483                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4484                         ret = hns3_bind_ring_with_vector(hw,
4485                                         intr_handle->intr_vec[q_id], true,
4486                                         HNS3_RING_TYPE_RX, q_id);
4487                         if (ret)
4488                                 return ret;
4489                 }
4490         }
4491
4492         return 0;
4493 }
4494
4495 static void
4496 hns3_restore_filter(struct rte_eth_dev *dev)
4497 {
4498         hns3_restore_rss_filter(dev);
4499 }
4500
4501 static int
4502 hns3_dev_start(struct rte_eth_dev *dev)
4503 {
4504         struct hns3_adapter *hns = dev->data->dev_private;
4505         struct hns3_hw *hw = &hns->hw;
4506         int ret;
4507
4508         PMD_INIT_FUNC_TRACE();
4509         if (rte_atomic16_read(&hw->reset.resetting))
4510                 return -EBUSY;
4511
4512         rte_spinlock_lock(&hw->lock);
4513         hw->adapter_state = HNS3_NIC_STARTING;
4514
4515         ret = hns3_do_start(hns, true);
4516         if (ret) {
4517                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4518                 rte_spinlock_unlock(&hw->lock);
4519                 return ret;
4520         }
4521         ret = hns3_map_rx_interrupt(dev);
4522         if (ret) {
4523                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4524                 rte_spinlock_unlock(&hw->lock);
4525                 return ret;
4526         }
4527
4528         hw->adapter_state = HNS3_NIC_STARTED;
4529         rte_spinlock_unlock(&hw->lock);
4530
4531         hns3_set_rxtx_function(dev);
4532         hns3_mp_req_start_rxtx(dev);
4533         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4534
4535         hns3_restore_filter(dev);
4536
4537         /* Enable interrupt of all rx queues before enabling queues */
4538         hns3_dev_all_rx_queue_intr_enable(hw, true);
4539         /*
4540          * When finished the initialization, enable queues to receive/transmit
4541          * packets.
4542          */
4543         hns3_enable_all_queues(hw, true);
4544
4545         hns3_info(hw, "hns3 dev start successful!");
4546         return 0;
4547 }
4548
4549 static int
4550 hns3_do_stop(struct hns3_adapter *hns)
4551 {
4552         struct hns3_hw *hw = &hns->hw;
4553         bool reset_queue;
4554         int ret;
4555
4556         ret = hns3_cfg_mac_mode(hw, false);
4557         if (ret)
4558                 return ret;
4559         hw->mac.link_status = ETH_LINK_DOWN;
4560
4561         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4562                 hns3_configure_all_mac_addr(hns, true);
4563                 reset_queue = true;
4564         } else
4565                 reset_queue = false;
4566         hw->mac.default_addr_setted = false;
4567         return hns3_stop_queues(hns, reset_queue);
4568 }
4569
4570 static void
4571 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4572 {
4573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4575         struct hns3_adapter *hns = dev->data->dev_private;
4576         struct hns3_hw *hw = &hns->hw;
4577         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4578         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4579         uint16_t q_id;
4580
4581         if (dev->data->dev_conf.intr_conf.rxq == 0)
4582                 return;
4583
4584         /* unmap the ring with vector */
4585         if (rte_intr_allow_others(intr_handle)) {
4586                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4587                 base = RTE_INTR_VEC_RXTX_OFFSET;
4588         }
4589         if (rte_intr_dp_is_en(intr_handle)) {
4590                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4591                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4592                                                          HNS3_RING_TYPE_RX,
4593                                                          q_id);
4594                         if (vec < base + intr_handle->nb_efd - 1)
4595                                 vec++;
4596                 }
4597         }
4598         /* Clean datapath event and queue/vec mapping */
4599         rte_intr_efd_disable(intr_handle);
4600         if (intr_handle->intr_vec) {
4601                 rte_free(intr_handle->intr_vec);
4602                 intr_handle->intr_vec = NULL;
4603         }
4604 }
4605
4606 static void
4607 hns3_dev_stop(struct rte_eth_dev *dev)
4608 {
4609         struct hns3_adapter *hns = dev->data->dev_private;
4610         struct hns3_hw *hw = &hns->hw;
4611
4612         PMD_INIT_FUNC_TRACE();
4613
4614         hw->adapter_state = HNS3_NIC_STOPPING;
4615         hns3_set_rxtx_function(dev);
4616         rte_wmb();
4617         /* Disable datapath on secondary process. */
4618         hns3_mp_req_stop_rxtx(dev);
4619         /* Prevent crashes when queues are still in use. */
4620         rte_delay_ms(hw->tqps_num);
4621
4622         rte_spinlock_lock(&hw->lock);
4623         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4624                 hns3_do_stop(hns);
4625                 hns3_unmap_rx_interrupt(dev);
4626                 hns3_dev_release_mbufs(hns);
4627                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4628         }
4629         rte_eal_alarm_cancel(hns3_service_handler, dev);
4630         rte_spinlock_unlock(&hw->lock);
4631 }
4632
4633 static void
4634 hns3_dev_close(struct rte_eth_dev *eth_dev)
4635 {
4636         struct hns3_adapter *hns = eth_dev->data->dev_private;
4637         struct hns3_hw *hw = &hns->hw;
4638
4639         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4640                 rte_free(eth_dev->process_private);
4641                 eth_dev->process_private = NULL;
4642                 return;
4643         }
4644
4645         if (hw->adapter_state == HNS3_NIC_STARTED)
4646                 hns3_dev_stop(eth_dev);
4647
4648         hw->adapter_state = HNS3_NIC_CLOSING;
4649         hns3_reset_abort(hns);
4650         hw->adapter_state = HNS3_NIC_CLOSED;
4651
4652         hns3_configure_all_mc_mac_addr(hns, true);
4653         hns3_remove_all_vlan_table(hns);
4654         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4655         hns3_uninit_pf(eth_dev);
4656         hns3_free_all_queues(eth_dev);
4657         rte_free(hw->reset.wait_data);
4658         rte_free(eth_dev->process_private);
4659         eth_dev->process_private = NULL;
4660         hns3_mp_uninit_primary();
4661         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4662 }
4663
4664 static int
4665 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4666 {
4667         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4668         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4669
4670         fc_conf->pause_time = pf->pause_time;
4671
4672         /* return fc current mode */
4673         switch (hw->current_mode) {
4674         case HNS3_FC_FULL:
4675                 fc_conf->mode = RTE_FC_FULL;
4676                 break;
4677         case HNS3_FC_TX_PAUSE:
4678                 fc_conf->mode = RTE_FC_TX_PAUSE;
4679                 break;
4680         case HNS3_FC_RX_PAUSE:
4681                 fc_conf->mode = RTE_FC_RX_PAUSE;
4682                 break;
4683         case HNS3_FC_NONE:
4684         default:
4685                 fc_conf->mode = RTE_FC_NONE;
4686                 break;
4687         }
4688
4689         return 0;
4690 }
4691
4692 static void
4693 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4694 {
4695         switch (mode) {
4696         case RTE_FC_NONE:
4697                 hw->requested_mode = HNS3_FC_NONE;
4698                 break;
4699         case RTE_FC_RX_PAUSE:
4700                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4701                 break;
4702         case RTE_FC_TX_PAUSE:
4703                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4704                 break;
4705         case RTE_FC_FULL:
4706                 hw->requested_mode = HNS3_FC_FULL;
4707                 break;
4708         default:
4709                 hw->requested_mode = HNS3_FC_NONE;
4710                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4711                           "configured to RTE_FC_NONE", mode);
4712                 break;
4713         }
4714 }
4715
4716 static int
4717 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4718 {
4719         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4721         int ret;
4722
4723         if (fc_conf->high_water || fc_conf->low_water ||
4724             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4725                 hns3_err(hw, "Unsupported flow control settings specified, "
4726                          "high_water(%u), low_water(%u), send_xon(%u) and "
4727                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4728                          fc_conf->high_water, fc_conf->low_water,
4729                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4730                 return -EINVAL;
4731         }
4732         if (fc_conf->autoneg) {
4733                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4734                 return -EINVAL;
4735         }
4736         if (!fc_conf->pause_time) {
4737                 hns3_err(hw, "Invalid pause time %d setting.",
4738                          fc_conf->pause_time);
4739                 return -EINVAL;
4740         }
4741
4742         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4743             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4744                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4745                          "current_fc_status = %d", hw->current_fc_status);
4746                 return -EOPNOTSUPP;
4747         }
4748
4749         hns3_get_fc_mode(hw, fc_conf->mode);
4750         if (hw->requested_mode == hw->current_mode &&
4751             pf->pause_time == fc_conf->pause_time)
4752                 return 0;
4753
4754         rte_spinlock_lock(&hw->lock);
4755         ret = hns3_fc_enable(dev, fc_conf);
4756         rte_spinlock_unlock(&hw->lock);
4757
4758         return ret;
4759 }
4760
4761 static int
4762 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4763                             struct rte_eth_pfc_conf *pfc_conf)
4764 {
4765         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4766         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4767         uint8_t priority;
4768         int ret;
4769
4770         if (!hns3_dev_dcb_supported(hw)) {
4771                 hns3_err(hw, "This port does not support dcb configurations.");
4772                 return -EOPNOTSUPP;
4773         }
4774
4775         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4776             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4777                 hns3_err(hw, "Unsupported flow control settings specified, "
4778                          "high_water(%u), low_water(%u), send_xon(%u) and "
4779                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4780                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4781                          pfc_conf->fc.send_xon,
4782                          pfc_conf->fc.mac_ctrl_frame_fwd);
4783                 return -EINVAL;
4784         }
4785         if (pfc_conf->fc.autoneg) {
4786                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4787                 return -EINVAL;
4788         }
4789         if (pfc_conf->fc.pause_time == 0) {
4790                 hns3_err(hw, "Invalid pause time %d setting.",
4791                          pfc_conf->fc.pause_time);
4792                 return -EINVAL;
4793         }
4794
4795         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4796             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4797                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4798                              "current_fc_status = %d", hw->current_fc_status);
4799                 return -EOPNOTSUPP;
4800         }
4801
4802         priority = pfc_conf->priority;
4803         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4804         if (hw->dcb_info.pfc_en & BIT(priority) &&
4805             hw->requested_mode == hw->current_mode &&
4806             pfc_conf->fc.pause_time == pf->pause_time)
4807                 return 0;
4808
4809         rte_spinlock_lock(&hw->lock);
4810         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4811         rte_spinlock_unlock(&hw->lock);
4812
4813         return ret;
4814 }
4815
4816 static int
4817 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4818 {
4819         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4821         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4822         int i;
4823
4824         rte_spinlock_lock(&hw->lock);
4825         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4826                 dcb_info->nb_tcs = pf->local_max_tc;
4827         else
4828                 dcb_info->nb_tcs = 1;
4829
4830         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4831                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4832         for (i = 0; i < dcb_info->nb_tcs; i++)
4833                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4834
4835         for (i = 0; i < hw->num_tc; i++) {
4836                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4837                 dcb_info->tc_queue.tc_txq[0][i].base =
4838                                                 hw->tc_queue[i].tqp_offset;
4839                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4840                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4841                                                 hw->tc_queue[i].tqp_count;
4842         }
4843         rte_spinlock_unlock(&hw->lock);
4844
4845         return 0;
4846 }
4847
4848 static int
4849 hns3_reinit_dev(struct hns3_adapter *hns)
4850 {
4851         struct hns3_hw *hw = &hns->hw;
4852         int ret;
4853
4854         ret = hns3_cmd_init(hw);
4855         if (ret) {
4856                 hns3_err(hw, "Failed to init cmd: %d", ret);
4857                 return ret;
4858         }
4859
4860         ret = hns3_reset_all_queues(hns);
4861         if (ret) {
4862                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4863                 return ret;
4864         }
4865
4866         ret = hns3_init_hardware(hns);
4867         if (ret) {
4868                 hns3_err(hw, "Failed to init hardware: %d", ret);
4869                 return ret;
4870         }
4871
4872         ret = hns3_enable_hw_error_intr(hns, true);
4873         if (ret) {
4874                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4875                              ret);
4876                 return ret;
4877         }
4878         hns3_info(hw, "Reset done, driver initialization finished.");
4879
4880         return 0;
4881 }
4882
4883 static bool
4884 is_pf_reset_done(struct hns3_hw *hw)
4885 {
4886         uint32_t val, reg, reg_bit;
4887
4888         switch (hw->reset.level) {
4889         case HNS3_IMP_RESET:
4890                 reg = HNS3_GLOBAL_RESET_REG;
4891                 reg_bit = HNS3_IMP_RESET_BIT;
4892                 break;
4893         case HNS3_GLOBAL_RESET:
4894                 reg = HNS3_GLOBAL_RESET_REG;
4895                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4896                 break;
4897         case HNS3_FUNC_RESET:
4898                 reg = HNS3_FUN_RST_ING;
4899                 reg_bit = HNS3_FUN_RST_ING_B;
4900                 break;
4901         case HNS3_FLR_RESET:
4902         default:
4903                 hns3_err(hw, "Wait for unsupported reset level: %d",
4904                          hw->reset.level);
4905                 return true;
4906         }
4907         val = hns3_read_dev(hw, reg);
4908         if (hns3_get_bit(val, reg_bit))
4909                 return false;
4910         else
4911                 return true;
4912 }
4913
4914 bool
4915 hns3_is_reset_pending(struct hns3_adapter *hns)
4916 {
4917         struct hns3_hw *hw = &hns->hw;
4918         enum hns3_reset_level reset;
4919
4920         hns3_check_event_cause(hns, NULL);
4921         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4922         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4923                 hns3_warn(hw, "High level reset %d is pending", reset);
4924                 return true;
4925         }
4926         reset = hns3_get_reset_level(hns, &hw->reset.request);
4927         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4928                 hns3_warn(hw, "High level reset %d is request", reset);
4929                 return true;
4930         }
4931         return false;
4932 }
4933
4934 static int
4935 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4936 {
4937         struct hns3_hw *hw = &hns->hw;
4938         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4939         struct timeval tv;
4940
4941         if (wait_data->result == HNS3_WAIT_SUCCESS)
4942                 return 0;
4943         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4944                 gettimeofday(&tv, NULL);
4945                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4946                           tv.tv_sec, tv.tv_usec);
4947                 return -ETIME;
4948         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4949                 return -EAGAIN;
4950
4951         wait_data->hns = hns;
4952         wait_data->check_completion = is_pf_reset_done;
4953         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4954                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4955         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4956         wait_data->count = HNS3_RESET_WAIT_CNT;
4957         wait_data->result = HNS3_WAIT_REQUEST;
4958         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4959         return -EAGAIN;
4960 }
4961
4962 static int
4963 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4964 {
4965         struct hns3_cmd_desc desc;
4966         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4967
4968         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4969         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4970         req->fun_reset_vfid = func_id;
4971
4972         return hns3_cmd_send(hw, &desc, 1);
4973 }
4974
4975 static int
4976 hns3_imp_reset_cmd(struct hns3_hw *hw)
4977 {
4978         struct hns3_cmd_desc desc;
4979
4980         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4981         desc.data[0] = 0xeedd;
4982
4983         return hns3_cmd_send(hw, &desc, 1);
4984 }
4985
4986 static void
4987 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4988 {
4989         struct hns3_hw *hw = &hns->hw;
4990         struct timeval tv;
4991         uint32_t val;
4992
4993         gettimeofday(&tv, NULL);
4994         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4995             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4996                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4997                           tv.tv_sec, tv.tv_usec);
4998                 return;
4999         }
5000
5001         switch (reset_level) {
5002         case HNS3_IMP_RESET:
5003                 hns3_imp_reset_cmd(hw);
5004                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5005                           tv.tv_sec, tv.tv_usec);
5006                 break;
5007         case HNS3_GLOBAL_RESET:
5008                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5009                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5010                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5011                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5012                           tv.tv_sec, tv.tv_usec);
5013                 break;
5014         case HNS3_FUNC_RESET:
5015                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5016                           tv.tv_sec, tv.tv_usec);
5017                 /* schedule again to check later */
5018                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5019                 hns3_schedule_reset(hns);
5020                 break;
5021         default:
5022                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5023                 return;
5024         }
5025         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5026 }
5027
5028 static enum hns3_reset_level
5029 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5030 {
5031         struct hns3_hw *hw = &hns->hw;
5032         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5033
5034         /* Return the highest priority reset level amongst all */
5035         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5036                 reset_level = HNS3_IMP_RESET;
5037         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5038                 reset_level = HNS3_GLOBAL_RESET;
5039         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5040                 reset_level = HNS3_FUNC_RESET;
5041         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5042                 reset_level = HNS3_FLR_RESET;
5043
5044         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5045                 return HNS3_NONE_RESET;
5046
5047         return reset_level;
5048 }
5049
5050 static int
5051 hns3_prepare_reset(struct hns3_adapter *hns)
5052 {
5053         struct hns3_hw *hw = &hns->hw;
5054         uint32_t reg_val;
5055         int ret;
5056
5057         switch (hw->reset.level) {
5058         case HNS3_FUNC_RESET:
5059                 ret = hns3_func_reset_cmd(hw, 0);
5060                 if (ret)
5061                         return ret;
5062
5063                 /*
5064                  * After performaning pf reset, it is not necessary to do the
5065                  * mailbox handling or send any command to firmware, because
5066                  * any mailbox handling or command to firmware is only valid
5067                  * after hns3_cmd_init is called.
5068                  */
5069                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5070                 hw->reset.stats.request_cnt++;
5071                 break;
5072         case HNS3_IMP_RESET:
5073                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5074                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5075                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5076                 break;
5077         default:
5078                 break;
5079         }
5080         return 0;
5081 }
5082
5083 static int
5084 hns3_set_rst_done(struct hns3_hw *hw)
5085 {
5086         struct hns3_pf_rst_done_cmd *req;
5087         struct hns3_cmd_desc desc;
5088
5089         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5090         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5091         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5092         return hns3_cmd_send(hw, &desc, 1);
5093 }
5094
5095 static int
5096 hns3_stop_service(struct hns3_adapter *hns)
5097 {
5098         struct hns3_hw *hw = &hns->hw;
5099         struct rte_eth_dev *eth_dev;
5100
5101         eth_dev = &rte_eth_devices[hw->data->port_id];
5102         if (hw->adapter_state == HNS3_NIC_STARTED)
5103                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5104         hw->mac.link_status = ETH_LINK_DOWN;
5105
5106         hns3_set_rxtx_function(eth_dev);
5107         rte_wmb();
5108         /* Disable datapath on secondary process. */
5109         hns3_mp_req_stop_rxtx(eth_dev);
5110         rte_delay_ms(hw->tqps_num);
5111
5112         rte_spinlock_lock(&hw->lock);
5113         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5114             hw->adapter_state == HNS3_NIC_STOPPING) {
5115                 hns3_do_stop(hns);
5116                 hw->reset.mbuf_deferred_free = true;
5117         } else
5118                 hw->reset.mbuf_deferred_free = false;
5119
5120         /*
5121          * It is cumbersome for hardware to pick-and-choose entries for deletion
5122          * from table space. Hence, for function reset software intervention is
5123          * required to delete the entries
5124          */
5125         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5126                 hns3_configure_all_mc_mac_addr(hns, true);
5127         rte_spinlock_unlock(&hw->lock);
5128
5129         return 0;
5130 }
5131
5132 static int
5133 hns3_start_service(struct hns3_adapter *hns)
5134 {
5135         struct hns3_hw *hw = &hns->hw;
5136         struct rte_eth_dev *eth_dev;
5137
5138         if (hw->reset.level == HNS3_IMP_RESET ||
5139             hw->reset.level == HNS3_GLOBAL_RESET)
5140                 hns3_set_rst_done(hw);
5141         eth_dev = &rte_eth_devices[hw->data->port_id];
5142         hns3_set_rxtx_function(eth_dev);
5143         hns3_mp_req_start_rxtx(eth_dev);
5144         if (hw->adapter_state == HNS3_NIC_STARTED) {
5145                 hns3_service_handler(eth_dev);
5146
5147                 /* Enable interrupt of all rx queues before enabling queues */
5148                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5149                 /*
5150                  * When finished the initialization, enable queues to receive
5151                  * and transmit packets.
5152                  */
5153                 hns3_enable_all_queues(hw, true);
5154         }
5155
5156         return 0;
5157 }
5158
5159 static int
5160 hns3_restore_conf(struct hns3_adapter *hns)
5161 {
5162         struct hns3_hw *hw = &hns->hw;
5163         int ret;
5164
5165         ret = hns3_configure_all_mac_addr(hns, false);
5166         if (ret)
5167                 return ret;
5168
5169         ret = hns3_configure_all_mc_mac_addr(hns, false);
5170         if (ret)
5171                 goto err_mc_mac;
5172
5173         ret = hns3_dev_promisc_restore(hns);
5174         if (ret)
5175                 goto err_promisc;
5176
5177         ret = hns3_restore_vlan_table(hns);
5178         if (ret)
5179                 goto err_promisc;
5180
5181         ret = hns3_restore_vlan_conf(hns);
5182         if (ret)
5183                 goto err_promisc;
5184
5185         ret = hns3_restore_all_fdir_filter(hns);
5186         if (ret)
5187                 goto err_promisc;
5188
5189         ret = hns3_restore_rx_interrupt(hw);
5190         if (ret)
5191                 goto err_promisc;
5192
5193         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5194                 ret = hns3_do_start(hns, false);
5195                 if (ret)
5196                         goto err_promisc;
5197                 hns3_info(hw, "hns3 dev restart successful!");
5198         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5199                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5200         return 0;
5201
5202 err_promisc:
5203         hns3_configure_all_mc_mac_addr(hns, true);
5204 err_mc_mac:
5205         hns3_configure_all_mac_addr(hns, true);
5206         return ret;
5207 }
5208
5209 static void
5210 hns3_reset_service(void *param)
5211 {
5212         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5213         struct hns3_hw *hw = &hns->hw;
5214         enum hns3_reset_level reset_level;
5215         struct timeval tv_delta;
5216         struct timeval tv_start;
5217         struct timeval tv;
5218         uint64_t msec;
5219         int ret;
5220
5221         /*
5222          * The interrupt is not triggered within the delay time.
5223          * The interrupt may have been lost. It is necessary to handle
5224          * the interrupt to recover from the error.
5225          */
5226         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5227                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5228                 hns3_err(hw, "Handling interrupts in delayed tasks");
5229                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5230                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5231                 if (reset_level == HNS3_NONE_RESET) {
5232                         hns3_err(hw, "No reset level is set, try IMP reset");
5233                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5234                 }
5235         }
5236         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5237
5238         /*
5239          * Check if there is any ongoing reset in the hardware. This status can
5240          * be checked from reset_pending. If there is then, we need to wait for
5241          * hardware to complete reset.
5242          *    a. If we are able to figure out in reasonable time that hardware
5243          *       has fully resetted then, we can proceed with driver, client
5244          *       reset.
5245          *    b. else, we can come back later to check this status so re-sched
5246          *       now.
5247          */
5248         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5249         if (reset_level != HNS3_NONE_RESET) {
5250                 gettimeofday(&tv_start, NULL);
5251                 ret = hns3_reset_process(hns, reset_level);
5252                 gettimeofday(&tv, NULL);
5253                 timersub(&tv, &tv_start, &tv_delta);
5254                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5255                        tv_delta.tv_usec / USEC_PER_MSEC;
5256                 if (msec > HNS3_RESET_PROCESS_MS)
5257                         hns3_err(hw, "%d handle long time delta %" PRIx64
5258                                      " ms time=%ld.%.6ld",
5259                                  hw->reset.level, msec,
5260                                  tv.tv_sec, tv.tv_usec);
5261                 if (ret == -EAGAIN)
5262                         return;
5263         }
5264
5265         /* Check if we got any *new* reset requests to be honored */
5266         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5267         if (reset_level != HNS3_NONE_RESET)
5268                 hns3_msix_process(hns, reset_level);
5269 }
5270
5271 static const struct eth_dev_ops hns3_eth_dev_ops = {
5272         .dev_start          = hns3_dev_start,
5273         .dev_stop           = hns3_dev_stop,
5274         .dev_close          = hns3_dev_close,
5275         .promiscuous_enable = hns3_dev_promiscuous_enable,
5276         .promiscuous_disable = hns3_dev_promiscuous_disable,
5277         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5278         .allmulticast_disable = hns3_dev_allmulticast_disable,
5279         .mtu_set            = hns3_dev_mtu_set,
5280         .stats_get          = hns3_stats_get,
5281         .stats_reset        = hns3_stats_reset,
5282         .xstats_get         = hns3_dev_xstats_get,
5283         .xstats_get_names   = hns3_dev_xstats_get_names,
5284         .xstats_reset       = hns3_dev_xstats_reset,
5285         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5286         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5287         .dev_infos_get          = hns3_dev_infos_get,
5288         .fw_version_get         = hns3_fw_version_get,
5289         .rx_queue_setup         = hns3_rx_queue_setup,
5290         .tx_queue_setup         = hns3_tx_queue_setup,
5291         .rx_queue_release       = hns3_dev_rx_queue_release,
5292         .tx_queue_release       = hns3_dev_tx_queue_release,
5293         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5294         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5295         .dev_configure          = hns3_dev_configure,
5296         .flow_ctrl_get          = hns3_flow_ctrl_get,
5297         .flow_ctrl_set          = hns3_flow_ctrl_set,
5298         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5299         .mac_addr_add           = hns3_add_mac_addr,
5300         .mac_addr_remove        = hns3_remove_mac_addr,
5301         .mac_addr_set           = hns3_set_default_mac_addr,
5302         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5303         .link_update            = hns3_dev_link_update,
5304         .rss_hash_update        = hns3_dev_rss_hash_update,
5305         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5306         .reta_update            = hns3_dev_rss_reta_update,
5307         .reta_query             = hns3_dev_rss_reta_query,
5308         .filter_ctrl            = hns3_dev_filter_ctrl,
5309         .vlan_filter_set        = hns3_vlan_filter_set,
5310         .vlan_tpid_set          = hns3_vlan_tpid_set,
5311         .vlan_offload_set       = hns3_vlan_offload_set,
5312         .vlan_pvid_set          = hns3_vlan_pvid_set,
5313         .get_reg                = hns3_get_regs,
5314         .get_dcb_info           = hns3_get_dcb_info,
5315         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5316 };
5317
5318 static const struct hns3_reset_ops hns3_reset_ops = {
5319         .reset_service       = hns3_reset_service,
5320         .stop_service        = hns3_stop_service,
5321         .prepare_reset       = hns3_prepare_reset,
5322         .wait_hardware_ready = hns3_wait_hardware_ready,
5323         .reinit_dev          = hns3_reinit_dev,
5324         .restore_conf        = hns3_restore_conf,
5325         .start_service       = hns3_start_service,
5326 };
5327
5328 static int
5329 hns3_dev_init(struct rte_eth_dev *eth_dev)
5330 {
5331         struct rte_device *dev = eth_dev->device;
5332         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5333         struct hns3_adapter *hns = eth_dev->data->dev_private;
5334         struct hns3_hw *hw = &hns->hw;
5335         uint16_t device_id = pci_dev->id.device_id;
5336         uint8_t revision;
5337         int ret;
5338
5339         PMD_INIT_FUNC_TRACE();
5340
5341         /* Get PCI revision id */
5342         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5343                                   HNS3_PCI_REVISION_ID);
5344         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5345                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5346                              ret);
5347                 return -EIO;
5348         }
5349         hw->revision = revision;
5350
5351         eth_dev->process_private = (struct hns3_process_private *)
5352             rte_zmalloc_socket("hns3_filter_list",
5353                                sizeof(struct hns3_process_private),
5354                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5355         if (eth_dev->process_private == NULL) {
5356                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5357                 return -ENOMEM;
5358         }
5359         /* initialize flow filter lists */
5360         hns3_filterlist_init(eth_dev);
5361
5362         hns3_set_rxtx_function(eth_dev);
5363         eth_dev->dev_ops = &hns3_eth_dev_ops;
5364         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5365                 hns3_mp_init_secondary();
5366                 hw->secondary_cnt++;
5367                 return 0;
5368         }
5369
5370         hns3_mp_init_primary();
5371         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5372
5373         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5374             device_id == HNS3_DEV_ID_50GE_RDMA ||
5375             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5376                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5377
5378         hns->is_vf = false;
5379         hw->data = eth_dev->data;
5380
5381         /*
5382          * Set default max packet size according to the mtu
5383          * default vale in DPDK frame.
5384          */
5385         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5386
5387         ret = hns3_reset_init(hw);
5388         if (ret)
5389                 goto err_init_reset;
5390         hw->reset.ops = &hns3_reset_ops;
5391
5392         ret = hns3_init_pf(eth_dev);
5393         if (ret) {
5394                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5395                 goto err_init_pf;
5396         }
5397
5398         /* Allocate memory for storing MAC addresses */
5399         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5400                                                sizeof(struct rte_ether_addr) *
5401                                                HNS3_UC_MACADDR_NUM, 0);
5402         if (eth_dev->data->mac_addrs == NULL) {
5403                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5404                              "to store MAC addresses",
5405                              sizeof(struct rte_ether_addr) *
5406                              HNS3_UC_MACADDR_NUM);
5407                 ret = -ENOMEM;
5408                 goto err_rte_zmalloc;
5409         }
5410
5411         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5412                             &eth_dev->data->mac_addrs[0]);
5413
5414         hw->adapter_state = HNS3_NIC_INITIALIZED;
5415         /*
5416          * Pass the information to the rte_eth_dev_close() that it should also
5417          * release the private port resources.
5418          */
5419         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5420
5421         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5422                 hns3_err(hw, "Reschedule reset service after dev_init");
5423                 hns3_schedule_reset(hns);
5424         } else {
5425                 /* IMP will wait ready flag before reset */
5426                 hns3_notify_reset_ready(hw, false);
5427         }
5428
5429         hns3_info(hw, "hns3 dev initialization successful!");
5430         return 0;
5431
5432 err_rte_zmalloc:
5433         hns3_uninit_pf(eth_dev);
5434
5435 err_init_pf:
5436         rte_free(hw->reset.wait_data);
5437 err_init_reset:
5438         eth_dev->dev_ops = NULL;
5439         eth_dev->rx_pkt_burst = NULL;
5440         eth_dev->tx_pkt_burst = NULL;
5441         eth_dev->tx_pkt_prepare = NULL;
5442         rte_free(eth_dev->process_private);
5443         eth_dev->process_private = NULL;
5444         return ret;
5445 }
5446
5447 static int
5448 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5449 {
5450         struct hns3_adapter *hns = eth_dev->data->dev_private;
5451         struct hns3_hw *hw = &hns->hw;
5452
5453         PMD_INIT_FUNC_TRACE();
5454
5455         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5456                 return -EPERM;
5457
5458         eth_dev->dev_ops = NULL;
5459         eth_dev->rx_pkt_burst = NULL;
5460         eth_dev->tx_pkt_burst = NULL;
5461         eth_dev->tx_pkt_prepare = NULL;
5462         if (hw->adapter_state < HNS3_NIC_CLOSING)
5463                 hns3_dev_close(eth_dev);
5464
5465         hw->adapter_state = HNS3_NIC_REMOVED;
5466         return 0;
5467 }
5468
5469 static int
5470 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5471                    struct rte_pci_device *pci_dev)
5472 {
5473         return rte_eth_dev_pci_generic_probe(pci_dev,
5474                                              sizeof(struct hns3_adapter),
5475                                              hns3_dev_init);
5476 }
5477
5478 static int
5479 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5480 {
5481         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5482 }
5483
5484 static const struct rte_pci_id pci_id_hns3_map[] = {
5485         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5486         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5487         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5488         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5489         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5490         { .vendor_id = 0, /* sentinel */ },
5491 };
5492
5493 static struct rte_pci_driver rte_hns3_pmd = {
5494         .id_table = pci_id_hns3_map,
5495         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5496         .probe = eth_hns3_pci_probe,
5497         .remove = eth_hns3_pci_remove,
5498 };
5499
5500 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5501 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5502 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5503
5504 RTE_INIT(hns3_init_log)
5505 {
5506         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5507         if (hns3_logtype_init >= 0)
5508                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5509         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5510         if (hns3_logtype_driver >= 0)
5511                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5512 }