drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105
 106 void hns3_ether_format_addr(char *buf, uint16_t size,
 107                             const struct rte_ether_addr *ether_addr)
 108 {
 109         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 110                 ether_addr->addr_bytes[0],
 111                 ether_addr->addr_bytes[4],
 112                 ether_addr->addr_bytes[5]);
 113 }
 114
 115 static void
 116 hns3_pf_disable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 119 }
 120
 121 static void
 122 hns3_pf_enable_irq0(struct hns3_hw *hw)
 123 {
 124         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 125 }
 126
 127 static enum hns3_evt_cause
 128 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 129                           uint32_t *vec_val)
 130 {
 131         struct hns3_hw *hw = &hns->hw;
 132
 133         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 134         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 135         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 136         if (!is_delay) {
 137                 hw->reset.stats.imp_cnt++;
 138                 hns3_warn(hw, "IMP reset detected, clear reset status");
 139         } else {
 140                 hns3_schedule_delayed_reset(hns);
 141                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 142         }
 143
 144         return HNS3_VECTOR0_EVENT_RST;
 145 }
 146
 147 static enum hns3_evt_cause
 148 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 149                              uint32_t *vec_val)
 150 {
 151         struct hns3_hw *hw = &hns->hw;
 152
 153         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 154         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 155         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 156         if (!is_delay) {
 157                 hw->reset.stats.global_cnt++;
 158                 hns3_warn(hw, "Global reset detected, clear reset status");
 159         } else {
 160                 hns3_schedule_delayed_reset(hns);
 161                 hns3_warn(hw,
 162                           "Global reset detected, don't clear reset status");
 163         }
 164
 165         return HNS3_VECTOR0_EVENT_RST;
 166 }
 167
 168 static enum hns3_evt_cause
 169 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 170 {
 171         struct hns3_hw *hw = &hns->hw;
 172         uint32_t vector0_int_stats;
 173         uint32_t cmdq_src_val;
 174         uint32_t hw_err_src_reg;
 175         uint32_t val;
 176         enum hns3_evt_cause ret;
 177         bool is_delay;
 178
 179         /* fetch the events from their corresponding regs */
 180         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 181         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 182         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 183
 184         is_delay = clearval == NULL ? true : false;
 185         /*
 186          * Assumption: If by any chance reset and mailbox events are reported
 187          * together then we will only process reset event and defer the
 188          * processing of the mailbox events. Since, we would have not cleared
 189          * RX CMDQ event this time we would receive again another interrupt
 190          * from H/W just for the mailbox.
 191          */
 192         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 193                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Global reset */
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 199                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 200                 goto out;
 201         }
 202
 203         /* check for vector0 msix event source */
 204         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 205             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 206                 val = vector0_int_stats | hw_err_src_reg;
 207                 ret = HNS3_VECTOR0_EVENT_ERR;
 208                 goto out;
 209         }
 210
 211         /* check for vector0 mailbox(=CMDQ RX) event source */
 212         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 213                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 214                 val = cmdq_src_val;
 215                 ret = HNS3_VECTOR0_EVENT_MBX;
 216                 goto out;
 217         }
 218
 219         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 220                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 221                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 222         val = vector0_int_stats;
 223         ret = HNS3_VECTOR0_EVENT_OTHER;
 224 out:
 225
 226         if (clearval)
 227                 *clearval = val;
 228         return ret;
 229 }
 230
 231 static void
 232 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 233 {
 234         if (event_type == HNS3_VECTOR0_EVENT_RST)
 235                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 236         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 237                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 238 }
 239
 240 static void
 241 hns3_clear_all_event_cause(struct hns3_hw *hw)
 242 {
 243         uint32_t vector0_int_stats;
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245
 246         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 247                 hns3_warn(hw, "Probe during IMP reset interrupt");
 248
 249         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 250                 hns3_warn(hw, "Probe during Global reset interrupt");
 251
 252         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 253                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 255                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 257 }
 258
 259 static void
 260 hns3_interrupt_handler(void *param)
 261 {
 262         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 263         struct hns3_adapter *hns = dev->data->dev_private;
 264         struct hns3_hw *hw = &hns->hw;
 265         enum hns3_evt_cause event_cause;
 266         uint32_t clearval = 0;
 267
 268         /* Disable interrupt */
 269         hns3_pf_disable_irq0(hw);
 270
 271         event_cause = hns3_check_event_cause(hns, &clearval);
 272         /* vector 0 interrupt is shared with reset and mailbox source events. */
 273         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 274                 hns3_warn(hw, "Received err interrupt");
 275                 hns3_handle_msix_error(hns, &hw->reset.request);
 276                 hns3_handle_ras_error(hns, &hw->reset.request);
 277                 hns3_schedule_reset(hns);
 278         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 279                 hns3_warn(hw, "Received reset interrupt");
 280                 hns3_schedule_reset(hns);
 281         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 282                 hns3_dev_handle_mbx_msg(hw);
 283         else
 284                 hns3_err(hw, "Received unknown event");
 285
 286         hns3_clear_event_cause(hw, event_cause, clearval);
 287         /* Enable interrupt if it is not cause by reset */
 288         hns3_pf_enable_irq0(hw);
 289 }
 290
 291 static int
 292 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 293 {
 294 #define HNS3_VLAN_ID_OFFSET_STEP        160
 295 #define HNS3_VLAN_BYTE_SIZE             8
 296         struct hns3_vlan_filter_pf_cfg_cmd *req;
 297         struct hns3_hw *hw = &hns->hw;
 298         uint8_t vlan_offset_byte_val;
 299         struct hns3_cmd_desc desc;
 300         uint8_t vlan_offset_byte;
 301         uint8_t vlan_offset_base;
 302         int ret;
 303
 304         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 305
 306         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 307         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 308                            HNS3_VLAN_BYTE_SIZE;
 309         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 310
 311         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 312         req->vlan_offset = vlan_offset_base;
 313         req->vlan_cfg = on ? 0 : 1;
 314         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 315
 316         ret = hns3_cmd_send(hw, &desc, 1);
 317         if (ret)
 318                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 319                          vlan_id, ret);
 320
 321         return ret;
 322 }
 323
 324 static void
 325 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 326 {
 327         struct hns3_user_vlan_table *vlan_entry;
 328         struct hns3_pf *pf = &hns->pf;
 329
 330         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 331                 if (vlan_entry->vlan_id == vlan_id) {
 332                         if (vlan_entry->hd_tbl_status)
 333                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 334                         LIST_REMOVE(vlan_entry, next);
 335                         rte_free(vlan_entry);
 336                         break;
 337                 }
 338         }
 339 }
 340
 341 static void
 342 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 343                         bool writen_to_tbl)
 344 {
 345         struct hns3_user_vlan_table *vlan_entry;
 346         struct hns3_hw *hw = &hns->hw;
 347         struct hns3_pf *pf = &hns->pf;
 348
 349         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 350                 if (vlan_entry->vlan_id == vlan_id)
 351                         return;
 352         }
 353
 354         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 355         if (vlan_entry == NULL) {
 356                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 357                 return;
 358         }
 359
 360         vlan_entry->hd_tbl_status = writen_to_tbl;
 361         vlan_entry->vlan_id = vlan_id;
 362
 363         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 364 }
 365
 366 static int
 367 hns3_restore_vlan_table(struct hns3_adapter *hns)
 368 {
 369         struct hns3_user_vlan_table *vlan_entry;
 370         struct hns3_hw *hw = &hns->hw;
 371         struct hns3_pf *pf = &hns->pf;
 372         uint16_t vlan_id;
 373         int ret = 0;
 374
 375         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 376                 return hns3_vlan_pvid_configure(hns,
 377                                                 hw->port_base_vlan_cfg.pvid, 1);
 378
 379         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 380                 if (vlan_entry->hd_tbl_status) {
 381                         vlan_id = vlan_entry->vlan_id;
 382                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 383                         if (ret)
 384                                 break;
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int
 392 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 393 {
 394         struct hns3_hw *hw = &hns->hw;
 395         bool writen_to_tbl = false;
 396         int ret = 0;
 397
 398         /*
 399          * When vlan filter is enabled, hardware regards packets without vlan
 400          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 401          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 402          */
 403         if (on == 0 && vlan_id == 0)
 404                 return 0;
 405
 406         /*
 407          * When port base vlan enabled, we use port base vlan as the vlan
 408          * filter condition. In this case, we don't update vlan filter table
 409          * when user add new vlan or remove exist vlan, just update the
 410          * vlan list. The vlan id in vlan list will be writen in vlan filter
 411          * table until port base vlan disabled
 412          */
 413         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 414                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 415                 writen_to_tbl = true;
 416         }
 417
 418         if (ret == 0) {
 419                 if (on)
 420                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 421                 else
 422                         hns3_rm_dev_vlan_table(hns, vlan_id);
 423         }
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 429 {
 430         struct hns3_adapter *hns = dev->data->dev_private;
 431         struct hns3_hw *hw = &hns->hw;
 432         int ret;
 433
 434         rte_spinlock_lock(&hw->lock);
 435         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 436         rte_spinlock_unlock(&hw->lock);
 437         return ret;
 438 }
 439
 440 static int
 441 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 442                          uint16_t tpid)
 443 {
 444         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 445         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 446         struct hns3_hw *hw = &hns->hw;
 447         struct hns3_cmd_desc desc;
 448         int ret;
 449
 450         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 451              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 452                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 453                 return -EINVAL;
 454         }
 455
 456         if (tpid != RTE_ETHER_TYPE_VLAN) {
 457                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 458                 return -EINVAL;
 459         }
 460
 461         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 462         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 463
 464         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 465                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 466                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 467         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 468                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 471                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 472         }
 473
 474         ret = hns3_cmd_send(hw, &desc, 1);
 475         if (ret) {
 476                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 477                          ret);
 478                 return ret;
 479         }
 480
 481         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 482
 483         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 484         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 485         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 486
 487         ret = hns3_cmd_send(hw, &desc, 1);
 488         if (ret)
 489                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 490                          ret);
 491         return ret;
 492 }
 493
 494 static int
 495 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 496                    uint16_t tpid)
 497 {
 498         struct hns3_adapter *hns = dev->data->dev_private;
 499         struct hns3_hw *hw = &hns->hw;
 500         int ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 504         rte_spinlock_unlock(&hw->lock);
 505         return ret;
 506 }
 507
 508 static int
 509 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 510                              struct hns3_rx_vtag_cfg *vcfg)
 511 {
 512         struct hns3_vport_vtag_rx_cfg_cmd *req;
 513         struct hns3_hw *hw = &hns->hw;
 514         struct hns3_cmd_desc desc;
 515         uint16_t vport_id;
 516         uint8_t bitmap;
 517         int ret;
 518
 519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 520
 521         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 523                      vcfg->strip_tag1_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 525                      vcfg->strip_tag2_en ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 527                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 528         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 529                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 530
 531         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 533                      vcfg->strip_tag1_discard_en ? 1 : 0);
 534         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 535                      vcfg->strip_tag2_discard_en ? 1 : 0);
 536         /*
 537          * In current version VF is not supported when PF is driven by DPDK
 538          * driver, just need to configure parameters for PF vport.
 539          */
 540         vport_id = HNS3_PF_FUNC_ID;
 541         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 542         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 543         req->vf_bitmap[req->vf_offset] = bitmap;
 544
 545         ret = hns3_cmd_send(hw, &desc, 1);
 546         if (ret)
 547                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 548         return ret;
 549 }
 550
 551 static void
 552 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 553                            struct hns3_rx_vtag_cfg *vcfg)
 554 {
 555         struct hns3_pf *pf = &hns->pf;
 556         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 557 }
 558
 559 static void
 560 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 561                            struct hns3_tx_vtag_cfg *vcfg)
 562 {
 563         struct hns3_pf *pf = &hns->pf;
 564         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 565 }
 566
 567 static int
 568 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 569 {
 570         struct hns3_rx_vtag_cfg rxvlan_cfg;
 571         struct hns3_hw *hw = &hns->hw;
 572         int ret;
 573
 574         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 575                 rxvlan_cfg.strip_tag1_en = false;
 576                 rxvlan_cfg.strip_tag2_en = enable;
 577                 rxvlan_cfg.strip_tag2_discard_en = false;
 578         } else {
 579                 rxvlan_cfg.strip_tag1_en = enable;
 580                 rxvlan_cfg.strip_tag2_en = true;
 581                 rxvlan_cfg.strip_tag2_discard_en = true;
 582         }
 583
 584         rxvlan_cfg.strip_tag1_discard_en = false;
 585         rxvlan_cfg.vlan1_vlan_prionly = false;
 586         rxvlan_cfg.vlan2_vlan_prionly = false;
 587         rxvlan_cfg.rx_vlan_offload_en = enable;
 588
 589         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 590         if (ret) {
 591                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 592                 return ret;
 593         }
 594
 595         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 602                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 603 {
 604         struct hns3_vlan_filter_ctrl_cmd *req;
 605         struct hns3_cmd_desc desc;
 606         int ret;
 607
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 609
 610         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 611         req->vlan_type = vlan_type;
 612         req->vlan_fe = filter_en ? fe_type : 0;
 613         req->vf_id = vf_id;
 614
 615         ret = hns3_cmd_send(hw, &desc, 1);
 616         if (ret)
 617                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3_vlan_filter_init(struct hns3_adapter *hns)
 624 {
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 629                                         HNS3_FILTER_FE_EGRESS, false,
 630                                         HNS3_PF_FUNC_ID);
 631         if (ret) {
 632                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 633                 return ret;
 634         }
 635
 636         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 637                                         HNS3_FILTER_FE_INGRESS, false,
 638                                         HNS3_PF_FUNC_ID);
 639         if (ret)
 640                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 647 {
 648         struct hns3_hw *hw = &hns->hw;
 649         int ret;
 650
 651         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 652                                         HNS3_FILTER_FE_INGRESS, enable,
 653                                         HNS3_PF_FUNC_ID);
 654         if (ret)
 655                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 656                          enable ? "enable" : "disable", ret);
 657
 658         return ret;
 659 }
 660
 661 static int
 662 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 663 {
 664         struct hns3_adapter *hns = dev->data->dev_private;
 665         struct hns3_hw *hw = &hns->hw;
 666         struct rte_eth_rxmode *rxmode;
 667         unsigned int tmp_mask;
 668         bool enable;
 669         int ret = 0;
 670
 671         rte_spinlock_lock(&hw->lock);
 672         rxmode = &dev->data->dev_conf.rxmode;
 673         tmp_mask = (unsigned int)mask;
 674         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 675                 /* ignore vlan filter configuration during promiscuous mode */
 676                 if (!dev->data->promiscuous) {
 677                         /* Enable or disable VLAN filter */
 678                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 679                                  true : false;
 680
 681                         ret = hns3_enable_vlan_filter(hns, enable);
 682                         if (ret) {
 683                                 rte_spinlock_unlock(&hw->lock);
 684                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 685                                          enable ? "enable" : "disable", ret);
 686                                 return ret;
 687                         }
 688                 }
 689         }
 690
 691         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 692                 /* Enable or disable VLAN stripping */
 693                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 694                     true : false;
 695
 696                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 697                 if (ret) {
 698                         rte_spinlock_unlock(&hw->lock);
 699                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 700                                  enable ? "enable" : "disable", ret);
 701                         return ret;
 702                 }
 703         }
 704
 705         rte_spinlock_unlock(&hw->lock);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 712                              struct hns3_tx_vtag_cfg *vcfg)
 713 {
 714         struct hns3_vport_vtag_tx_cfg_cmd *req;
 715         struct hns3_cmd_desc desc;
 716         struct hns3_hw *hw = &hns->hw;
 717         uint16_t vport_id;
 718         uint8_t bitmap;
 719         int ret;
 720
 721         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 722
 723         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 724         req->def_vlan_tag1 = vcfg->default_tag1;
 725         req->def_vlan_tag2 = vcfg->default_tag2;
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 727                      vcfg->accept_tag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 729                      vcfg->accept_untag1 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 731                      vcfg->accept_tag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 733                      vcfg->accept_untag2 ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 735                      vcfg->insert_tag1_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 737                      vcfg->insert_tag2_en ? 1 : 0);
 738         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 739
 740         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 741         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 742                      vcfg->tag_shift_mode_en ? 1 : 0);
 743
 744         /*
 745          * In current version VF is not supported when PF is driven by DPDK
 746          * driver, just need to configure parameters for PF vport.
 747          */
 748         vport_id = HNS3_PF_FUNC_ID;
 749         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 750         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 751         req->vf_bitmap[req->vf_offset] = bitmap;
 752
 753         ret = hns3_cmd_send(hw, &desc, 1);
 754         if (ret)
 755                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 756
 757         return ret;
 758 }
 759
 760 static int
 761 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 762                      uint16_t pvid)
 763 {
 764         struct hns3_hw *hw = &hns->hw;
 765         struct hns3_tx_vtag_cfg txvlan_cfg;
 766         int ret;
 767
 768         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 769                 txvlan_cfg.accept_tag1 = true;
 770                 txvlan_cfg.insert_tag1_en = false;
 771                 txvlan_cfg.default_tag1 = 0;
 772         } else {
 773                 txvlan_cfg.accept_tag1 =
 774                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 775                 txvlan_cfg.insert_tag1_en = true;
 776                 txvlan_cfg.default_tag1 = pvid;
 777         }
 778
 779         txvlan_cfg.accept_untag1 = true;
 780         txvlan_cfg.accept_tag2 = true;
 781         txvlan_cfg.accept_untag2 = true;
 782         txvlan_cfg.insert_tag2_en = false;
 783         txvlan_cfg.default_tag2 = 0;
 784         txvlan_cfg.tag_shift_mode_en = true;
 785
 786         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 787         if (ret) {
 788                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 789                          ret);
 790                 return ret;
 791         }
 792
 793         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 794         return ret;
 795 }
 796
 797
 798 static void
 799 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 800 {
 801         struct hns3_user_vlan_table *vlan_entry;
 802         struct hns3_pf *pf = &hns->pf;
 803
 804         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 805                 if (vlan_entry->hd_tbl_status) {
 806                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 807                         vlan_entry->hd_tbl_status = false;
 808                 }
 809         }
 810
 811         if (is_del_list) {
 812                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 813                 while (vlan_entry) {
 814                         LIST_REMOVE(vlan_entry, next);
 815                         rte_free(vlan_entry);
 816                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 817                 }
 818         }
 819 }
 820
 821 static void
 822 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 823 {
 824         struct hns3_user_vlan_table *vlan_entry;
 825         struct hns3_pf *pf = &hns->pf;
 826
 827         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 828                 if (!vlan_entry->hd_tbl_status) {
 829                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 830                         vlan_entry->hd_tbl_status = true;
 831                 }
 832         }
 833 }
 834
 835 static void
 836 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 837 {
 838         struct hns3_hw *hw = &hns->hw;
 839         int ret;
 840
 841         hns3_rm_all_vlan_table(hns, true);
 842         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 843                 ret = hns3_set_port_vlan_filter(hns,
 844                                                 hw->port_base_vlan_cfg.pvid, 0);
 845                 if (ret) {
 846                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 847                                  ret);
 848                         return;
 849                 }
 850         }
 851 }
 852
 853 static int
 854 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 855                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 856 {
 857         struct hns3_hw *hw = &hns->hw;
 858         uint16_t old_pvid;
 859         int ret;
 860
 861         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 862                 old_pvid = hw->port_base_vlan_cfg.pvid;
 863                 if (old_pvid != HNS3_INVALID_PVID) {
 864                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 865                         if (ret) {
 866                                 hns3_err(hw, "failed to remove old pvid %u, "
 867                                                 "ret = %d", old_pvid, ret);
 868                                 return ret;
 869                         }
 870                 }
 871
 872                 hns3_rm_all_vlan_table(hns, false);
 873                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 874                 if (ret) {
 875                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 876                                         new_pvid, ret);
 877                         return ret;
 878                 }
 879         } else {
 880                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 881                 if (ret) {
 882                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 883                                         new_pvid, ret);
 884                         return ret;
 885                 }
 886
 887                 hns3_add_all_vlan_table(hns);
 888         }
 889         return 0;
 890 }
 891
 892 static int
 893 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 894 {
 895         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 896         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 897         bool rx_strip_en;
 898         int ret;
 899
 900         rx_strip_en = old_cfg->rx_vlan_offload_en;
 901         if (on) {
 902                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 903                 rx_vlan_cfg.strip_tag2_en = true;
 904                 rx_vlan_cfg.strip_tag2_discard_en = true;
 905         } else {
 906                 rx_vlan_cfg.strip_tag1_en = false;
 907                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 908                 rx_vlan_cfg.strip_tag2_discard_en = false;
 909         }
 910         rx_vlan_cfg.strip_tag1_discard_en = false;
 911         rx_vlan_cfg.vlan1_vlan_prionly = false;
 912         rx_vlan_cfg.vlan2_vlan_prionly = false;
 913         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 914
 915         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 916         if (ret)
 917                 return ret;
 918
 919         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 920         return ret;
 921 }
 922
 923 static int
 924 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 925 {
 926         struct hns3_hw *hw = &hns->hw;
 927         uint16_t port_base_vlan_state;
 928         int ret;
 929
 930         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 931                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 932                         hns3_warn(hw, "Invalid operation! As current pvid set "
 933                                   "is %u, disable pvid %u is invalid",
 934                                   hw->port_base_vlan_cfg.pvid, pvid);
 935                 return 0;
 936         }
 937
 938         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 939                                     HNS3_PORT_BASE_VLAN_DISABLE;
 940         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 941         if (ret) {
 942                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 943                          ret);
 944                 return ret;
 945         }
 946
 947         ret = hns3_en_pvid_strip(hns, on);
 948         if (ret) {
 949                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 950                          "ret = %d", ret);
 951                 return ret;
 952         }
 953
 954         if (pvid == HNS3_INVALID_PVID)
 955                 goto out;
 956         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 957         if (ret) {
 958                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 959                          ret);
 960                 return ret;
 961         }
 962
 963 out:
 964         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 965         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 966         return ret;
 967 }
 968
 969 static int
 970 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 971 {
 972         struct hns3_adapter *hns = dev->data->dev_private;
 973         struct hns3_hw *hw = &hns->hw;
 974         bool pvid_en_state_change;
 975         uint16_t pvid_state;
 976         int ret;
 977
 978         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 979                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 980                          RTE_ETHER_MAX_VLAN_ID);
 981                 return -EINVAL;
 982         }
 983
 984         /*
 985          * If PVID configuration state change, should refresh the PVID
 986          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 987          */
 988         pvid_state = hw->port_base_vlan_cfg.state;
 989         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 990             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 991                 pvid_en_state_change = false;
 992         else
 993                 pvid_en_state_change = true;
 994
 995         rte_spinlock_lock(&hw->lock);
 996         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 997         rte_spinlock_unlock(&hw->lock);
 998         if (ret)
 999                 return ret;
1000         /*
1001          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1002          * need be processed by PMD driver.
1003          */
1004         if (pvid_en_state_change &&
1005             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1006                 hns3_update_all_queues_pvid_proc_en(hw);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 hns3_default_vlan_config(struct hns3_adapter *hns)
1013 {
1014         struct hns3_hw *hw = &hns->hw;
1015         int ret;
1016
1017         /*
1018          * When vlan filter is enabled, hardware regards packets without vlan
1019          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1020          * table, packets without vlan won't be received. So, add vlan 0 as
1021          * the default vlan.
1022          */
1023         ret = hns3_vlan_filter_configure(hns, 0, 1);
1024         if (ret)
1025                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1026         return ret;
1027 }
1028
1029 static int
1030 hns3_init_vlan_config(struct hns3_adapter *hns)
1031 {
1032         struct hns3_hw *hw = &hns->hw;
1033         int ret;
1034
1035         /*
1036          * This function can be called in the initialization and reset process,
1037          * when in reset process, it means that hardware had been reseted
1038          * successfully and we need to restore the hardware configuration to
1039          * ensure that the hardware configuration remains unchanged before and
1040          * after reset.
1041          */
1042         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1043                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1044                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1045         }
1046
1047         ret = hns3_vlan_filter_init(hns);
1048         if (ret) {
1049                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1050                 return ret;
1051         }
1052
1053         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1054                                        RTE_ETHER_TYPE_VLAN);
1055         if (ret) {
1056                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1057                 return ret;
1058         }
1059
1060         /*
1061          * When in the reinit dev stage of the reset process, the following
1062          * vlan-related configurations may differ from those at initialization,
1063          * we will restore configurations to hardware in hns3_restore_vlan_table
1064          * and hns3_restore_vlan_conf later.
1065          */
1066         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1067                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1068                 if (ret) {
1069                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1070                         return ret;
1071                 }
1072
1073                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1074                 if (ret) {
1075                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1076                                  ret);
1077                         return ret;
1078                 }
1079         }
1080
1081         return hns3_default_vlan_config(hns);
1082 }
1083
1084 static int
1085 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1086 {
1087         struct hns3_pf *pf = &hns->pf;
1088         struct hns3_hw *hw = &hns->hw;
1089         uint64_t offloads;
1090         bool enable;
1091         int ret;
1092
1093         if (!hw->data->promiscuous) {
1094                 /* restore vlan filter states */
1095                 offloads = hw->data->dev_conf.rxmode.offloads;
1096                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1097                 ret = hns3_enable_vlan_filter(hns, enable);
1098                 if (ret) {
1099                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1100                                  "ret = %d", ret);
1101                         return ret;
1102                 }
1103         }
1104
1105         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1106         if (ret) {
1107                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1108                 return ret;
1109         }
1110
1111         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1112         if (ret)
1113                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1114
1115         return ret;
1116 }
1117
1118 static int
1119 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1120 {
1121         struct hns3_adapter *hns = dev->data->dev_private;
1122         struct rte_eth_dev_data *data = dev->data;
1123         struct rte_eth_txmode *txmode;
1124         struct hns3_hw *hw = &hns->hw;
1125         int mask;
1126         int ret;
1127
1128         txmode = &data->dev_conf.txmode;
1129         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1130                 hns3_warn(hw,
1131                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1132                           "configuration is not supported! Ignore these two "
1133                           "parameters: hw_vlan_reject_tagged(%u), "
1134                           "hw_vlan_reject_untagged(%u)",
1135                           txmode->hw_vlan_reject_tagged,
1136                           txmode->hw_vlan_reject_untagged);
1137
1138         /* Apply vlan offload setting */
1139         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1140         ret = hns3_vlan_offload_set(dev, mask);
1141         if (ret) {
1142                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1143                          ret);
1144                 return ret;
1145         }
1146
1147         /*
1148          * If pvid config is not set in rte_eth_conf, driver needn't to set
1149          * VLAN pvid related configuration to hardware.
1150          */
1151         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1152                 return 0;
1153
1154         /* Apply pvid setting */
1155         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1156                                  txmode->hw_vlan_insert_pvid);
1157         if (ret)
1158                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1159                          txmode->pvid, ret);
1160
1161         return ret;
1162 }
1163
1164 static int
1165 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1166                 unsigned int tso_mss_max)
1167 {
1168         struct hns3_cfg_tso_status_cmd *req;
1169         struct hns3_cmd_desc desc;
1170         uint16_t tso_mss;
1171
1172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1173
1174         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1175
1176         tso_mss = 0;
1177         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1178                        tso_mss_min);
1179         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1180
1181         tso_mss = 0;
1182         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1183                        tso_mss_max);
1184         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1185
1186         return hns3_cmd_send(hw, &desc, 1);
1187 }
1188
1189 static int
1190 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1191                    uint16_t *allocated_size, bool is_alloc)
1192 {
1193         struct hns3_umv_spc_alc_cmd *req;
1194         struct hns3_cmd_desc desc;
1195         int ret;
1196
1197         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1198         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1199         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1200         req->space_size = rte_cpu_to_le_32(space_size);
1201
1202         ret = hns3_cmd_send(hw, &desc, 1);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1205                              is_alloc ? "allocate" : "free", ret);
1206                 return ret;
1207         }
1208
1209         if (is_alloc && allocated_size)
1210                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1211
1212         return 0;
1213 }
1214
1215 static int
1216 hns3_init_umv_space(struct hns3_hw *hw)
1217 {
1218         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219         struct hns3_pf *pf = &hns->pf;
1220         uint16_t allocated_size = 0;
1221         int ret;
1222
1223         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1224                                  true);
1225         if (ret)
1226                 return ret;
1227
1228         if (allocated_size < pf->wanted_umv_size)
1229                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1230                              pf->wanted_umv_size, allocated_size);
1231
1232         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1233                                                 pf->wanted_umv_size;
1234         pf->used_umv_size = 0;
1235         return 0;
1236 }
1237
1238 static int
1239 hns3_uninit_umv_space(struct hns3_hw *hw)
1240 {
1241         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242         struct hns3_pf *pf = &hns->pf;
1243         int ret;
1244
1245         if (pf->max_umv_size == 0)
1246                 return 0;
1247
1248         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1249         if (ret)
1250                 return ret;
1251
1252         pf->max_umv_size = 0;
1253
1254         return 0;
1255 }
1256
1257 static bool
1258 hns3_is_umv_space_full(struct hns3_hw *hw)
1259 {
1260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1261         struct hns3_pf *pf = &hns->pf;
1262         bool is_full;
1263
1264         is_full = (pf->used_umv_size >= pf->max_umv_size);
1265
1266         return is_full;
1267 }
1268
1269 static void
1270 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1271 {
1272         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1273         struct hns3_pf *pf = &hns->pf;
1274
1275         if (is_free) {
1276                 if (pf->used_umv_size > 0)
1277                         pf->used_umv_size--;
1278         } else
1279                 pf->used_umv_size++;
1280 }
1281
1282 static void
1283 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1284                       const uint8_t *addr, bool is_mc)
1285 {
1286         const unsigned char *mac_addr = addr;
1287         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1288                             ((uint32_t)mac_addr[2] << 16) |
1289                             ((uint32_t)mac_addr[1] << 8) |
1290                             (uint32_t)mac_addr[0];
1291         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1292
1293         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1294         if (is_mc) {
1295                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1296                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1297                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1298         }
1299
1300         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1301         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1302 }
1303
1304 static int
1305 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1306                              uint8_t resp_code,
1307                              enum hns3_mac_vlan_tbl_opcode op)
1308 {
1309         if (cmdq_resp) {
1310                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1311                          cmdq_resp);
1312                 return -EIO;
1313         }
1314
1315         if (op == HNS3_MAC_VLAN_ADD) {
1316                 if (resp_code == 0 || resp_code == 1) {
1317                         return 0;
1318                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1319                         hns3_err(hw, "add mac addr failed for uc_overflow");
1320                         return -ENOSPC;
1321                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1322                         hns3_err(hw, "add mac addr failed for mc_overflow");
1323                         return -ENOSPC;
1324                 }
1325
1326                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1327                          resp_code);
1328                 return -EIO;
1329         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1330                 if (resp_code == 0) {
1331                         return 0;
1332                 } else if (resp_code == 1) {
1333                         hns3_dbg(hw, "remove mac addr failed for miss");
1334                         return -ENOENT;
1335                 }
1336
1337                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1338                          resp_code);
1339                 return -EIO;
1340         } else if (op == HNS3_MAC_VLAN_LKUP) {
1341                 if (resp_code == 0) {
1342                         return 0;
1343                 } else if (resp_code == 1) {
1344                         hns3_dbg(hw, "lookup mac addr failed for miss");
1345                         return -ENOENT;
1346                 }
1347
1348                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1349                          resp_code);
1350                 return -EIO;
1351         }
1352
1353         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1354                  op);
1355
1356         return -EINVAL;
1357 }
1358
1359 static int
1360 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1361                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1362                          struct hns3_cmd_desc *desc, bool is_mc)
1363 {
1364         uint8_t resp_code;
1365         uint16_t retval;
1366         int ret;
1367
1368         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1369         if (is_mc) {
1370                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 memcpy(desc[0].data, req,
1372                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1373                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1374                                           true);
1375                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1376                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1377                                           true);
1378                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379         } else {
1380                 memcpy(desc[0].data, req,
1381                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1382                 ret = hns3_cmd_send(hw, desc, 1);
1383         }
1384         if (ret) {
1385                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1386                          ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc[0].retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_LKUP);
1394 }
1395
1396 static int
1397 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1398                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1399                       struct hns3_cmd_desc *mc_desc)
1400 {
1401         uint8_t resp_code;
1402         uint16_t retval;
1403         int cfg_status;
1404         int ret;
1405
1406         if (mc_desc == NULL) {
1407                 struct hns3_cmd_desc desc;
1408
1409                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1410                 memcpy(desc.data, req,
1411                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 ret = hns3_cmd_send(hw, &desc, 1);
1413                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1414                 retval = rte_le_to_cpu_16(desc.retval);
1415
1416                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1417                                                           HNS3_MAC_VLAN_ADD);
1418         } else {
1419                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1420                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1422                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1423                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1424                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1425                 memcpy(mc_desc[0].data, req,
1426                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1427                 mc_desc[0].retval = 0;
1428                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1429                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1430                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1431
1432                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1433                                                           HNS3_MAC_VLAN_ADD);
1434         }
1435
1436         if (ret) {
1437                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1438                 return ret;
1439         }
1440
1441         return cfg_status;
1442 }
1443
1444 static int
1445 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1446                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1447 {
1448         struct hns3_cmd_desc desc;
1449         uint8_t resp_code;
1450         uint16_t retval;
1451         int ret;
1452
1453         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1454
1455         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1456
1457         ret = hns3_cmd_send(hw, &desc, 1);
1458         if (ret) {
1459                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1460                 return ret;
1461         }
1462         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1463         retval = rte_le_to_cpu_16(desc.retval);
1464
1465         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1466                                             HNS3_MAC_VLAN_REMOVE);
1467 }
1468
1469 static int
1470 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1471 {
1472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1473         struct hns3_mac_vlan_tbl_entry_cmd req;
1474         struct hns3_pf *pf = &hns->pf;
1475         struct hns3_cmd_desc desc[3];
1476         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1477         uint16_t egress_port = 0;
1478         uint8_t vf_id;
1479         int ret;
1480
1481         /* check if mac addr is valid */
1482         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1483                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1484                                       mac_addr);
1485                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1486                          mac_str);
1487                 return -EINVAL;
1488         }
1489
1490         memset(&req, 0, sizeof(req));
1491
1492         /*
1493          * In current version VF is not supported when PF is driven by DPDK
1494          * driver, just need to configure parameters for PF vport.
1495          */
1496         vf_id = HNS3_PF_FUNC_ID;
1497         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1498                        HNS3_MAC_EPORT_VFID_S, vf_id);
1499
1500         req.egress_port = rte_cpu_to_le_16(egress_port);
1501
1502         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1503
1504         /*
1505          * Lookup the mac address in the mac_vlan table, and add
1506          * it if the entry is inexistent. Repeated unicast entry
1507          * is not allowed in the mac vlan table.
1508          */
1509         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1510         if (ret == -ENOENT) {
1511                 if (!hns3_is_umv_space_full(hw)) {
1512                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1513                         if (!ret)
1514                                 hns3_update_umv_space(hw, false);
1515                         return ret;
1516                 }
1517
1518                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1519
1520                 return -ENOSPC;
1521         }
1522
1523         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1524
1525         /* check if we just hit the duplicate */
1526         if (ret == 0) {
1527                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1528                 return 0;
1529         }
1530
1531         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1532                  mac_str);
1533
1534         return ret;
1535 }
1536
1537 static int
1538 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541         struct rte_ether_addr *addr;
1542         int ret;
1543         int i;
1544
1545         for (i = 0; i < hw->mc_addrs_num; i++) {
1546                 addr = &hw->mc_addrs[i];
1547                 /* Check if there are duplicate addresses */
1548                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1549                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                               addr);
1551                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1552                                  "(%s) is added by the set_mc_mac_addr_list "
1553                                  "API", mac_str);
1554                         return -EINVAL;
1555                 }
1556         }
1557
1558         ret = hns3_add_mc_addr(hw, mac_addr);
1559         if (ret) {
1560                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1563                          mac_str, ret);
1564         }
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         int ret;
1573
1574         ret = hns3_remove_mc_addr(hw, mac_addr);
1575         if (ret) {
1576                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1577                                       mac_addr);
1578                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1579                          mac_str, ret);
1580         }
1581         return ret;
1582 }
1583
1584 static int
1585 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1586                   uint32_t idx, __rte_unused uint32_t pool)
1587 {
1588         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590         int ret;
1591
1592         rte_spinlock_lock(&hw->lock);
1593
1594         /*
1595          * In hns3 network engine adding UC and MC mac address with different
1596          * commands with firmware. We need to determine whether the input
1597          * address is a UC or a MC address to call different commands.
1598          * By the way, it is recommended calling the API function named
1599          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1600          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1601          * may affect the specifications of UC mac addresses.
1602          */
1603         if (rte_is_multicast_ether_addr(mac_addr))
1604                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1605         else
1606                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1607
1608         if (ret) {
1609                 rte_spinlock_unlock(&hw->lock);
1610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                       mac_addr);
1612                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1613                          ret);
1614                 return ret;
1615         }
1616
1617         if (idx == 0)
1618                 hw->mac.default_addr_setted = true;
1619         rte_spinlock_unlock(&hw->lock);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         struct hns3_mac_vlan_tbl_entry_cmd req;
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         int ret;
1630
1631         /* check if mac addr is valid */
1632         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1633                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634                                       mac_addr);
1635                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1636                          mac_str);
1637                 return -EINVAL;
1638         }
1639
1640         memset(&req, 0, sizeof(req));
1641         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1643         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1644         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1645                 return 0;
1646         else if (ret == 0)
1647                 hns3_update_umv_space(hw, true);
1648
1649         return ret;
1650 }
1651
1652 static void
1653 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1654 {
1655         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         /* index will be checked by upper level rte interface */
1657         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         if (rte_is_multicast_ether_addr(mac_addr))
1664                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1665         else
1666                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1667         rte_spinlock_unlock(&hw->lock);
1668         if (ret) {
1669                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670                                       mac_addr);
1671                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1672                          ret);
1673         }
1674 }
1675
1676 static int
1677 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1678                           struct rte_ether_addr *mac_addr)
1679 {
1680         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_ether_addr *oaddr;
1682         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683         bool default_addr_setted;
1684         bool rm_succes = false;
1685         int ret, ret_val;
1686
1687         /*
1688          * It has been guaranteed that input parameter named mac_addr is valid
1689          * address in the rte layer of DPDK framework.
1690          */
1691         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1692         default_addr_setted = hw->mac.default_addr_setted;
1693         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1694                 return 0;
1695
1696         rte_spinlock_lock(&hw->lock);
1697         if (default_addr_setted) {
1698                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1699                 if (ret) {
1700                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701                                               oaddr);
1702                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1703                                   mac_str, ret);
1704                         rm_succes = false;
1705                 } else
1706                         rm_succes = true;
1707         }
1708
1709         ret = hns3_add_uc_addr_common(hw, mac_addr);
1710         if (ret) {
1711                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1714                 goto err_add_uc_addr;
1715         }
1716
1717         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1718         if (ret) {
1719                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1720                 goto err_pause_addr_cfg;
1721         }
1722
1723         rte_ether_addr_copy(mac_addr,
1724                             (struct rte_ether_addr *)hw->mac.mac_addr);
1725         hw->mac.default_addr_setted = true;
1726         rte_spinlock_unlock(&hw->lock);
1727
1728         return 0;
1729
1730 err_pause_addr_cfg:
1731         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1732         if (ret_val) {
1733                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734                                       mac_addr);
1735                 hns3_warn(hw,
1736                           "Failed to roll back to del setted mac addr(%s): %d",
1737                           mac_str, ret_val);
1738         }
1739
1740 err_add_uc_addr:
1741         if (rm_succes) {
1742                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1743                 if (ret_val) {
1744                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745                                               oaddr);
1746                         hns3_warn(hw,
1747                                   "Failed to restore old uc mac addr(%s): %d",
1748                                   mac_str, ret_val);
1749                         hw->mac.default_addr_setted = false;
1750                 }
1751         }
1752         rte_spinlock_unlock(&hw->lock);
1753
1754         return ret;
1755 }
1756
1757 static int
1758 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1759 {
1760         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1761         struct hns3_hw *hw = &hns->hw;
1762         struct rte_ether_addr *addr;
1763         int err = 0;
1764         int ret;
1765         int i;
1766
1767         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1768                 addr = &hw->data->mac_addrs[i];
1769                 if (rte_is_zero_ether_addr(addr))
1770                         continue;
1771                 if (rte_is_multicast_ether_addr(addr))
1772                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1773                               hns3_add_mc_addr(hw, addr);
1774                 else
1775                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1776                               hns3_add_uc_addr_common(hw, addr);
1777
1778                 if (ret) {
1779                         err = ret;
1780                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                               addr);
1782                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1783                                  "ret = %d.", del ? "remove" : "restore",
1784                                  mac_str, i, ret);
1785                 }
1786         }
1787         return err;
1788 }
1789
1790 static void
1791 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1792 {
1793 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1794         uint8_t word_num;
1795         uint8_t bit_num;
1796
1797         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1798                 word_num = vfid / 32;
1799                 bit_num = vfid % 32;
1800                 if (clr)
1801                         desc[1].data[word_num] &=
1802                             rte_cpu_to_le_32(~(1UL << bit_num));
1803                 else
1804                         desc[1].data[word_num] |=
1805                             rte_cpu_to_le_32(1UL << bit_num);
1806         } else {
1807                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1808                 bit_num = vfid % 32;
1809                 if (clr)
1810                         desc[2].data[word_num] &=
1811                             rte_cpu_to_le_32(~(1UL << bit_num));
1812                 else
1813                         desc[2].data[word_num] |=
1814                             rte_cpu_to_le_32(1UL << bit_num);
1815         }
1816 }
1817
1818 static int
1819 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1820 {
1821         struct hns3_mac_vlan_tbl_entry_cmd req;
1822         struct hns3_cmd_desc desc[3];
1823         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824         uint8_t vf_id;
1825         int ret;
1826
1827         /* Check if mac addr is valid */
1828         if (!rte_is_multicast_ether_addr(mac_addr)) {
1829                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                       mac_addr);
1831                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1832                          mac_str);
1833                 return -EINVAL;
1834         }
1835
1836         memset(&req, 0, sizeof(req));
1837         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1838         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1839         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1840         if (ret) {
1841                 /* This mac addr do not exist, add new entry for it */
1842                 memset(desc[0].data, 0, sizeof(desc[0].data));
1843                 memset(desc[1].data, 0, sizeof(desc[0].data));
1844                 memset(desc[2].data, 0, sizeof(desc[0].data));
1845         }
1846
1847         /*
1848          * In current version VF is not supported when PF is driven by DPDK
1849          * driver, just need to configure parameters for PF vport.
1850          */
1851         vf_id = HNS3_PF_FUNC_ID;
1852         hns3_update_desc_vfid(desc, vf_id, false);
1853         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1854         if (ret) {
1855                 if (ret == -ENOSPC)
1856                         hns3_err(hw, "mc mac vlan table is full");
1857                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1858                                       mac_addr);
1859                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1860         }
1861
1862         return ret;
1863 }
1864
1865 static int
1866 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1867 {
1868         struct hns3_mac_vlan_tbl_entry_cmd req;
1869         struct hns3_cmd_desc desc[3];
1870         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1871         uint8_t vf_id;
1872         int ret;
1873
1874         /* Check if mac addr is valid */
1875         if (!rte_is_multicast_ether_addr(mac_addr)) {
1876                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1877                                       mac_addr);
1878                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1879                          mac_str);
1880                 return -EINVAL;
1881         }
1882
1883         memset(&req, 0, sizeof(req));
1884         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1885         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1886         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1887         if (ret == 0) {
1888                 /*
1889                  * This mac addr exist, remove this handle's VFID for it.
1890                  * In current version VF is not supported when PF is driven by
1891                  * DPDK driver, just need to configure parameters for PF vport.
1892                  */
1893                 vf_id = HNS3_PF_FUNC_ID;
1894                 hns3_update_desc_vfid(desc, vf_id, true);
1895
1896                 /* All the vfid is zero, so need to delete this entry */
1897                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1898         } else if (ret == -ENOENT) {
1899                 /* This mac addr doesn't exist. */
1900                 return 0;
1901         }
1902
1903         if (ret) {
1904                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1905                                       mac_addr);
1906                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1907         }
1908
1909         return ret;
1910 }
1911
1912 static int
1913 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1914                            struct rte_ether_addr *mc_addr_set,
1915                            uint32_t nb_mc_addr)
1916 {
1917         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1918         struct rte_ether_addr *addr;
1919         uint32_t i;
1920         uint32_t j;
1921
1922         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1923                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1924                          "invalid. valid range: 0~%d",
1925                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1926                 return -EINVAL;
1927         }
1928
1929         /* Check if input mac addresses are valid */
1930         for (i = 0; i < nb_mc_addr; i++) {
1931                 addr = &mc_addr_set[i];
1932                 if (!rte_is_multicast_ether_addr(addr)) {
1933                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934                                               addr);
1935                         hns3_err(hw,
1936                                  "failed to set mc mac addr, addr(%s) invalid.",
1937                                  mac_str);
1938                         return -EINVAL;
1939                 }
1940
1941                 /* Check if there are duplicate addresses */
1942                 for (j = i + 1; j < nb_mc_addr; j++) {
1943                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944                                 hns3_ether_format_addr(mac_str,
1945                                                       RTE_ETHER_ADDR_FMT_SIZE,
1946                                                       addr);
1947                                 hns3_err(hw, "failed to set mc mac addr, "
1948                                          "addrs invalid. two same addrs(%s).",
1949                                          mac_str);
1950                                 return -EINVAL;
1951                         }
1952                 }
1953
1954                 /*
1955                  * Check if there are duplicate addresses between mac_addrs
1956                  * and mc_addr_set
1957                  */
1958                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1959                         if (rte_is_same_ether_addr(addr,
1960                                                    &hw->data->mac_addrs[j])) {
1961                                 hns3_ether_format_addr(mac_str,
1962                                                       RTE_ETHER_ADDR_FMT_SIZE,
1963                                                       addr);
1964                                 hns3_err(hw, "failed to set mc mac addr, "
1965                                          "addrs invalid. addrs(%s) has already "
1966                                          "configured in mac_addr add API",
1967                                          mac_str);
1968                                 return -EINVAL;
1969                         }
1970                 }
1971         }
1972
1973         return 0;
1974 }
1975
1976 static void
1977 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1978                            struct rte_ether_addr *mc_addr_set,
1979                            int mc_addr_num,
1980                            struct rte_ether_addr *reserved_addr_list,
1981                            int *reserved_addr_num,
1982                            struct rte_ether_addr *add_addr_list,
1983                            int *add_addr_num,
1984                            struct rte_ether_addr *rm_addr_list,
1985                            int *rm_addr_num)
1986 {
1987         struct rte_ether_addr *addr;
1988         int current_addr_num;
1989         int reserved_num = 0;
1990         int add_num = 0;
1991         int rm_num = 0;
1992         int num;
1993         int i;
1994         int j;
1995         bool same_addr;
1996
1997         /* Calculate the mc mac address list that should be removed */
1998         current_addr_num = hw->mc_addrs_num;
1999         for (i = 0; i < current_addr_num; i++) {
2000                 addr = &hw->mc_addrs[i];
2001                 same_addr = false;
2002                 for (j = 0; j < mc_addr_num; j++) {
2003                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2004                                 same_addr = true;
2005                                 break;
2006                         }
2007                 }
2008
2009                 if (!same_addr) {
2010                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2011                         rm_num++;
2012                 } else {
2013                         rte_ether_addr_copy(addr,
2014                                             &reserved_addr_list[reserved_num]);
2015                         reserved_num++;
2016                 }
2017         }
2018
2019         /* Calculate the mc mac address list that should be added */
2020         for (i = 0; i < mc_addr_num; i++) {
2021                 addr = &mc_addr_set[i];
2022                 same_addr = false;
2023                 for (j = 0; j < current_addr_num; j++) {
2024                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2025                                 same_addr = true;
2026                                 break;
2027                         }
2028                 }
2029
2030                 if (!same_addr) {
2031                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2032                         add_num++;
2033                 }
2034         }
2035
2036         /* Reorder the mc mac address list maintained by driver */
2037         for (i = 0; i < reserved_num; i++)
2038                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2039
2040         for (i = 0; i < rm_num; i++) {
2041                 num = reserved_num + i;
2042                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2043         }
2044
2045         *reserved_addr_num = reserved_num;
2046         *add_addr_num = add_num;
2047         *rm_addr_num = rm_num;
2048 }
2049
2050 static int
2051 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2052                           struct rte_ether_addr *mc_addr_set,
2053                           uint32_t nb_mc_addr)
2054 {
2055         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2058         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2059         struct rte_ether_addr *addr;
2060         int reserved_addr_num;
2061         int add_addr_num;
2062         int rm_addr_num;
2063         int mc_addr_num;
2064         int num;
2065         int ret;
2066         int i;
2067
2068         /* Check if input parameters are valid */
2069         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2070         if (ret)
2071                 return ret;
2072
2073         rte_spinlock_lock(&hw->lock);
2074
2075         /*
2076          * Calculate the mc mac address lists those should be removed and be
2077          * added, Reorder the mc mac address list maintained by driver.
2078          */
2079         mc_addr_num = (int)nb_mc_addr;
2080         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2081                                    reserved_addr_list, &reserved_addr_num,
2082                                    add_addr_list, &add_addr_num,
2083                                    rm_addr_list, &rm_addr_num);
2084
2085         /* Remove mc mac addresses */
2086         for (i = 0; i < rm_addr_num; i++) {
2087                 num = rm_addr_num - i - 1;
2088                 addr = &rm_addr_list[num];
2089                 ret = hns3_remove_mc_addr(hw, addr);
2090                 if (ret) {
2091                         rte_spinlock_unlock(&hw->lock);
2092                         return ret;
2093                 }
2094                 hw->mc_addrs_num--;
2095         }
2096
2097         /* Add mc mac addresses */
2098         for (i = 0; i < add_addr_num; i++) {
2099                 addr = &add_addr_list[i];
2100                 ret = hns3_add_mc_addr(hw, addr);
2101                 if (ret) {
2102                         rte_spinlock_unlock(&hw->lock);
2103                         return ret;
2104                 }
2105
2106                 num = reserved_addr_num + i;
2107                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2108                 hw->mc_addrs_num++;
2109         }
2110         rte_spinlock_unlock(&hw->lock);
2111
2112         return 0;
2113 }
2114
2115 static int
2116 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2117 {
2118         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2119         struct hns3_hw *hw = &hns->hw;
2120         struct rte_ether_addr *addr;
2121         int err = 0;
2122         int ret;
2123         int i;
2124
2125         for (i = 0; i < hw->mc_addrs_num; i++) {
2126                 addr = &hw->mc_addrs[i];
2127                 if (!rte_is_multicast_ether_addr(addr))
2128                         continue;
2129                 if (del)
2130                         ret = hns3_remove_mc_addr(hw, addr);
2131                 else
2132                         ret = hns3_add_mc_addr(hw, addr);
2133                 if (ret) {
2134                         err = ret;
2135                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2136                                               addr);
2137                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2138                                  del ? "Remove" : "Restore", mac_str, ret);
2139                 }
2140         }
2141         return err;
2142 }
2143
2144 static int
2145 hns3_check_mq_mode(struct rte_eth_dev *dev)
2146 {
2147         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2148         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2152         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2153         uint8_t num_tc;
2154         int max_tc = 0;
2155         int i;
2156
2157         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2158         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2159
2160         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2161                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2162                          "rx_mq_mode = %d", rx_mq_mode);
2163                 return -EINVAL;
2164         }
2165
2166         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2167             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2168                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2169                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2170                          rx_mq_mode, tx_mq_mode);
2171                 return -EINVAL;
2172         }
2173
2174         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2175                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2176                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2177                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2178                         return -EINVAL;
2179                 }
2180
2181                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2182                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2183                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2184                                  "nb_tcs(%d) != %d or %d in rx direction.",
2185                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2186                         return -EINVAL;
2187                 }
2188
2189                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2190                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2191                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2192                         return -EINVAL;
2193                 }
2194
2195                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2196                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2197                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2198                                          "is not equal to one in tx direction.",
2199                                          i, dcb_rx_conf->dcb_tc[i]);
2200                                 return -EINVAL;
2201                         }
2202                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2203                                 max_tc = dcb_rx_conf->dcb_tc[i];
2204                 }
2205
2206                 num_tc = max_tc + 1;
2207                 if (num_tc > dcb_rx_conf->nb_tcs) {
2208                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2209                                  num_tc, dcb_rx_conf->nb_tcs);
2210                         return -EINVAL;
2211                 }
2212         }
2213
2214         return 0;
2215 }
2216
2217 static int
2218 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2219 {
2220         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221
2222         if (!hns3_dev_dcb_supported(hw)) {
2223                 hns3_err(hw, "this port does not support dcb configurations.");
2224                 return -EOPNOTSUPP;
2225         }
2226
2227         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2228                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2229                 return -EOPNOTSUPP;
2230         }
2231
2232         /* Check multiple queue mode */
2233         return hns3_check_mq_mode(dev);
2234 }
2235
2236 static int
2237 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2238                            enum hns3_ring_type queue_type, uint16_t queue_id)
2239 {
2240         struct hns3_cmd_desc desc;
2241         struct hns3_ctrl_vector_chain_cmd *req =
2242                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2243         enum hns3_cmd_status status;
2244         enum hns3_opcode_type op;
2245         uint16_t tqp_type_and_id = 0;
2246         uint16_t type;
2247         uint16_t gl;
2248
2249         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2250         hns3_cmd_setup_basic_desc(&desc, op, false);
2251         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2252                                               HNS3_TQP_INT_ID_L_S);
2253         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2254                                               HNS3_TQP_INT_ID_H_S);
2255
2256         if (queue_type == HNS3_RING_TYPE_RX)
2257                 gl = HNS3_RING_GL_RX;
2258         else
2259                 gl = HNS3_RING_GL_TX;
2260
2261         type = queue_type;
2262
2263         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2264                        type);
2265         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2266         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2267                        gl);
2268         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2269         req->int_cause_num = 1;
2270         status = hns3_cmd_send(hw, &desc, 1);
2271         if (status) {
2272                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2273                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2274                 return status;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3_init_ring_with_vector(struct hns3_hw *hw)
2282 {
2283         uint16_t vec;
2284         int ret;
2285         int i;
2286
2287         /*
2288          * In hns3 network engine, vector 0 is always the misc interrupt of this
2289          * function, vector 1~N can be used respectively for the queues of the
2290          * function. Tx and Rx queues with the same number share the interrupt
2291          * vector. In the initialization clearing the all hardware mapping
2292          * relationship configurations between queues and interrupt vectors is
2293          * needed, so some error caused by the residual configurations, such as
2294          * the unexpected Tx interrupt, can be avoid.
2295          */
2296         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2297         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2298                 vec = vec - 1; /* the last interrupt is reserved */
2299         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2300         for (i = 0; i < hw->intr_tqps_num; i++) {
2301                 /*
2302                  * Set gap limiter/rate limiter/quanity limiter algorithm
2303                  * configuration for interrupt coalesce of queue's interrupt.
2304                  */
2305                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2306                                        HNS3_TQP_INTR_GL_DEFAULT);
2307                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2308                                        HNS3_TQP_INTR_GL_DEFAULT);
2309                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2310                 /*
2311                  * QL(quantity limiter) is not used currently, just set 0 to
2312                  * close it.
2313                  */
2314                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2315
2316                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2317                                                  HNS3_RING_TYPE_TX, i);
2318                 if (ret) {
2319                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2320                                           "vector: %u, ret=%d", i, vec, ret);
2321                         return ret;
2322                 }
2323
2324                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2325                                                  HNS3_RING_TYPE_RX, i);
2326                 if (ret) {
2327                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2328                                           "vector: %u, ret=%d", i, vec, ret);
2329                         return ret;
2330                 }
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 hns3_dev_configure(struct rte_eth_dev *dev)
2338 {
2339         struct hns3_adapter *hns = dev->data->dev_private;
2340         struct rte_eth_conf *conf = &dev->data->dev_conf;
2341         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2342         struct hns3_hw *hw = &hns->hw;
2343         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2344         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2345         struct rte_eth_rss_conf rss_conf;
2346         uint32_t max_rx_pkt_len;
2347         uint16_t mtu;
2348         bool gro_en;
2349         int ret;
2350
2351         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2352
2353         /*
2354          * Some versions of hardware network engine does not support
2355          * individually enable/disable/reset the Tx or Rx queue. These devices
2356          * must enable/disable/reset Tx and Rx queues at the same time. When the
2357          * numbers of Tx queues allocated by upper applications are not equal to
2358          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2359          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2360          * work as usual. But these fake queues are imperceptible, and can not
2361          * be used by upper applications.
2362          */
2363         if (!hns3_dev_indep_txrx_supported(hw)) {
2364                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2365                 if (ret) {
2366                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2367                                  ret);
2368                         return ret;
2369                 }
2370         }
2371
2372         hw->adapter_state = HNS3_NIC_CONFIGURING;
2373         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2374                 hns3_err(hw, "setting link speed/duplex not supported");
2375                 ret = -EINVAL;
2376                 goto cfg_err;
2377         }
2378
2379         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2380                 ret = hns3_check_dcb_cfg(dev);
2381                 if (ret)
2382                         goto cfg_err;
2383         }
2384
2385         /* When RSS is not configured, redirect the packet queue 0 */
2386         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2387                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2388                 rss_conf = conf->rx_adv_conf.rss_conf;
2389                 hw->rss_dis_flag = false;
2390                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2391                 if (ret)
2392                         goto cfg_err;
2393         }
2394
2395         /*
2396          * If jumbo frames are enabled, MTU needs to be refreshed
2397          * according to the maximum RX packet length.
2398          */
2399         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2400                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2401                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2402                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2403                         hns3_err(hw, "maximum Rx packet length must be greater "
2404                                  "than %u and less than %u when jumbo frame enabled.",
2405                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2406                                  (uint16_t)HNS3_MAX_FRAME_LEN);
2407                         ret = -EINVAL;
2408                         goto cfg_err;
2409                 }
2410
2411                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2412                 ret = hns3_dev_mtu_set(dev, mtu);
2413                 if (ret)
2414                         goto cfg_err;
2415                 dev->data->mtu = mtu;
2416         }
2417
2418         ret = hns3_dev_configure_vlan(dev);
2419         if (ret)
2420                 goto cfg_err;
2421
2422         /* config hardware GRO */
2423         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2424         ret = hns3_config_gro(hw, gro_en);
2425         if (ret)
2426                 goto cfg_err;
2427
2428         hns->rx_simple_allowed = true;
2429         hns->rx_vec_allowed = true;
2430         hns->tx_simple_allowed = true;
2431         hns->tx_vec_allowed = true;
2432
2433         hns3_init_rx_ptype_tble(dev);
2434         hw->adapter_state = HNS3_NIC_CONFIGURED;
2435
2436         return 0;
2437
2438 cfg_err:
2439         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2440         hw->adapter_state = HNS3_NIC_INITIALIZED;
2441
2442         return ret;
2443 }
2444
2445 static int
2446 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2447 {
2448         struct hns3_config_max_frm_size_cmd *req;
2449         struct hns3_cmd_desc desc;
2450
2451         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2452
2453         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2454         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2455         req->min_frm_size = RTE_ETHER_MIN_LEN;
2456
2457         return hns3_cmd_send(hw, &desc, 1);
2458 }
2459
2460 static int
2461 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2462 {
2463         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2464         uint16_t original_mps = hns->pf.mps;
2465         int err;
2466         int ret;
2467
2468         ret = hns3_set_mac_mtu(hw, mps);
2469         if (ret) {
2470                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2471                 return ret;
2472         }
2473
2474         hns->pf.mps = mps;
2475         ret = hns3_buffer_alloc(hw);
2476         if (ret) {
2477                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2478                 goto rollback;
2479         }
2480
2481         return 0;
2482
2483 rollback:
2484         err = hns3_set_mac_mtu(hw, original_mps);
2485         if (err) {
2486                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2487                 return ret;
2488         }
2489         hns->pf.mps = original_mps;
2490
2491         return ret;
2492 }
2493
2494 static int
2495 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2496 {
2497         struct hns3_adapter *hns = dev->data->dev_private;
2498         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2499         struct hns3_hw *hw = &hns->hw;
2500         bool is_jumbo_frame;
2501         int ret;
2502
2503         if (dev->data->dev_started) {
2504                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2505                          "before configuration", dev->data->port_id);
2506                 return -EBUSY;
2507         }
2508
2509         rte_spinlock_lock(&hw->lock);
2510         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2511         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2512
2513         /*
2514          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2515          * assign to "uint16_t" type variable.
2516          */
2517         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2518         if (ret) {
2519                 rte_spinlock_unlock(&hw->lock);
2520                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2521                          dev->data->port_id, mtu, ret);
2522                 return ret;
2523         }
2524
2525         if (is_jumbo_frame)
2526                 dev->data->dev_conf.rxmode.offloads |=
2527                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2528         else
2529                 dev->data->dev_conf.rxmode.offloads &=
2530                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2531         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2532         rte_spinlock_unlock(&hw->lock);
2533
2534         return 0;
2535 }
2536
2537 int
2538 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2539 {
2540         struct hns3_adapter *hns = eth_dev->data->dev_private;
2541         struct hns3_hw *hw = &hns->hw;
2542         uint16_t queue_num = hw->tqps_num;
2543
2544         /*
2545          * In interrupt mode, 'max_rx_queues' is set based on the number of
2546          * MSI-X interrupt resources of the hardware.
2547          */
2548         if (hw->data->dev_conf.intr_conf.rxq == 1)
2549                 queue_num = hw->intr_tqps_num;
2550
2551         info->max_rx_queues = queue_num;
2552         info->max_tx_queues = hw->tqps_num;
2553         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2554         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2555         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2556         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2557         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2558         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2559                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2560                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2561                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2562                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2563                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2564                                  DEV_RX_OFFLOAD_KEEP_CRC |
2565                                  DEV_RX_OFFLOAD_SCATTER |
2566                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2567                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2568                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2569                                  DEV_RX_OFFLOAD_RSS_HASH |
2570                                  DEV_RX_OFFLOAD_TCP_LRO);
2571         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2572                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2573                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2574                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2575                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2576                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2577                                  DEV_TX_OFFLOAD_TCP_TSO |
2578                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2579                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2580                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2581                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2582                                  hns3_txvlan_cap_get(hw));
2583
2584         if (hns3_dev_indep_txrx_supported(hw))
2585                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2586                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2587
2588         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2589                 .nb_max = HNS3_MAX_RING_DESC,
2590                 .nb_min = HNS3_MIN_RING_DESC,
2591                 .nb_align = HNS3_ALIGN_RING_DESC,
2592         };
2593
2594         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2595                 .nb_max = HNS3_MAX_RING_DESC,
2596                 .nb_min = HNS3_MIN_RING_DESC,
2597                 .nb_align = HNS3_ALIGN_RING_DESC,
2598                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2599                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2600         };
2601
2602         info->default_rxconf = (struct rte_eth_rxconf) {
2603                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2604                 /*
2605                  * If there are no available Rx buffer descriptors, incoming
2606                  * packets are always dropped by hardware based on hns3 network
2607                  * engine.
2608                  */
2609                 .rx_drop_en = 1,
2610                 .offloads = 0,
2611         };
2612         info->default_txconf = (struct rte_eth_txconf) {
2613                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2614                 .offloads = 0,
2615         };
2616
2617         info->vmdq_queue_num = 0;
2618
2619         info->reta_size = hw->rss_ind_tbl_size;
2620         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2621         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2622
2623         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2624         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2625         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2626         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2627         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2628         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2629
2630         return 0;
2631 }
2632
2633 static int
2634 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2635                     size_t fw_size)
2636 {
2637         struct hns3_adapter *hns = eth_dev->data->dev_private;
2638         struct hns3_hw *hw = &hns->hw;
2639         uint32_t version = hw->fw_version;
2640         int ret;
2641
2642         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2643                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2644                                       HNS3_FW_VERSION_BYTE3_S),
2645                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2646                                       HNS3_FW_VERSION_BYTE2_S),
2647                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2648                                       HNS3_FW_VERSION_BYTE1_S),
2649                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2650                                       HNS3_FW_VERSION_BYTE0_S));
2651         ret += 1; /* add the size of '\0' */
2652         if (fw_size < (uint32_t)ret)
2653                 return ret;
2654         else
2655                 return 0;
2656 }
2657
2658 static int
2659 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2660                      __rte_unused int wait_to_complete)
2661 {
2662         struct hns3_adapter *hns = eth_dev->data->dev_private;
2663         struct hns3_hw *hw = &hns->hw;
2664         struct hns3_mac *mac = &hw->mac;
2665         struct rte_eth_link new_link;
2666
2667         if (!hns3_is_reset_pending(hns)) {
2668                 hns3_update_link_status(hw);
2669                 hns3_update_link_info(eth_dev);
2670         }
2671
2672         memset(&new_link, 0, sizeof(new_link));
2673         switch (mac->link_speed) {
2674         case ETH_SPEED_NUM_10M:
2675         case ETH_SPEED_NUM_100M:
2676         case ETH_SPEED_NUM_1G:
2677         case ETH_SPEED_NUM_10G:
2678         case ETH_SPEED_NUM_25G:
2679         case ETH_SPEED_NUM_40G:
2680         case ETH_SPEED_NUM_50G:
2681         case ETH_SPEED_NUM_100G:
2682         case ETH_SPEED_NUM_200G:
2683                 new_link.link_speed = mac->link_speed;
2684                 break;
2685         default:
2686                 new_link.link_speed = ETH_SPEED_NUM_100M;
2687                 break;
2688         }
2689
2690         new_link.link_duplex = mac->link_duplex;
2691         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2692         new_link.link_autoneg =
2693             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2694
2695         return rte_eth_linkstatus_set(eth_dev, &new_link);
2696 }
2697
2698 static int
2699 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2700 {
2701         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2702         struct hns3_pf *pf = &hns->pf;
2703
2704         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2705                 return -EINVAL;
2706
2707         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2708
2709         return 0;
2710 }
2711
2712 static int
2713 hns3_query_function_status(struct hns3_hw *hw)
2714 {
2715 #define HNS3_QUERY_MAX_CNT              10
2716 #define HNS3_QUERY_SLEEP_MSCOEND        1
2717         struct hns3_func_status_cmd *req;
2718         struct hns3_cmd_desc desc;
2719         int timeout = 0;
2720         int ret;
2721
2722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2723         req = (struct hns3_func_status_cmd *)desc.data;
2724
2725         do {
2726                 ret = hns3_cmd_send(hw, &desc, 1);
2727                 if (ret) {
2728                         PMD_INIT_LOG(ERR, "query function status failed %d",
2729                                      ret);
2730                         return ret;
2731                 }
2732
2733                 /* Check pf reset is done */
2734                 if (req->pf_state)
2735                         break;
2736
2737                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2738         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2739
2740         return hns3_parse_func_status(hw, req);
2741 }
2742
2743 static int
2744 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2745 {
2746         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2747         struct hns3_pf *pf = &hns->pf;
2748
2749         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2750                 /*
2751                  * The total_tqps_num obtained from firmware is maximum tqp
2752                  * numbers of this port, which should be used for PF and VFs.
2753                  * There is no need for pf to have so many tqp numbers in
2754                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2755                  * coming from config file, is assigned to maximum queue number
2756                  * for the PF of this port by user. So users can modify the
2757                  * maximum queue number of PF according to their own application
2758                  * scenarios, which is more flexible to use. In addition, many
2759                  * memories can be saved due to allocating queue statistics
2760                  * room according to the actual number of queues required. The
2761                  * maximum queue number of PF for network engine with
2762                  * revision_id greater than 0x30 is assigned by config file.
2763                  */
2764                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2765                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2766                                  "must be greater than 0.",
2767                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2768                         return -EINVAL;
2769                 }
2770
2771                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2772                                        hw->total_tqps_num);
2773         } else {
2774                 /*
2775                  * Due to the limitation on the number of PF interrupts
2776                  * available, the maximum queue number assigned to PF on
2777                  * the network engine with revision_id 0x21 is 64.
2778                  */
2779                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2780                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2781         }
2782
2783         return 0;
2784 }
2785
2786 static int
2787 hns3_query_pf_resource(struct hns3_hw *hw)
2788 {
2789         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2790         struct hns3_pf *pf = &hns->pf;
2791         struct hns3_pf_res_cmd *req;
2792         struct hns3_cmd_desc desc;
2793         int ret;
2794
2795         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2796         ret = hns3_cmd_send(hw, &desc, 1);
2797         if (ret) {
2798                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2799                 return ret;
2800         }
2801
2802         req = (struct hns3_pf_res_cmd *)desc.data;
2803         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2804                              rte_le_to_cpu_16(req->ext_tqp_num);
2805         ret = hns3_get_pf_max_tqp_num(hw);
2806         if (ret)
2807                 return ret;
2808
2809         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2810         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2811
2812         if (req->tx_buf_size)
2813                 pf->tx_buf_size =
2814                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2815         else
2816                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2817
2818         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2819
2820         if (req->dv_buf_size)
2821                 pf->dv_buf_size =
2822                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2823         else
2824                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2825
2826         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2827
2828         hw->num_msi =
2829                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2830                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2831
2832         return 0;
2833 }
2834
2835 static void
2836 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2837 {
2838         struct hns3_cfg_param_cmd *req;
2839         uint64_t mac_addr_tmp_high;
2840         uint8_t ext_rss_size_max;
2841         uint64_t mac_addr_tmp;
2842         uint32_t i;
2843
2844         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2845
2846         /* get the configuration */
2847         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2848                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2849         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2850                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2851         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2852                                            HNS3_CFG_TQP_DESC_N_M,
2853                                            HNS3_CFG_TQP_DESC_N_S);
2854
2855         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2856                                        HNS3_CFG_PHY_ADDR_M,
2857                                        HNS3_CFG_PHY_ADDR_S);
2858         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2859                                          HNS3_CFG_MEDIA_TP_M,
2860                                          HNS3_CFG_MEDIA_TP_S);
2861         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2862                                          HNS3_CFG_RX_BUF_LEN_M,
2863                                          HNS3_CFG_RX_BUF_LEN_S);
2864         /* get mac address */
2865         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2866         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2867                                            HNS3_CFG_MAC_ADDR_H_M,
2868                                            HNS3_CFG_MAC_ADDR_H_S);
2869
2870         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2871
2872         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2873                                             HNS3_CFG_DEFAULT_SPEED_M,
2874                                             HNS3_CFG_DEFAULT_SPEED_S);
2875         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2876                                            HNS3_CFG_RSS_SIZE_M,
2877                                            HNS3_CFG_RSS_SIZE_S);
2878
2879         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2880                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2881
2882         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2883         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2884
2885         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2886                                             HNS3_CFG_SPEED_ABILITY_M,
2887                                             HNS3_CFG_SPEED_ABILITY_S);
2888         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2889                                         HNS3_CFG_UMV_TBL_SPACE_M,
2890                                         HNS3_CFG_UMV_TBL_SPACE_S);
2891         if (!cfg->umv_space)
2892                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2893
2894         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2895                                                HNS3_CFG_EXT_RSS_SIZE_M,
2896                                                HNS3_CFG_EXT_RSS_SIZE_S);
2897
2898         /*
2899          * Field ext_rss_size_max obtained from firmware will be more flexible
2900          * for future changes and expansions, which is an exponent of 2, instead
2901          * of reading out directly. If this field is not zero, hns3 PF PMD
2902          * driver uses it as rss_size_max under one TC. Device, whose revision
2903          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2904          * maximum number of queues supported under a TC through this field.
2905          */
2906         if (ext_rss_size_max)
2907                 cfg->rss_size_max = 1U << ext_rss_size_max;
2908 }
2909
2910 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2911  * @hw: pointer to struct hns3_hw
2912  * @hcfg: the config structure to be getted
2913  */
2914 static int
2915 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2916 {
2917         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2918         struct hns3_cfg_param_cmd *req;
2919         uint32_t offset;
2920         uint32_t i;
2921         int ret;
2922
2923         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2924                 offset = 0;
2925                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2926                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2927                                           true);
2928                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2929                                i * HNS3_CFG_RD_LEN_BYTES);
2930                 /* Len should be divided by 4 when send to hardware */
2931                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2932                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2933                 req->offset = rte_cpu_to_le_32(offset);
2934         }
2935
2936         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2937         if (ret) {
2938                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2939                 return ret;
2940         }
2941
2942         hns3_parse_cfg(hcfg, desc);
2943
2944         return 0;
2945 }
2946
2947 static int
2948 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2949 {
2950         switch (speed_cmd) {
2951         case HNS3_CFG_SPEED_10M:
2952                 *speed = ETH_SPEED_NUM_10M;
2953                 break;
2954         case HNS3_CFG_SPEED_100M:
2955                 *speed = ETH_SPEED_NUM_100M;
2956                 break;
2957         case HNS3_CFG_SPEED_1G:
2958                 *speed = ETH_SPEED_NUM_1G;
2959                 break;
2960         case HNS3_CFG_SPEED_10G:
2961                 *speed = ETH_SPEED_NUM_10G;
2962                 break;
2963         case HNS3_CFG_SPEED_25G:
2964                 *speed = ETH_SPEED_NUM_25G;
2965                 break;
2966         case HNS3_CFG_SPEED_40G:
2967                 *speed = ETH_SPEED_NUM_40G;
2968                 break;
2969         case HNS3_CFG_SPEED_50G:
2970                 *speed = ETH_SPEED_NUM_50G;
2971                 break;
2972         case HNS3_CFG_SPEED_100G:
2973                 *speed = ETH_SPEED_NUM_100G;
2974                 break;
2975         case HNS3_CFG_SPEED_200G:
2976                 *speed = ETH_SPEED_NUM_200G;
2977                 break;
2978         default:
2979                 return -EINVAL;
2980         }
2981
2982         return 0;
2983 }
2984
2985 static void
2986 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2987 {
2988         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2989         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2990         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2991         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2992         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2993 }
2994
2995 static void
2996 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2997 {
2998         struct hns3_dev_specs_0_cmd *req0;
2999
3000         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3001
3002         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3003         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3004         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3005         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3006         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3007 }
3008
3009 static int
3010 hns3_check_dev_specifications(struct hns3_hw *hw)
3011 {
3012         if (hw->rss_ind_tbl_size == 0 ||
3013             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3014                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3015                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3016                               HNS3_RSS_IND_TBL_SIZE_MAX);
3017                 return -EINVAL;
3018         }
3019
3020         return 0;
3021 }
3022
3023 static int
3024 hns3_query_dev_specifications(struct hns3_hw *hw)
3025 {
3026         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3027         int ret;
3028         int i;
3029
3030         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3031                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3032                                           true);
3033                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3034         }
3035         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3036
3037         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3038         if (ret)
3039                 return ret;
3040
3041         hns3_parse_dev_specifications(hw, desc);
3042
3043         return hns3_check_dev_specifications(hw);
3044 }
3045
3046 static int
3047 hns3_get_capability(struct hns3_hw *hw)
3048 {
3049         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3050         struct rte_pci_device *pci_dev;
3051         struct hns3_pf *pf = &hns->pf;
3052         struct rte_eth_dev *eth_dev;
3053         uint16_t device_id;
3054         uint8_t revision;
3055         int ret;
3056
3057         eth_dev = &rte_eth_devices[hw->data->port_id];
3058         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3059         device_id = pci_dev->id.device_id;
3060
3061         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3062             device_id == HNS3_DEV_ID_50GE_RDMA ||
3063             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3064             device_id == HNS3_DEV_ID_200G_RDMA)
3065                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3066
3067         /* Get PCI revision id */
3068         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3069                                   HNS3_PCI_REVISION_ID);
3070         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3071                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3072                              ret);
3073                 return -EIO;
3074         }
3075         hw->revision = revision;
3076
3077         if (revision < PCI_REVISION_ID_HIP09_A) {
3078                 hns3_set_default_dev_specifications(hw);
3079                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3080                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3081                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3082                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3083                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3084                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3085                 hw->rss_info.ipv6_sctp_offload_supported = false;
3086                 return 0;
3087         }
3088
3089         ret = hns3_query_dev_specifications(hw);
3090         if (ret) {
3091                 PMD_INIT_LOG(ERR,
3092                              "failed to query dev specifications, ret = %d",
3093                              ret);
3094                 return ret;
3095         }
3096
3097         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3098         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3099         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3100         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3101         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3102         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3103         hw->rss_info.ipv6_sctp_offload_supported = true;
3104
3105         return 0;
3106 }
3107
3108 static int
3109 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3110 {
3111         int ret;
3112
3113         switch (media_type) {
3114         case HNS3_MEDIA_TYPE_COPPER:
3115                 if (!hns3_dev_copper_supported(hw)) {
3116                         PMD_INIT_LOG(ERR,
3117                                      "Media type is copper, not supported.");
3118                         ret = -EOPNOTSUPP;
3119                 } else {
3120                         ret = 0;
3121                 }
3122                 break;
3123         case HNS3_MEDIA_TYPE_FIBER:
3124                 ret = 0;
3125                 break;
3126         case HNS3_MEDIA_TYPE_BACKPLANE:
3127                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3128                 ret = -EOPNOTSUPP;
3129                 break;
3130         default:
3131                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3132                 ret = -EINVAL;
3133                 break;
3134         }
3135
3136         return ret;
3137 }
3138
3139 static int
3140 hns3_get_board_configuration(struct hns3_hw *hw)
3141 {
3142         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3143         struct hns3_pf *pf = &hns->pf;
3144         struct hns3_cfg cfg;
3145         int ret;
3146
3147         ret = hns3_get_board_cfg(hw, &cfg);
3148         if (ret) {
3149                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3150                 return ret;
3151         }
3152
3153         ret = hns3_check_media_type(hw, cfg.media_type);
3154         if (ret)
3155                 return ret;
3156
3157         hw->mac.media_type = cfg.media_type;
3158         hw->rss_size_max = cfg.rss_size_max;
3159         hw->rss_dis_flag = false;
3160         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3161         hw->mac.phy_addr = cfg.phy_addr;
3162         hw->mac.default_addr_setted = false;
3163         hw->num_tx_desc = cfg.tqp_desc_num;
3164         hw->num_rx_desc = cfg.tqp_desc_num;
3165         hw->dcb_info.num_pg = 1;
3166         hw->dcb_info.hw_pfc_map = 0;
3167
3168         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3169         if (ret) {
3170                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3171                              cfg.default_speed, ret);
3172                 return ret;
3173         }
3174
3175         pf->tc_max = cfg.tc_num;
3176         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3177                 PMD_INIT_LOG(WARNING,
3178                              "Get TC num(%u) from flash, set TC num to 1",
3179                              pf->tc_max);
3180                 pf->tc_max = 1;
3181         }
3182
3183         /* Dev does not support DCB */
3184         if (!hns3_dev_dcb_supported(hw)) {
3185                 pf->tc_max = 1;
3186                 pf->pfc_max = 0;
3187         } else
3188                 pf->pfc_max = pf->tc_max;
3189
3190         hw->dcb_info.num_tc = 1;
3191         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3192                                      hw->tqps_num / hw->dcb_info.num_tc);
3193         hns3_set_bit(hw->hw_tc_map, 0, 1);
3194         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3195
3196         pf->wanted_umv_size = cfg.umv_space;
3197
3198         return ret;
3199 }
3200
3201 static int
3202 hns3_get_configuration(struct hns3_hw *hw)
3203 {
3204         int ret;
3205
3206         ret = hns3_query_function_status(hw);
3207         if (ret) {
3208                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3209                 return ret;
3210         }
3211
3212         /* Get device capability */
3213         ret = hns3_get_capability(hw);
3214         if (ret) {
3215                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3216                 return ret;
3217         }
3218
3219         /* Get pf resource */
3220         ret = hns3_query_pf_resource(hw);
3221         if (ret) {
3222                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3223                 return ret;
3224         }
3225
3226         ret = hns3_get_board_configuration(hw);
3227         if (ret) {
3228                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3229                 return ret;
3230         }
3231
3232         ret = hns3_query_dev_fec_info(hw);
3233         if (ret)
3234                 PMD_INIT_LOG(ERR,
3235                              "failed to query FEC information, ret = %d", ret);
3236
3237         return ret;
3238 }
3239
3240 static int
3241 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3242                       uint16_t tqp_vid, bool is_pf)
3243 {
3244         struct hns3_tqp_map_cmd *req;
3245         struct hns3_cmd_desc desc;
3246         int ret;
3247
3248         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3249
3250         req = (struct hns3_tqp_map_cmd *)desc.data;
3251         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3252         req->tqp_vf = func_id;
3253         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3254         if (!is_pf)
3255                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3256         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3257
3258         ret = hns3_cmd_send(hw, &desc, 1);
3259         if (ret)
3260                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3261
3262         return ret;
3263 }
3264
3265 static int
3266 hns3_map_tqp(struct hns3_hw *hw)
3267 {
3268         int ret;
3269         int i;
3270
3271         /*
3272          * In current version, VF is not supported when PF is driven by DPDK
3273          * driver, so we assign total tqps_num tqps allocated to this port
3274          * to PF.
3275          */
3276         for (i = 0; i < hw->total_tqps_num; i++) {
3277                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3278                 if (ret)
3279                         return ret;
3280         }
3281
3282         return 0;
3283 }
3284
3285 static int
3286 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3287 {
3288         struct hns3_config_mac_speed_dup_cmd *req;
3289         struct hns3_cmd_desc desc;
3290         int ret;
3291
3292         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3293
3294         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3295
3296         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3297
3298         switch (speed) {
3299         case ETH_SPEED_NUM_10M:
3300                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3301                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3302                 break;
3303         case ETH_SPEED_NUM_100M:
3304                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3305                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3306                 break;
3307         case ETH_SPEED_NUM_1G:
3308                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3309                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3310                 break;
3311         case ETH_SPEED_NUM_10G:
3312                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3313                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3314                 break;
3315         case ETH_SPEED_NUM_25G:
3316                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3317                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3318                 break;
3319         case ETH_SPEED_NUM_40G:
3320                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3321                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3322                 break;
3323         case ETH_SPEED_NUM_50G:
3324                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3325                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3326                 break;
3327         case ETH_SPEED_NUM_100G:
3328                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3329                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3330                 break;
3331         case ETH_SPEED_NUM_200G:
3332                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3333                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3334                 break;
3335         default:
3336                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3337                 return -EINVAL;
3338         }
3339
3340         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3341
3342         ret = hns3_cmd_send(hw, &desc, 1);
3343         if (ret)
3344                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3345
3346         return ret;
3347 }
3348
3349 static int
3350 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3351 {
3352         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3353         struct hns3_pf *pf = &hns->pf;
3354         struct hns3_priv_buf *priv;
3355         uint32_t i, total_size;
3356
3357         total_size = pf->pkt_buf_size;
3358
3359         /* alloc tx buffer for all enabled tc */
3360         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3361                 priv = &buf_alloc->priv_buf[i];
3362
3363                 if (hw->hw_tc_map & BIT(i)) {
3364                         if (total_size < pf->tx_buf_size)
3365                                 return -ENOMEM;
3366
3367                         priv->tx_buf_size = pf->tx_buf_size;
3368                 } else
3369                         priv->tx_buf_size = 0;
3370
3371                 total_size -= priv->tx_buf_size;
3372         }
3373
3374         return 0;
3375 }
3376
3377 static int
3378 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3379 {
3380 /* TX buffer size is unit by 128 byte */
3381 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3382 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3383         struct hns3_tx_buff_alloc_cmd *req;
3384         struct hns3_cmd_desc desc;
3385         uint32_t buf_size;
3386         uint32_t i;
3387         int ret;
3388
3389         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3390
3391         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3392         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3393                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3394
3395                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3396                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3397                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3398         }
3399
3400         ret = hns3_cmd_send(hw, &desc, 1);
3401         if (ret)
3402                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3403
3404         return ret;
3405 }
3406
3407 static int
3408 hns3_get_tc_num(struct hns3_hw *hw)
3409 {
3410         int cnt = 0;
3411         uint8_t i;
3412
3413         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3414                 if (hw->hw_tc_map & BIT(i))
3415                         cnt++;
3416         return cnt;
3417 }
3418
3419 static uint32_t
3420 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3421 {
3422         struct hns3_priv_buf *priv;
3423         uint32_t rx_priv = 0;
3424         int i;
3425
3426         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3427                 priv = &buf_alloc->priv_buf[i];
3428                 if (priv->enable)
3429                         rx_priv += priv->buf_size;
3430         }
3431         return rx_priv;
3432 }
3433
3434 static uint32_t
3435 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3436 {
3437         uint32_t total_tx_size = 0;
3438         uint32_t i;
3439
3440         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3441                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3442
3443         return total_tx_size;
3444 }
3445
3446 /* Get the number of pfc enabled TCs, which have private buffer */
3447 static int
3448 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3449 {
3450         struct hns3_priv_buf *priv;
3451         int cnt = 0;
3452         uint8_t i;
3453
3454         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3455                 priv = &buf_alloc->priv_buf[i];
3456                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3457                         cnt++;
3458         }
3459
3460         return cnt;
3461 }
3462
3463 /* Get the number of pfc disabled TCs, which have private buffer */
3464 static int
3465 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3466                          struct hns3_pkt_buf_alloc *buf_alloc)
3467 {
3468         struct hns3_priv_buf *priv;
3469         int cnt = 0;
3470         uint8_t i;
3471
3472         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3473                 priv = &buf_alloc->priv_buf[i];
3474                 if (hw->hw_tc_map & BIT(i) &&
3475                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3476                         cnt++;
3477         }
3478
3479         return cnt;
3480 }
3481
3482 static bool
3483 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3484                   uint32_t rx_all)
3485 {
3486         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3487         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3488         struct hns3_pf *pf = &hns->pf;
3489         uint32_t shared_buf, aligned_mps;
3490         uint32_t rx_priv;
3491         uint8_t tc_num;
3492         uint8_t i;
3493
3494         tc_num = hns3_get_tc_num(hw);
3495         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3496
3497         if (hns3_dev_dcb_supported(hw))
3498                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3499                                         pf->dv_buf_size;
3500         else
3501                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3502                                         + pf->dv_buf_size;
3503
3504         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3505         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3506                              HNS3_BUF_SIZE_UNIT);
3507
3508         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3509         if (rx_all < rx_priv + shared_std)
3510                 return false;
3511
3512         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3513         buf_alloc->s_buf.buf_size = shared_buf;
3514         if (hns3_dev_dcb_supported(hw)) {
3515                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3516                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3517                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3518                                   HNS3_BUF_SIZE_UNIT);
3519         } else {
3520                 buf_alloc->s_buf.self.high =
3521                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3522                 buf_alloc->s_buf.self.low = aligned_mps;
3523         }
3524
3525         if (hns3_dev_dcb_supported(hw)) {
3526                 hi_thrd = shared_buf - pf->dv_buf_size;
3527
3528                 if (tc_num <= NEED_RESERVE_TC_NUM)
3529                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3530                                   BUF_MAX_PERCENT;
3531
3532                 if (tc_num)
3533                         hi_thrd = hi_thrd / tc_num;
3534
3535                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3536                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3537                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3538         } else {
3539                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3540                 lo_thrd = aligned_mps;
3541         }
3542
3543         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3544                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3545                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3546         }
3547
3548         return true;
3549 }
3550
3551 static bool
3552 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3553                      struct hns3_pkt_buf_alloc *buf_alloc)
3554 {
3555         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3556         struct hns3_pf *pf = &hns->pf;
3557         struct hns3_priv_buf *priv;
3558         uint32_t aligned_mps;
3559         uint32_t rx_all;
3560         uint8_t i;
3561
3562         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3563         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3564
3565         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3566                 priv = &buf_alloc->priv_buf[i];
3567
3568                 priv->enable = 0;
3569                 priv->wl.low = 0;
3570                 priv->wl.high = 0;
3571                 priv->buf_size = 0;
3572
3573                 if (!(hw->hw_tc_map & BIT(i)))
3574                         continue;
3575
3576                 priv->enable = 1;
3577                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3578                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3579                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3580                                                 HNS3_BUF_SIZE_UNIT);
3581                 } else {
3582                         priv->wl.low = 0;
3583                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3584                                         aligned_mps;
3585                 }
3586
3587                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3588         }
3589
3590         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3591 }
3592
3593 static bool
3594 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3595                              struct hns3_pkt_buf_alloc *buf_alloc)
3596 {
3597         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3598         struct hns3_pf *pf = &hns->pf;
3599         struct hns3_priv_buf *priv;
3600         int no_pfc_priv_num;
3601         uint32_t rx_all;
3602         uint8_t mask;
3603         int i;
3604
3605         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3606         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3607
3608         /* let the last to be cleared first */
3609         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3610                 priv = &buf_alloc->priv_buf[i];
3611                 mask = BIT((uint8_t)i);
3612
3613                 if (hw->hw_tc_map & mask &&
3614                     !(hw->dcb_info.hw_pfc_map & mask)) {
3615                         /* Clear the no pfc TC private buffer */
3616                         priv->wl.low = 0;
3617                         priv->wl.high = 0;
3618                         priv->buf_size = 0;
3619                         priv->enable = 0;
3620                         no_pfc_priv_num--;
3621                 }
3622
3623                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3624                     no_pfc_priv_num == 0)
3625                         break;
3626         }
3627
3628         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3629 }
3630
3631 static bool
3632 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3633                            struct hns3_pkt_buf_alloc *buf_alloc)
3634 {
3635         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3636         struct hns3_pf *pf = &hns->pf;
3637         struct hns3_priv_buf *priv;
3638         uint32_t rx_all;
3639         int pfc_priv_num;
3640         uint8_t mask;
3641         int i;
3642
3643         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3644         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3645
3646         /* let the last to be cleared first */
3647         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3648                 priv = &buf_alloc->priv_buf[i];
3649                 mask = BIT((uint8_t)i);
3650                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3651                         /* Reduce the number of pfc TC with private buffer */
3652                         priv->wl.low = 0;
3653                         priv->enable = 0;
3654                         priv->wl.high = 0;
3655                         priv->buf_size = 0;
3656                         pfc_priv_num--;
3657                 }
3658                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3659                     pfc_priv_num == 0)
3660                         break;
3661         }
3662
3663         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3664 }
3665
3666 static bool
3667 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3668                           struct hns3_pkt_buf_alloc *buf_alloc)
3669 {
3670 #define COMPENSATE_BUFFER       0x3C00
3671 #define COMPENSATE_HALF_MPS_NUM 5
3672 #define PRIV_WL_GAP             0x1800
3673         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3674         struct hns3_pf *pf = &hns->pf;
3675         uint32_t tc_num = hns3_get_tc_num(hw);
3676         uint32_t half_mps = pf->mps >> 1;
3677         struct hns3_priv_buf *priv;
3678         uint32_t min_rx_priv;
3679         uint32_t rx_priv;
3680         uint8_t i;
3681
3682         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3683         if (tc_num)
3684                 rx_priv = rx_priv / tc_num;
3685
3686         if (tc_num <= NEED_RESERVE_TC_NUM)
3687                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3688
3689         /*
3690          * Minimum value of private buffer in rx direction (min_rx_priv) is
3691          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3692          * buffer if rx_priv is greater than min_rx_priv.
3693          */
3694         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3695                         COMPENSATE_HALF_MPS_NUM * half_mps;
3696         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3697         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3698
3699         if (rx_priv < min_rx_priv)
3700                 return false;
3701
3702         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3703                 priv = &buf_alloc->priv_buf[i];
3704                 priv->enable = 0;
3705                 priv->wl.low = 0;
3706                 priv->wl.high = 0;
3707                 priv->buf_size = 0;
3708
3709                 if (!(hw->hw_tc_map & BIT(i)))
3710                         continue;
3711
3712                 priv->enable = 1;
3713                 priv->buf_size = rx_priv;
3714                 priv->wl.high = rx_priv - pf->dv_buf_size;
3715                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3716         }
3717
3718         buf_alloc->s_buf.buf_size = 0;
3719
3720         return true;
3721 }
3722
3723 /*
3724  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3725  * @hw: pointer to struct hns3_hw
3726  * @buf_alloc: pointer to buffer calculation data
3727  * @return: 0: calculate sucessful, negative: fail
3728  */
3729 static int
3730 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3731 {
3732         /* When DCB is not supported, rx private buffer is not allocated. */
3733         if (!hns3_dev_dcb_supported(hw)) {
3734                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3735                 struct hns3_pf *pf = &hns->pf;
3736                 uint32_t rx_all = pf->pkt_buf_size;
3737
3738                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3739                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3740                         return -ENOMEM;
3741
3742                 return 0;
3743         }
3744
3745         /*
3746          * Try to allocate privated packet buffer for all TCs without share
3747          * buffer.
3748          */
3749         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3750                 return 0;
3751
3752         /*
3753          * Try to allocate privated packet buffer for all TCs with share
3754          * buffer.
3755          */
3756         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3757                 return 0;
3758
3759         /*
3760          * For different application scenes, the enabled port number, TC number
3761          * and no_drop TC number are different. In order to obtain the better
3762          * performance, software could allocate the buffer size and configure
3763          * the waterline by tring to decrease the private buffer size according
3764          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3765          * enabled tc.
3766          */
3767         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3768                 return 0;
3769
3770         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3771                 return 0;
3772
3773         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3774                 return 0;
3775
3776         return -ENOMEM;
3777 }
3778
3779 static int
3780 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3781 {
3782         struct hns3_rx_priv_buff_cmd *req;
3783         struct hns3_cmd_desc desc;
3784         uint32_t buf_size;
3785         int ret;
3786         int i;
3787
3788         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3789         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3790
3791         /* Alloc private buffer TCs */
3792         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3793                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3794
3795                 req->buf_num[i] =
3796                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3797                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3798         }
3799
3800         buf_size = buf_alloc->s_buf.buf_size;
3801         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3802                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3803
3804         ret = hns3_cmd_send(hw, &desc, 1);
3805         if (ret)
3806                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3807
3808         return ret;
3809 }
3810
3811 static int
3812 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3813 {
3814 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3815         struct hns3_rx_priv_wl_buf *req;
3816         struct hns3_priv_buf *priv;
3817         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3818         int i, j;
3819         int ret;
3820
3821         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3822                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3823                                           false);
3824                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3825
3826                 /* The first descriptor set the NEXT bit to 1 */
3827                 if (i == 0)
3828                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3829                 else
3830                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3831
3832                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3833                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3834
3835                         priv = &buf_alloc->priv_buf[idx];
3836                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3837                                                         HNS3_BUF_UNIT_S);
3838                         req->tc_wl[j].high |=
3839                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3840                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3841                                                         HNS3_BUF_UNIT_S);
3842                         req->tc_wl[j].low |=
3843                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3844                 }
3845         }
3846
3847         /* Send 2 descriptor at one time */
3848         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3849         if (ret)
3850                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3851                              ret);
3852         return ret;
3853 }
3854
3855 static int
3856 hns3_common_thrd_config(struct hns3_hw *hw,
3857                         struct hns3_pkt_buf_alloc *buf_alloc)
3858 {
3859 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3860         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3861         struct hns3_rx_com_thrd *req;
3862         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3863         struct hns3_tc_thrd *tc;
3864         int tc_idx;
3865         int i, j;
3866         int ret;
3867
3868         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3869                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3870                                           false);
3871                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3872
3873                 /* The first descriptor set the NEXT bit to 1 */
3874                 if (i == 0)
3875                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3876                 else
3877                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3878
3879                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3880                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3881                         tc = &s_buf->tc_thrd[tc_idx];
3882
3883                         req->com_thrd[j].high =
3884                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3885                         req->com_thrd[j].high |=
3886                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3887                         req->com_thrd[j].low =
3888                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3889                         req->com_thrd[j].low |=
3890                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3891                 }
3892         }
3893
3894         /* Send 2 descriptors at one time */
3895         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3896         if (ret)
3897                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3898
3899         return ret;
3900 }
3901
3902 static int
3903 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3904 {
3905         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3906         struct hns3_rx_com_wl *req;
3907         struct hns3_cmd_desc desc;
3908         int ret;
3909
3910         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3911
3912         req = (struct hns3_rx_com_wl *)desc.data;
3913         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3914         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3915
3916         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3917         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3918
3919         ret = hns3_cmd_send(hw, &desc, 1);
3920         if (ret)
3921                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3922
3923         return ret;
3924 }
3925
3926 int
3927 hns3_buffer_alloc(struct hns3_hw *hw)
3928 {
3929         struct hns3_pkt_buf_alloc pkt_buf;
3930         int ret;
3931
3932         memset(&pkt_buf, 0, sizeof(pkt_buf));
3933         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3934         if (ret) {
3935                 PMD_INIT_LOG(ERR,
3936                              "could not calc tx buffer size for all TCs %d",
3937                              ret);
3938                 return ret;
3939         }
3940
3941         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3942         if (ret) {
3943                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3944                 return ret;
3945         }
3946
3947         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3948         if (ret) {
3949                 PMD_INIT_LOG(ERR,
3950                              "could not calc rx priv buffer size for all TCs %d",
3951                              ret);
3952                 return ret;
3953         }
3954
3955         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3956         if (ret) {
3957                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3958                 return ret;
3959         }
3960
3961         if (hns3_dev_dcb_supported(hw)) {
3962                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3963                 if (ret) {
3964                         PMD_INIT_LOG(ERR,
3965                                      "could not configure rx private waterline %d",
3966                                      ret);
3967                         return ret;
3968                 }
3969
3970                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3971                 if (ret) {
3972                         PMD_INIT_LOG(ERR,
3973                                      "could not configure common threshold %d",
3974                                      ret);
3975                         return ret;
3976                 }
3977         }
3978
3979         ret = hns3_common_wl_config(hw, &pkt_buf);
3980         if (ret)
3981                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3982                              ret);
3983
3984         return ret;
3985 }
3986
3987 static int
3988 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
3989 {
3990         struct hns3_firmware_compat_cmd *req;
3991         struct hns3_cmd_desc desc;
3992         uint32_t compat = 0;
3993
3994         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
3995         req = (struct hns3_firmware_compat_cmd *)desc.data;
3996
3997         if (is_init) {
3998                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
3999                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4000                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4001                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4002         }
4003
4004         req->compat = rte_cpu_to_le_32(compat);
4005
4006         return hns3_cmd_send(hw, &desc, 1);
4007 }
4008
4009 static int
4010 hns3_mac_init(struct hns3_hw *hw)
4011 {
4012         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4013         struct hns3_mac *mac = &hw->mac;
4014         struct hns3_pf *pf = &hns->pf;
4015         int ret;
4016
4017         pf->support_sfp_query = true;
4018         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4019         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4020         if (ret) {
4021                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4022                 return ret;
4023         }
4024
4025         mac->link_status = ETH_LINK_DOWN;
4026
4027         return hns3_config_mtu(hw, pf->mps);
4028 }
4029
4030 static int
4031 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4032 {
4033 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4034 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4035 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4036 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4037         int return_status;
4038
4039         if (cmdq_resp) {
4040                 PMD_INIT_LOG(ERR,
4041                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4042                              cmdq_resp);
4043                 return -EIO;
4044         }
4045
4046         switch (resp_code) {
4047         case HNS3_ETHERTYPE_SUCCESS_ADD:
4048         case HNS3_ETHERTYPE_ALREADY_ADD:
4049                 return_status = 0;
4050                 break;
4051         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4052                 PMD_INIT_LOG(ERR,
4053                              "add mac ethertype failed for manager table overflow.");
4054                 return_status = -EIO;
4055                 break;
4056         case HNS3_ETHERTYPE_KEY_CONFLICT:
4057                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4058                 return_status = -EIO;
4059                 break;
4060         default:
4061                 PMD_INIT_LOG(ERR,
4062                              "add mac ethertype failed for undefined, code=%u.",
4063                              resp_code);
4064                 return_status = -EIO;
4065                 break;
4066         }
4067
4068         return return_status;
4069 }
4070
4071 static int
4072 hns3_add_mgr_tbl(struct hns3_hw *hw,
4073                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4074 {
4075         struct hns3_cmd_desc desc;
4076         uint8_t resp_code;
4077         uint16_t retval;
4078         int ret;
4079
4080         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4081         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4082
4083         ret = hns3_cmd_send(hw, &desc, 1);
4084         if (ret) {
4085                 PMD_INIT_LOG(ERR,
4086                              "add mac ethertype failed for cmd_send, ret =%d.",
4087                              ret);
4088                 return ret;
4089         }
4090
4091         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4092         retval = rte_le_to_cpu_16(desc.retval);
4093
4094         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4095 }
4096
4097 static void
4098 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4099                      int *table_item_num)
4100 {
4101         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4102
4103         /*
4104          * In current version, we add one item in management table as below:
4105          * 0x0180C200000E -- LLDP MC address
4106          */
4107         tbl = mgr_table;
4108         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4109         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4110         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4111         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4112         tbl->i_port_bitmap = 0x1;
4113         *table_item_num = 1;
4114 }
4115
4116 static int
4117 hns3_init_mgr_tbl(struct hns3_hw *hw)
4118 {
4119 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4120         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4121         int table_item_num;
4122         int ret;
4123         int i;
4124
4125         memset(mgr_table, 0, sizeof(mgr_table));
4126         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4127         for (i = 0; i < table_item_num; i++) {
4128                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4129                 if (ret) {
4130                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4131                                      ret);
4132                         return ret;
4133                 }
4134         }
4135
4136         return 0;
4137 }
4138
4139 static void
4140 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4141                         bool en_mc, bool en_bc, int vport_id)
4142 {
4143         if (!param)
4144                 return;
4145
4146         memset(param, 0, sizeof(struct hns3_promisc_param));
4147         if (en_uc)
4148                 param->enable = HNS3_PROMISC_EN_UC;
4149         if (en_mc)
4150                 param->enable |= HNS3_PROMISC_EN_MC;
4151         if (en_bc)
4152                 param->enable |= HNS3_PROMISC_EN_BC;
4153         param->vf_id = vport_id;
4154 }
4155
4156 static int
4157 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4158 {
4159         struct hns3_promisc_cfg_cmd *req;
4160         struct hns3_cmd_desc desc;
4161         int ret;
4162
4163         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4164
4165         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4166         req->vf_id = param->vf_id;
4167         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4168             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4169
4170         ret = hns3_cmd_send(hw, &desc, 1);
4171         if (ret)
4172                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4173
4174         return ret;
4175 }
4176
4177 static int
4178 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4179 {
4180         struct hns3_promisc_param param;
4181         bool en_bc_pmc = true;
4182         uint8_t vf_id;
4183
4184         /*
4185          * In current version VF is not supported when PF is driven by DPDK
4186          * driver, just need to configure parameters for PF vport.
4187          */
4188         vf_id = HNS3_PF_FUNC_ID;
4189
4190         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4191         return hns3_cmd_set_promisc_mode(hw, &param);
4192 }
4193
4194 static int
4195 hns3_promisc_init(struct hns3_hw *hw)
4196 {
4197         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4198         struct hns3_pf *pf = &hns->pf;
4199         struct hns3_promisc_param param;
4200         uint16_t func_id;
4201         int ret;
4202
4203         ret = hns3_set_promisc_mode(hw, false, false);
4204         if (ret) {
4205                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4206                 return ret;
4207         }
4208
4209         /*
4210          * In current version VFs are not supported when PF is driven by DPDK
4211          * driver. After PF has been taken over by DPDK, the original VF will
4212          * be invalid. So, there is a possibility of entry residues. It should
4213          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4214          * during init.
4215          */
4216         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4217                 hns3_promisc_param_init(&param, false, false, false, func_id);
4218                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4219                 if (ret) {
4220                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4221                                         " ret = %d", func_id, ret);
4222                         return ret;
4223                 }
4224         }
4225
4226         return 0;
4227 }
4228
4229 static void
4230 hns3_promisc_uninit(struct hns3_hw *hw)
4231 {
4232         struct hns3_promisc_param param;
4233         uint16_t func_id;
4234         int ret;
4235
4236         func_id = HNS3_PF_FUNC_ID;
4237
4238         /*
4239          * In current version VFs are not supported when PF is driven by
4240          * DPDK driver, and VFs' promisc mode status has been cleared during
4241          * init and their status will not change. So just clear PF's promisc
4242          * mode status during uninit.
4243          */
4244         hns3_promisc_param_init(&param, false, false, false, func_id);
4245         ret = hns3_cmd_set_promisc_mode(hw, &param);
4246         if (ret)
4247                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4248                                 " uninit, ret = %d", ret);
4249 }
4250
4251 static int
4252 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4253 {
4254         bool allmulti = dev->data->all_multicast ? true : false;
4255         struct hns3_adapter *hns = dev->data->dev_private;
4256         struct hns3_hw *hw = &hns->hw;
4257         uint64_t offloads;
4258         int err;
4259         int ret;
4260
4261         rte_spinlock_lock(&hw->lock);
4262         ret = hns3_set_promisc_mode(hw, true, true);
4263         if (ret) {
4264                 rte_spinlock_unlock(&hw->lock);
4265                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4266                          ret);
4267                 return ret;
4268         }
4269
4270         /*
4271          * When promiscuous mode was enabled, disable the vlan filter to let
4272          * all packets coming in in the receiving direction.
4273          */
4274         offloads = dev->data->dev_conf.rxmode.offloads;
4275         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4276                 ret = hns3_enable_vlan_filter(hns, false);
4277                 if (ret) {
4278                         hns3_err(hw, "failed to enable promiscuous mode due to "
4279                                      "failure to disable vlan filter, ret = %d",
4280                                  ret);
4281                         err = hns3_set_promisc_mode(hw, false, allmulti);
4282                         if (err)
4283                                 hns3_err(hw, "failed to restore promiscuous "
4284                                          "status after disable vlan filter "
4285                                          "failed during enabling promiscuous "
4286                                          "mode, ret = %d", ret);
4287                 }
4288         }
4289
4290         rte_spinlock_unlock(&hw->lock);
4291
4292         return ret;
4293 }
4294
4295 static int
4296 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4297 {
4298         bool allmulti = dev->data->all_multicast ? true : false;
4299         struct hns3_adapter *hns = dev->data->dev_private;
4300         struct hns3_hw *hw = &hns->hw;
4301         uint64_t offloads;
4302         int err;
4303         int ret;
4304
4305         /* If now in all_multicast mode, must remain in all_multicast mode. */
4306         rte_spinlock_lock(&hw->lock);
4307         ret = hns3_set_promisc_mode(hw, false, allmulti);
4308         if (ret) {
4309                 rte_spinlock_unlock(&hw->lock);
4310                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4311                          ret);
4312                 return ret;
4313         }
4314         /* when promiscuous mode was disabled, restore the vlan filter status */
4315         offloads = dev->data->dev_conf.rxmode.offloads;
4316         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4317                 ret = hns3_enable_vlan_filter(hns, true);
4318                 if (ret) {
4319                         hns3_err(hw, "failed to disable promiscuous mode due to"
4320                                  " failure to restore vlan filter, ret = %d",
4321                                  ret);
4322                         err = hns3_set_promisc_mode(hw, true, true);
4323                         if (err)
4324                                 hns3_err(hw, "failed to restore promiscuous "
4325                                          "status after enabling vlan filter "
4326                                          "failed during disabling promiscuous "
4327                                          "mode, ret = %d", ret);
4328                 }
4329         }
4330         rte_spinlock_unlock(&hw->lock);
4331
4332         return ret;
4333 }
4334
4335 static int
4336 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4337 {
4338         struct hns3_adapter *hns = dev->data->dev_private;
4339         struct hns3_hw *hw = &hns->hw;
4340         int ret;
4341
4342         if (dev->data->promiscuous)
4343                 return 0;
4344
4345         rte_spinlock_lock(&hw->lock);
4346         ret = hns3_set_promisc_mode(hw, false, true);
4347         rte_spinlock_unlock(&hw->lock);
4348         if (ret)
4349                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4350                          ret);
4351
4352         return ret;
4353 }
4354
4355 static int
4356 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4357 {
4358         struct hns3_adapter *hns = dev->data->dev_private;
4359         struct hns3_hw *hw = &hns->hw;
4360         int ret;
4361
4362         /* If now in promiscuous mode, must remain in all_multicast mode. */
4363         if (dev->data->promiscuous)
4364                 return 0;
4365
4366         rte_spinlock_lock(&hw->lock);
4367         ret = hns3_set_promisc_mode(hw, false, false);
4368         rte_spinlock_unlock(&hw->lock);
4369         if (ret)
4370                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4371                          ret);
4372
4373         return ret;
4374 }
4375
4376 static int
4377 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4378 {
4379         struct hns3_hw *hw = &hns->hw;
4380         bool allmulti = hw->data->all_multicast ? true : false;
4381         int ret;
4382
4383         if (hw->data->promiscuous) {
4384                 ret = hns3_set_promisc_mode(hw, true, true);
4385                 if (ret)
4386                         hns3_err(hw, "failed to restore promiscuous mode, "
4387                                  "ret = %d", ret);
4388                 return ret;
4389         }
4390
4391         ret = hns3_set_promisc_mode(hw, false, allmulti);
4392         if (ret)
4393                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4394                          ret);
4395         return ret;
4396 }
4397
4398 static int
4399 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4400 {
4401         struct hns3_sfp_speed_cmd *resp;
4402         struct hns3_cmd_desc desc;
4403         int ret;
4404
4405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4406         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4407         ret = hns3_cmd_send(hw, &desc, 1);
4408         if (ret == -EOPNOTSUPP) {
4409                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4410                 return ret;
4411         } else if (ret) {
4412                 hns3_err(hw, "get sfp speed failed %d", ret);
4413                 return ret;
4414         }
4415
4416         *speed = resp->sfp_speed;
4417
4418         return 0;
4419 }
4420
4421 static uint8_t
4422 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4423 {
4424         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4425                 duplex = ETH_LINK_FULL_DUPLEX;
4426
4427         return duplex;
4428 }
4429
4430 static int
4431 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4432 {
4433         struct hns3_mac *mac = &hw->mac;
4434         int ret;
4435
4436         duplex = hns3_check_speed_dup(duplex, speed);
4437         if (mac->link_speed == speed && mac->link_duplex == duplex)
4438                 return 0;
4439
4440         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4441         if (ret)
4442                 return ret;
4443
4444         ret = hns3_port_shaper_update(hw, speed);
4445         if (ret)
4446                 return ret;
4447
4448         mac->link_speed = speed;
4449         mac->link_duplex = duplex;
4450
4451         return 0;
4452 }
4453
4454 static int
4455 hns3_update_fiber_link_info(struct hns3_hw *hw)
4456 {
4457         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4458         uint32_t speed;
4459         int ret;
4460
4461         /* If IMP do not support get SFP/qSFP speed, return directly */
4462         if (!pf->support_sfp_query)
4463                 return 0;
4464
4465         ret = hns3_get_sfp_speed(hw, &speed);
4466         if (ret == -EOPNOTSUPP) {
4467                 pf->support_sfp_query = false;
4468                 return ret;
4469         } else if (ret)
4470                 return ret;
4471
4472         if (speed == ETH_SPEED_NUM_NONE)
4473                 return 0; /* do nothing if no SFP */
4474
4475         /* Config full duplex for SFP */
4476         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4477 }
4478
4479 static void
4480 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4481 {
4482         struct hns3_phy_params_bd0_cmd *req;
4483
4484         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4485         mac->link_speed = rte_le_to_cpu_32(req->speed);
4486         mac->link_duplex = hns3_get_bit(req->duplex,
4487                                            HNS3_PHY_DUPLEX_CFG_B);
4488         mac->link_autoneg = hns3_get_bit(req->autoneg,
4489                                            HNS3_PHY_AUTONEG_CFG_B);
4490         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4491         mac->advertising = rte_le_to_cpu_32(req->advertising);
4492         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4493         mac->support_autoneg = !!(mac->supported_capa &
4494                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4495 }
4496
4497 static int
4498 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4499 {
4500         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4501         uint16_t i;
4502         int ret;
4503
4504         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4505                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4506                                           true);
4507                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4508         }
4509         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4510
4511         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4512         if (ret) {
4513                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4514                 return ret;
4515         }
4516
4517         hns3_parse_phy_params(desc, mac);
4518
4519         return 0;
4520 }
4521
4522 static int
4523 hns3_update_phy_link_info(struct hns3_hw *hw)
4524 {
4525         struct hns3_mac *mac = &hw->mac;
4526         struct hns3_mac mac_info;
4527         int ret;
4528
4529         memset(&mac_info, 0, sizeof(struct hns3_mac));
4530         ret = hns3_get_phy_params(hw, &mac_info);
4531         if (ret)
4532                 return ret;
4533
4534         if (mac_info.link_speed != mac->link_speed) {
4535                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4536                 if (ret)
4537                         return ret;
4538         }
4539
4540         mac->link_speed = mac_info.link_speed;
4541         mac->link_duplex = mac_info.link_duplex;
4542         mac->link_autoneg = mac_info.link_autoneg;
4543         mac->supported_capa = mac_info.supported_capa;
4544         mac->advertising = mac_info.advertising;
4545         mac->lp_advertising = mac_info.lp_advertising;
4546         mac->support_autoneg = mac_info.support_autoneg;
4547
4548         return 0;
4549 }
4550
4551 static int
4552 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4553 {
4554         struct hns3_adapter *hns = eth_dev->data->dev_private;
4555         struct hns3_hw *hw = &hns->hw;
4556         int ret = 0;
4557
4558         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4559                 ret = hns3_update_phy_link_info(hw);
4560         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4561                 ret = hns3_update_fiber_link_info(hw);
4562
4563         return ret;
4564 }
4565
4566 static int
4567 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4568 {
4569         struct hns3_config_mac_mode_cmd *req;
4570         struct hns3_cmd_desc desc;
4571         uint32_t loop_en = 0;
4572         uint8_t val = 0;
4573         int ret;
4574
4575         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4576
4577         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4578         if (enable)
4579                 val = 1;
4580         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4581         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4582         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4583         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4584         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4585         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4586         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4587         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4588         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4589         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4590
4591         /*
4592          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4593          * when receiving frames. Otherwise, CRC will be stripped.
4594          */
4595         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4596                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4597         else
4598                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4599         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4600         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4601         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4602         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4603
4604         ret = hns3_cmd_send(hw, &desc, 1);
4605         if (ret)
4606                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4607
4608         return ret;
4609 }
4610
4611 static int
4612 hns3_get_mac_link_status(struct hns3_hw *hw)
4613 {
4614         struct hns3_link_status_cmd *req;
4615         struct hns3_cmd_desc desc;
4616         int link_status;
4617         int ret;
4618
4619         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4620         ret = hns3_cmd_send(hw, &desc, 1);
4621         if (ret) {
4622                 hns3_err(hw, "get link status cmd failed %d", ret);
4623                 return ETH_LINK_DOWN;
4624         }
4625
4626         req = (struct hns3_link_status_cmd *)desc.data;
4627         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4628
4629         return !!link_status;
4630 }
4631
4632 static bool
4633 hns3_update_link_status(struct hns3_hw *hw)
4634 {
4635         int state;
4636
4637         state = hns3_get_mac_link_status(hw);
4638         if (state != hw->mac.link_status) {
4639                 hw->mac.link_status = state;
4640                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4641                 return true;
4642         }
4643
4644         return false;
4645 }
4646
4647 /*
4648  * Current, the PF driver get link status by two ways:
4649  * 1) Periodic polling in the intr thread context, driver call
4650  *    hns3_update_link_status to update link status.
4651  * 2) Firmware report async interrupt, driver process the event in the intr
4652  *    thread context, and call hns3_update_link_status to update link status.
4653  *
4654  * If detect link status changed, driver need report LSE. One method is add the
4655  * report LSE logic in hns3_update_link_status.
4656  *
4657  * But the PF driver ops(link_update) also call hns3_update_link_status to
4658  * update link status.
4659  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4660  * bonding application.
4661  *
4662  * So add the one new API which used only in intr thread context.
4663  */
4664 void
4665 hns3_update_link_status_and_event(struct hns3_hw *hw)
4666 {
4667         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4668         bool changed = hns3_update_link_status(hw);
4669         if (changed)
4670                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4671 }
4672
4673 static void
4674 hns3_service_handler(void *param)
4675 {
4676         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4677         struct hns3_adapter *hns = eth_dev->data->dev_private;
4678         struct hns3_hw *hw = &hns->hw;
4679
4680         if (!hns3_is_reset_pending(hns)) {
4681                 hns3_update_link_status_and_event(hw);
4682                 hns3_update_link_info(eth_dev);
4683         } else {
4684                 hns3_warn(hw, "Cancel the query when reset is pending");
4685         }
4686
4687         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4688 }
4689
4690 static int
4691 hns3_init_hardware(struct hns3_adapter *hns)
4692 {
4693         struct hns3_hw *hw = &hns->hw;
4694         int ret;
4695
4696         ret = hns3_map_tqp(hw);
4697         if (ret) {
4698                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4699                 return ret;
4700         }
4701
4702         ret = hns3_init_umv_space(hw);
4703         if (ret) {
4704                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4705                 return ret;
4706         }
4707
4708         ret = hns3_mac_init(hw);
4709         if (ret) {
4710                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4711                 goto err_mac_init;
4712         }
4713
4714         ret = hns3_init_mgr_tbl(hw);
4715         if (ret) {
4716                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4717                 goto err_mac_init;
4718         }
4719
4720         ret = hns3_promisc_init(hw);
4721         if (ret) {
4722                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4723                              ret);
4724                 goto err_mac_init;
4725         }
4726
4727         ret = hns3_init_vlan_config(hns);
4728         if (ret) {
4729                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4730                 goto err_mac_init;
4731         }
4732
4733         ret = hns3_dcb_init(hw);
4734         if (ret) {
4735                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4736                 goto err_mac_init;
4737         }
4738
4739         ret = hns3_init_fd_config(hns);
4740         if (ret) {
4741                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4742                 goto err_mac_init;
4743         }
4744
4745         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4746         if (ret) {
4747                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4748                 goto err_mac_init;
4749         }
4750
4751         ret = hns3_config_gro(hw, false);
4752         if (ret) {
4753                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4754                 goto err_mac_init;
4755         }
4756
4757         /*
4758          * In the initialization clearing the all hardware mapping relationship
4759          * configurations between queues and interrupt vectors is needed, so
4760          * some error caused by the residual configurations, such as the
4761          * unexpected interrupt, can be avoid.
4762          */
4763         ret = hns3_init_ring_with_vector(hw);
4764         if (ret) {
4765                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4766                 goto err_mac_init;
4767         }
4768
4769         /*
4770          * Requiring firmware to enable some features, driver can
4771          * still work without it.
4772          */
4773         ret = hns3_firmware_compat_config(hw, true);
4774         if (ret)
4775                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4776                              "supported, ret = %d.", ret);
4777
4778         return 0;
4779
4780 err_mac_init:
4781         hns3_uninit_umv_space(hw);
4782         return ret;
4783 }
4784
4785 static int
4786 hns3_clear_hw(struct hns3_hw *hw)
4787 {
4788         struct hns3_cmd_desc desc;
4789         int ret;
4790
4791         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4792
4793         ret = hns3_cmd_send(hw, &desc, 1);
4794         if (ret && ret != -EOPNOTSUPP)
4795                 return ret;
4796
4797         return 0;
4798 }
4799
4800 static void
4801 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4802 {
4803         uint32_t val;
4804
4805         /*
4806          * The new firmware support report more hardware error types by
4807          * msix mode. These errors are defined as RAS errors in hardware
4808          * and belong to a different type from the MSI-x errors processed
4809          * by the network driver.
4810          *
4811          * Network driver should open the new error report on initialition
4812          */
4813         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4814         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4815         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4816 }
4817
4818 static int
4819 hns3_init_pf(struct rte_eth_dev *eth_dev)
4820 {
4821         struct rte_device *dev = eth_dev->device;
4822         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4823         struct hns3_adapter *hns = eth_dev->data->dev_private;
4824         struct hns3_hw *hw = &hns->hw;
4825         int ret;
4826
4827         PMD_INIT_FUNC_TRACE();
4828
4829         /* Get hardware io base address from pcie BAR2 IO space */
4830         hw->io_base = pci_dev->mem_resource[2].addr;
4831
4832         /* Firmware command queue initialize */
4833         ret = hns3_cmd_init_queue(hw);
4834         if (ret) {
4835                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4836                 goto err_cmd_init_queue;
4837         }
4838
4839         hns3_clear_all_event_cause(hw);
4840
4841         /* Firmware command initialize */
4842         ret = hns3_cmd_init(hw);
4843         if (ret) {
4844                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4845                 goto err_cmd_init;
4846         }
4847
4848         /*
4849          * To ensure that the hardware environment is clean during
4850          * initialization, the driver actively clear the hardware environment
4851          * during initialization, including PF and corresponding VFs' vlan, mac,
4852          * flow table configurations, etc.
4853          */
4854         ret = hns3_clear_hw(hw);
4855         if (ret) {
4856                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4857                 goto err_cmd_init;
4858         }
4859
4860         /* Hardware statistics of imissed registers cleared. */
4861         ret = hns3_update_imissed_stats(hw, true);
4862         if (ret) {
4863                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4864                 return ret;
4865         }
4866
4867         hns3_config_all_msix_error(hw, true);
4868
4869         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4870                                          hns3_interrupt_handler,
4871                                          eth_dev);
4872         if (ret) {
4873                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4874                 goto err_intr_callback_register;
4875         }
4876
4877         /* Enable interrupt */
4878         rte_intr_enable(&pci_dev->intr_handle);
4879         hns3_pf_enable_irq0(hw);
4880
4881         /* Get configuration */
4882         ret = hns3_get_configuration(hw);
4883         if (ret) {
4884                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4885                 goto err_get_config;
4886         }
4887
4888         ret = hns3_tqp_stats_init(hw);
4889         if (ret)
4890                 goto err_get_config;
4891
4892         ret = hns3_init_hardware(hns);
4893         if (ret) {
4894                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4895                 goto err_init_hw;
4896         }
4897
4898         /* Initialize flow director filter list & hash */
4899         ret = hns3_fdir_filter_init(hns);
4900         if (ret) {
4901                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4902                 goto err_fdir;
4903         }
4904
4905         hns3_rss_set_default_args(hw);
4906
4907         ret = hns3_enable_hw_error_intr(hns, true);
4908         if (ret) {
4909                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4910                              ret);
4911                 goto err_enable_intr;
4912         }
4913
4914         hns3_tm_conf_init(eth_dev);
4915
4916         return 0;
4917
4918 err_enable_intr:
4919         hns3_fdir_filter_uninit(hns);
4920 err_fdir:
4921         (void)hns3_firmware_compat_config(hw, false);
4922         hns3_uninit_umv_space(hw);
4923 err_init_hw:
4924         hns3_tqp_stats_uninit(hw);
4925 err_get_config:
4926         hns3_pf_disable_irq0(hw);
4927         rte_intr_disable(&pci_dev->intr_handle);
4928         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4929                              eth_dev);
4930 err_intr_callback_register:
4931 err_cmd_init:
4932         hns3_cmd_uninit(hw);
4933         hns3_cmd_destroy_queue(hw);
4934 err_cmd_init_queue:
4935         hw->io_base = NULL;
4936
4937         return ret;
4938 }
4939
4940 static void
4941 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4942 {
4943         struct hns3_adapter *hns = eth_dev->data->dev_private;
4944         struct rte_device *dev = eth_dev->device;
4945         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4946         struct hns3_hw *hw = &hns->hw;
4947
4948         PMD_INIT_FUNC_TRACE();
4949
4950         hns3_tm_conf_uninit(eth_dev);
4951         hns3_enable_hw_error_intr(hns, false);
4952         hns3_rss_uninit(hns);
4953         (void)hns3_config_gro(hw, false);
4954         hns3_promisc_uninit(hw);
4955         hns3_fdir_filter_uninit(hns);
4956         (void)hns3_firmware_compat_config(hw, false);
4957         hns3_uninit_umv_space(hw);
4958         hns3_tqp_stats_uninit(hw);
4959         hns3_pf_disable_irq0(hw);
4960         rte_intr_disable(&pci_dev->intr_handle);
4961         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4962                              eth_dev);
4963         hns3_config_all_msix_error(hw, false);
4964         hns3_cmd_uninit(hw);
4965         hns3_cmd_destroy_queue(hw);
4966         hw->io_base = NULL;
4967 }
4968
4969 static int
4970 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4971 {
4972         struct hns3_hw *hw = &hns->hw;
4973         int ret;
4974
4975         ret = hns3_dcb_cfg_update(hns);
4976         if (ret)
4977                 return ret;
4978
4979         /*
4980          * The hns3_dcb_cfg_update may configure TM module, so
4981          * hns3_tm_conf_update must called later.
4982          */
4983         ret = hns3_tm_conf_update(hw);
4984         if (ret) {
4985                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4986                 return ret;
4987         }
4988
4989         hns3_enable_rxd_adv_layout(hw);
4990
4991         ret = hns3_init_queues(hns, reset_queue);
4992         if (ret) {
4993                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4994                 return ret;
4995         }
4996
4997         ret = hns3_cfg_mac_mode(hw, true);
4998         if (ret) {
4999                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5000                 goto err_config_mac_mode;
5001         }
5002         return 0;
5003
5004 err_config_mac_mode:
5005         hns3_dev_release_mbufs(hns);
5006         /*
5007          * Here is exception handling, hns3_reset_all_tqps will have the
5008          * corresponding error message if it is handled incorrectly, so it is
5009          * not necessary to check hns3_reset_all_tqps return value, here keep
5010          * ret as the error code causing the exception.
5011          */
5012         (void)hns3_reset_all_tqps(hns);
5013         return ret;
5014 }
5015
5016 static int
5017 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5018 {
5019         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5020         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5021         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5023         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5024         uint32_t intr_vector;
5025         uint16_t q_id;
5026         int ret;
5027
5028         /*
5029          * hns3 needs a separate interrupt to be used as event interrupt which
5030          * could not be shared with task queue pair, so KERNEL drivers need
5031          * support multiple interrupt vectors.
5032          */
5033         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5034             !rte_intr_cap_multiple(intr_handle))
5035                 return 0;
5036
5037         rte_intr_disable(intr_handle);
5038         intr_vector = hw->used_rx_queues;
5039         /* creates event fd for each intr vector when MSIX is used */
5040         if (rte_intr_efd_enable(intr_handle, intr_vector))
5041                 return -EINVAL;
5042
5043         if (intr_handle->intr_vec == NULL) {
5044                 intr_handle->intr_vec =
5045                         rte_zmalloc("intr_vec",
5046                                     hw->used_rx_queues * sizeof(int), 0);
5047                 if (intr_handle->intr_vec == NULL) {
5048                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5049                                         hw->used_rx_queues);
5050                         ret = -ENOMEM;
5051                         goto alloc_intr_vec_error;
5052                 }
5053         }
5054
5055         if (rte_intr_allow_others(intr_handle)) {
5056                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5057                 base = RTE_INTR_VEC_RXTX_OFFSET;
5058         }
5059
5060         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5061                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5062                                                  HNS3_RING_TYPE_RX, q_id);
5063                 if (ret)
5064                         goto bind_vector_error;
5065                 intr_handle->intr_vec[q_id] = vec;
5066                 /*
5067                  * If there are not enough efds (e.g. not enough interrupt),
5068                  * remaining queues will be bond to the last interrupt.
5069                  */
5070                 if (vec < base + intr_handle->nb_efd - 1)
5071                         vec++;
5072         }
5073         rte_intr_enable(intr_handle);
5074         return 0;
5075
5076 bind_vector_error:
5077         rte_free(intr_handle->intr_vec);
5078         intr_handle->intr_vec = NULL;
5079 alloc_intr_vec_error:
5080         rte_intr_efd_disable(intr_handle);
5081         return ret;
5082 }
5083
5084 static int
5085 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5086 {
5087         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5088         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5089         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5090         uint16_t q_id;
5091         int ret;
5092
5093         if (dev->data->dev_conf.intr_conf.rxq == 0)
5094                 return 0;
5095
5096         if (rte_intr_dp_is_en(intr_handle)) {
5097                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5098                         ret = hns3_bind_ring_with_vector(hw,
5099                                         intr_handle->intr_vec[q_id], true,
5100                                         HNS3_RING_TYPE_RX, q_id);
5101                         if (ret)
5102                                 return ret;
5103                 }
5104         }
5105
5106         return 0;
5107 }
5108
5109 static void
5110 hns3_restore_filter(struct rte_eth_dev *dev)
5111 {
5112         hns3_restore_rss_filter(dev);
5113 }
5114
5115 static int
5116 hns3_dev_start(struct rte_eth_dev *dev)
5117 {
5118         struct hns3_adapter *hns = dev->data->dev_private;
5119         struct hns3_hw *hw = &hns->hw;
5120         int ret;
5121
5122         PMD_INIT_FUNC_TRACE();
5123         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5124                 return -EBUSY;
5125
5126         rte_spinlock_lock(&hw->lock);
5127         hw->adapter_state = HNS3_NIC_STARTING;
5128
5129         ret = hns3_do_start(hns, true);
5130         if (ret) {
5131                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5132                 rte_spinlock_unlock(&hw->lock);
5133                 return ret;
5134         }
5135         ret = hns3_map_rx_interrupt(dev);
5136         if (ret) {
5137                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5138                 rte_spinlock_unlock(&hw->lock);
5139                 return ret;
5140         }
5141
5142         /*
5143          * There are three register used to control the status of a TQP
5144          * (contains a pair of Tx queue and Rx queue) in the new version network
5145          * engine. One is used to control the enabling of Tx queue, the other is
5146          * used to control the enabling of Rx queue, and the last is the master
5147          * switch used to control the enabling of the tqp. The Tx register and
5148          * TQP register must be enabled at the same time to enable a Tx queue.
5149          * The same applies to the Rx queue. For the older network engine, this
5150          * function only refresh the enabled flag, and it is used to update the
5151          * status of queue in the dpdk framework.
5152          */
5153         ret = hns3_start_all_txqs(dev);
5154         if (ret) {
5155                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5156                 rte_spinlock_unlock(&hw->lock);
5157                 return ret;
5158         }
5159
5160         ret = hns3_start_all_rxqs(dev);
5161         if (ret) {
5162                 hns3_stop_all_txqs(dev);
5163                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5164                 rte_spinlock_unlock(&hw->lock);
5165                 return ret;
5166         }
5167
5168         hw->adapter_state = HNS3_NIC_STARTED;
5169         rte_spinlock_unlock(&hw->lock);
5170
5171         hns3_rx_scattered_calc(dev);
5172         hns3_set_rxtx_function(dev);
5173         hns3_mp_req_start_rxtx(dev);
5174         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5175
5176         hns3_restore_filter(dev);
5177
5178         /* Enable interrupt of all rx queues before enabling queues */
5179         hns3_dev_all_rx_queue_intr_enable(hw, true);
5180
5181         /*
5182          * After finished the initialization, enable tqps to receive/transmit
5183          * packets and refresh all queue status.
5184          */
5185         hns3_start_tqps(hw);
5186
5187         hns3_tm_dev_start_proc(hw);
5188
5189         hns3_info(hw, "hns3 dev start successful!");
5190         return 0;
5191 }
5192
5193 static int
5194 hns3_do_stop(struct hns3_adapter *hns)
5195 {
5196         struct hns3_hw *hw = &hns->hw;
5197         int ret;
5198
5199         ret = hns3_cfg_mac_mode(hw, false);
5200         if (ret)
5201                 return ret;
5202         hw->mac.link_status = ETH_LINK_DOWN;
5203
5204         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5205                 hns3_configure_all_mac_addr(hns, true);
5206                 ret = hns3_reset_all_tqps(hns);
5207                 if (ret) {
5208                         hns3_err(hw, "failed to reset all queues ret = %d.",
5209                                  ret);
5210                         return ret;
5211                 }
5212         }
5213         hw->mac.default_addr_setted = false;
5214         return 0;
5215 }
5216
5217 static void
5218 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5219 {
5220         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5221         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5222         struct hns3_adapter *hns = dev->data->dev_private;
5223         struct hns3_hw *hw = &hns->hw;
5224         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5225         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5226         uint16_t q_id;
5227
5228         if (dev->data->dev_conf.intr_conf.rxq == 0)
5229                 return;
5230
5231         /* unmap the ring with vector */
5232         if (rte_intr_allow_others(intr_handle)) {
5233                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5234                 base = RTE_INTR_VEC_RXTX_OFFSET;
5235         }
5236         if (rte_intr_dp_is_en(intr_handle)) {
5237                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5238                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5239                                                          HNS3_RING_TYPE_RX,
5240                                                          q_id);
5241                         if (vec < base + intr_handle->nb_efd - 1)
5242                                 vec++;
5243                 }
5244         }
5245         /* Clean datapath event and queue/vec mapping */
5246         rte_intr_efd_disable(intr_handle);
5247         if (intr_handle->intr_vec) {
5248                 rte_free(intr_handle->intr_vec);
5249                 intr_handle->intr_vec = NULL;
5250         }
5251 }
5252
5253 static int
5254 hns3_dev_stop(struct rte_eth_dev *dev)
5255 {
5256         struct hns3_adapter *hns = dev->data->dev_private;
5257         struct hns3_hw *hw = &hns->hw;
5258
5259         PMD_INIT_FUNC_TRACE();
5260         dev->data->dev_started = 0;
5261
5262         hw->adapter_state = HNS3_NIC_STOPPING;
5263         hns3_set_rxtx_function(dev);
5264         rte_wmb();
5265         /* Disable datapath on secondary process. */
5266         hns3_mp_req_stop_rxtx(dev);
5267         /* Prevent crashes when queues are still in use. */
5268         rte_delay_ms(hw->tqps_num);
5269
5270         rte_spinlock_lock(&hw->lock);
5271         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5272                 hns3_tm_dev_stop_proc(hw);
5273                 hns3_stop_tqps(hw);
5274                 hns3_do_stop(hns);
5275                 hns3_unmap_rx_interrupt(dev);
5276                 hns3_dev_release_mbufs(hns);
5277                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5278         }
5279         hns3_rx_scattered_reset(dev);
5280         rte_eal_alarm_cancel(hns3_service_handler, dev);
5281         rte_spinlock_unlock(&hw->lock);
5282
5283         return 0;
5284 }
5285
5286 static int
5287 hns3_dev_close(struct rte_eth_dev *eth_dev)
5288 {
5289         struct hns3_adapter *hns = eth_dev->data->dev_private;
5290         struct hns3_hw *hw = &hns->hw;
5291         int ret = 0;
5292
5293         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5294                 rte_free(eth_dev->process_private);
5295                 eth_dev->process_private = NULL;
5296                 return 0;
5297         }
5298
5299         if (hw->adapter_state == HNS3_NIC_STARTED)
5300                 ret = hns3_dev_stop(eth_dev);
5301
5302         hw->adapter_state = HNS3_NIC_CLOSING;
5303         hns3_reset_abort(hns);
5304         hw->adapter_state = HNS3_NIC_CLOSED;
5305
5306         hns3_configure_all_mc_mac_addr(hns, true);
5307         hns3_remove_all_vlan_table(hns);
5308         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5309         hns3_uninit_pf(eth_dev);
5310         hns3_free_all_queues(eth_dev);
5311         rte_free(hw->reset.wait_data);
5312         rte_free(eth_dev->process_private);
5313         eth_dev->process_private = NULL;
5314         hns3_mp_uninit_primary();
5315         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5316
5317         return ret;
5318 }
5319
5320 static int
5321 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5322 {
5323         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5325
5326         fc_conf->pause_time = pf->pause_time;
5327
5328         /* return fc current mode */
5329         switch (hw->current_mode) {
5330         case HNS3_FC_FULL:
5331                 fc_conf->mode = RTE_FC_FULL;
5332                 break;
5333         case HNS3_FC_TX_PAUSE:
5334                 fc_conf->mode = RTE_FC_TX_PAUSE;
5335                 break;
5336         case HNS3_FC_RX_PAUSE:
5337                 fc_conf->mode = RTE_FC_RX_PAUSE;
5338                 break;
5339         case HNS3_FC_NONE:
5340         default:
5341                 fc_conf->mode = RTE_FC_NONE;
5342                 break;
5343         }
5344
5345         return 0;
5346 }
5347
5348 static void
5349 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5350 {
5351         switch (mode) {
5352         case RTE_FC_NONE:
5353                 hw->requested_mode = HNS3_FC_NONE;
5354                 break;
5355         case RTE_FC_RX_PAUSE:
5356                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5357                 break;
5358         case RTE_FC_TX_PAUSE:
5359                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5360                 break;
5361         case RTE_FC_FULL:
5362                 hw->requested_mode = HNS3_FC_FULL;
5363                 break;
5364         default:
5365                 hw->requested_mode = HNS3_FC_NONE;
5366                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5367                           "configured to RTE_FC_NONE", mode);
5368                 break;
5369         }
5370 }
5371
5372 static int
5373 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5374 {
5375         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5377         int ret;
5378
5379         if (fc_conf->high_water || fc_conf->low_water ||
5380             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5381                 hns3_err(hw, "Unsupported flow control settings specified, "
5382                          "high_water(%u), low_water(%u), send_xon(%u) and "
5383                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5384                          fc_conf->high_water, fc_conf->low_water,
5385                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5386                 return -EINVAL;
5387         }
5388         if (fc_conf->autoneg) {
5389                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5390                 return -EINVAL;
5391         }
5392         if (!fc_conf->pause_time) {
5393                 hns3_err(hw, "Invalid pause time %u setting.",
5394                          fc_conf->pause_time);
5395                 return -EINVAL;
5396         }
5397
5398         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5399             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5400                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5401                          "current_fc_status = %d", hw->current_fc_status);
5402                 return -EOPNOTSUPP;
5403         }
5404
5405         hns3_get_fc_mode(hw, fc_conf->mode);
5406         if (hw->requested_mode == hw->current_mode &&
5407             pf->pause_time == fc_conf->pause_time)
5408                 return 0;
5409
5410         rte_spinlock_lock(&hw->lock);
5411         ret = hns3_fc_enable(dev, fc_conf);
5412         rte_spinlock_unlock(&hw->lock);
5413
5414         return ret;
5415 }
5416
5417 static int
5418 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5419                             struct rte_eth_pfc_conf *pfc_conf)
5420 {
5421         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5423         uint8_t priority;
5424         int ret;
5425
5426         if (!hns3_dev_dcb_supported(hw)) {
5427                 hns3_err(hw, "This port does not support dcb configurations.");
5428                 return -EOPNOTSUPP;
5429         }
5430
5431         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5432             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5433                 hns3_err(hw, "Unsupported flow control settings specified, "
5434                          "high_water(%u), low_water(%u), send_xon(%u) and "
5435                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5436                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5437                          pfc_conf->fc.send_xon,
5438                          pfc_conf->fc.mac_ctrl_frame_fwd);
5439                 return -EINVAL;
5440         }
5441         if (pfc_conf->fc.autoneg) {
5442                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5443                 return -EINVAL;
5444         }
5445         if (pfc_conf->fc.pause_time == 0) {
5446                 hns3_err(hw, "Invalid pause time %u setting.",
5447                          pfc_conf->fc.pause_time);
5448                 return -EINVAL;
5449         }
5450
5451         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5452             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5453                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5454                              "current_fc_status = %d", hw->current_fc_status);
5455                 return -EOPNOTSUPP;
5456         }
5457
5458         priority = pfc_conf->priority;
5459         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5460         if (hw->dcb_info.pfc_en & BIT(priority) &&
5461             hw->requested_mode == hw->current_mode &&
5462             pfc_conf->fc.pause_time == pf->pause_time)
5463                 return 0;
5464
5465         rte_spinlock_lock(&hw->lock);
5466         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5467         rte_spinlock_unlock(&hw->lock);
5468
5469         return ret;
5470 }
5471
5472 static int
5473 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5474 {
5475         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5476         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5478         int i;
5479
5480         rte_spinlock_lock(&hw->lock);
5481         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5482                 dcb_info->nb_tcs = pf->local_max_tc;
5483         else
5484                 dcb_info->nb_tcs = 1;
5485
5486         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5487                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5488         for (i = 0; i < dcb_info->nb_tcs; i++)
5489                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5490
5491         for (i = 0; i < hw->num_tc; i++) {
5492                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5493                 dcb_info->tc_queue.tc_txq[0][i].base =
5494                                                 hw->tc_queue[i].tqp_offset;
5495                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5496                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5497                                                 hw->tc_queue[i].tqp_count;
5498         }
5499         rte_spinlock_unlock(&hw->lock);
5500
5501         return 0;
5502 }
5503
5504 static int
5505 hns3_reinit_dev(struct hns3_adapter *hns)
5506 {
5507         struct hns3_hw *hw = &hns->hw;
5508         int ret;
5509
5510         ret = hns3_cmd_init(hw);
5511         if (ret) {
5512                 hns3_err(hw, "Failed to init cmd: %d", ret);
5513                 return ret;
5514         }
5515
5516         ret = hns3_reset_all_tqps(hns);
5517         if (ret) {
5518                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5519                 return ret;
5520         }
5521
5522         ret = hns3_init_hardware(hns);
5523         if (ret) {
5524                 hns3_err(hw, "Failed to init hardware: %d", ret);
5525                 return ret;
5526         }
5527
5528         ret = hns3_enable_hw_error_intr(hns, true);
5529         if (ret) {
5530                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5531                              ret);
5532                 return ret;
5533         }
5534         hns3_info(hw, "Reset done, driver initialization finished.");
5535
5536         return 0;
5537 }
5538
5539 static bool
5540 is_pf_reset_done(struct hns3_hw *hw)
5541 {
5542         uint32_t val, reg, reg_bit;
5543
5544         switch (hw->reset.level) {
5545         case HNS3_IMP_RESET:
5546                 reg = HNS3_GLOBAL_RESET_REG;
5547                 reg_bit = HNS3_IMP_RESET_BIT;
5548                 break;
5549         case HNS3_GLOBAL_RESET:
5550                 reg = HNS3_GLOBAL_RESET_REG;
5551                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5552                 break;
5553         case HNS3_FUNC_RESET:
5554                 reg = HNS3_FUN_RST_ING;
5555                 reg_bit = HNS3_FUN_RST_ING_B;
5556                 break;
5557         case HNS3_FLR_RESET:
5558         default:
5559                 hns3_err(hw, "Wait for unsupported reset level: %d",
5560                          hw->reset.level);
5561                 return true;
5562         }
5563         val = hns3_read_dev(hw, reg);
5564         if (hns3_get_bit(val, reg_bit))
5565                 return false;
5566         else
5567                 return true;
5568 }
5569
5570 bool
5571 hns3_is_reset_pending(struct hns3_adapter *hns)
5572 {
5573         struct hns3_hw *hw = &hns->hw;
5574         enum hns3_reset_level reset;
5575
5576         hns3_check_event_cause(hns, NULL);
5577         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5578         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5579                 hns3_warn(hw, "High level reset %d is pending", reset);
5580                 return true;
5581         }
5582         reset = hns3_get_reset_level(hns, &hw->reset.request);
5583         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5584                 hns3_warn(hw, "High level reset %d is request", reset);
5585                 return true;
5586         }
5587         return false;
5588 }
5589
5590 static int
5591 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5592 {
5593         struct hns3_hw *hw = &hns->hw;
5594         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5595         struct timeval tv;
5596
5597         if (wait_data->result == HNS3_WAIT_SUCCESS)
5598                 return 0;
5599         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5600                 gettimeofday(&tv, NULL);
5601                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5602                           tv.tv_sec, tv.tv_usec);
5603                 return -ETIME;
5604         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5605                 return -EAGAIN;
5606
5607         wait_data->hns = hns;
5608         wait_data->check_completion = is_pf_reset_done;
5609         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5610                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5611         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5612         wait_data->count = HNS3_RESET_WAIT_CNT;
5613         wait_data->result = HNS3_WAIT_REQUEST;
5614         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5615         return -EAGAIN;
5616 }
5617
5618 static int
5619 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5620 {
5621         struct hns3_cmd_desc desc;
5622         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5623
5624         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5625         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5626         req->fun_reset_vfid = func_id;
5627
5628         return hns3_cmd_send(hw, &desc, 1);
5629 }
5630
5631 static int
5632 hns3_imp_reset_cmd(struct hns3_hw *hw)
5633 {
5634         struct hns3_cmd_desc desc;
5635
5636         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5637         desc.data[0] = 0xeedd;
5638
5639         return hns3_cmd_send(hw, &desc, 1);
5640 }
5641
5642 static void
5643 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5644 {
5645         struct hns3_hw *hw = &hns->hw;
5646         struct timeval tv;
5647         uint32_t val;
5648
5649         gettimeofday(&tv, NULL);
5650         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5651             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5652                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5653                           tv.tv_sec, tv.tv_usec);
5654                 return;
5655         }
5656
5657         switch (reset_level) {
5658         case HNS3_IMP_RESET:
5659                 hns3_imp_reset_cmd(hw);
5660                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5661                           tv.tv_sec, tv.tv_usec);
5662                 break;
5663         case HNS3_GLOBAL_RESET:
5664                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5665                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5666                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5667                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5668                           tv.tv_sec, tv.tv_usec);
5669                 break;
5670         case HNS3_FUNC_RESET:
5671                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5672                           tv.tv_sec, tv.tv_usec);
5673                 /* schedule again to check later */
5674                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5675                 hns3_schedule_reset(hns);
5676                 break;
5677         default:
5678                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5679                 return;
5680         }
5681         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5682 }
5683
5684 static enum hns3_reset_level
5685 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5686 {
5687         struct hns3_hw *hw = &hns->hw;
5688         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5689
5690         /* Return the highest priority reset level amongst all */
5691         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5692                 reset_level = HNS3_IMP_RESET;
5693         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5694                 reset_level = HNS3_GLOBAL_RESET;
5695         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5696                 reset_level = HNS3_FUNC_RESET;
5697         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5698                 reset_level = HNS3_FLR_RESET;
5699
5700         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5701                 return HNS3_NONE_RESET;
5702
5703         return reset_level;
5704 }
5705
5706 static void
5707 hns3_record_imp_error(struct hns3_adapter *hns)
5708 {
5709         struct hns3_hw *hw = &hns->hw;
5710         uint32_t reg_val;
5711
5712         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5713         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5714                 hns3_warn(hw, "Detected IMP RD poison!");
5715                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5716                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5717                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5718         }
5719
5720         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5721                 hns3_warn(hw, "Detected IMP CMDQ error!");
5722                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5723                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5724                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5725         }
5726 }
5727
5728 static int
5729 hns3_prepare_reset(struct hns3_adapter *hns)
5730 {
5731         struct hns3_hw *hw = &hns->hw;
5732         uint32_t reg_val;
5733         int ret;
5734
5735         switch (hw->reset.level) {
5736         case HNS3_FUNC_RESET:
5737                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5738                 if (ret)
5739                         return ret;
5740
5741                 /*
5742                  * After performaning pf reset, it is not necessary to do the
5743                  * mailbox handling or send any command to firmware, because
5744                  * any mailbox handling or command to firmware is only valid
5745                  * after hns3_cmd_init is called.
5746                  */
5747                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5748                 hw->reset.stats.request_cnt++;
5749                 break;
5750         case HNS3_IMP_RESET:
5751                 hns3_record_imp_error(hns);
5752                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5753                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5754                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5755                 break;
5756         default:
5757                 break;
5758         }
5759         return 0;
5760 }
5761
5762 static int
5763 hns3_set_rst_done(struct hns3_hw *hw)
5764 {
5765         struct hns3_pf_rst_done_cmd *req;
5766         struct hns3_cmd_desc desc;
5767
5768         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5769         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5770         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5771         return hns3_cmd_send(hw, &desc, 1);
5772 }
5773
5774 static int
5775 hns3_stop_service(struct hns3_adapter *hns)
5776 {
5777         struct hns3_hw *hw = &hns->hw;
5778         struct rte_eth_dev *eth_dev;
5779
5780         eth_dev = &rte_eth_devices[hw->data->port_id];
5781         if (hw->adapter_state == HNS3_NIC_STARTED) {
5782                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5783                 hns3_update_link_status_and_event(hw);
5784         }
5785         hw->mac.link_status = ETH_LINK_DOWN;
5786
5787         hns3_set_rxtx_function(eth_dev);
5788         rte_wmb();
5789         /* Disable datapath on secondary process. */
5790         hns3_mp_req_stop_rxtx(eth_dev);
5791         rte_delay_ms(hw->tqps_num);
5792
5793         rte_spinlock_lock(&hw->lock);
5794         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5795             hw->adapter_state == HNS3_NIC_STOPPING) {
5796                 hns3_enable_all_queues(hw, false);
5797                 hns3_do_stop(hns);
5798                 hw->reset.mbuf_deferred_free = true;
5799         } else
5800                 hw->reset.mbuf_deferred_free = false;
5801
5802         /*
5803          * It is cumbersome for hardware to pick-and-choose entries for deletion
5804          * from table space. Hence, for function reset software intervention is
5805          * required to delete the entries
5806          */
5807         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5808                 hns3_configure_all_mc_mac_addr(hns, true);
5809         rte_spinlock_unlock(&hw->lock);
5810
5811         return 0;
5812 }
5813
5814 static int
5815 hns3_start_service(struct hns3_adapter *hns)
5816 {
5817         struct hns3_hw *hw = &hns->hw;
5818         struct rte_eth_dev *eth_dev;
5819
5820         if (hw->reset.level == HNS3_IMP_RESET ||
5821             hw->reset.level == HNS3_GLOBAL_RESET)
5822                 hns3_set_rst_done(hw);
5823         eth_dev = &rte_eth_devices[hw->data->port_id];
5824         hns3_set_rxtx_function(eth_dev);
5825         hns3_mp_req_start_rxtx(eth_dev);
5826         if (hw->adapter_state == HNS3_NIC_STARTED) {
5827                 /*
5828                  * This API parent function already hold the hns3_hw.lock, the
5829                  * hns3_service_handler may report lse, in bonding application
5830                  * it will call driver's ops which may acquire the hns3_hw.lock
5831                  * again, thus lead to deadlock.
5832                  * We defer calls hns3_service_handler to avoid the deadlock.
5833                  */
5834                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5835                                   hns3_service_handler, eth_dev);
5836
5837                 /* Enable interrupt of all rx queues before enabling queues */
5838                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5839                 /*
5840                  * Enable state of each rxq and txq will be recovered after
5841                  * reset, so we need to restore them before enable all tqps;
5842                  */
5843                 hns3_restore_tqp_enable_state(hw);
5844                 /*
5845                  * When finished the initialization, enable queues to receive
5846                  * and transmit packets.
5847                  */
5848                 hns3_enable_all_queues(hw, true);
5849         }
5850
5851         return 0;
5852 }
5853
5854 static int
5855 hns3_restore_conf(struct hns3_adapter *hns)
5856 {
5857         struct hns3_hw *hw = &hns->hw;
5858         int ret;
5859
5860         ret = hns3_configure_all_mac_addr(hns, false);
5861         if (ret)
5862                 return ret;
5863
5864         ret = hns3_configure_all_mc_mac_addr(hns, false);
5865         if (ret)
5866                 goto err_mc_mac;
5867
5868         ret = hns3_dev_promisc_restore(hns);
5869         if (ret)
5870                 goto err_promisc;
5871
5872         ret = hns3_restore_vlan_table(hns);
5873         if (ret)
5874                 goto err_promisc;
5875
5876         ret = hns3_restore_vlan_conf(hns);
5877         if (ret)
5878                 goto err_promisc;
5879
5880         ret = hns3_restore_all_fdir_filter(hns);
5881         if (ret)
5882                 goto err_promisc;
5883
5884         ret = hns3_restore_rx_interrupt(hw);
5885         if (ret)
5886                 goto err_promisc;
5887
5888         ret = hns3_restore_gro_conf(hw);
5889         if (ret)
5890                 goto err_promisc;
5891
5892         ret = hns3_restore_fec(hw);
5893         if (ret)
5894                 goto err_promisc;
5895
5896         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5897                 ret = hns3_do_start(hns, false);
5898                 if (ret)
5899                         goto err_promisc;
5900                 hns3_info(hw, "hns3 dev restart successful!");
5901         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5902                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5903         return 0;
5904
5905 err_promisc:
5906         hns3_configure_all_mc_mac_addr(hns, true);
5907 err_mc_mac:
5908         hns3_configure_all_mac_addr(hns, true);
5909         return ret;
5910 }
5911
5912 static void
5913 hns3_reset_service(void *param)
5914 {
5915         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5916         struct hns3_hw *hw = &hns->hw;
5917         enum hns3_reset_level reset_level;
5918         struct timeval tv_delta;
5919         struct timeval tv_start;
5920         struct timeval tv;
5921         uint64_t msec;
5922         int ret;
5923
5924         /*
5925          * The interrupt is not triggered within the delay time.
5926          * The interrupt may have been lost. It is necessary to handle
5927          * the interrupt to recover from the error.
5928          */
5929         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5930                             SCHEDULE_DEFERRED) {
5931                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5932                                   __ATOMIC_RELAXED);
5933                 hns3_err(hw, "Handling interrupts in delayed tasks");
5934                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5935                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5936                 if (reset_level == HNS3_NONE_RESET) {
5937                         hns3_err(hw, "No reset level is set, try IMP reset");
5938                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5939                 }
5940         }
5941         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5942
5943         /*
5944          * Check if there is any ongoing reset in the hardware. This status can
5945          * be checked from reset_pending. If there is then, we need to wait for
5946          * hardware to complete reset.
5947          *    a. If we are able to figure out in reasonable time that hardware
5948          *       has fully resetted then, we can proceed with driver, client
5949          *       reset.
5950          *    b. else, we can come back later to check this status so re-sched
5951          *       now.
5952          */
5953         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5954         if (reset_level != HNS3_NONE_RESET) {
5955                 gettimeofday(&tv_start, NULL);
5956                 ret = hns3_reset_process(hns, reset_level);
5957                 gettimeofday(&tv, NULL);
5958                 timersub(&tv, &tv_start, &tv_delta);
5959                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5960                        tv_delta.tv_usec / USEC_PER_MSEC;
5961                 if (msec > HNS3_RESET_PROCESS_MS)
5962                         hns3_err(hw, "%d handle long time delta %" PRIx64
5963                                      " ms time=%ld.%.6ld",
5964                                  hw->reset.level, msec,
5965                                  tv.tv_sec, tv.tv_usec);
5966                 if (ret == -EAGAIN)
5967                         return;
5968         }
5969
5970         /* Check if we got any *new* reset requests to be honored */
5971         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5972         if (reset_level != HNS3_NONE_RESET)
5973                 hns3_msix_process(hns, reset_level);
5974 }
5975
5976 static unsigned int
5977 hns3_get_speed_capa_num(uint16_t device_id)
5978 {
5979         unsigned int num;
5980
5981         switch (device_id) {
5982         case HNS3_DEV_ID_25GE:
5983         case HNS3_DEV_ID_25GE_RDMA:
5984                 num = 2;
5985                 break;
5986         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5987         case HNS3_DEV_ID_200G_RDMA:
5988                 num = 1;
5989                 break;
5990         default:
5991                 num = 0;
5992                 break;
5993         }
5994
5995         return num;
5996 }
5997
5998 static int
5999 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6000                         uint16_t device_id)
6001 {
6002         switch (device_id) {
6003         case HNS3_DEV_ID_25GE:
6004         /* fallthrough */
6005         case HNS3_DEV_ID_25GE_RDMA:
6006                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6007                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6008
6009                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6010                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6011                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6012                 break;
6013         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6014                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6015                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6016                 break;
6017         case HNS3_DEV_ID_200G_RDMA:
6018                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6019                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6020                 break;
6021         default:
6022                 return -ENOTSUP;
6023         }
6024
6025         return 0;
6026 }
6027
6028 static int
6029 hns3_fec_get_capability(struct rte_eth_dev *dev,
6030                         struct rte_eth_fec_capa *speed_fec_capa,
6031                         unsigned int num)
6032 {
6033         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6034         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6035         uint16_t device_id = pci_dev->id.device_id;
6036         unsigned int capa_num;
6037         int ret;
6038
6039         capa_num = hns3_get_speed_capa_num(device_id);
6040         if (capa_num == 0) {
6041                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6042                          device_id);
6043                 return -ENOTSUP;
6044         }
6045
6046         if (speed_fec_capa == NULL || num < capa_num)
6047                 return capa_num;
6048
6049         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6050         if (ret)
6051                 return -ENOTSUP;
6052
6053         return capa_num;
6054 }
6055
6056 static int
6057 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6058 {
6059         struct hns3_config_fec_cmd *req;
6060         struct hns3_cmd_desc desc;
6061         int ret;
6062
6063         /*
6064          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6065          * in device of link speed
6066          * below 10 Gbps.
6067          */
6068         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6069                 *state = 0;
6070                 return 0;
6071         }
6072
6073         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6074         req = (struct hns3_config_fec_cmd *)desc.data;
6075         ret = hns3_cmd_send(hw, &desc, 1);
6076         if (ret) {
6077                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6078                          ret);
6079                 return ret;
6080         }
6081
6082         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6083         return 0;
6084 }
6085
6086 static int
6087 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6088 {
6089 #define QUERY_ACTIVE_SPEED      1
6090         struct hns3_sfp_speed_cmd *resp;
6091         uint32_t tmp_fec_capa;
6092         uint8_t auto_state;
6093         struct hns3_cmd_desc desc;
6094         int ret;
6095
6096         /*
6097          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6098          * configured FEC mode is returned.
6099          * If link is up, current FEC mode is returned.
6100          */
6101         if (hw->mac.link_status == ETH_LINK_DOWN) {
6102                 ret = get_current_fec_auto_state(hw, &auto_state);
6103                 if (ret)
6104                         return ret;
6105
6106                 if (auto_state == 0x1) {
6107                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6108                         return 0;
6109                 }
6110         }
6111
6112         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6113         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6114         resp->query_type = QUERY_ACTIVE_SPEED;
6115
6116         ret = hns3_cmd_send(hw, &desc, 1);
6117         if (ret == -EOPNOTSUPP) {
6118                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6119                 return ret;
6120         } else if (ret) {
6121                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6122                 return ret;
6123         }
6124
6125         /*
6126          * FEC mode order defined in hns3 hardware is inconsistend with
6127          * that defined in the ethdev library. So the sequence needs
6128          * to be converted.
6129          */
6130         switch (resp->active_fec) {
6131         case HNS3_HW_FEC_MODE_NOFEC:
6132                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6133                 break;
6134         case HNS3_HW_FEC_MODE_BASER:
6135                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6136                 break;
6137         case HNS3_HW_FEC_MODE_RS:
6138                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6139                 break;
6140         default:
6141                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6142                 break;
6143         }
6144
6145         *fec_capa = tmp_fec_capa;
6146         return 0;
6147 }
6148
6149 static int
6150 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6151 {
6152         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153
6154         return hns3_fec_get_internal(hw, fec_capa);
6155 }
6156
6157 static int
6158 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6159 {
6160         struct hns3_config_fec_cmd *req;
6161         struct hns3_cmd_desc desc;
6162         int ret;
6163
6164         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6165
6166         req = (struct hns3_config_fec_cmd *)desc.data;
6167         switch (mode) {
6168         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6169                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6170                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6171                 break;
6172         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6173                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6174                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6175                 break;
6176         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6177                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6178                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6179                 break;
6180         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6181                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6182                 break;
6183         default:
6184                 return 0;
6185         }
6186         ret = hns3_cmd_send(hw, &desc, 1);
6187         if (ret)
6188                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6189
6190         return ret;
6191 }
6192
6193 static uint32_t
6194 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6195 {
6196         struct hns3_mac *mac = &hw->mac;
6197         uint32_t cur_capa;
6198
6199         switch (mac->link_speed) {
6200         case ETH_SPEED_NUM_10G:
6201                 cur_capa = fec_capa[1].capa;
6202                 break;
6203         case ETH_SPEED_NUM_25G:
6204         case ETH_SPEED_NUM_100G:
6205         case ETH_SPEED_NUM_200G:
6206                 cur_capa = fec_capa[0].capa;
6207                 break;
6208         default:
6209                 cur_capa = 0;
6210                 break;
6211         }
6212
6213         return cur_capa;
6214 }
6215
6216 static bool
6217 is_fec_mode_one_bit_set(uint32_t mode)
6218 {
6219         int cnt = 0;
6220         uint8_t i;
6221
6222         for (i = 0; i < sizeof(mode); i++)
6223                 if (mode >> i & 0x1)
6224                         cnt++;
6225
6226         return cnt == 1 ? true : false;
6227 }
6228
6229 static int
6230 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6231 {
6232 #define FEC_CAPA_NUM 2
6233         struct hns3_adapter *hns = dev->data->dev_private;
6234         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6235         struct hns3_pf *pf = &hns->pf;
6236
6237         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6238         uint32_t cur_capa;
6239         uint32_t num = FEC_CAPA_NUM;
6240         int ret;
6241
6242         ret = hns3_fec_get_capability(dev, fec_capa, num);
6243         if (ret < 0)
6244                 return ret;
6245
6246         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6247         if (!is_fec_mode_one_bit_set(mode))
6248                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6249                              "FEC mode should be only one bit set", mode);
6250
6251         /*
6252          * Check whether the configured mode is within the FEC capability.
6253          * If not, the configured mode will not be supported.
6254          */
6255         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6256         if (!(cur_capa & mode)) {
6257                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6258                 return -EINVAL;
6259         }
6260
6261         ret = hns3_set_fec_hw(hw, mode);
6262         if (ret)
6263                 return ret;
6264
6265         pf->fec_mode = mode;
6266         return 0;
6267 }
6268
6269 static int
6270 hns3_restore_fec(struct hns3_hw *hw)
6271 {
6272         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6273         struct hns3_pf *pf = &hns->pf;
6274         uint32_t mode = pf->fec_mode;
6275         int ret;
6276
6277         ret = hns3_set_fec_hw(hw, mode);
6278         if (ret)
6279                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6280                          mode, ret);
6281
6282         return ret;
6283 }
6284
6285 static int
6286 hns3_query_dev_fec_info(struct hns3_hw *hw)
6287 {
6288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6289         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6290         int ret;
6291
6292         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6293         if (ret)
6294                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6295
6296         return ret;
6297 }
6298
6299 static bool
6300 hns3_optical_module_existed(struct hns3_hw *hw)
6301 {
6302         struct hns3_cmd_desc desc;
6303         bool existed;
6304         int ret;
6305
6306         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6307         ret = hns3_cmd_send(hw, &desc, 1);
6308         if (ret) {
6309                 hns3_err(hw,
6310                          "fail to get optical module exist state, ret = %d.\n",
6311                          ret);
6312                 return false;
6313         }
6314         existed = !!desc.data[0];
6315
6316         return existed;
6317 }
6318
6319 static int
6320 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6321                                 uint32_t len, uint8_t *data)
6322 {
6323 #define HNS3_SFP_INFO_CMD_NUM 6
6324 #define HNS3_SFP_INFO_MAX_LEN \
6325         (HNS3_SFP_INFO_BD0_LEN + \
6326         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6327         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6328         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6329         uint16_t read_len;
6330         uint16_t copy_len;
6331         int ret;
6332         int i;
6333
6334         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6335                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6336                                           true);
6337                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6338                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6339         }
6340
6341         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6342         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6343         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6344         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6345
6346         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6347         if (ret) {
6348                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6349                                 ret);
6350                 return ret;
6351         }
6352
6353         /* The data format in BD0 is different with the others. */
6354         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6355         memcpy(data, sfp_info_bd0->data, copy_len);
6356         read_len = copy_len;
6357
6358         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6359                 if (read_len >= len)
6360                         break;
6361
6362                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6363                 memcpy(data + read_len, desc[i].data, copy_len);
6364                 read_len += copy_len;
6365         }
6366
6367         return (int)read_len;
6368 }
6369
6370 static int
6371 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6372                        struct rte_dev_eeprom_info *info)
6373 {
6374         struct hns3_adapter *hns = dev->data->dev_private;
6375         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6376         uint32_t offset = info->offset;
6377         uint32_t len = info->length;
6378         uint8_t *data = info->data;
6379         uint32_t read_len = 0;
6380
6381         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6382                 return -ENOTSUP;
6383
6384         if (!hns3_optical_module_existed(hw)) {
6385                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6386                 return -EIO;
6387         }
6388
6389         while (read_len < len) {
6390                 int ret;
6391                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6392                                                   len - read_len,
6393                                                   data + read_len);
6394                 if (ret < 0)
6395                         return -EIO;
6396                 read_len += ret;
6397         }
6398
6399         return 0;
6400 }
6401
6402 static int
6403 hns3_get_module_info(struct rte_eth_dev *dev,
6404                      struct rte_eth_dev_module_info *modinfo)
6405 {
6406 #define HNS3_SFF8024_ID_SFP             0x03
6407 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6408 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6409 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6410 #define HNS3_SFF_8636_V1_3              0x03
6411         struct hns3_adapter *hns = dev->data->dev_private;
6412         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6413         struct rte_dev_eeprom_info info;
6414         struct hns3_sfp_type sfp_type;
6415         int ret;
6416
6417         memset(&sfp_type, 0, sizeof(sfp_type));
6418         memset(&info, 0, sizeof(info));
6419         info.data = (uint8_t *)&sfp_type;
6420         info.length = sizeof(sfp_type);
6421         ret = hns3_get_module_eeprom(dev, &info);
6422         if (ret)
6423                 return ret;
6424
6425         switch (sfp_type.type) {
6426         case HNS3_SFF8024_ID_SFP:
6427                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6428                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6429                 break;
6430         case HNS3_SFF8024_ID_QSFP_8438:
6431                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6432                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6433                 break;
6434         case HNS3_SFF8024_ID_QSFP_8436_8636:
6435                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6436                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6437                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6438                 } else {
6439                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6440                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6441                 }
6442                 break;
6443         case HNS3_SFF8024_ID_QSFP28_8636:
6444                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6445                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6446                 break;
6447         default:
6448                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6449                          sfp_type.type, sfp_type.ext_type);
6450                 return -EINVAL;
6451         }
6452
6453         return 0;
6454 }
6455
6456 static const struct eth_dev_ops hns3_eth_dev_ops = {
6457         .dev_configure      = hns3_dev_configure,
6458         .dev_start          = hns3_dev_start,
6459         .dev_stop           = hns3_dev_stop,
6460         .dev_close          = hns3_dev_close,
6461         .promiscuous_enable = hns3_dev_promiscuous_enable,
6462         .promiscuous_disable = hns3_dev_promiscuous_disable,
6463         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6464         .allmulticast_disable = hns3_dev_allmulticast_disable,
6465         .mtu_set            = hns3_dev_mtu_set,
6466         .stats_get          = hns3_stats_get,
6467         .stats_reset        = hns3_stats_reset,
6468         .xstats_get         = hns3_dev_xstats_get,
6469         .xstats_get_names   = hns3_dev_xstats_get_names,
6470         .xstats_reset       = hns3_dev_xstats_reset,
6471         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6472         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6473         .dev_infos_get          = hns3_dev_infos_get,
6474         .fw_version_get         = hns3_fw_version_get,
6475         .rx_queue_setup         = hns3_rx_queue_setup,
6476         .tx_queue_setup         = hns3_tx_queue_setup,
6477         .rx_queue_release       = hns3_dev_rx_queue_release,
6478         .tx_queue_release       = hns3_dev_tx_queue_release,
6479         .rx_queue_start         = hns3_dev_rx_queue_start,
6480         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6481         .tx_queue_start         = hns3_dev_tx_queue_start,
6482         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6483         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6484         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6485         .rxq_info_get           = hns3_rxq_info_get,
6486         .txq_info_get           = hns3_txq_info_get,
6487         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6488         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6489         .flow_ctrl_get          = hns3_flow_ctrl_get,
6490         .flow_ctrl_set          = hns3_flow_ctrl_set,
6491         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6492         .mac_addr_add           = hns3_add_mac_addr,
6493         .mac_addr_remove        = hns3_remove_mac_addr,
6494         .mac_addr_set           = hns3_set_default_mac_addr,
6495         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6496         .link_update            = hns3_dev_link_update,
6497         .rss_hash_update        = hns3_dev_rss_hash_update,
6498         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6499         .reta_update            = hns3_dev_rss_reta_update,
6500         .reta_query             = hns3_dev_rss_reta_query,
6501         .filter_ctrl            = hns3_dev_filter_ctrl,
6502         .vlan_filter_set        = hns3_vlan_filter_set,
6503         .vlan_tpid_set          = hns3_vlan_tpid_set,
6504         .vlan_offload_set       = hns3_vlan_offload_set,
6505         .vlan_pvid_set          = hns3_vlan_pvid_set,
6506         .get_reg                = hns3_get_regs,
6507         .get_module_info        = hns3_get_module_info,
6508         .get_module_eeprom      = hns3_get_module_eeprom,
6509         .get_dcb_info           = hns3_get_dcb_info,
6510         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6511         .fec_get_capability     = hns3_fec_get_capability,
6512         .fec_get                = hns3_fec_get,
6513         .fec_set                = hns3_fec_set,
6514         .tm_ops_get             = hns3_tm_ops_get,
6515         .tx_done_cleanup        = hns3_tx_done_cleanup,
6516 };
6517
6518 static const struct hns3_reset_ops hns3_reset_ops = {
6519         .reset_service       = hns3_reset_service,
6520         .stop_service        = hns3_stop_service,
6521         .prepare_reset       = hns3_prepare_reset,
6522         .wait_hardware_ready = hns3_wait_hardware_ready,
6523         .reinit_dev          = hns3_reinit_dev,
6524         .restore_conf        = hns3_restore_conf,
6525         .start_service       = hns3_start_service,
6526 };
6527
6528 static int
6529 hns3_dev_init(struct rte_eth_dev *eth_dev)
6530 {
6531         struct hns3_adapter *hns = eth_dev->data->dev_private;
6532         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6533         struct rte_ether_addr *eth_addr;
6534         struct hns3_hw *hw = &hns->hw;
6535         int ret;
6536
6537         PMD_INIT_FUNC_TRACE();
6538
6539         eth_dev->process_private = (struct hns3_process_private *)
6540             rte_zmalloc_socket("hns3_filter_list",
6541                                sizeof(struct hns3_process_private),
6542                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6543         if (eth_dev->process_private == NULL) {
6544                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6545                 return -ENOMEM;
6546         }
6547         /* initialize flow filter lists */
6548         hns3_filterlist_init(eth_dev);
6549
6550         hns3_set_rxtx_function(eth_dev);
6551         eth_dev->dev_ops = &hns3_eth_dev_ops;
6552         eth_dev->rx_queue_count = hns3_rx_queue_count;
6553         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6554                 ret = hns3_mp_init_secondary();
6555                 if (ret) {
6556                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6557                                      "process, ret = %d", ret);
6558                         goto err_mp_init_secondary;
6559                 }
6560
6561                 hw->secondary_cnt++;
6562                 return 0;
6563         }
6564
6565         ret = hns3_mp_init_primary();
6566         if (ret) {
6567                 PMD_INIT_LOG(ERR,
6568                              "Failed to init for primary process, ret = %d",
6569                              ret);
6570                 goto err_mp_init_primary;
6571         }
6572
6573         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6574         hns->is_vf = false;
6575         hw->data = eth_dev->data;
6576
6577         /*
6578          * Set default max packet size according to the mtu
6579          * default vale in DPDK frame.
6580          */
6581         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6582
6583         ret = hns3_reset_init(hw);
6584         if (ret)
6585                 goto err_init_reset;
6586         hw->reset.ops = &hns3_reset_ops;
6587
6588         ret = hns3_init_pf(eth_dev);
6589         if (ret) {
6590                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6591                 goto err_init_pf;
6592         }
6593
6594         /* Allocate memory for storing MAC addresses */
6595         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6596                                                sizeof(struct rte_ether_addr) *
6597                                                HNS3_UC_MACADDR_NUM, 0);
6598         if (eth_dev->data->mac_addrs == NULL) {
6599                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6600                              "to store MAC addresses",
6601                              sizeof(struct rte_ether_addr) *
6602                              HNS3_UC_MACADDR_NUM);
6603                 ret = -ENOMEM;
6604                 goto err_rte_zmalloc;
6605         }
6606
6607         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6608         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6609                 rte_eth_random_addr(hw->mac.mac_addr);
6610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6611                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6612                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6613                           "unicast address, using random MAC address %s",
6614                           mac_str);
6615         }
6616         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6617                             &eth_dev->data->mac_addrs[0]);
6618
6619         hw->adapter_state = HNS3_NIC_INITIALIZED;
6620
6621         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6622                             SCHEDULE_PENDING) {
6623                 hns3_err(hw, "Reschedule reset service after dev_init");
6624                 hns3_schedule_reset(hns);
6625         } else {
6626                 /* IMP will wait ready flag before reset */
6627                 hns3_notify_reset_ready(hw, false);
6628         }
6629
6630         hns3_info(hw, "hns3 dev initialization successful!");
6631         return 0;
6632
6633 err_rte_zmalloc:
6634         hns3_uninit_pf(eth_dev);
6635
6636 err_init_pf:
6637         rte_free(hw->reset.wait_data);
6638
6639 err_init_reset:
6640         hns3_mp_uninit_primary();
6641
6642 err_mp_init_primary:
6643 err_mp_init_secondary:
6644         eth_dev->dev_ops = NULL;
6645         eth_dev->rx_pkt_burst = NULL;
6646         eth_dev->tx_pkt_burst = NULL;
6647         eth_dev->tx_pkt_prepare = NULL;
6648         rte_free(eth_dev->process_private);
6649         eth_dev->process_private = NULL;
6650         return ret;
6651 }
6652
6653 static int
6654 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6655 {
6656         struct hns3_adapter *hns = eth_dev->data->dev_private;
6657         struct hns3_hw *hw = &hns->hw;
6658
6659         PMD_INIT_FUNC_TRACE();
6660
6661         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6662                 rte_free(eth_dev->process_private);
6663                 eth_dev->process_private = NULL;
6664                 return 0;
6665         }
6666
6667         if (hw->adapter_state < HNS3_NIC_CLOSING)
6668                 hns3_dev_close(eth_dev);
6669
6670         hw->adapter_state = HNS3_NIC_REMOVED;
6671         return 0;
6672 }
6673
6674 static int
6675 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6676                    struct rte_pci_device *pci_dev)
6677 {
6678         return rte_eth_dev_pci_generic_probe(pci_dev,
6679                                              sizeof(struct hns3_adapter),
6680                                              hns3_dev_init);
6681 }
6682
6683 static int
6684 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6685 {
6686         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6687 }
6688
6689 static const struct rte_pci_id pci_id_hns3_map[] = {
6690         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6691         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6692         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6693         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6694         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6695         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6696         { .vendor_id = 0, }, /* sentinel */
6697 };
6698
6699 static struct rte_pci_driver rte_hns3_pmd = {
6700         .id_table = pci_id_hns3_map,
6701         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6702         .probe = eth_hns3_pci_probe,
6703         .remove = eth_hns3_pci_remove,
6704 };
6705
6706 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6707 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6708 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6709 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6710 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);