drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <rte_ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_INVALID_PVID               0xFFFF
  23
  24 #define HNS3_FILTER_TYPE_VF             0
  25 #define HNS3_FILTER_TYPE_PORT           1
  26 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  27 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  28 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  29 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  30 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  31 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  32                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  33 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  35
  36 /* Reset related Registers */
  37 #define HNS3_GLOBAL_RESET_BIT           0
  38 #define HNS3_CORE_RESET_BIT             1
  39 #define HNS3_IMP_RESET_BIT              2
  40 #define HNS3_FUN_RST_ING_B              0
  41
  42 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  44 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  46
  47 #define HNS3_RESET_WAIT_MS      100
  48 #define HNS3_RESET_WAIT_CNT     200
  49
  50 /* FEC mode order defined in HNS3 hardware */
  51 #define HNS3_HW_FEC_MODE_NOFEC  0
  52 #define HNS3_HW_FEC_MODE_BASER  1
  53 #define HNS3_HW_FEC_MODE_RS     2
  54
  55 enum hns3_evt_cause {
  56         HNS3_VECTOR0_EVENT_RST,
  57         HNS3_VECTOR0_EVENT_MBX,
  58         HNS3_VECTOR0_EVENT_ERR,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  96
  97 static int hns3_add_mc_addr(struct hns3_hw *hw,
  98                             struct rte_ether_addr *mac_addr);
  99 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_restore_fec(struct hns3_hw *hw);
 102 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 103
 104 void hns3_ether_format_addr(char *buf, uint16_t size,
 105                             const struct rte_ether_addr *ether_addr)
 106 {
 107         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 108                 ether_addr->addr_bytes[0],
 109                 ether_addr->addr_bytes[4],
 110                 ether_addr->addr_bytes[5]);
 111 }
 112
 113 static void
 114 hns3_pf_disable_irq0(struct hns3_hw *hw)
 115 {
 116         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 117 }
 118
 119 static void
 120 hns3_pf_enable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 123 }
 124
 125 static enum hns3_evt_cause
 126 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 127 {
 128         struct hns3_hw *hw = &hns->hw;
 129         uint32_t vector0_int_stats;
 130         uint32_t cmdq_src_val;
 131         uint32_t hw_err_src_reg;
 132         uint32_t val;
 133         enum hns3_evt_cause ret;
 134
 135         /* fetch the events from their corresponding regs */
 136         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 137         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 138         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 139
 140         /*
 141          * Assumption: If by any chance reset and mailbox events are reported
 142          * together then we will only process reset event and defer the
 143          * processing of the mailbox events. Since, we would have not cleared
 144          * RX CMDQ event this time we would receive again another interrupt
 145          * from H/W just for the mailbox.
 146          */
 147         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 148                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 149                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 150                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 151                 if (clearval) {
 152                         hw->reset.stats.imp_cnt++;
 153                         hns3_warn(hw, "IMP reset detected, clear reset status");
 154                 } else {
 155                         hns3_schedule_delayed_reset(hns);
 156                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 157                 }
 158
 159                 ret = HNS3_VECTOR0_EVENT_RST;
 160                 goto out;
 161         }
 162
 163         /* Global reset */
 164         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 165                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 166                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 167                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 168                 if (clearval) {
 169                         hw->reset.stats.global_cnt++;
 170                         hns3_warn(hw, "Global reset detected, clear reset status");
 171                 } else {
 172                         hns3_schedule_delayed_reset(hns);
 173                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 174                 }
 175
 176                 ret = HNS3_VECTOR0_EVENT_RST;
 177                 goto out;
 178         }
 179
 180         /* check for vector0 msix event source */
 181         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 182             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 183                 val = vector0_int_stats | hw_err_src_reg;
 184                 ret = HNS3_VECTOR0_EVENT_ERR;
 185                 goto out;
 186         }
 187
 188         /* check for vector0 mailbox(=CMDQ RX) event source */
 189         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 190                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 191                 val = cmdq_src_val;
 192                 ret = HNS3_VECTOR0_EVENT_MBX;
 193                 goto out;
 194         }
 195
 196         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 197                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 198                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 199         val = vector0_int_stats;
 200         ret = HNS3_VECTOR0_EVENT_OTHER;
 201 out:
 202
 203         if (clearval)
 204                 *clearval = val;
 205         return ret;
 206 }
 207
 208 static void
 209 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 210 {
 211         if (event_type == HNS3_VECTOR0_EVENT_RST)
 212                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 213         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 214                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 215 }
 216
 217 static void
 218 hns3_clear_all_event_cause(struct hns3_hw *hw)
 219 {
 220         uint32_t vector0_int_stats;
 221         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 222
 223         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 224                 hns3_warn(hw, "Probe during IMP reset interrupt");
 225
 226         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 227                 hns3_warn(hw, "Probe during Global reset interrupt");
 228
 229         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 230                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 231                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 232                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 233         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 234 }
 235
 236 static void
 237 hns3_interrupt_handler(void *param)
 238 {
 239         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 240         struct hns3_adapter *hns = dev->data->dev_private;
 241         struct hns3_hw *hw = &hns->hw;
 242         enum hns3_evt_cause event_cause;
 243         uint32_t clearval = 0;
 244
 245         /* Disable interrupt */
 246         hns3_pf_disable_irq0(hw);
 247
 248         event_cause = hns3_check_event_cause(hns, &clearval);
 249         /* vector 0 interrupt is shared with reset and mailbox source events. */
 250         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 251                 hns3_warn(hw, "Received err interrupt");
 252                 hns3_handle_msix_error(hns, &hw->reset.request);
 253                 hns3_handle_ras_error(hns, &hw->reset.request);
 254                 hns3_schedule_reset(hns);
 255         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 256                 hns3_warn(hw, "Received reset interrupt");
 257                 hns3_schedule_reset(hns);
 258         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 259                 hns3_dev_handle_mbx_msg(hw);
 260         else
 261                 hns3_err(hw, "Received unknown event");
 262
 263         hns3_clear_event_cause(hw, event_cause, clearval);
 264         /* Enable interrupt if it is not cause by reset */
 265         hns3_pf_enable_irq0(hw);
 266 }
 267
 268 static int
 269 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 270 {
 271 #define HNS3_VLAN_ID_OFFSET_STEP        160
 272 #define HNS3_VLAN_BYTE_SIZE             8
 273         struct hns3_vlan_filter_pf_cfg_cmd *req;
 274         struct hns3_hw *hw = &hns->hw;
 275         uint8_t vlan_offset_byte_val;
 276         struct hns3_cmd_desc desc;
 277         uint8_t vlan_offset_byte;
 278         uint8_t vlan_offset_base;
 279         int ret;
 280
 281         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 282
 283         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 284         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 285                            HNS3_VLAN_BYTE_SIZE;
 286         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 287
 288         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 289         req->vlan_offset = vlan_offset_base;
 290         req->vlan_cfg = on ? 0 : 1;
 291         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 292
 293         ret = hns3_cmd_send(hw, &desc, 1);
 294         if (ret)
 295                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 296                          vlan_id, ret);
 297
 298         return ret;
 299 }
 300
 301 static void
 302 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 303 {
 304         struct hns3_user_vlan_table *vlan_entry;
 305         struct hns3_pf *pf = &hns->pf;
 306
 307         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 308                 if (vlan_entry->vlan_id == vlan_id) {
 309                         if (vlan_entry->hd_tbl_status)
 310                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 311                         LIST_REMOVE(vlan_entry, next);
 312                         rte_free(vlan_entry);
 313                         break;
 314                 }
 315         }
 316 }
 317
 318 static void
 319 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 320                         bool writen_to_tbl)
 321 {
 322         struct hns3_user_vlan_table *vlan_entry;
 323         struct hns3_hw *hw = &hns->hw;
 324         struct hns3_pf *pf = &hns->pf;
 325
 326         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 327                 if (vlan_entry->vlan_id == vlan_id)
 328                         return;
 329         }
 330
 331         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 332         if (vlan_entry == NULL) {
 333                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 334                 return;
 335         }
 336
 337         vlan_entry->hd_tbl_status = writen_to_tbl;
 338         vlan_entry->vlan_id = vlan_id;
 339
 340         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 341 }
 342
 343 static int
 344 hns3_restore_vlan_table(struct hns3_adapter *hns)
 345 {
 346         struct hns3_user_vlan_table *vlan_entry;
 347         struct hns3_hw *hw = &hns->hw;
 348         struct hns3_pf *pf = &hns->pf;
 349         uint16_t vlan_id;
 350         int ret = 0;
 351
 352         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 353                 return hns3_vlan_pvid_configure(hns,
 354                                                 hw->port_base_vlan_cfg.pvid, 1);
 355
 356         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 357                 if (vlan_entry->hd_tbl_status) {
 358                         vlan_id = vlan_entry->vlan_id;
 359                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 360                         if (ret)
 361                                 break;
 362                 }
 363         }
 364
 365         return ret;
 366 }
 367
 368 static int
 369 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 370 {
 371         struct hns3_hw *hw = &hns->hw;
 372         bool writen_to_tbl = false;
 373         int ret = 0;
 374
 375         /*
 376          * When vlan filter is enabled, hardware regards packets without vlan
 377          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 378          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 379          */
 380         if (on == 0 && vlan_id == 0)
 381                 return 0;
 382
 383         /*
 384          * When port base vlan enabled, we use port base vlan as the vlan
 385          * filter condition. In this case, we don't update vlan filter table
 386          * when user add new vlan or remove exist vlan, just update the
 387          * vlan list. The vlan id in vlan list will be writen in vlan filter
 388          * table until port base vlan disabled
 389          */
 390         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 391                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 392                 writen_to_tbl = true;
 393         }
 394
 395         if (ret == 0) {
 396                 if (on)
 397                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 398                 else
 399                         hns3_rm_dev_vlan_table(hns, vlan_id);
 400         }
 401         return ret;
 402 }
 403
 404 static int
 405 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 406 {
 407         struct hns3_adapter *hns = dev->data->dev_private;
 408         struct hns3_hw *hw = &hns->hw;
 409         int ret;
 410
 411         rte_spinlock_lock(&hw->lock);
 412         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 413         rte_spinlock_unlock(&hw->lock);
 414         return ret;
 415 }
 416
 417 static int
 418 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 419                          uint16_t tpid)
 420 {
 421         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 422         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 423         struct hns3_hw *hw = &hns->hw;
 424         struct hns3_cmd_desc desc;
 425         int ret;
 426
 427         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 428              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 429                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 430                 return -EINVAL;
 431         }
 432
 433         if (tpid != RTE_ETHER_TYPE_VLAN) {
 434                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 435                 return -EINVAL;
 436         }
 437
 438         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 439         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 440
 441         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 442                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 443                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 444         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 445                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 446                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 447                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 448                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 449         }
 450
 451         ret = hns3_cmd_send(hw, &desc, 1);
 452         if (ret) {
 453                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 454                          ret);
 455                 return ret;
 456         }
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 459
 460         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 461         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 462         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 463
 464         ret = hns3_cmd_send(hw, &desc, 1);
 465         if (ret)
 466                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 467                          ret);
 468         return ret;
 469 }
 470
 471 static int
 472 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 473                    uint16_t tpid)
 474 {
 475         struct hns3_adapter *hns = dev->data->dev_private;
 476         struct hns3_hw *hw = &hns->hw;
 477         int ret;
 478
 479         rte_spinlock_lock(&hw->lock);
 480         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 481         rte_spinlock_unlock(&hw->lock);
 482         return ret;
 483 }
 484
 485 static int
 486 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 487                              struct hns3_rx_vtag_cfg *vcfg)
 488 {
 489         struct hns3_vport_vtag_rx_cfg_cmd *req;
 490         struct hns3_hw *hw = &hns->hw;
 491         struct hns3_cmd_desc desc;
 492         uint16_t vport_id;
 493         uint8_t bitmap;
 494         int ret;
 495
 496         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 497
 498         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 499         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 500                      vcfg->strip_tag1_en ? 1 : 0);
 501         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 502                      vcfg->strip_tag2_en ? 1 : 0);
 503         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 504                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 505         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 506                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 507
 508         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 509         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 510                      vcfg->strip_tag1_discard_en ? 1 : 0);
 511         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 512                      vcfg->strip_tag2_discard_en ? 1 : 0);
 513         /*
 514          * In current version VF is not supported when PF is driven by DPDK
 515          * driver, just need to configure parameters for PF vport.
 516          */
 517         vport_id = HNS3_PF_FUNC_ID;
 518         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 519         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 520         req->vf_bitmap[req->vf_offset] = bitmap;
 521
 522         ret = hns3_cmd_send(hw, &desc, 1);
 523         if (ret)
 524                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 525         return ret;
 526 }
 527
 528 static void
 529 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 530                            struct hns3_rx_vtag_cfg *vcfg)
 531 {
 532         struct hns3_pf *pf = &hns->pf;
 533         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 534 }
 535
 536 static void
 537 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 538                            struct hns3_tx_vtag_cfg *vcfg)
 539 {
 540         struct hns3_pf *pf = &hns->pf;
 541         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 542 }
 543
 544 static int
 545 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 546 {
 547         struct hns3_rx_vtag_cfg rxvlan_cfg;
 548         struct hns3_hw *hw = &hns->hw;
 549         int ret;
 550
 551         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 552                 rxvlan_cfg.strip_tag1_en = false;
 553                 rxvlan_cfg.strip_tag2_en = enable;
 554                 rxvlan_cfg.strip_tag2_discard_en = false;
 555         } else {
 556                 rxvlan_cfg.strip_tag1_en = enable;
 557                 rxvlan_cfg.strip_tag2_en = true;
 558                 rxvlan_cfg.strip_tag2_discard_en = true;
 559         }
 560
 561         rxvlan_cfg.strip_tag1_discard_en = false;
 562         rxvlan_cfg.vlan1_vlan_prionly = false;
 563         rxvlan_cfg.vlan2_vlan_prionly = false;
 564         rxvlan_cfg.rx_vlan_offload_en = enable;
 565
 566         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 567         if (ret) {
 568                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 569                 return ret;
 570         }
 571
 572         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 573
 574         return ret;
 575 }
 576
 577 static int
 578 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 579                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 580 {
 581         struct hns3_vlan_filter_ctrl_cmd *req;
 582         struct hns3_cmd_desc desc;
 583         int ret;
 584
 585         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 586
 587         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 588         req->vlan_type = vlan_type;
 589         req->vlan_fe = filter_en ? fe_type : 0;
 590         req->vf_id = vf_id;
 591
 592         ret = hns3_cmd_send(hw, &desc, 1);
 593         if (ret)
 594                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 595
 596         return ret;
 597 }
 598
 599 static int
 600 hns3_vlan_filter_init(struct hns3_adapter *hns)
 601 {
 602         struct hns3_hw *hw = &hns->hw;
 603         int ret;
 604
 605         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 606                                         HNS3_FILTER_FE_EGRESS, false,
 607                                         HNS3_PF_FUNC_ID);
 608         if (ret) {
 609                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 610                 return ret;
 611         }
 612
 613         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 614                                         HNS3_FILTER_FE_INGRESS, false,
 615                                         HNS3_PF_FUNC_ID);
 616         if (ret)
 617                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 624 {
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 629                                         HNS3_FILTER_FE_INGRESS, enable,
 630                                         HNS3_PF_FUNC_ID);
 631         if (ret)
 632                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 633                          enable ? "enable" : "disable", ret);
 634
 635         return ret;
 636 }
 637
 638 static int
 639 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 640 {
 641         struct hns3_adapter *hns = dev->data->dev_private;
 642         struct hns3_hw *hw = &hns->hw;
 643         struct rte_eth_rxmode *rxmode;
 644         unsigned int tmp_mask;
 645         bool enable;
 646         int ret = 0;
 647
 648         rte_spinlock_lock(&hw->lock);
 649         rxmode = &dev->data->dev_conf.rxmode;
 650         tmp_mask = (unsigned int)mask;
 651         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 652                 /* ignore vlan filter configuration during promiscuous mode */
 653                 if (!dev->data->promiscuous) {
 654                         /* Enable or disable VLAN filter */
 655                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 656                                  true : false;
 657
 658                         ret = hns3_enable_vlan_filter(hns, enable);
 659                         if (ret) {
 660                                 rte_spinlock_unlock(&hw->lock);
 661                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 662                                          enable ? "enable" : "disable", ret);
 663                                 return ret;
 664                         }
 665                 }
 666         }
 667
 668         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 669                 /* Enable or disable VLAN stripping */
 670                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 671                     true : false;
 672
 673                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 674                 if (ret) {
 675                         rte_spinlock_unlock(&hw->lock);
 676                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 677                                  enable ? "enable" : "disable", ret);
 678                         return ret;
 679                 }
 680         }
 681
 682         rte_spinlock_unlock(&hw->lock);
 683
 684         return ret;
 685 }
 686
 687 static int
 688 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 689                              struct hns3_tx_vtag_cfg *vcfg)
 690 {
 691         struct hns3_vport_vtag_tx_cfg_cmd *req;
 692         struct hns3_cmd_desc desc;
 693         struct hns3_hw *hw = &hns->hw;
 694         uint16_t vport_id;
 695         uint8_t bitmap;
 696         int ret;
 697
 698         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 699
 700         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 701         req->def_vlan_tag1 = vcfg->default_tag1;
 702         req->def_vlan_tag2 = vcfg->default_tag2;
 703         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 704                      vcfg->accept_tag1 ? 1 : 0);
 705         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 706                      vcfg->accept_untag1 ? 1 : 0);
 707         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 708                      vcfg->accept_tag2 ? 1 : 0);
 709         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 710                      vcfg->accept_untag2 ? 1 : 0);
 711         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 712                      vcfg->insert_tag1_en ? 1 : 0);
 713         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 714                      vcfg->insert_tag2_en ? 1 : 0);
 715         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 716
 717         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 718         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 719                      vcfg->tag_shift_mode_en ? 1 : 0);
 720
 721         /*
 722          * In current version VF is not supported when PF is driven by DPDK
 723          * driver, just need to configure parameters for PF vport.
 724          */
 725         vport_id = HNS3_PF_FUNC_ID;
 726         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 727         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 728         req->vf_bitmap[req->vf_offset] = bitmap;
 729
 730         ret = hns3_cmd_send(hw, &desc, 1);
 731         if (ret)
 732                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 733
 734         return ret;
 735 }
 736
 737 static int
 738 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 739                      uint16_t pvid)
 740 {
 741         struct hns3_hw *hw = &hns->hw;
 742         struct hns3_tx_vtag_cfg txvlan_cfg;
 743         int ret;
 744
 745         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 746                 txvlan_cfg.accept_tag1 = true;
 747                 txvlan_cfg.insert_tag1_en = false;
 748                 txvlan_cfg.default_tag1 = 0;
 749         } else {
 750                 txvlan_cfg.accept_tag1 =
 751                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 752                 txvlan_cfg.insert_tag1_en = true;
 753                 txvlan_cfg.default_tag1 = pvid;
 754         }
 755
 756         txvlan_cfg.accept_untag1 = true;
 757         txvlan_cfg.accept_tag2 = true;
 758         txvlan_cfg.accept_untag2 = true;
 759         txvlan_cfg.insert_tag2_en = false;
 760         txvlan_cfg.default_tag2 = 0;
 761         txvlan_cfg.tag_shift_mode_en = true;
 762
 763         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 764         if (ret) {
 765                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 766                          ret);
 767                 return ret;
 768         }
 769
 770         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 771         return ret;
 772 }
 773
 774
 775 static void
 776 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 777 {
 778         struct hns3_user_vlan_table *vlan_entry;
 779         struct hns3_pf *pf = &hns->pf;
 780
 781         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 782                 if (vlan_entry->hd_tbl_status) {
 783                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 784                         vlan_entry->hd_tbl_status = false;
 785                 }
 786         }
 787
 788         if (is_del_list) {
 789                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 790                 while (vlan_entry) {
 791                         LIST_REMOVE(vlan_entry, next);
 792                         rte_free(vlan_entry);
 793                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 794                 }
 795         }
 796 }
 797
 798 static void
 799 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 800 {
 801         struct hns3_user_vlan_table *vlan_entry;
 802         struct hns3_pf *pf = &hns->pf;
 803
 804         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 805                 if (!vlan_entry->hd_tbl_status) {
 806                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 807                         vlan_entry->hd_tbl_status = true;
 808                 }
 809         }
 810 }
 811
 812 static void
 813 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 814 {
 815         struct hns3_hw *hw = &hns->hw;
 816         int ret;
 817
 818         hns3_rm_all_vlan_table(hns, true);
 819         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 820                 ret = hns3_set_port_vlan_filter(hns,
 821                                                 hw->port_base_vlan_cfg.pvid, 0);
 822                 if (ret) {
 823                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 824                                  ret);
 825                         return;
 826                 }
 827         }
 828 }
 829
 830 static int
 831 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 832                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 833 {
 834         struct hns3_hw *hw = &hns->hw;
 835         uint16_t old_pvid;
 836         int ret;
 837
 838         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 839                 old_pvid = hw->port_base_vlan_cfg.pvid;
 840                 if (old_pvid != HNS3_INVALID_PVID) {
 841                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 842                         if (ret) {
 843                                 hns3_err(hw, "failed to remove old pvid %u, "
 844                                                 "ret = %d", old_pvid, ret);
 845                                 return ret;
 846                         }
 847                 }
 848
 849                 hns3_rm_all_vlan_table(hns, false);
 850                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 851                 if (ret) {
 852                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 853                                         new_pvid, ret);
 854                         return ret;
 855                 }
 856         } else {
 857                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 858                 if (ret) {
 859                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 860                                         new_pvid, ret);
 861                         return ret;
 862                 }
 863
 864                 hns3_add_all_vlan_table(hns);
 865         }
 866         return 0;
 867 }
 868
 869 static int
 870 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 871 {
 872         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 873         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 874         bool rx_strip_en;
 875         int ret;
 876
 877         rx_strip_en = old_cfg->rx_vlan_offload_en;
 878         if (on) {
 879                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 880                 rx_vlan_cfg.strip_tag2_en = true;
 881                 rx_vlan_cfg.strip_tag2_discard_en = true;
 882         } else {
 883                 rx_vlan_cfg.strip_tag1_en = false;
 884                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 885                 rx_vlan_cfg.strip_tag2_discard_en = false;
 886         }
 887         rx_vlan_cfg.strip_tag1_discard_en = false;
 888         rx_vlan_cfg.vlan1_vlan_prionly = false;
 889         rx_vlan_cfg.vlan2_vlan_prionly = false;
 890         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 891
 892         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 893         if (ret)
 894                 return ret;
 895
 896         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 897         return ret;
 898 }
 899
 900 static int
 901 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 902 {
 903         struct hns3_hw *hw = &hns->hw;
 904         uint16_t port_base_vlan_state;
 905         int ret;
 906
 907         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 908                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 909                         hns3_warn(hw, "Invalid operation! As current pvid set "
 910                                   "is %u, disable pvid %u is invalid",
 911                                   hw->port_base_vlan_cfg.pvid, pvid);
 912                 return 0;
 913         }
 914
 915         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 916                                     HNS3_PORT_BASE_VLAN_DISABLE;
 917         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 918         if (ret) {
 919                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 920                          ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_en_pvid_strip(hns, on);
 925         if (ret) {
 926                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 927                          "ret = %d", ret);
 928                 return ret;
 929         }
 930
 931         if (pvid == HNS3_INVALID_PVID)
 932                 goto out;
 933         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 934         if (ret) {
 935                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 936                          ret);
 937                 return ret;
 938         }
 939
 940 out:
 941         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 942         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 943         return ret;
 944 }
 945
 946 static int
 947 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 948 {
 949         struct hns3_adapter *hns = dev->data->dev_private;
 950         struct hns3_hw *hw = &hns->hw;
 951         bool pvid_en_state_change;
 952         uint16_t pvid_state;
 953         int ret;
 954
 955         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 956                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 957                          RTE_ETHER_MAX_VLAN_ID);
 958                 return -EINVAL;
 959         }
 960
 961         /*
 962          * If PVID configuration state change, should refresh the PVID
 963          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 964          */
 965         pvid_state = hw->port_base_vlan_cfg.state;
 966         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 967             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 968                 pvid_en_state_change = false;
 969         else
 970                 pvid_en_state_change = true;
 971
 972         rte_spinlock_lock(&hw->lock);
 973         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 974         rte_spinlock_unlock(&hw->lock);
 975         if (ret)
 976                 return ret;
 977         /*
 978          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 979          * need be processed by PMD driver.
 980          */
 981         if (pvid_en_state_change &&
 982             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 983                 hns3_update_all_queues_pvid_proc_en(hw);
 984
 985         return 0;
 986 }
 987
 988 static int
 989 hns3_default_vlan_config(struct hns3_adapter *hns)
 990 {
 991         struct hns3_hw *hw = &hns->hw;
 992         int ret;
 993
 994         /*
 995          * When vlan filter is enabled, hardware regards packets without vlan
 996          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
 997          * table, packets without vlan won't be received. So, add vlan 0 as
 998          * the default vlan.
 999          */
1000         ret = hns3_vlan_filter_configure(hns, 0, 1);
1001         if (ret)
1002                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1003         return ret;
1004 }
1005
1006 static int
1007 hns3_init_vlan_config(struct hns3_adapter *hns)
1008 {
1009         struct hns3_hw *hw = &hns->hw;
1010         int ret;
1011
1012         /*
1013          * This function can be called in the initialization and reset process,
1014          * when in reset process, it means that hardware had been reseted
1015          * successfully and we need to restore the hardware configuration to
1016          * ensure that the hardware configuration remains unchanged before and
1017          * after reset.
1018          */
1019         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1020                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1021                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1022         }
1023
1024         ret = hns3_vlan_filter_init(hns);
1025         if (ret) {
1026                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1027                 return ret;
1028         }
1029
1030         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1031                                        RTE_ETHER_TYPE_VLAN);
1032         if (ret) {
1033                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1034                 return ret;
1035         }
1036
1037         /*
1038          * When in the reinit dev stage of the reset process, the following
1039          * vlan-related configurations may differ from those at initialization,
1040          * we will restore configurations to hardware in hns3_restore_vlan_table
1041          * and hns3_restore_vlan_conf later.
1042          */
1043         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1044                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1045                 if (ret) {
1046                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1047                         return ret;
1048                 }
1049
1050                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1051                 if (ret) {
1052                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1053                                  ret);
1054                         return ret;
1055                 }
1056         }
1057
1058         return hns3_default_vlan_config(hns);
1059 }
1060
1061 static int
1062 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1063 {
1064         struct hns3_pf *pf = &hns->pf;
1065         struct hns3_hw *hw = &hns->hw;
1066         uint64_t offloads;
1067         bool enable;
1068         int ret;
1069
1070         if (!hw->data->promiscuous) {
1071                 /* restore vlan filter states */
1072                 offloads = hw->data->dev_conf.rxmode.offloads;
1073                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1074                 ret = hns3_enable_vlan_filter(hns, enable);
1075                 if (ret) {
1076                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1077                                  "ret = %d", ret);
1078                         return ret;
1079                 }
1080         }
1081
1082         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1083         if (ret) {
1084                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1085                 return ret;
1086         }
1087
1088         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1089         if (ret)
1090                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1091
1092         return ret;
1093 }
1094
1095 static int
1096 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1097 {
1098         struct hns3_adapter *hns = dev->data->dev_private;
1099         struct rte_eth_dev_data *data = dev->data;
1100         struct rte_eth_txmode *txmode;
1101         struct hns3_hw *hw = &hns->hw;
1102         int mask;
1103         int ret;
1104
1105         txmode = &data->dev_conf.txmode;
1106         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1107                 hns3_warn(hw,
1108                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1109                           "configuration is not supported! Ignore these two "
1110                           "parameters: hw_vlan_reject_tagged(%u), "
1111                           "hw_vlan_reject_untagged(%u)",
1112                           txmode->hw_vlan_reject_tagged,
1113                           txmode->hw_vlan_reject_untagged);
1114
1115         /* Apply vlan offload setting */
1116         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1117         ret = hns3_vlan_offload_set(dev, mask);
1118         if (ret) {
1119                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1120                          ret);
1121                 return ret;
1122         }
1123
1124         /*
1125          * If pvid config is not set in rte_eth_conf, driver needn't to set
1126          * VLAN pvid related configuration to hardware.
1127          */
1128         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1129                 return 0;
1130
1131         /* Apply pvid setting */
1132         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1133                                  txmode->hw_vlan_insert_pvid);
1134         if (ret)
1135                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1136                          txmode->pvid, ret);
1137
1138         return ret;
1139 }
1140
1141 static int
1142 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1143                 unsigned int tso_mss_max)
1144 {
1145         struct hns3_cfg_tso_status_cmd *req;
1146         struct hns3_cmd_desc desc;
1147         uint16_t tso_mss;
1148
1149         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1150
1151         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1152
1153         tso_mss = 0;
1154         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1155                        tso_mss_min);
1156         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1157
1158         tso_mss = 0;
1159         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1160                        tso_mss_max);
1161         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1162
1163         return hns3_cmd_send(hw, &desc, 1);
1164 }
1165
1166 static int
1167 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1168                    uint16_t *allocated_size, bool is_alloc)
1169 {
1170         struct hns3_umv_spc_alc_cmd *req;
1171         struct hns3_cmd_desc desc;
1172         int ret;
1173
1174         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1175         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1176         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1177         req->space_size = rte_cpu_to_le_32(space_size);
1178
1179         ret = hns3_cmd_send(hw, &desc, 1);
1180         if (ret) {
1181                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1182                              is_alloc ? "allocate" : "free", ret);
1183                 return ret;
1184         }
1185
1186         if (is_alloc && allocated_size)
1187                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1188
1189         return 0;
1190 }
1191
1192 static int
1193 hns3_init_umv_space(struct hns3_hw *hw)
1194 {
1195         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1196         struct hns3_pf *pf = &hns->pf;
1197         uint16_t allocated_size = 0;
1198         int ret;
1199
1200         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1201                                  true);
1202         if (ret)
1203                 return ret;
1204
1205         if (allocated_size < pf->wanted_umv_size)
1206                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1207                              pf->wanted_umv_size, allocated_size);
1208
1209         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1210                                                 pf->wanted_umv_size;
1211         pf->used_umv_size = 0;
1212         return 0;
1213 }
1214
1215 static int
1216 hns3_uninit_umv_space(struct hns3_hw *hw)
1217 {
1218         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219         struct hns3_pf *pf = &hns->pf;
1220         int ret;
1221
1222         if (pf->max_umv_size == 0)
1223                 return 0;
1224
1225         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1226         if (ret)
1227                 return ret;
1228
1229         pf->max_umv_size = 0;
1230
1231         return 0;
1232 }
1233
1234 static bool
1235 hns3_is_umv_space_full(struct hns3_hw *hw)
1236 {
1237         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1238         struct hns3_pf *pf = &hns->pf;
1239         bool is_full;
1240
1241         is_full = (pf->used_umv_size >= pf->max_umv_size);
1242
1243         return is_full;
1244 }
1245
1246 static void
1247 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1248 {
1249         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1250         struct hns3_pf *pf = &hns->pf;
1251
1252         if (is_free) {
1253                 if (pf->used_umv_size > 0)
1254                         pf->used_umv_size--;
1255         } else
1256                 pf->used_umv_size++;
1257 }
1258
1259 static void
1260 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1261                       const uint8_t *addr, bool is_mc)
1262 {
1263         const unsigned char *mac_addr = addr;
1264         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1265                             ((uint32_t)mac_addr[2] << 16) |
1266                             ((uint32_t)mac_addr[1] << 8) |
1267                             (uint32_t)mac_addr[0];
1268         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1269
1270         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1271         if (is_mc) {
1272                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1273                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1274                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1275         }
1276
1277         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1278         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1279 }
1280
1281 static int
1282 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1283                              uint8_t resp_code,
1284                              enum hns3_mac_vlan_tbl_opcode op)
1285 {
1286         if (cmdq_resp) {
1287                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1288                          cmdq_resp);
1289                 return -EIO;
1290         }
1291
1292         if (op == HNS3_MAC_VLAN_ADD) {
1293                 if (resp_code == 0 || resp_code == 1) {
1294                         return 0;
1295                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1296                         hns3_err(hw, "add mac addr failed for uc_overflow");
1297                         return -ENOSPC;
1298                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1299                         hns3_err(hw, "add mac addr failed for mc_overflow");
1300                         return -ENOSPC;
1301                 }
1302
1303                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1304                          resp_code);
1305                 return -EIO;
1306         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1307                 if (resp_code == 0) {
1308                         return 0;
1309                 } else if (resp_code == 1) {
1310                         hns3_dbg(hw, "remove mac addr failed for miss");
1311                         return -ENOENT;
1312                 }
1313
1314                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1315                          resp_code);
1316                 return -EIO;
1317         } else if (op == HNS3_MAC_VLAN_LKUP) {
1318                 if (resp_code == 0) {
1319                         return 0;
1320                 } else if (resp_code == 1) {
1321                         hns3_dbg(hw, "lookup mac addr failed for miss");
1322                         return -ENOENT;
1323                 }
1324
1325                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1326                          resp_code);
1327                 return -EIO;
1328         }
1329
1330         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1331                  op);
1332
1333         return -EINVAL;
1334 }
1335
1336 static int
1337 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1338                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1339                          struct hns3_cmd_desc *desc, bool is_mc)
1340 {
1341         uint8_t resp_code;
1342         uint16_t retval;
1343         int ret;
1344
1345         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1346         if (is_mc) {
1347                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1348                 memcpy(desc[0].data, req,
1349                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1350                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1351                                           true);
1352                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1353                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1354                                           true);
1355                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1356         } else {
1357                 memcpy(desc[0].data, req,
1358                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1359                 ret = hns3_cmd_send(hw, desc, 1);
1360         }
1361         if (ret) {
1362                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1363                          ret);
1364                 return ret;
1365         }
1366         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1367         retval = rte_le_to_cpu_16(desc[0].retval);
1368
1369         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1370                                             HNS3_MAC_VLAN_LKUP);
1371 }
1372
1373 static int
1374 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1375                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1376                       struct hns3_cmd_desc *mc_desc)
1377 {
1378         uint8_t resp_code;
1379         uint16_t retval;
1380         int cfg_status;
1381         int ret;
1382
1383         if (mc_desc == NULL) {
1384                 struct hns3_cmd_desc desc;
1385
1386                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1387                 memcpy(desc.data, req,
1388                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1389                 ret = hns3_cmd_send(hw, &desc, 1);
1390                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1391                 retval = rte_le_to_cpu_16(desc.retval);
1392
1393                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1394                                                           HNS3_MAC_VLAN_ADD);
1395         } else {
1396                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1397                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1398                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1399                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1400                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1401                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1402                 memcpy(mc_desc[0].data, req,
1403                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1404                 mc_desc[0].retval = 0;
1405                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1406                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1407                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1408
1409                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1410                                                           HNS3_MAC_VLAN_ADD);
1411         }
1412
1413         if (ret) {
1414                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1415                 return ret;
1416         }
1417
1418         return cfg_status;
1419 }
1420
1421 static int
1422 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1423                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1424 {
1425         struct hns3_cmd_desc desc;
1426         uint8_t resp_code;
1427         uint16_t retval;
1428         int ret;
1429
1430         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1431
1432         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1433
1434         ret = hns3_cmd_send(hw, &desc, 1);
1435         if (ret) {
1436                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1437                 return ret;
1438         }
1439         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1440         retval = rte_le_to_cpu_16(desc.retval);
1441
1442         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1443                                             HNS3_MAC_VLAN_REMOVE);
1444 }
1445
1446 static int
1447 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1448 {
1449         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1450         struct hns3_mac_vlan_tbl_entry_cmd req;
1451         struct hns3_pf *pf = &hns->pf;
1452         struct hns3_cmd_desc desc[3];
1453         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1454         uint16_t egress_port = 0;
1455         uint8_t vf_id;
1456         int ret;
1457
1458         /* check if mac addr is valid */
1459         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1460                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1461                                       mac_addr);
1462                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1463                          mac_str);
1464                 return -EINVAL;
1465         }
1466
1467         memset(&req, 0, sizeof(req));
1468
1469         /*
1470          * In current version VF is not supported when PF is driven by DPDK
1471          * driver, just need to configure parameters for PF vport.
1472          */
1473         vf_id = HNS3_PF_FUNC_ID;
1474         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1475                        HNS3_MAC_EPORT_VFID_S, vf_id);
1476
1477         req.egress_port = rte_cpu_to_le_16(egress_port);
1478
1479         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1480
1481         /*
1482          * Lookup the mac address in the mac_vlan table, and add
1483          * it if the entry is inexistent. Repeated unicast entry
1484          * is not allowed in the mac vlan table.
1485          */
1486         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1487         if (ret == -ENOENT) {
1488                 if (!hns3_is_umv_space_full(hw)) {
1489                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1490                         if (!ret)
1491                                 hns3_update_umv_space(hw, false);
1492                         return ret;
1493                 }
1494
1495                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1496
1497                 return -ENOSPC;
1498         }
1499
1500         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1501
1502         /* check if we just hit the duplicate */
1503         if (ret == 0) {
1504                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1505                 return 0;
1506         }
1507
1508         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1509                  mac_str);
1510
1511         return ret;
1512 }
1513
1514 static int
1515 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1516 {
1517         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1518         struct rte_ether_addr *addr;
1519         int ret;
1520         int i;
1521
1522         for (i = 0; i < hw->mc_addrs_num; i++) {
1523                 addr = &hw->mc_addrs[i];
1524                 /* Check if there are duplicate addresses */
1525                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1526                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1527                                               addr);
1528                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1529                                  "(%s) is added by the set_mc_mac_addr_list "
1530                                  "API", mac_str);
1531                         return -EINVAL;
1532                 }
1533         }
1534
1535         ret = hns3_add_mc_addr(hw, mac_addr);
1536         if (ret) {
1537                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1538                                       mac_addr);
1539                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1540                          mac_str, ret);
1541         }
1542         return ret;
1543 }
1544
1545 static int
1546 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1547 {
1548         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1549         int ret;
1550
1551         ret = hns3_remove_mc_addr(hw, mac_addr);
1552         if (ret) {
1553                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                       mac_addr);
1555                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1556                          mac_str, ret);
1557         }
1558         return ret;
1559 }
1560
1561 static int
1562 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1563                   uint32_t idx, __rte_unused uint32_t pool)
1564 {
1565         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1567         int ret;
1568
1569         rte_spinlock_lock(&hw->lock);
1570
1571         /*
1572          * In hns3 network engine adding UC and MC mac address with different
1573          * commands with firmware. We need to determine whether the input
1574          * address is a UC or a MC address to call different commands.
1575          * By the way, it is recommended calling the API function named
1576          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1577          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1578          * may affect the specifications of UC mac addresses.
1579          */
1580         if (rte_is_multicast_ether_addr(mac_addr))
1581                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1582         else
1583                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1584
1585         if (ret) {
1586                 rte_spinlock_unlock(&hw->lock);
1587                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1588                                       mac_addr);
1589                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1590                          ret);
1591                 return ret;
1592         }
1593
1594         if (idx == 0)
1595                 hw->mac.default_addr_setted = true;
1596         rte_spinlock_unlock(&hw->lock);
1597
1598         return ret;
1599 }
1600
1601 static int
1602 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1603 {
1604         struct hns3_mac_vlan_tbl_entry_cmd req;
1605         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1606         int ret;
1607
1608         /* check if mac addr is valid */
1609         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                       mac_addr);
1612                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1613                          mac_str);
1614                 return -EINVAL;
1615         }
1616
1617         memset(&req, 0, sizeof(req));
1618         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1619         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1620         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1621         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1622                 return 0;
1623         else if (ret == 0)
1624                 hns3_update_umv_space(hw, true);
1625
1626         return ret;
1627 }
1628
1629 static void
1630 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1631 {
1632         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         /* index will be checked by upper level rte interface */
1634         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1635         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1636         int ret;
1637
1638         rte_spinlock_lock(&hw->lock);
1639
1640         if (rte_is_multicast_ether_addr(mac_addr))
1641                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1642         else
1643                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1644         rte_spinlock_unlock(&hw->lock);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1649                          ret);
1650         }
1651 }
1652
1653 static int
1654 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1655                           struct rte_ether_addr *mac_addr)
1656 {
1657         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         struct rte_ether_addr *oaddr;
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         bool default_addr_setted;
1661         bool rm_succes = false;
1662         int ret, ret_val;
1663
1664         /*
1665          * It has been guaranteed that input parameter named mac_addr is valid
1666          * address in the rte layer of DPDK framework.
1667          */
1668         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1669         default_addr_setted = hw->mac.default_addr_setted;
1670         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1671                 return 0;
1672
1673         rte_spinlock_lock(&hw->lock);
1674         if (default_addr_setted) {
1675                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1676                 if (ret) {
1677                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1678                                               oaddr);
1679                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1680                                   mac_str, ret);
1681                         rm_succes = false;
1682                 } else
1683                         rm_succes = true;
1684         }
1685
1686         ret = hns3_add_uc_addr_common(hw, mac_addr);
1687         if (ret) {
1688                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1689                                       mac_addr);
1690                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1691                 goto err_add_uc_addr;
1692         }
1693
1694         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1695         if (ret) {
1696                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1697                 goto err_pause_addr_cfg;
1698         }
1699
1700         rte_ether_addr_copy(mac_addr,
1701                             (struct rte_ether_addr *)hw->mac.mac_addr);
1702         hw->mac.default_addr_setted = true;
1703         rte_spinlock_unlock(&hw->lock);
1704
1705         return 0;
1706
1707 err_pause_addr_cfg:
1708         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1709         if (ret_val) {
1710                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1711                                       mac_addr);
1712                 hns3_warn(hw,
1713                           "Failed to roll back to del setted mac addr(%s): %d",
1714                           mac_str, ret_val);
1715         }
1716
1717 err_add_uc_addr:
1718         if (rm_succes) {
1719                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1720                 if (ret_val) {
1721                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1722                                               oaddr);
1723                         hns3_warn(hw,
1724                                   "Failed to restore old uc mac addr(%s): %d",
1725                                   mac_str, ret_val);
1726                         hw->mac.default_addr_setted = false;
1727                 }
1728         }
1729         rte_spinlock_unlock(&hw->lock);
1730
1731         return ret;
1732 }
1733
1734 static int
1735 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1736 {
1737         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1738         struct hns3_hw *hw = &hns->hw;
1739         struct rte_ether_addr *addr;
1740         int err = 0;
1741         int ret;
1742         int i;
1743
1744         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1745                 addr = &hw->data->mac_addrs[i];
1746                 if (rte_is_zero_ether_addr(addr))
1747                         continue;
1748                 if (rte_is_multicast_ether_addr(addr))
1749                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1750                               hns3_add_mc_addr(hw, addr);
1751                 else
1752                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1753                               hns3_add_uc_addr_common(hw, addr);
1754
1755                 if (ret) {
1756                         err = ret;
1757                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1758                                               addr);
1759                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1760                                  "ret = %d.", del ? "remove" : "restore",
1761                                  mac_str, i, ret);
1762                 }
1763         }
1764         return err;
1765 }
1766
1767 static void
1768 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1769 {
1770 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1771         uint8_t word_num;
1772         uint8_t bit_num;
1773
1774         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1775                 word_num = vfid / 32;
1776                 bit_num = vfid % 32;
1777                 if (clr)
1778                         desc[1].data[word_num] &=
1779                             rte_cpu_to_le_32(~(1UL << bit_num));
1780                 else
1781                         desc[1].data[word_num] |=
1782                             rte_cpu_to_le_32(1UL << bit_num);
1783         } else {
1784                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1785                 bit_num = vfid % 32;
1786                 if (clr)
1787                         desc[2].data[word_num] &=
1788                             rte_cpu_to_le_32(~(1UL << bit_num));
1789                 else
1790                         desc[2].data[word_num] |=
1791                             rte_cpu_to_le_32(1UL << bit_num);
1792         }
1793 }
1794
1795 static int
1796 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1797 {
1798         struct hns3_mac_vlan_tbl_entry_cmd req;
1799         struct hns3_cmd_desc desc[3];
1800         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1801         uint8_t vf_id;
1802         int ret;
1803
1804         /* Check if mac addr is valid */
1805         if (!rte_is_multicast_ether_addr(mac_addr)) {
1806                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1807                                       mac_addr);
1808                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1809                          mac_str);
1810                 return -EINVAL;
1811         }
1812
1813         memset(&req, 0, sizeof(req));
1814         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1815         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1816         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1817         if (ret) {
1818                 /* This mac addr do not exist, add new entry for it */
1819                 memset(desc[0].data, 0, sizeof(desc[0].data));
1820                 memset(desc[1].data, 0, sizeof(desc[0].data));
1821                 memset(desc[2].data, 0, sizeof(desc[0].data));
1822         }
1823
1824         /*
1825          * In current version VF is not supported when PF is driven by DPDK
1826          * driver, just need to configure parameters for PF vport.
1827          */
1828         vf_id = HNS3_PF_FUNC_ID;
1829         hns3_update_desc_vfid(desc, vf_id, false);
1830         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1831         if (ret) {
1832                 if (ret == -ENOSPC)
1833                         hns3_err(hw, "mc mac vlan table is full");
1834                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1835                                       mac_addr);
1836                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1837         }
1838
1839         return ret;
1840 }
1841
1842 static int
1843 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1844 {
1845         struct hns3_mac_vlan_tbl_entry_cmd req;
1846         struct hns3_cmd_desc desc[3];
1847         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1848         uint8_t vf_id;
1849         int ret;
1850
1851         /* Check if mac addr is valid */
1852         if (!rte_is_multicast_ether_addr(mac_addr)) {
1853                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1854                                       mac_addr);
1855                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1856                          mac_str);
1857                 return -EINVAL;
1858         }
1859
1860         memset(&req, 0, sizeof(req));
1861         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1862         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1863         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1864         if (ret == 0) {
1865                 /*
1866                  * This mac addr exist, remove this handle's VFID for it.
1867                  * In current version VF is not supported when PF is driven by
1868                  * DPDK driver, just need to configure parameters for PF vport.
1869                  */
1870                 vf_id = HNS3_PF_FUNC_ID;
1871                 hns3_update_desc_vfid(desc, vf_id, true);
1872
1873                 /* All the vfid is zero, so need to delete this entry */
1874                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1875         } else if (ret == -ENOENT) {
1876                 /* This mac addr doesn't exist. */
1877                 return 0;
1878         }
1879
1880         if (ret) {
1881                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1882                                       mac_addr);
1883                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1884         }
1885
1886         return ret;
1887 }
1888
1889 static int
1890 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1891                            struct rte_ether_addr *mc_addr_set,
1892                            uint32_t nb_mc_addr)
1893 {
1894         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1895         struct rte_ether_addr *addr;
1896         uint32_t i;
1897         uint32_t j;
1898
1899         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1900                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1901                          "invalid. valid range: 0~%d",
1902                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1903                 return -EINVAL;
1904         }
1905
1906         /* Check if input mac addresses are valid */
1907         for (i = 0; i < nb_mc_addr; i++) {
1908                 addr = &mc_addr_set[i];
1909                 if (!rte_is_multicast_ether_addr(addr)) {
1910                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1911                                               addr);
1912                         hns3_err(hw,
1913                                  "failed to set mc mac addr, addr(%s) invalid.",
1914                                  mac_str);
1915                         return -EINVAL;
1916                 }
1917
1918                 /* Check if there are duplicate addresses */
1919                 for (j = i + 1; j < nb_mc_addr; j++) {
1920                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1921                                 hns3_ether_format_addr(mac_str,
1922                                                       RTE_ETHER_ADDR_FMT_SIZE,
1923                                                       addr);
1924                                 hns3_err(hw, "failed to set mc mac addr, "
1925                                          "addrs invalid. two same addrs(%s).",
1926                                          mac_str);
1927                                 return -EINVAL;
1928                         }
1929                 }
1930
1931                 /*
1932                  * Check if there are duplicate addresses between mac_addrs
1933                  * and mc_addr_set
1934                  */
1935                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1936                         if (rte_is_same_ether_addr(addr,
1937                                                    &hw->data->mac_addrs[j])) {
1938                                 hns3_ether_format_addr(mac_str,
1939                                                       RTE_ETHER_ADDR_FMT_SIZE,
1940                                                       addr);
1941                                 hns3_err(hw, "failed to set mc mac addr, "
1942                                          "addrs invalid. addrs(%s) has already "
1943                                          "configured in mac_addr add API",
1944                                          mac_str);
1945                                 return -EINVAL;
1946                         }
1947                 }
1948         }
1949
1950         return 0;
1951 }
1952
1953 static void
1954 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1955                            struct rte_ether_addr *mc_addr_set,
1956                            int mc_addr_num,
1957                            struct rte_ether_addr *reserved_addr_list,
1958                            int *reserved_addr_num,
1959                            struct rte_ether_addr *add_addr_list,
1960                            int *add_addr_num,
1961                            struct rte_ether_addr *rm_addr_list,
1962                            int *rm_addr_num)
1963 {
1964         struct rte_ether_addr *addr;
1965         int current_addr_num;
1966         int reserved_num = 0;
1967         int add_num = 0;
1968         int rm_num = 0;
1969         int num;
1970         int i;
1971         int j;
1972         bool same_addr;
1973
1974         /* Calculate the mc mac address list that should be removed */
1975         current_addr_num = hw->mc_addrs_num;
1976         for (i = 0; i < current_addr_num; i++) {
1977                 addr = &hw->mc_addrs[i];
1978                 same_addr = false;
1979                 for (j = 0; j < mc_addr_num; j++) {
1980                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1981                                 same_addr = true;
1982                                 break;
1983                         }
1984                 }
1985
1986                 if (!same_addr) {
1987                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1988                         rm_num++;
1989                 } else {
1990                         rte_ether_addr_copy(addr,
1991                                             &reserved_addr_list[reserved_num]);
1992                         reserved_num++;
1993                 }
1994         }
1995
1996         /* Calculate the mc mac address list that should be added */
1997         for (i = 0; i < mc_addr_num; i++) {
1998                 addr = &mc_addr_set[i];
1999                 same_addr = false;
2000                 for (j = 0; j < current_addr_num; j++) {
2001                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2002                                 same_addr = true;
2003                                 break;
2004                         }
2005                 }
2006
2007                 if (!same_addr) {
2008                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2009                         add_num++;
2010                 }
2011         }
2012
2013         /* Reorder the mc mac address list maintained by driver */
2014         for (i = 0; i < reserved_num; i++)
2015                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2016
2017         for (i = 0; i < rm_num; i++) {
2018                 num = reserved_num + i;
2019                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2020         }
2021
2022         *reserved_addr_num = reserved_num;
2023         *add_addr_num = add_num;
2024         *rm_addr_num = rm_num;
2025 }
2026
2027 static int
2028 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2029                           struct rte_ether_addr *mc_addr_set,
2030                           uint32_t nb_mc_addr)
2031 {
2032         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2034         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2035         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2036         struct rte_ether_addr *addr;
2037         int reserved_addr_num;
2038         int add_addr_num;
2039         int rm_addr_num;
2040         int mc_addr_num;
2041         int num;
2042         int ret;
2043         int i;
2044
2045         /* Check if input parameters are valid */
2046         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2047         if (ret)
2048                 return ret;
2049
2050         rte_spinlock_lock(&hw->lock);
2051
2052         /*
2053          * Calculate the mc mac address lists those should be removed and be
2054          * added, Reorder the mc mac address list maintained by driver.
2055          */
2056         mc_addr_num = (int)nb_mc_addr;
2057         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2058                                    reserved_addr_list, &reserved_addr_num,
2059                                    add_addr_list, &add_addr_num,
2060                                    rm_addr_list, &rm_addr_num);
2061
2062         /* Remove mc mac addresses */
2063         for (i = 0; i < rm_addr_num; i++) {
2064                 num = rm_addr_num - i - 1;
2065                 addr = &rm_addr_list[num];
2066                 ret = hns3_remove_mc_addr(hw, addr);
2067                 if (ret) {
2068                         rte_spinlock_unlock(&hw->lock);
2069                         return ret;
2070                 }
2071                 hw->mc_addrs_num--;
2072         }
2073
2074         /* Add mc mac addresses */
2075         for (i = 0; i < add_addr_num; i++) {
2076                 addr = &add_addr_list[i];
2077                 ret = hns3_add_mc_addr(hw, addr);
2078                 if (ret) {
2079                         rte_spinlock_unlock(&hw->lock);
2080                         return ret;
2081                 }
2082
2083                 num = reserved_addr_num + i;
2084                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2085                 hw->mc_addrs_num++;
2086         }
2087         rte_spinlock_unlock(&hw->lock);
2088
2089         return 0;
2090 }
2091
2092 static int
2093 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2094 {
2095         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2096         struct hns3_hw *hw = &hns->hw;
2097         struct rte_ether_addr *addr;
2098         int err = 0;
2099         int ret;
2100         int i;
2101
2102         for (i = 0; i < hw->mc_addrs_num; i++) {
2103                 addr = &hw->mc_addrs[i];
2104                 if (!rte_is_multicast_ether_addr(addr))
2105                         continue;
2106                 if (del)
2107                         ret = hns3_remove_mc_addr(hw, addr);
2108                 else
2109                         ret = hns3_add_mc_addr(hw, addr);
2110                 if (ret) {
2111                         err = ret;
2112                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2113                                               addr);
2114                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2115                                  del ? "Remove" : "Restore", mac_str, ret);
2116                 }
2117         }
2118         return err;
2119 }
2120
2121 static int
2122 hns3_check_mq_mode(struct rte_eth_dev *dev)
2123 {
2124         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2125         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2126         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2128         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2129         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2130         uint8_t num_tc;
2131         int max_tc = 0;
2132         int i;
2133
2134         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2135         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2136
2137         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2138                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2139                          "rx_mq_mode = %d", rx_mq_mode);
2140                 return -EINVAL;
2141         }
2142
2143         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2144             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2145                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2146                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2147                          rx_mq_mode, tx_mq_mode);
2148                 return -EINVAL;
2149         }
2150
2151         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2152                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2153                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2154                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2155                         return -EINVAL;
2156                 }
2157
2158                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2159                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2160                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2161                                  "nb_tcs(%d) != %d or %d in rx direction.",
2162                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2163                         return -EINVAL;
2164                 }
2165
2166                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2167                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2168                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2169                         return -EINVAL;
2170                 }
2171
2172                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2173                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2174                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2175                                          "is not equal to one in tx direction.",
2176                                          i, dcb_rx_conf->dcb_tc[i]);
2177                                 return -EINVAL;
2178                         }
2179                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2180                                 max_tc = dcb_rx_conf->dcb_tc[i];
2181                 }
2182
2183                 num_tc = max_tc + 1;
2184                 if (num_tc > dcb_rx_conf->nb_tcs) {
2185                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2186                                  num_tc, dcb_rx_conf->nb_tcs);
2187                         return -EINVAL;
2188                 }
2189         }
2190
2191         return 0;
2192 }
2193
2194 static int
2195 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2196 {
2197         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198
2199         if (!hns3_dev_dcb_supported(hw)) {
2200                 hns3_err(hw, "this port does not support dcb configurations.");
2201                 return -EOPNOTSUPP;
2202         }
2203
2204         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2205                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2206                 return -EOPNOTSUPP;
2207         }
2208
2209         /* Check multiple queue mode */
2210         return hns3_check_mq_mode(dev);
2211 }
2212
2213 static int
2214 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2215                            enum hns3_ring_type queue_type, uint16_t queue_id)
2216 {
2217         struct hns3_cmd_desc desc;
2218         struct hns3_ctrl_vector_chain_cmd *req =
2219                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2220         enum hns3_cmd_status status;
2221         enum hns3_opcode_type op;
2222         uint16_t tqp_type_and_id = 0;
2223         const char *op_str;
2224         uint16_t type;
2225         uint16_t gl;
2226
2227         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2228         hns3_cmd_setup_basic_desc(&desc, op, false);
2229         req->int_vector_id = vector_id;
2230
2231         if (queue_type == HNS3_RING_TYPE_RX)
2232                 gl = HNS3_RING_GL_RX;
2233         else
2234                 gl = HNS3_RING_GL_TX;
2235
2236         type = queue_type;
2237
2238         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2239                        type);
2240         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2241         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2242                        gl);
2243         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2244         req->int_cause_num = 1;
2245         op_str = mmap ? "Map" : "Unmap";
2246         status = hns3_cmd_send(hw, &desc, 1);
2247         if (status) {
2248                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2249                          op_str, queue_id, req->int_vector_id, status);
2250                 return status;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int
2257 hns3_init_ring_with_vector(struct hns3_hw *hw)
2258 {
2259         uint16_t vec;
2260         int ret;
2261         int i;
2262
2263         /*
2264          * In hns3 network engine, vector 0 is always the misc interrupt of this
2265          * function, vector 1~N can be used respectively for the queues of the
2266          * function. Tx and Rx queues with the same number share the interrupt
2267          * vector. In the initialization clearing the all hardware mapping
2268          * relationship configurations between queues and interrupt vectors is
2269          * needed, so some error caused by the residual configurations, such as
2270          * the unexpected Tx interrupt, can be avoid.
2271          */
2272         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2273         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2274                 vec = vec - 1; /* the last interrupt is reserved */
2275         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2276         for (i = 0; i < hw->intr_tqps_num; i++) {
2277                 /*
2278                  * Set gap limiter/rate limiter/quanity limiter algorithm
2279                  * configuration for interrupt coalesce of queue's interrupt.
2280                  */
2281                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2282                                        HNS3_TQP_INTR_GL_DEFAULT);
2283                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2284                                        HNS3_TQP_INTR_GL_DEFAULT);
2285                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2286                 /*
2287                  * QL(quantity limiter) is not used currently, just set 0 to
2288                  * close it.
2289                  */
2290                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2291
2292                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2293                                                  HNS3_RING_TYPE_TX, i);
2294                 if (ret) {
2295                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2296                                           "vector: %u, ret=%d", i, vec, ret);
2297                         return ret;
2298                 }
2299
2300                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2301                                                  HNS3_RING_TYPE_RX, i);
2302                 if (ret) {
2303                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2304                                           "vector: %u, ret=%d", i, vec, ret);
2305                         return ret;
2306                 }
2307         }
2308
2309         return 0;
2310 }
2311
2312 static int
2313 hns3_dev_configure(struct rte_eth_dev *dev)
2314 {
2315         struct hns3_adapter *hns = dev->data->dev_private;
2316         struct rte_eth_conf *conf = &dev->data->dev_conf;
2317         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2318         struct hns3_hw *hw = &hns->hw;
2319         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2320         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2321         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2322         struct rte_eth_rss_conf rss_conf;
2323         uint16_t mtu;
2324         bool gro_en;
2325         int ret;
2326
2327         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2328
2329         /*
2330          * Some versions of hardware network engine does not support
2331          * individually enable/disable/reset the Tx or Rx queue. These devices
2332          * must enable/disable/reset Tx and Rx queues at the same time. When the
2333          * numbers of Tx queues allocated by upper applications are not equal to
2334          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2335          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2336          * work as usual. But these fake queues are imperceptible, and can not
2337          * be used by upper applications.
2338          */
2339         if (!hns3_dev_indep_txrx_supported(hw)) {
2340                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2341                 if (ret) {
2342                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2343                                  ret);
2344                         return ret;
2345                 }
2346         }
2347
2348         hw->adapter_state = HNS3_NIC_CONFIGURING;
2349         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2350                 hns3_err(hw, "setting link speed/duplex not supported");
2351                 ret = -EINVAL;
2352                 goto cfg_err;
2353         }
2354
2355         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2356                 ret = hns3_check_dcb_cfg(dev);
2357                 if (ret)
2358                         goto cfg_err;
2359         }
2360
2361         /* When RSS is not configured, redirect the packet queue 0 */
2362         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2363                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2364                 rss_conf = conf->rx_adv_conf.rss_conf;
2365                 hw->rss_dis_flag = false;
2366                 if (rss_conf.rss_key == NULL) {
2367                         rss_conf.rss_key = rss_cfg->key;
2368                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2369                 }
2370
2371                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2372                 if (ret)
2373                         goto cfg_err;
2374         }
2375
2376         /*
2377          * If jumbo frames are enabled, MTU needs to be refreshed
2378          * according to the maximum RX packet length.
2379          */
2380         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2381                 /*
2382                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2383                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2384                  * can safely assign to "uint16_t" type variable.
2385                  */
2386                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2387                 ret = hns3_dev_mtu_set(dev, mtu);
2388                 if (ret)
2389                         goto cfg_err;
2390                 dev->data->mtu = mtu;
2391         }
2392
2393         ret = hns3_dev_configure_vlan(dev);
2394         if (ret)
2395                 goto cfg_err;
2396
2397         /* config hardware GRO */
2398         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2399         ret = hns3_config_gro(hw, gro_en);
2400         if (ret)
2401                 goto cfg_err;
2402
2403         hns->rx_simple_allowed = true;
2404         hns->rx_vec_allowed = true;
2405         hns->tx_simple_allowed = true;
2406         hns->tx_vec_allowed = true;
2407
2408         hns3_init_rx_ptype_tble(dev);
2409         hw->adapter_state = HNS3_NIC_CONFIGURED;
2410
2411         return 0;
2412
2413 cfg_err:
2414         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2415         hw->adapter_state = HNS3_NIC_INITIALIZED;
2416
2417         return ret;
2418 }
2419
2420 static int
2421 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2422 {
2423         struct hns3_config_max_frm_size_cmd *req;
2424         struct hns3_cmd_desc desc;
2425
2426         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2427
2428         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2429         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2430         req->min_frm_size = RTE_ETHER_MIN_LEN;
2431
2432         return hns3_cmd_send(hw, &desc, 1);
2433 }
2434
2435 static int
2436 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2437 {
2438         int ret;
2439
2440         ret = hns3_set_mac_mtu(hw, mps);
2441         if (ret) {
2442                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2443                 return ret;
2444         }
2445
2446         ret = hns3_buffer_alloc(hw);
2447         if (ret)
2448                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2449
2450         return ret;
2451 }
2452
2453 static int
2454 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2455 {
2456         struct hns3_adapter *hns = dev->data->dev_private;
2457         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2458         struct hns3_hw *hw = &hns->hw;
2459         bool is_jumbo_frame;
2460         int ret;
2461
2462         if (dev->data->dev_started) {
2463                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2464                          "before configuration", dev->data->port_id);
2465                 return -EBUSY;
2466         }
2467
2468         rte_spinlock_lock(&hw->lock);
2469         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2470         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2471
2472         /*
2473          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2474          * assign to "uint16_t" type variable.
2475          */
2476         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2477         if (ret) {
2478                 rte_spinlock_unlock(&hw->lock);
2479                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2480                          dev->data->port_id, mtu, ret);
2481                 return ret;
2482         }
2483         hns->pf.mps = (uint16_t)frame_size;
2484         if (is_jumbo_frame)
2485                 dev->data->dev_conf.rxmode.offloads |=
2486                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2487         else
2488                 dev->data->dev_conf.rxmode.offloads &=
2489                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2490         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2491         rte_spinlock_unlock(&hw->lock);
2492
2493         return 0;
2494 }
2495
2496 int
2497 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2498 {
2499         struct hns3_adapter *hns = eth_dev->data->dev_private;
2500         struct hns3_hw *hw = &hns->hw;
2501         uint16_t queue_num = hw->tqps_num;
2502
2503         /*
2504          * In interrupt mode, 'max_rx_queues' is set based on the number of
2505          * MSI-X interrupt resources of the hardware.
2506          */
2507         if (hw->data->dev_conf.intr_conf.rxq == 1)
2508                 queue_num = hw->intr_tqps_num;
2509
2510         info->max_rx_queues = queue_num;
2511         info->max_tx_queues = hw->tqps_num;
2512         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2513         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2514         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2515         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2516         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2517         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2518                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2519                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2520                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2521                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2522                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2523                                  DEV_RX_OFFLOAD_KEEP_CRC |
2524                                  DEV_RX_OFFLOAD_SCATTER |
2525                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2526                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2527                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2528                                  DEV_RX_OFFLOAD_RSS_HASH |
2529                                  DEV_RX_OFFLOAD_TCP_LRO);
2530         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2531                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2532                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2533                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2534                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2535                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2536                                  DEV_TX_OFFLOAD_TCP_TSO |
2537                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2538                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2539                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2540                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2541                                  hns3_txvlan_cap_get(hw));
2542
2543         if (hns3_dev_indep_txrx_supported(hw))
2544                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2545                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2546
2547         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2548                 .nb_max = HNS3_MAX_RING_DESC,
2549                 .nb_min = HNS3_MIN_RING_DESC,
2550                 .nb_align = HNS3_ALIGN_RING_DESC,
2551         };
2552
2553         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2554                 .nb_max = HNS3_MAX_RING_DESC,
2555                 .nb_min = HNS3_MIN_RING_DESC,
2556                 .nb_align = HNS3_ALIGN_RING_DESC,
2557                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2558                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2559         };
2560
2561         info->default_rxconf = (struct rte_eth_rxconf) {
2562                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2563                 /*
2564                  * If there are no available Rx buffer descriptors, incoming
2565                  * packets are always dropped by hardware based on hns3 network
2566                  * engine.
2567                  */
2568                 .rx_drop_en = 1,
2569                 .offloads = 0,
2570         };
2571         info->default_txconf = (struct rte_eth_txconf) {
2572                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2573                 .offloads = 0,
2574         };
2575
2576         info->vmdq_queue_num = 0;
2577
2578         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2579         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2580         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2581
2582         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2583         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2584         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2585         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2586         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2587         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2588
2589         return 0;
2590 }
2591
2592 static int
2593 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2594                     size_t fw_size)
2595 {
2596         struct hns3_adapter *hns = eth_dev->data->dev_private;
2597         struct hns3_hw *hw = &hns->hw;
2598         uint32_t version = hw->fw_version;
2599         int ret;
2600
2601         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2602                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2603                                       HNS3_FW_VERSION_BYTE3_S),
2604                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2605                                       HNS3_FW_VERSION_BYTE2_S),
2606                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2607                                       HNS3_FW_VERSION_BYTE1_S),
2608                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2609                                       HNS3_FW_VERSION_BYTE0_S));
2610         ret += 1; /* add the size of '\0' */
2611         if (fw_size < (uint32_t)ret)
2612                 return ret;
2613         else
2614                 return 0;
2615 }
2616
2617 static int
2618 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2619                      __rte_unused int wait_to_complete)
2620 {
2621         struct hns3_adapter *hns = eth_dev->data->dev_private;
2622         struct hns3_hw *hw = &hns->hw;
2623         struct hns3_mac *mac = &hw->mac;
2624         struct rte_eth_link new_link;
2625
2626         if (!hns3_is_reset_pending(hns)) {
2627                 hns3_update_speed_duplex(eth_dev);
2628                 hns3_update_link_status(hw);
2629         }
2630
2631         memset(&new_link, 0, sizeof(new_link));
2632         switch (mac->link_speed) {
2633         case ETH_SPEED_NUM_10M:
2634         case ETH_SPEED_NUM_100M:
2635         case ETH_SPEED_NUM_1G:
2636         case ETH_SPEED_NUM_10G:
2637         case ETH_SPEED_NUM_25G:
2638         case ETH_SPEED_NUM_40G:
2639         case ETH_SPEED_NUM_50G:
2640         case ETH_SPEED_NUM_100G:
2641         case ETH_SPEED_NUM_200G:
2642                 new_link.link_speed = mac->link_speed;
2643                 break;
2644         default:
2645                 new_link.link_speed = ETH_SPEED_NUM_100M;
2646                 break;
2647         }
2648
2649         new_link.link_duplex = mac->link_duplex;
2650         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2651         new_link.link_autoneg =
2652             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2653
2654         return rte_eth_linkstatus_set(eth_dev, &new_link);
2655 }
2656
2657 static int
2658 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2659 {
2660         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2661         struct hns3_pf *pf = &hns->pf;
2662
2663         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2664                 return -EINVAL;
2665
2666         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2667
2668         return 0;
2669 }
2670
2671 static int
2672 hns3_query_function_status(struct hns3_hw *hw)
2673 {
2674 #define HNS3_QUERY_MAX_CNT              10
2675 #define HNS3_QUERY_SLEEP_MSCOEND        1
2676         struct hns3_func_status_cmd *req;
2677         struct hns3_cmd_desc desc;
2678         int timeout = 0;
2679         int ret;
2680
2681         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2682         req = (struct hns3_func_status_cmd *)desc.data;
2683
2684         do {
2685                 ret = hns3_cmd_send(hw, &desc, 1);
2686                 if (ret) {
2687                         PMD_INIT_LOG(ERR, "query function status failed %d",
2688                                      ret);
2689                         return ret;
2690                 }
2691
2692                 /* Check pf reset is done */
2693                 if (req->pf_state)
2694                         break;
2695
2696                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2697         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2698
2699         return hns3_parse_func_status(hw, req);
2700 }
2701
2702 static int
2703 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2704 {
2705         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2706         struct hns3_pf *pf = &hns->pf;
2707
2708         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2709                 /*
2710                  * The total_tqps_num obtained from firmware is maximum tqp
2711                  * numbers of this port, which should be used for PF and VFs.
2712                  * There is no need for pf to have so many tqp numbers in
2713                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2714                  * coming from config file, is assigned to maximum queue number
2715                  * for the PF of this port by user. So users can modify the
2716                  * maximum queue number of PF according to their own application
2717                  * scenarios, which is more flexible to use. In addition, many
2718                  * memories can be saved due to allocating queue statistics
2719                  * room according to the actual number of queues required. The
2720                  * maximum queue number of PF for network engine with
2721                  * revision_id greater than 0x30 is assigned by config file.
2722                  */
2723                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2724                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2725                                  "must be greater than 0.",
2726                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2727                         return -EINVAL;
2728                 }
2729
2730                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2731                                        hw->total_tqps_num);
2732         } else {
2733                 /*
2734                  * Due to the limitation on the number of PF interrupts
2735                  * available, the maximum queue number assigned to PF on
2736                  * the network engine with revision_id 0x21 is 64.
2737                  */
2738                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2739                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2740         }
2741
2742         return 0;
2743 }
2744
2745 static int
2746 hns3_query_pf_resource(struct hns3_hw *hw)
2747 {
2748         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2749         struct hns3_pf *pf = &hns->pf;
2750         struct hns3_pf_res_cmd *req;
2751         struct hns3_cmd_desc desc;
2752         int ret;
2753
2754         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2755         ret = hns3_cmd_send(hw, &desc, 1);
2756         if (ret) {
2757                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2758                 return ret;
2759         }
2760
2761         req = (struct hns3_pf_res_cmd *)desc.data;
2762         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2763                              rte_le_to_cpu_16(req->ext_tqp_num);
2764         ret = hns3_get_pf_max_tqp_num(hw);
2765         if (ret)
2766                 return ret;
2767
2768         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2769         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2770
2771         if (req->tx_buf_size)
2772                 pf->tx_buf_size =
2773                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2774         else
2775                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2776
2777         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2778
2779         if (req->dv_buf_size)
2780                 pf->dv_buf_size =
2781                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2782         else
2783                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2784
2785         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2786
2787         hw->num_msi =
2788                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2789                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2790
2791         return 0;
2792 }
2793
2794 static void
2795 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2796 {
2797         struct hns3_cfg_param_cmd *req;
2798         uint64_t mac_addr_tmp_high;
2799         uint8_t ext_rss_size_max;
2800         uint64_t mac_addr_tmp;
2801         uint32_t i;
2802
2803         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2804
2805         /* get the configuration */
2806         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2807                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2808         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2809                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2810         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2811                                            HNS3_CFG_TQP_DESC_N_M,
2812                                            HNS3_CFG_TQP_DESC_N_S);
2813
2814         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2815                                        HNS3_CFG_PHY_ADDR_M,
2816                                        HNS3_CFG_PHY_ADDR_S);
2817         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2818                                          HNS3_CFG_MEDIA_TP_M,
2819                                          HNS3_CFG_MEDIA_TP_S);
2820         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2821                                          HNS3_CFG_RX_BUF_LEN_M,
2822                                          HNS3_CFG_RX_BUF_LEN_S);
2823         /* get mac address */
2824         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2825         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2826                                            HNS3_CFG_MAC_ADDR_H_M,
2827                                            HNS3_CFG_MAC_ADDR_H_S);
2828
2829         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2830
2831         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2832                                             HNS3_CFG_DEFAULT_SPEED_M,
2833                                             HNS3_CFG_DEFAULT_SPEED_S);
2834         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2835                                            HNS3_CFG_RSS_SIZE_M,
2836                                            HNS3_CFG_RSS_SIZE_S);
2837
2838         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2839                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2840
2841         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2842         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2843
2844         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2845                                             HNS3_CFG_SPEED_ABILITY_M,
2846                                             HNS3_CFG_SPEED_ABILITY_S);
2847         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2848                                         HNS3_CFG_UMV_TBL_SPACE_M,
2849                                         HNS3_CFG_UMV_TBL_SPACE_S);
2850         if (!cfg->umv_space)
2851                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2852
2853         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2854                                                HNS3_CFG_EXT_RSS_SIZE_M,
2855                                                HNS3_CFG_EXT_RSS_SIZE_S);
2856
2857         /*
2858          * Field ext_rss_size_max obtained from firmware will be more flexible
2859          * for future changes and expansions, which is an exponent of 2, instead
2860          * of reading out directly. If this field is not zero, hns3 PF PMD
2861          * driver uses it as rss_size_max under one TC. Device, whose revision
2862          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2863          * maximum number of queues supported under a TC through this field.
2864          */
2865         if (ext_rss_size_max)
2866                 cfg->rss_size_max = 1U << ext_rss_size_max;
2867 }
2868
2869 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2870  * @hw: pointer to struct hns3_hw
2871  * @hcfg: the config structure to be getted
2872  */
2873 static int
2874 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2875 {
2876         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2877         struct hns3_cfg_param_cmd *req;
2878         uint32_t offset;
2879         uint32_t i;
2880         int ret;
2881
2882         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2883                 offset = 0;
2884                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2885                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2886                                           true);
2887                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2888                                i * HNS3_CFG_RD_LEN_BYTES);
2889                 /* Len should be divided by 4 when send to hardware */
2890                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2891                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2892                 req->offset = rte_cpu_to_le_32(offset);
2893         }
2894
2895         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2896         if (ret) {
2897                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2898                 return ret;
2899         }
2900
2901         hns3_parse_cfg(hcfg, desc);
2902
2903         return 0;
2904 }
2905
2906 static int
2907 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2908 {
2909         switch (speed_cmd) {
2910         case HNS3_CFG_SPEED_10M:
2911                 *speed = ETH_SPEED_NUM_10M;
2912                 break;
2913         case HNS3_CFG_SPEED_100M:
2914                 *speed = ETH_SPEED_NUM_100M;
2915                 break;
2916         case HNS3_CFG_SPEED_1G:
2917                 *speed = ETH_SPEED_NUM_1G;
2918                 break;
2919         case HNS3_CFG_SPEED_10G:
2920                 *speed = ETH_SPEED_NUM_10G;
2921                 break;
2922         case HNS3_CFG_SPEED_25G:
2923                 *speed = ETH_SPEED_NUM_25G;
2924                 break;
2925         case HNS3_CFG_SPEED_40G:
2926                 *speed = ETH_SPEED_NUM_40G;
2927                 break;
2928         case HNS3_CFG_SPEED_50G:
2929                 *speed = ETH_SPEED_NUM_50G;
2930                 break;
2931         case HNS3_CFG_SPEED_100G:
2932                 *speed = ETH_SPEED_NUM_100G;
2933                 break;
2934         case HNS3_CFG_SPEED_200G:
2935                 *speed = ETH_SPEED_NUM_200G;
2936                 break;
2937         default:
2938                 return -EINVAL;
2939         }
2940
2941         return 0;
2942 }
2943
2944 static void
2945 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2946 {
2947         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2948         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2949         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2950         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2951         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2952 }
2953
2954 static void
2955 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2956 {
2957         struct hns3_dev_specs_0_cmd *req0;
2958
2959         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2960
2961         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2962         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2963         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2964         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2965         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2966 }
2967
2968 static int
2969 hns3_query_dev_specifications(struct hns3_hw *hw)
2970 {
2971         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2972         int ret;
2973         int i;
2974
2975         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2976                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2977                                           true);
2978                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2979         }
2980         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2981
2982         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2983         if (ret)
2984                 return ret;
2985
2986         hns3_parse_dev_specifications(hw, desc);
2987
2988         return 0;
2989 }
2990
2991 static int
2992 hns3_get_capability(struct hns3_hw *hw)
2993 {
2994         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2995         struct rte_pci_device *pci_dev;
2996         struct hns3_pf *pf = &hns->pf;
2997         struct rte_eth_dev *eth_dev;
2998         uint16_t device_id;
2999         uint8_t revision;
3000         int ret;
3001
3002         eth_dev = &rte_eth_devices[hw->data->port_id];
3003         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3004         device_id = pci_dev->id.device_id;
3005
3006         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3007             device_id == HNS3_DEV_ID_50GE_RDMA ||
3008             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3009             device_id == HNS3_DEV_ID_200G_RDMA)
3010                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3011
3012         /* Get PCI revision id */
3013         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3014                                   HNS3_PCI_REVISION_ID);
3015         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3016                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3017                              ret);
3018                 return -EIO;
3019         }
3020         hw->revision = revision;
3021
3022         if (revision < PCI_REVISION_ID_HIP09_A) {
3023                 hns3_set_default_dev_specifications(hw);
3024                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3025                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3026                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3027                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3028                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3029                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3030                 hw->rss_info.ipv6_sctp_offload_supported = false;
3031                 return 0;
3032         }
3033
3034         ret = hns3_query_dev_specifications(hw);
3035         if (ret) {
3036                 PMD_INIT_LOG(ERR,
3037                              "failed to query dev specifications, ret = %d",
3038                              ret);
3039                 return ret;
3040         }
3041
3042         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3043         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3044         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3045         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3046         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3047         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3048         hw->rss_info.ipv6_sctp_offload_supported = true;
3049
3050         return 0;
3051 }
3052
3053 static int
3054 hns3_get_board_configuration(struct hns3_hw *hw)
3055 {
3056         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3057         struct hns3_pf *pf = &hns->pf;
3058         struct hns3_cfg cfg;
3059         int ret;
3060
3061         ret = hns3_get_board_cfg(hw, &cfg);
3062         if (ret) {
3063                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3064                 return ret;
3065         }
3066
3067         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3068             !hns3_dev_copper_supported(hw)) {
3069                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3070                 return -EOPNOTSUPP;
3071         }
3072
3073         hw->mac.media_type = cfg.media_type;
3074         hw->rss_size_max = cfg.rss_size_max;
3075         hw->rss_dis_flag = false;
3076         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3077         hw->mac.phy_addr = cfg.phy_addr;
3078         hw->mac.default_addr_setted = false;
3079         hw->num_tx_desc = cfg.tqp_desc_num;
3080         hw->num_rx_desc = cfg.tqp_desc_num;
3081         hw->dcb_info.num_pg = 1;
3082         hw->dcb_info.hw_pfc_map = 0;
3083
3084         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3085         if (ret) {
3086                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3087                              cfg.default_speed, ret);
3088                 return ret;
3089         }
3090
3091         pf->tc_max = cfg.tc_num;
3092         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3093                 PMD_INIT_LOG(WARNING,
3094                              "Get TC num(%u) from flash, set TC num to 1",
3095                              pf->tc_max);
3096                 pf->tc_max = 1;
3097         }
3098
3099         /* Dev does not support DCB */
3100         if (!hns3_dev_dcb_supported(hw)) {
3101                 pf->tc_max = 1;
3102                 pf->pfc_max = 0;
3103         } else
3104                 pf->pfc_max = pf->tc_max;
3105
3106         hw->dcb_info.num_tc = 1;
3107         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3108                                      hw->tqps_num / hw->dcb_info.num_tc);
3109         hns3_set_bit(hw->hw_tc_map, 0, 1);
3110         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3111
3112         pf->wanted_umv_size = cfg.umv_space;
3113
3114         return ret;
3115 }
3116
3117 static int
3118 hns3_get_configuration(struct hns3_hw *hw)
3119 {
3120         int ret;
3121
3122         ret = hns3_query_function_status(hw);
3123         if (ret) {
3124                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3125                 return ret;
3126         }
3127
3128         /* Get device capability */
3129         ret = hns3_get_capability(hw);
3130         if (ret) {
3131                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3132                 return ret;
3133         }
3134
3135         /* Get pf resource */
3136         ret = hns3_query_pf_resource(hw);
3137         if (ret) {
3138                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3139                 return ret;
3140         }
3141
3142         ret = hns3_get_board_configuration(hw);
3143         if (ret) {
3144                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3145                 return ret;
3146         }
3147
3148         ret = hns3_query_dev_fec_info(hw);
3149         if (ret)
3150                 PMD_INIT_LOG(ERR,
3151                              "failed to query FEC information, ret = %d", ret);
3152
3153         return ret;
3154 }
3155
3156 static int
3157 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3158                       uint16_t tqp_vid, bool is_pf)
3159 {
3160         struct hns3_tqp_map_cmd *req;
3161         struct hns3_cmd_desc desc;
3162         int ret;
3163
3164         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3165
3166         req = (struct hns3_tqp_map_cmd *)desc.data;
3167         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3168         req->tqp_vf = func_id;
3169         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3170         if (!is_pf)
3171                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3172         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3173
3174         ret = hns3_cmd_send(hw, &desc, 1);
3175         if (ret)
3176                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3177
3178         return ret;
3179 }
3180
3181 static int
3182 hns3_map_tqp(struct hns3_hw *hw)
3183 {
3184         int ret;
3185         int i;
3186
3187         /*
3188          * In current version, VF is not supported when PF is driven by DPDK
3189          * driver, so we assign total tqps_num tqps allocated to this port
3190          * to PF.
3191          */
3192         for (i = 0; i < hw->total_tqps_num; i++) {
3193                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3194                 if (ret)
3195                         return ret;
3196         }
3197
3198         return 0;
3199 }
3200
3201 static int
3202 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3203 {
3204         struct hns3_config_mac_speed_dup_cmd *req;
3205         struct hns3_cmd_desc desc;
3206         int ret;
3207
3208         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3209
3210         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3211
3212         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3213
3214         switch (speed) {
3215         case ETH_SPEED_NUM_10M:
3216                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3217                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3218                 break;
3219         case ETH_SPEED_NUM_100M:
3220                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3221                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3222                 break;
3223         case ETH_SPEED_NUM_1G:
3224                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3225                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3226                 break;
3227         case ETH_SPEED_NUM_10G:
3228                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3229                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3230                 break;
3231         case ETH_SPEED_NUM_25G:
3232                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3234                 break;
3235         case ETH_SPEED_NUM_40G:
3236                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3238                 break;
3239         case ETH_SPEED_NUM_50G:
3240                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3242                 break;
3243         case ETH_SPEED_NUM_100G:
3244                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3245                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3246                 break;
3247         case ETH_SPEED_NUM_200G:
3248                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3250                 break;
3251         default:
3252                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3253                 return -EINVAL;
3254         }
3255
3256         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3257
3258         ret = hns3_cmd_send(hw, &desc, 1);
3259         if (ret)
3260                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3261
3262         return ret;
3263 }
3264
3265 static int
3266 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3267 {
3268         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3269         struct hns3_pf *pf = &hns->pf;
3270         struct hns3_priv_buf *priv;
3271         uint32_t i, total_size;
3272
3273         total_size = pf->pkt_buf_size;
3274
3275         /* alloc tx buffer for all enabled tc */
3276         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3277                 priv = &buf_alloc->priv_buf[i];
3278
3279                 if (hw->hw_tc_map & BIT(i)) {
3280                         if (total_size < pf->tx_buf_size)
3281                                 return -ENOMEM;
3282
3283                         priv->tx_buf_size = pf->tx_buf_size;
3284                 } else
3285                         priv->tx_buf_size = 0;
3286
3287                 total_size -= priv->tx_buf_size;
3288         }
3289
3290         return 0;
3291 }
3292
3293 static int
3294 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3295 {
3296 /* TX buffer size is unit by 128 byte */
3297 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3298 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3299         struct hns3_tx_buff_alloc_cmd *req;
3300         struct hns3_cmd_desc desc;
3301         uint32_t buf_size;
3302         uint32_t i;
3303         int ret;
3304
3305         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3306
3307         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3308         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3309                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3310
3311                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3312                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3313                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3314         }
3315
3316         ret = hns3_cmd_send(hw, &desc, 1);
3317         if (ret)
3318                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3319
3320         return ret;
3321 }
3322
3323 static int
3324 hns3_get_tc_num(struct hns3_hw *hw)
3325 {
3326         int cnt = 0;
3327         uint8_t i;
3328
3329         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3330                 if (hw->hw_tc_map & BIT(i))
3331                         cnt++;
3332         return cnt;
3333 }
3334
3335 static uint32_t
3336 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3337 {
3338         struct hns3_priv_buf *priv;
3339         uint32_t rx_priv = 0;
3340         int i;
3341
3342         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3343                 priv = &buf_alloc->priv_buf[i];
3344                 if (priv->enable)
3345                         rx_priv += priv->buf_size;
3346         }
3347         return rx_priv;
3348 }
3349
3350 static uint32_t
3351 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3352 {
3353         uint32_t total_tx_size = 0;
3354         uint32_t i;
3355
3356         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3357                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3358
3359         return total_tx_size;
3360 }
3361
3362 /* Get the number of pfc enabled TCs, which have private buffer */
3363 static int
3364 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3365 {
3366         struct hns3_priv_buf *priv;
3367         int cnt = 0;
3368         uint8_t i;
3369
3370         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3371                 priv = &buf_alloc->priv_buf[i];
3372                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3373                         cnt++;
3374         }
3375
3376         return cnt;
3377 }
3378
3379 /* Get the number of pfc disabled TCs, which have private buffer */
3380 static int
3381 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3382                          struct hns3_pkt_buf_alloc *buf_alloc)
3383 {
3384         struct hns3_priv_buf *priv;
3385         int cnt = 0;
3386         uint8_t i;
3387
3388         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3389                 priv = &buf_alloc->priv_buf[i];
3390                 if (hw->hw_tc_map & BIT(i) &&
3391                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3392                         cnt++;
3393         }
3394
3395         return cnt;
3396 }
3397
3398 static bool
3399 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3400                   uint32_t rx_all)
3401 {
3402         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3403         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3404         struct hns3_pf *pf = &hns->pf;
3405         uint32_t shared_buf, aligned_mps;
3406         uint32_t rx_priv;
3407         uint8_t tc_num;
3408         uint8_t i;
3409
3410         tc_num = hns3_get_tc_num(hw);
3411         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3412
3413         if (hns3_dev_dcb_supported(hw))
3414                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3415                                         pf->dv_buf_size;
3416         else
3417                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3418                                         + pf->dv_buf_size;
3419
3420         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3421         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3422                              HNS3_BUF_SIZE_UNIT);
3423
3424         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3425         if (rx_all < rx_priv + shared_std)
3426                 return false;
3427
3428         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3429         buf_alloc->s_buf.buf_size = shared_buf;
3430         if (hns3_dev_dcb_supported(hw)) {
3431                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3432                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3433                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3434                                   HNS3_BUF_SIZE_UNIT);
3435         } else {
3436                 buf_alloc->s_buf.self.high =
3437                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3438                 buf_alloc->s_buf.self.low = aligned_mps;
3439         }
3440
3441         if (hns3_dev_dcb_supported(hw)) {
3442                 hi_thrd = shared_buf - pf->dv_buf_size;
3443
3444                 if (tc_num <= NEED_RESERVE_TC_NUM)
3445                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3446                                   BUF_MAX_PERCENT;
3447
3448                 if (tc_num)
3449                         hi_thrd = hi_thrd / tc_num;
3450
3451                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3452                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3453                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3454         } else {
3455                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3456                 lo_thrd = aligned_mps;
3457         }
3458
3459         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3460                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3461                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3462         }
3463
3464         return true;
3465 }
3466
3467 static bool
3468 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3469                      struct hns3_pkt_buf_alloc *buf_alloc)
3470 {
3471         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3472         struct hns3_pf *pf = &hns->pf;
3473         struct hns3_priv_buf *priv;
3474         uint32_t aligned_mps;
3475         uint32_t rx_all;
3476         uint8_t i;
3477
3478         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3479         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3480
3481         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3482                 priv = &buf_alloc->priv_buf[i];
3483
3484                 priv->enable = 0;
3485                 priv->wl.low = 0;
3486                 priv->wl.high = 0;
3487                 priv->buf_size = 0;
3488
3489                 if (!(hw->hw_tc_map & BIT(i)))
3490                         continue;
3491
3492                 priv->enable = 1;
3493                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3494                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3495                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3496                                                 HNS3_BUF_SIZE_UNIT);
3497                 } else {
3498                         priv->wl.low = 0;
3499                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3500                                         aligned_mps;
3501                 }
3502
3503                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3504         }
3505
3506         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3507 }
3508
3509 static bool
3510 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3511                              struct hns3_pkt_buf_alloc *buf_alloc)
3512 {
3513         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3514         struct hns3_pf *pf = &hns->pf;
3515         struct hns3_priv_buf *priv;
3516         int no_pfc_priv_num;
3517         uint32_t rx_all;
3518         uint8_t mask;
3519         int i;
3520
3521         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3522         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3523
3524         /* let the last to be cleared first */
3525         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3526                 priv = &buf_alloc->priv_buf[i];
3527                 mask = BIT((uint8_t)i);
3528
3529                 if (hw->hw_tc_map & mask &&
3530                     !(hw->dcb_info.hw_pfc_map & mask)) {
3531                         /* Clear the no pfc TC private buffer */
3532                         priv->wl.low = 0;
3533                         priv->wl.high = 0;
3534                         priv->buf_size = 0;
3535                         priv->enable = 0;
3536                         no_pfc_priv_num--;
3537                 }
3538
3539                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3540                     no_pfc_priv_num == 0)
3541                         break;
3542         }
3543
3544         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3545 }
3546
3547 static bool
3548 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3549                            struct hns3_pkt_buf_alloc *buf_alloc)
3550 {
3551         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3552         struct hns3_pf *pf = &hns->pf;
3553         struct hns3_priv_buf *priv;
3554         uint32_t rx_all;
3555         int pfc_priv_num;
3556         uint8_t mask;
3557         int i;
3558
3559         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3560         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3561
3562         /* let the last to be cleared first */
3563         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3564                 priv = &buf_alloc->priv_buf[i];
3565                 mask = BIT((uint8_t)i);
3566                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3567                         /* Reduce the number of pfc TC with private buffer */
3568                         priv->wl.low = 0;
3569                         priv->enable = 0;
3570                         priv->wl.high = 0;
3571                         priv->buf_size = 0;
3572                         pfc_priv_num--;
3573                 }
3574                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3575                     pfc_priv_num == 0)
3576                         break;
3577         }
3578
3579         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3580 }
3581
3582 static bool
3583 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3584                           struct hns3_pkt_buf_alloc *buf_alloc)
3585 {
3586 #define COMPENSATE_BUFFER       0x3C00
3587 #define COMPENSATE_HALF_MPS_NUM 5
3588 #define PRIV_WL_GAP             0x1800
3589         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3590         struct hns3_pf *pf = &hns->pf;
3591         uint32_t tc_num = hns3_get_tc_num(hw);
3592         uint32_t half_mps = pf->mps >> 1;
3593         struct hns3_priv_buf *priv;
3594         uint32_t min_rx_priv;
3595         uint32_t rx_priv;
3596         uint8_t i;
3597
3598         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3599         if (tc_num)
3600                 rx_priv = rx_priv / tc_num;
3601
3602         if (tc_num <= NEED_RESERVE_TC_NUM)
3603                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3604
3605         /*
3606          * Minimum value of private buffer in rx direction (min_rx_priv) is
3607          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3608          * buffer if rx_priv is greater than min_rx_priv.
3609          */
3610         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3611                         COMPENSATE_HALF_MPS_NUM * half_mps;
3612         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3613         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3614
3615         if (rx_priv < min_rx_priv)
3616                 return false;
3617
3618         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3619                 priv = &buf_alloc->priv_buf[i];
3620                 priv->enable = 0;
3621                 priv->wl.low = 0;
3622                 priv->wl.high = 0;
3623                 priv->buf_size = 0;
3624
3625                 if (!(hw->hw_tc_map & BIT(i)))
3626                         continue;
3627
3628                 priv->enable = 1;
3629                 priv->buf_size = rx_priv;
3630                 priv->wl.high = rx_priv - pf->dv_buf_size;
3631                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3632         }
3633
3634         buf_alloc->s_buf.buf_size = 0;
3635
3636         return true;
3637 }
3638
3639 /*
3640  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3641  * @hw: pointer to struct hns3_hw
3642  * @buf_alloc: pointer to buffer calculation data
3643  * @return: 0: calculate sucessful, negative: fail
3644  */
3645 static int
3646 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3647 {
3648         /* When DCB is not supported, rx private buffer is not allocated. */
3649         if (!hns3_dev_dcb_supported(hw)) {
3650                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3651                 struct hns3_pf *pf = &hns->pf;
3652                 uint32_t rx_all = pf->pkt_buf_size;
3653
3654                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3655                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3656                         return -ENOMEM;
3657
3658                 return 0;
3659         }
3660
3661         /*
3662          * Try to allocate privated packet buffer for all TCs without share
3663          * buffer.
3664          */
3665         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3666                 return 0;
3667
3668         /*
3669          * Try to allocate privated packet buffer for all TCs with share
3670          * buffer.
3671          */
3672         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3673                 return 0;
3674
3675         /*
3676          * For different application scenes, the enabled port number, TC number
3677          * and no_drop TC number are different. In order to obtain the better
3678          * performance, software could allocate the buffer size and configure
3679          * the waterline by tring to decrease the private buffer size according
3680          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3681          * enabled tc.
3682          */
3683         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3684                 return 0;
3685
3686         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3687                 return 0;
3688
3689         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3690                 return 0;
3691
3692         return -ENOMEM;
3693 }
3694
3695 static int
3696 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3697 {
3698         struct hns3_rx_priv_buff_cmd *req;
3699         struct hns3_cmd_desc desc;
3700         uint32_t buf_size;
3701         int ret;
3702         int i;
3703
3704         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3705         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3706
3707         /* Alloc private buffer TCs */
3708         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3709                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3710
3711                 req->buf_num[i] =
3712                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3713                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3714         }
3715
3716         buf_size = buf_alloc->s_buf.buf_size;
3717         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3718                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3719
3720         ret = hns3_cmd_send(hw, &desc, 1);
3721         if (ret)
3722                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3723
3724         return ret;
3725 }
3726
3727 static int
3728 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3729 {
3730 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3731         struct hns3_rx_priv_wl_buf *req;
3732         struct hns3_priv_buf *priv;
3733         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3734         int i, j;
3735         int ret;
3736
3737         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3738                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3739                                           false);
3740                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3741
3742                 /* The first descriptor set the NEXT bit to 1 */
3743                 if (i == 0)
3744                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3745                 else
3746                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3747
3748                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3749                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3750
3751                         priv = &buf_alloc->priv_buf[idx];
3752                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3753                                                         HNS3_BUF_UNIT_S);
3754                         req->tc_wl[j].high |=
3755                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3756                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3757                                                         HNS3_BUF_UNIT_S);
3758                         req->tc_wl[j].low |=
3759                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3760                 }
3761         }
3762
3763         /* Send 2 descriptor at one time */
3764         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3765         if (ret)
3766                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3767                              ret);
3768         return ret;
3769 }
3770
3771 static int
3772 hns3_common_thrd_config(struct hns3_hw *hw,
3773                         struct hns3_pkt_buf_alloc *buf_alloc)
3774 {
3775 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3776         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3777         struct hns3_rx_com_thrd *req;
3778         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3779         struct hns3_tc_thrd *tc;
3780         int tc_idx;
3781         int i, j;
3782         int ret;
3783
3784         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3785                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3786                                           false);
3787                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3788
3789                 /* The first descriptor set the NEXT bit to 1 */
3790                 if (i == 0)
3791                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3792                 else
3793                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3794
3795                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3796                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3797                         tc = &s_buf->tc_thrd[tc_idx];
3798
3799                         req->com_thrd[j].high =
3800                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3801                         req->com_thrd[j].high |=
3802                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3803                         req->com_thrd[j].low =
3804                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3805                         req->com_thrd[j].low |=
3806                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3807                 }
3808         }
3809
3810         /* Send 2 descriptors at one time */
3811         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3812         if (ret)
3813                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3814
3815         return ret;
3816 }
3817
3818 static int
3819 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3820 {
3821         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3822         struct hns3_rx_com_wl *req;
3823         struct hns3_cmd_desc desc;
3824         int ret;
3825
3826         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3827
3828         req = (struct hns3_rx_com_wl *)desc.data;
3829         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3830         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3831
3832         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3833         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3834
3835         ret = hns3_cmd_send(hw, &desc, 1);
3836         if (ret)
3837                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3838
3839         return ret;
3840 }
3841
3842 int
3843 hns3_buffer_alloc(struct hns3_hw *hw)
3844 {
3845         struct hns3_pkt_buf_alloc pkt_buf;
3846         int ret;
3847
3848         memset(&pkt_buf, 0, sizeof(pkt_buf));
3849         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3850         if (ret) {
3851                 PMD_INIT_LOG(ERR,
3852                              "could not calc tx buffer size for all TCs %d",
3853                              ret);
3854                 return ret;
3855         }
3856
3857         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3858         if (ret) {
3859                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3860                 return ret;
3861         }
3862
3863         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3864         if (ret) {
3865                 PMD_INIT_LOG(ERR,
3866                              "could not calc rx priv buffer size for all TCs %d",
3867                              ret);
3868                 return ret;
3869         }
3870
3871         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3872         if (ret) {
3873                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3874                 return ret;
3875         }
3876
3877         if (hns3_dev_dcb_supported(hw)) {
3878                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3879                 if (ret) {
3880                         PMD_INIT_LOG(ERR,
3881                                      "could not configure rx private waterline %d",
3882                                      ret);
3883                         return ret;
3884                 }
3885
3886                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3887                 if (ret) {
3888                         PMD_INIT_LOG(ERR,
3889                                      "could not configure common threshold %d",
3890                                      ret);
3891                         return ret;
3892                 }
3893         }
3894
3895         ret = hns3_common_wl_config(hw, &pkt_buf);
3896         if (ret)
3897                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3898                              ret);
3899
3900         return ret;
3901 }
3902
3903 static int
3904 hns3_mac_init(struct hns3_hw *hw)
3905 {
3906         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3907         struct hns3_mac *mac = &hw->mac;
3908         struct hns3_pf *pf = &hns->pf;
3909         int ret;
3910
3911         pf->support_sfp_query = true;
3912         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3913         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3914         if (ret) {
3915                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3916                 return ret;
3917         }
3918
3919         mac->link_status = ETH_LINK_DOWN;
3920
3921         return hns3_config_mtu(hw, pf->mps);
3922 }
3923
3924 static int
3925 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3926 {
3927 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3928 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3929 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3930 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3931         int return_status;
3932
3933         if (cmdq_resp) {
3934                 PMD_INIT_LOG(ERR,
3935                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3936                              cmdq_resp);
3937                 return -EIO;
3938         }
3939
3940         switch (resp_code) {
3941         case HNS3_ETHERTYPE_SUCCESS_ADD:
3942         case HNS3_ETHERTYPE_ALREADY_ADD:
3943                 return_status = 0;
3944                 break;
3945         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3946                 PMD_INIT_LOG(ERR,
3947                              "add mac ethertype failed for manager table overflow.");
3948                 return_status = -EIO;
3949                 break;
3950         case HNS3_ETHERTYPE_KEY_CONFLICT:
3951                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3952                 return_status = -EIO;
3953                 break;
3954         default:
3955                 PMD_INIT_LOG(ERR,
3956                              "add mac ethertype failed for undefined, code=%u.",
3957                              resp_code);
3958                 return_status = -EIO;
3959                 break;
3960         }
3961
3962         return return_status;
3963 }
3964
3965 static int
3966 hns3_add_mgr_tbl(struct hns3_hw *hw,
3967                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3968 {
3969         struct hns3_cmd_desc desc;
3970         uint8_t resp_code;
3971         uint16_t retval;
3972         int ret;
3973
3974         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3975         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3976
3977         ret = hns3_cmd_send(hw, &desc, 1);
3978         if (ret) {
3979                 PMD_INIT_LOG(ERR,
3980                              "add mac ethertype failed for cmd_send, ret =%d.",
3981                              ret);
3982                 return ret;
3983         }
3984
3985         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3986         retval = rte_le_to_cpu_16(desc.retval);
3987
3988         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3989 }
3990
3991 static void
3992 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3993                      int *table_item_num)
3994 {
3995         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3996
3997         /*
3998          * In current version, we add one item in management table as below:
3999          * 0x0180C200000E -- LLDP MC address
4000          */
4001         tbl = mgr_table;
4002         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4003         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4004         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4005         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4006         tbl->i_port_bitmap = 0x1;
4007         *table_item_num = 1;
4008 }
4009
4010 static int
4011 hns3_init_mgr_tbl(struct hns3_hw *hw)
4012 {
4013 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4014         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4015         int table_item_num;
4016         int ret;
4017         int i;
4018
4019         memset(mgr_table, 0, sizeof(mgr_table));
4020         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4021         for (i = 0; i < table_item_num; i++) {
4022                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4023                 if (ret) {
4024                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4025                                      ret);
4026                         return ret;
4027                 }
4028         }
4029
4030         return 0;
4031 }
4032
4033 static void
4034 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4035                         bool en_mc, bool en_bc, int vport_id)
4036 {
4037         if (!param)
4038                 return;
4039
4040         memset(param, 0, sizeof(struct hns3_promisc_param));
4041         if (en_uc)
4042                 param->enable = HNS3_PROMISC_EN_UC;
4043         if (en_mc)
4044                 param->enable |= HNS3_PROMISC_EN_MC;
4045         if (en_bc)
4046                 param->enable |= HNS3_PROMISC_EN_BC;
4047         param->vf_id = vport_id;
4048 }
4049
4050 static int
4051 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4052 {
4053         struct hns3_promisc_cfg_cmd *req;
4054         struct hns3_cmd_desc desc;
4055         int ret;
4056
4057         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4058
4059         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4060         req->vf_id = param->vf_id;
4061         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4062             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4063
4064         ret = hns3_cmd_send(hw, &desc, 1);
4065         if (ret)
4066                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4067
4068         return ret;
4069 }
4070
4071 static int
4072 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4073 {
4074         struct hns3_promisc_param param;
4075         bool en_bc_pmc = true;
4076         uint8_t vf_id;
4077
4078         /*
4079          * In current version VF is not supported when PF is driven by DPDK
4080          * driver, just need to configure parameters for PF vport.
4081          */
4082         vf_id = HNS3_PF_FUNC_ID;
4083
4084         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4085         return hns3_cmd_set_promisc_mode(hw, &param);
4086 }
4087
4088 static int
4089 hns3_promisc_init(struct hns3_hw *hw)
4090 {
4091         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4092         struct hns3_pf *pf = &hns->pf;
4093         struct hns3_promisc_param param;
4094         uint16_t func_id;
4095         int ret;
4096
4097         ret = hns3_set_promisc_mode(hw, false, false);
4098         if (ret) {
4099                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4100                 return ret;
4101         }
4102
4103         /*
4104          * In current version VFs are not supported when PF is driven by DPDK
4105          * driver. After PF has been taken over by DPDK, the original VF will
4106          * be invalid. So, there is a possibility of entry residues. It should
4107          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4108          * during init.
4109          */
4110         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4111                 hns3_promisc_param_init(&param, false, false, false, func_id);
4112                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4113                 if (ret) {
4114                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4115                                         " ret = %d", func_id, ret);
4116                         return ret;
4117                 }
4118         }
4119
4120         return 0;
4121 }
4122
4123 static void
4124 hns3_promisc_uninit(struct hns3_hw *hw)
4125 {
4126         struct hns3_promisc_param param;
4127         uint16_t func_id;
4128         int ret;
4129
4130         func_id = HNS3_PF_FUNC_ID;
4131
4132         /*
4133          * In current version VFs are not supported when PF is driven by
4134          * DPDK driver, and VFs' promisc mode status has been cleared during
4135          * init and their status will not change. So just clear PF's promisc
4136          * mode status during uninit.
4137          */
4138         hns3_promisc_param_init(&param, false, false, false, func_id);
4139         ret = hns3_cmd_set_promisc_mode(hw, &param);
4140         if (ret)
4141                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4142                                 " uninit, ret = %d", ret);
4143 }
4144
4145 static int
4146 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4147 {
4148         bool allmulti = dev->data->all_multicast ? true : false;
4149         struct hns3_adapter *hns = dev->data->dev_private;
4150         struct hns3_hw *hw = &hns->hw;
4151         uint64_t offloads;
4152         int err;
4153         int ret;
4154
4155         rte_spinlock_lock(&hw->lock);
4156         ret = hns3_set_promisc_mode(hw, true, true);
4157         if (ret) {
4158                 rte_spinlock_unlock(&hw->lock);
4159                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4160                          ret);
4161                 return ret;
4162         }
4163
4164         /*
4165          * When promiscuous mode was enabled, disable the vlan filter to let
4166          * all packets coming in in the receiving direction.
4167          */
4168         offloads = dev->data->dev_conf.rxmode.offloads;
4169         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4170                 ret = hns3_enable_vlan_filter(hns, false);
4171                 if (ret) {
4172                         hns3_err(hw, "failed to enable promiscuous mode due to "
4173                                      "failure to disable vlan filter, ret = %d",
4174                                  ret);
4175                         err = hns3_set_promisc_mode(hw, false, allmulti);
4176                         if (err)
4177                                 hns3_err(hw, "failed to restore promiscuous "
4178                                          "status after disable vlan filter "
4179                                          "failed during enabling promiscuous "
4180                                          "mode, ret = %d", ret);
4181                 }
4182         }
4183
4184         rte_spinlock_unlock(&hw->lock);
4185
4186         return ret;
4187 }
4188
4189 static int
4190 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4191 {
4192         bool allmulti = dev->data->all_multicast ? true : false;
4193         struct hns3_adapter *hns = dev->data->dev_private;
4194         struct hns3_hw *hw = &hns->hw;
4195         uint64_t offloads;
4196         int err;
4197         int ret;
4198
4199         /* If now in all_multicast mode, must remain in all_multicast mode. */
4200         rte_spinlock_lock(&hw->lock);
4201         ret = hns3_set_promisc_mode(hw, false, allmulti);
4202         if (ret) {
4203                 rte_spinlock_unlock(&hw->lock);
4204                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4205                          ret);
4206                 return ret;
4207         }
4208         /* when promiscuous mode was disabled, restore the vlan filter status */
4209         offloads = dev->data->dev_conf.rxmode.offloads;
4210         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4211                 ret = hns3_enable_vlan_filter(hns, true);
4212                 if (ret) {
4213                         hns3_err(hw, "failed to disable promiscuous mode due to"
4214                                  " failure to restore vlan filter, ret = %d",
4215                                  ret);
4216                         err = hns3_set_promisc_mode(hw, true, true);
4217                         if (err)
4218                                 hns3_err(hw, "failed to restore promiscuous "
4219                                          "status after enabling vlan filter "
4220                                          "failed during disabling promiscuous "
4221                                          "mode, ret = %d", ret);
4222                 }
4223         }
4224         rte_spinlock_unlock(&hw->lock);
4225
4226         return ret;
4227 }
4228
4229 static int
4230 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4231 {
4232         struct hns3_adapter *hns = dev->data->dev_private;
4233         struct hns3_hw *hw = &hns->hw;
4234         int ret;
4235
4236         if (dev->data->promiscuous)
4237                 return 0;
4238
4239         rte_spinlock_lock(&hw->lock);
4240         ret = hns3_set_promisc_mode(hw, false, true);
4241         rte_spinlock_unlock(&hw->lock);
4242         if (ret)
4243                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4244                          ret);
4245
4246         return ret;
4247 }
4248
4249 static int
4250 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4251 {
4252         struct hns3_adapter *hns = dev->data->dev_private;
4253         struct hns3_hw *hw = &hns->hw;
4254         int ret;
4255
4256         /* If now in promiscuous mode, must remain in all_multicast mode. */
4257         if (dev->data->promiscuous)
4258                 return 0;
4259
4260         rte_spinlock_lock(&hw->lock);
4261         ret = hns3_set_promisc_mode(hw, false, false);
4262         rte_spinlock_unlock(&hw->lock);
4263         if (ret)
4264                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4265                          ret);
4266
4267         return ret;
4268 }
4269
4270 static int
4271 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4272 {
4273         struct hns3_hw *hw = &hns->hw;
4274         bool allmulti = hw->data->all_multicast ? true : false;
4275         int ret;
4276
4277         if (hw->data->promiscuous) {
4278                 ret = hns3_set_promisc_mode(hw, true, true);
4279                 if (ret)
4280                         hns3_err(hw, "failed to restore promiscuous mode, "
4281                                  "ret = %d", ret);
4282                 return ret;
4283         }
4284
4285         ret = hns3_set_promisc_mode(hw, false, allmulti);
4286         if (ret)
4287                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4288                          ret);
4289         return ret;
4290 }
4291
4292 static int
4293 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4294 {
4295         struct hns3_sfp_speed_cmd *resp;
4296         struct hns3_cmd_desc desc;
4297         int ret;
4298
4299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4300         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4301         ret = hns3_cmd_send(hw, &desc, 1);
4302         if (ret == -EOPNOTSUPP) {
4303                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4304                 return ret;
4305         } else if (ret) {
4306                 hns3_err(hw, "get sfp speed failed %d", ret);
4307                 return ret;
4308         }
4309
4310         *speed = resp->sfp_speed;
4311
4312         return 0;
4313 }
4314
4315 static uint8_t
4316 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4317 {
4318         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4319                 duplex = ETH_LINK_FULL_DUPLEX;
4320
4321         return duplex;
4322 }
4323
4324 static int
4325 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4326 {
4327         struct hns3_mac *mac = &hw->mac;
4328         uint32_t cur_speed = mac->link_speed;
4329         int ret;
4330
4331         duplex = hns3_check_speed_dup(duplex, speed);
4332         if (mac->link_speed == speed && mac->link_duplex == duplex)
4333                 return 0;
4334
4335         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4336         if (ret)
4337                 return ret;
4338
4339         mac->link_speed = speed;
4340         ret = hns3_dcb_port_shaper_cfg(hw);
4341         if (ret) {
4342                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4343                 mac->link_speed = cur_speed;
4344                 return ret;
4345         }
4346
4347         mac->link_duplex = duplex;
4348
4349         return 0;
4350 }
4351
4352 static int
4353 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4354 {
4355         struct hns3_adapter *hns = eth_dev->data->dev_private;
4356         struct hns3_hw *hw = &hns->hw;
4357         struct hns3_pf *pf = &hns->pf;
4358         uint32_t speed;
4359         int ret;
4360
4361         /* If IMP do not support get SFP/qSFP speed, return directly */
4362         if (!pf->support_sfp_query)
4363                 return 0;
4364
4365         ret = hns3_get_sfp_speed(hw, &speed);
4366         if (ret == -EOPNOTSUPP) {
4367                 pf->support_sfp_query = false;
4368                 return ret;
4369         } else if (ret)
4370                 return ret;
4371
4372         if (speed == ETH_SPEED_NUM_NONE)
4373                 return 0; /* do nothing if no SFP */
4374
4375         /* Config full duplex for SFP */
4376         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4377 }
4378
4379 static int
4380 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4381 {
4382         struct hns3_config_mac_mode_cmd *req;
4383         struct hns3_cmd_desc desc;
4384         uint32_t loop_en = 0;
4385         uint8_t val = 0;
4386         int ret;
4387
4388         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4389
4390         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4391         if (enable)
4392                 val = 1;
4393         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4394         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4395         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4396         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4397         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4398         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4399         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4400         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4401         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4402         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4403
4404         /*
4405          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4406          * when receiving frames. Otherwise, CRC will be stripped.
4407          */
4408         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4409                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4410         else
4411                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4412         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4413         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4414         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4415         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4416
4417         ret = hns3_cmd_send(hw, &desc, 1);
4418         if (ret)
4419                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4420
4421         return ret;
4422 }
4423
4424 static int
4425 hns3_get_mac_link_status(struct hns3_hw *hw)
4426 {
4427         struct hns3_link_status_cmd *req;
4428         struct hns3_cmd_desc desc;
4429         int link_status;
4430         int ret;
4431
4432         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4433         ret = hns3_cmd_send(hw, &desc, 1);
4434         if (ret) {
4435                 hns3_err(hw, "get link status cmd failed %d", ret);
4436                 return ETH_LINK_DOWN;
4437         }
4438
4439         req = (struct hns3_link_status_cmd *)desc.data;
4440         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4441
4442         return !!link_status;
4443 }
4444
4445 void
4446 hns3_update_link_status(struct hns3_hw *hw)
4447 {
4448         int state;
4449
4450         state = hns3_get_mac_link_status(hw);
4451         if (state != hw->mac.link_status) {
4452                 hw->mac.link_status = state;
4453                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4454         }
4455 }
4456
4457 static void
4458 hns3_service_handler(void *param)
4459 {
4460         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4461         struct hns3_adapter *hns = eth_dev->data->dev_private;
4462         struct hns3_hw *hw = &hns->hw;
4463
4464         if (!hns3_is_reset_pending(hns)) {
4465                 hns3_update_speed_duplex(eth_dev);
4466                 hns3_update_link_status(hw);
4467         } else
4468                 hns3_warn(hw, "Cancel the query when reset is pending");
4469
4470         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4471 }
4472
4473 static int
4474 hns3_init_hardware(struct hns3_adapter *hns)
4475 {
4476         struct hns3_hw *hw = &hns->hw;
4477         int ret;
4478
4479         ret = hns3_map_tqp(hw);
4480         if (ret) {
4481                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4482                 return ret;
4483         }
4484
4485         ret = hns3_init_umv_space(hw);
4486         if (ret) {
4487                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4488                 return ret;
4489         }
4490
4491         ret = hns3_mac_init(hw);
4492         if (ret) {
4493                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4494                 goto err_mac_init;
4495         }
4496
4497         ret = hns3_init_mgr_tbl(hw);
4498         if (ret) {
4499                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4500                 goto err_mac_init;
4501         }
4502
4503         ret = hns3_promisc_init(hw);
4504         if (ret) {
4505                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4506                              ret);
4507                 goto err_mac_init;
4508         }
4509
4510         ret = hns3_init_vlan_config(hns);
4511         if (ret) {
4512                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4513                 goto err_mac_init;
4514         }
4515
4516         ret = hns3_dcb_init(hw);
4517         if (ret) {
4518                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4519                 goto err_mac_init;
4520         }
4521
4522         ret = hns3_init_fd_config(hns);
4523         if (ret) {
4524                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4525                 goto err_mac_init;
4526         }
4527
4528         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4529         if (ret) {
4530                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4531                 goto err_mac_init;
4532         }
4533
4534         ret = hns3_config_gro(hw, false);
4535         if (ret) {
4536                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4537                 goto err_mac_init;
4538         }
4539
4540         /*
4541          * In the initialization clearing the all hardware mapping relationship
4542          * configurations between queues and interrupt vectors is needed, so
4543          * some error caused by the residual configurations, such as the
4544          * unexpected interrupt, can be avoid.
4545          */
4546         ret = hns3_init_ring_with_vector(hw);
4547         if (ret) {
4548                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4549                 goto err_mac_init;
4550         }
4551
4552         return 0;
4553
4554 err_mac_init:
4555         hns3_uninit_umv_space(hw);
4556         return ret;
4557 }
4558
4559 static int
4560 hns3_clear_hw(struct hns3_hw *hw)
4561 {
4562         struct hns3_cmd_desc desc;
4563         int ret;
4564
4565         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4566
4567         ret = hns3_cmd_send(hw, &desc, 1);
4568         if (ret && ret != -EOPNOTSUPP)
4569                 return ret;
4570
4571         return 0;
4572 }
4573
4574 static void
4575 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4576 {
4577         uint32_t val;
4578
4579         /*
4580          * The new firmware support report more hardware error types by
4581          * msix mode. These errors are defined as RAS errors in hardware
4582          * and belong to a different type from the MSI-x errors processed
4583          * by the network driver.
4584          *
4585          * Network driver should open the new error report on initialition
4586          */
4587         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4588         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4589         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4590 }
4591
4592 static int
4593 hns3_init_pf(struct rte_eth_dev *eth_dev)
4594 {
4595         struct rte_device *dev = eth_dev->device;
4596         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4597         struct hns3_adapter *hns = eth_dev->data->dev_private;
4598         struct hns3_hw *hw = &hns->hw;
4599         int ret;
4600
4601         PMD_INIT_FUNC_TRACE();
4602
4603         /* Get hardware io base address from pcie BAR2 IO space */
4604         hw->io_base = pci_dev->mem_resource[2].addr;
4605
4606         /* Firmware command queue initialize */
4607         ret = hns3_cmd_init_queue(hw);
4608         if (ret) {
4609                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4610                 goto err_cmd_init_queue;
4611         }
4612
4613         hns3_clear_all_event_cause(hw);
4614
4615         /* Firmware command initialize */
4616         ret = hns3_cmd_init(hw);
4617         if (ret) {
4618                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4619                 goto err_cmd_init;
4620         }
4621
4622         /*
4623          * To ensure that the hardware environment is clean during
4624          * initialization, the driver actively clear the hardware environment
4625          * during initialization, including PF and corresponding VFs' vlan, mac,
4626          * flow table configurations, etc.
4627          */
4628         ret = hns3_clear_hw(hw);
4629         if (ret) {
4630                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4631                 goto err_cmd_init;
4632         }
4633
4634         hns3_config_all_msix_error(hw, true);
4635
4636         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4637                                          hns3_interrupt_handler,
4638                                          eth_dev);
4639         if (ret) {
4640                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4641                 goto err_intr_callback_register;
4642         }
4643
4644         /* Enable interrupt */
4645         rte_intr_enable(&pci_dev->intr_handle);
4646         hns3_pf_enable_irq0(hw);
4647
4648         /* Get configuration */
4649         ret = hns3_get_configuration(hw);
4650         if (ret) {
4651                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4652                 goto err_get_config;
4653         }
4654
4655         ret = hns3_tqp_stats_init(hw);
4656         if (ret)
4657                 goto err_get_config;
4658
4659         ret = hns3_init_hardware(hns);
4660         if (ret) {
4661                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4662                 goto err_init_hw;
4663         }
4664
4665         /* Initialize flow director filter list & hash */
4666         ret = hns3_fdir_filter_init(hns);
4667         if (ret) {
4668                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4669                 goto err_fdir;
4670         }
4671
4672         hns3_set_default_rss_args(hw);
4673
4674         ret = hns3_enable_hw_error_intr(hns, true);
4675         if (ret) {
4676                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4677                              ret);
4678                 goto err_enable_intr;
4679         }
4680
4681         hns3_tm_conf_init(eth_dev);
4682
4683         return 0;
4684
4685 err_enable_intr:
4686         hns3_fdir_filter_uninit(hns);
4687 err_fdir:
4688         hns3_uninit_umv_space(hw);
4689 err_init_hw:
4690         hns3_tqp_stats_uninit(hw);
4691 err_get_config:
4692         hns3_pf_disable_irq0(hw);
4693         rte_intr_disable(&pci_dev->intr_handle);
4694         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4695                              eth_dev);
4696 err_intr_callback_register:
4697 err_cmd_init:
4698         hns3_cmd_uninit(hw);
4699         hns3_cmd_destroy_queue(hw);
4700 err_cmd_init_queue:
4701         hw->io_base = NULL;
4702
4703         return ret;
4704 }
4705
4706 static void
4707 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4708 {
4709         struct hns3_adapter *hns = eth_dev->data->dev_private;
4710         struct rte_device *dev = eth_dev->device;
4711         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4712         struct hns3_hw *hw = &hns->hw;
4713
4714         PMD_INIT_FUNC_TRACE();
4715
4716         hns3_tm_conf_uninit(eth_dev);
4717         hns3_enable_hw_error_intr(hns, false);
4718         hns3_rss_uninit(hns);
4719         (void)hns3_config_gro(hw, false);
4720         hns3_promisc_uninit(hw);
4721         hns3_fdir_filter_uninit(hns);
4722         hns3_uninit_umv_space(hw);
4723         hns3_tqp_stats_uninit(hw);
4724         hns3_pf_disable_irq0(hw);
4725         rte_intr_disable(&pci_dev->intr_handle);
4726         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4727                              eth_dev);
4728         hns3_config_all_msix_error(hw, false);
4729         hns3_cmd_uninit(hw);
4730         hns3_cmd_destroy_queue(hw);
4731         hw->io_base = NULL;
4732 }
4733
4734 static int
4735 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4736 {
4737         struct hns3_hw *hw = &hns->hw;
4738         int ret;
4739
4740         ret = hns3_dcb_cfg_update(hns);
4741         if (ret)
4742                 return ret;
4743
4744         /*
4745          * The hns3_dcb_cfg_update may configure TM module, so
4746          * hns3_tm_conf_update must called later.
4747          */
4748         ret = hns3_tm_conf_update(hw);
4749         if (ret) {
4750                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4751                 return ret;
4752         }
4753
4754         ret = hns3_init_queues(hns, reset_queue);
4755         if (ret) {
4756                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4757                 return ret;
4758         }
4759
4760         ret = hns3_cfg_mac_mode(hw, true);
4761         if (ret) {
4762                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4763                 goto err_config_mac_mode;
4764         }
4765         return 0;
4766
4767 err_config_mac_mode:
4768         hns3_dev_release_mbufs(hns);
4769         /*
4770          * Here is exception handling, hns3_reset_all_tqps will have the
4771          * corresponding error message if it is handled incorrectly, so it is
4772          * not necessary to check hns3_reset_all_tqps return value, here keep
4773          * ret as the error code causing the exception.
4774          */
4775         (void)hns3_reset_all_tqps(hns);
4776         return ret;
4777 }
4778
4779 static int
4780 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4781 {
4782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4784         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4786         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4787         uint32_t intr_vector;
4788         uint16_t q_id;
4789         int ret;
4790
4791         if (dev->data->dev_conf.intr_conf.rxq == 0)
4792                 return 0;
4793
4794         /* disable uio/vfio intr/eventfd mapping */
4795         rte_intr_disable(intr_handle);
4796
4797         /* check and configure queue intr-vector mapping */
4798         if (rte_intr_cap_multiple(intr_handle) ||
4799             !RTE_ETH_DEV_SRIOV(dev).active) {
4800                 intr_vector = hw->used_rx_queues;
4801                 /* creates event fd for each intr vector when MSIX is used */
4802                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4803                         return -EINVAL;
4804         }
4805         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4806                 intr_handle->intr_vec =
4807                         rte_zmalloc("intr_vec",
4808                                     hw->used_rx_queues * sizeof(int), 0);
4809                 if (intr_handle->intr_vec == NULL) {
4810                         hns3_err(hw, "Failed to allocate %u rx_queues"
4811                                      " intr_vec", hw->used_rx_queues);
4812                         ret = -ENOMEM;
4813                         goto alloc_intr_vec_error;
4814                 }
4815         }
4816
4817         if (rte_intr_allow_others(intr_handle)) {
4818                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4819                 base = RTE_INTR_VEC_RXTX_OFFSET;
4820         }
4821         if (rte_intr_dp_is_en(intr_handle)) {
4822                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4823                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4824                                                          HNS3_RING_TYPE_RX,
4825                                                          q_id);
4826                         if (ret)
4827                                 goto bind_vector_error;
4828                         intr_handle->intr_vec[q_id] = vec;
4829                         if (vec < base + intr_handle->nb_efd - 1)
4830                                 vec++;
4831                 }
4832         }
4833         rte_intr_enable(intr_handle);
4834         return 0;
4835
4836 bind_vector_error:
4837         rte_intr_efd_disable(intr_handle);
4838         if (intr_handle->intr_vec) {
4839                 free(intr_handle->intr_vec);
4840                 intr_handle->intr_vec = NULL;
4841         }
4842         return ret;
4843 alloc_intr_vec_error:
4844         rte_intr_efd_disable(intr_handle);
4845         return ret;
4846 }
4847
4848 static int
4849 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4850 {
4851         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4852         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4853         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4854         uint16_t q_id;
4855         int ret;
4856
4857         if (dev->data->dev_conf.intr_conf.rxq == 0)
4858                 return 0;
4859
4860         if (rte_intr_dp_is_en(intr_handle)) {
4861                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4862                         ret = hns3_bind_ring_with_vector(hw,
4863                                         intr_handle->intr_vec[q_id], true,
4864                                         HNS3_RING_TYPE_RX, q_id);
4865                         if (ret)
4866                                 return ret;
4867                 }
4868         }
4869
4870         return 0;
4871 }
4872
4873 static void
4874 hns3_restore_filter(struct rte_eth_dev *dev)
4875 {
4876         hns3_restore_rss_filter(dev);
4877 }
4878
4879 static int
4880 hns3_dev_start(struct rte_eth_dev *dev)
4881 {
4882         struct hns3_adapter *hns = dev->data->dev_private;
4883         struct hns3_hw *hw = &hns->hw;
4884         int ret;
4885
4886         PMD_INIT_FUNC_TRACE();
4887         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4888                 return -EBUSY;
4889
4890         rte_spinlock_lock(&hw->lock);
4891         hw->adapter_state = HNS3_NIC_STARTING;
4892
4893         ret = hns3_do_start(hns, true);
4894         if (ret) {
4895                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4896                 rte_spinlock_unlock(&hw->lock);
4897                 return ret;
4898         }
4899         ret = hns3_map_rx_interrupt(dev);
4900         if (ret) {
4901                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4902                 rte_spinlock_unlock(&hw->lock);
4903                 return ret;
4904         }
4905
4906         /*
4907          * There are three register used to control the status of a TQP
4908          * (contains a pair of Tx queue and Rx queue) in the new version network
4909          * engine. One is used to control the enabling of Tx queue, the other is
4910          * used to control the enabling of Rx queue, and the last is the master
4911          * switch used to control the enabling of the tqp. The Tx register and
4912          * TQP register must be enabled at the same time to enable a Tx queue.
4913          * The same applies to the Rx queue. For the older network engine, this
4914          * function only refresh the enabled flag, and it is used to update the
4915          * status of queue in the dpdk framework.
4916          */
4917         ret = hns3_start_all_txqs(dev);
4918         if (ret) {
4919                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4920                 rte_spinlock_unlock(&hw->lock);
4921                 return ret;
4922         }
4923
4924         ret = hns3_start_all_rxqs(dev);
4925         if (ret) {
4926                 hns3_stop_all_txqs(dev);
4927                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4928                 rte_spinlock_unlock(&hw->lock);
4929                 return ret;
4930         }
4931
4932         hw->adapter_state = HNS3_NIC_STARTED;
4933         rte_spinlock_unlock(&hw->lock);
4934
4935         hns3_rx_scattered_calc(dev);
4936         hns3_set_rxtx_function(dev);
4937         hns3_mp_req_start_rxtx(dev);
4938         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4939
4940         hns3_restore_filter(dev);
4941
4942         /* Enable interrupt of all rx queues before enabling queues */
4943         hns3_dev_all_rx_queue_intr_enable(hw, true);
4944
4945         /*
4946          * After finished the initialization, enable tqps to receive/transmit
4947          * packets and refresh all queue status.
4948          */
4949         hns3_start_tqps(hw);
4950
4951         hns3_tm_dev_start_proc(hw);
4952
4953         hns3_info(hw, "hns3 dev start successful!");
4954         return 0;
4955 }
4956
4957 static int
4958 hns3_do_stop(struct hns3_adapter *hns)
4959 {
4960         struct hns3_hw *hw = &hns->hw;
4961         int ret;
4962
4963         ret = hns3_cfg_mac_mode(hw, false);
4964         if (ret)
4965                 return ret;
4966         hw->mac.link_status = ETH_LINK_DOWN;
4967
4968         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4969                 hns3_configure_all_mac_addr(hns, true);
4970                 ret = hns3_reset_all_tqps(hns);
4971                 if (ret) {
4972                         hns3_err(hw, "failed to reset all queues ret = %d.",
4973                                  ret);
4974                         return ret;
4975                 }
4976         }
4977         hw->mac.default_addr_setted = false;
4978         return 0;
4979 }
4980
4981 static void
4982 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4983 {
4984         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4985         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4986         struct hns3_adapter *hns = dev->data->dev_private;
4987         struct hns3_hw *hw = &hns->hw;
4988         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4989         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4990         uint16_t q_id;
4991
4992         if (dev->data->dev_conf.intr_conf.rxq == 0)
4993                 return;
4994
4995         /* unmap the ring with vector */
4996         if (rte_intr_allow_others(intr_handle)) {
4997                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4998                 base = RTE_INTR_VEC_RXTX_OFFSET;
4999         }
5000         if (rte_intr_dp_is_en(intr_handle)) {
5001                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5002                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5003                                                          HNS3_RING_TYPE_RX,
5004                                                          q_id);
5005                         if (vec < base + intr_handle->nb_efd - 1)
5006                                 vec++;
5007                 }
5008         }
5009         /* Clean datapath event and queue/vec mapping */
5010         rte_intr_efd_disable(intr_handle);
5011         if (intr_handle->intr_vec) {
5012                 rte_free(intr_handle->intr_vec);
5013                 intr_handle->intr_vec = NULL;
5014         }
5015 }
5016
5017 static int
5018 hns3_dev_stop(struct rte_eth_dev *dev)
5019 {
5020         struct hns3_adapter *hns = dev->data->dev_private;
5021         struct hns3_hw *hw = &hns->hw;
5022
5023         PMD_INIT_FUNC_TRACE();
5024         dev->data->dev_started = 0;
5025
5026         hw->adapter_state = HNS3_NIC_STOPPING;
5027         hns3_set_rxtx_function(dev);
5028         rte_wmb();
5029         /* Disable datapath on secondary process. */
5030         hns3_mp_req_stop_rxtx(dev);
5031         /* Prevent crashes when queues are still in use. */
5032         rte_delay_ms(hw->tqps_num);
5033
5034         rte_spinlock_lock(&hw->lock);
5035         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5036                 hns3_tm_dev_stop_proc(hw);
5037                 hns3_stop_tqps(hw);
5038                 hns3_do_stop(hns);
5039                 hns3_unmap_rx_interrupt(dev);
5040                 hns3_dev_release_mbufs(hns);
5041                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5042         }
5043         hns3_rx_scattered_reset(dev);
5044         rte_eal_alarm_cancel(hns3_service_handler, dev);
5045         rte_spinlock_unlock(&hw->lock);
5046
5047         return 0;
5048 }
5049
5050 static int
5051 hns3_dev_close(struct rte_eth_dev *eth_dev)
5052 {
5053         struct hns3_adapter *hns = eth_dev->data->dev_private;
5054         struct hns3_hw *hw = &hns->hw;
5055         int ret = 0;
5056
5057         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5058                 rte_free(eth_dev->process_private);
5059                 eth_dev->process_private = NULL;
5060                 return 0;
5061         }
5062
5063         if (hw->adapter_state == HNS3_NIC_STARTED)
5064                 ret = hns3_dev_stop(eth_dev);
5065
5066         hw->adapter_state = HNS3_NIC_CLOSING;
5067         hns3_reset_abort(hns);
5068         hw->adapter_state = HNS3_NIC_CLOSED;
5069
5070         hns3_configure_all_mc_mac_addr(hns, true);
5071         hns3_remove_all_vlan_table(hns);
5072         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5073         hns3_uninit_pf(eth_dev);
5074         hns3_free_all_queues(eth_dev);
5075         rte_free(hw->reset.wait_data);
5076         rte_free(eth_dev->process_private);
5077         eth_dev->process_private = NULL;
5078         hns3_mp_uninit_primary();
5079         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5080
5081         return ret;
5082 }
5083
5084 static int
5085 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5086 {
5087         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5089
5090         fc_conf->pause_time = pf->pause_time;
5091
5092         /* return fc current mode */
5093         switch (hw->current_mode) {
5094         case HNS3_FC_FULL:
5095                 fc_conf->mode = RTE_FC_FULL;
5096                 break;
5097         case HNS3_FC_TX_PAUSE:
5098                 fc_conf->mode = RTE_FC_TX_PAUSE;
5099                 break;
5100         case HNS3_FC_RX_PAUSE:
5101                 fc_conf->mode = RTE_FC_RX_PAUSE;
5102                 break;
5103         case HNS3_FC_NONE:
5104         default:
5105                 fc_conf->mode = RTE_FC_NONE;
5106                 break;
5107         }
5108
5109         return 0;
5110 }
5111
5112 static void
5113 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5114 {
5115         switch (mode) {
5116         case RTE_FC_NONE:
5117                 hw->requested_mode = HNS3_FC_NONE;
5118                 break;
5119         case RTE_FC_RX_PAUSE:
5120                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5121                 break;
5122         case RTE_FC_TX_PAUSE:
5123                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5124                 break;
5125         case RTE_FC_FULL:
5126                 hw->requested_mode = HNS3_FC_FULL;
5127                 break;
5128         default:
5129                 hw->requested_mode = HNS3_FC_NONE;
5130                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5131                           "configured to RTE_FC_NONE", mode);
5132                 break;
5133         }
5134 }
5135
5136 static int
5137 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5138 {
5139         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5141         int ret;
5142
5143         if (fc_conf->high_water || fc_conf->low_water ||
5144             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5145                 hns3_err(hw, "Unsupported flow control settings specified, "
5146                          "high_water(%u), low_water(%u), send_xon(%u) and "
5147                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5148                          fc_conf->high_water, fc_conf->low_water,
5149                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5150                 return -EINVAL;
5151         }
5152         if (fc_conf->autoneg) {
5153                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5154                 return -EINVAL;
5155         }
5156         if (!fc_conf->pause_time) {
5157                 hns3_err(hw, "Invalid pause time %u setting.",
5158                          fc_conf->pause_time);
5159                 return -EINVAL;
5160         }
5161
5162         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5163             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5164                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5165                          "current_fc_status = %d", hw->current_fc_status);
5166                 return -EOPNOTSUPP;
5167         }
5168
5169         hns3_get_fc_mode(hw, fc_conf->mode);
5170         if (hw->requested_mode == hw->current_mode &&
5171             pf->pause_time == fc_conf->pause_time)
5172                 return 0;
5173
5174         rte_spinlock_lock(&hw->lock);
5175         ret = hns3_fc_enable(dev, fc_conf);
5176         rte_spinlock_unlock(&hw->lock);
5177
5178         return ret;
5179 }
5180
5181 static int
5182 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5183                             struct rte_eth_pfc_conf *pfc_conf)
5184 {
5185         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5186         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5187         uint8_t priority;
5188         int ret;
5189
5190         if (!hns3_dev_dcb_supported(hw)) {
5191                 hns3_err(hw, "This port does not support dcb configurations.");
5192                 return -EOPNOTSUPP;
5193         }
5194
5195         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5196             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5197                 hns3_err(hw, "Unsupported flow control settings specified, "
5198                          "high_water(%u), low_water(%u), send_xon(%u) and "
5199                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5200                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5201                          pfc_conf->fc.send_xon,
5202                          pfc_conf->fc.mac_ctrl_frame_fwd);
5203                 return -EINVAL;
5204         }
5205         if (pfc_conf->fc.autoneg) {
5206                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5207                 return -EINVAL;
5208         }
5209         if (pfc_conf->fc.pause_time == 0) {
5210                 hns3_err(hw, "Invalid pause time %u setting.",
5211                          pfc_conf->fc.pause_time);
5212                 return -EINVAL;
5213         }
5214
5215         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5216             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5217                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5218                              "current_fc_status = %d", hw->current_fc_status);
5219                 return -EOPNOTSUPP;
5220         }
5221
5222         priority = pfc_conf->priority;
5223         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5224         if (hw->dcb_info.pfc_en & BIT(priority) &&
5225             hw->requested_mode == hw->current_mode &&
5226             pfc_conf->fc.pause_time == pf->pause_time)
5227                 return 0;
5228
5229         rte_spinlock_lock(&hw->lock);
5230         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5231         rte_spinlock_unlock(&hw->lock);
5232
5233         return ret;
5234 }
5235
5236 static int
5237 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5238 {
5239         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5241         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5242         int i;
5243
5244         rte_spinlock_lock(&hw->lock);
5245         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5246                 dcb_info->nb_tcs = pf->local_max_tc;
5247         else
5248                 dcb_info->nb_tcs = 1;
5249
5250         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5251                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5252         for (i = 0; i < dcb_info->nb_tcs; i++)
5253                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5254
5255         for (i = 0; i < hw->num_tc; i++) {
5256                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5257                 dcb_info->tc_queue.tc_txq[0][i].base =
5258                                                 hw->tc_queue[i].tqp_offset;
5259                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5260                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5261                                                 hw->tc_queue[i].tqp_count;
5262         }
5263         rte_spinlock_unlock(&hw->lock);
5264
5265         return 0;
5266 }
5267
5268 static int
5269 hns3_reinit_dev(struct hns3_adapter *hns)
5270 {
5271         struct hns3_hw *hw = &hns->hw;
5272         int ret;
5273
5274         ret = hns3_cmd_init(hw);
5275         if (ret) {
5276                 hns3_err(hw, "Failed to init cmd: %d", ret);
5277                 return ret;
5278         }
5279
5280         ret = hns3_reset_all_tqps(hns);
5281         if (ret) {
5282                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5283                 return ret;
5284         }
5285
5286         ret = hns3_init_hardware(hns);
5287         if (ret) {
5288                 hns3_err(hw, "Failed to init hardware: %d", ret);
5289                 return ret;
5290         }
5291
5292         ret = hns3_enable_hw_error_intr(hns, true);
5293         if (ret) {
5294                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5295                              ret);
5296                 return ret;
5297         }
5298         hns3_info(hw, "Reset done, driver initialization finished.");
5299
5300         return 0;
5301 }
5302
5303 static bool
5304 is_pf_reset_done(struct hns3_hw *hw)
5305 {
5306         uint32_t val, reg, reg_bit;
5307
5308         switch (hw->reset.level) {
5309         case HNS3_IMP_RESET:
5310                 reg = HNS3_GLOBAL_RESET_REG;
5311                 reg_bit = HNS3_IMP_RESET_BIT;
5312                 break;
5313         case HNS3_GLOBAL_RESET:
5314                 reg = HNS3_GLOBAL_RESET_REG;
5315                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5316                 break;
5317         case HNS3_FUNC_RESET:
5318                 reg = HNS3_FUN_RST_ING;
5319                 reg_bit = HNS3_FUN_RST_ING_B;
5320                 break;
5321         case HNS3_FLR_RESET:
5322         default:
5323                 hns3_err(hw, "Wait for unsupported reset level: %d",
5324                          hw->reset.level);
5325                 return true;
5326         }
5327         val = hns3_read_dev(hw, reg);
5328         if (hns3_get_bit(val, reg_bit))
5329                 return false;
5330         else
5331                 return true;
5332 }
5333
5334 bool
5335 hns3_is_reset_pending(struct hns3_adapter *hns)
5336 {
5337         struct hns3_hw *hw = &hns->hw;
5338         enum hns3_reset_level reset;
5339
5340         hns3_check_event_cause(hns, NULL);
5341         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5342         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5343                 hns3_warn(hw, "High level reset %d is pending", reset);
5344                 return true;
5345         }
5346         reset = hns3_get_reset_level(hns, &hw->reset.request);
5347         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5348                 hns3_warn(hw, "High level reset %d is request", reset);
5349                 return true;
5350         }
5351         return false;
5352 }
5353
5354 static int
5355 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5356 {
5357         struct hns3_hw *hw = &hns->hw;
5358         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5359         struct timeval tv;
5360
5361         if (wait_data->result == HNS3_WAIT_SUCCESS)
5362                 return 0;
5363         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5364                 gettimeofday(&tv, NULL);
5365                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5366                           tv.tv_sec, tv.tv_usec);
5367                 return -ETIME;
5368         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5369                 return -EAGAIN;
5370
5371         wait_data->hns = hns;
5372         wait_data->check_completion = is_pf_reset_done;
5373         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5374                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5375         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5376         wait_data->count = HNS3_RESET_WAIT_CNT;
5377         wait_data->result = HNS3_WAIT_REQUEST;
5378         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5379         return -EAGAIN;
5380 }
5381
5382 static int
5383 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5384 {
5385         struct hns3_cmd_desc desc;
5386         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5387
5388         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5389         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5390         req->fun_reset_vfid = func_id;
5391
5392         return hns3_cmd_send(hw, &desc, 1);
5393 }
5394
5395 static int
5396 hns3_imp_reset_cmd(struct hns3_hw *hw)
5397 {
5398         struct hns3_cmd_desc desc;
5399
5400         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5401         desc.data[0] = 0xeedd;
5402
5403         return hns3_cmd_send(hw, &desc, 1);
5404 }
5405
5406 static void
5407 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5408 {
5409         struct hns3_hw *hw = &hns->hw;
5410         struct timeval tv;
5411         uint32_t val;
5412
5413         gettimeofday(&tv, NULL);
5414         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5415             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5416                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5417                           tv.tv_sec, tv.tv_usec);
5418                 return;
5419         }
5420
5421         switch (reset_level) {
5422         case HNS3_IMP_RESET:
5423                 hns3_imp_reset_cmd(hw);
5424                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5425                           tv.tv_sec, tv.tv_usec);
5426                 break;
5427         case HNS3_GLOBAL_RESET:
5428                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5429                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5430                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5431                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5432                           tv.tv_sec, tv.tv_usec);
5433                 break;
5434         case HNS3_FUNC_RESET:
5435                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5436                           tv.tv_sec, tv.tv_usec);
5437                 /* schedule again to check later */
5438                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5439                 hns3_schedule_reset(hns);
5440                 break;
5441         default:
5442                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5443                 return;
5444         }
5445         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5446 }
5447
5448 static enum hns3_reset_level
5449 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5450 {
5451         struct hns3_hw *hw = &hns->hw;
5452         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5453
5454         /* Return the highest priority reset level amongst all */
5455         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5456                 reset_level = HNS3_IMP_RESET;
5457         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5458                 reset_level = HNS3_GLOBAL_RESET;
5459         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5460                 reset_level = HNS3_FUNC_RESET;
5461         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5462                 reset_level = HNS3_FLR_RESET;
5463
5464         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5465                 return HNS3_NONE_RESET;
5466
5467         return reset_level;
5468 }
5469
5470 static void
5471 hns3_record_imp_error(struct hns3_adapter *hns)
5472 {
5473         struct hns3_hw *hw = &hns->hw;
5474         uint32_t reg_val;
5475
5476         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5477         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5478                 hns3_warn(hw, "Detected IMP RD poison!");
5479                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5480                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5481                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5482         }
5483
5484         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5485                 hns3_warn(hw, "Detected IMP CMDQ error!");
5486                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5487                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5488                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5489         }
5490 }
5491
5492 static int
5493 hns3_prepare_reset(struct hns3_adapter *hns)
5494 {
5495         struct hns3_hw *hw = &hns->hw;
5496         uint32_t reg_val;
5497         int ret;
5498
5499         switch (hw->reset.level) {
5500         case HNS3_FUNC_RESET:
5501                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5502                 if (ret)
5503                         return ret;
5504
5505                 /*
5506                  * After performaning pf reset, it is not necessary to do the
5507                  * mailbox handling or send any command to firmware, because
5508                  * any mailbox handling or command to firmware is only valid
5509                  * after hns3_cmd_init is called.
5510                  */
5511                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5512                 hw->reset.stats.request_cnt++;
5513                 break;
5514         case HNS3_IMP_RESET:
5515                 hns3_record_imp_error(hns);
5516                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5517                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5518                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5519                 break;
5520         default:
5521                 break;
5522         }
5523         return 0;
5524 }
5525
5526 static int
5527 hns3_set_rst_done(struct hns3_hw *hw)
5528 {
5529         struct hns3_pf_rst_done_cmd *req;
5530         struct hns3_cmd_desc desc;
5531
5532         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5533         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5534         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5535         return hns3_cmd_send(hw, &desc, 1);
5536 }
5537
5538 static int
5539 hns3_stop_service(struct hns3_adapter *hns)
5540 {
5541         struct hns3_hw *hw = &hns->hw;
5542         struct rte_eth_dev *eth_dev;
5543
5544         eth_dev = &rte_eth_devices[hw->data->port_id];
5545         if (hw->adapter_state == HNS3_NIC_STARTED)
5546                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5547         hw->mac.link_status = ETH_LINK_DOWN;
5548
5549         hns3_set_rxtx_function(eth_dev);
5550         rte_wmb();
5551         /* Disable datapath on secondary process. */
5552         hns3_mp_req_stop_rxtx(eth_dev);
5553         rte_delay_ms(hw->tqps_num);
5554
5555         rte_spinlock_lock(&hw->lock);
5556         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5557             hw->adapter_state == HNS3_NIC_STOPPING) {
5558                 hns3_enable_all_queues(hw, false);
5559                 hns3_do_stop(hns);
5560                 hw->reset.mbuf_deferred_free = true;
5561         } else
5562                 hw->reset.mbuf_deferred_free = false;
5563
5564         /*
5565          * It is cumbersome for hardware to pick-and-choose entries for deletion
5566          * from table space. Hence, for function reset software intervention is
5567          * required to delete the entries
5568          */
5569         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5570                 hns3_configure_all_mc_mac_addr(hns, true);
5571         rte_spinlock_unlock(&hw->lock);
5572
5573         return 0;
5574 }
5575
5576 static int
5577 hns3_start_service(struct hns3_adapter *hns)
5578 {
5579         struct hns3_hw *hw = &hns->hw;
5580         struct rte_eth_dev *eth_dev;
5581
5582         if (hw->reset.level == HNS3_IMP_RESET ||
5583             hw->reset.level == HNS3_GLOBAL_RESET)
5584                 hns3_set_rst_done(hw);
5585         eth_dev = &rte_eth_devices[hw->data->port_id];
5586         hns3_set_rxtx_function(eth_dev);
5587         hns3_mp_req_start_rxtx(eth_dev);
5588         if (hw->adapter_state == HNS3_NIC_STARTED) {
5589                 hns3_service_handler(eth_dev);
5590
5591                 /* Enable interrupt of all rx queues before enabling queues */
5592                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5593                 /*
5594                  * Enable state of each rxq and txq will be recovered after
5595                  * reset, so we need to restore them before enable all tqps;
5596                  */
5597                 hns3_restore_tqp_enable_state(hw);
5598                 /*
5599                  * When finished the initialization, enable queues to receive
5600                  * and transmit packets.
5601                  */
5602                 hns3_enable_all_queues(hw, true);
5603         }
5604
5605         return 0;
5606 }
5607
5608 static int
5609 hns3_restore_conf(struct hns3_adapter *hns)
5610 {
5611         struct hns3_hw *hw = &hns->hw;
5612         int ret;
5613
5614         ret = hns3_configure_all_mac_addr(hns, false);
5615         if (ret)
5616                 return ret;
5617
5618         ret = hns3_configure_all_mc_mac_addr(hns, false);
5619         if (ret)
5620                 goto err_mc_mac;
5621
5622         ret = hns3_dev_promisc_restore(hns);
5623         if (ret)
5624                 goto err_promisc;
5625
5626         ret = hns3_restore_vlan_table(hns);
5627         if (ret)
5628                 goto err_promisc;
5629
5630         ret = hns3_restore_vlan_conf(hns);
5631         if (ret)
5632                 goto err_promisc;
5633
5634         ret = hns3_restore_all_fdir_filter(hns);
5635         if (ret)
5636                 goto err_promisc;
5637
5638         ret = hns3_restore_rx_interrupt(hw);
5639         if (ret)
5640                 goto err_promisc;
5641
5642         ret = hns3_restore_gro_conf(hw);
5643         if (ret)
5644                 goto err_promisc;
5645
5646         ret = hns3_restore_fec(hw);
5647         if (ret)
5648                 goto err_promisc;
5649
5650         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5651                 ret = hns3_do_start(hns, false);
5652                 if (ret)
5653                         goto err_promisc;
5654                 hns3_info(hw, "hns3 dev restart successful!");
5655         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5656                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5657         return 0;
5658
5659 err_promisc:
5660         hns3_configure_all_mc_mac_addr(hns, true);
5661 err_mc_mac:
5662         hns3_configure_all_mac_addr(hns, true);
5663         return ret;
5664 }
5665
5666 static void
5667 hns3_reset_service(void *param)
5668 {
5669         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5670         struct hns3_hw *hw = &hns->hw;
5671         enum hns3_reset_level reset_level;
5672         struct timeval tv_delta;
5673         struct timeval tv_start;
5674         struct timeval tv;
5675         uint64_t msec;
5676         int ret;
5677
5678         /*
5679          * The interrupt is not triggered within the delay time.
5680          * The interrupt may have been lost. It is necessary to handle
5681          * the interrupt to recover from the error.
5682          */
5683         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5684                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5685                 hns3_err(hw, "Handling interrupts in delayed tasks");
5686                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5687                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5688                 if (reset_level == HNS3_NONE_RESET) {
5689                         hns3_err(hw, "No reset level is set, try IMP reset");
5690                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5691                 }
5692         }
5693         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5694
5695         /*
5696          * Check if there is any ongoing reset in the hardware. This status can
5697          * be checked from reset_pending. If there is then, we need to wait for
5698          * hardware to complete reset.
5699          *    a. If we are able to figure out in reasonable time that hardware
5700          *       has fully resetted then, we can proceed with driver, client
5701          *       reset.
5702          *    b. else, we can come back later to check this status so re-sched
5703          *       now.
5704          */
5705         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5706         if (reset_level != HNS3_NONE_RESET) {
5707                 gettimeofday(&tv_start, NULL);
5708                 ret = hns3_reset_process(hns, reset_level);
5709                 gettimeofday(&tv, NULL);
5710                 timersub(&tv, &tv_start, &tv_delta);
5711                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5712                        tv_delta.tv_usec / USEC_PER_MSEC;
5713                 if (msec > HNS3_RESET_PROCESS_MS)
5714                         hns3_err(hw, "%d handle long time delta %" PRIx64
5715                                      " ms time=%ld.%.6ld",
5716                                  hw->reset.level, msec,
5717                                  tv.tv_sec, tv.tv_usec);
5718                 if (ret == -EAGAIN)
5719                         return;
5720         }
5721
5722         /* Check if we got any *new* reset requests to be honored */
5723         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5724         if (reset_level != HNS3_NONE_RESET)
5725                 hns3_msix_process(hns, reset_level);
5726 }
5727
5728 static unsigned int
5729 hns3_get_speed_capa_num(uint16_t device_id)
5730 {
5731         unsigned int num;
5732
5733         switch (device_id) {
5734         case HNS3_DEV_ID_25GE:
5735         case HNS3_DEV_ID_25GE_RDMA:
5736                 num = 2;
5737                 break;
5738         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5739         case HNS3_DEV_ID_200G_RDMA:
5740                 num = 1;
5741                 break;
5742         default:
5743                 num = 0;
5744                 break;
5745         }
5746
5747         return num;
5748 }
5749
5750 static int
5751 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5752                         uint16_t device_id)
5753 {
5754         switch (device_id) {
5755         case HNS3_DEV_ID_25GE:
5756         /* fallthrough */
5757         case HNS3_DEV_ID_25GE_RDMA:
5758                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5759                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5760
5761                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5762                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5763                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5764                 break;
5765         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5766                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5767                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5768                 break;
5769         case HNS3_DEV_ID_200G_RDMA:
5770                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5771                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5772                 break;
5773         default:
5774                 return -ENOTSUP;
5775         }
5776
5777         return 0;
5778 }
5779
5780 static int
5781 hns3_fec_get_capability(struct rte_eth_dev *dev,
5782                         struct rte_eth_fec_capa *speed_fec_capa,
5783                         unsigned int num)
5784 {
5785         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5787         uint16_t device_id = pci_dev->id.device_id;
5788         unsigned int capa_num;
5789         int ret;
5790
5791         capa_num = hns3_get_speed_capa_num(device_id);
5792         if (capa_num == 0) {
5793                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5794                          device_id);
5795                 return -ENOTSUP;
5796         }
5797
5798         if (speed_fec_capa == NULL || num < capa_num)
5799                 return capa_num;
5800
5801         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5802         if (ret)
5803                 return -ENOTSUP;
5804
5805         return capa_num;
5806 }
5807
5808 static int
5809 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5810 {
5811         struct hns3_config_fec_cmd *req;
5812         struct hns3_cmd_desc desc;
5813         int ret;
5814
5815         /*
5816          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5817          * in device of link speed
5818          * below 10 Gbps.
5819          */
5820         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5821                 *state = 0;
5822                 return 0;
5823         }
5824
5825         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5826         req = (struct hns3_config_fec_cmd *)desc.data;
5827         ret = hns3_cmd_send(hw, &desc, 1);
5828         if (ret) {
5829                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5830                          ret);
5831                 return ret;
5832         }
5833
5834         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5835         return 0;
5836 }
5837
5838 static int
5839 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5840 {
5841 #define QUERY_ACTIVE_SPEED      1
5842         struct hns3_sfp_speed_cmd *resp;
5843         uint32_t tmp_fec_capa;
5844         uint8_t auto_state;
5845         struct hns3_cmd_desc desc;
5846         int ret;
5847
5848         /*
5849          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5850          * configured FEC mode is returned.
5851          * If link is up, current FEC mode is returned.
5852          */
5853         if (hw->mac.link_status == ETH_LINK_DOWN) {
5854                 ret = get_current_fec_auto_state(hw, &auto_state);
5855                 if (ret)
5856                         return ret;
5857
5858                 if (auto_state == 0x1) {
5859                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5860                         return 0;
5861                 }
5862         }
5863
5864         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5865         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5866         resp->query_type = QUERY_ACTIVE_SPEED;
5867
5868         ret = hns3_cmd_send(hw, &desc, 1);
5869         if (ret == -EOPNOTSUPP) {
5870                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5871                 return ret;
5872         } else if (ret) {
5873                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5874                 return ret;
5875         }
5876
5877         /*
5878          * FEC mode order defined in hns3 hardware is inconsistend with
5879          * that defined in the ethdev library. So the sequence needs
5880          * to be converted.
5881          */
5882         switch (resp->active_fec) {
5883         case HNS3_HW_FEC_MODE_NOFEC:
5884                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5885                 break;
5886         case HNS3_HW_FEC_MODE_BASER:
5887                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5888                 break;
5889         case HNS3_HW_FEC_MODE_RS:
5890                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5891                 break;
5892         default:
5893                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5894                 break;
5895         }
5896
5897         *fec_capa = tmp_fec_capa;
5898         return 0;
5899 }
5900
5901 static int
5902 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5903 {
5904         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905
5906         return hns3_fec_get_internal(hw, fec_capa);
5907 }
5908
5909 static int
5910 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5911 {
5912         struct hns3_config_fec_cmd *req;
5913         struct hns3_cmd_desc desc;
5914         int ret;
5915
5916         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5917
5918         req = (struct hns3_config_fec_cmd *)desc.data;
5919         switch (mode) {
5920         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5921                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5922                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5923                 break;
5924         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5925                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5926                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5927                 break;
5928         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5929                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5930                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5931                 break;
5932         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5933                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5934                 break;
5935         default:
5936                 return 0;
5937         }
5938         ret = hns3_cmd_send(hw, &desc, 1);
5939         if (ret)
5940                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5941
5942         return ret;
5943 }
5944
5945 static uint32_t
5946 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5947 {
5948         struct hns3_mac *mac = &hw->mac;
5949         uint32_t cur_capa;
5950
5951         switch (mac->link_speed) {
5952         case ETH_SPEED_NUM_10G:
5953                 cur_capa = fec_capa[1].capa;
5954                 break;
5955         case ETH_SPEED_NUM_25G:
5956         case ETH_SPEED_NUM_100G:
5957         case ETH_SPEED_NUM_200G:
5958                 cur_capa = fec_capa[0].capa;
5959                 break;
5960         default:
5961                 cur_capa = 0;
5962                 break;
5963         }
5964
5965         return cur_capa;
5966 }
5967
5968 static bool
5969 is_fec_mode_one_bit_set(uint32_t mode)
5970 {
5971         int cnt = 0;
5972         uint8_t i;
5973
5974         for (i = 0; i < sizeof(mode); i++)
5975                 if (mode >> i & 0x1)
5976                         cnt++;
5977
5978         return cnt == 1 ? true : false;
5979 }
5980
5981 static int
5982 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5983 {
5984 #define FEC_CAPA_NUM 2
5985         struct hns3_adapter *hns = dev->data->dev_private;
5986         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5987         struct hns3_pf *pf = &hns->pf;
5988
5989         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5990         uint32_t cur_capa;
5991         uint32_t num = FEC_CAPA_NUM;
5992         int ret;
5993
5994         ret = hns3_fec_get_capability(dev, fec_capa, num);
5995         if (ret < 0)
5996                 return ret;
5997
5998         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5999         if (!is_fec_mode_one_bit_set(mode))
6000                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6001                              "FEC mode should be only one bit set", mode);
6002
6003         /*
6004          * Check whether the configured mode is within the FEC capability.
6005          * If not, the configured mode will not be supported.
6006          */
6007         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6008         if (!(cur_capa & mode)) {
6009                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6010                 return -EINVAL;
6011         }
6012
6013         ret = hns3_set_fec_hw(hw, mode);
6014         if (ret)
6015                 return ret;
6016
6017         pf->fec_mode = mode;
6018         return 0;
6019 }
6020
6021 static int
6022 hns3_restore_fec(struct hns3_hw *hw)
6023 {
6024         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6025         struct hns3_pf *pf = &hns->pf;
6026         uint32_t mode = pf->fec_mode;
6027         int ret;
6028
6029         ret = hns3_set_fec_hw(hw, mode);
6030         if (ret)
6031                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6032                          mode, ret);
6033
6034         return ret;
6035 }
6036
6037 static int
6038 hns3_query_dev_fec_info(struct hns3_hw *hw)
6039 {
6040         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6041         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6042         int ret;
6043
6044         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6045         if (ret)
6046                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6047
6048         return ret;
6049 }
6050
6051 static const struct eth_dev_ops hns3_eth_dev_ops = {
6052         .dev_configure      = hns3_dev_configure,
6053         .dev_start          = hns3_dev_start,
6054         .dev_stop           = hns3_dev_stop,
6055         .dev_close          = hns3_dev_close,
6056         .promiscuous_enable = hns3_dev_promiscuous_enable,
6057         .promiscuous_disable = hns3_dev_promiscuous_disable,
6058         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6059         .allmulticast_disable = hns3_dev_allmulticast_disable,
6060         .mtu_set            = hns3_dev_mtu_set,
6061         .stats_get          = hns3_stats_get,
6062         .stats_reset        = hns3_stats_reset,
6063         .xstats_get         = hns3_dev_xstats_get,
6064         .xstats_get_names   = hns3_dev_xstats_get_names,
6065         .xstats_reset       = hns3_dev_xstats_reset,
6066         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6067         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6068         .dev_infos_get          = hns3_dev_infos_get,
6069         .fw_version_get         = hns3_fw_version_get,
6070         .rx_queue_setup         = hns3_rx_queue_setup,
6071         .tx_queue_setup         = hns3_tx_queue_setup,
6072         .rx_queue_release       = hns3_dev_rx_queue_release,
6073         .tx_queue_release       = hns3_dev_tx_queue_release,
6074         .rx_queue_start         = hns3_dev_rx_queue_start,
6075         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6076         .tx_queue_start         = hns3_dev_tx_queue_start,
6077         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6078         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6079         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6080         .rxq_info_get           = hns3_rxq_info_get,
6081         .txq_info_get           = hns3_txq_info_get,
6082         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6083         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6084         .flow_ctrl_get          = hns3_flow_ctrl_get,
6085         .flow_ctrl_set          = hns3_flow_ctrl_set,
6086         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6087         .mac_addr_add           = hns3_add_mac_addr,
6088         .mac_addr_remove        = hns3_remove_mac_addr,
6089         .mac_addr_set           = hns3_set_default_mac_addr,
6090         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6091         .link_update            = hns3_dev_link_update,
6092         .rss_hash_update        = hns3_dev_rss_hash_update,
6093         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6094         .reta_update            = hns3_dev_rss_reta_update,
6095         .reta_query             = hns3_dev_rss_reta_query,
6096         .filter_ctrl            = hns3_dev_filter_ctrl,
6097         .vlan_filter_set        = hns3_vlan_filter_set,
6098         .vlan_tpid_set          = hns3_vlan_tpid_set,
6099         .vlan_offload_set       = hns3_vlan_offload_set,
6100         .vlan_pvid_set          = hns3_vlan_pvid_set,
6101         .get_reg                = hns3_get_regs,
6102         .get_dcb_info           = hns3_get_dcb_info,
6103         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6104         .fec_get_capability     = hns3_fec_get_capability,
6105         .fec_get                = hns3_fec_get,
6106         .fec_set                = hns3_fec_set,
6107         .tm_ops_get             = hns3_tm_ops_get,
6108 };
6109
6110 static const struct hns3_reset_ops hns3_reset_ops = {
6111         .reset_service       = hns3_reset_service,
6112         .stop_service        = hns3_stop_service,
6113         .prepare_reset       = hns3_prepare_reset,
6114         .wait_hardware_ready = hns3_wait_hardware_ready,
6115         .reinit_dev          = hns3_reinit_dev,
6116         .restore_conf        = hns3_restore_conf,
6117         .start_service       = hns3_start_service,
6118 };
6119
6120 static int
6121 hns3_dev_init(struct rte_eth_dev *eth_dev)
6122 {
6123         struct hns3_adapter *hns = eth_dev->data->dev_private;
6124         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6125         struct rte_ether_addr *eth_addr;
6126         struct hns3_hw *hw = &hns->hw;
6127         int ret;
6128
6129         PMD_INIT_FUNC_TRACE();
6130
6131         eth_dev->process_private = (struct hns3_process_private *)
6132             rte_zmalloc_socket("hns3_filter_list",
6133                                sizeof(struct hns3_process_private),
6134                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6135         if (eth_dev->process_private == NULL) {
6136                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6137                 return -ENOMEM;
6138         }
6139         /* initialize flow filter lists */
6140         hns3_filterlist_init(eth_dev);
6141
6142         hns3_set_rxtx_function(eth_dev);
6143         eth_dev->dev_ops = &hns3_eth_dev_ops;
6144         eth_dev->rx_queue_count = hns3_rx_queue_count;
6145         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6146                 ret = hns3_mp_init_secondary();
6147                 if (ret) {
6148                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6149                                      "process, ret = %d", ret);
6150                         goto err_mp_init_secondary;
6151                 }
6152
6153                 hw->secondary_cnt++;
6154                 return 0;
6155         }
6156
6157         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6158
6159         ret = hns3_mp_init_primary();
6160         if (ret) {
6161                 PMD_INIT_LOG(ERR,
6162                              "Failed to init for primary process, ret = %d",
6163                              ret);
6164                 goto err_mp_init_primary;
6165         }
6166
6167         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6168         hns->is_vf = false;
6169         hw->data = eth_dev->data;
6170
6171         /*
6172          * Set default max packet size according to the mtu
6173          * default vale in DPDK frame.
6174          */
6175         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6176
6177         ret = hns3_reset_init(hw);
6178         if (ret)
6179                 goto err_init_reset;
6180         hw->reset.ops = &hns3_reset_ops;
6181
6182         ret = hns3_init_pf(eth_dev);
6183         if (ret) {
6184                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6185                 goto err_init_pf;
6186         }
6187
6188         /* Allocate memory for storing MAC addresses */
6189         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6190                                                sizeof(struct rte_ether_addr) *
6191                                                HNS3_UC_MACADDR_NUM, 0);
6192         if (eth_dev->data->mac_addrs == NULL) {
6193                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6194                              "to store MAC addresses",
6195                              sizeof(struct rte_ether_addr) *
6196                              HNS3_UC_MACADDR_NUM);
6197                 ret = -ENOMEM;
6198                 goto err_rte_zmalloc;
6199         }
6200
6201         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6202         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6203                 rte_eth_random_addr(hw->mac.mac_addr);
6204                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6205                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6206                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6207                           "unicast address, using random MAC address %s",
6208                           mac_str);
6209         }
6210         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6211                             &eth_dev->data->mac_addrs[0]);
6212
6213         hw->adapter_state = HNS3_NIC_INITIALIZED;
6214
6215         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6216                 hns3_err(hw, "Reschedule reset service after dev_init");
6217                 hns3_schedule_reset(hns);
6218         } else {
6219                 /* IMP will wait ready flag before reset */
6220                 hns3_notify_reset_ready(hw, false);
6221         }
6222
6223         hns3_info(hw, "hns3 dev initialization successful!");
6224         return 0;
6225
6226 err_rte_zmalloc:
6227         hns3_uninit_pf(eth_dev);
6228
6229 err_init_pf:
6230         rte_free(hw->reset.wait_data);
6231
6232 err_init_reset:
6233         hns3_mp_uninit_primary();
6234
6235 err_mp_init_primary:
6236 err_mp_init_secondary:
6237         eth_dev->dev_ops = NULL;
6238         eth_dev->rx_pkt_burst = NULL;
6239         eth_dev->tx_pkt_burst = NULL;
6240         eth_dev->tx_pkt_prepare = NULL;
6241         rte_free(eth_dev->process_private);
6242         eth_dev->process_private = NULL;
6243         return ret;
6244 }
6245
6246 static int
6247 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6248 {
6249         struct hns3_adapter *hns = eth_dev->data->dev_private;
6250         struct hns3_hw *hw = &hns->hw;
6251
6252         PMD_INIT_FUNC_TRACE();
6253
6254         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6255                 return -EPERM;
6256
6257         if (hw->adapter_state < HNS3_NIC_CLOSING)
6258                 hns3_dev_close(eth_dev);
6259
6260         hw->adapter_state = HNS3_NIC_REMOVED;
6261         return 0;
6262 }
6263
6264 static int
6265 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6266                    struct rte_pci_device *pci_dev)
6267 {
6268         return rte_eth_dev_pci_generic_probe(pci_dev,
6269                                              sizeof(struct hns3_adapter),
6270                                              hns3_dev_init);
6271 }
6272
6273 static int
6274 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6275 {
6276         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6277 }
6278
6279 static const struct rte_pci_id pci_id_hns3_map[] = {
6280         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6281         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6282         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6283         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6284         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6285         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6286         { .vendor_id = 0, }, /* sentinel */
6287 };
6288
6289 static struct rte_pci_driver rte_hns3_pmd = {
6290         .id_table = pci_id_hns3_map,
6291         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6292         .probe = eth_hns3_pci_probe,
6293         .remove = eth_hns3_pci_remove,
6294 };
6295
6296 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6297 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6298 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6299 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6300 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);