1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2021 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3_SERVICE_QUICK_INTERVAL 10
24 #define HNS3_INVALID_PVID 0xFFFF
26 #define HNS3_FILTER_TYPE_VF 0
27 #define HNS3_FILTER_TYPE_PORT 1
28 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
30 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
31 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
32 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
33 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
34 | HNS3_FILTER_FE_ROCE_EGRESS_B)
35 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
36 | HNS3_FILTER_FE_ROCE_INGRESS_B)
38 /* Reset related Registers */
39 #define HNS3_GLOBAL_RESET_BIT 0
40 #define HNS3_CORE_RESET_BIT 1
41 #define HNS3_IMP_RESET_BIT 2
42 #define HNS3_FUN_RST_ING_B 0
44 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
46 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
49 #define HNS3_RESET_WAIT_MS 100
50 #define HNS3_RESET_WAIT_CNT 200
52 /* FEC mode order defined in HNS3 hardware */
53 #define HNS3_HW_FEC_MODE_NOFEC 0
54 #define HNS3_HW_FEC_MODE_BASER 1
55 #define HNS3_HW_FEC_MODE_RS 2
58 HNS3_VECTOR0_EVENT_RST,
59 HNS3_VECTOR0_EVENT_MBX,
60 HNS3_VECTOR0_EVENT_ERR,
61 HNS3_VECTOR0_EVENT_PTP,
62 HNS3_VECTOR0_EVENT_OTHER,
65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
66 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
67 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
70 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
72 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
75 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
76 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
79 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
81 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
84 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
85 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
88 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
89 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
90 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
99 static bool hns3_update_link_status(struct hns3_hw *hw);
101 static int hns3_add_mc_addr(struct hns3_hw *hw,
102 struct rte_ether_addr *mac_addr);
103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
104 struct rte_ether_addr *mac_addr);
105 static int hns3_restore_fec(struct hns3_hw *hw);
106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
107 static int hns3_do_stop(struct hns3_adapter *hns);
109 void hns3_ether_format_addr(char *buf, uint16_t size,
110 const struct rte_ether_addr *ether_addr)
112 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
113 ether_addr->addr_bytes[0],
114 ether_addr->addr_bytes[4],
115 ether_addr->addr_bytes[5]);
119 hns3_pf_disable_irq0(struct hns3_hw *hw)
121 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
125 hns3_pf_enable_irq0(struct hns3_hw *hw)
127 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
130 static enum hns3_evt_cause
131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
134 struct hns3_hw *hw = &hns->hw;
136 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
137 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
138 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
140 hw->reset.stats.imp_cnt++;
141 hns3_warn(hw, "IMP reset detected, clear reset status");
143 hns3_schedule_delayed_reset(hns);
144 hns3_warn(hw, "IMP reset detected, don't clear reset status");
147 return HNS3_VECTOR0_EVENT_RST;
150 static enum hns3_evt_cause
151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
154 struct hns3_hw *hw = &hns->hw;
156 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
157 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
158 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
160 hw->reset.stats.global_cnt++;
161 hns3_warn(hw, "Global reset detected, clear reset status");
163 hns3_schedule_delayed_reset(hns);
165 "Global reset detected, don't clear reset status");
168 return HNS3_VECTOR0_EVENT_RST;
171 static enum hns3_evt_cause
172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
174 struct hns3_hw *hw = &hns->hw;
175 uint32_t vector0_int_stats;
176 uint32_t cmdq_src_val;
177 uint32_t hw_err_src_reg;
179 enum hns3_evt_cause ret;
182 /* fetch the events from their corresponding regs */
183 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
184 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
185 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
187 is_delay = clearval == NULL ? true : false;
189 * Assumption: If by any chance reset and mailbox events are reported
190 * together then we will only process reset event and defer the
191 * processing of the mailbox events. Since, we would have not cleared
192 * RX CMDQ event this time we would receive again another interrupt
193 * from H/W just for the mailbox.
195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
196 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
201 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
202 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
206 /* Check for vector0 1588 event source */
207 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
208 val = BIT(HNS3_VECTOR0_1588_INT_B);
209 ret = HNS3_VECTOR0_EVENT_PTP;
213 /* check for vector0 msix event source */
214 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
215 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
216 val = vector0_int_stats | hw_err_src_reg;
217 ret = HNS3_VECTOR0_EVENT_ERR;
221 /* check for vector0 mailbox(=CMDQ RX) event source */
222 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
223 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
225 ret = HNS3_VECTOR0_EVENT_MBX;
229 val = vector0_int_stats;
230 ret = HNS3_VECTOR0_EVENT_OTHER;
239 hns3_is_1588_event_type(uint32_t event_type)
241 return (event_type == HNS3_VECTOR0_EVENT_PTP);
245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
247 if (event_type == HNS3_VECTOR0_EVENT_RST ||
248 hns3_is_1588_event_type(event_type))
249 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
250 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
251 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
255 hns3_clear_all_event_cause(struct hns3_hw *hw)
257 uint32_t vector0_int_stats;
258 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
260 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
261 hns3_warn(hw, "Probe during IMP reset interrupt");
263 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
264 hns3_warn(hw, "Probe during Global reset interrupt");
266 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
267 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
268 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
269 BIT(HNS3_VECTOR0_CORERESET_INT_B));
270 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
271 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
272 BIT(HNS3_VECTOR0_1588_INT_B));
276 hns3_handle_mac_tnl(struct hns3_hw *hw)
278 struct hns3_cmd_desc desc;
282 /* query and clear mac tnl interruptions */
283 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
284 ret = hns3_cmd_send(hw, &desc, 1);
286 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
290 status = rte_le_to_cpu_32(desc.data[0]);
292 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
293 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
295 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
296 ret = hns3_cmd_send(hw, &desc, 1);
298 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
304 hns3_interrupt_handler(void *param)
306 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
307 struct hns3_adapter *hns = dev->data->dev_private;
308 struct hns3_hw *hw = &hns->hw;
309 enum hns3_evt_cause event_cause;
310 uint32_t clearval = 0;
311 uint32_t vector0_int;
315 /* Disable interrupt */
316 hns3_pf_disable_irq0(hw);
318 event_cause = hns3_check_event_cause(hns, &clearval);
319 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
320 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
321 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
322 /* vector 0 interrupt is shared with reset and mailbox source events. */
323 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
324 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
325 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
326 vector0_int, ras_int, cmdq_int);
327 hns3_handle_msix_error(hns, &hw->reset.request);
328 hns3_handle_ras_error(hns, &hw->reset.request);
329 hns3_handle_mac_tnl(hw);
330 hns3_schedule_reset(hns);
331 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
332 hns3_warn(hw, "received reset interrupt");
333 hns3_schedule_reset(hns);
334 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
335 hns3_dev_handle_mbx_msg(hw);
337 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
338 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
339 vector0_int, ras_int, cmdq_int);
342 hns3_clear_event_cause(hw, event_cause, clearval);
343 /* Enable interrupt if it is not cause by reset */
344 hns3_pf_enable_irq0(hw);
348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
350 #define HNS3_VLAN_ID_OFFSET_STEP 160
351 #define HNS3_VLAN_BYTE_SIZE 8
352 struct hns3_vlan_filter_pf_cfg_cmd *req;
353 struct hns3_hw *hw = &hns->hw;
354 uint8_t vlan_offset_byte_val;
355 struct hns3_cmd_desc desc;
356 uint8_t vlan_offset_byte;
357 uint8_t vlan_offset_base;
360 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
362 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
363 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
365 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
367 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
368 req->vlan_offset = vlan_offset_base;
369 req->vlan_cfg = on ? 0 : 1;
370 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
372 ret = hns3_cmd_send(hw, &desc, 1);
374 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
383 struct hns3_user_vlan_table *vlan_entry;
384 struct hns3_pf *pf = &hns->pf;
386 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
387 if (vlan_entry->vlan_id == vlan_id) {
388 if (vlan_entry->hd_tbl_status)
389 hns3_set_port_vlan_filter(hns, vlan_id, 0);
390 LIST_REMOVE(vlan_entry, next);
391 rte_free(vlan_entry);
398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
401 struct hns3_user_vlan_table *vlan_entry;
402 struct hns3_hw *hw = &hns->hw;
403 struct hns3_pf *pf = &hns->pf;
405 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
406 if (vlan_entry->vlan_id == vlan_id)
410 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
411 if (vlan_entry == NULL) {
412 hns3_err(hw, "Failed to malloc hns3 vlan table");
416 vlan_entry->hd_tbl_status = writen_to_tbl;
417 vlan_entry->vlan_id = vlan_id;
419 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
423 hns3_restore_vlan_table(struct hns3_adapter *hns)
425 struct hns3_user_vlan_table *vlan_entry;
426 struct hns3_hw *hw = &hns->hw;
427 struct hns3_pf *pf = &hns->pf;
431 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
432 return hns3_vlan_pvid_configure(hns,
433 hw->port_base_vlan_cfg.pvid, 1);
435 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
436 if (vlan_entry->hd_tbl_status) {
437 vlan_id = vlan_entry->vlan_id;
438 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
450 struct hns3_hw *hw = &hns->hw;
451 bool writen_to_tbl = false;
455 * When vlan filter is enabled, hardware regards packets without vlan
456 * as packets with vlan 0. So, to receive packets without vlan, vlan id
457 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
459 if (on == 0 && vlan_id == 0)
463 * When port base vlan enabled, we use port base vlan as the vlan
464 * filter condition. In this case, we don't update vlan filter table
465 * when user add new vlan or remove exist vlan, just update the
466 * vlan list. The vlan id in vlan list will be writen in vlan filter
467 * table until port base vlan disabled
469 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
470 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
471 writen_to_tbl = true;
476 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
478 hns3_rm_dev_vlan_table(hns, vlan_id);
484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
486 struct hns3_adapter *hns = dev->data->dev_private;
487 struct hns3_hw *hw = &hns->hw;
490 rte_spinlock_lock(&hw->lock);
491 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
492 rte_spinlock_unlock(&hw->lock);
497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
500 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
501 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
502 struct hns3_hw *hw = &hns->hw;
503 struct hns3_cmd_desc desc;
506 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
507 vlan_type != ETH_VLAN_TYPE_OUTER)) {
508 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
512 if (tpid != RTE_ETHER_TYPE_VLAN) {
513 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
517 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
518 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
520 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
521 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
523 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
524 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
525 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
526 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
527 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
530 ret = hns3_cmd_send(hw, &desc, 1);
532 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
537 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
539 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
540 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
541 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
543 ret = hns3_cmd_send(hw, &desc, 1);
545 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
554 struct hns3_adapter *hns = dev->data->dev_private;
555 struct hns3_hw *hw = &hns->hw;
558 rte_spinlock_lock(&hw->lock);
559 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
560 rte_spinlock_unlock(&hw->lock);
565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
566 struct hns3_rx_vtag_cfg *vcfg)
568 struct hns3_vport_vtag_rx_cfg_cmd *req;
569 struct hns3_hw *hw = &hns->hw;
570 struct hns3_cmd_desc desc;
575 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
577 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
578 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
579 vcfg->strip_tag1_en ? 1 : 0);
580 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
581 vcfg->strip_tag2_en ? 1 : 0);
582 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
583 vcfg->vlan1_vlan_prionly ? 1 : 0);
584 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
585 vcfg->vlan2_vlan_prionly ? 1 : 0);
587 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
588 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
589 vcfg->strip_tag1_discard_en ? 1 : 0);
590 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
591 vcfg->strip_tag2_discard_en ? 1 : 0);
593 * In current version VF is not supported when PF is driven by DPDK
594 * driver, just need to configure parameters for PF vport.
596 vport_id = HNS3_PF_FUNC_ID;
597 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
598 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
599 req->vf_bitmap[req->vf_offset] = bitmap;
601 ret = hns3_cmd_send(hw, &desc, 1);
603 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
609 struct hns3_rx_vtag_cfg *vcfg)
611 struct hns3_pf *pf = &hns->pf;
612 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
617 struct hns3_tx_vtag_cfg *vcfg)
619 struct hns3_pf *pf = &hns->pf;
620 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
626 struct hns3_rx_vtag_cfg rxvlan_cfg;
627 struct hns3_hw *hw = &hns->hw;
630 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
631 rxvlan_cfg.strip_tag1_en = false;
632 rxvlan_cfg.strip_tag2_en = enable;
633 rxvlan_cfg.strip_tag2_discard_en = false;
635 rxvlan_cfg.strip_tag1_en = enable;
636 rxvlan_cfg.strip_tag2_en = true;
637 rxvlan_cfg.strip_tag2_discard_en = true;
640 rxvlan_cfg.strip_tag1_discard_en = false;
641 rxvlan_cfg.vlan1_vlan_prionly = false;
642 rxvlan_cfg.vlan2_vlan_prionly = false;
643 rxvlan_cfg.rx_vlan_offload_en = enable;
645 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
647 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
651 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
658 uint8_t fe_type, bool filter_en, uint8_t vf_id)
660 struct hns3_vlan_filter_ctrl_cmd *req;
661 struct hns3_cmd_desc desc;
664 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
666 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
667 req->vlan_type = vlan_type;
668 req->vlan_fe = filter_en ? fe_type : 0;
671 ret = hns3_cmd_send(hw, &desc, 1);
673 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
679 hns3_vlan_filter_init(struct hns3_adapter *hns)
681 struct hns3_hw *hw = &hns->hw;
684 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
685 HNS3_FILTER_FE_EGRESS, false,
688 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
692 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
693 HNS3_FILTER_FE_INGRESS, false,
696 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
704 struct hns3_hw *hw = &hns->hw;
707 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
708 HNS3_FILTER_FE_INGRESS, enable,
711 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
712 enable ? "enable" : "disable", ret);
718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
720 struct hns3_adapter *hns = dev->data->dev_private;
721 struct hns3_hw *hw = &hns->hw;
722 struct rte_eth_rxmode *rxmode;
723 unsigned int tmp_mask;
727 rte_spinlock_lock(&hw->lock);
728 rxmode = &dev->data->dev_conf.rxmode;
729 tmp_mask = (unsigned int)mask;
730 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
731 /* ignore vlan filter configuration during promiscuous mode */
732 if (!dev->data->promiscuous) {
733 /* Enable or disable VLAN filter */
734 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
737 ret = hns3_enable_vlan_filter(hns, enable);
739 rte_spinlock_unlock(&hw->lock);
740 hns3_err(hw, "failed to %s rx filter, ret = %d",
741 enable ? "enable" : "disable", ret);
747 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
748 /* Enable or disable VLAN stripping */
749 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
752 ret = hns3_en_hw_strip_rxvtag(hns, enable);
754 rte_spinlock_unlock(&hw->lock);
755 hns3_err(hw, "failed to %s rx strip, ret = %d",
756 enable ? "enable" : "disable", ret);
761 rte_spinlock_unlock(&hw->lock);
767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
768 struct hns3_tx_vtag_cfg *vcfg)
770 struct hns3_vport_vtag_tx_cfg_cmd *req;
771 struct hns3_cmd_desc desc;
772 struct hns3_hw *hw = &hns->hw;
777 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
779 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
780 req->def_vlan_tag1 = vcfg->default_tag1;
781 req->def_vlan_tag2 = vcfg->default_tag2;
782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
783 vcfg->accept_tag1 ? 1 : 0);
784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
785 vcfg->accept_untag1 ? 1 : 0);
786 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
787 vcfg->accept_tag2 ? 1 : 0);
788 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
789 vcfg->accept_untag2 ? 1 : 0);
790 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
791 vcfg->insert_tag1_en ? 1 : 0);
792 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
793 vcfg->insert_tag2_en ? 1 : 0);
794 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
796 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
797 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
798 vcfg->tag_shift_mode_en ? 1 : 0);
801 * In current version VF is not supported when PF is driven by DPDK
802 * driver, just need to configure parameters for PF vport.
804 vport_id = HNS3_PF_FUNC_ID;
805 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
806 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
807 req->vf_bitmap[req->vf_offset] = bitmap;
809 ret = hns3_cmd_send(hw, &desc, 1);
811 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
820 struct hns3_hw *hw = &hns->hw;
821 struct hns3_tx_vtag_cfg txvlan_cfg;
824 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
825 txvlan_cfg.accept_tag1 = true;
826 txvlan_cfg.insert_tag1_en = false;
827 txvlan_cfg.default_tag1 = 0;
829 txvlan_cfg.accept_tag1 =
830 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
831 txvlan_cfg.insert_tag1_en = true;
832 txvlan_cfg.default_tag1 = pvid;
835 txvlan_cfg.accept_untag1 = true;
836 txvlan_cfg.accept_tag2 = true;
837 txvlan_cfg.accept_untag2 = true;
838 txvlan_cfg.insert_tag2_en = false;
839 txvlan_cfg.default_tag2 = 0;
840 txvlan_cfg.tag_shift_mode_en = true;
842 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
844 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
849 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
857 struct hns3_user_vlan_table *vlan_entry;
858 struct hns3_pf *pf = &hns->pf;
860 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
861 if (vlan_entry->hd_tbl_status) {
862 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
863 vlan_entry->hd_tbl_status = false;
868 vlan_entry = LIST_FIRST(&pf->vlan_list);
870 LIST_REMOVE(vlan_entry, next);
871 rte_free(vlan_entry);
872 vlan_entry = LIST_FIRST(&pf->vlan_list);
878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
880 struct hns3_user_vlan_table *vlan_entry;
881 struct hns3_pf *pf = &hns->pf;
883 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
884 if (!vlan_entry->hd_tbl_status) {
885 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
886 vlan_entry->hd_tbl_status = true;
892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
894 struct hns3_hw *hw = &hns->hw;
897 hns3_rm_all_vlan_table(hns, true);
898 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
899 ret = hns3_set_port_vlan_filter(hns,
900 hw->port_base_vlan_cfg.pvid, 0);
902 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
911 uint16_t port_base_vlan_state, uint16_t new_pvid)
913 struct hns3_hw *hw = &hns->hw;
917 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
918 old_pvid = hw->port_base_vlan_cfg.pvid;
919 if (old_pvid != HNS3_INVALID_PVID) {
920 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
922 hns3_err(hw, "failed to remove old pvid %u, "
923 "ret = %d", old_pvid, ret);
928 hns3_rm_all_vlan_table(hns, false);
929 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
931 hns3_err(hw, "failed to add new pvid %u, ret = %d",
936 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
938 hns3_err(hw, "failed to remove pvid %u, ret = %d",
943 hns3_add_all_vlan_table(hns);
949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
951 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
952 struct hns3_rx_vtag_cfg rx_vlan_cfg;
956 rx_strip_en = old_cfg->rx_vlan_offload_en;
958 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
959 rx_vlan_cfg.strip_tag2_en = true;
960 rx_vlan_cfg.strip_tag2_discard_en = true;
962 rx_vlan_cfg.strip_tag1_en = false;
963 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
964 rx_vlan_cfg.strip_tag2_discard_en = false;
966 rx_vlan_cfg.strip_tag1_discard_en = false;
967 rx_vlan_cfg.vlan1_vlan_prionly = false;
968 rx_vlan_cfg.vlan2_vlan_prionly = false;
969 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
971 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
975 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
982 struct hns3_hw *hw = &hns->hw;
983 uint16_t port_base_vlan_state;
986 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
987 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
988 hns3_warn(hw, "Invalid operation! As current pvid set "
989 "is %u, disable pvid %u is invalid",
990 hw->port_base_vlan_cfg.pvid, pvid);
994 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
995 HNS3_PORT_BASE_VLAN_DISABLE;
996 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
998 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1003 ret = hns3_en_pvid_strip(hns, on);
1005 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1007 goto pvid_vlan_strip_fail;
1010 if (pvid == HNS3_INVALID_PVID)
1012 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1014 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1016 goto vlan_filter_set_fail;
1020 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1024 vlan_filter_set_fail:
1025 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1026 HNS3_PORT_BASE_VLAN_ENABLE);
1028 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1030 pvid_vlan_strip_fail:
1031 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1032 hw->port_base_vlan_cfg.pvid);
1034 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1040 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1042 struct hns3_adapter *hns = dev->data->dev_private;
1043 struct hns3_hw *hw = &hns->hw;
1044 bool pvid_en_state_change;
1045 uint16_t pvid_state;
1048 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1049 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1050 RTE_ETHER_MAX_VLAN_ID);
1055 * If PVID configuration state change, should refresh the PVID
1056 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1058 pvid_state = hw->port_base_vlan_cfg.state;
1059 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1060 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1061 pvid_en_state_change = false;
1063 pvid_en_state_change = true;
1065 rte_spinlock_lock(&hw->lock);
1066 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1067 rte_spinlock_unlock(&hw->lock);
1071 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1072 * need be processed by PMD driver.
1074 if (pvid_en_state_change &&
1075 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1076 hns3_update_all_queues_pvid_proc_en(hw);
1082 hns3_default_vlan_config(struct hns3_adapter *hns)
1084 struct hns3_hw *hw = &hns->hw;
1088 * When vlan filter is enabled, hardware regards packets without vlan
1089 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1090 * table, packets without vlan won't be received. So, add vlan 0 as
1093 ret = hns3_vlan_filter_configure(hns, 0, 1);
1095 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1100 hns3_init_vlan_config(struct hns3_adapter *hns)
1102 struct hns3_hw *hw = &hns->hw;
1106 * This function can be called in the initialization and reset process,
1107 * when in reset process, it means that hardware had been reseted
1108 * successfully and we need to restore the hardware configuration to
1109 * ensure that the hardware configuration remains unchanged before and
1112 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1113 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1114 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1117 ret = hns3_vlan_filter_init(hns);
1119 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1123 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1124 RTE_ETHER_TYPE_VLAN);
1126 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1131 * When in the reinit dev stage of the reset process, the following
1132 * vlan-related configurations may differ from those at initialization,
1133 * we will restore configurations to hardware in hns3_restore_vlan_table
1134 * and hns3_restore_vlan_conf later.
1136 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1137 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1139 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1143 ret = hns3_en_hw_strip_rxvtag(hns, false);
1145 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1151 return hns3_default_vlan_config(hns);
1155 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1157 struct hns3_pf *pf = &hns->pf;
1158 struct hns3_hw *hw = &hns->hw;
1163 if (!hw->data->promiscuous) {
1164 /* restore vlan filter states */
1165 offloads = hw->data->dev_conf.rxmode.offloads;
1166 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1167 ret = hns3_enable_vlan_filter(hns, enable);
1169 hns3_err(hw, "failed to restore vlan rx filter conf, "
1175 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1177 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1181 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1183 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1189 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1191 struct hns3_adapter *hns = dev->data->dev_private;
1192 struct rte_eth_dev_data *data = dev->data;
1193 struct rte_eth_txmode *txmode;
1194 struct hns3_hw *hw = &hns->hw;
1198 txmode = &data->dev_conf.txmode;
1199 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1201 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1202 "configuration is not supported! Ignore these two "
1203 "parameters: hw_vlan_reject_tagged(%u), "
1204 "hw_vlan_reject_untagged(%u)",
1205 txmode->hw_vlan_reject_tagged,
1206 txmode->hw_vlan_reject_untagged);
1208 /* Apply vlan offload setting */
1209 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1210 ret = hns3_vlan_offload_set(dev, mask);
1212 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1218 * If pvid config is not set in rte_eth_conf, driver needn't to set
1219 * VLAN pvid related configuration to hardware.
1221 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1224 /* Apply pvid setting */
1225 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1226 txmode->hw_vlan_insert_pvid);
1228 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1235 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1236 unsigned int tso_mss_max)
1238 struct hns3_cfg_tso_status_cmd *req;
1239 struct hns3_cmd_desc desc;
1242 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1244 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1247 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1249 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1252 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1254 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1256 return hns3_cmd_send(hw, &desc, 1);
1260 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1261 uint16_t *allocated_size, bool is_alloc)
1263 struct hns3_umv_spc_alc_cmd *req;
1264 struct hns3_cmd_desc desc;
1267 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1268 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1269 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1270 req->space_size = rte_cpu_to_le_32(space_size);
1272 ret = hns3_cmd_send(hw, &desc, 1);
1274 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1275 is_alloc ? "allocate" : "free", ret);
1279 if (is_alloc && allocated_size)
1280 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1286 hns3_init_umv_space(struct hns3_hw *hw)
1288 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1289 struct hns3_pf *pf = &hns->pf;
1290 uint16_t allocated_size = 0;
1293 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1298 if (allocated_size < pf->wanted_umv_size)
1299 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1300 pf->wanted_umv_size, allocated_size);
1302 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1303 pf->wanted_umv_size;
1304 pf->used_umv_size = 0;
1309 hns3_uninit_umv_space(struct hns3_hw *hw)
1311 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312 struct hns3_pf *pf = &hns->pf;
1315 if (pf->max_umv_size == 0)
1318 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1322 pf->max_umv_size = 0;
1328 hns3_is_umv_space_full(struct hns3_hw *hw)
1330 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331 struct hns3_pf *pf = &hns->pf;
1334 is_full = (pf->used_umv_size >= pf->max_umv_size);
1340 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1342 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1343 struct hns3_pf *pf = &hns->pf;
1346 if (pf->used_umv_size > 0)
1347 pf->used_umv_size--;
1349 pf->used_umv_size++;
1353 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1354 const uint8_t *addr, bool is_mc)
1356 const unsigned char *mac_addr = addr;
1357 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1358 ((uint32_t)mac_addr[2] << 16) |
1359 ((uint32_t)mac_addr[1] << 8) |
1360 (uint32_t)mac_addr[0];
1361 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1363 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1365 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1366 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1367 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1370 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1371 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1375 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1377 enum hns3_mac_vlan_tbl_opcode op)
1380 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1385 if (op == HNS3_MAC_VLAN_ADD) {
1386 if (resp_code == 0 || resp_code == 1) {
1388 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1389 hns3_err(hw, "add mac addr failed for uc_overflow");
1391 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1392 hns3_err(hw, "add mac addr failed for mc_overflow");
1396 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1399 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1400 if (resp_code == 0) {
1402 } else if (resp_code == 1) {
1403 hns3_dbg(hw, "remove mac addr failed for miss");
1407 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1410 } else if (op == HNS3_MAC_VLAN_LKUP) {
1411 if (resp_code == 0) {
1413 } else if (resp_code == 1) {
1414 hns3_dbg(hw, "lookup mac addr failed for miss");
1418 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1423 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1430 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1431 struct hns3_mac_vlan_tbl_entry_cmd *req,
1432 struct hns3_cmd_desc *desc, bool is_mc)
1438 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1440 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1441 memcpy(desc[0].data, req,
1442 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1443 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1445 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1446 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1448 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1450 memcpy(desc[0].data, req,
1451 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1452 ret = hns3_cmd_send(hw, desc, 1);
1455 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1459 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1460 retval = rte_le_to_cpu_16(desc[0].retval);
1462 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1463 HNS3_MAC_VLAN_LKUP);
1467 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1468 struct hns3_mac_vlan_tbl_entry_cmd *req,
1469 struct hns3_cmd_desc *mc_desc)
1476 if (mc_desc == NULL) {
1477 struct hns3_cmd_desc desc;
1479 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480 memcpy(desc.data, req,
1481 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482 ret = hns3_cmd_send(hw, &desc, 1);
1483 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1484 retval = rte_le_to_cpu_16(desc.retval);
1486 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1489 hns3_cmd_reuse_desc(&mc_desc[0], false);
1490 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491 hns3_cmd_reuse_desc(&mc_desc[1], false);
1492 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1493 hns3_cmd_reuse_desc(&mc_desc[2], false);
1494 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1495 memcpy(mc_desc[0].data, req,
1496 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1497 mc_desc[0].retval = 0;
1498 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1499 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1500 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1502 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1507 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1515 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1516 struct hns3_mac_vlan_tbl_entry_cmd *req)
1518 struct hns3_cmd_desc desc;
1523 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1525 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1527 ret = hns3_cmd_send(hw, &desc, 1);
1529 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1532 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1533 retval = rte_le_to_cpu_16(desc.retval);
1535 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1536 HNS3_MAC_VLAN_REMOVE);
1540 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1542 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1543 struct hns3_mac_vlan_tbl_entry_cmd req;
1544 struct hns3_pf *pf = &hns->pf;
1545 struct hns3_cmd_desc desc[3];
1546 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1547 uint16_t egress_port = 0;
1551 /* check if mac addr is valid */
1552 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1553 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1555 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1560 memset(&req, 0, sizeof(req));
1563 * In current version VF is not supported when PF is driven by DPDK
1564 * driver, just need to configure parameters for PF vport.
1566 vf_id = HNS3_PF_FUNC_ID;
1567 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1568 HNS3_MAC_EPORT_VFID_S, vf_id);
1570 req.egress_port = rte_cpu_to_le_16(egress_port);
1572 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1575 * Lookup the mac address in the mac_vlan table, and add
1576 * it if the entry is inexistent. Repeated unicast entry
1577 * is not allowed in the mac vlan table.
1579 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1580 if (ret == -ENOENT) {
1581 if (!hns3_is_umv_space_full(hw)) {
1582 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1584 hns3_update_umv_space(hw, false);
1588 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1593 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1595 /* check if we just hit the duplicate */
1597 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1601 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1608 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1610 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611 struct rte_ether_addr *addr;
1615 for (i = 0; i < hw->mc_addrs_num; i++) {
1616 addr = &hw->mc_addrs[i];
1617 /* Check if there are duplicate addresses */
1618 if (rte_is_same_ether_addr(addr, mac_addr)) {
1619 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1621 hns3_err(hw, "failed to add mc mac addr, same addrs"
1622 "(%s) is added by the set_mc_mac_addr_list "
1628 ret = hns3_add_mc_addr(hw, mac_addr);
1630 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1632 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1639 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1641 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1644 ret = hns3_remove_mc_addr(hw, mac_addr);
1646 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1648 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1655 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1656 uint32_t idx, __rte_unused uint32_t pool)
1658 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1662 rte_spinlock_lock(&hw->lock);
1665 * In hns3 network engine adding UC and MC mac address with different
1666 * commands with firmware. We need to determine whether the input
1667 * address is a UC or a MC address to call different commands.
1668 * By the way, it is recommended calling the API function named
1669 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1670 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1671 * may affect the specifications of UC mac addresses.
1673 if (rte_is_multicast_ether_addr(mac_addr))
1674 ret = hns3_add_mc_addr_common(hw, mac_addr);
1676 ret = hns3_add_uc_addr_common(hw, mac_addr);
1679 rte_spinlock_unlock(&hw->lock);
1680 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1682 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1688 hw->mac.default_addr_setted = true;
1689 rte_spinlock_unlock(&hw->lock);
1695 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1697 struct hns3_mac_vlan_tbl_entry_cmd req;
1698 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1701 /* check if mac addr is valid */
1702 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1703 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1705 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1710 memset(&req, 0, sizeof(req));
1711 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1712 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1713 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1714 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1717 hns3_update_umv_space(hw, true);
1723 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1725 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 /* index will be checked by upper level rte interface */
1727 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1728 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1731 rte_spinlock_lock(&hw->lock);
1733 if (rte_is_multicast_ether_addr(mac_addr))
1734 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1736 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1737 rte_spinlock_unlock(&hw->lock);
1739 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1741 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1747 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1748 struct rte_ether_addr *mac_addr)
1750 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751 struct rte_ether_addr *oaddr;
1752 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753 bool default_addr_setted;
1754 bool rm_succes = false;
1758 * It has been guaranteed that input parameter named mac_addr is valid
1759 * address in the rte layer of DPDK framework.
1761 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1762 default_addr_setted = hw->mac.default_addr_setted;
1763 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1766 rte_spinlock_lock(&hw->lock);
1767 if (default_addr_setted) {
1768 ret = hns3_remove_uc_addr_common(hw, oaddr);
1770 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1772 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1779 ret = hns3_add_uc_addr_common(hw, mac_addr);
1781 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1783 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1784 goto err_add_uc_addr;
1787 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1789 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1790 goto err_pause_addr_cfg;
1793 rte_ether_addr_copy(mac_addr,
1794 (struct rte_ether_addr *)hw->mac.mac_addr);
1795 hw->mac.default_addr_setted = true;
1796 rte_spinlock_unlock(&hw->lock);
1801 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1803 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806 "Failed to roll back to del setted mac addr(%s): %d",
1812 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1814 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1817 "Failed to restore old uc mac addr(%s): %d",
1819 hw->mac.default_addr_setted = false;
1822 rte_spinlock_unlock(&hw->lock);
1828 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1830 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1831 struct hns3_hw *hw = &hns->hw;
1832 struct rte_ether_addr *addr;
1837 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1838 addr = &hw->data->mac_addrs[i];
1839 if (rte_is_zero_ether_addr(addr))
1841 if (rte_is_multicast_ether_addr(addr))
1842 ret = del ? hns3_remove_mc_addr(hw, addr) :
1843 hns3_add_mc_addr(hw, addr);
1845 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1846 hns3_add_uc_addr_common(hw, addr);
1850 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1852 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1853 "ret = %d.", del ? "remove" : "restore",
1861 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1863 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1867 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1868 word_num = vfid / 32;
1869 bit_num = vfid % 32;
1871 desc[1].data[word_num] &=
1872 rte_cpu_to_le_32(~(1UL << bit_num));
1874 desc[1].data[word_num] |=
1875 rte_cpu_to_le_32(1UL << bit_num);
1877 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1878 bit_num = vfid % 32;
1880 desc[2].data[word_num] &=
1881 rte_cpu_to_le_32(~(1UL << bit_num));
1883 desc[2].data[word_num] |=
1884 rte_cpu_to_le_32(1UL << bit_num);
1889 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1891 struct hns3_mac_vlan_tbl_entry_cmd req;
1892 struct hns3_cmd_desc desc[3];
1893 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1897 /* Check if mac addr is valid */
1898 if (!rte_is_multicast_ether_addr(mac_addr)) {
1899 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1901 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1906 memset(&req, 0, sizeof(req));
1907 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1908 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1909 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1911 /* This mac addr do not exist, add new entry for it */
1912 memset(desc[0].data, 0, sizeof(desc[0].data));
1913 memset(desc[1].data, 0, sizeof(desc[0].data));
1914 memset(desc[2].data, 0, sizeof(desc[0].data));
1918 * In current version VF is not supported when PF is driven by DPDK
1919 * driver, just need to configure parameters for PF vport.
1921 vf_id = HNS3_PF_FUNC_ID;
1922 hns3_update_desc_vfid(desc, vf_id, false);
1923 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1926 hns3_err(hw, "mc mac vlan table is full");
1927 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1929 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1936 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1938 struct hns3_mac_vlan_tbl_entry_cmd req;
1939 struct hns3_cmd_desc desc[3];
1940 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1944 /* Check if mac addr is valid */
1945 if (!rte_is_multicast_ether_addr(mac_addr)) {
1946 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1948 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1953 memset(&req, 0, sizeof(req));
1954 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1955 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1956 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1959 * This mac addr exist, remove this handle's VFID for it.
1960 * In current version VF is not supported when PF is driven by
1961 * DPDK driver, just need to configure parameters for PF vport.
1963 vf_id = HNS3_PF_FUNC_ID;
1964 hns3_update_desc_vfid(desc, vf_id, true);
1966 /* All the vfid is zero, so need to delete this entry */
1967 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968 } else if (ret == -ENOENT) {
1969 /* This mac addr doesn't exist. */
1974 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1976 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984 struct rte_ether_addr *mc_addr_set,
1985 uint32_t nb_mc_addr)
1987 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988 struct rte_ether_addr *addr;
1992 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994 "invalid. valid range: 0~%d",
1995 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1999 /* Check if input mac addresses are valid */
2000 for (i = 0; i < nb_mc_addr; i++) {
2001 addr = &mc_addr_set[i];
2002 if (!rte_is_multicast_ether_addr(addr)) {
2003 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2006 "failed to set mc mac addr, addr(%s) invalid.",
2011 /* Check if there are duplicate addresses */
2012 for (j = i + 1; j < nb_mc_addr; j++) {
2013 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014 hns3_ether_format_addr(mac_str,
2015 RTE_ETHER_ADDR_FMT_SIZE,
2017 hns3_err(hw, "failed to set mc mac addr, "
2018 "addrs invalid. two same addrs(%s).",
2025 * Check if there are duplicate addresses between mac_addrs
2028 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029 if (rte_is_same_ether_addr(addr,
2030 &hw->data->mac_addrs[j])) {
2031 hns3_ether_format_addr(mac_str,
2032 RTE_ETHER_ADDR_FMT_SIZE,
2034 hns3_err(hw, "failed to set mc mac addr, "
2035 "addrs invalid. addrs(%s) has already "
2036 "configured in mac_addr add API",
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048 struct rte_ether_addr *mc_addr_set,
2050 struct rte_ether_addr *reserved_addr_list,
2051 int *reserved_addr_num,
2052 struct rte_ether_addr *add_addr_list,
2054 struct rte_ether_addr *rm_addr_list,
2057 struct rte_ether_addr *addr;
2058 int current_addr_num;
2059 int reserved_num = 0;
2067 /* Calculate the mc mac address list that should be removed */
2068 current_addr_num = hw->mc_addrs_num;
2069 for (i = 0; i < current_addr_num; i++) {
2070 addr = &hw->mc_addrs[i];
2072 for (j = 0; j < mc_addr_num; j++) {
2073 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2080 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2083 rte_ether_addr_copy(addr,
2084 &reserved_addr_list[reserved_num]);
2089 /* Calculate the mc mac address list that should be added */
2090 for (i = 0; i < mc_addr_num; i++) {
2091 addr = &mc_addr_set[i];
2093 for (j = 0; j < current_addr_num; j++) {
2094 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2101 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2106 /* Reorder the mc mac address list maintained by driver */
2107 for (i = 0; i < reserved_num; i++)
2108 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2110 for (i = 0; i < rm_num; i++) {
2111 num = reserved_num + i;
2112 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2115 *reserved_addr_num = reserved_num;
2116 *add_addr_num = add_num;
2117 *rm_addr_num = rm_num;
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122 struct rte_ether_addr *mc_addr_set,
2123 uint32_t nb_mc_addr)
2125 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129 struct rte_ether_addr *addr;
2130 int reserved_addr_num;
2138 /* Check if input parameters are valid */
2139 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2143 rte_spinlock_lock(&hw->lock);
2146 * Calculate the mc mac address lists those should be removed and be
2147 * added, Reorder the mc mac address list maintained by driver.
2149 mc_addr_num = (int)nb_mc_addr;
2150 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151 reserved_addr_list, &reserved_addr_num,
2152 add_addr_list, &add_addr_num,
2153 rm_addr_list, &rm_addr_num);
2155 /* Remove mc mac addresses */
2156 for (i = 0; i < rm_addr_num; i++) {
2157 num = rm_addr_num - i - 1;
2158 addr = &rm_addr_list[num];
2159 ret = hns3_remove_mc_addr(hw, addr);
2161 rte_spinlock_unlock(&hw->lock);
2167 /* Add mc mac addresses */
2168 for (i = 0; i < add_addr_num; i++) {
2169 addr = &add_addr_list[i];
2170 ret = hns3_add_mc_addr(hw, addr);
2172 rte_spinlock_unlock(&hw->lock);
2176 num = reserved_addr_num + i;
2177 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2180 rte_spinlock_unlock(&hw->lock);
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2188 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189 struct hns3_hw *hw = &hns->hw;
2190 struct rte_ether_addr *addr;
2195 for (i = 0; i < hw->mc_addrs_num; i++) {
2196 addr = &hw->mc_addrs[i];
2197 if (!rte_is_multicast_ether_addr(addr))
2200 ret = hns3_remove_mc_addr(hw, addr);
2202 ret = hns3_add_mc_addr(hw, addr);
2205 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2207 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208 del ? "Remove" : "Restore", mac_str, ret);
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2217 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2227 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2228 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2230 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2231 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2232 "rx_mq_mode = %d", rx_mq_mode);
2236 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2237 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2238 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2239 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2240 rx_mq_mode, tx_mq_mode);
2244 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2245 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2246 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2247 dcb_rx_conf->nb_tcs, pf->tc_max);
2251 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2252 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2253 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2254 "nb_tcs(%d) != %d or %d in rx direction.",
2255 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2259 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2260 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2261 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2265 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2266 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2267 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2268 "is not equal to one in tx direction.",
2269 i, dcb_rx_conf->dcb_tc[i]);
2272 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2273 max_tc = dcb_rx_conf->dcb_tc[i];
2276 num_tc = max_tc + 1;
2277 if (num_tc > dcb_rx_conf->nb_tcs) {
2278 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2279 num_tc, dcb_rx_conf->nb_tcs);
2288 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2290 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292 if (!hns3_dev_dcb_supported(hw)) {
2293 hns3_err(hw, "this port does not support dcb configurations.");
2297 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2298 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2302 /* Check multiple queue mode */
2303 return hns3_check_mq_mode(dev);
2307 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2308 enum hns3_ring_type queue_type, uint16_t queue_id)
2310 struct hns3_cmd_desc desc;
2311 struct hns3_ctrl_vector_chain_cmd *req =
2312 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2313 enum hns3_cmd_status status;
2314 enum hns3_opcode_type op;
2315 uint16_t tqp_type_and_id = 0;
2319 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2320 hns3_cmd_setup_basic_desc(&desc, op, false);
2321 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2322 HNS3_TQP_INT_ID_L_S);
2323 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2324 HNS3_TQP_INT_ID_H_S);
2326 if (queue_type == HNS3_RING_TYPE_RX)
2327 gl = HNS3_RING_GL_RX;
2329 gl = HNS3_RING_GL_TX;
2333 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2335 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2336 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2338 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2339 req->int_cause_num = 1;
2340 status = hns3_cmd_send(hw, &desc, 1);
2342 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2343 en ? "Map" : "Unmap", queue_id, vector_id, status);
2351 hns3_init_ring_with_vector(struct hns3_hw *hw)
2358 * In hns3 network engine, vector 0 is always the misc interrupt of this
2359 * function, vector 1~N can be used respectively for the queues of the
2360 * function. Tx and Rx queues with the same number share the interrupt
2361 * vector. In the initialization clearing the all hardware mapping
2362 * relationship configurations between queues and interrupt vectors is
2363 * needed, so some error caused by the residual configurations, such as
2364 * the unexpected Tx interrupt, can be avoid.
2366 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2367 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2368 vec = vec - 1; /* the last interrupt is reserved */
2369 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2370 for (i = 0; i < hw->intr_tqps_num; i++) {
2372 * Set gap limiter/rate limiter/quanity limiter algorithm
2373 * configuration for interrupt coalesce of queue's interrupt.
2375 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2376 HNS3_TQP_INTR_GL_DEFAULT);
2377 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2378 HNS3_TQP_INTR_GL_DEFAULT);
2379 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2381 * QL(quantity limiter) is not used currently, just set 0 to
2384 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2386 ret = hns3_bind_ring_with_vector(hw, vec, false,
2387 HNS3_RING_TYPE_TX, i);
2389 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2390 "vector: %u, ret=%d", i, vec, ret);
2394 ret = hns3_bind_ring_with_vector(hw, vec, false,
2395 HNS3_RING_TYPE_RX, i);
2397 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2398 "vector: %u, ret=%d", i, vec, ret);
2407 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2409 struct hns3_adapter *hns = dev->data->dev_private;
2410 struct hns3_hw *hw = &hns->hw;
2411 uint32_t max_rx_pkt_len;
2415 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2419 * If jumbo frames are enabled, MTU needs to be refreshed
2420 * according to the maximum RX packet length.
2422 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2423 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2424 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2425 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2426 "and no more than %u when jumbo frame enabled.",
2427 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2428 (uint16_t)HNS3_MAX_FRAME_LEN);
2432 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2433 ret = hns3_dev_mtu_set(dev, mtu);
2436 dev->data->mtu = mtu;
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2444 struct hns3_adapter *hns = dev->data->dev_private;
2445 struct rte_eth_conf *conf = &dev->data->dev_conf;
2446 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447 struct hns3_hw *hw = &hns->hw;
2448 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450 struct rte_eth_rss_conf rss_conf;
2454 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2457 * Some versions of hardware network engine does not support
2458 * individually enable/disable/reset the Tx or Rx queue. These devices
2459 * must enable/disable/reset Tx and Rx queues at the same time. When the
2460 * numbers of Tx queues allocated by upper applications are not equal to
2461 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463 * work as usual. But these fake queues are imperceptible, and can not
2464 * be used by upper applications.
2466 if (!hns3_dev_indep_txrx_supported(hw)) {
2467 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2469 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2475 hw->adapter_state = HNS3_NIC_CONFIGURING;
2476 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2477 hns3_err(hw, "setting link speed/duplex not supported");
2482 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2483 ret = hns3_check_dcb_cfg(dev);
2488 /* When RSS is not configured, redirect the packet queue 0 */
2489 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2490 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2491 rss_conf = conf->rx_adv_conf.rss_conf;
2492 hw->rss_dis_flag = false;
2493 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2498 ret = hns3_refresh_mtu(dev, conf);
2502 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2506 ret = hns3_dev_configure_vlan(dev);
2510 /* config hardware GRO */
2511 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2512 ret = hns3_config_gro(hw, gro_en);
2516 hns->rx_simple_allowed = true;
2517 hns->rx_vec_allowed = true;
2518 hns->tx_simple_allowed = true;
2519 hns->tx_vec_allowed = true;
2521 hns3_init_rx_ptype_tble(dev);
2522 hw->adapter_state = HNS3_NIC_CONFIGURED;
2527 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2528 hw->adapter_state = HNS3_NIC_INITIALIZED;
2534 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2536 struct hns3_config_max_frm_size_cmd *req;
2537 struct hns3_cmd_desc desc;
2539 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2541 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2542 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2543 req->min_frm_size = RTE_ETHER_MIN_LEN;
2545 return hns3_cmd_send(hw, &desc, 1);
2549 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2551 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2552 uint16_t original_mps = hns->pf.mps;
2556 ret = hns3_set_mac_mtu(hw, mps);
2558 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2563 ret = hns3_buffer_alloc(hw);
2565 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2572 err = hns3_set_mac_mtu(hw, original_mps);
2574 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2577 hns->pf.mps = original_mps;
2583 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2585 struct hns3_adapter *hns = dev->data->dev_private;
2586 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2587 struct hns3_hw *hw = &hns->hw;
2588 bool is_jumbo_frame;
2591 if (dev->data->dev_started) {
2592 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2593 "before configuration", dev->data->port_id);
2597 rte_spinlock_lock(&hw->lock);
2598 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2599 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2602 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2603 * assign to "uint16_t" type variable.
2605 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2607 rte_spinlock_unlock(&hw->lock);
2608 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2609 dev->data->port_id, mtu, ret);
2614 dev->data->dev_conf.rxmode.offloads |=
2615 DEV_RX_OFFLOAD_JUMBO_FRAME;
2617 dev->data->dev_conf.rxmode.offloads &=
2618 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2619 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2620 rte_spinlock_unlock(&hw->lock);
2626 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2628 struct hns3_adapter *hns = eth_dev->data->dev_private;
2629 struct hns3_hw *hw = &hns->hw;
2630 uint16_t queue_num = hw->tqps_num;
2633 * In interrupt mode, 'max_rx_queues' is set based on the number of
2634 * MSI-X interrupt resources of the hardware.
2636 if (hw->data->dev_conf.intr_conf.rxq == 1)
2637 queue_num = hw->intr_tqps_num;
2639 info->max_rx_queues = queue_num;
2640 info->max_tx_queues = hw->tqps_num;
2641 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2642 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2643 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2644 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2645 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2646 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2647 DEV_RX_OFFLOAD_TCP_CKSUM |
2648 DEV_RX_OFFLOAD_UDP_CKSUM |
2649 DEV_RX_OFFLOAD_SCTP_CKSUM |
2650 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2651 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2652 DEV_RX_OFFLOAD_KEEP_CRC |
2653 DEV_RX_OFFLOAD_SCATTER |
2654 DEV_RX_OFFLOAD_VLAN_STRIP |
2655 DEV_RX_OFFLOAD_VLAN_FILTER |
2656 DEV_RX_OFFLOAD_JUMBO_FRAME |
2657 DEV_RX_OFFLOAD_RSS_HASH |
2658 DEV_RX_OFFLOAD_TCP_LRO);
2659 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2660 DEV_TX_OFFLOAD_IPV4_CKSUM |
2661 DEV_TX_OFFLOAD_TCP_CKSUM |
2662 DEV_TX_OFFLOAD_UDP_CKSUM |
2663 DEV_TX_OFFLOAD_SCTP_CKSUM |
2664 DEV_TX_OFFLOAD_MULTI_SEGS |
2665 DEV_TX_OFFLOAD_TCP_TSO |
2666 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2667 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2668 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2669 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2670 hns3_txvlan_cap_get(hw));
2672 if (hns3_dev_outer_udp_cksum_supported(hw))
2673 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2675 if (hns3_dev_indep_txrx_supported(hw))
2676 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2677 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2679 if (hns3_dev_ptp_supported(hw))
2680 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2682 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2683 .nb_max = HNS3_MAX_RING_DESC,
2684 .nb_min = HNS3_MIN_RING_DESC,
2685 .nb_align = HNS3_ALIGN_RING_DESC,
2688 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2689 .nb_max = HNS3_MAX_RING_DESC,
2690 .nb_min = HNS3_MIN_RING_DESC,
2691 .nb_align = HNS3_ALIGN_RING_DESC,
2692 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2693 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2696 info->default_rxconf = (struct rte_eth_rxconf) {
2697 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2699 * If there are no available Rx buffer descriptors, incoming
2700 * packets are always dropped by hardware based on hns3 network
2706 info->default_txconf = (struct rte_eth_txconf) {
2707 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2711 info->vmdq_queue_num = 0;
2713 info->reta_size = hw->rss_ind_tbl_size;
2714 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2715 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2717 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2718 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2719 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2720 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2721 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2722 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2728 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2731 struct hns3_adapter *hns = eth_dev->data->dev_private;
2732 struct hns3_hw *hw = &hns->hw;
2733 uint32_t version = hw->fw_version;
2736 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2737 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2738 HNS3_FW_VERSION_BYTE3_S),
2739 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2740 HNS3_FW_VERSION_BYTE2_S),
2741 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2742 HNS3_FW_VERSION_BYTE1_S),
2743 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2744 HNS3_FW_VERSION_BYTE0_S));
2745 ret += 1; /* add the size of '\0' */
2746 if (fw_size < (uint32_t)ret)
2753 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2755 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2757 (void)hns3_update_link_status(hw);
2759 return hns3_update_link_info(eth_dev);
2763 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2764 struct rte_eth_link *new_link)
2766 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2767 struct hns3_mac *mac = &hw->mac;
2769 switch (mac->link_speed) {
2770 case ETH_SPEED_NUM_10M:
2771 case ETH_SPEED_NUM_100M:
2772 case ETH_SPEED_NUM_1G:
2773 case ETH_SPEED_NUM_10G:
2774 case ETH_SPEED_NUM_25G:
2775 case ETH_SPEED_NUM_40G:
2776 case ETH_SPEED_NUM_50G:
2777 case ETH_SPEED_NUM_100G:
2778 case ETH_SPEED_NUM_200G:
2779 new_link->link_speed = mac->link_speed;
2782 if (mac->link_status)
2783 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2785 new_link->link_speed = ETH_SPEED_NUM_NONE;
2789 new_link->link_duplex = mac->link_duplex;
2790 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2791 new_link->link_autoneg =
2792 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2796 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2798 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2799 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2801 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2802 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2803 struct hns3_mac *mac = &hw->mac;
2804 struct rte_eth_link new_link;
2808 ret = hns3_update_port_link_info(eth_dev);
2810 mac->link_status = ETH_LINK_DOWN;
2811 hns3_err(hw, "failed to get port link info, ret = %d.",
2816 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2819 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2820 } while (retry_cnt--);
2822 memset(&new_link, 0, sizeof(new_link));
2823 hns3_setup_linkstatus(eth_dev, &new_link);
2825 return rte_eth_linkstatus_set(eth_dev, &new_link);
2829 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2831 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2832 struct hns3_pf *pf = &hns->pf;
2834 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2837 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2843 hns3_query_function_status(struct hns3_hw *hw)
2845 #define HNS3_QUERY_MAX_CNT 10
2846 #define HNS3_QUERY_SLEEP_MSCOEND 1
2847 struct hns3_func_status_cmd *req;
2848 struct hns3_cmd_desc desc;
2852 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2853 req = (struct hns3_func_status_cmd *)desc.data;
2856 ret = hns3_cmd_send(hw, &desc, 1);
2858 PMD_INIT_LOG(ERR, "query function status failed %d",
2863 /* Check pf reset is done */
2867 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2868 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2870 return hns3_parse_func_status(hw, req);
2874 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2876 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2877 struct hns3_pf *pf = &hns->pf;
2879 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2881 * The total_tqps_num obtained from firmware is maximum tqp
2882 * numbers of this port, which should be used for PF and VFs.
2883 * There is no need for pf to have so many tqp numbers in
2884 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2885 * coming from config file, is assigned to maximum queue number
2886 * for the PF of this port by user. So users can modify the
2887 * maximum queue number of PF according to their own application
2888 * scenarios, which is more flexible to use. In addition, many
2889 * memories can be saved due to allocating queue statistics
2890 * room according to the actual number of queues required. The
2891 * maximum queue number of PF for network engine with
2892 * revision_id greater than 0x30 is assigned by config file.
2894 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2895 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2896 "must be greater than 0.",
2897 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2901 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2902 hw->total_tqps_num);
2905 * Due to the limitation on the number of PF interrupts
2906 * available, the maximum queue number assigned to PF on
2907 * the network engine with revision_id 0x21 is 64.
2909 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2910 HNS3_MAX_TQP_NUM_HIP08_PF);
2917 hns3_query_pf_resource(struct hns3_hw *hw)
2919 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2920 struct hns3_pf *pf = &hns->pf;
2921 struct hns3_pf_res_cmd *req;
2922 struct hns3_cmd_desc desc;
2925 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2926 ret = hns3_cmd_send(hw, &desc, 1);
2928 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2932 req = (struct hns3_pf_res_cmd *)desc.data;
2933 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2934 rte_le_to_cpu_16(req->ext_tqp_num);
2935 ret = hns3_get_pf_max_tqp_num(hw);
2939 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2940 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2942 if (req->tx_buf_size)
2944 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2946 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2948 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2950 if (req->dv_buf_size)
2952 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2954 pf->dv_buf_size = HNS3_DEFAULT_DV;
2956 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2959 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2960 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2966 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2968 struct hns3_cfg_param_cmd *req;
2969 uint64_t mac_addr_tmp_high;
2970 uint8_t ext_rss_size_max;
2971 uint64_t mac_addr_tmp;
2974 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2976 /* get the configuration */
2977 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2978 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2979 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2980 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2981 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2982 HNS3_CFG_TQP_DESC_N_M,
2983 HNS3_CFG_TQP_DESC_N_S);
2985 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2986 HNS3_CFG_PHY_ADDR_M,
2987 HNS3_CFG_PHY_ADDR_S);
2988 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2989 HNS3_CFG_MEDIA_TP_M,
2990 HNS3_CFG_MEDIA_TP_S);
2991 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2992 HNS3_CFG_RX_BUF_LEN_M,
2993 HNS3_CFG_RX_BUF_LEN_S);
2994 /* get mac address */
2995 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2996 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2997 HNS3_CFG_MAC_ADDR_H_M,
2998 HNS3_CFG_MAC_ADDR_H_S);
3000 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3002 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3003 HNS3_CFG_DEFAULT_SPEED_M,
3004 HNS3_CFG_DEFAULT_SPEED_S);
3005 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3006 HNS3_CFG_RSS_SIZE_M,
3007 HNS3_CFG_RSS_SIZE_S);
3009 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3010 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3012 req = (struct hns3_cfg_param_cmd *)desc[1].data;
3013 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3015 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3016 HNS3_CFG_SPEED_ABILITY_M,
3017 HNS3_CFG_SPEED_ABILITY_S);
3018 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3019 HNS3_CFG_UMV_TBL_SPACE_M,
3020 HNS3_CFG_UMV_TBL_SPACE_S);
3021 if (!cfg->umv_space)
3022 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3024 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3025 HNS3_CFG_EXT_RSS_SIZE_M,
3026 HNS3_CFG_EXT_RSS_SIZE_S);
3029 * Field ext_rss_size_max obtained from firmware will be more flexible
3030 * for future changes and expansions, which is an exponent of 2, instead
3031 * of reading out directly. If this field is not zero, hns3 PF PMD
3032 * driver uses it as rss_size_max under one TC. Device, whose revision
3033 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3034 * maximum number of queues supported under a TC through this field.
3036 if (ext_rss_size_max)
3037 cfg->rss_size_max = 1U << ext_rss_size_max;
3040 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3041 * @hw: pointer to struct hns3_hw
3042 * @hcfg: the config structure to be getted
3045 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3047 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3048 struct hns3_cfg_param_cmd *req;
3053 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3055 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3056 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3058 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3059 i * HNS3_CFG_RD_LEN_BYTES);
3060 /* Len should be divided by 4 when send to hardware */
3061 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3062 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3063 req->offset = rte_cpu_to_le_32(offset);
3066 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3068 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3072 hns3_parse_cfg(hcfg, desc);
3078 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3080 switch (speed_cmd) {
3081 case HNS3_CFG_SPEED_10M:
3082 *speed = ETH_SPEED_NUM_10M;
3084 case HNS3_CFG_SPEED_100M:
3085 *speed = ETH_SPEED_NUM_100M;
3087 case HNS3_CFG_SPEED_1G:
3088 *speed = ETH_SPEED_NUM_1G;
3090 case HNS3_CFG_SPEED_10G:
3091 *speed = ETH_SPEED_NUM_10G;
3093 case HNS3_CFG_SPEED_25G:
3094 *speed = ETH_SPEED_NUM_25G;
3096 case HNS3_CFG_SPEED_40G:
3097 *speed = ETH_SPEED_NUM_40G;
3099 case HNS3_CFG_SPEED_50G:
3100 *speed = ETH_SPEED_NUM_50G;
3102 case HNS3_CFG_SPEED_100G:
3103 *speed = ETH_SPEED_NUM_100G;
3105 case HNS3_CFG_SPEED_200G:
3106 *speed = ETH_SPEED_NUM_200G;
3116 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3118 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3119 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3120 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3121 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3122 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3126 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3128 struct hns3_dev_specs_0_cmd *req0;
3130 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3132 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3133 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3134 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3135 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3136 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3140 hns3_check_dev_specifications(struct hns3_hw *hw)
3142 if (hw->rss_ind_tbl_size == 0 ||
3143 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3144 hns3_err(hw, "the size of hash lookup table configured (%u)"
3145 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3146 HNS3_RSS_IND_TBL_SIZE_MAX);
3154 hns3_query_dev_specifications(struct hns3_hw *hw)
3156 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3160 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3161 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3163 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3165 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3167 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3171 hns3_parse_dev_specifications(hw, desc);
3173 return hns3_check_dev_specifications(hw);
3177 hns3_get_capability(struct hns3_hw *hw)
3179 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3180 struct rte_pci_device *pci_dev;
3181 struct hns3_pf *pf = &hns->pf;
3182 struct rte_eth_dev *eth_dev;
3187 eth_dev = &rte_eth_devices[hw->data->port_id];
3188 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3189 device_id = pci_dev->id.device_id;
3191 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3192 device_id == HNS3_DEV_ID_50GE_RDMA ||
3193 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3194 device_id == HNS3_DEV_ID_200G_RDMA)
3195 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3197 /* Get PCI revision id */
3198 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3199 HNS3_PCI_REVISION_ID);
3200 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3201 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3205 hw->revision = revision;
3207 if (revision < PCI_REVISION_ID_HIP09_A) {
3208 hns3_set_default_dev_specifications(hw);
3209 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3210 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3211 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3212 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3213 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3214 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3215 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3216 hw->rss_info.ipv6_sctp_offload_supported = false;
3217 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3221 ret = hns3_query_dev_specifications(hw);
3224 "failed to query dev specifications, ret = %d",
3229 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3230 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3231 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3232 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3233 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3234 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3235 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3236 hw->rss_info.ipv6_sctp_offload_supported = true;
3237 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3243 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3247 switch (media_type) {
3248 case HNS3_MEDIA_TYPE_COPPER:
3249 if (!hns3_dev_copper_supported(hw)) {
3251 "Media type is copper, not supported.");
3257 case HNS3_MEDIA_TYPE_FIBER:
3260 case HNS3_MEDIA_TYPE_BACKPLANE:
3261 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3265 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3274 hns3_get_board_configuration(struct hns3_hw *hw)
3276 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3277 struct hns3_pf *pf = &hns->pf;
3278 struct hns3_cfg cfg;
3281 ret = hns3_get_board_cfg(hw, &cfg);
3283 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3287 ret = hns3_check_media_type(hw, cfg.media_type);
3291 hw->mac.media_type = cfg.media_type;
3292 hw->rss_size_max = cfg.rss_size_max;
3293 hw->rss_dis_flag = false;
3294 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3295 hw->mac.phy_addr = cfg.phy_addr;
3296 hw->mac.default_addr_setted = false;
3297 hw->num_tx_desc = cfg.tqp_desc_num;
3298 hw->num_rx_desc = cfg.tqp_desc_num;
3299 hw->dcb_info.num_pg = 1;
3300 hw->dcb_info.hw_pfc_map = 0;
3302 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3304 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3305 cfg.default_speed, ret);
3309 pf->tc_max = cfg.tc_num;
3310 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3311 PMD_INIT_LOG(WARNING,
3312 "Get TC num(%u) from flash, set TC num to 1",
3317 /* Dev does not support DCB */
3318 if (!hns3_dev_dcb_supported(hw)) {
3322 pf->pfc_max = pf->tc_max;
3324 hw->dcb_info.num_tc = 1;
3325 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3326 hw->tqps_num / hw->dcb_info.num_tc);
3327 hns3_set_bit(hw->hw_tc_map, 0, 1);
3328 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3330 pf->wanted_umv_size = cfg.umv_space;
3336 hns3_get_configuration(struct hns3_hw *hw)
3340 ret = hns3_query_function_status(hw);
3342 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3346 /* Get device capability */
3347 ret = hns3_get_capability(hw);
3349 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3353 /* Get pf resource */
3354 ret = hns3_query_pf_resource(hw);
3356 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3360 ret = hns3_get_board_configuration(hw);
3362 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3366 ret = hns3_query_dev_fec_info(hw);
3369 "failed to query FEC information, ret = %d", ret);
3375 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3376 uint16_t tqp_vid, bool is_pf)
3378 struct hns3_tqp_map_cmd *req;
3379 struct hns3_cmd_desc desc;
3382 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3384 req = (struct hns3_tqp_map_cmd *)desc.data;
3385 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3386 req->tqp_vf = func_id;
3387 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3389 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3390 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3392 ret = hns3_cmd_send(hw, &desc, 1);
3394 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3400 hns3_map_tqp(struct hns3_hw *hw)
3406 * In current version, VF is not supported when PF is driven by DPDK
3407 * driver, so we assign total tqps_num tqps allocated to this port
3410 for (i = 0; i < hw->total_tqps_num; i++) {
3411 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3420 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3422 struct hns3_config_mac_speed_dup_cmd *req;
3423 struct hns3_cmd_desc desc;
3426 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3428 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3430 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3433 case ETH_SPEED_NUM_10M:
3434 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3435 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3437 case ETH_SPEED_NUM_100M:
3438 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3439 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3441 case ETH_SPEED_NUM_1G:
3442 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3443 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3445 case ETH_SPEED_NUM_10G:
3446 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3447 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3449 case ETH_SPEED_NUM_25G:
3450 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3451 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3453 case ETH_SPEED_NUM_40G:
3454 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3455 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3457 case ETH_SPEED_NUM_50G:
3458 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3459 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3461 case ETH_SPEED_NUM_100G:
3462 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3463 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3465 case ETH_SPEED_NUM_200G:
3466 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3467 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3470 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3474 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3476 ret = hns3_cmd_send(hw, &desc, 1);
3478 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3484 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3486 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3487 struct hns3_pf *pf = &hns->pf;
3488 struct hns3_priv_buf *priv;
3489 uint32_t i, total_size;
3491 total_size = pf->pkt_buf_size;
3493 /* alloc tx buffer for all enabled tc */
3494 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3495 priv = &buf_alloc->priv_buf[i];
3497 if (hw->hw_tc_map & BIT(i)) {
3498 if (total_size < pf->tx_buf_size)
3501 priv->tx_buf_size = pf->tx_buf_size;
3503 priv->tx_buf_size = 0;
3505 total_size -= priv->tx_buf_size;
3512 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3514 /* TX buffer size is unit by 128 byte */
3515 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3516 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3517 struct hns3_tx_buff_alloc_cmd *req;
3518 struct hns3_cmd_desc desc;
3523 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3525 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3526 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3527 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3529 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3530 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3531 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3534 ret = hns3_cmd_send(hw, &desc, 1);
3536 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3542 hns3_get_tc_num(struct hns3_hw *hw)
3547 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3548 if (hw->hw_tc_map & BIT(i))
3554 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3556 struct hns3_priv_buf *priv;
3557 uint32_t rx_priv = 0;
3560 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3561 priv = &buf_alloc->priv_buf[i];
3563 rx_priv += priv->buf_size;
3569 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3571 uint32_t total_tx_size = 0;
3574 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3575 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3577 return total_tx_size;
3580 /* Get the number of pfc enabled TCs, which have private buffer */
3582 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3584 struct hns3_priv_buf *priv;
3588 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3589 priv = &buf_alloc->priv_buf[i];
3590 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3597 /* Get the number of pfc disabled TCs, which have private buffer */
3599 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3600 struct hns3_pkt_buf_alloc *buf_alloc)
3602 struct hns3_priv_buf *priv;
3606 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3607 priv = &buf_alloc->priv_buf[i];
3608 if (hw->hw_tc_map & BIT(i) &&
3609 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3617 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3620 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3621 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3622 struct hns3_pf *pf = &hns->pf;
3623 uint32_t shared_buf, aligned_mps;
3628 tc_num = hns3_get_tc_num(hw);
3629 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3631 if (hns3_dev_dcb_supported(hw))
3632 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3635 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3638 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3639 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3640 HNS3_BUF_SIZE_UNIT);
3642 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3643 if (rx_all < rx_priv + shared_std)
3646 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3647 buf_alloc->s_buf.buf_size = shared_buf;
3648 if (hns3_dev_dcb_supported(hw)) {
3649 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3650 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3651 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3652 HNS3_BUF_SIZE_UNIT);
3654 buf_alloc->s_buf.self.high =
3655 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3656 buf_alloc->s_buf.self.low = aligned_mps;
3659 if (hns3_dev_dcb_supported(hw)) {
3660 hi_thrd = shared_buf - pf->dv_buf_size;
3662 if (tc_num <= NEED_RESERVE_TC_NUM)
3663 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3667 hi_thrd = hi_thrd / tc_num;
3669 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3670 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3671 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3673 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3674 lo_thrd = aligned_mps;
3677 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3678 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3679 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3686 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3687 struct hns3_pkt_buf_alloc *buf_alloc)
3689 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3690 struct hns3_pf *pf = &hns->pf;
3691 struct hns3_priv_buf *priv;
3692 uint32_t aligned_mps;
3696 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3697 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3699 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3700 priv = &buf_alloc->priv_buf[i];
3707 if (!(hw->hw_tc_map & BIT(i)))
3711 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3712 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3713 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3714 HNS3_BUF_SIZE_UNIT);
3717 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3721 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3724 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3728 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3729 struct hns3_pkt_buf_alloc *buf_alloc)
3731 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3732 struct hns3_pf *pf = &hns->pf;
3733 struct hns3_priv_buf *priv;
3734 int no_pfc_priv_num;
3739 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3740 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3742 /* let the last to be cleared first */
3743 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3744 priv = &buf_alloc->priv_buf[i];
3745 mask = BIT((uint8_t)i);
3747 if (hw->hw_tc_map & mask &&
3748 !(hw->dcb_info.hw_pfc_map & mask)) {
3749 /* Clear the no pfc TC private buffer */
3757 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3758 no_pfc_priv_num == 0)
3762 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3766 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3767 struct hns3_pkt_buf_alloc *buf_alloc)
3769 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3770 struct hns3_pf *pf = &hns->pf;
3771 struct hns3_priv_buf *priv;
3777 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3778 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3780 /* let the last to be cleared first */
3781 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3782 priv = &buf_alloc->priv_buf[i];
3783 mask = BIT((uint8_t)i);
3784 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3785 /* Reduce the number of pfc TC with private buffer */
3792 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3797 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3801 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3802 struct hns3_pkt_buf_alloc *buf_alloc)
3804 #define COMPENSATE_BUFFER 0x3C00
3805 #define COMPENSATE_HALF_MPS_NUM 5
3806 #define PRIV_WL_GAP 0x1800
3807 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3808 struct hns3_pf *pf = &hns->pf;
3809 uint32_t tc_num = hns3_get_tc_num(hw);
3810 uint32_t half_mps = pf->mps >> 1;
3811 struct hns3_priv_buf *priv;
3812 uint32_t min_rx_priv;
3816 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3818 rx_priv = rx_priv / tc_num;
3820 if (tc_num <= NEED_RESERVE_TC_NUM)
3821 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3824 * Minimum value of private buffer in rx direction (min_rx_priv) is
3825 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3826 * buffer if rx_priv is greater than min_rx_priv.
3828 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3829 COMPENSATE_HALF_MPS_NUM * half_mps;
3830 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3831 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3833 if (rx_priv < min_rx_priv)
3836 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3837 priv = &buf_alloc->priv_buf[i];
3843 if (!(hw->hw_tc_map & BIT(i)))
3847 priv->buf_size = rx_priv;
3848 priv->wl.high = rx_priv - pf->dv_buf_size;
3849 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3852 buf_alloc->s_buf.buf_size = 0;
3858 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3859 * @hw: pointer to struct hns3_hw
3860 * @buf_alloc: pointer to buffer calculation data
3861 * @return: 0: calculate sucessful, negative: fail
3864 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3866 /* When DCB is not supported, rx private buffer is not allocated. */
3867 if (!hns3_dev_dcb_supported(hw)) {
3868 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3869 struct hns3_pf *pf = &hns->pf;
3870 uint32_t rx_all = pf->pkt_buf_size;
3872 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3873 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3880 * Try to allocate privated packet buffer for all TCs without share
3883 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3887 * Try to allocate privated packet buffer for all TCs with share
3890 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3894 * For different application scenes, the enabled port number, TC number
3895 * and no_drop TC number are different. In order to obtain the better
3896 * performance, software could allocate the buffer size and configure
3897 * the waterline by tring to decrease the private buffer size according
3898 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3901 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3904 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3907 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3914 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3916 struct hns3_rx_priv_buff_cmd *req;
3917 struct hns3_cmd_desc desc;
3922 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3923 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3925 /* Alloc private buffer TCs */
3926 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3927 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3930 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3931 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3934 buf_size = buf_alloc->s_buf.buf_size;
3935 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3936 (1 << HNS3_TC0_PRI_BUF_EN_B));
3938 ret = hns3_cmd_send(hw, &desc, 1);
3940 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3946 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3948 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3949 struct hns3_rx_priv_wl_buf *req;
3950 struct hns3_priv_buf *priv;
3951 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3955 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3956 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3958 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3960 /* The first descriptor set the NEXT bit to 1 */
3962 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3964 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3966 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3967 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3969 priv = &buf_alloc->priv_buf[idx];
3970 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3972 req->tc_wl[j].high |=
3973 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3974 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3976 req->tc_wl[j].low |=
3977 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3981 /* Send 2 descriptor at one time */
3982 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3984 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3990 hns3_common_thrd_config(struct hns3_hw *hw,
3991 struct hns3_pkt_buf_alloc *buf_alloc)
3993 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3994 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3995 struct hns3_rx_com_thrd *req;
3996 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3997 struct hns3_tc_thrd *tc;
4002 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4003 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4005 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4007 /* The first descriptor set the NEXT bit to 1 */
4009 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4011 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4013 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4014 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4015 tc = &s_buf->tc_thrd[tc_idx];
4017 req->com_thrd[j].high =
4018 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4019 req->com_thrd[j].high |=
4020 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4021 req->com_thrd[j].low =
4022 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4023 req->com_thrd[j].low |=
4024 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4028 /* Send 2 descriptors at one time */
4029 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4031 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4037 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4039 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4040 struct hns3_rx_com_wl *req;
4041 struct hns3_cmd_desc desc;
4044 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4046 req = (struct hns3_rx_com_wl *)desc.data;
4047 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4048 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4050 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4051 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4053 ret = hns3_cmd_send(hw, &desc, 1);
4055 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4061 hns3_buffer_alloc(struct hns3_hw *hw)
4063 struct hns3_pkt_buf_alloc pkt_buf;
4066 memset(&pkt_buf, 0, sizeof(pkt_buf));
4067 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4070 "could not calc tx buffer size for all TCs %d",
4075 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4077 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4081 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4084 "could not calc rx priv buffer size for all TCs %d",
4089 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4091 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4095 if (hns3_dev_dcb_supported(hw)) {
4096 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4099 "could not configure rx private waterline %d",
4104 ret = hns3_common_thrd_config(hw, &pkt_buf);
4107 "could not configure common threshold %d",
4113 ret = hns3_common_wl_config(hw, &pkt_buf);
4115 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4122 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4124 struct hns3_firmware_compat_cmd *req;
4125 struct hns3_cmd_desc desc;
4126 uint32_t compat = 0;
4128 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4129 req = (struct hns3_firmware_compat_cmd *)desc.data;
4132 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4133 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4134 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4135 hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4138 req->compat = rte_cpu_to_le_32(compat);
4140 return hns3_cmd_send(hw, &desc, 1);
4144 hns3_mac_init(struct hns3_hw *hw)
4146 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4147 struct hns3_mac *mac = &hw->mac;
4148 struct hns3_pf *pf = &hns->pf;
4151 pf->support_sfp_query = true;
4152 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4153 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4155 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4159 mac->link_status = ETH_LINK_DOWN;
4161 return hns3_config_mtu(hw, pf->mps);
4165 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4167 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4168 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4169 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4170 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4175 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4180 switch (resp_code) {
4181 case HNS3_ETHERTYPE_SUCCESS_ADD:
4182 case HNS3_ETHERTYPE_ALREADY_ADD:
4185 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4187 "add mac ethertype failed for manager table overflow.");
4188 return_status = -EIO;
4190 case HNS3_ETHERTYPE_KEY_CONFLICT:
4191 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4192 return_status = -EIO;
4196 "add mac ethertype failed for undefined, code=%u.",
4198 return_status = -EIO;
4202 return return_status;
4206 hns3_add_mgr_tbl(struct hns3_hw *hw,
4207 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4209 struct hns3_cmd_desc desc;
4214 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4215 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4217 ret = hns3_cmd_send(hw, &desc, 1);
4220 "add mac ethertype failed for cmd_send, ret =%d.",
4225 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4226 retval = rte_le_to_cpu_16(desc.retval);
4228 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4232 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4233 int *table_item_num)
4235 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4238 * In current version, we add one item in management table as below:
4239 * 0x0180C200000E -- LLDP MC address
4242 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4243 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4244 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4245 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4246 tbl->i_port_bitmap = 0x1;
4247 *table_item_num = 1;
4251 hns3_init_mgr_tbl(struct hns3_hw *hw)
4253 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4254 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4259 memset(mgr_table, 0, sizeof(mgr_table));
4260 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4261 for (i = 0; i < table_item_num; i++) {
4262 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4264 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4274 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4275 bool en_mc, bool en_bc, int vport_id)
4280 memset(param, 0, sizeof(struct hns3_promisc_param));
4282 param->enable = HNS3_PROMISC_EN_UC;
4284 param->enable |= HNS3_PROMISC_EN_MC;
4286 param->enable |= HNS3_PROMISC_EN_BC;
4287 param->vf_id = vport_id;
4291 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4293 struct hns3_promisc_cfg_cmd *req;
4294 struct hns3_cmd_desc desc;
4297 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4299 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4300 req->vf_id = param->vf_id;
4301 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4302 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4304 ret = hns3_cmd_send(hw, &desc, 1);
4306 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4312 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4314 struct hns3_promisc_param param;
4315 bool en_bc_pmc = true;
4319 * In current version VF is not supported when PF is driven by DPDK
4320 * driver, just need to configure parameters for PF vport.
4322 vf_id = HNS3_PF_FUNC_ID;
4324 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4325 return hns3_cmd_set_promisc_mode(hw, ¶m);
4329 hns3_promisc_init(struct hns3_hw *hw)
4331 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4332 struct hns3_pf *pf = &hns->pf;
4333 struct hns3_promisc_param param;
4337 ret = hns3_set_promisc_mode(hw, false, false);
4339 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4344 * In current version VFs are not supported when PF is driven by DPDK
4345 * driver. After PF has been taken over by DPDK, the original VF will
4346 * be invalid. So, there is a possibility of entry residues. It should
4347 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4350 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4351 hns3_promisc_param_init(¶m, false, false, false, func_id);
4352 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4354 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4355 " ret = %d", func_id, ret);
4364 hns3_promisc_uninit(struct hns3_hw *hw)
4366 struct hns3_promisc_param param;
4370 func_id = HNS3_PF_FUNC_ID;
4373 * In current version VFs are not supported when PF is driven by
4374 * DPDK driver, and VFs' promisc mode status has been cleared during
4375 * init and their status will not change. So just clear PF's promisc
4376 * mode status during uninit.
4378 hns3_promisc_param_init(¶m, false, false, false, func_id);
4379 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4381 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4382 " uninit, ret = %d", ret);
4386 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4388 bool allmulti = dev->data->all_multicast ? true : false;
4389 struct hns3_adapter *hns = dev->data->dev_private;
4390 struct hns3_hw *hw = &hns->hw;
4395 rte_spinlock_lock(&hw->lock);
4396 ret = hns3_set_promisc_mode(hw, true, true);
4398 rte_spinlock_unlock(&hw->lock);
4399 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4405 * When promiscuous mode was enabled, disable the vlan filter to let
4406 * all packets coming in in the receiving direction.
4408 offloads = dev->data->dev_conf.rxmode.offloads;
4409 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4410 ret = hns3_enable_vlan_filter(hns, false);
4412 hns3_err(hw, "failed to enable promiscuous mode due to "
4413 "failure to disable vlan filter, ret = %d",
4415 err = hns3_set_promisc_mode(hw, false, allmulti);
4417 hns3_err(hw, "failed to restore promiscuous "
4418 "status after disable vlan filter "
4419 "failed during enabling promiscuous "
4420 "mode, ret = %d", ret);
4424 rte_spinlock_unlock(&hw->lock);
4430 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4432 bool allmulti = dev->data->all_multicast ? true : false;
4433 struct hns3_adapter *hns = dev->data->dev_private;
4434 struct hns3_hw *hw = &hns->hw;
4439 /* If now in all_multicast mode, must remain in all_multicast mode. */
4440 rte_spinlock_lock(&hw->lock);
4441 ret = hns3_set_promisc_mode(hw, false, allmulti);
4443 rte_spinlock_unlock(&hw->lock);
4444 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4448 /* when promiscuous mode was disabled, restore the vlan filter status */
4449 offloads = dev->data->dev_conf.rxmode.offloads;
4450 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4451 ret = hns3_enable_vlan_filter(hns, true);
4453 hns3_err(hw, "failed to disable promiscuous mode due to"
4454 " failure to restore vlan filter, ret = %d",
4456 err = hns3_set_promisc_mode(hw, true, true);
4458 hns3_err(hw, "failed to restore promiscuous "
4459 "status after enabling vlan filter "
4460 "failed during disabling promiscuous "
4461 "mode, ret = %d", ret);
4464 rte_spinlock_unlock(&hw->lock);
4470 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4472 struct hns3_adapter *hns = dev->data->dev_private;
4473 struct hns3_hw *hw = &hns->hw;
4476 if (dev->data->promiscuous)
4479 rte_spinlock_lock(&hw->lock);
4480 ret = hns3_set_promisc_mode(hw, false, true);
4481 rte_spinlock_unlock(&hw->lock);
4483 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4490 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4492 struct hns3_adapter *hns = dev->data->dev_private;
4493 struct hns3_hw *hw = &hns->hw;
4496 /* If now in promiscuous mode, must remain in all_multicast mode. */
4497 if (dev->data->promiscuous)
4500 rte_spinlock_lock(&hw->lock);
4501 ret = hns3_set_promisc_mode(hw, false, false);
4502 rte_spinlock_unlock(&hw->lock);
4504 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4511 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4513 struct hns3_hw *hw = &hns->hw;
4514 bool allmulti = hw->data->all_multicast ? true : false;
4517 if (hw->data->promiscuous) {
4518 ret = hns3_set_promisc_mode(hw, true, true);
4520 hns3_err(hw, "failed to restore promiscuous mode, "
4525 ret = hns3_set_promisc_mode(hw, false, allmulti);
4527 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4533 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4535 struct hns3_sfp_speed_cmd *resp;
4536 struct hns3_cmd_desc desc;
4539 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4540 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4541 ret = hns3_cmd_send(hw, &desc, 1);
4542 if (ret == -EOPNOTSUPP) {
4543 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4546 hns3_err(hw, "get sfp speed failed %d", ret);
4550 *speed = resp->sfp_speed;
4556 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4558 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4559 duplex = ETH_LINK_FULL_DUPLEX;
4565 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4567 struct hns3_mac *mac = &hw->mac;
4570 duplex = hns3_check_speed_dup(duplex, speed);
4571 if (mac->link_speed == speed && mac->link_duplex == duplex)
4574 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4578 ret = hns3_port_shaper_update(hw, speed);
4582 mac->link_speed = speed;
4583 mac->link_duplex = duplex;
4589 hns3_update_fiber_link_info(struct hns3_hw *hw)
4591 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4595 /* If IMP do not support get SFP/qSFP speed, return directly */
4596 if (!pf->support_sfp_query)
4599 ret = hns3_get_sfp_speed(hw, &speed);
4600 if (ret == -EOPNOTSUPP) {
4601 pf->support_sfp_query = false;
4606 if (speed == ETH_SPEED_NUM_NONE)
4607 return 0; /* do nothing if no SFP */
4609 /* Config full duplex for SFP */
4610 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4614 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4616 struct hns3_phy_params_bd0_cmd *req;
4618 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4619 mac->link_speed = rte_le_to_cpu_32(req->speed);
4620 mac->link_duplex = hns3_get_bit(req->duplex,
4621 HNS3_PHY_DUPLEX_CFG_B);
4622 mac->link_autoneg = hns3_get_bit(req->autoneg,
4623 HNS3_PHY_AUTONEG_CFG_B);
4624 mac->supported_capa = rte_le_to_cpu_32(req->supported);
4625 mac->advertising = rte_le_to_cpu_32(req->advertising);
4626 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4627 mac->support_autoneg = !!(mac->supported_capa &
4628 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4632 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4634 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4638 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4639 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4641 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4643 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4645 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4647 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4651 hns3_parse_copper_phy_params(desc, mac);
4657 hns3_update_copper_link_info(struct hns3_hw *hw)
4659 struct hns3_mac *mac = &hw->mac;
4660 struct hns3_mac mac_info;
4663 memset(&mac_info, 0, sizeof(struct hns3_mac));
4664 ret = hns3_get_copper_phy_params(hw, &mac_info);
4668 if (mac_info.link_speed != mac->link_speed) {
4669 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4674 mac->link_speed = mac_info.link_speed;
4675 mac->link_duplex = mac_info.link_duplex;
4676 mac->link_autoneg = mac_info.link_autoneg;
4677 mac->supported_capa = mac_info.supported_capa;
4678 mac->advertising = mac_info.advertising;
4679 mac->lp_advertising = mac_info.lp_advertising;
4680 mac->support_autoneg = mac_info.support_autoneg;
4686 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4688 struct hns3_adapter *hns = eth_dev->data->dev_private;
4689 struct hns3_hw *hw = &hns->hw;
4692 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4693 ret = hns3_update_copper_link_info(hw);
4694 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4695 ret = hns3_update_fiber_link_info(hw);
4701 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4703 struct hns3_config_mac_mode_cmd *req;
4704 struct hns3_cmd_desc desc;
4705 uint32_t loop_en = 0;
4709 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4711 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4714 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4715 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4716 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4717 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4718 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4719 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4720 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4721 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4722 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4723 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4726 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4727 * when receiving frames. Otherwise, CRC will be stripped.
4729 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4730 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4732 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4733 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4734 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4735 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4736 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4738 ret = hns3_cmd_send(hw, &desc, 1);
4740 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4746 hns3_get_mac_link_status(struct hns3_hw *hw)
4748 struct hns3_link_status_cmd *req;
4749 struct hns3_cmd_desc desc;
4753 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4754 ret = hns3_cmd_send(hw, &desc, 1);
4756 hns3_err(hw, "get link status cmd failed %d", ret);
4757 return ETH_LINK_DOWN;
4760 req = (struct hns3_link_status_cmd *)desc.data;
4761 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4763 return !!link_status;
4767 hns3_update_link_status(struct hns3_hw *hw)
4771 state = hns3_get_mac_link_status(hw);
4772 if (state != hw->mac.link_status) {
4773 hw->mac.link_status = state;
4774 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4775 hns3_config_mac_tnl_int(hw,
4776 state == ETH_LINK_UP ? true : false);
4784 * Current, the PF driver get link status by two ways:
4785 * 1) Periodic polling in the intr thread context, driver call
4786 * hns3_update_link_status to update link status.
4787 * 2) Firmware report async interrupt, driver process the event in the intr
4788 * thread context, and call hns3_update_link_status to update link status.
4790 * If detect link status changed, driver need report LSE. One method is add the
4791 * report LSE logic in hns3_update_link_status.
4793 * But the PF driver ops(link_update) also call hns3_update_link_status to
4794 * update link status.
4795 * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4796 * bonding application.
4798 * So add the one new API which used only in intr thread context.
4801 hns3_update_link_status_and_event(struct hns3_hw *hw)
4803 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4804 bool changed = hns3_update_link_status(hw);
4806 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4810 hns3_service_handler(void *param)
4812 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4813 struct hns3_adapter *hns = eth_dev->data->dev_private;
4814 struct hns3_hw *hw = &hns->hw;
4816 if (!hns3_is_reset_pending(hns)) {
4817 hns3_update_link_status_and_event(hw);
4818 hns3_update_link_info(eth_dev);
4820 hns3_warn(hw, "Cancel the query when reset is pending");
4823 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4827 hns3_init_hardware(struct hns3_adapter *hns)
4829 struct hns3_hw *hw = &hns->hw;
4832 ret = hns3_map_tqp(hw);
4834 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4838 ret = hns3_init_umv_space(hw);
4840 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4844 ret = hns3_mac_init(hw);
4846 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4850 ret = hns3_init_mgr_tbl(hw);
4852 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4856 ret = hns3_promisc_init(hw);
4858 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4863 ret = hns3_init_vlan_config(hns);
4865 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4869 ret = hns3_dcb_init(hw);
4871 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4875 ret = hns3_init_fd_config(hns);
4877 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4881 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4883 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4887 ret = hns3_config_gro(hw, false);
4889 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4894 * In the initialization clearing the all hardware mapping relationship
4895 * configurations between queues and interrupt vectors is needed, so
4896 * some error caused by the residual configurations, such as the
4897 * unexpected interrupt, can be avoid.
4899 ret = hns3_init_ring_with_vector(hw);
4901 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4906 * Requiring firmware to enable some features, driver can
4907 * still work without it.
4909 ret = hns3_firmware_compat_config(hw, true);
4911 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4912 "supported, ret = %d.", ret);
4917 hns3_uninit_umv_space(hw);
4922 hns3_clear_hw(struct hns3_hw *hw)
4924 struct hns3_cmd_desc desc;
4927 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4929 ret = hns3_cmd_send(hw, &desc, 1);
4930 if (ret && ret != -EOPNOTSUPP)
4937 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4942 * The new firmware support report more hardware error types by
4943 * msix mode. These errors are defined as RAS errors in hardware
4944 * and belong to a different type from the MSI-x errors processed
4945 * by the network driver.
4947 * Network driver should open the new error report on initialition
4949 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4950 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4951 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4955 hns3_init_pf(struct rte_eth_dev *eth_dev)
4957 struct rte_device *dev = eth_dev->device;
4958 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4959 struct hns3_adapter *hns = eth_dev->data->dev_private;
4960 struct hns3_hw *hw = &hns->hw;
4963 PMD_INIT_FUNC_TRACE();
4965 /* Get hardware io base address from pcie BAR2 IO space */
4966 hw->io_base = pci_dev->mem_resource[2].addr;
4968 /* Firmware command queue initialize */
4969 ret = hns3_cmd_init_queue(hw);
4971 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4972 goto err_cmd_init_queue;
4975 hns3_clear_all_event_cause(hw);
4977 /* Firmware command initialize */
4978 ret = hns3_cmd_init(hw);
4980 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4985 * To ensure that the hardware environment is clean during
4986 * initialization, the driver actively clear the hardware environment
4987 * during initialization, including PF and corresponding VFs' vlan, mac,
4988 * flow table configurations, etc.
4990 ret = hns3_clear_hw(hw);
4992 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4996 /* Hardware statistics of imissed registers cleared. */
4997 ret = hns3_update_imissed_stats(hw, true);
4999 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5003 hns3_config_all_msix_error(hw, true);
5005 ret = rte_intr_callback_register(&pci_dev->intr_handle,
5006 hns3_interrupt_handler,
5009 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5010 goto err_intr_callback_register;
5013 ret = hns3_ptp_init(hw);
5015 goto err_get_config;
5017 /* Enable interrupt */
5018 rte_intr_enable(&pci_dev->intr_handle);
5019 hns3_pf_enable_irq0(hw);
5021 /* Get configuration */
5022 ret = hns3_get_configuration(hw);
5024 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5025 goto err_get_config;
5028 ret = hns3_tqp_stats_init(hw);
5030 goto err_get_config;
5032 ret = hns3_init_hardware(hns);
5034 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5038 /* Initialize flow director filter list & hash */
5039 ret = hns3_fdir_filter_init(hns);
5041 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5045 hns3_rss_set_default_args(hw);
5047 ret = hns3_enable_hw_error_intr(hns, true);
5049 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5051 goto err_enable_intr;
5054 hns3_tm_conf_init(eth_dev);
5059 hns3_fdir_filter_uninit(hns);
5061 (void)hns3_firmware_compat_config(hw, false);
5062 hns3_uninit_umv_space(hw);
5064 hns3_tqp_stats_uninit(hw);
5066 hns3_pf_disable_irq0(hw);
5067 rte_intr_disable(&pci_dev->intr_handle);
5068 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5070 err_intr_callback_register:
5072 hns3_cmd_uninit(hw);
5073 hns3_cmd_destroy_queue(hw);
5081 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5083 struct hns3_adapter *hns = eth_dev->data->dev_private;
5084 struct rte_device *dev = eth_dev->device;
5085 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5086 struct hns3_hw *hw = &hns->hw;
5088 PMD_INIT_FUNC_TRACE();
5090 hns3_tm_conf_uninit(eth_dev);
5091 hns3_enable_hw_error_intr(hns, false);
5092 hns3_rss_uninit(hns);
5093 (void)hns3_config_gro(hw, false);
5094 hns3_promisc_uninit(hw);
5095 hns3_fdir_filter_uninit(hns);
5096 (void)hns3_firmware_compat_config(hw, false);
5097 hns3_uninit_umv_space(hw);
5098 hns3_tqp_stats_uninit(hw);
5099 hns3_config_mac_tnl_int(hw, false);
5100 hns3_pf_disable_irq0(hw);
5101 rte_intr_disable(&pci_dev->intr_handle);
5102 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5104 hns3_config_all_msix_error(hw, false);
5105 hns3_cmd_uninit(hw);
5106 hns3_cmd_destroy_queue(hw);
5111 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5113 struct hns3_hw *hw = &hns->hw;
5116 ret = hns3_dcb_cfg_update(hns);
5121 * The hns3_dcb_cfg_update may configure TM module, so
5122 * hns3_tm_conf_update must called later.
5124 ret = hns3_tm_conf_update(hw);
5126 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5130 hns3_enable_rxd_adv_layout(hw);
5132 ret = hns3_init_queues(hns, reset_queue);
5134 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5138 ret = hns3_cfg_mac_mode(hw, true);
5140 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5141 goto err_config_mac_mode;
5145 err_config_mac_mode:
5146 hns3_dev_release_mbufs(hns);
5148 * Here is exception handling, hns3_reset_all_tqps will have the
5149 * corresponding error message if it is handled incorrectly, so it is
5150 * not necessary to check hns3_reset_all_tqps return value, here keep
5151 * ret as the error code causing the exception.
5153 (void)hns3_reset_all_tqps(hns);
5158 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5160 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5161 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5162 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5163 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5164 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5165 uint32_t intr_vector;
5170 * hns3 needs a separate interrupt to be used as event interrupt which
5171 * could not be shared with task queue pair, so KERNEL drivers need
5172 * support multiple interrupt vectors.
5174 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5175 !rte_intr_cap_multiple(intr_handle))
5178 rte_intr_disable(intr_handle);
5179 intr_vector = hw->used_rx_queues;
5180 /* creates event fd for each intr vector when MSIX is used */
5181 if (rte_intr_efd_enable(intr_handle, intr_vector))
5184 if (intr_handle->intr_vec == NULL) {
5185 intr_handle->intr_vec =
5186 rte_zmalloc("intr_vec",
5187 hw->used_rx_queues * sizeof(int), 0);
5188 if (intr_handle->intr_vec == NULL) {
5189 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5190 hw->used_rx_queues);
5192 goto alloc_intr_vec_error;
5196 if (rte_intr_allow_others(intr_handle)) {
5197 vec = RTE_INTR_VEC_RXTX_OFFSET;
5198 base = RTE_INTR_VEC_RXTX_OFFSET;
5201 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5202 ret = hns3_bind_ring_with_vector(hw, vec, true,
5203 HNS3_RING_TYPE_RX, q_id);
5205 goto bind_vector_error;
5206 intr_handle->intr_vec[q_id] = vec;
5208 * If there are not enough efds (e.g. not enough interrupt),
5209 * remaining queues will be bond to the last interrupt.
5211 if (vec < base + intr_handle->nb_efd - 1)
5214 rte_intr_enable(intr_handle);
5218 rte_free(intr_handle->intr_vec);
5219 intr_handle->intr_vec = NULL;
5220 alloc_intr_vec_error:
5221 rte_intr_efd_disable(intr_handle);
5226 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5228 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5229 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5230 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5234 if (dev->data->dev_conf.intr_conf.rxq == 0)
5237 if (rte_intr_dp_is_en(intr_handle)) {
5238 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5239 ret = hns3_bind_ring_with_vector(hw,
5240 intr_handle->intr_vec[q_id], true,
5241 HNS3_RING_TYPE_RX, q_id);
5251 hns3_restore_filter(struct rte_eth_dev *dev)
5253 hns3_restore_rss_filter(dev);
5257 hns3_dev_start(struct rte_eth_dev *dev)
5259 struct hns3_adapter *hns = dev->data->dev_private;
5260 struct hns3_hw *hw = &hns->hw;
5263 PMD_INIT_FUNC_TRACE();
5264 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5267 rte_spinlock_lock(&hw->lock);
5268 hw->adapter_state = HNS3_NIC_STARTING;
5270 ret = hns3_do_start(hns, true);
5272 hw->adapter_state = HNS3_NIC_CONFIGURED;
5273 rte_spinlock_unlock(&hw->lock);
5276 ret = hns3_map_rx_interrupt(dev);
5278 goto map_rx_inter_err;
5281 * There are three register used to control the status of a TQP
5282 * (contains a pair of Tx queue and Rx queue) in the new version network
5283 * engine. One is used to control the enabling of Tx queue, the other is
5284 * used to control the enabling of Rx queue, and the last is the master
5285 * switch used to control the enabling of the tqp. The Tx register and
5286 * TQP register must be enabled at the same time to enable a Tx queue.
5287 * The same applies to the Rx queue. For the older network engine, this
5288 * function only refresh the enabled flag, and it is used to update the
5289 * status of queue in the dpdk framework.
5291 ret = hns3_start_all_txqs(dev);
5293 goto map_rx_inter_err;
5295 ret = hns3_start_all_rxqs(dev);
5297 goto start_all_rxqs_fail;
5299 hw->adapter_state = HNS3_NIC_STARTED;
5300 rte_spinlock_unlock(&hw->lock);
5302 hns3_rx_scattered_calc(dev);
5303 hns3_set_rxtx_function(dev);
5304 hns3_mp_req_start_rxtx(dev);
5305 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5307 hns3_restore_filter(dev);
5309 /* Enable interrupt of all rx queues before enabling queues */
5310 hns3_dev_all_rx_queue_intr_enable(hw, true);
5313 * After finished the initialization, enable tqps to receive/transmit
5314 * packets and refresh all queue status.
5316 hns3_start_tqps(hw);
5318 hns3_tm_dev_start_proc(hw);
5320 hns3_info(hw, "hns3 dev start successful!");
5324 start_all_rxqs_fail:
5325 hns3_stop_all_txqs(dev);
5327 (void)hns3_do_stop(hns);
5328 hw->adapter_state = HNS3_NIC_CONFIGURED;
5329 rte_spinlock_unlock(&hw->lock);
5335 hns3_do_stop(struct hns3_adapter *hns)
5337 struct hns3_hw *hw = &hns->hw;
5341 * The "hns3_do_stop" function will also be called by .stop_service to
5342 * prepare reset. At the time of global or IMP reset, the command cannot
5343 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5344 * accessed during the reset process. So the mbuf can not be released
5345 * during reset and is required to be released after the reset is
5348 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5349 hns3_dev_release_mbufs(hns);
5351 ret = hns3_cfg_mac_mode(hw, false);
5354 hw->mac.link_status = ETH_LINK_DOWN;
5356 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5357 hns3_configure_all_mac_addr(hns, true);
5358 ret = hns3_reset_all_tqps(hns);
5360 hns3_err(hw, "failed to reset all queues ret = %d.",
5365 hw->mac.default_addr_setted = false;
5370 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5372 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5373 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5374 struct hns3_adapter *hns = dev->data->dev_private;
5375 struct hns3_hw *hw = &hns->hw;
5376 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5377 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5380 if (dev->data->dev_conf.intr_conf.rxq == 0)
5383 /* unmap the ring with vector */
5384 if (rte_intr_allow_others(intr_handle)) {
5385 vec = RTE_INTR_VEC_RXTX_OFFSET;
5386 base = RTE_INTR_VEC_RXTX_OFFSET;
5388 if (rte_intr_dp_is_en(intr_handle)) {
5389 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5390 (void)hns3_bind_ring_with_vector(hw, vec, false,
5393 if (vec < base + intr_handle->nb_efd - 1)
5397 /* Clean datapath event and queue/vec mapping */
5398 rte_intr_efd_disable(intr_handle);
5399 if (intr_handle->intr_vec) {
5400 rte_free(intr_handle->intr_vec);
5401 intr_handle->intr_vec = NULL;
5406 hns3_dev_stop(struct rte_eth_dev *dev)
5408 struct hns3_adapter *hns = dev->data->dev_private;
5409 struct hns3_hw *hw = &hns->hw;
5411 PMD_INIT_FUNC_TRACE();
5412 dev->data->dev_started = 0;
5414 hw->adapter_state = HNS3_NIC_STOPPING;
5415 hns3_set_rxtx_function(dev);
5417 /* Disable datapath on secondary process. */
5418 hns3_mp_req_stop_rxtx(dev);
5419 /* Prevent crashes when queues are still in use. */
5420 rte_delay_ms(hw->tqps_num);
5422 rte_spinlock_lock(&hw->lock);
5423 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5424 hns3_tm_dev_stop_proc(hw);
5425 hns3_config_mac_tnl_int(hw, false);
5428 hns3_unmap_rx_interrupt(dev);
5429 hw->adapter_state = HNS3_NIC_CONFIGURED;
5431 hns3_rx_scattered_reset(dev);
5432 rte_eal_alarm_cancel(hns3_service_handler, dev);
5433 rte_spinlock_unlock(&hw->lock);
5439 hns3_dev_close(struct rte_eth_dev *eth_dev)
5441 struct hns3_adapter *hns = eth_dev->data->dev_private;
5442 struct hns3_hw *hw = &hns->hw;
5445 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5446 rte_free(eth_dev->process_private);
5447 eth_dev->process_private = NULL;
5451 if (hw->adapter_state == HNS3_NIC_STARTED)
5452 ret = hns3_dev_stop(eth_dev);
5454 hw->adapter_state = HNS3_NIC_CLOSING;
5455 hns3_reset_abort(hns);
5456 hw->adapter_state = HNS3_NIC_CLOSED;
5458 hns3_configure_all_mc_mac_addr(hns, true);
5459 hns3_remove_all_vlan_table(hns);
5460 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5461 hns3_uninit_pf(eth_dev);
5462 hns3_free_all_queues(eth_dev);
5463 rte_free(hw->reset.wait_data);
5464 rte_free(eth_dev->process_private);
5465 eth_dev->process_private = NULL;
5466 hns3_mp_uninit_primary();
5467 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5473 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5475 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5476 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5478 fc_conf->pause_time = pf->pause_time;
5480 /* return fc current mode */
5481 switch (hw->current_mode) {
5483 fc_conf->mode = RTE_FC_FULL;
5485 case HNS3_FC_TX_PAUSE:
5486 fc_conf->mode = RTE_FC_TX_PAUSE;
5488 case HNS3_FC_RX_PAUSE:
5489 fc_conf->mode = RTE_FC_RX_PAUSE;
5493 fc_conf->mode = RTE_FC_NONE;
5501 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5505 hw->requested_mode = HNS3_FC_NONE;
5507 case RTE_FC_RX_PAUSE:
5508 hw->requested_mode = HNS3_FC_RX_PAUSE;
5510 case RTE_FC_TX_PAUSE:
5511 hw->requested_mode = HNS3_FC_TX_PAUSE;
5514 hw->requested_mode = HNS3_FC_FULL;
5517 hw->requested_mode = HNS3_FC_NONE;
5518 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5519 "configured to RTE_FC_NONE", mode);
5525 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5527 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5531 if (fc_conf->high_water || fc_conf->low_water ||
5532 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5533 hns3_err(hw, "Unsupported flow control settings specified, "
5534 "high_water(%u), low_water(%u), send_xon(%u) and "
5535 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5536 fc_conf->high_water, fc_conf->low_water,
5537 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5540 if (fc_conf->autoneg) {
5541 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5544 if (!fc_conf->pause_time) {
5545 hns3_err(hw, "Invalid pause time %u setting.",
5546 fc_conf->pause_time);
5550 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5551 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5552 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5553 "current_fc_status = %d", hw->current_fc_status);
5557 if (hw->num_tc > 1) {
5558 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5562 hns3_get_fc_mode(hw, fc_conf->mode);
5563 if (hw->requested_mode == hw->current_mode &&
5564 pf->pause_time == fc_conf->pause_time)
5567 rte_spinlock_lock(&hw->lock);
5568 ret = hns3_fc_enable(dev, fc_conf);
5569 rte_spinlock_unlock(&hw->lock);
5575 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5576 struct rte_eth_pfc_conf *pfc_conf)
5578 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5579 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5583 if (!hns3_dev_dcb_supported(hw)) {
5584 hns3_err(hw, "This port does not support dcb configurations.");
5588 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5589 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5590 hns3_err(hw, "Unsupported flow control settings specified, "
5591 "high_water(%u), low_water(%u), send_xon(%u) and "
5592 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5593 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5594 pfc_conf->fc.send_xon,
5595 pfc_conf->fc.mac_ctrl_frame_fwd);
5598 if (pfc_conf->fc.autoneg) {
5599 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5602 if (pfc_conf->fc.pause_time == 0) {
5603 hns3_err(hw, "Invalid pause time %u setting.",
5604 pfc_conf->fc.pause_time);
5608 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5609 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5610 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5611 "current_fc_status = %d", hw->current_fc_status);
5615 priority = pfc_conf->priority;
5616 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5617 if (hw->dcb_info.pfc_en & BIT(priority) &&
5618 hw->requested_mode == hw->current_mode &&
5619 pfc_conf->fc.pause_time == pf->pause_time)
5622 rte_spinlock_lock(&hw->lock);
5623 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5624 rte_spinlock_unlock(&hw->lock);
5630 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5632 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5633 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5634 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5637 rte_spinlock_lock(&hw->lock);
5638 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5639 dcb_info->nb_tcs = pf->local_max_tc;
5641 dcb_info->nb_tcs = 1;
5643 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5644 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5645 for (i = 0; i < dcb_info->nb_tcs; i++)
5646 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5648 for (i = 0; i < hw->num_tc; i++) {
5649 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5650 dcb_info->tc_queue.tc_txq[0][i].base =
5651 hw->tc_queue[i].tqp_offset;
5652 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5653 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5654 hw->tc_queue[i].tqp_count;
5656 rte_spinlock_unlock(&hw->lock);
5662 hns3_reinit_dev(struct hns3_adapter *hns)
5664 struct hns3_hw *hw = &hns->hw;
5667 ret = hns3_cmd_init(hw);
5669 hns3_err(hw, "Failed to init cmd: %d", ret);
5673 ret = hns3_reset_all_tqps(hns);
5675 hns3_err(hw, "Failed to reset all queues: %d", ret);
5679 ret = hns3_init_hardware(hns);
5681 hns3_err(hw, "Failed to init hardware: %d", ret);
5685 ret = hns3_enable_hw_error_intr(hns, true);
5687 hns3_err(hw, "fail to enable hw error interrupts: %d",
5691 hns3_info(hw, "Reset done, driver initialization finished.");
5697 is_pf_reset_done(struct hns3_hw *hw)
5699 uint32_t val, reg, reg_bit;
5701 switch (hw->reset.level) {
5702 case HNS3_IMP_RESET:
5703 reg = HNS3_GLOBAL_RESET_REG;
5704 reg_bit = HNS3_IMP_RESET_BIT;
5706 case HNS3_GLOBAL_RESET:
5707 reg = HNS3_GLOBAL_RESET_REG;
5708 reg_bit = HNS3_GLOBAL_RESET_BIT;
5710 case HNS3_FUNC_RESET:
5711 reg = HNS3_FUN_RST_ING;
5712 reg_bit = HNS3_FUN_RST_ING_B;
5714 case HNS3_FLR_RESET:
5716 hns3_err(hw, "Wait for unsupported reset level: %d",
5720 val = hns3_read_dev(hw, reg);
5721 if (hns3_get_bit(val, reg_bit))
5728 hns3_is_reset_pending(struct hns3_adapter *hns)
5730 struct hns3_hw *hw = &hns->hw;
5731 enum hns3_reset_level reset;
5733 hns3_check_event_cause(hns, NULL);
5734 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5735 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5736 hns3_warn(hw, "High level reset %d is pending", reset);
5739 reset = hns3_get_reset_level(hns, &hw->reset.request);
5740 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5741 hns3_warn(hw, "High level reset %d is request", reset);
5748 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5750 struct hns3_hw *hw = &hns->hw;
5751 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5754 if (wait_data->result == HNS3_WAIT_SUCCESS)
5756 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5757 gettimeofday(&tv, NULL);
5758 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5759 tv.tv_sec, tv.tv_usec);
5761 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5764 wait_data->hns = hns;
5765 wait_data->check_completion = is_pf_reset_done;
5766 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5767 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5768 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5769 wait_data->count = HNS3_RESET_WAIT_CNT;
5770 wait_data->result = HNS3_WAIT_REQUEST;
5771 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5776 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5778 struct hns3_cmd_desc desc;
5779 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5781 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5782 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5783 req->fun_reset_vfid = func_id;
5785 return hns3_cmd_send(hw, &desc, 1);
5789 hns3_imp_reset_cmd(struct hns3_hw *hw)
5791 struct hns3_cmd_desc desc;
5793 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5794 desc.data[0] = 0xeedd;
5796 return hns3_cmd_send(hw, &desc, 1);
5800 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5802 struct hns3_hw *hw = &hns->hw;
5806 gettimeofday(&tv, NULL);
5807 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5808 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5809 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5810 tv.tv_sec, tv.tv_usec);
5814 switch (reset_level) {
5815 case HNS3_IMP_RESET:
5816 hns3_imp_reset_cmd(hw);
5817 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5818 tv.tv_sec, tv.tv_usec);
5820 case HNS3_GLOBAL_RESET:
5821 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5822 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5823 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5824 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5825 tv.tv_sec, tv.tv_usec);
5827 case HNS3_FUNC_RESET:
5828 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5829 tv.tv_sec, tv.tv_usec);
5830 /* schedule again to check later */
5831 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5832 hns3_schedule_reset(hns);
5835 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5838 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5841 static enum hns3_reset_level
5842 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5844 struct hns3_hw *hw = &hns->hw;
5845 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5847 /* Return the highest priority reset level amongst all */
5848 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5849 reset_level = HNS3_IMP_RESET;
5850 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5851 reset_level = HNS3_GLOBAL_RESET;
5852 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5853 reset_level = HNS3_FUNC_RESET;
5854 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5855 reset_level = HNS3_FLR_RESET;
5857 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5858 return HNS3_NONE_RESET;
5864 hns3_record_imp_error(struct hns3_adapter *hns)
5866 struct hns3_hw *hw = &hns->hw;
5869 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5870 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5871 hns3_warn(hw, "Detected IMP RD poison!");
5872 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5873 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5876 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5877 hns3_warn(hw, "Detected IMP CMDQ error!");
5878 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5879 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5884 hns3_prepare_reset(struct hns3_adapter *hns)
5886 struct hns3_hw *hw = &hns->hw;
5890 switch (hw->reset.level) {
5891 case HNS3_FUNC_RESET:
5892 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5897 * After performaning pf reset, it is not necessary to do the
5898 * mailbox handling or send any command to firmware, because
5899 * any mailbox handling or command to firmware is only valid
5900 * after hns3_cmd_init is called.
5902 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5903 hw->reset.stats.request_cnt++;
5905 case HNS3_IMP_RESET:
5906 hns3_record_imp_error(hns);
5907 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5908 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5909 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5918 hns3_set_rst_done(struct hns3_hw *hw)
5920 struct hns3_pf_rst_done_cmd *req;
5921 struct hns3_cmd_desc desc;
5923 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5924 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5925 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5926 return hns3_cmd_send(hw, &desc, 1);
5930 hns3_stop_service(struct hns3_adapter *hns)
5932 struct hns3_hw *hw = &hns->hw;
5933 struct rte_eth_dev *eth_dev;
5935 eth_dev = &rte_eth_devices[hw->data->port_id];
5936 if (hw->adapter_state == HNS3_NIC_STARTED) {
5937 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5938 hns3_update_link_status_and_event(hw);
5940 hw->mac.link_status = ETH_LINK_DOWN;
5942 hns3_set_rxtx_function(eth_dev);
5944 /* Disable datapath on secondary process. */
5945 hns3_mp_req_stop_rxtx(eth_dev);
5946 rte_delay_ms(hw->tqps_num);
5948 rte_spinlock_lock(&hw->lock);
5949 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5950 hw->adapter_state == HNS3_NIC_STOPPING) {
5951 hns3_enable_all_queues(hw, false);
5953 hw->reset.mbuf_deferred_free = true;
5955 hw->reset.mbuf_deferred_free = false;
5958 * It is cumbersome for hardware to pick-and-choose entries for deletion
5959 * from table space. Hence, for function reset software intervention is
5960 * required to delete the entries
5962 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5963 hns3_configure_all_mc_mac_addr(hns, true);
5964 rte_spinlock_unlock(&hw->lock);
5970 hns3_start_service(struct hns3_adapter *hns)
5972 struct hns3_hw *hw = &hns->hw;
5973 struct rte_eth_dev *eth_dev;
5975 if (hw->reset.level == HNS3_IMP_RESET ||
5976 hw->reset.level == HNS3_GLOBAL_RESET)
5977 hns3_set_rst_done(hw);
5978 eth_dev = &rte_eth_devices[hw->data->port_id];
5979 hns3_set_rxtx_function(eth_dev);
5980 hns3_mp_req_start_rxtx(eth_dev);
5981 if (hw->adapter_state == HNS3_NIC_STARTED) {
5983 * This API parent function already hold the hns3_hw.lock, the
5984 * hns3_service_handler may report lse, in bonding application
5985 * it will call driver's ops which may acquire the hns3_hw.lock
5986 * again, thus lead to deadlock.
5987 * We defer calls hns3_service_handler to avoid the deadlock.
5989 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5990 hns3_service_handler, eth_dev);
5992 /* Enable interrupt of all rx queues before enabling queues */
5993 hns3_dev_all_rx_queue_intr_enable(hw, true);
5995 * Enable state of each rxq and txq will be recovered after
5996 * reset, so we need to restore them before enable all tqps;
5998 hns3_restore_tqp_enable_state(hw);
6000 * When finished the initialization, enable queues to receive
6001 * and transmit packets.
6003 hns3_enable_all_queues(hw, true);
6010 hns3_restore_conf(struct hns3_adapter *hns)
6012 struct hns3_hw *hw = &hns->hw;
6015 ret = hns3_configure_all_mac_addr(hns, false);
6019 ret = hns3_configure_all_mc_mac_addr(hns, false);
6023 ret = hns3_dev_promisc_restore(hns);
6027 ret = hns3_restore_vlan_table(hns);
6031 ret = hns3_restore_vlan_conf(hns);
6035 ret = hns3_restore_all_fdir_filter(hns);
6039 ret = hns3_restore_ptp(hns);
6043 ret = hns3_restore_rx_interrupt(hw);
6047 ret = hns3_restore_gro_conf(hw);
6051 ret = hns3_restore_fec(hw);
6055 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6056 ret = hns3_do_start(hns, false);
6059 hns3_info(hw, "hns3 dev restart successful!");
6060 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6061 hw->adapter_state = HNS3_NIC_CONFIGURED;
6065 hns3_configure_all_mc_mac_addr(hns, true);
6067 hns3_configure_all_mac_addr(hns, true);
6072 hns3_reset_service(void *param)
6074 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6075 struct hns3_hw *hw = &hns->hw;
6076 enum hns3_reset_level reset_level;
6077 struct timeval tv_delta;
6078 struct timeval tv_start;
6084 * The interrupt is not triggered within the delay time.
6085 * The interrupt may have been lost. It is necessary to handle
6086 * the interrupt to recover from the error.
6088 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6089 SCHEDULE_DEFERRED) {
6090 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6092 hns3_err(hw, "Handling interrupts in delayed tasks");
6093 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6094 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6095 if (reset_level == HNS3_NONE_RESET) {
6096 hns3_err(hw, "No reset level is set, try IMP reset");
6097 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6100 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6103 * Check if there is any ongoing reset in the hardware. This status can
6104 * be checked from reset_pending. If there is then, we need to wait for
6105 * hardware to complete reset.
6106 * a. If we are able to figure out in reasonable time that hardware
6107 * has fully resetted then, we can proceed with driver, client
6109 * b. else, we can come back later to check this status so re-sched
6112 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6113 if (reset_level != HNS3_NONE_RESET) {
6114 gettimeofday(&tv_start, NULL);
6115 ret = hns3_reset_process(hns, reset_level);
6116 gettimeofday(&tv, NULL);
6117 timersub(&tv, &tv_start, &tv_delta);
6118 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6119 tv_delta.tv_usec / USEC_PER_MSEC;
6120 if (msec > HNS3_RESET_PROCESS_MS)
6121 hns3_err(hw, "%d handle long time delta %" PRIx64
6122 " ms time=%ld.%.6ld",
6123 hw->reset.level, msec,
6124 tv.tv_sec, tv.tv_usec);
6129 /* Check if we got any *new* reset requests to be honored */
6130 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6131 if (reset_level != HNS3_NONE_RESET)
6132 hns3_msix_process(hns, reset_level);
6136 hns3_get_speed_capa_num(uint16_t device_id)
6140 switch (device_id) {
6141 case HNS3_DEV_ID_25GE:
6142 case HNS3_DEV_ID_25GE_RDMA:
6145 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6146 case HNS3_DEV_ID_200G_RDMA:
6158 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6161 switch (device_id) {
6162 case HNS3_DEV_ID_25GE:
6164 case HNS3_DEV_ID_25GE_RDMA:
6165 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6166 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6168 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6169 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6170 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6172 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6173 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6174 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6176 case HNS3_DEV_ID_200G_RDMA:
6177 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6178 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6188 hns3_fec_get_capability(struct rte_eth_dev *dev,
6189 struct rte_eth_fec_capa *speed_fec_capa,
6192 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6194 uint16_t device_id = pci_dev->id.device_id;
6195 unsigned int capa_num;
6198 capa_num = hns3_get_speed_capa_num(device_id);
6199 if (capa_num == 0) {
6200 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6205 if (speed_fec_capa == NULL || num < capa_num)
6208 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6216 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6218 struct hns3_config_fec_cmd *req;
6219 struct hns3_cmd_desc desc;
6223 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6224 * in device of link speed
6227 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6232 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6233 req = (struct hns3_config_fec_cmd *)desc.data;
6234 ret = hns3_cmd_send(hw, &desc, 1);
6236 hns3_err(hw, "get current fec auto state failed, ret = %d",
6241 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6246 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6248 #define QUERY_ACTIVE_SPEED 1
6249 struct hns3_sfp_speed_cmd *resp;
6250 uint32_t tmp_fec_capa;
6252 struct hns3_cmd_desc desc;
6256 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6257 * configured FEC mode is returned.
6258 * If link is up, current FEC mode is returned.
6260 if (hw->mac.link_status == ETH_LINK_DOWN) {
6261 ret = get_current_fec_auto_state(hw, &auto_state);
6265 if (auto_state == 0x1) {
6266 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6271 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6272 resp = (struct hns3_sfp_speed_cmd *)desc.data;
6273 resp->query_type = QUERY_ACTIVE_SPEED;
6275 ret = hns3_cmd_send(hw, &desc, 1);
6276 if (ret == -EOPNOTSUPP) {
6277 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6280 hns3_err(hw, "get FEC failed, ret = %d", ret);
6285 * FEC mode order defined in hns3 hardware is inconsistend with
6286 * that defined in the ethdev library. So the sequence needs
6289 switch (resp->active_fec) {
6290 case HNS3_HW_FEC_MODE_NOFEC:
6291 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6293 case HNS3_HW_FEC_MODE_BASER:
6294 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6296 case HNS3_HW_FEC_MODE_RS:
6297 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6300 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6304 *fec_capa = tmp_fec_capa;
6309 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6311 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313 return hns3_fec_get_internal(hw, fec_capa);
6317 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6319 struct hns3_config_fec_cmd *req;
6320 struct hns3_cmd_desc desc;
6323 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6325 req = (struct hns3_config_fec_cmd *)desc.data;
6327 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6328 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6329 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6331 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6332 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6333 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6335 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6336 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6337 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6339 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6340 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6345 ret = hns3_cmd_send(hw, &desc, 1);
6347 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6353 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6355 struct hns3_mac *mac = &hw->mac;
6358 switch (mac->link_speed) {
6359 case ETH_SPEED_NUM_10G:
6360 cur_capa = fec_capa[1].capa;
6362 case ETH_SPEED_NUM_25G:
6363 case ETH_SPEED_NUM_100G:
6364 case ETH_SPEED_NUM_200G:
6365 cur_capa = fec_capa[0].capa;
6376 is_fec_mode_one_bit_set(uint32_t mode)
6381 for (i = 0; i < sizeof(mode); i++)
6382 if (mode >> i & 0x1)
6385 return cnt == 1 ? true : false;
6389 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6391 #define FEC_CAPA_NUM 2
6392 struct hns3_adapter *hns = dev->data->dev_private;
6393 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6394 struct hns3_pf *pf = &hns->pf;
6396 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6398 uint32_t num = FEC_CAPA_NUM;
6401 ret = hns3_fec_get_capability(dev, fec_capa, num);
6405 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6406 if (!is_fec_mode_one_bit_set(mode))
6407 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6408 "FEC mode should be only one bit set", mode);
6411 * Check whether the configured mode is within the FEC capability.
6412 * If not, the configured mode will not be supported.
6414 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6415 if (!(cur_capa & mode)) {
6416 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6420 ret = hns3_set_fec_hw(hw, mode);
6424 pf->fec_mode = mode;
6429 hns3_restore_fec(struct hns3_hw *hw)
6431 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6432 struct hns3_pf *pf = &hns->pf;
6433 uint32_t mode = pf->fec_mode;
6436 ret = hns3_set_fec_hw(hw, mode);
6438 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6445 hns3_query_dev_fec_info(struct hns3_hw *hw)
6447 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6448 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6451 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6453 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6459 hns3_optical_module_existed(struct hns3_hw *hw)
6461 struct hns3_cmd_desc desc;
6465 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6466 ret = hns3_cmd_send(hw, &desc, 1);
6469 "fail to get optical module exist state, ret = %d.\n",
6473 existed = !!desc.data[0];
6479 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6480 uint32_t len, uint8_t *data)
6482 #define HNS3_SFP_INFO_CMD_NUM 6
6483 #define HNS3_SFP_INFO_MAX_LEN \
6484 (HNS3_SFP_INFO_BD0_LEN + \
6485 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6486 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6487 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6493 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6494 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6496 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6497 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6500 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6501 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6502 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6503 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6505 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6507 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6512 /* The data format in BD0 is different with the others. */
6513 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6514 memcpy(data, sfp_info_bd0->data, copy_len);
6515 read_len = copy_len;
6517 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6518 if (read_len >= len)
6521 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6522 memcpy(data + read_len, desc[i].data, copy_len);
6523 read_len += copy_len;
6526 return (int)read_len;
6530 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6531 struct rte_dev_eeprom_info *info)
6533 struct hns3_adapter *hns = dev->data->dev_private;
6534 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6535 uint32_t offset = info->offset;
6536 uint32_t len = info->length;
6537 uint8_t *data = info->data;
6538 uint32_t read_len = 0;
6540 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6543 if (!hns3_optical_module_existed(hw)) {
6544 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6548 while (read_len < len) {
6550 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6562 hns3_get_module_info(struct rte_eth_dev *dev,
6563 struct rte_eth_dev_module_info *modinfo)
6565 #define HNS3_SFF8024_ID_SFP 0x03
6566 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
6567 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
6568 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
6569 #define HNS3_SFF_8636_V1_3 0x03
6570 struct hns3_adapter *hns = dev->data->dev_private;
6571 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6572 struct rte_dev_eeprom_info info;
6573 struct hns3_sfp_type sfp_type;
6576 memset(&sfp_type, 0, sizeof(sfp_type));
6577 memset(&info, 0, sizeof(info));
6578 info.data = (uint8_t *)&sfp_type;
6579 info.length = sizeof(sfp_type);
6580 ret = hns3_get_module_eeprom(dev, &info);
6584 switch (sfp_type.type) {
6585 case HNS3_SFF8024_ID_SFP:
6586 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6587 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6589 case HNS3_SFF8024_ID_QSFP_8438:
6590 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6591 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6593 case HNS3_SFF8024_ID_QSFP_8436_8636:
6594 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6595 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6596 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6598 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6599 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6602 case HNS3_SFF8024_ID_QSFP28_8636:
6603 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6604 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6607 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6608 sfp_type.type, sfp_type.ext_type);
6616 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6618 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6622 if (strcmp(value, "vec") == 0)
6623 hint = HNS3_IO_FUNC_HINT_VEC;
6624 else if (strcmp(value, "sve") == 0)
6625 hint = HNS3_IO_FUNC_HINT_SVE;
6626 else if (strcmp(value, "simple") == 0)
6627 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6628 else if (strcmp(value, "common") == 0)
6629 hint = HNS3_IO_FUNC_HINT_COMMON;
6631 /* If the hint is valid then update output parameters */
6632 if (hint != HNS3_IO_FUNC_HINT_NONE)
6633 *(uint32_t *)extra_args = hint;
6639 hns3_get_io_hint_func_name(uint32_t hint)
6642 case HNS3_IO_FUNC_HINT_VEC:
6644 case HNS3_IO_FUNC_HINT_SVE:
6646 case HNS3_IO_FUNC_HINT_SIMPLE:
6648 case HNS3_IO_FUNC_HINT_COMMON:
6656 hns3_parse_devargs(struct rte_eth_dev *dev)
6658 struct hns3_adapter *hns = dev->data->dev_private;
6659 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6660 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6661 struct hns3_hw *hw = &hns->hw;
6662 struct rte_kvargs *kvlist;
6664 if (dev->device->devargs == NULL)
6667 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6671 rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6672 &hns3_parse_io_hint_func, &rx_func_hint);
6673 rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6674 &hns3_parse_io_hint_func, &tx_func_hint);
6675 rte_kvargs_free(kvlist);
6677 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6678 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6679 hns3_get_io_hint_func_name(rx_func_hint));
6680 hns->rx_func_hint = rx_func_hint;
6681 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6682 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6683 hns3_get_io_hint_func_name(tx_func_hint));
6684 hns->tx_func_hint = tx_func_hint;
6687 static const struct eth_dev_ops hns3_eth_dev_ops = {
6688 .dev_configure = hns3_dev_configure,
6689 .dev_start = hns3_dev_start,
6690 .dev_stop = hns3_dev_stop,
6691 .dev_close = hns3_dev_close,
6692 .promiscuous_enable = hns3_dev_promiscuous_enable,
6693 .promiscuous_disable = hns3_dev_promiscuous_disable,
6694 .allmulticast_enable = hns3_dev_allmulticast_enable,
6695 .allmulticast_disable = hns3_dev_allmulticast_disable,
6696 .mtu_set = hns3_dev_mtu_set,
6697 .stats_get = hns3_stats_get,
6698 .stats_reset = hns3_stats_reset,
6699 .xstats_get = hns3_dev_xstats_get,
6700 .xstats_get_names = hns3_dev_xstats_get_names,
6701 .xstats_reset = hns3_dev_xstats_reset,
6702 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6703 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6704 .dev_infos_get = hns3_dev_infos_get,
6705 .fw_version_get = hns3_fw_version_get,
6706 .rx_queue_setup = hns3_rx_queue_setup,
6707 .tx_queue_setup = hns3_tx_queue_setup,
6708 .rx_queue_release = hns3_dev_rx_queue_release,
6709 .tx_queue_release = hns3_dev_tx_queue_release,
6710 .rx_queue_start = hns3_dev_rx_queue_start,
6711 .rx_queue_stop = hns3_dev_rx_queue_stop,
6712 .tx_queue_start = hns3_dev_tx_queue_start,
6713 .tx_queue_stop = hns3_dev_tx_queue_stop,
6714 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6715 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6716 .rxq_info_get = hns3_rxq_info_get,
6717 .txq_info_get = hns3_txq_info_get,
6718 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6719 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6720 .flow_ctrl_get = hns3_flow_ctrl_get,
6721 .flow_ctrl_set = hns3_flow_ctrl_set,
6722 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6723 .mac_addr_add = hns3_add_mac_addr,
6724 .mac_addr_remove = hns3_remove_mac_addr,
6725 .mac_addr_set = hns3_set_default_mac_addr,
6726 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6727 .link_update = hns3_dev_link_update,
6728 .rss_hash_update = hns3_dev_rss_hash_update,
6729 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6730 .reta_update = hns3_dev_rss_reta_update,
6731 .reta_query = hns3_dev_rss_reta_query,
6732 .flow_ops_get = hns3_dev_flow_ops_get,
6733 .vlan_filter_set = hns3_vlan_filter_set,
6734 .vlan_tpid_set = hns3_vlan_tpid_set,
6735 .vlan_offload_set = hns3_vlan_offload_set,
6736 .vlan_pvid_set = hns3_vlan_pvid_set,
6737 .get_reg = hns3_get_regs,
6738 .get_module_info = hns3_get_module_info,
6739 .get_module_eeprom = hns3_get_module_eeprom,
6740 .get_dcb_info = hns3_get_dcb_info,
6741 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6742 .fec_get_capability = hns3_fec_get_capability,
6743 .fec_get = hns3_fec_get,
6744 .fec_set = hns3_fec_set,
6745 .tm_ops_get = hns3_tm_ops_get,
6746 .tx_done_cleanup = hns3_tx_done_cleanup,
6747 .timesync_enable = hns3_timesync_enable,
6748 .timesync_disable = hns3_timesync_disable,
6749 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6750 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6751 .timesync_adjust_time = hns3_timesync_adjust_time,
6752 .timesync_read_time = hns3_timesync_read_time,
6753 .timesync_write_time = hns3_timesync_write_time,
6756 static const struct hns3_reset_ops hns3_reset_ops = {
6757 .reset_service = hns3_reset_service,
6758 .stop_service = hns3_stop_service,
6759 .prepare_reset = hns3_prepare_reset,
6760 .wait_hardware_ready = hns3_wait_hardware_ready,
6761 .reinit_dev = hns3_reinit_dev,
6762 .restore_conf = hns3_restore_conf,
6763 .start_service = hns3_start_service,
6767 hns3_dev_init(struct rte_eth_dev *eth_dev)
6769 struct hns3_adapter *hns = eth_dev->data->dev_private;
6770 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6771 struct rte_ether_addr *eth_addr;
6772 struct hns3_hw *hw = &hns->hw;
6775 PMD_INIT_FUNC_TRACE();
6777 eth_dev->process_private = (struct hns3_process_private *)
6778 rte_zmalloc_socket("hns3_filter_list",
6779 sizeof(struct hns3_process_private),
6780 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6781 if (eth_dev->process_private == NULL) {
6782 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6785 /* initialize flow filter lists */
6786 hns3_filterlist_init(eth_dev);
6788 hns3_set_rxtx_function(eth_dev);
6789 eth_dev->dev_ops = &hns3_eth_dev_ops;
6790 eth_dev->rx_queue_count = hns3_rx_queue_count;
6791 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6792 ret = hns3_mp_init_secondary();
6794 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6795 "process, ret = %d", ret);
6796 goto err_mp_init_secondary;
6799 hw->secondary_cnt++;
6803 ret = hns3_mp_init_primary();
6806 "Failed to init for primary process, ret = %d",
6808 goto err_mp_init_primary;
6811 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6813 hw->data = eth_dev->data;
6814 hns3_parse_devargs(eth_dev);
6817 * Set default max packet size according to the mtu
6818 * default vale in DPDK frame.
6820 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6822 ret = hns3_reset_init(hw);
6824 goto err_init_reset;
6825 hw->reset.ops = &hns3_reset_ops;
6827 ret = hns3_init_pf(eth_dev);
6829 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6833 /* Allocate memory for storing MAC addresses */
6834 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6835 sizeof(struct rte_ether_addr) *
6836 HNS3_UC_MACADDR_NUM, 0);
6837 if (eth_dev->data->mac_addrs == NULL) {
6838 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6839 "to store MAC addresses",
6840 sizeof(struct rte_ether_addr) *
6841 HNS3_UC_MACADDR_NUM);
6843 goto err_rte_zmalloc;
6846 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6847 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6848 rte_eth_random_addr(hw->mac.mac_addr);
6849 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6850 (struct rte_ether_addr *)hw->mac.mac_addr);
6851 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6852 "unicast address, using random MAC address %s",
6855 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6856 ð_dev->data->mac_addrs[0]);
6858 hw->adapter_state = HNS3_NIC_INITIALIZED;
6860 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6862 hns3_err(hw, "Reschedule reset service after dev_init");
6863 hns3_schedule_reset(hns);
6865 /* IMP will wait ready flag before reset */
6866 hns3_notify_reset_ready(hw, false);
6869 hns3_info(hw, "hns3 dev initialization successful!");
6873 hns3_uninit_pf(eth_dev);
6876 rte_free(hw->reset.wait_data);
6879 hns3_mp_uninit_primary();
6881 err_mp_init_primary:
6882 err_mp_init_secondary:
6883 eth_dev->dev_ops = NULL;
6884 eth_dev->rx_pkt_burst = NULL;
6885 eth_dev->rx_descriptor_status = NULL;
6886 eth_dev->tx_pkt_burst = NULL;
6887 eth_dev->tx_pkt_prepare = NULL;
6888 eth_dev->tx_descriptor_status = NULL;
6889 rte_free(eth_dev->process_private);
6890 eth_dev->process_private = NULL;
6895 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6897 struct hns3_adapter *hns = eth_dev->data->dev_private;
6898 struct hns3_hw *hw = &hns->hw;
6900 PMD_INIT_FUNC_TRACE();
6902 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6903 rte_free(eth_dev->process_private);
6904 eth_dev->process_private = NULL;
6908 if (hw->adapter_state < HNS3_NIC_CLOSING)
6909 hns3_dev_close(eth_dev);
6911 hw->adapter_state = HNS3_NIC_REMOVED;
6916 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6917 struct rte_pci_device *pci_dev)
6919 return rte_eth_dev_pci_generic_probe(pci_dev,
6920 sizeof(struct hns3_adapter),
6925 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6927 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6930 static const struct rte_pci_id pci_id_hns3_map[] = {
6931 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6932 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6933 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6934 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6935 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6936 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6937 { .vendor_id = 0, }, /* sentinel */
6940 static struct rte_pci_driver rte_hns3_pmd = {
6941 .id_table = pci_id_hns3_map,
6942 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6943 .probe = eth_hns3_pci_probe,
6944 .remove = eth_hns3_pci_remove,
6947 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6948 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6949 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6950 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6951 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6952 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6953 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6954 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);