drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVALID_PVID               0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  60 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  62
  63 #define HNS3_RESET_WAIT_MS      100
  64 #define HNS3_RESET_WAIT_CNT     200
  65
  66 enum hns3_evt_cause {
  67         HNS3_VECTOR0_EVENT_RST,
  68         HNS3_VECTOR0_EVENT_MBX,
  69         HNS3_VECTOR0_EVENT_ERR,
  70         HNS3_VECTOR0_EVENT_OTHER,
  71 };
  72
  73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  74                                                  uint64_t *levels);
  75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  77                                     int on);
  78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  79
  80 static int hns3_add_mc_addr(struct hns3_hw *hw,
  81                             struct rte_ether_addr *mac_addr);
  82 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84
  85 static void
  86 hns3_pf_disable_irq0(struct hns3_hw *hw)
  87 {
  88         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  89 }
  90
  91 static void
  92 hns3_pf_enable_irq0(struct hns3_hw *hw)
  93 {
  94         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  95 }
  96
  97 static enum hns3_evt_cause
  98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  99 {
 100         struct hns3_hw *hw = &hns->hw;
 101         uint32_t vector0_int_stats;
 102         uint32_t cmdq_src_val;
 103         uint32_t hw_err_src_reg;
 104         uint32_t val;
 105         enum hns3_evt_cause ret;
 106
 107         /* fetch the events from their corresponding regs */
 108         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 109         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 110         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 154             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 155                 val = vector0_int_stats | hw_err_src_reg;
 156                 ret = HNS3_VECTOR0_EVENT_ERR;
 157                 goto out;
 158         }
 159
 160         /* check for vector0 mailbox(=CMDQ RX) event source */
 161         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 162                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 163                 val = cmdq_src_val;
 164                 ret = HNS3_VECTOR0_EVENT_MBX;
 165                 goto out;
 166         }
 167
 168         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 169                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 170                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 171         val = vector0_int_stats;
 172         ret = HNS3_VECTOR0_EVENT_OTHER;
 173 out:
 174
 175         if (clearval)
 176                 *clearval = val;
 177         return ret;
 178 }
 179
 180 static void
 181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 182 {
 183         if (event_type == HNS3_VECTOR0_EVENT_RST)
 184                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 185         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 186                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 187 }
 188
 189 static void
 190 hns3_clear_all_event_cause(struct hns3_hw *hw)
 191 {
 192         uint32_t vector0_int_stats;
 193         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 194
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 196                 hns3_warn(hw, "Probe during IMP reset interrupt");
 197
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 199                 hns3_warn(hw, "Probe during Global reset interrupt");
 200
 201         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 202                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 204                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 205         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 206 }
 207
 208 static void
 209 hns3_interrupt_handler(void *param)
 210 {
 211         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 212         struct hns3_adapter *hns = dev->data->dev_private;
 213         struct hns3_hw *hw = &hns->hw;
 214         enum hns3_evt_cause event_cause;
 215         uint32_t clearval = 0;
 216
 217         /* Disable interrupt */
 218         hns3_pf_disable_irq0(hw);
 219
 220         event_cause = hns3_check_event_cause(hns, &clearval);
 221
 222         /* vector 0 interrupt is shared with reset and mailbox source events. */
 223         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 224                 hns3_warn(hw, "Received err interrupt");
 225                 hns3_handle_msix_error(hns, &hw->reset.request);
 226                 hns3_handle_ras_error(hns, &hw->reset.request);
 227                 hns3_schedule_reset(hns);
 228         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 229                 hns3_warn(hw, "Received reset interrupt");
 230                 hns3_schedule_reset(hns);
 231         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 232                 hns3_dev_handle_mbx_msg(hw);
 233         else
 234                 hns3_err(hw, "Received unknown event");
 235
 236         hns3_clear_event_cause(hw, event_cause, clearval);
 237         /* Enable interrupt if it is not cause by reset */
 238         hns3_pf_enable_irq0(hw);
 239 }
 240
 241 static int
 242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 243 {
 244 #define HNS3_VLAN_ID_OFFSET_STEP        160
 245 #define HNS3_VLAN_BYTE_SIZE             8
 246         struct hns3_vlan_filter_pf_cfg_cmd *req;
 247         struct hns3_hw *hw = &hns->hw;
 248         uint8_t vlan_offset_byte_val;
 249         struct hns3_cmd_desc desc;
 250         uint8_t vlan_offset_byte;
 251         uint8_t vlan_offset_base;
 252         int ret;
 253
 254         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 255
 256         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 257         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 258                            HNS3_VLAN_BYTE_SIZE;
 259         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 260
 261         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 262         req->vlan_offset = vlan_offset_base;
 263         req->vlan_cfg = on ? 0 : 1;
 264         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 265
 266         ret = hns3_cmd_send(hw, &desc, 1);
 267         if (ret)
 268                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 269                          vlan_id, ret);
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 276 {
 277         struct hns3_user_vlan_table *vlan_entry;
 278         struct hns3_pf *pf = &hns->pf;
 279
 280         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 281                 if (vlan_entry->vlan_id == vlan_id) {
 282                         if (vlan_entry->hd_tbl_status)
 283                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 284                         LIST_REMOVE(vlan_entry, next);
 285                         rte_free(vlan_entry);
 286                         break;
 287                 }
 288         }
 289 }
 290
 291 static void
 292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 293                         bool writen_to_tbl)
 294 {
 295         struct hns3_user_vlan_table *vlan_entry;
 296         struct hns3_hw *hw = &hns->hw;
 297         struct hns3_pf *pf = &hns->pf;
 298
 299         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 300                 if (vlan_entry->vlan_id == vlan_id)
 301                         return;
 302         }
 303
 304         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 305         if (vlan_entry == NULL) {
 306                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 307                 return;
 308         }
 309
 310         vlan_entry->hd_tbl_status = writen_to_tbl;
 311         vlan_entry->vlan_id = vlan_id;
 312
 313         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 314 }
 315
 316 static int
 317 hns3_restore_vlan_table(struct hns3_adapter *hns)
 318 {
 319         struct hns3_user_vlan_table *vlan_entry;
 320         struct hns3_hw *hw = &hns->hw;
 321         struct hns3_pf *pf = &hns->pf;
 322         uint16_t vlan_id;
 323         int ret = 0;
 324
 325         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 326                 return hns3_vlan_pvid_configure(hns,
 327                                                 hw->port_base_vlan_cfg.pvid, 1);
 328
 329         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 330                 if (vlan_entry->hd_tbl_status) {
 331                         vlan_id = vlan_entry->vlan_id;
 332                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 333                         if (ret)
 334                                 break;
 335                 }
 336         }
 337
 338         return ret;
 339 }
 340
 341 static int
 342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 343 {
 344         struct hns3_hw *hw = &hns->hw;
 345         bool writen_to_tbl = false;
 346         int ret = 0;
 347
 348         /*
 349          * When vlan filter is enabled, hardware regards packets without vlan
 350          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 351          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 352          */
 353         if (on == 0 && vlan_id == 0)
 354                 return 0;
 355
 356         /*
 357          * When port base vlan enabled, we use port base vlan as the vlan
 358          * filter condition. In this case, we don't update vlan filter table
 359          * when user add new vlan or remove exist vlan, just update the
 360          * vlan list. The vlan id in vlan list will be writen in vlan filter
 361          * table until port base vlan disabled
 362          */
 363         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 364                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 365                 writen_to_tbl = true;
 366         }
 367
 368         if (ret == 0) {
 369                 if (on)
 370                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 371                 else
 372                         hns3_rm_dev_vlan_table(hns, vlan_id);
 373         }
 374         return ret;
 375 }
 376
 377 static int
 378 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 379 {
 380         struct hns3_adapter *hns = dev->data->dev_private;
 381         struct hns3_hw *hw = &hns->hw;
 382         int ret;
 383
 384         rte_spinlock_lock(&hw->lock);
 385         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 386         rte_spinlock_unlock(&hw->lock);
 387         return ret;
 388 }
 389
 390 static int
 391 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 392                          uint16_t tpid)
 393 {
 394         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 395         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 396         struct hns3_hw *hw = &hns->hw;
 397         struct hns3_cmd_desc desc;
 398         int ret;
 399
 400         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 401              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 402                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 403                 return -EINVAL;
 404         }
 405
 406         if (tpid != RTE_ETHER_TYPE_VLAN) {
 407                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 408                 return -EINVAL;
 409         }
 410
 411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 412         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 413
 414         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 415                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 416                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 417         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 418                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 419                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 420                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 421                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 422         }
 423
 424         ret = hns3_cmd_send(hw, &desc, 1);
 425         if (ret) {
 426                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 427                          ret);
 428                 return ret;
 429         }
 430
 431         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 432
 433         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 434         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 435         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 436
 437         ret = hns3_cmd_send(hw, &desc, 1);
 438         if (ret)
 439                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 440                          ret);
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 446                    uint16_t tpid)
 447 {
 448         struct hns3_adapter *hns = dev->data->dev_private;
 449         struct hns3_hw *hw = &hns->hw;
 450         int ret;
 451
 452         rte_spinlock_lock(&hw->lock);
 453         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 454         rte_spinlock_unlock(&hw->lock);
 455         return ret;
 456 }
 457
 458 static int
 459 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 460                              struct hns3_rx_vtag_cfg *vcfg)
 461 {
 462         struct hns3_vport_vtag_rx_cfg_cmd *req;
 463         struct hns3_hw *hw = &hns->hw;
 464         struct hns3_cmd_desc desc;
 465         uint16_t vport_id;
 466         uint8_t bitmap;
 467         int ret;
 468
 469         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 470
 471         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 473                      vcfg->strip_tag1_en ? 1 : 0);
 474         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 475                      vcfg->strip_tag2_en ? 1 : 0);
 476         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 477                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 478         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 479                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 480
 481         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 482         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 483                      vcfg->strip_tag1_discard_en ? 1 : 0);
 484         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 485                      vcfg->strip_tag2_discard_en ? 1 : 0);
 486         /*
 487          * In current version VF is not supported when PF is driven by DPDK
 488          * driver, just need to configure parameters for PF vport.
 489          */
 490         vport_id = HNS3_PF_FUNC_ID;
 491         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 492         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 493         req->vf_bitmap[req->vf_offset] = bitmap;
 494
 495         ret = hns3_cmd_send(hw, &desc, 1);
 496         if (ret)
 497                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 498         return ret;
 499 }
 500
 501 static void
 502 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 503                            struct hns3_rx_vtag_cfg *vcfg)
 504 {
 505         struct hns3_pf *pf = &hns->pf;
 506         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 507 }
 508
 509 static void
 510 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 511                            struct hns3_tx_vtag_cfg *vcfg)
 512 {
 513         struct hns3_pf *pf = &hns->pf;
 514         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 515 }
 516
 517 static int
 518 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 519 {
 520         struct hns3_rx_vtag_cfg rxvlan_cfg;
 521         struct hns3_hw *hw = &hns->hw;
 522         int ret;
 523
 524         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 525                 rxvlan_cfg.strip_tag1_en = false;
 526                 rxvlan_cfg.strip_tag2_en = enable;
 527                 rxvlan_cfg.strip_tag2_discard_en = false;
 528         } else {
 529                 rxvlan_cfg.strip_tag1_en = enable;
 530                 rxvlan_cfg.strip_tag2_en = true;
 531                 rxvlan_cfg.strip_tag2_discard_en = true;
 532         }
 533
 534         rxvlan_cfg.strip_tag1_discard_en = false;
 535         rxvlan_cfg.vlan1_vlan_prionly = false;
 536         rxvlan_cfg.vlan2_vlan_prionly = false;
 537         rxvlan_cfg.rx_vlan_offload_en = enable;
 538
 539         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 540         if (ret) {
 541                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 542                 return ret;
 543         }
 544
 545         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 546
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 552                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 553 {
 554         struct hns3_vlan_filter_ctrl_cmd *req;
 555         struct hns3_cmd_desc desc;
 556         int ret;
 557
 558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 559
 560         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 561         req->vlan_type = vlan_type;
 562         req->vlan_fe = filter_en ? fe_type : 0;
 563         req->vf_id = vf_id;
 564
 565         ret = hns3_cmd_send(hw, &desc, 1);
 566         if (ret)
 567                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 568
 569         return ret;
 570 }
 571
 572 static int
 573 hns3_vlan_filter_init(struct hns3_adapter *hns)
 574 {
 575         struct hns3_hw *hw = &hns->hw;
 576         int ret;
 577
 578         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 579                                         HNS3_FILTER_FE_EGRESS, false,
 580                                         HNS3_PF_FUNC_ID);
 581         if (ret) {
 582                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 583                 return ret;
 584         }
 585
 586         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 587                                         HNS3_FILTER_FE_INGRESS, false,
 588                                         HNS3_PF_FUNC_ID);
 589         if (ret)
 590                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 591
 592         return ret;
 593 }
 594
 595 static int
 596 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 597 {
 598         struct hns3_hw *hw = &hns->hw;
 599         int ret;
 600
 601         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 602                                         HNS3_FILTER_FE_INGRESS, enable,
 603                                         HNS3_PF_FUNC_ID);
 604         if (ret)
 605                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 606                          enable ? "enable" : "disable", ret);
 607
 608         return ret;
 609 }
 610
 611 static int
 612 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 613 {
 614         struct hns3_adapter *hns = dev->data->dev_private;
 615         struct hns3_hw *hw = &hns->hw;
 616         struct rte_eth_rxmode *rxmode;
 617         unsigned int tmp_mask;
 618         bool enable;
 619         int ret = 0;
 620
 621         rte_spinlock_lock(&hw->lock);
 622         rxmode = &dev->data->dev_conf.rxmode;
 623         tmp_mask = (unsigned int)mask;
 624         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 625                 /* ignore vlan filter configuration during promiscuous mode */
 626                 if (!dev->data->promiscuous) {
 627                         /* Enable or disable VLAN filter */
 628                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 629                                  true : false;
 630
 631                         ret = hns3_enable_vlan_filter(hns, enable);
 632                         if (ret) {
 633                                 rte_spinlock_unlock(&hw->lock);
 634                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 635                                          enable ? "enable" : "disable", ret);
 636                                 return ret;
 637                         }
 638                 }
 639         }
 640
 641         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 642                 /* Enable or disable VLAN stripping */
 643                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 644                     true : false;
 645
 646                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 647                 if (ret) {
 648                         rte_spinlock_unlock(&hw->lock);
 649                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 650                                  enable ? "enable" : "disable", ret);
 651                         return ret;
 652                 }
 653         }
 654
 655         rte_spinlock_unlock(&hw->lock);
 656
 657         return ret;
 658 }
 659
 660 static int
 661 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 662                              struct hns3_tx_vtag_cfg *vcfg)
 663 {
 664         struct hns3_vport_vtag_tx_cfg_cmd *req;
 665         struct hns3_cmd_desc desc;
 666         struct hns3_hw *hw = &hns->hw;
 667         uint16_t vport_id;
 668         uint8_t bitmap;
 669         int ret;
 670
 671         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 672
 673         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 674         req->def_vlan_tag1 = vcfg->default_tag1;
 675         req->def_vlan_tag2 = vcfg->default_tag2;
 676         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 677                      vcfg->accept_tag1 ? 1 : 0);
 678         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 679                      vcfg->accept_untag1 ? 1 : 0);
 680         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 681                      vcfg->accept_tag2 ? 1 : 0);
 682         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 683                      vcfg->accept_untag2 ? 1 : 0);
 684         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 685                      vcfg->insert_tag1_en ? 1 : 0);
 686         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 687                      vcfg->insert_tag2_en ? 1 : 0);
 688         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 689
 690         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 691         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 692                      vcfg->tag_shift_mode_en ? 1 : 0);
 693
 694         /*
 695          * In current version VF is not supported when PF is driven by DPDK
 696          * driver, just need to configure parameters for PF vport.
 697          */
 698         vport_id = HNS3_PF_FUNC_ID;
 699         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 700         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 701         req->vf_bitmap[req->vf_offset] = bitmap;
 702
 703         ret = hns3_cmd_send(hw, &desc, 1);
 704         if (ret)
 705                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 712                      uint16_t pvid)
 713 {
 714         struct hns3_hw *hw = &hns->hw;
 715         struct hns3_tx_vtag_cfg txvlan_cfg;
 716         int ret;
 717
 718         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 719                 txvlan_cfg.accept_tag1 = true;
 720                 txvlan_cfg.insert_tag1_en = false;
 721                 txvlan_cfg.default_tag1 = 0;
 722         } else {
 723                 txvlan_cfg.accept_tag1 =
 724                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 725                 txvlan_cfg.insert_tag1_en = true;
 726                 txvlan_cfg.default_tag1 = pvid;
 727         }
 728
 729         txvlan_cfg.accept_untag1 = true;
 730         txvlan_cfg.accept_tag2 = true;
 731         txvlan_cfg.accept_untag2 = true;
 732         txvlan_cfg.insert_tag2_en = false;
 733         txvlan_cfg.default_tag2 = 0;
 734         txvlan_cfg.tag_shift_mode_en = true;
 735
 736         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 737         if (ret) {
 738                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 739                          ret);
 740                 return ret;
 741         }
 742
 743         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 744         return ret;
 745 }
 746
 747
 748 static void
 749 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 750 {
 751         struct hns3_user_vlan_table *vlan_entry;
 752         struct hns3_pf *pf = &hns->pf;
 753
 754         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 755                 if (vlan_entry->hd_tbl_status) {
 756                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 757                         vlan_entry->hd_tbl_status = false;
 758                 }
 759         }
 760
 761         if (is_del_list) {
 762                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 763                 while (vlan_entry) {
 764                         LIST_REMOVE(vlan_entry, next);
 765                         rte_free(vlan_entry);
 766                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 767                 }
 768         }
 769 }
 770
 771 static void
 772 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_user_vlan_table *vlan_entry;
 775         struct hns3_pf *pf = &hns->pf;
 776
 777         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 778                 if (!vlan_entry->hd_tbl_status) {
 779                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 780                         vlan_entry->hd_tbl_status = true;
 781                 }
 782         }
 783 }
 784
 785 static void
 786 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 787 {
 788         struct hns3_hw *hw = &hns->hw;
 789         int ret;
 790
 791         hns3_rm_all_vlan_table(hns, true);
 792         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 793                 ret = hns3_set_port_vlan_filter(hns,
 794                                                 hw->port_base_vlan_cfg.pvid, 0);
 795                 if (ret) {
 796                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 797                                  ret);
 798                         return;
 799                 }
 800         }
 801 }
 802
 803 static int
 804 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 805                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 806 {
 807         struct hns3_hw *hw = &hns->hw;
 808         uint16_t old_pvid;
 809         int ret;
 810
 811         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 812                 old_pvid = hw->port_base_vlan_cfg.pvid;
 813                 if (old_pvid != HNS3_INVALID_PVID) {
 814                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 815                         if (ret) {
 816                                 hns3_err(hw, "failed to remove old pvid %u, "
 817                                                 "ret = %d", old_pvid, ret);
 818                                 return ret;
 819                         }
 820                 }
 821
 822                 hns3_rm_all_vlan_table(hns, false);
 823                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 824                 if (ret) {
 825                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 826                                         new_pvid, ret);
 827                         return ret;
 828                 }
 829         } else {
 830                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 831                 if (ret) {
 832                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 833                                         new_pvid, ret);
 834                         return ret;
 835                 }
 836
 837                 hns3_add_all_vlan_table(hns);
 838         }
 839         return 0;
 840 }
 841
 842 static int
 843 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 844 {
 845         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 846         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 847         bool rx_strip_en;
 848         int ret;
 849
 850         rx_strip_en = old_cfg->rx_vlan_offload_en;
 851         if (on) {
 852                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 853                 rx_vlan_cfg.strip_tag2_en = true;
 854                 rx_vlan_cfg.strip_tag2_discard_en = true;
 855         } else {
 856                 rx_vlan_cfg.strip_tag1_en = false;
 857                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 858                 rx_vlan_cfg.strip_tag2_discard_en = false;
 859         }
 860         rx_vlan_cfg.strip_tag1_discard_en = false;
 861         rx_vlan_cfg.vlan1_vlan_prionly = false;
 862         rx_vlan_cfg.vlan2_vlan_prionly = false;
 863         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 864
 865         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 866         if (ret)
 867                 return ret;
 868
 869         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 870         return ret;
 871 }
 872
 873 static int
 874 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 875 {
 876         struct hns3_hw *hw = &hns->hw;
 877         uint16_t port_base_vlan_state;
 878         int ret;
 879
 880         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 881                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 882                         hns3_warn(hw, "Invalid operation! As current pvid set "
 883                                   "is %u, disable pvid %u is invalid",
 884                                   hw->port_base_vlan_cfg.pvid, pvid);
 885                 return 0;
 886         }
 887
 888         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 889                                     HNS3_PORT_BASE_VLAN_DISABLE;
 890         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 891         if (ret) {
 892                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 893                          ret);
 894                 return ret;
 895         }
 896
 897         ret = hns3_en_pvid_strip(hns, on);
 898         if (ret) {
 899                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 900                          "ret = %d", ret);
 901                 return ret;
 902         }
 903
 904         if (pvid == HNS3_INVALID_PVID)
 905                 goto out;
 906         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 907         if (ret) {
 908                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 909                          ret);
 910                 return ret;
 911         }
 912
 913 out:
 914         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 915         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 916         return ret;
 917 }
 918
 919 static int
 920 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 921 {
 922         struct hns3_adapter *hns = dev->data->dev_private;
 923         struct hns3_hw *hw = &hns->hw;
 924         bool pvid_en_state_change;
 925         uint16_t pvid_state;
 926         int ret;
 927
 928         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 929                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 930                          RTE_ETHER_MAX_VLAN_ID);
 931                 return -EINVAL;
 932         }
 933
 934         /*
 935          * If PVID configuration state change, should refresh the PVID
 936          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 937          */
 938         pvid_state = hw->port_base_vlan_cfg.state;
 939         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 940             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 941                 pvid_en_state_change = false;
 942         else
 943                 pvid_en_state_change = true;
 944
 945         rte_spinlock_lock(&hw->lock);
 946         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 947         rte_spinlock_unlock(&hw->lock);
 948         if (ret)
 949                 return ret;
 950         /*
 951          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 952          * need be processed by PMD driver.
 953          */
 954         if (pvid_en_state_change &&
 955             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 956                 hns3_update_all_queues_pvid_proc_en(hw);
 957
 958         return 0;
 959 }
 960
 961 static int
 962 hns3_default_vlan_config(struct hns3_adapter *hns)
 963 {
 964         struct hns3_hw *hw = &hns->hw;
 965         int ret;
 966
 967         /*
 968          * When vlan filter is enabled, hardware regards packets without vlan
 969          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
 970          * table, packets without vlan won't be received. So, add vlan 0 as
 971          * the default vlan.
 972          */
 973         ret = hns3_vlan_filter_configure(hns, 0, 1);
 974         if (ret)
 975                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_init_vlan_config(struct hns3_adapter *hns)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         int ret;
 984
 985         /*
 986          * This function can be called in the initialization and reset process,
 987          * when in reset process, it means that hardware had been reseted
 988          * successfully and we need to restore the hardware configuration to
 989          * ensure that the hardware configuration remains unchanged before and
 990          * after reset.
 991          */
 992         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 993                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 994                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
 995         }
 996
 997         ret = hns3_vlan_filter_init(hns);
 998         if (ret) {
 999                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1004                                        RTE_ETHER_TYPE_VLAN);
1005         if (ret) {
1006                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1007                 return ret;
1008         }
1009
1010         /*
1011          * When in the reinit dev stage of the reset process, the following
1012          * vlan-related configurations may differ from those at initialization,
1013          * we will restore configurations to hardware in hns3_restore_vlan_table
1014          * and hns3_restore_vlan_conf later.
1015          */
1016         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1017                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1018                 if (ret) {
1019                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1020                         return ret;
1021                 }
1022
1023                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1024                 if (ret) {
1025                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1026                                  ret);
1027                         return ret;
1028                 }
1029         }
1030
1031         return hns3_default_vlan_config(hns);
1032 }
1033
1034 static int
1035 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1036 {
1037         struct hns3_pf *pf = &hns->pf;
1038         struct hns3_hw *hw = &hns->hw;
1039         uint64_t offloads;
1040         bool enable;
1041         int ret;
1042
1043         if (!hw->data->promiscuous) {
1044                 /* restore vlan filter states */
1045                 offloads = hw->data->dev_conf.rxmode.offloads;
1046                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1047                 ret = hns3_enable_vlan_filter(hns, enable);
1048                 if (ret) {
1049                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1050                                  "ret = %d", ret);
1051                         return ret;
1052                 }
1053         }
1054
1055         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1056         if (ret) {
1057                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1058                 return ret;
1059         }
1060
1061         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1062         if (ret)
1063                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1064
1065         return ret;
1066 }
1067
1068 static int
1069 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1070 {
1071         struct hns3_adapter *hns = dev->data->dev_private;
1072         struct rte_eth_dev_data *data = dev->data;
1073         struct rte_eth_txmode *txmode;
1074         struct hns3_hw *hw = &hns->hw;
1075         int mask;
1076         int ret;
1077
1078         txmode = &data->dev_conf.txmode;
1079         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1080                 hns3_warn(hw,
1081                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1082                           "configuration is not supported! Ignore these two "
1083                           "parameters: hw_vlan_reject_tagged(%d), "
1084                           "hw_vlan_reject_untagged(%d)",
1085                           txmode->hw_vlan_reject_tagged,
1086                           txmode->hw_vlan_reject_untagged);
1087
1088         /* Apply vlan offload setting */
1089         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1090         ret = hns3_vlan_offload_set(dev, mask);
1091         if (ret) {
1092                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1093                          ret);
1094                 return ret;
1095         }
1096
1097         /*
1098          * If pvid config is not set in rte_eth_conf, driver needn't to set
1099          * VLAN pvid related configuration to hardware.
1100          */
1101         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1102                 return 0;
1103
1104         /* Apply pvid setting */
1105         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1106                                  txmode->hw_vlan_insert_pvid);
1107         if (ret)
1108                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1109                          txmode->pvid, ret);
1110
1111         return ret;
1112 }
1113
1114 static int
1115 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1116                 unsigned int tso_mss_max)
1117 {
1118         struct hns3_cfg_tso_status_cmd *req;
1119         struct hns3_cmd_desc desc;
1120         uint16_t tso_mss;
1121
1122         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1123
1124         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1125
1126         tso_mss = 0;
1127         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1128                        tso_mss_min);
1129         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1130
1131         tso_mss = 0;
1132         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1133                        tso_mss_max);
1134         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1135
1136         return hns3_cmd_send(hw, &desc, 1);
1137 }
1138
1139 static int
1140 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1141                    uint16_t *allocated_size, bool is_alloc)
1142 {
1143         struct hns3_umv_spc_alc_cmd *req;
1144         struct hns3_cmd_desc desc;
1145         int ret;
1146
1147         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1148         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1149         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1150         req->space_size = rte_cpu_to_le_32(space_size);
1151
1152         ret = hns3_cmd_send(hw, &desc, 1);
1153         if (ret) {
1154                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1155                              is_alloc ? "allocate" : "free", ret);
1156                 return ret;
1157         }
1158
1159         if (is_alloc && allocated_size)
1160                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1161
1162         return 0;
1163 }
1164
1165 static int
1166 hns3_init_umv_space(struct hns3_hw *hw)
1167 {
1168         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169         struct hns3_pf *pf = &hns->pf;
1170         uint16_t allocated_size = 0;
1171         int ret;
1172
1173         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1174                                  true);
1175         if (ret)
1176                 return ret;
1177
1178         if (allocated_size < pf->wanted_umv_size)
1179                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1180                              pf->wanted_umv_size, allocated_size);
1181
1182         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1183                                                 pf->wanted_umv_size;
1184         pf->used_umv_size = 0;
1185         return 0;
1186 }
1187
1188 static int
1189 hns3_uninit_umv_space(struct hns3_hw *hw)
1190 {
1191         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1192         struct hns3_pf *pf = &hns->pf;
1193         int ret;
1194
1195         if (pf->max_umv_size == 0)
1196                 return 0;
1197
1198         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1199         if (ret)
1200                 return ret;
1201
1202         pf->max_umv_size = 0;
1203
1204         return 0;
1205 }
1206
1207 static bool
1208 hns3_is_umv_space_full(struct hns3_hw *hw)
1209 {
1210         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1211         struct hns3_pf *pf = &hns->pf;
1212         bool is_full;
1213
1214         is_full = (pf->used_umv_size >= pf->max_umv_size);
1215
1216         return is_full;
1217 }
1218
1219 static void
1220 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1221 {
1222         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1223         struct hns3_pf *pf = &hns->pf;
1224
1225         if (is_free) {
1226                 if (pf->used_umv_size > 0)
1227                         pf->used_umv_size--;
1228         } else
1229                 pf->used_umv_size++;
1230 }
1231
1232 static void
1233 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1234                       const uint8_t *addr, bool is_mc)
1235 {
1236         const unsigned char *mac_addr = addr;
1237         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1238                             ((uint32_t)mac_addr[2] << 16) |
1239                             ((uint32_t)mac_addr[1] << 8) |
1240                             (uint32_t)mac_addr[0];
1241         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1242
1243         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1244         if (is_mc) {
1245                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1246                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1247                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1248         }
1249
1250         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1251         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1252 }
1253
1254 static int
1255 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1256                              uint8_t resp_code,
1257                              enum hns3_mac_vlan_tbl_opcode op)
1258 {
1259         if (cmdq_resp) {
1260                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1261                          cmdq_resp);
1262                 return -EIO;
1263         }
1264
1265         if (op == HNS3_MAC_VLAN_ADD) {
1266                 if (resp_code == 0 || resp_code == 1) {
1267                         return 0;
1268                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1269                         hns3_err(hw, "add mac addr failed for uc_overflow");
1270                         return -ENOSPC;
1271                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1272                         hns3_err(hw, "add mac addr failed for mc_overflow");
1273                         return -ENOSPC;
1274                 }
1275
1276                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1277                          resp_code);
1278                 return -EIO;
1279         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1280                 if (resp_code == 0) {
1281                         return 0;
1282                 } else if (resp_code == 1) {
1283                         hns3_dbg(hw, "remove mac addr failed for miss");
1284                         return -ENOENT;
1285                 }
1286
1287                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1288                          resp_code);
1289                 return -EIO;
1290         } else if (op == HNS3_MAC_VLAN_LKUP) {
1291                 if (resp_code == 0) {
1292                         return 0;
1293                 } else if (resp_code == 1) {
1294                         hns3_dbg(hw, "lookup mac addr failed for miss");
1295                         return -ENOENT;
1296                 }
1297
1298                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1299                          resp_code);
1300                 return -EIO;
1301         }
1302
1303         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1304                  op);
1305
1306         return -EINVAL;
1307 }
1308
1309 static int
1310 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1311                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1312                          struct hns3_cmd_desc *desc, bool is_mc)
1313 {
1314         uint8_t resp_code;
1315         uint16_t retval;
1316         int ret;
1317
1318         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1319         if (is_mc) {
1320                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1321                 memcpy(desc[0].data, req,
1322                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1324                                           true);
1325                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1326                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1327                                           true);
1328                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1329         } else {
1330                 memcpy(desc[0].data, req,
1331                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1332                 ret = hns3_cmd_send(hw, desc, 1);
1333         }
1334         if (ret) {
1335                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1336                          ret);
1337                 return ret;
1338         }
1339         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1340         retval = rte_le_to_cpu_16(desc[0].retval);
1341
1342         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343                                             HNS3_MAC_VLAN_LKUP);
1344 }
1345
1346 static int
1347 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1348                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1349                       struct hns3_cmd_desc *mc_desc)
1350 {
1351         uint8_t resp_code;
1352         uint16_t retval;
1353         int cfg_status;
1354         int ret;
1355
1356         if (mc_desc == NULL) {
1357                 struct hns3_cmd_desc desc;
1358
1359                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1360                 memcpy(desc.data, req,
1361                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362                 ret = hns3_cmd_send(hw, &desc, 1);
1363                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1364                 retval = rte_le_to_cpu_16(desc.retval);
1365
1366                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1367                                                           HNS3_MAC_VLAN_ADD);
1368         } else {
1369                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1370                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1372                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1373                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1374                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1375                 memcpy(mc_desc[0].data, req,
1376                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1377                 mc_desc[0].retval = 0;
1378                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1380                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1381
1382                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1383                                                           HNS3_MAC_VLAN_ADD);
1384         }
1385
1386         if (ret) {
1387                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1388                 return ret;
1389         }
1390
1391         return cfg_status;
1392 }
1393
1394 static int
1395 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1396                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1397 {
1398         struct hns3_cmd_desc desc;
1399         uint8_t resp_code;
1400         uint16_t retval;
1401         int ret;
1402
1403         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1404
1405         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1406
1407         ret = hns3_cmd_send(hw, &desc, 1);
1408         if (ret) {
1409                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1410                 return ret;
1411         }
1412         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1413         retval = rte_le_to_cpu_16(desc.retval);
1414
1415         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1416                                             HNS3_MAC_VLAN_REMOVE);
1417 }
1418
1419 static int
1420 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1421 {
1422         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1423         struct hns3_mac_vlan_tbl_entry_cmd req;
1424         struct hns3_pf *pf = &hns->pf;
1425         struct hns3_cmd_desc desc[3];
1426         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1427         uint16_t egress_port = 0;
1428         uint8_t vf_id;
1429         int ret;
1430
1431         /* check if mac addr is valid */
1432         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1433                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1434                                       mac_addr);
1435                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1436                          mac_str);
1437                 return -EINVAL;
1438         }
1439
1440         memset(&req, 0, sizeof(req));
1441
1442         /*
1443          * In current version VF is not supported when PF is driven by DPDK
1444          * driver, just need to configure parameters for PF vport.
1445          */
1446         vf_id = HNS3_PF_FUNC_ID;
1447         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1448                        HNS3_MAC_EPORT_VFID_S, vf_id);
1449
1450         req.egress_port = rte_cpu_to_le_16(egress_port);
1451
1452         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1453
1454         /*
1455          * Lookup the mac address in the mac_vlan table, and add
1456          * it if the entry is inexistent. Repeated unicast entry
1457          * is not allowed in the mac vlan table.
1458          */
1459         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1460         if (ret == -ENOENT) {
1461                 if (!hns3_is_umv_space_full(hw)) {
1462                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1463                         if (!ret)
1464                                 hns3_update_umv_space(hw, false);
1465                         return ret;
1466                 }
1467
1468                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1469
1470                 return -ENOSPC;
1471         }
1472
1473         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1474
1475         /* check if we just hit the duplicate */
1476         if (ret == 0) {
1477                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1478                 return 0;
1479         }
1480
1481         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1482                  mac_str);
1483
1484         return ret;
1485 }
1486
1487 static int
1488 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1489 {
1490         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1491         struct rte_ether_addr *addr;
1492         int ret;
1493         int i;
1494
1495         for (i = 0; i < hw->mc_addrs_num; i++) {
1496                 addr = &hw->mc_addrs[i];
1497                 /* Check if there are duplicate addresses */
1498                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1499                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1500                                               addr);
1501                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1502                                  "(%s) is added by the set_mc_mac_addr_list "
1503                                  "API", mac_str);
1504                         return -EINVAL;
1505                 }
1506         }
1507
1508         ret = hns3_add_mc_addr(hw, mac_addr);
1509         if (ret) {
1510                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1511                                       mac_addr);
1512                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1513                          mac_str, ret);
1514         }
1515         return ret;
1516 }
1517
1518 static int
1519 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1520 {
1521         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1522         int ret;
1523
1524         ret = hns3_remove_mc_addr(hw, mac_addr);
1525         if (ret) {
1526                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1527                                       mac_addr);
1528                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1529                          mac_str, ret);
1530         }
1531         return ret;
1532 }
1533
1534 static int
1535 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1536                   uint32_t idx, __rte_unused uint32_t pool)
1537 {
1538         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1540         int ret;
1541
1542         rte_spinlock_lock(&hw->lock);
1543
1544         /*
1545          * In hns3 network engine adding UC and MC mac address with different
1546          * commands with firmware. We need to determine whether the input
1547          * address is a UC or a MC address to call different commands.
1548          * By the way, it is recommended calling the API function named
1549          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1550          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1551          * may affect the specifications of UC mac addresses.
1552          */
1553         if (rte_is_multicast_ether_addr(mac_addr))
1554                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1555         else
1556                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1557
1558         if (ret) {
1559                 rte_spinlock_unlock(&hw->lock);
1560                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1563                          ret);
1564                 return ret;
1565         }
1566
1567         if (idx == 0)
1568                 hw->mac.default_addr_setted = true;
1569         rte_spinlock_unlock(&hw->lock);
1570
1571         return ret;
1572 }
1573
1574 static int
1575 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1576 {
1577         struct hns3_mac_vlan_tbl_entry_cmd req;
1578         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1579         int ret;
1580
1581         /* check if mac addr is valid */
1582         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1583                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1584                                       mac_addr);
1585                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1586                          mac_str);
1587                 return -EINVAL;
1588         }
1589
1590         memset(&req, 0, sizeof(req));
1591         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1592         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1593         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1594         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1595                 return 0;
1596         else if (ret == 0)
1597                 hns3_update_umv_space(hw, true);
1598
1599         return ret;
1600 }
1601
1602 static void
1603 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1604 {
1605         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         /* index will be checked by upper level rte interface */
1607         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1608         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609         int ret;
1610
1611         rte_spinlock_lock(&hw->lock);
1612
1613         if (rte_is_multicast_ether_addr(mac_addr))
1614                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1615         else
1616                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1617         rte_spinlock_unlock(&hw->lock);
1618         if (ret) {
1619                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                       mac_addr);
1621                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1622                          ret);
1623         }
1624 }
1625
1626 static int
1627 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1628                           struct rte_ether_addr *mac_addr)
1629 {
1630         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct rte_ether_addr *oaddr;
1632         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1633         bool default_addr_setted;
1634         bool rm_succes = false;
1635         int ret, ret_val;
1636
1637         /*
1638          * It has been guaranteed that input parameter named mac_addr is valid
1639          * address in the rte layer of DPDK framework.
1640          */
1641         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1642         default_addr_setted = hw->mac.default_addr_setted;
1643         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1644                 return 0;
1645
1646         rte_spinlock_lock(&hw->lock);
1647         if (default_addr_setted) {
1648                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1649                 if (ret) {
1650                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1651                                               oaddr);
1652                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1653                                   mac_str, ret);
1654                         rm_succes = false;
1655                 } else
1656                         rm_succes = true;
1657         }
1658
1659         ret = hns3_add_uc_addr_common(hw, mac_addr);
1660         if (ret) {
1661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1662                                       mac_addr);
1663                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1664                 goto err_add_uc_addr;
1665         }
1666
1667         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1668         if (ret) {
1669                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1670                 goto err_pause_addr_cfg;
1671         }
1672
1673         rte_ether_addr_copy(mac_addr,
1674                             (struct rte_ether_addr *)hw->mac.mac_addr);
1675         hw->mac.default_addr_setted = true;
1676         rte_spinlock_unlock(&hw->lock);
1677
1678         return 0;
1679
1680 err_pause_addr_cfg:
1681         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1682         if (ret_val) {
1683                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1684                                       mac_addr);
1685                 hns3_warn(hw,
1686                           "Failed to roll back to del setted mac addr(%s): %d",
1687                           mac_str, ret_val);
1688         }
1689
1690 err_add_uc_addr:
1691         if (rm_succes) {
1692                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1693                 if (ret_val) {
1694                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1695                                               oaddr);
1696                         hns3_warn(hw,
1697                                   "Failed to restore old uc mac addr(%s): %d",
1698                                   mac_str, ret_val);
1699                         hw->mac.default_addr_setted = false;
1700                 }
1701         }
1702         rte_spinlock_unlock(&hw->lock);
1703
1704         return ret;
1705 }
1706
1707 static int
1708 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1709 {
1710         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1711         struct hns3_hw *hw = &hns->hw;
1712         struct rte_ether_addr *addr;
1713         int err = 0;
1714         int ret;
1715         int i;
1716
1717         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1718                 addr = &hw->data->mac_addrs[i];
1719                 if (rte_is_zero_ether_addr(addr))
1720                         continue;
1721                 if (rte_is_multicast_ether_addr(addr))
1722                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1723                               hns3_add_mc_addr(hw, addr);
1724                 else
1725                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1726                               hns3_add_uc_addr_common(hw, addr);
1727
1728                 if (ret) {
1729                         err = ret;
1730                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1731                                               addr);
1732                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1733                                  "ret = %d.", del ? "remove" : "restore",
1734                                  mac_str, i, ret);
1735                 }
1736         }
1737         return err;
1738 }
1739
1740 static void
1741 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1742 {
1743 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1744         uint8_t word_num;
1745         uint8_t bit_num;
1746
1747         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1748                 word_num = vfid / 32;
1749                 bit_num = vfid % 32;
1750                 if (clr)
1751                         desc[1].data[word_num] &=
1752                             rte_cpu_to_le_32(~(1UL << bit_num));
1753                 else
1754                         desc[1].data[word_num] |=
1755                             rte_cpu_to_le_32(1UL << bit_num);
1756         } else {
1757                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1758                 bit_num = vfid % 32;
1759                 if (clr)
1760                         desc[2].data[word_num] &=
1761                             rte_cpu_to_le_32(~(1UL << bit_num));
1762                 else
1763                         desc[2].data[word_num] |=
1764                             rte_cpu_to_le_32(1UL << bit_num);
1765         }
1766 }
1767
1768 static int
1769 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1770 {
1771         struct hns3_mac_vlan_tbl_entry_cmd req;
1772         struct hns3_cmd_desc desc[3];
1773         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1774         uint8_t vf_id;
1775         int ret;
1776
1777         /* Check if mac addr is valid */
1778         if (!rte_is_multicast_ether_addr(mac_addr)) {
1779                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780                                       mac_addr);
1781                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1782                          mac_str);
1783                 return -EINVAL;
1784         }
1785
1786         memset(&req, 0, sizeof(req));
1787         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1788         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1789         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1790         if (ret) {
1791                 /* This mac addr do not exist, add new entry for it */
1792                 memset(desc[0].data, 0, sizeof(desc[0].data));
1793                 memset(desc[1].data, 0, sizeof(desc[0].data));
1794                 memset(desc[2].data, 0, sizeof(desc[0].data));
1795         }
1796
1797         /*
1798          * In current version VF is not supported when PF is driven by DPDK
1799          * driver, just need to configure parameters for PF vport.
1800          */
1801         vf_id = HNS3_PF_FUNC_ID;
1802         hns3_update_desc_vfid(desc, vf_id, false);
1803         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1804         if (ret) {
1805                 if (ret == -ENOSPC)
1806                         hns3_err(hw, "mc mac vlan table is full");
1807                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1808                                       mac_addr);
1809                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1810         }
1811
1812         return ret;
1813 }
1814
1815 static int
1816 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1817 {
1818         struct hns3_mac_vlan_tbl_entry_cmd req;
1819         struct hns3_cmd_desc desc[3];
1820         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1821         uint8_t vf_id;
1822         int ret;
1823
1824         /* Check if mac addr is valid */
1825         if (!rte_is_multicast_ether_addr(mac_addr)) {
1826                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1827                                       mac_addr);
1828                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1829                          mac_str);
1830                 return -EINVAL;
1831         }
1832
1833         memset(&req, 0, sizeof(req));
1834         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1835         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1836         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1837         if (ret == 0) {
1838                 /*
1839                  * This mac addr exist, remove this handle's VFID for it.
1840                  * In current version VF is not supported when PF is driven by
1841                  * DPDK driver, just need to configure parameters for PF vport.
1842                  */
1843                 vf_id = HNS3_PF_FUNC_ID;
1844                 hns3_update_desc_vfid(desc, vf_id, true);
1845
1846                 /* All the vfid is zero, so need to delete this entry */
1847                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1848         } else if (ret == -ENOENT) {
1849                 /* This mac addr doesn't exist. */
1850                 return 0;
1851         }
1852
1853         if (ret) {
1854                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1855                                       mac_addr);
1856                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1857         }
1858
1859         return ret;
1860 }
1861
1862 static int
1863 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1864                            struct rte_ether_addr *mc_addr_set,
1865                            uint32_t nb_mc_addr)
1866 {
1867         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1868         struct rte_ether_addr *addr;
1869         uint32_t i;
1870         uint32_t j;
1871
1872         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1873                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1874                          "invalid. valid range: 0~%d",
1875                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1876                 return -EINVAL;
1877         }
1878
1879         /* Check if input mac addresses are valid */
1880         for (i = 0; i < nb_mc_addr; i++) {
1881                 addr = &mc_addr_set[i];
1882                 if (!rte_is_multicast_ether_addr(addr)) {
1883                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1884                                               addr);
1885                         hns3_err(hw,
1886                                  "failed to set mc mac addr, addr(%s) invalid.",
1887                                  mac_str);
1888                         return -EINVAL;
1889                 }
1890
1891                 /* Check if there are duplicate addresses */
1892                 for (j = i + 1; j < nb_mc_addr; j++) {
1893                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1894                                 rte_ether_format_addr(mac_str,
1895                                                       RTE_ETHER_ADDR_FMT_SIZE,
1896                                                       addr);
1897                                 hns3_err(hw, "failed to set mc mac addr, "
1898                                          "addrs invalid. two same addrs(%s).",
1899                                          mac_str);
1900                                 return -EINVAL;
1901                         }
1902                 }
1903
1904                 /*
1905                  * Check if there are duplicate addresses between mac_addrs
1906                  * and mc_addr_set
1907                  */
1908                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1909                         if (rte_is_same_ether_addr(addr,
1910                                                    &hw->data->mac_addrs[j])) {
1911                                 rte_ether_format_addr(mac_str,
1912                                                       RTE_ETHER_ADDR_FMT_SIZE,
1913                                                       addr);
1914                                 hns3_err(hw, "failed to set mc mac addr, "
1915                                          "addrs invalid. addrs(%s) has already "
1916                                          "configured in mac_addr add API",
1917                                          mac_str);
1918                                 return -EINVAL;
1919                         }
1920                 }
1921         }
1922
1923         return 0;
1924 }
1925
1926 static void
1927 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1928                            struct rte_ether_addr *mc_addr_set,
1929                            int mc_addr_num,
1930                            struct rte_ether_addr *reserved_addr_list,
1931                            int *reserved_addr_num,
1932                            struct rte_ether_addr *add_addr_list,
1933                            int *add_addr_num,
1934                            struct rte_ether_addr *rm_addr_list,
1935                            int *rm_addr_num)
1936 {
1937         struct rte_ether_addr *addr;
1938         int current_addr_num;
1939         int reserved_num = 0;
1940         int add_num = 0;
1941         int rm_num = 0;
1942         int num;
1943         int i;
1944         int j;
1945         bool same_addr;
1946
1947         /* Calculate the mc mac address list that should be removed */
1948         current_addr_num = hw->mc_addrs_num;
1949         for (i = 0; i < current_addr_num; i++) {
1950                 addr = &hw->mc_addrs[i];
1951                 same_addr = false;
1952                 for (j = 0; j < mc_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1961                         rm_num++;
1962                 } else {
1963                         rte_ether_addr_copy(addr,
1964                                             &reserved_addr_list[reserved_num]);
1965                         reserved_num++;
1966                 }
1967         }
1968
1969         /* Calculate the mc mac address list that should be added */
1970         for (i = 0; i < mc_addr_num; i++) {
1971                 addr = &mc_addr_set[i];
1972                 same_addr = false;
1973                 for (j = 0; j < current_addr_num; j++) {
1974                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1975                                 same_addr = true;
1976                                 break;
1977                         }
1978                 }
1979
1980                 if (!same_addr) {
1981                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1982                         add_num++;
1983                 }
1984         }
1985
1986         /* Reorder the mc mac address list maintained by driver */
1987         for (i = 0; i < reserved_num; i++)
1988                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1989
1990         for (i = 0; i < rm_num; i++) {
1991                 num = reserved_num + i;
1992                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1993         }
1994
1995         *reserved_addr_num = reserved_num;
1996         *add_addr_num = add_num;
1997         *rm_addr_num = rm_num;
1998 }
1999
2000 static int
2001 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2002                           struct rte_ether_addr *mc_addr_set,
2003                           uint32_t nb_mc_addr)
2004 {
2005         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2007         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2008         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2009         struct rte_ether_addr *addr;
2010         int reserved_addr_num;
2011         int add_addr_num;
2012         int rm_addr_num;
2013         int mc_addr_num;
2014         int num;
2015         int ret;
2016         int i;
2017
2018         /* Check if input parameters are valid */
2019         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2020         if (ret)
2021                 return ret;
2022
2023         rte_spinlock_lock(&hw->lock);
2024
2025         /*
2026          * Calculate the mc mac address lists those should be removed and be
2027          * added, Reorder the mc mac address list maintained by driver.
2028          */
2029         mc_addr_num = (int)nb_mc_addr;
2030         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2031                                    reserved_addr_list, &reserved_addr_num,
2032                                    add_addr_list, &add_addr_num,
2033                                    rm_addr_list, &rm_addr_num);
2034
2035         /* Remove mc mac addresses */
2036         for (i = 0; i < rm_addr_num; i++) {
2037                 num = rm_addr_num - i - 1;
2038                 addr = &rm_addr_list[num];
2039                 ret = hns3_remove_mc_addr(hw, addr);
2040                 if (ret) {
2041                         rte_spinlock_unlock(&hw->lock);
2042                         return ret;
2043                 }
2044                 hw->mc_addrs_num--;
2045         }
2046
2047         /* Add mc mac addresses */
2048         for (i = 0; i < add_addr_num; i++) {
2049                 addr = &add_addr_list[i];
2050                 ret = hns3_add_mc_addr(hw, addr);
2051                 if (ret) {
2052                         rte_spinlock_unlock(&hw->lock);
2053                         return ret;
2054                 }
2055
2056                 num = reserved_addr_num + i;
2057                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2058                 hw->mc_addrs_num++;
2059         }
2060         rte_spinlock_unlock(&hw->lock);
2061
2062         return 0;
2063 }
2064
2065 static int
2066 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2067 {
2068         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2069         struct hns3_hw *hw = &hns->hw;
2070         struct rte_ether_addr *addr;
2071         int err = 0;
2072         int ret;
2073         int i;
2074
2075         for (i = 0; i < hw->mc_addrs_num; i++) {
2076                 addr = &hw->mc_addrs[i];
2077                 if (!rte_is_multicast_ether_addr(addr))
2078                         continue;
2079                 if (del)
2080                         ret = hns3_remove_mc_addr(hw, addr);
2081                 else
2082                         ret = hns3_add_mc_addr(hw, addr);
2083                 if (ret) {
2084                         err = ret;
2085                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2086                                               addr);
2087                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2088                                  del ? "Remove" : "Restore", mac_str, ret);
2089                 }
2090         }
2091         return err;
2092 }
2093
2094 static int
2095 hns3_check_mq_mode(struct rte_eth_dev *dev)
2096 {
2097         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2098         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2099         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2102         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2103         uint8_t num_tc;
2104         int max_tc = 0;
2105         int i;
2106
2107         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2108         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2109
2110         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2111                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2112                          "rx_mq_mode = %d", rx_mq_mode);
2113                 return -EINVAL;
2114         }
2115
2116         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2117             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2118                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2119                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2120                          rx_mq_mode, tx_mq_mode);
2121                 return -EINVAL;
2122         }
2123
2124         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2125                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2126                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2127                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2128                         return -EINVAL;
2129                 }
2130
2131                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2132                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2133                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2134                                  "nb_tcs(%d) != %d or %d in rx direction.",
2135                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2136                         return -EINVAL;
2137                 }
2138
2139                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2140                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2141                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2142                         return -EINVAL;
2143                 }
2144
2145                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2146                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2147                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2148                                          "is not equal to one in tx direction.",
2149                                          i, dcb_rx_conf->dcb_tc[i]);
2150                                 return -EINVAL;
2151                         }
2152                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2153                                 max_tc = dcb_rx_conf->dcb_tc[i];
2154                 }
2155
2156                 num_tc = max_tc + 1;
2157                 if (num_tc > dcb_rx_conf->nb_tcs) {
2158                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2159                                  num_tc, dcb_rx_conf->nb_tcs);
2160                         return -EINVAL;
2161                 }
2162         }
2163
2164         return 0;
2165 }
2166
2167 static int
2168 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2169 {
2170         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171
2172         if (!hns3_dev_dcb_supported(hw)) {
2173                 hns3_err(hw, "this port does not support dcb configurations.");
2174                 return -EOPNOTSUPP;
2175         }
2176
2177         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2178                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2179                 return -EOPNOTSUPP;
2180         }
2181
2182         /* Check multiple queue mode */
2183         return hns3_check_mq_mode(dev);
2184 }
2185
2186 static int
2187 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2188                            enum hns3_ring_type queue_type, uint16_t queue_id)
2189 {
2190         struct hns3_cmd_desc desc;
2191         struct hns3_ctrl_vector_chain_cmd *req =
2192                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2193         enum hns3_cmd_status status;
2194         enum hns3_opcode_type op;
2195         uint16_t tqp_type_and_id = 0;
2196         const char *op_str;
2197         uint16_t type;
2198         uint16_t gl;
2199
2200         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2201         hns3_cmd_setup_basic_desc(&desc, op, false);
2202         req->int_vector_id = vector_id;
2203
2204         if (queue_type == HNS3_RING_TYPE_RX)
2205                 gl = HNS3_RING_GL_RX;
2206         else
2207                 gl = HNS3_RING_GL_TX;
2208
2209         type = queue_type;
2210
2211         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2212                        type);
2213         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2214         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2215                        gl);
2216         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2217         req->int_cause_num = 1;
2218         op_str = mmap ? "Map" : "Unmap";
2219         status = hns3_cmd_send(hw, &desc, 1);
2220         if (status) {
2221                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2222                          op_str, queue_id, req->int_vector_id, status);
2223                 return status;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int
2230 hns3_init_ring_with_vector(struct hns3_hw *hw)
2231 {
2232         uint16_t vec;
2233         int ret;
2234         int i;
2235
2236         /*
2237          * In hns3 network engine, vector 0 is always the misc interrupt of this
2238          * function, vector 1~N can be used respectively for the queues of the
2239          * function. Tx and Rx queues with the same number share the interrupt
2240          * vector. In the initialization clearing the all hardware mapping
2241          * relationship configurations between queues and interrupt vectors is
2242          * needed, so some error caused by the residual configurations, such as
2243          * the unexpected Tx interrupt, can be avoid.
2244          */
2245         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2246         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2247                 vec = vec - 1; /* the last interrupt is reserved */
2248         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2249         for (i = 0; i < hw->intr_tqps_num; i++) {
2250                 /*
2251                  * Set gap limiter/rate limiter/quanity limiter algorithm
2252                  * configuration for interrupt coalesce of queue's interrupt.
2253                  */
2254                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2255                                        HNS3_TQP_INTR_GL_DEFAULT);
2256                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2257                                        HNS3_TQP_INTR_GL_DEFAULT);
2258                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2259                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2260
2261                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2262                                                  HNS3_RING_TYPE_TX, i);
2263                 if (ret) {
2264                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2265                                           "vector: %d, ret=%d", i, vec, ret);
2266                         return ret;
2267                 }
2268
2269                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2270                                                  HNS3_RING_TYPE_RX, i);
2271                 if (ret) {
2272                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2273                                           "vector: %d, ret=%d", i, vec, ret);
2274                         return ret;
2275                 }
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int
2282 hns3_dev_configure(struct rte_eth_dev *dev)
2283 {
2284         struct hns3_adapter *hns = dev->data->dev_private;
2285         struct rte_eth_conf *conf = &dev->data->dev_conf;
2286         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2287         struct hns3_hw *hw = &hns->hw;
2288         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2289         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2290         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2291         struct rte_eth_rss_conf rss_conf;
2292         uint16_t mtu;
2293         bool gro_en;
2294         int ret;
2295
2296         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2297
2298         /*
2299          * Some versions of hardware network engine does not support
2300          * individually enable/disable/reset the Tx or Rx queue. These devices
2301          * must enable/disable/reset Tx and Rx queues at the same time. When the
2302          * numbers of Tx queues allocated by upper applications are not equal to
2303          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2304          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2305          * work as usual. But these fake queues are imperceptible, and can not
2306          * be used by upper applications.
2307          */
2308         if (!hns3_dev_indep_txrx_supported(hw)) {
2309                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2310                 if (ret) {
2311                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2312                                  ret);
2313                         return ret;
2314                 }
2315         }
2316
2317         hw->adapter_state = HNS3_NIC_CONFIGURING;
2318         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2319                 hns3_err(hw, "setting link speed/duplex not supported");
2320                 ret = -EINVAL;
2321                 goto cfg_err;
2322         }
2323
2324         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2325                 ret = hns3_check_dcb_cfg(dev);
2326                 if (ret)
2327                         goto cfg_err;
2328         }
2329
2330         /* When RSS is not configured, redirect the packet queue 0 */
2331         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2332                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2333                 rss_conf = conf->rx_adv_conf.rss_conf;
2334                 hw->rss_dis_flag = false;
2335                 if (rss_conf.rss_key == NULL) {
2336                         rss_conf.rss_key = rss_cfg->key;
2337                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2338                 }
2339
2340                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2341                 if (ret)
2342                         goto cfg_err;
2343         }
2344
2345         /*
2346          * If jumbo frames are enabled, MTU needs to be refreshed
2347          * according to the maximum RX packet length.
2348          */
2349         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2350                 /*
2351                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2352                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2353                  * can safely assign to "uint16_t" type variable.
2354                  */
2355                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2356                 ret = hns3_dev_mtu_set(dev, mtu);
2357                 if (ret)
2358                         goto cfg_err;
2359                 dev->data->mtu = mtu;
2360         }
2361
2362         ret = hns3_dev_configure_vlan(dev);
2363         if (ret)
2364                 goto cfg_err;
2365
2366         /* config hardware GRO */
2367         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2368         ret = hns3_config_gro(hw, gro_en);
2369         if (ret)
2370                 goto cfg_err;
2371
2372         hns->rx_simple_allowed = true;
2373         hns->rx_vec_allowed = true;
2374         hns->tx_simple_allowed = true;
2375         hns->tx_vec_allowed = true;
2376
2377         hns3_init_rx_ptype_tble(dev);
2378         hw->adapter_state = HNS3_NIC_CONFIGURED;
2379
2380         return 0;
2381
2382 cfg_err:
2383         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2384         hw->adapter_state = HNS3_NIC_INITIALIZED;
2385
2386         return ret;
2387 }
2388
2389 static int
2390 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2391 {
2392         struct hns3_config_max_frm_size_cmd *req;
2393         struct hns3_cmd_desc desc;
2394
2395         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2396
2397         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2398         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2399         req->min_frm_size = RTE_ETHER_MIN_LEN;
2400
2401         return hns3_cmd_send(hw, &desc, 1);
2402 }
2403
2404 static int
2405 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2406 {
2407         int ret;
2408
2409         ret = hns3_set_mac_mtu(hw, mps);
2410         if (ret) {
2411                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2412                 return ret;
2413         }
2414
2415         ret = hns3_buffer_alloc(hw);
2416         if (ret)
2417                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2418
2419         return ret;
2420 }
2421
2422 static int
2423 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2424 {
2425         struct hns3_adapter *hns = dev->data->dev_private;
2426         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2427         struct hns3_hw *hw = &hns->hw;
2428         bool is_jumbo_frame;
2429         int ret;
2430
2431         if (dev->data->dev_started) {
2432                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2433                          "before configuration", dev->data->port_id);
2434                 return -EBUSY;
2435         }
2436
2437         rte_spinlock_lock(&hw->lock);
2438         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2439         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2440
2441         /*
2442          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2443          * assign to "uint16_t" type variable.
2444          */
2445         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2446         if (ret) {
2447                 rte_spinlock_unlock(&hw->lock);
2448                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2449                          dev->data->port_id, mtu, ret);
2450                 return ret;
2451         }
2452         hns->pf.mps = (uint16_t)frame_size;
2453         if (is_jumbo_frame)
2454                 dev->data->dev_conf.rxmode.offloads |=
2455                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2456         else
2457                 dev->data->dev_conf.rxmode.offloads &=
2458                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2459         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2460         rte_spinlock_unlock(&hw->lock);
2461
2462         return 0;
2463 }
2464
2465 static int
2466 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2467 {
2468         struct hns3_adapter *hns = eth_dev->data->dev_private;
2469         struct hns3_hw *hw = &hns->hw;
2470         uint16_t queue_num = hw->tqps_num;
2471
2472         /*
2473          * In interrupt mode, 'max_rx_queues' is set based on the number of
2474          * MSI-X interrupt resources of the hardware.
2475          */
2476         if (hw->data->dev_conf.intr_conf.rxq == 1)
2477                 queue_num = hw->intr_tqps_num;
2478
2479         info->max_rx_queues = queue_num;
2480         info->max_tx_queues = hw->tqps_num;
2481         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2482         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2483         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2484         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2485         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2486         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2487                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2488                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2489                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2490                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2491                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2492                                  DEV_RX_OFFLOAD_KEEP_CRC |
2493                                  DEV_RX_OFFLOAD_SCATTER |
2494                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2495                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2496                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2497                                  DEV_RX_OFFLOAD_RSS_HASH |
2498                                  DEV_RX_OFFLOAD_TCP_LRO);
2499         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2500                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2501                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2502                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2503                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2504                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2505                                  DEV_TX_OFFLOAD_TCP_TSO |
2506                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2507                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2508                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2509                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2510                                  hns3_txvlan_cap_get(hw));
2511
2512         if (hns3_dev_indep_txrx_supported(hw))
2513                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2514                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2515
2516         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2517                 .nb_max = HNS3_MAX_RING_DESC,
2518                 .nb_min = HNS3_MIN_RING_DESC,
2519                 .nb_align = HNS3_ALIGN_RING_DESC,
2520         };
2521
2522         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2523                 .nb_max = HNS3_MAX_RING_DESC,
2524                 .nb_min = HNS3_MIN_RING_DESC,
2525                 .nb_align = HNS3_ALIGN_RING_DESC,
2526                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2527                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2528         };
2529
2530         info->default_rxconf = (struct rte_eth_rxconf) {
2531                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2532                 /*
2533                  * If there are no available Rx buffer descriptors, incoming
2534                  * packets are always dropped by hardware based on hns3 network
2535                  * engine.
2536                  */
2537                 .rx_drop_en = 1,
2538                 .offloads = 0,
2539         };
2540         info->default_txconf = (struct rte_eth_txconf) {
2541                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2542                 .offloads = 0,
2543         };
2544
2545         info->vmdq_queue_num = 0;
2546
2547         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2548         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2549         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2550
2551         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2552         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2553         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2554         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2555         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2556         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2557
2558         return 0;
2559 }
2560
2561 static int
2562 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2563                     size_t fw_size)
2564 {
2565         struct hns3_adapter *hns = eth_dev->data->dev_private;
2566         struct hns3_hw *hw = &hns->hw;
2567         uint32_t version = hw->fw_version;
2568         int ret;
2569
2570         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2571                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2572                                       HNS3_FW_VERSION_BYTE3_S),
2573                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2574                                       HNS3_FW_VERSION_BYTE2_S),
2575                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2576                                       HNS3_FW_VERSION_BYTE1_S),
2577                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2578                                       HNS3_FW_VERSION_BYTE0_S));
2579         ret += 1; /* add the size of '\0' */
2580         if (fw_size < (uint32_t)ret)
2581                 return ret;
2582         else
2583                 return 0;
2584 }
2585
2586 static int
2587 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2588                      __rte_unused int wait_to_complete)
2589 {
2590         struct hns3_adapter *hns = eth_dev->data->dev_private;
2591         struct hns3_hw *hw = &hns->hw;
2592         struct hns3_mac *mac = &hw->mac;
2593         struct rte_eth_link new_link;
2594
2595         if (!hns3_is_reset_pending(hns)) {
2596                 hns3_update_speed_duplex(eth_dev);
2597                 hns3_update_link_status(hw);
2598         }
2599
2600         memset(&new_link, 0, sizeof(new_link));
2601         switch (mac->link_speed) {
2602         case ETH_SPEED_NUM_10M:
2603         case ETH_SPEED_NUM_100M:
2604         case ETH_SPEED_NUM_1G:
2605         case ETH_SPEED_NUM_10G:
2606         case ETH_SPEED_NUM_25G:
2607         case ETH_SPEED_NUM_40G:
2608         case ETH_SPEED_NUM_50G:
2609         case ETH_SPEED_NUM_100G:
2610         case ETH_SPEED_NUM_200G:
2611                 new_link.link_speed = mac->link_speed;
2612                 break;
2613         default:
2614                 new_link.link_speed = ETH_SPEED_NUM_100M;
2615                 break;
2616         }
2617
2618         new_link.link_duplex = mac->link_duplex;
2619         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2620         new_link.link_autoneg =
2621             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2622
2623         return rte_eth_linkstatus_set(eth_dev, &new_link);
2624 }
2625
2626 static int
2627 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2628 {
2629         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2630         struct hns3_pf *pf = &hns->pf;
2631
2632         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2633                 return -EINVAL;
2634
2635         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2636
2637         return 0;
2638 }
2639
2640 static int
2641 hns3_query_function_status(struct hns3_hw *hw)
2642 {
2643 #define HNS3_QUERY_MAX_CNT              10
2644 #define HNS3_QUERY_SLEEP_MSCOEND        1
2645         struct hns3_func_status_cmd *req;
2646         struct hns3_cmd_desc desc;
2647         int timeout = 0;
2648         int ret;
2649
2650         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2651         req = (struct hns3_func_status_cmd *)desc.data;
2652
2653         do {
2654                 ret = hns3_cmd_send(hw, &desc, 1);
2655                 if (ret) {
2656                         PMD_INIT_LOG(ERR, "query function status failed %d",
2657                                      ret);
2658                         return ret;
2659                 }
2660
2661                 /* Check pf reset is done */
2662                 if (req->pf_state)
2663                         break;
2664
2665                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2666         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2667
2668         return hns3_parse_func_status(hw, req);
2669 }
2670
2671 static int
2672 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2673 {
2674         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2675         struct hns3_pf *pf = &hns->pf;
2676
2677         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2678                 /*
2679                  * The total_tqps_num obtained from firmware is maximum tqp
2680                  * numbers of this port, which should be used for PF and VFs.
2681                  * There is no need for pf to have so many tqp numbers in
2682                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2683                  * coming from config file, is assigned to maximum queue number
2684                  * for the PF of this port by user. So users can modify the
2685                  * maximum queue number of PF according to their own application
2686                  * scenarios, which is more flexible to use. In addition, many
2687                  * memories can be saved due to allocating queue statistics
2688                  * room according to the actual number of queues required. The
2689                  * maximum queue number of PF for network engine with
2690                  * revision_id greater than 0x30 is assigned by config file.
2691                  */
2692                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2693                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2694                                  "must be greater than 0.",
2695                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2696                         return -EINVAL;
2697                 }
2698
2699                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2700                                        hw->total_tqps_num);
2701         } else {
2702                 /*
2703                  * Due to the limitation on the number of PF interrupts
2704                  * available, the maximum queue number assigned to PF on
2705                  * the network engine with revision_id 0x21 is 64.
2706                  */
2707                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2708                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int
2715 hns3_query_pf_resource(struct hns3_hw *hw)
2716 {
2717         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2718         struct hns3_pf *pf = &hns->pf;
2719         struct hns3_pf_res_cmd *req;
2720         struct hns3_cmd_desc desc;
2721         int ret;
2722
2723         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2724         ret = hns3_cmd_send(hw, &desc, 1);
2725         if (ret) {
2726                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2727                 return ret;
2728         }
2729
2730         req = (struct hns3_pf_res_cmd *)desc.data;
2731         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2732                              rte_le_to_cpu_16(req->ext_tqp_num);
2733         ret = hns3_get_pf_max_tqp_num(hw);
2734         if (ret)
2735                 return ret;
2736
2737         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2738         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2739
2740         if (req->tx_buf_size)
2741                 pf->tx_buf_size =
2742                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2743         else
2744                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2745
2746         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2747
2748         if (req->dv_buf_size)
2749                 pf->dv_buf_size =
2750                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2751         else
2752                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2753
2754         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2755
2756         hw->num_msi =
2757                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2758                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2759
2760         return 0;
2761 }
2762
2763 static void
2764 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2765 {
2766         struct hns3_cfg_param_cmd *req;
2767         uint64_t mac_addr_tmp_high;
2768         uint8_t ext_rss_size_max;
2769         uint64_t mac_addr_tmp;
2770         uint32_t i;
2771
2772         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2773
2774         /* get the configuration */
2775         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2776                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2777         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2778                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2779         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2780                                            HNS3_CFG_TQP_DESC_N_M,
2781                                            HNS3_CFG_TQP_DESC_N_S);
2782
2783         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2784                                        HNS3_CFG_PHY_ADDR_M,
2785                                        HNS3_CFG_PHY_ADDR_S);
2786         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2787                                          HNS3_CFG_MEDIA_TP_M,
2788                                          HNS3_CFG_MEDIA_TP_S);
2789         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2790                                          HNS3_CFG_RX_BUF_LEN_M,
2791                                          HNS3_CFG_RX_BUF_LEN_S);
2792         /* get mac address */
2793         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2794         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2795                                            HNS3_CFG_MAC_ADDR_H_M,
2796                                            HNS3_CFG_MAC_ADDR_H_S);
2797
2798         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2799
2800         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2801                                             HNS3_CFG_DEFAULT_SPEED_M,
2802                                             HNS3_CFG_DEFAULT_SPEED_S);
2803         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2804                                            HNS3_CFG_RSS_SIZE_M,
2805                                            HNS3_CFG_RSS_SIZE_S);
2806
2807         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2808                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2809
2810         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2811         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2812
2813         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2814                                             HNS3_CFG_SPEED_ABILITY_M,
2815                                             HNS3_CFG_SPEED_ABILITY_S);
2816         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2817                                         HNS3_CFG_UMV_TBL_SPACE_M,
2818                                         HNS3_CFG_UMV_TBL_SPACE_S);
2819         if (!cfg->umv_space)
2820                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2821
2822         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2823                                                HNS3_CFG_EXT_RSS_SIZE_M,
2824                                                HNS3_CFG_EXT_RSS_SIZE_S);
2825
2826         /*
2827          * Field ext_rss_size_max obtained from firmware will be more flexible
2828          * for future changes and expansions, which is an exponent of 2, instead
2829          * of reading out directly. If this field is not zero, hns3 PF PMD
2830          * driver uses it as rss_size_max under one TC. Device, whose revision
2831          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2832          * maximum number of queues supported under a TC through this field.
2833          */
2834         if (ext_rss_size_max)
2835                 cfg->rss_size_max = 1U << ext_rss_size_max;
2836 }
2837
2838 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2839  * @hw: pointer to struct hns3_hw
2840  * @hcfg: the config structure to be getted
2841  */
2842 static int
2843 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2844 {
2845         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2846         struct hns3_cfg_param_cmd *req;
2847         uint32_t offset;
2848         uint32_t i;
2849         int ret;
2850
2851         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2852                 offset = 0;
2853                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2854                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2855                                           true);
2856                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2857                                i * HNS3_CFG_RD_LEN_BYTES);
2858                 /* Len should be divided by 4 when send to hardware */
2859                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2860                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2861                 req->offset = rte_cpu_to_le_32(offset);
2862         }
2863
2864         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2865         if (ret) {
2866                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2867                 return ret;
2868         }
2869
2870         hns3_parse_cfg(hcfg, desc);
2871
2872         return 0;
2873 }
2874
2875 static int
2876 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2877 {
2878         switch (speed_cmd) {
2879         case HNS3_CFG_SPEED_10M:
2880                 *speed = ETH_SPEED_NUM_10M;
2881                 break;
2882         case HNS3_CFG_SPEED_100M:
2883                 *speed = ETH_SPEED_NUM_100M;
2884                 break;
2885         case HNS3_CFG_SPEED_1G:
2886                 *speed = ETH_SPEED_NUM_1G;
2887                 break;
2888         case HNS3_CFG_SPEED_10G:
2889                 *speed = ETH_SPEED_NUM_10G;
2890                 break;
2891         case HNS3_CFG_SPEED_25G:
2892                 *speed = ETH_SPEED_NUM_25G;
2893                 break;
2894         case HNS3_CFG_SPEED_40G:
2895                 *speed = ETH_SPEED_NUM_40G;
2896                 break;
2897         case HNS3_CFG_SPEED_50G:
2898                 *speed = ETH_SPEED_NUM_50G;
2899                 break;
2900         case HNS3_CFG_SPEED_100G:
2901                 *speed = ETH_SPEED_NUM_100G;
2902                 break;
2903         case HNS3_CFG_SPEED_200G:
2904                 *speed = ETH_SPEED_NUM_200G;
2905                 break;
2906         default:
2907                 return -EINVAL;
2908         }
2909
2910         return 0;
2911 }
2912
2913 static void
2914 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2915 {
2916         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2917         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2918         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2919         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2920 }
2921
2922 static void
2923 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2924 {
2925         struct hns3_dev_specs_0_cmd *req0;
2926
2927         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2928
2929         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2930         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2931         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2932         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2933 }
2934
2935 static int
2936 hns3_query_dev_specifications(struct hns3_hw *hw)
2937 {
2938         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2939         int ret;
2940         int i;
2941
2942         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2943                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2944                                           true);
2945                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2946         }
2947         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2948
2949         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2950         if (ret)
2951                 return ret;
2952
2953         hns3_parse_dev_specifications(hw, desc);
2954
2955         return 0;
2956 }
2957
2958 static int
2959 hns3_get_capability(struct hns3_hw *hw)
2960 {
2961         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2962         struct rte_pci_device *pci_dev;
2963         struct hns3_pf *pf = &hns->pf;
2964         struct rte_eth_dev *eth_dev;
2965         uint16_t device_id;
2966         uint8_t revision;
2967         int ret;
2968
2969         eth_dev = &rte_eth_devices[hw->data->port_id];
2970         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2971         device_id = pci_dev->id.device_id;
2972
2973         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2974             device_id == HNS3_DEV_ID_50GE_RDMA ||
2975             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2976             device_id == HNS3_DEV_ID_200G_RDMA)
2977                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2978
2979         /* Get PCI revision id */
2980         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2981                                   HNS3_PCI_REVISION_ID);
2982         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2983                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2984                              ret);
2985                 return -EIO;
2986         }
2987         hw->revision = revision;
2988
2989         if (revision < PCI_REVISION_ID_HIP09_A) {
2990                 hns3_set_default_dev_specifications(hw);
2991                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2992                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2993                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2994                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2995                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2996                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2997                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2998                 return 0;
2999         }
3000
3001         ret = hns3_query_dev_specifications(hw);
3002         if (ret) {
3003                 PMD_INIT_LOG(ERR,
3004                              "failed to query dev specifications, ret = %d",
3005                              ret);
3006                 return ret;
3007         }
3008
3009         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3010         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
3011         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3012         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3013         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3014         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3015         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3016
3017         return 0;
3018 }
3019
3020 static int
3021 hns3_get_board_configuration(struct hns3_hw *hw)
3022 {
3023         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3024         struct hns3_pf *pf = &hns->pf;
3025         struct hns3_cfg cfg;
3026         int ret;
3027
3028         ret = hns3_get_board_cfg(hw, &cfg);
3029         if (ret) {
3030                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3031                 return ret;
3032         }
3033
3034         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3035             !hns3_dev_copper_supported(hw)) {
3036                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3037                 return -EOPNOTSUPP;
3038         }
3039
3040         hw->mac.media_type = cfg.media_type;
3041         hw->rss_size_max = cfg.rss_size_max;
3042         hw->rss_dis_flag = false;
3043         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3044         hw->mac.phy_addr = cfg.phy_addr;
3045         hw->mac.default_addr_setted = false;
3046         hw->num_tx_desc = cfg.tqp_desc_num;
3047         hw->num_rx_desc = cfg.tqp_desc_num;
3048         hw->dcb_info.num_pg = 1;
3049         hw->dcb_info.hw_pfc_map = 0;
3050
3051         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3052         if (ret) {
3053                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
3054                              cfg.default_speed, ret);
3055                 return ret;
3056         }
3057
3058         pf->tc_max = cfg.tc_num;
3059         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3060                 PMD_INIT_LOG(WARNING,
3061                              "Get TC num(%u) from flash, set TC num to 1",
3062                              pf->tc_max);
3063                 pf->tc_max = 1;
3064         }
3065
3066         /* Dev does not support DCB */
3067         if (!hns3_dev_dcb_supported(hw)) {
3068                 pf->tc_max = 1;
3069                 pf->pfc_max = 0;
3070         } else
3071                 pf->pfc_max = pf->tc_max;
3072
3073         hw->dcb_info.num_tc = 1;
3074         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3075                                      hw->tqps_num / hw->dcb_info.num_tc);
3076         hns3_set_bit(hw->hw_tc_map, 0, 1);
3077         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3078
3079         pf->wanted_umv_size = cfg.umv_space;
3080
3081         return ret;
3082 }
3083
3084 static int
3085 hns3_get_configuration(struct hns3_hw *hw)
3086 {
3087         int ret;
3088
3089         ret = hns3_query_function_status(hw);
3090         if (ret) {
3091                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3092                 return ret;
3093         }
3094
3095         /* Get device capability */
3096         ret = hns3_get_capability(hw);
3097         if (ret) {
3098                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3099                 return ret;
3100         }
3101
3102         /* Get pf resource */
3103         ret = hns3_query_pf_resource(hw);
3104         if (ret) {
3105                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3106                 return ret;
3107         }
3108
3109         ret = hns3_get_board_configuration(hw);
3110         if (ret)
3111                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3112
3113         return ret;
3114 }
3115
3116 static int
3117 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3118                       uint16_t tqp_vid, bool is_pf)
3119 {
3120         struct hns3_tqp_map_cmd *req;
3121         struct hns3_cmd_desc desc;
3122         int ret;
3123
3124         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3125
3126         req = (struct hns3_tqp_map_cmd *)desc.data;
3127         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3128         req->tqp_vf = func_id;
3129         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3130         if (!is_pf)
3131                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3132         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3133
3134         ret = hns3_cmd_send(hw, &desc, 1);
3135         if (ret)
3136                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3137
3138         return ret;
3139 }
3140
3141 static int
3142 hns3_map_tqp(struct hns3_hw *hw)
3143 {
3144         int ret;
3145         int i;
3146
3147         /*
3148          * In current version, VF is not supported when PF is driven by DPDK
3149          * driver, so we assign total tqps_num tqps allocated to this port
3150          * to PF.
3151          */
3152         for (i = 0; i < hw->total_tqps_num; i++) {
3153                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3154                 if (ret)
3155                         return ret;
3156         }
3157
3158         return 0;
3159 }
3160
3161 static int
3162 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3163 {
3164         struct hns3_config_mac_speed_dup_cmd *req;
3165         struct hns3_cmd_desc desc;
3166         int ret;
3167
3168         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3169
3170         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3171
3172         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3173
3174         switch (speed) {
3175         case ETH_SPEED_NUM_10M:
3176                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3177                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3178                 break;
3179         case ETH_SPEED_NUM_100M:
3180                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3181                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3182                 break;
3183         case ETH_SPEED_NUM_1G:
3184                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3185                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3186                 break;
3187         case ETH_SPEED_NUM_10G:
3188                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3189                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3190                 break;
3191         case ETH_SPEED_NUM_25G:
3192                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3193                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3194                 break;
3195         case ETH_SPEED_NUM_40G:
3196                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3197                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3198                 break;
3199         case ETH_SPEED_NUM_50G:
3200                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3201                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3202                 break;
3203         case ETH_SPEED_NUM_100G:
3204                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3205                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3206                 break;
3207         case ETH_SPEED_NUM_200G:
3208                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3209                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3210                 break;
3211         default:
3212                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3213                 return -EINVAL;
3214         }
3215
3216         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3217
3218         ret = hns3_cmd_send(hw, &desc, 1);
3219         if (ret)
3220                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3221
3222         return ret;
3223 }
3224
3225 static int
3226 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3227 {
3228         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3229         struct hns3_pf *pf = &hns->pf;
3230         struct hns3_priv_buf *priv;
3231         uint32_t i, total_size;
3232
3233         total_size = pf->pkt_buf_size;
3234
3235         /* alloc tx buffer for all enabled tc */
3236         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3237                 priv = &buf_alloc->priv_buf[i];
3238
3239                 if (hw->hw_tc_map & BIT(i)) {
3240                         if (total_size < pf->tx_buf_size)
3241                                 return -ENOMEM;
3242
3243                         priv->tx_buf_size = pf->tx_buf_size;
3244                 } else
3245                         priv->tx_buf_size = 0;
3246
3247                 total_size -= priv->tx_buf_size;
3248         }
3249
3250         return 0;
3251 }
3252
3253 static int
3254 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3255 {
3256 /* TX buffer size is unit by 128 byte */
3257 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3258 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3259         struct hns3_tx_buff_alloc_cmd *req;
3260         struct hns3_cmd_desc desc;
3261         uint32_t buf_size;
3262         uint32_t i;
3263         int ret;
3264
3265         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3266
3267         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3268         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3269                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3270
3271                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3272                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3273                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3274         }
3275
3276         ret = hns3_cmd_send(hw, &desc, 1);
3277         if (ret)
3278                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3279
3280         return ret;
3281 }
3282
3283 static int
3284 hns3_get_tc_num(struct hns3_hw *hw)
3285 {
3286         int cnt = 0;
3287         uint8_t i;
3288
3289         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3290                 if (hw->hw_tc_map & BIT(i))
3291                         cnt++;
3292         return cnt;
3293 }
3294
3295 static uint32_t
3296 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3297 {
3298         struct hns3_priv_buf *priv;
3299         uint32_t rx_priv = 0;
3300         int i;
3301
3302         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3303                 priv = &buf_alloc->priv_buf[i];
3304                 if (priv->enable)
3305                         rx_priv += priv->buf_size;
3306         }
3307         return rx_priv;
3308 }
3309
3310 static uint32_t
3311 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3312 {
3313         uint32_t total_tx_size = 0;
3314         uint32_t i;
3315
3316         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3317                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3318
3319         return total_tx_size;
3320 }
3321
3322 /* Get the number of pfc enabled TCs, which have private buffer */
3323 static int
3324 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3325 {
3326         struct hns3_priv_buf *priv;
3327         int cnt = 0;
3328         uint8_t i;
3329
3330         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3331                 priv = &buf_alloc->priv_buf[i];
3332                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3333                         cnt++;
3334         }
3335
3336         return cnt;
3337 }
3338
3339 /* Get the number of pfc disabled TCs, which have private buffer */
3340 static int
3341 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3342                          struct hns3_pkt_buf_alloc *buf_alloc)
3343 {
3344         struct hns3_priv_buf *priv;
3345         int cnt = 0;
3346         uint8_t i;
3347
3348         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3349                 priv = &buf_alloc->priv_buf[i];
3350                 if (hw->hw_tc_map & BIT(i) &&
3351                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3352                         cnt++;
3353         }
3354
3355         return cnt;
3356 }
3357
3358 static bool
3359 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3360                   uint32_t rx_all)
3361 {
3362         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3363         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3364         struct hns3_pf *pf = &hns->pf;
3365         uint32_t shared_buf, aligned_mps;
3366         uint32_t rx_priv;
3367         uint8_t tc_num;
3368         uint8_t i;
3369
3370         tc_num = hns3_get_tc_num(hw);
3371         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3372
3373         if (hns3_dev_dcb_supported(hw))
3374                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3375                                         pf->dv_buf_size;
3376         else
3377                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3378                                         + pf->dv_buf_size;
3379
3380         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3381         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3382                              HNS3_BUF_SIZE_UNIT);
3383
3384         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3385         if (rx_all < rx_priv + shared_std)
3386                 return false;
3387
3388         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3389         buf_alloc->s_buf.buf_size = shared_buf;
3390         if (hns3_dev_dcb_supported(hw)) {
3391                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3392                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3393                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3394                                   HNS3_BUF_SIZE_UNIT);
3395         } else {
3396                 buf_alloc->s_buf.self.high =
3397                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3398                 buf_alloc->s_buf.self.low = aligned_mps;
3399         }
3400
3401         if (hns3_dev_dcb_supported(hw)) {
3402                 hi_thrd = shared_buf - pf->dv_buf_size;
3403
3404                 if (tc_num <= NEED_RESERVE_TC_NUM)
3405                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3406                                         / BUF_MAX_PERCENT;
3407
3408                 if (tc_num)
3409                         hi_thrd = hi_thrd / tc_num;
3410
3411                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3412                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3413                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3414         } else {
3415                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3416                 lo_thrd = aligned_mps;
3417         }
3418
3419         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3420                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3421                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3422         }
3423
3424         return true;
3425 }
3426
3427 static bool
3428 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3429                      struct hns3_pkt_buf_alloc *buf_alloc)
3430 {
3431         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3432         struct hns3_pf *pf = &hns->pf;
3433         struct hns3_priv_buf *priv;
3434         uint32_t aligned_mps;
3435         uint32_t rx_all;
3436         uint8_t i;
3437
3438         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3439         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3440
3441         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3442                 priv = &buf_alloc->priv_buf[i];
3443
3444                 priv->enable = 0;
3445                 priv->wl.low = 0;
3446                 priv->wl.high = 0;
3447                 priv->buf_size = 0;
3448
3449                 if (!(hw->hw_tc_map & BIT(i)))
3450                         continue;
3451
3452                 priv->enable = 1;
3453                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3454                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3455                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3456                                                 HNS3_BUF_SIZE_UNIT);
3457                 } else {
3458                         priv->wl.low = 0;
3459                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3460                                         aligned_mps;
3461                 }
3462
3463                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3464         }
3465
3466         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3467 }
3468
3469 static bool
3470 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3471                              struct hns3_pkt_buf_alloc *buf_alloc)
3472 {
3473         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3474         struct hns3_pf *pf = &hns->pf;
3475         struct hns3_priv_buf *priv;
3476         int no_pfc_priv_num;
3477         uint32_t rx_all;
3478         uint8_t mask;
3479         int i;
3480
3481         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3482         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3483
3484         /* let the last to be cleared first */
3485         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3486                 priv = &buf_alloc->priv_buf[i];
3487                 mask = BIT((uint8_t)i);
3488
3489                 if (hw->hw_tc_map & mask &&
3490                     !(hw->dcb_info.hw_pfc_map & mask)) {
3491                         /* Clear the no pfc TC private buffer */
3492                         priv->wl.low = 0;
3493                         priv->wl.high = 0;
3494                         priv->buf_size = 0;
3495                         priv->enable = 0;
3496                         no_pfc_priv_num--;
3497                 }
3498
3499                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3500                     no_pfc_priv_num == 0)
3501                         break;
3502         }
3503
3504         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3505 }
3506
3507 static bool
3508 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3509                            struct hns3_pkt_buf_alloc *buf_alloc)
3510 {
3511         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3512         struct hns3_pf *pf = &hns->pf;
3513         struct hns3_priv_buf *priv;
3514         uint32_t rx_all;
3515         int pfc_priv_num;
3516         uint8_t mask;
3517         int i;
3518
3519         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3520         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3521
3522         /* let the last to be cleared first */
3523         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3524                 priv = &buf_alloc->priv_buf[i];
3525                 mask = BIT((uint8_t)i);
3526
3527                 if (hw->hw_tc_map & mask &&
3528                     hw->dcb_info.hw_pfc_map & mask) {
3529                         /* Reduce the number of pfc TC with private buffer */
3530                         priv->wl.low = 0;
3531                         priv->enable = 0;
3532                         priv->wl.high = 0;
3533                         priv->buf_size = 0;
3534                         pfc_priv_num--;
3535                 }
3536                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3537                     pfc_priv_num == 0)
3538                         break;
3539         }
3540
3541         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3542 }
3543
3544 static bool
3545 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3546                           struct hns3_pkt_buf_alloc *buf_alloc)
3547 {
3548 #define COMPENSATE_BUFFER       0x3C00
3549 #define COMPENSATE_HALF_MPS_NUM 5
3550 #define PRIV_WL_GAP             0x1800
3551         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3552         struct hns3_pf *pf = &hns->pf;
3553         uint32_t tc_num = hns3_get_tc_num(hw);
3554         uint32_t half_mps = pf->mps >> 1;
3555         struct hns3_priv_buf *priv;
3556         uint32_t min_rx_priv;
3557         uint32_t rx_priv;
3558         uint8_t i;
3559
3560         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3561         if (tc_num)
3562                 rx_priv = rx_priv / tc_num;
3563
3564         if (tc_num <= NEED_RESERVE_TC_NUM)
3565                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3566
3567         /*
3568          * Minimum value of private buffer in rx direction (min_rx_priv) is
3569          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3570          * buffer if rx_priv is greater than min_rx_priv.
3571          */
3572         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3573                         COMPENSATE_HALF_MPS_NUM * half_mps;
3574         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3575         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3576
3577         if (rx_priv < min_rx_priv)
3578                 return false;
3579
3580         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3581                 priv = &buf_alloc->priv_buf[i];
3582
3583                 priv->enable = 0;
3584                 priv->wl.low = 0;
3585                 priv->wl.high = 0;
3586                 priv->buf_size = 0;
3587
3588                 if (!(hw->hw_tc_map & BIT(i)))
3589                         continue;
3590
3591                 priv->enable = 1;
3592                 priv->buf_size = rx_priv;
3593                 priv->wl.high = rx_priv - pf->dv_buf_size;
3594                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3595         }
3596
3597         buf_alloc->s_buf.buf_size = 0;
3598
3599         return true;
3600 }
3601
3602 /*
3603  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3604  * @hw: pointer to struct hns3_hw
3605  * @buf_alloc: pointer to buffer calculation data
3606  * @return: 0: calculate sucessful, negative: fail
3607  */
3608 static int
3609 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3610 {
3611         /* When DCB is not supported, rx private buffer is not allocated. */
3612         if (!hns3_dev_dcb_supported(hw)) {
3613                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3614                 struct hns3_pf *pf = &hns->pf;
3615                 uint32_t rx_all = pf->pkt_buf_size;
3616
3617                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3618                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3619                         return -ENOMEM;
3620
3621                 return 0;
3622         }
3623
3624         /*
3625          * Try to allocate privated packet buffer for all TCs without share
3626          * buffer.
3627          */
3628         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3629                 return 0;
3630
3631         /*
3632          * Try to allocate privated packet buffer for all TCs with share
3633          * buffer.
3634          */
3635         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3636                 return 0;
3637
3638         /*
3639          * For different application scenes, the enabled port number, TC number
3640          * and no_drop TC number are different. In order to obtain the better
3641          * performance, software could allocate the buffer size and configure
3642          * the waterline by tring to decrease the private buffer size according
3643          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3644          * enabled tc.
3645          */
3646         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3647                 return 0;
3648
3649         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3650                 return 0;
3651
3652         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3653                 return 0;
3654
3655         return -ENOMEM;
3656 }
3657
3658 static int
3659 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3660 {
3661         struct hns3_rx_priv_buff_cmd *req;
3662         struct hns3_cmd_desc desc;
3663         uint32_t buf_size;
3664         int ret;
3665         int i;
3666
3667         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3668         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3669
3670         /* Alloc private buffer TCs */
3671         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3672                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3673
3674                 req->buf_num[i] =
3675                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3676                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3677         }
3678
3679         buf_size = buf_alloc->s_buf.buf_size;
3680         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3681                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3682
3683         ret = hns3_cmd_send(hw, &desc, 1);
3684         if (ret)
3685                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3686
3687         return ret;
3688 }
3689
3690 static int
3691 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3692 {
3693 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3694         struct hns3_rx_priv_wl_buf *req;
3695         struct hns3_priv_buf *priv;
3696         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3697         int i, j;
3698         int ret;
3699
3700         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3701                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3702                                           false);
3703                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3704
3705                 /* The first descriptor set the NEXT bit to 1 */
3706                 if (i == 0)
3707                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3708                 else
3709                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3710
3711                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3712                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3713
3714                         priv = &buf_alloc->priv_buf[idx];
3715                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3716                                                         HNS3_BUF_UNIT_S);
3717                         req->tc_wl[j].high |=
3718                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3719                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3720                                                         HNS3_BUF_UNIT_S);
3721                         req->tc_wl[j].low |=
3722                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3723                 }
3724         }
3725
3726         /* Send 2 descriptor at one time */
3727         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3728         if (ret)
3729                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3730                              ret);
3731         return ret;
3732 }
3733
3734 static int
3735 hns3_common_thrd_config(struct hns3_hw *hw,
3736                         struct hns3_pkt_buf_alloc *buf_alloc)
3737 {
3738 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3739         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3740         struct hns3_rx_com_thrd *req;
3741         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3742         struct hns3_tc_thrd *tc;
3743         int tc_idx;
3744         int i, j;
3745         int ret;
3746
3747         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3748                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3749                                           false);
3750                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3751
3752                 /* The first descriptor set the NEXT bit to 1 */
3753                 if (i == 0)
3754                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3755                 else
3756                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3757
3758                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3759                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3760                         tc = &s_buf->tc_thrd[tc_idx];
3761
3762                         req->com_thrd[j].high =
3763                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3764                         req->com_thrd[j].high |=
3765                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3766                         req->com_thrd[j].low =
3767                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3768                         req->com_thrd[j].low |=
3769                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3770                 }
3771         }
3772
3773         /* Send 2 descriptors at one time */
3774         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3775         if (ret)
3776                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3777
3778         return ret;
3779 }
3780
3781 static int
3782 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3783 {
3784         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3785         struct hns3_rx_com_wl *req;
3786         struct hns3_cmd_desc desc;
3787         int ret;
3788
3789         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3790
3791         req = (struct hns3_rx_com_wl *)desc.data;
3792         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3793         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3794
3795         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3796         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3797
3798         ret = hns3_cmd_send(hw, &desc, 1);
3799         if (ret)
3800                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3801
3802         return ret;
3803 }
3804
3805 int
3806 hns3_buffer_alloc(struct hns3_hw *hw)
3807 {
3808         struct hns3_pkt_buf_alloc pkt_buf;
3809         int ret;
3810
3811         memset(&pkt_buf, 0, sizeof(pkt_buf));
3812         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3813         if (ret) {
3814                 PMD_INIT_LOG(ERR,
3815                              "could not calc tx buffer size for all TCs %d",
3816                              ret);
3817                 return ret;
3818         }
3819
3820         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3821         if (ret) {
3822                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3823                 return ret;
3824         }
3825
3826         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3827         if (ret) {
3828                 PMD_INIT_LOG(ERR,
3829                              "could not calc rx priv buffer size for all TCs %d",
3830                              ret);
3831                 return ret;
3832         }
3833
3834         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3835         if (ret) {
3836                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3837                 return ret;
3838         }
3839
3840         if (hns3_dev_dcb_supported(hw)) {
3841                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3842                 if (ret) {
3843                         PMD_INIT_LOG(ERR,
3844                                      "could not configure rx private waterline %d",
3845                                      ret);
3846                         return ret;
3847                 }
3848
3849                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3850                 if (ret) {
3851                         PMD_INIT_LOG(ERR,
3852                                      "could not configure common threshold %d",
3853                                      ret);
3854                         return ret;
3855                 }
3856         }
3857
3858         ret = hns3_common_wl_config(hw, &pkt_buf);
3859         if (ret)
3860                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3861                              ret);
3862
3863         return ret;
3864 }
3865
3866 static int
3867 hns3_mac_init(struct hns3_hw *hw)
3868 {
3869         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3870         struct hns3_mac *mac = &hw->mac;
3871         struct hns3_pf *pf = &hns->pf;
3872         int ret;
3873
3874         pf->support_sfp_query = true;
3875         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3876         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3877         if (ret) {
3878                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3879                 return ret;
3880         }
3881
3882         mac->link_status = ETH_LINK_DOWN;
3883
3884         return hns3_config_mtu(hw, pf->mps);
3885 }
3886
3887 static int
3888 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3889 {
3890 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3891 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3892 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3893 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3894         int return_status;
3895
3896         if (cmdq_resp) {
3897                 PMD_INIT_LOG(ERR,
3898                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3899                              cmdq_resp);
3900                 return -EIO;
3901         }
3902
3903         switch (resp_code) {
3904         case HNS3_ETHERTYPE_SUCCESS_ADD:
3905         case HNS3_ETHERTYPE_ALREADY_ADD:
3906                 return_status = 0;
3907                 break;
3908         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3909                 PMD_INIT_LOG(ERR,
3910                              "add mac ethertype failed for manager table overflow.");
3911                 return_status = -EIO;
3912                 break;
3913         case HNS3_ETHERTYPE_KEY_CONFLICT:
3914                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3915                 return_status = -EIO;
3916                 break;
3917         default:
3918                 PMD_INIT_LOG(ERR,
3919                              "add mac ethertype failed for undefined, code=%d.",
3920                              resp_code);
3921                 return_status = -EIO;
3922                 break;
3923         }
3924
3925         return return_status;
3926 }
3927
3928 static int
3929 hns3_add_mgr_tbl(struct hns3_hw *hw,
3930                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3931 {
3932         struct hns3_cmd_desc desc;
3933         uint8_t resp_code;
3934         uint16_t retval;
3935         int ret;
3936
3937         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3938         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3939
3940         ret = hns3_cmd_send(hw, &desc, 1);
3941         if (ret) {
3942                 PMD_INIT_LOG(ERR,
3943                              "add mac ethertype failed for cmd_send, ret =%d.",
3944                              ret);
3945                 return ret;
3946         }
3947
3948         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3949         retval = rte_le_to_cpu_16(desc.retval);
3950
3951         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3952 }
3953
3954 static void
3955 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3956                      int *table_item_num)
3957 {
3958         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3959
3960         /*
3961          * In current version, we add one item in management table as below:
3962          * 0x0180C200000E -- LLDP MC address
3963          */
3964         tbl = mgr_table;
3965         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3966         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3967         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3968         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3969         tbl->i_port_bitmap = 0x1;
3970         *table_item_num = 1;
3971 }
3972
3973 static int
3974 hns3_init_mgr_tbl(struct hns3_hw *hw)
3975 {
3976 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3977         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3978         int table_item_num;
3979         int ret;
3980         int i;
3981
3982         memset(mgr_table, 0, sizeof(mgr_table));
3983         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3984         for (i = 0; i < table_item_num; i++) {
3985                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3986                 if (ret) {
3987                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3988                                      ret);
3989                         return ret;
3990                 }
3991         }
3992
3993         return 0;
3994 }
3995
3996 static void
3997 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3998                         bool en_mc, bool en_bc, int vport_id)
3999 {
4000         if (!param)
4001                 return;
4002
4003         memset(param, 0, sizeof(struct hns3_promisc_param));
4004         if (en_uc)
4005                 param->enable = HNS3_PROMISC_EN_UC;
4006         if (en_mc)
4007                 param->enable |= HNS3_PROMISC_EN_MC;
4008         if (en_bc)
4009                 param->enable |= HNS3_PROMISC_EN_BC;
4010         param->vf_id = vport_id;
4011 }
4012
4013 static int
4014 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4015 {
4016         struct hns3_promisc_cfg_cmd *req;
4017         struct hns3_cmd_desc desc;
4018         int ret;
4019
4020         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4021
4022         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4023         req->vf_id = param->vf_id;
4024         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4025             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4026
4027         ret = hns3_cmd_send(hw, &desc, 1);
4028         if (ret)
4029                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4030
4031         return ret;
4032 }
4033
4034 static int
4035 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4036 {
4037         struct hns3_promisc_param param;
4038         bool en_bc_pmc = true;
4039         uint8_t vf_id;
4040
4041         /*
4042          * In current version VF is not supported when PF is driven by DPDK
4043          * driver, just need to configure parameters for PF vport.
4044          */
4045         vf_id = HNS3_PF_FUNC_ID;
4046
4047         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4048         return hns3_cmd_set_promisc_mode(hw, &param);
4049 }
4050
4051 static int
4052 hns3_promisc_init(struct hns3_hw *hw)
4053 {
4054         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4055         struct hns3_pf *pf = &hns->pf;
4056         struct hns3_promisc_param param;
4057         uint16_t func_id;
4058         int ret;
4059
4060         ret = hns3_set_promisc_mode(hw, false, false);
4061         if (ret) {
4062                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4063                 return ret;
4064         }
4065
4066         /*
4067          * In current version VFs are not supported when PF is driven by DPDK
4068          * driver. After PF has been taken over by DPDK, the original VF will
4069          * be invalid. So, there is a possibility of entry residues. It should
4070          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4071          * during init.
4072          */
4073         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4074                 hns3_promisc_param_init(&param, false, false, false, func_id);
4075                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4076                 if (ret) {
4077                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4078                                         " ret = %d", func_id, ret);
4079                         return ret;
4080                 }
4081         }
4082
4083         return 0;
4084 }
4085
4086 static void
4087 hns3_promisc_uninit(struct hns3_hw *hw)
4088 {
4089         struct hns3_promisc_param param;
4090         uint16_t func_id;
4091         int ret;
4092
4093         func_id = HNS3_PF_FUNC_ID;
4094
4095         /*
4096          * In current version VFs are not supported when PF is driven by
4097          * DPDK driver, and VFs' promisc mode status has been cleared during
4098          * init and their status will not change. So just clear PF's promisc
4099          * mode status during uninit.
4100          */
4101         hns3_promisc_param_init(&param, false, false, false, func_id);
4102         ret = hns3_cmd_set_promisc_mode(hw, &param);
4103         if (ret)
4104                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4105                                 " uninit, ret = %d", ret);
4106 }
4107
4108 static int
4109 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4110 {
4111         bool allmulti = dev->data->all_multicast ? true : false;
4112         struct hns3_adapter *hns = dev->data->dev_private;
4113         struct hns3_hw *hw = &hns->hw;
4114         uint64_t offloads;
4115         int err;
4116         int ret;
4117
4118         rte_spinlock_lock(&hw->lock);
4119         ret = hns3_set_promisc_mode(hw, true, true);
4120         if (ret) {
4121                 rte_spinlock_unlock(&hw->lock);
4122                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4123                          ret);
4124                 return ret;
4125         }
4126
4127         /*
4128          * When promiscuous mode was enabled, disable the vlan filter to let
4129          * all packets coming in in the receiving direction.
4130          */
4131         offloads = dev->data->dev_conf.rxmode.offloads;
4132         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4133                 ret = hns3_enable_vlan_filter(hns, false);
4134                 if (ret) {
4135                         hns3_err(hw, "failed to enable promiscuous mode due to "
4136                                      "failure to disable vlan filter, ret = %d",
4137                                  ret);
4138                         err = hns3_set_promisc_mode(hw, false, allmulti);
4139                         if (err)
4140                                 hns3_err(hw, "failed to restore promiscuous "
4141                                          "status after disable vlan filter "
4142                                          "failed during enabling promiscuous "
4143                                          "mode, ret = %d", ret);
4144                 }
4145         }
4146
4147         rte_spinlock_unlock(&hw->lock);
4148
4149         return ret;
4150 }
4151
4152 static int
4153 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4154 {
4155         bool allmulti = dev->data->all_multicast ? true : false;
4156         struct hns3_adapter *hns = dev->data->dev_private;
4157         struct hns3_hw *hw = &hns->hw;
4158         uint64_t offloads;
4159         int err;
4160         int ret;
4161
4162         /* If now in all_multicast mode, must remain in all_multicast mode. */
4163         rte_spinlock_lock(&hw->lock);
4164         ret = hns3_set_promisc_mode(hw, false, allmulti);
4165         if (ret) {
4166                 rte_spinlock_unlock(&hw->lock);
4167                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4168                          ret);
4169                 return ret;
4170         }
4171         /* when promiscuous mode was disabled, restore the vlan filter status */
4172         offloads = dev->data->dev_conf.rxmode.offloads;
4173         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4174                 ret = hns3_enable_vlan_filter(hns, true);
4175                 if (ret) {
4176                         hns3_err(hw, "failed to disable promiscuous mode due to"
4177                                  " failure to restore vlan filter, ret = %d",
4178                                  ret);
4179                         err = hns3_set_promisc_mode(hw, true, true);
4180                         if (err)
4181                                 hns3_err(hw, "failed to restore promiscuous "
4182                                          "status after enabling vlan filter "
4183                                          "failed during disabling promiscuous "
4184                                          "mode, ret = %d", ret);
4185                 }
4186         }
4187         rte_spinlock_unlock(&hw->lock);
4188
4189         return ret;
4190 }
4191
4192 static int
4193 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4194 {
4195         struct hns3_adapter *hns = dev->data->dev_private;
4196         struct hns3_hw *hw = &hns->hw;
4197         int ret;
4198
4199         if (dev->data->promiscuous)
4200                 return 0;
4201
4202         rte_spinlock_lock(&hw->lock);
4203         ret = hns3_set_promisc_mode(hw, false, true);
4204         rte_spinlock_unlock(&hw->lock);
4205         if (ret)
4206                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4207                          ret);
4208
4209         return ret;
4210 }
4211
4212 static int
4213 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4214 {
4215         struct hns3_adapter *hns = dev->data->dev_private;
4216         struct hns3_hw *hw = &hns->hw;
4217         int ret;
4218
4219         /* If now in promiscuous mode, must remain in all_multicast mode. */
4220         if (dev->data->promiscuous)
4221                 return 0;
4222
4223         rte_spinlock_lock(&hw->lock);
4224         ret = hns3_set_promisc_mode(hw, false, false);
4225         rte_spinlock_unlock(&hw->lock);
4226         if (ret)
4227                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4228                          ret);
4229
4230         return ret;
4231 }
4232
4233 static int
4234 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4235 {
4236         struct hns3_hw *hw = &hns->hw;
4237         bool allmulti = hw->data->all_multicast ? true : false;
4238         int ret;
4239
4240         if (hw->data->promiscuous) {
4241                 ret = hns3_set_promisc_mode(hw, true, true);
4242                 if (ret)
4243                         hns3_err(hw, "failed to restore promiscuous mode, "
4244                                  "ret = %d", ret);
4245                 return ret;
4246         }
4247
4248         ret = hns3_set_promisc_mode(hw, false, allmulti);
4249         if (ret)
4250                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4251                          ret);
4252         return ret;
4253 }
4254
4255 static int
4256 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4257 {
4258         struct hns3_sfp_speed_cmd *resp;
4259         struct hns3_cmd_desc desc;
4260         int ret;
4261
4262         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4263         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4264         ret = hns3_cmd_send(hw, &desc, 1);
4265         if (ret == -EOPNOTSUPP) {
4266                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4267                 return ret;
4268         } else if (ret) {
4269                 hns3_err(hw, "get sfp speed failed %d", ret);
4270                 return ret;
4271         }
4272
4273         *speed = resp->sfp_speed;
4274
4275         return 0;
4276 }
4277
4278 static uint8_t
4279 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4280 {
4281         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4282                 duplex = ETH_LINK_FULL_DUPLEX;
4283
4284         return duplex;
4285 }
4286
4287 static int
4288 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4289 {
4290         struct hns3_mac *mac = &hw->mac;
4291         int ret;
4292
4293         duplex = hns3_check_speed_dup(duplex, speed);
4294         if (mac->link_speed == speed && mac->link_duplex == duplex)
4295                 return 0;
4296
4297         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4298         if (ret)
4299                 return ret;
4300
4301         mac->link_speed = speed;
4302         mac->link_duplex = duplex;
4303
4304         return 0;
4305 }
4306
4307 static int
4308 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4309 {
4310         struct hns3_adapter *hns = eth_dev->data->dev_private;
4311         struct hns3_hw *hw = &hns->hw;
4312         struct hns3_pf *pf = &hns->pf;
4313         uint32_t speed;
4314         int ret;
4315
4316         /* If IMP do not support get SFP/qSFP speed, return directly */
4317         if (!pf->support_sfp_query)
4318                 return 0;
4319
4320         ret = hns3_get_sfp_speed(hw, &speed);
4321         if (ret == -EOPNOTSUPP) {
4322                 pf->support_sfp_query = false;
4323                 return ret;
4324         } else if (ret)
4325                 return ret;
4326
4327         if (speed == ETH_SPEED_NUM_NONE)
4328                 return 0; /* do nothing if no SFP */
4329
4330         /* Config full duplex for SFP */
4331         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4332 }
4333
4334 static int
4335 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4336 {
4337         struct hns3_config_mac_mode_cmd *req;
4338         struct hns3_cmd_desc desc;
4339         uint32_t loop_en = 0;
4340         uint8_t val = 0;
4341         int ret;
4342
4343         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4344
4345         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4346         if (enable)
4347                 val = 1;
4348         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4349         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4350         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4351         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4352         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4353         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4354         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4355         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4356         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4357         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4358
4359         /*
4360          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4361          * when receiving frames. Otherwise, CRC will be stripped.
4362          */
4363         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4364                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4365         else
4366                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4367         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4368         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4369         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4370         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4371
4372         ret = hns3_cmd_send(hw, &desc, 1);
4373         if (ret)
4374                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4375
4376         return ret;
4377 }
4378
4379 static int
4380 hns3_get_mac_link_status(struct hns3_hw *hw)
4381 {
4382         struct hns3_link_status_cmd *req;
4383         struct hns3_cmd_desc desc;
4384         int link_status;
4385         int ret;
4386
4387         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4388         ret = hns3_cmd_send(hw, &desc, 1);
4389         if (ret) {
4390                 hns3_err(hw, "get link status cmd failed %d", ret);
4391                 return ETH_LINK_DOWN;
4392         }
4393
4394         req = (struct hns3_link_status_cmd *)desc.data;
4395         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4396
4397         return !!link_status;
4398 }
4399
4400 void
4401 hns3_update_link_status(struct hns3_hw *hw)
4402 {
4403         int state;
4404
4405         state = hns3_get_mac_link_status(hw);
4406         if (state != hw->mac.link_status) {
4407                 hw->mac.link_status = state;
4408                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4409         }
4410 }
4411
4412 static void
4413 hns3_service_handler(void *param)
4414 {
4415         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4416         struct hns3_adapter *hns = eth_dev->data->dev_private;
4417         struct hns3_hw *hw = &hns->hw;
4418
4419         if (!hns3_is_reset_pending(hns)) {
4420                 hns3_update_speed_duplex(eth_dev);
4421                 hns3_update_link_status(hw);
4422         } else
4423                 hns3_warn(hw, "Cancel the query when reset is pending");
4424
4425         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4426 }
4427
4428 static int
4429 hns3_init_hardware(struct hns3_adapter *hns)
4430 {
4431         struct hns3_hw *hw = &hns->hw;
4432         int ret;
4433
4434         ret = hns3_map_tqp(hw);
4435         if (ret) {
4436                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4437                 return ret;
4438         }
4439
4440         ret = hns3_init_umv_space(hw);
4441         if (ret) {
4442                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4443                 return ret;
4444         }
4445
4446         ret = hns3_mac_init(hw);
4447         if (ret) {
4448                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4449                 goto err_mac_init;
4450         }
4451
4452         ret = hns3_init_mgr_tbl(hw);
4453         if (ret) {
4454                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4455                 goto err_mac_init;
4456         }
4457
4458         ret = hns3_promisc_init(hw);
4459         if (ret) {
4460                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4461                              ret);
4462                 goto err_mac_init;
4463         }
4464
4465         ret = hns3_init_vlan_config(hns);
4466         if (ret) {
4467                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4468                 goto err_mac_init;
4469         }
4470
4471         ret = hns3_dcb_init(hw);
4472         if (ret) {
4473                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4474                 goto err_mac_init;
4475         }
4476
4477         ret = hns3_init_fd_config(hns);
4478         if (ret) {
4479                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4480                 goto err_mac_init;
4481         }
4482
4483         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4484         if (ret) {
4485                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4486                 goto err_mac_init;
4487         }
4488
4489         ret = hns3_config_gro(hw, false);
4490         if (ret) {
4491                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4492                 goto err_mac_init;
4493         }
4494
4495         /*
4496          * In the initialization clearing the all hardware mapping relationship
4497          * configurations between queues and interrupt vectors is needed, so
4498          * some error caused by the residual configurations, such as the
4499          * unexpected interrupt, can be avoid.
4500          */
4501         ret = hns3_init_ring_with_vector(hw);
4502         if (ret) {
4503                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4504                 goto err_mac_init;
4505         }
4506
4507         return 0;
4508
4509 err_mac_init:
4510         hns3_uninit_umv_space(hw);
4511         return ret;
4512 }
4513
4514 static int
4515 hns3_clear_hw(struct hns3_hw *hw)
4516 {
4517         struct hns3_cmd_desc desc;
4518         int ret;
4519
4520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4521
4522         ret = hns3_cmd_send(hw, &desc, 1);
4523         if (ret && ret != -EOPNOTSUPP)
4524                 return ret;
4525
4526         return 0;
4527 }
4528
4529 static void
4530 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4531 {
4532         uint32_t val;
4533
4534         /*
4535          * The new firmware support report more hardware error types by
4536          * msix mode. These errors are defined as RAS errors in hardware
4537          * and belong to a different type from the MSI-x errors processed
4538          * by the network driver.
4539          *
4540          * Network driver should open the new error report on initialition
4541          */
4542         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4543         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4544         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4545 }
4546
4547 static int
4548 hns3_init_pf(struct rte_eth_dev *eth_dev)
4549 {
4550         struct rte_device *dev = eth_dev->device;
4551         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4552         struct hns3_adapter *hns = eth_dev->data->dev_private;
4553         struct hns3_hw *hw = &hns->hw;
4554         int ret;
4555
4556         PMD_INIT_FUNC_TRACE();
4557
4558         /* Get hardware io base address from pcie BAR2 IO space */
4559         hw->io_base = pci_dev->mem_resource[2].addr;
4560
4561         /* Firmware command queue initialize */
4562         ret = hns3_cmd_init_queue(hw);
4563         if (ret) {
4564                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4565                 goto err_cmd_init_queue;
4566         }
4567
4568         hns3_clear_all_event_cause(hw);
4569
4570         /* Firmware command initialize */
4571         ret = hns3_cmd_init(hw);
4572         if (ret) {
4573                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4574                 goto err_cmd_init;
4575         }
4576
4577         /*
4578          * To ensure that the hardware environment is clean during
4579          * initialization, the driver actively clear the hardware environment
4580          * during initialization, including PF and corresponding VFs' vlan, mac,
4581          * flow table configurations, etc.
4582          */
4583         ret = hns3_clear_hw(hw);
4584         if (ret) {
4585                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4586                 goto err_cmd_init;
4587         }
4588
4589         hns3_config_all_msix_error(hw, true);
4590
4591         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4592                                          hns3_interrupt_handler,
4593                                          eth_dev);
4594         if (ret) {
4595                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4596                 goto err_intr_callback_register;
4597         }
4598
4599         /* Enable interrupt */
4600         rte_intr_enable(&pci_dev->intr_handle);
4601         hns3_pf_enable_irq0(hw);
4602
4603         /* Get configuration */
4604         ret = hns3_get_configuration(hw);
4605         if (ret) {
4606                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4607                 goto err_get_config;
4608         }
4609
4610         ret = hns3_tqp_stats_init(hw);
4611         if (ret)
4612                 goto err_get_config;
4613
4614         ret = hns3_init_hardware(hns);
4615         if (ret) {
4616                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4617                 goto err_init_hw;
4618         }
4619
4620         /* Initialize flow director filter list & hash */
4621         ret = hns3_fdir_filter_init(hns);
4622         if (ret) {
4623                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4624                 goto err_fdir;
4625         }
4626
4627         hns3_set_default_rss_args(hw);
4628
4629         ret = hns3_enable_hw_error_intr(hns, true);
4630         if (ret) {
4631                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4632                              ret);
4633                 goto err_enable_intr;
4634         }
4635
4636         return 0;
4637
4638 err_enable_intr:
4639         hns3_fdir_filter_uninit(hns);
4640 err_fdir:
4641         hns3_uninit_umv_space(hw);
4642 err_init_hw:
4643         hns3_tqp_stats_uninit(hw);
4644 err_get_config:
4645         hns3_pf_disable_irq0(hw);
4646         rte_intr_disable(&pci_dev->intr_handle);
4647         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4648                              eth_dev);
4649 err_intr_callback_register:
4650 err_cmd_init:
4651         hns3_cmd_uninit(hw);
4652         hns3_cmd_destroy_queue(hw);
4653 err_cmd_init_queue:
4654         hw->io_base = NULL;
4655
4656         return ret;
4657 }
4658
4659 static void
4660 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4661 {
4662         struct hns3_adapter *hns = eth_dev->data->dev_private;
4663         struct rte_device *dev = eth_dev->device;
4664         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4665         struct hns3_hw *hw = &hns->hw;
4666
4667         PMD_INIT_FUNC_TRACE();
4668
4669         hns3_enable_hw_error_intr(hns, false);
4670         hns3_rss_uninit(hns);
4671         (void)hns3_config_gro(hw, false);
4672         hns3_promisc_uninit(hw);
4673         hns3_fdir_filter_uninit(hns);
4674         hns3_uninit_umv_space(hw);
4675         hns3_tqp_stats_uninit(hw);
4676         hns3_pf_disable_irq0(hw);
4677         rte_intr_disable(&pci_dev->intr_handle);
4678         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4679                              eth_dev);
4680         hns3_config_all_msix_error(hw, false);
4681         hns3_cmd_uninit(hw);
4682         hns3_cmd_destroy_queue(hw);
4683         hw->io_base = NULL;
4684 }
4685
4686 static int
4687 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4688 {
4689         struct hns3_hw *hw = &hns->hw;
4690         int ret;
4691
4692         ret = hns3_dcb_cfg_update(hns);
4693         if (ret)
4694                 return ret;
4695
4696         ret = hns3_init_queues(hns, reset_queue);
4697         if (ret) {
4698                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4699                 return ret;
4700         }
4701
4702         ret = hns3_cfg_mac_mode(hw, true);
4703         if (ret) {
4704                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4705                 goto err_config_mac_mode;
4706         }
4707         return 0;
4708
4709 err_config_mac_mode:
4710         hns3_dev_release_mbufs(hns);
4711         hns3_reset_all_tqps(hns);
4712         return ret;
4713 }
4714
4715 static int
4716 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4717 {
4718         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4720         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4722         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4723         uint32_t intr_vector;
4724         uint16_t q_id;
4725         int ret;
4726
4727         if (dev->data->dev_conf.intr_conf.rxq == 0)
4728                 return 0;
4729
4730         /* disable uio/vfio intr/eventfd mapping */
4731         rte_intr_disable(intr_handle);
4732
4733         /* check and configure queue intr-vector mapping */
4734         if (rte_intr_cap_multiple(intr_handle) ||
4735             !RTE_ETH_DEV_SRIOV(dev).active) {
4736                 intr_vector = hw->used_rx_queues;
4737                 /* creates event fd for each intr vector when MSIX is used */
4738                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4739                         return -EINVAL;
4740         }
4741         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4742                 intr_handle->intr_vec =
4743                         rte_zmalloc("intr_vec",
4744                                     hw->used_rx_queues * sizeof(int), 0);
4745                 if (intr_handle->intr_vec == NULL) {
4746                         hns3_err(hw, "Failed to allocate %d rx_queues"
4747                                      " intr_vec", hw->used_rx_queues);
4748                         ret = -ENOMEM;
4749                         goto alloc_intr_vec_error;
4750                 }
4751         }
4752
4753         if (rte_intr_allow_others(intr_handle)) {
4754                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4755                 base = RTE_INTR_VEC_RXTX_OFFSET;
4756         }
4757         if (rte_intr_dp_is_en(intr_handle)) {
4758                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4759                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4760                                                          HNS3_RING_TYPE_RX,
4761                                                          q_id);
4762                         if (ret)
4763                                 goto bind_vector_error;
4764                         intr_handle->intr_vec[q_id] = vec;
4765                         if (vec < base + intr_handle->nb_efd - 1)
4766                                 vec++;
4767                 }
4768         }
4769         rte_intr_enable(intr_handle);
4770         return 0;
4771
4772 bind_vector_error:
4773         rte_intr_efd_disable(intr_handle);
4774         if (intr_handle->intr_vec) {
4775                 free(intr_handle->intr_vec);
4776                 intr_handle->intr_vec = NULL;
4777         }
4778         return ret;
4779 alloc_intr_vec_error:
4780         rte_intr_efd_disable(intr_handle);
4781         return ret;
4782 }
4783
4784 static int
4785 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4786 {
4787         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4789         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4790         uint16_t q_id;
4791         int ret;
4792
4793         if (dev->data->dev_conf.intr_conf.rxq == 0)
4794                 return 0;
4795
4796         if (rte_intr_dp_is_en(intr_handle)) {
4797                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4798                         ret = hns3_bind_ring_with_vector(hw,
4799                                         intr_handle->intr_vec[q_id], true,
4800                                         HNS3_RING_TYPE_RX, q_id);
4801                         if (ret)
4802                                 return ret;
4803                 }
4804         }
4805
4806         return 0;
4807 }
4808
4809 static void
4810 hns3_restore_filter(struct rte_eth_dev *dev)
4811 {
4812         hns3_restore_rss_filter(dev);
4813 }
4814
4815 static int
4816 hns3_dev_start(struct rte_eth_dev *dev)
4817 {
4818         struct hns3_adapter *hns = dev->data->dev_private;
4819         struct hns3_hw *hw = &hns->hw;
4820         int ret;
4821
4822         PMD_INIT_FUNC_TRACE();
4823         if (rte_atomic16_read(&hw->reset.resetting))
4824                 return -EBUSY;
4825
4826         rte_spinlock_lock(&hw->lock);
4827         hw->adapter_state = HNS3_NIC_STARTING;
4828
4829         ret = hns3_do_start(hns, true);
4830         if (ret) {
4831                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4832                 rte_spinlock_unlock(&hw->lock);
4833                 return ret;
4834         }
4835         ret = hns3_map_rx_interrupt(dev);
4836         if (ret) {
4837                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4838                 rte_spinlock_unlock(&hw->lock);
4839                 return ret;
4840         }
4841
4842         /*
4843          * There are three register used to control the status of a TQP
4844          * (contains a pair of Tx queue and Rx queue) in the new version network
4845          * engine. One is used to control the enabling of Tx queue, the other is
4846          * used to control the enabling of Rx queue, and the last is the master
4847          * switch used to control the enabling of the tqp. The Tx register and
4848          * TQP register must be enabled at the same time to enable a Tx queue.
4849          * The same applies to the Rx queue. For the older network engine, this
4850          * function only refresh the enabled flag, and it is used to update the
4851          * status of queue in the dpdk framework.
4852          */
4853         ret = hns3_start_all_txqs(dev);
4854         if (ret) {
4855                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4856                 rte_spinlock_unlock(&hw->lock);
4857                 return ret;
4858         }
4859
4860         ret = hns3_start_all_rxqs(dev);
4861         if (ret) {
4862                 hns3_stop_all_txqs(dev);
4863                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4864                 rte_spinlock_unlock(&hw->lock);
4865                 return ret;
4866         }
4867
4868         hw->adapter_state = HNS3_NIC_STARTED;
4869         rte_spinlock_unlock(&hw->lock);
4870
4871         hns3_rx_scattered_calc(dev);
4872         hns3_set_rxtx_function(dev);
4873         hns3_mp_req_start_rxtx(dev);
4874         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4875
4876         hns3_restore_filter(dev);
4877
4878         /* Enable interrupt of all rx queues before enabling queues */
4879         hns3_dev_all_rx_queue_intr_enable(hw, true);
4880
4881         /*
4882          * After finished the initialization, enable tqps to receive/transmit
4883          * packets and refresh all queue status.
4884          */
4885         hns3_start_tqps(hw);
4886
4887         hns3_info(hw, "hns3 dev start successful!");
4888         return 0;
4889 }
4890
4891 static int
4892 hns3_do_stop(struct hns3_adapter *hns)
4893 {
4894         struct hns3_hw *hw = &hns->hw;
4895         int ret;
4896
4897         ret = hns3_cfg_mac_mode(hw, false);
4898         if (ret)
4899                 return ret;
4900         hw->mac.link_status = ETH_LINK_DOWN;
4901
4902         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4903                 hns3_configure_all_mac_addr(hns, true);
4904                 ret = hns3_reset_all_tqps(hns);
4905                 if (ret) {
4906                         hns3_err(hw, "failed to reset all queues ret = %d.",
4907                                  ret);
4908                         return ret;
4909                 }
4910         }
4911         hw->mac.default_addr_setted = false;
4912         return 0;
4913 }
4914
4915 static void
4916 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4917 {
4918         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4919         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4920         struct hns3_adapter *hns = dev->data->dev_private;
4921         struct hns3_hw *hw = &hns->hw;
4922         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4923         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4924         uint16_t q_id;
4925
4926         if (dev->data->dev_conf.intr_conf.rxq == 0)
4927                 return;
4928
4929         /* unmap the ring with vector */
4930         if (rte_intr_allow_others(intr_handle)) {
4931                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4932                 base = RTE_INTR_VEC_RXTX_OFFSET;
4933         }
4934         if (rte_intr_dp_is_en(intr_handle)) {
4935                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4936                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4937                                                          HNS3_RING_TYPE_RX,
4938                                                          q_id);
4939                         if (vec < base + intr_handle->nb_efd - 1)
4940                                 vec++;
4941                 }
4942         }
4943         /* Clean datapath event and queue/vec mapping */
4944         rte_intr_efd_disable(intr_handle);
4945         if (intr_handle->intr_vec) {
4946                 rte_free(intr_handle->intr_vec);
4947                 intr_handle->intr_vec = NULL;
4948         }
4949 }
4950
4951 static void
4952 hns3_dev_stop(struct rte_eth_dev *dev)
4953 {
4954         struct hns3_adapter *hns = dev->data->dev_private;
4955         struct hns3_hw *hw = &hns->hw;
4956
4957         PMD_INIT_FUNC_TRACE();
4958
4959         hw->adapter_state = HNS3_NIC_STOPPING;
4960         hns3_set_rxtx_function(dev);
4961         rte_wmb();
4962         /* Disable datapath on secondary process. */
4963         hns3_mp_req_stop_rxtx(dev);
4964         /* Prevent crashes when queues are still in use. */
4965         rte_delay_ms(hw->tqps_num);
4966
4967         rte_spinlock_lock(&hw->lock);
4968         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4969                 hns3_stop_tqps(hw);
4970                 hns3_do_stop(hns);
4971                 hns3_unmap_rx_interrupt(dev);
4972                 hns3_dev_release_mbufs(hns);
4973                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4974         }
4975         hns3_rx_scattered_reset(dev);
4976         rte_eal_alarm_cancel(hns3_service_handler, dev);
4977         rte_spinlock_unlock(&hw->lock);
4978 }
4979
4980 static int
4981 hns3_dev_close(struct rte_eth_dev *eth_dev)
4982 {
4983         struct hns3_adapter *hns = eth_dev->data->dev_private;
4984         struct hns3_hw *hw = &hns->hw;
4985
4986         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4987                 rte_free(eth_dev->process_private);
4988                 eth_dev->process_private = NULL;
4989                 return 0;
4990         }
4991
4992         if (hw->adapter_state == HNS3_NIC_STARTED)
4993                 hns3_dev_stop(eth_dev);
4994
4995         hw->adapter_state = HNS3_NIC_CLOSING;
4996         hns3_reset_abort(hns);
4997         hw->adapter_state = HNS3_NIC_CLOSED;
4998
4999         hns3_configure_all_mc_mac_addr(hns, true);
5000         hns3_remove_all_vlan_table(hns);
5001         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5002         hns3_uninit_pf(eth_dev);
5003         hns3_free_all_queues(eth_dev);
5004         rte_free(hw->reset.wait_data);
5005         rte_free(eth_dev->process_private);
5006         eth_dev->process_private = NULL;
5007         hns3_mp_uninit_primary();
5008         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
5009
5010         return 0;
5011 }
5012
5013 static int
5014 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5015 {
5016         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5018
5019         fc_conf->pause_time = pf->pause_time;
5020
5021         /* return fc current mode */
5022         switch (hw->current_mode) {
5023         case HNS3_FC_FULL:
5024                 fc_conf->mode = RTE_FC_FULL;
5025                 break;
5026         case HNS3_FC_TX_PAUSE:
5027                 fc_conf->mode = RTE_FC_TX_PAUSE;
5028                 break;
5029         case HNS3_FC_RX_PAUSE:
5030                 fc_conf->mode = RTE_FC_RX_PAUSE;
5031                 break;
5032         case HNS3_FC_NONE:
5033         default:
5034                 fc_conf->mode = RTE_FC_NONE;
5035                 break;
5036         }
5037
5038         return 0;
5039 }
5040
5041 static void
5042 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5043 {
5044         switch (mode) {
5045         case RTE_FC_NONE:
5046                 hw->requested_mode = HNS3_FC_NONE;
5047                 break;
5048         case RTE_FC_RX_PAUSE:
5049                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5050                 break;
5051         case RTE_FC_TX_PAUSE:
5052                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5053                 break;
5054         case RTE_FC_FULL:
5055                 hw->requested_mode = HNS3_FC_FULL;
5056                 break;
5057         default:
5058                 hw->requested_mode = HNS3_FC_NONE;
5059                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5060                           "configured to RTE_FC_NONE", mode);
5061                 break;
5062         }
5063 }
5064
5065 static int
5066 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5067 {
5068         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5070         int ret;
5071
5072         if (fc_conf->high_water || fc_conf->low_water ||
5073             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5074                 hns3_err(hw, "Unsupported flow control settings specified, "
5075                          "high_water(%u), low_water(%u), send_xon(%u) and "
5076                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5077                          fc_conf->high_water, fc_conf->low_water,
5078                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5079                 return -EINVAL;
5080         }
5081         if (fc_conf->autoneg) {
5082                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5083                 return -EINVAL;
5084         }
5085         if (!fc_conf->pause_time) {
5086                 hns3_err(hw, "Invalid pause time %d setting.",
5087                          fc_conf->pause_time);
5088                 return -EINVAL;
5089         }
5090
5091         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5092             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5093                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5094                          "current_fc_status = %d", hw->current_fc_status);
5095                 return -EOPNOTSUPP;
5096         }
5097
5098         hns3_get_fc_mode(hw, fc_conf->mode);
5099         if (hw->requested_mode == hw->current_mode &&
5100             pf->pause_time == fc_conf->pause_time)
5101                 return 0;
5102
5103         rte_spinlock_lock(&hw->lock);
5104         ret = hns3_fc_enable(dev, fc_conf);
5105         rte_spinlock_unlock(&hw->lock);
5106
5107         return ret;
5108 }
5109
5110 static int
5111 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5112                             struct rte_eth_pfc_conf *pfc_conf)
5113 {
5114         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5116         uint8_t priority;
5117         int ret;
5118
5119         if (!hns3_dev_dcb_supported(hw)) {
5120                 hns3_err(hw, "This port does not support dcb configurations.");
5121                 return -EOPNOTSUPP;
5122         }
5123
5124         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5125             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5126                 hns3_err(hw, "Unsupported flow control settings specified, "
5127                          "high_water(%u), low_water(%u), send_xon(%u) and "
5128                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5129                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5130                          pfc_conf->fc.send_xon,
5131                          pfc_conf->fc.mac_ctrl_frame_fwd);
5132                 return -EINVAL;
5133         }
5134         if (pfc_conf->fc.autoneg) {
5135                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5136                 return -EINVAL;
5137         }
5138         if (pfc_conf->fc.pause_time == 0) {
5139                 hns3_err(hw, "Invalid pause time %d setting.",
5140                          pfc_conf->fc.pause_time);
5141                 return -EINVAL;
5142         }
5143
5144         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5145             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5146                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5147                              "current_fc_status = %d", hw->current_fc_status);
5148                 return -EOPNOTSUPP;
5149         }
5150
5151         priority = pfc_conf->priority;
5152         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5153         if (hw->dcb_info.pfc_en & BIT(priority) &&
5154             hw->requested_mode == hw->current_mode &&
5155             pfc_conf->fc.pause_time == pf->pause_time)
5156                 return 0;
5157
5158         rte_spinlock_lock(&hw->lock);
5159         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5160         rte_spinlock_unlock(&hw->lock);
5161
5162         return ret;
5163 }
5164
5165 static int
5166 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5167 {
5168         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5170         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5171         int i;
5172
5173         rte_spinlock_lock(&hw->lock);
5174         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5175                 dcb_info->nb_tcs = pf->local_max_tc;
5176         else
5177                 dcb_info->nb_tcs = 1;
5178
5179         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5180                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5181         for (i = 0; i < dcb_info->nb_tcs; i++)
5182                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5183
5184         for (i = 0; i < hw->num_tc; i++) {
5185                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5186                 dcb_info->tc_queue.tc_txq[0][i].base =
5187                                                 hw->tc_queue[i].tqp_offset;
5188                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5189                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5190                                                 hw->tc_queue[i].tqp_count;
5191         }
5192         rte_spinlock_unlock(&hw->lock);
5193
5194         return 0;
5195 }
5196
5197 static int
5198 hns3_reinit_dev(struct hns3_adapter *hns)
5199 {
5200         struct hns3_hw *hw = &hns->hw;
5201         int ret;
5202
5203         ret = hns3_cmd_init(hw);
5204         if (ret) {
5205                 hns3_err(hw, "Failed to init cmd: %d", ret);
5206                 return ret;
5207         }
5208
5209         ret = hns3_reset_all_tqps(hns);
5210         if (ret) {
5211                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5212                 return ret;
5213         }
5214
5215         ret = hns3_init_hardware(hns);
5216         if (ret) {
5217                 hns3_err(hw, "Failed to init hardware: %d", ret);
5218                 return ret;
5219         }
5220
5221         ret = hns3_enable_hw_error_intr(hns, true);
5222         if (ret) {
5223                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5224                              ret);
5225                 return ret;
5226         }
5227         hns3_info(hw, "Reset done, driver initialization finished.");
5228
5229         return 0;
5230 }
5231
5232 static bool
5233 is_pf_reset_done(struct hns3_hw *hw)
5234 {
5235         uint32_t val, reg, reg_bit;
5236
5237         switch (hw->reset.level) {
5238         case HNS3_IMP_RESET:
5239                 reg = HNS3_GLOBAL_RESET_REG;
5240                 reg_bit = HNS3_IMP_RESET_BIT;
5241                 break;
5242         case HNS3_GLOBAL_RESET:
5243                 reg = HNS3_GLOBAL_RESET_REG;
5244                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5245                 break;
5246         case HNS3_FUNC_RESET:
5247                 reg = HNS3_FUN_RST_ING;
5248                 reg_bit = HNS3_FUN_RST_ING_B;
5249                 break;
5250         case HNS3_FLR_RESET:
5251         default:
5252                 hns3_err(hw, "Wait for unsupported reset level: %d",
5253                          hw->reset.level);
5254                 return true;
5255         }
5256         val = hns3_read_dev(hw, reg);
5257         if (hns3_get_bit(val, reg_bit))
5258                 return false;
5259         else
5260                 return true;
5261 }
5262
5263 bool
5264 hns3_is_reset_pending(struct hns3_adapter *hns)
5265 {
5266         struct hns3_hw *hw = &hns->hw;
5267         enum hns3_reset_level reset;
5268
5269         hns3_check_event_cause(hns, NULL);
5270         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5271         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5272                 hns3_warn(hw, "High level reset %d is pending", reset);
5273                 return true;
5274         }
5275         reset = hns3_get_reset_level(hns, &hw->reset.request);
5276         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5277                 hns3_warn(hw, "High level reset %d is request", reset);
5278                 return true;
5279         }
5280         return false;
5281 }
5282
5283 static int
5284 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5285 {
5286         struct hns3_hw *hw = &hns->hw;
5287         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5288         struct timeval tv;
5289
5290         if (wait_data->result == HNS3_WAIT_SUCCESS)
5291                 return 0;
5292         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5293                 gettimeofday(&tv, NULL);
5294                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5295                           tv.tv_sec, tv.tv_usec);
5296                 return -ETIME;
5297         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5298                 return -EAGAIN;
5299
5300         wait_data->hns = hns;
5301         wait_data->check_completion = is_pf_reset_done;
5302         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5303                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5304         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5305         wait_data->count = HNS3_RESET_WAIT_CNT;
5306         wait_data->result = HNS3_WAIT_REQUEST;
5307         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5308         return -EAGAIN;
5309 }
5310
5311 static int
5312 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5313 {
5314         struct hns3_cmd_desc desc;
5315         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5316
5317         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5318         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5319         req->fun_reset_vfid = func_id;
5320
5321         return hns3_cmd_send(hw, &desc, 1);
5322 }
5323
5324 static int
5325 hns3_imp_reset_cmd(struct hns3_hw *hw)
5326 {
5327         struct hns3_cmd_desc desc;
5328
5329         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5330         desc.data[0] = 0xeedd;
5331
5332         return hns3_cmd_send(hw, &desc, 1);
5333 }
5334
5335 static void
5336 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5337 {
5338         struct hns3_hw *hw = &hns->hw;
5339         struct timeval tv;
5340         uint32_t val;
5341
5342         gettimeofday(&tv, NULL);
5343         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5344             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5345                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5346                           tv.tv_sec, tv.tv_usec);
5347                 return;
5348         }
5349
5350         switch (reset_level) {
5351         case HNS3_IMP_RESET:
5352                 hns3_imp_reset_cmd(hw);
5353                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5354                           tv.tv_sec, tv.tv_usec);
5355                 break;
5356         case HNS3_GLOBAL_RESET:
5357                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5358                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5359                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5360                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5361                           tv.tv_sec, tv.tv_usec);
5362                 break;
5363         case HNS3_FUNC_RESET:
5364                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5365                           tv.tv_sec, tv.tv_usec);
5366                 /* schedule again to check later */
5367                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5368                 hns3_schedule_reset(hns);
5369                 break;
5370         default:
5371                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5372                 return;
5373         }
5374         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5375 }
5376
5377 static enum hns3_reset_level
5378 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5379 {
5380         struct hns3_hw *hw = &hns->hw;
5381         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5382
5383         /* Return the highest priority reset level amongst all */
5384         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5385                 reset_level = HNS3_IMP_RESET;
5386         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5387                 reset_level = HNS3_GLOBAL_RESET;
5388         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5389                 reset_level = HNS3_FUNC_RESET;
5390         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5391                 reset_level = HNS3_FLR_RESET;
5392
5393         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5394                 return HNS3_NONE_RESET;
5395
5396         return reset_level;
5397 }
5398
5399 static void
5400 hns3_record_imp_error(struct hns3_adapter *hns)
5401 {
5402         struct hns3_hw *hw = &hns->hw;
5403         uint32_t reg_val;
5404
5405         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5406         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5407                 hns3_warn(hw, "Detected IMP RD poison!");
5408                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5409                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5410                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5411         }
5412
5413         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5414                 hns3_warn(hw, "Detected IMP CMDQ error!");
5415                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5416                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5417                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5418         }
5419 }
5420
5421 static int
5422 hns3_prepare_reset(struct hns3_adapter *hns)
5423 {
5424         struct hns3_hw *hw = &hns->hw;
5425         uint32_t reg_val;
5426         int ret;
5427
5428         switch (hw->reset.level) {
5429         case HNS3_FUNC_RESET:
5430                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5431                 if (ret)
5432                         return ret;
5433
5434                 /*
5435                  * After performaning pf reset, it is not necessary to do the
5436                  * mailbox handling or send any command to firmware, because
5437                  * any mailbox handling or command to firmware is only valid
5438                  * after hns3_cmd_init is called.
5439                  */
5440                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5441                 hw->reset.stats.request_cnt++;
5442                 break;
5443         case HNS3_IMP_RESET:
5444                 hns3_record_imp_error(hns);
5445                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5446                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5447                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5448                 break;
5449         default:
5450                 break;
5451         }
5452         return 0;
5453 }
5454
5455 static int
5456 hns3_set_rst_done(struct hns3_hw *hw)
5457 {
5458         struct hns3_pf_rst_done_cmd *req;
5459         struct hns3_cmd_desc desc;
5460
5461         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5462         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5463         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5464         return hns3_cmd_send(hw, &desc, 1);
5465 }
5466
5467 static int
5468 hns3_stop_service(struct hns3_adapter *hns)
5469 {
5470         struct hns3_hw *hw = &hns->hw;
5471         struct rte_eth_dev *eth_dev;
5472
5473         eth_dev = &rte_eth_devices[hw->data->port_id];
5474         if (hw->adapter_state == HNS3_NIC_STARTED)
5475                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5476         hw->mac.link_status = ETH_LINK_DOWN;
5477
5478         hns3_set_rxtx_function(eth_dev);
5479         rte_wmb();
5480         /* Disable datapath on secondary process. */
5481         hns3_mp_req_stop_rxtx(eth_dev);
5482         rte_delay_ms(hw->tqps_num);
5483
5484         rte_spinlock_lock(&hw->lock);
5485         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5486             hw->adapter_state == HNS3_NIC_STOPPING) {
5487                 hns3_enable_all_queues(hw, false);
5488                 hns3_do_stop(hns);
5489                 hw->reset.mbuf_deferred_free = true;
5490         } else
5491                 hw->reset.mbuf_deferred_free = false;
5492
5493         /*
5494          * It is cumbersome for hardware to pick-and-choose entries for deletion
5495          * from table space. Hence, for function reset software intervention is
5496          * required to delete the entries
5497          */
5498         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5499                 hns3_configure_all_mc_mac_addr(hns, true);
5500         rte_spinlock_unlock(&hw->lock);
5501
5502         return 0;
5503 }
5504
5505 static int
5506 hns3_start_service(struct hns3_adapter *hns)
5507 {
5508         struct hns3_hw *hw = &hns->hw;
5509         struct rte_eth_dev *eth_dev;
5510
5511         if (hw->reset.level == HNS3_IMP_RESET ||
5512             hw->reset.level == HNS3_GLOBAL_RESET)
5513                 hns3_set_rst_done(hw);
5514         eth_dev = &rte_eth_devices[hw->data->port_id];
5515         hns3_set_rxtx_function(eth_dev);
5516         hns3_mp_req_start_rxtx(eth_dev);
5517         if (hw->adapter_state == HNS3_NIC_STARTED) {
5518                 hns3_service_handler(eth_dev);
5519
5520                 /* Enable interrupt of all rx queues before enabling queues */
5521                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5522                 /*
5523                  * When finished the initialization, enable queues to receive
5524                  * and transmit packets.
5525                  */
5526                 hns3_enable_all_queues(hw, true);
5527         }
5528
5529         return 0;
5530 }
5531
5532 static int
5533 hns3_restore_conf(struct hns3_adapter *hns)
5534 {
5535         struct hns3_hw *hw = &hns->hw;
5536         int ret;
5537
5538         ret = hns3_configure_all_mac_addr(hns, false);
5539         if (ret)
5540                 return ret;
5541
5542         ret = hns3_configure_all_mc_mac_addr(hns, false);
5543         if (ret)
5544                 goto err_mc_mac;
5545
5546         ret = hns3_dev_promisc_restore(hns);
5547         if (ret)
5548                 goto err_promisc;
5549
5550         ret = hns3_restore_vlan_table(hns);
5551         if (ret)
5552                 goto err_promisc;
5553
5554         ret = hns3_restore_vlan_conf(hns);
5555         if (ret)
5556                 goto err_promisc;
5557
5558         ret = hns3_restore_all_fdir_filter(hns);
5559         if (ret)
5560                 goto err_promisc;
5561
5562         ret = hns3_restore_rx_interrupt(hw);
5563         if (ret)
5564                 goto err_promisc;
5565
5566         ret = hns3_restore_gro_conf(hw);
5567         if (ret)
5568                 goto err_promisc;
5569
5570         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5571                 ret = hns3_do_start(hns, false);
5572                 if (ret)
5573                         goto err_promisc;
5574                 hns3_info(hw, "hns3 dev restart successful!");
5575         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5576                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5577         return 0;
5578
5579 err_promisc:
5580         hns3_configure_all_mc_mac_addr(hns, true);
5581 err_mc_mac:
5582         hns3_configure_all_mac_addr(hns, true);
5583         return ret;
5584 }
5585
5586 static void
5587 hns3_reset_service(void *param)
5588 {
5589         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5590         struct hns3_hw *hw = &hns->hw;
5591         enum hns3_reset_level reset_level;
5592         struct timeval tv_delta;
5593         struct timeval tv_start;
5594         struct timeval tv;
5595         uint64_t msec;
5596         int ret;
5597
5598         /*
5599          * The interrupt is not triggered within the delay time.
5600          * The interrupt may have been lost. It is necessary to handle
5601          * the interrupt to recover from the error.
5602          */
5603         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5604                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5605                 hns3_err(hw, "Handling interrupts in delayed tasks");
5606                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5607                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5608                 if (reset_level == HNS3_NONE_RESET) {
5609                         hns3_err(hw, "No reset level is set, try IMP reset");
5610                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5611                 }
5612         }
5613         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5614
5615         /*
5616          * Check if there is any ongoing reset in the hardware. This status can
5617          * be checked from reset_pending. If there is then, we need to wait for
5618          * hardware to complete reset.
5619          *    a. If we are able to figure out in reasonable time that hardware
5620          *       has fully resetted then, we can proceed with driver, client
5621          *       reset.
5622          *    b. else, we can come back later to check this status so re-sched
5623          *       now.
5624          */
5625         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5626         if (reset_level != HNS3_NONE_RESET) {
5627                 gettimeofday(&tv_start, NULL);
5628                 ret = hns3_reset_process(hns, reset_level);
5629                 gettimeofday(&tv, NULL);
5630                 timersub(&tv, &tv_start, &tv_delta);
5631                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5632                        tv_delta.tv_usec / USEC_PER_MSEC;
5633                 if (msec > HNS3_RESET_PROCESS_MS)
5634                         hns3_err(hw, "%d handle long time delta %" PRIx64
5635                                      " ms time=%ld.%.6ld",
5636                                  hw->reset.level, msec,
5637                                  tv.tv_sec, tv.tv_usec);
5638                 if (ret == -EAGAIN)
5639                         return;
5640         }
5641
5642         /* Check if we got any *new* reset requests to be honored */
5643         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5644         if (reset_level != HNS3_NONE_RESET)
5645                 hns3_msix_process(hns, reset_level);
5646 }
5647
5648 static const struct eth_dev_ops hns3_eth_dev_ops = {
5649         .dev_configure      = hns3_dev_configure,
5650         .dev_start          = hns3_dev_start,
5651         .dev_stop           = hns3_dev_stop,
5652         .dev_close          = hns3_dev_close,
5653         .promiscuous_enable = hns3_dev_promiscuous_enable,
5654         .promiscuous_disable = hns3_dev_promiscuous_disable,
5655         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5656         .allmulticast_disable = hns3_dev_allmulticast_disable,
5657         .mtu_set            = hns3_dev_mtu_set,
5658         .stats_get          = hns3_stats_get,
5659         .stats_reset        = hns3_stats_reset,
5660         .xstats_get         = hns3_dev_xstats_get,
5661         .xstats_get_names   = hns3_dev_xstats_get_names,
5662         .xstats_reset       = hns3_dev_xstats_reset,
5663         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5664         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5665         .dev_infos_get          = hns3_dev_infos_get,
5666         .fw_version_get         = hns3_fw_version_get,
5667         .rx_queue_setup         = hns3_rx_queue_setup,
5668         .tx_queue_setup         = hns3_tx_queue_setup,
5669         .rx_queue_release       = hns3_dev_rx_queue_release,
5670         .tx_queue_release       = hns3_dev_tx_queue_release,
5671         .rx_queue_start         = hns3_dev_rx_queue_start,
5672         .rx_queue_stop          = hns3_dev_rx_queue_stop,
5673         .tx_queue_start         = hns3_dev_tx_queue_start,
5674         .tx_queue_stop          = hns3_dev_tx_queue_stop,
5675         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5676         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5677         .rxq_info_get           = hns3_rxq_info_get,
5678         .txq_info_get           = hns3_txq_info_get,
5679         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
5680         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
5681         .flow_ctrl_get          = hns3_flow_ctrl_get,
5682         .flow_ctrl_set          = hns3_flow_ctrl_set,
5683         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5684         .mac_addr_add           = hns3_add_mac_addr,
5685         .mac_addr_remove        = hns3_remove_mac_addr,
5686         .mac_addr_set           = hns3_set_default_mac_addr,
5687         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5688         .link_update            = hns3_dev_link_update,
5689         .rss_hash_update        = hns3_dev_rss_hash_update,
5690         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5691         .reta_update            = hns3_dev_rss_reta_update,
5692         .reta_query             = hns3_dev_rss_reta_query,
5693         .filter_ctrl            = hns3_dev_filter_ctrl,
5694         .vlan_filter_set        = hns3_vlan_filter_set,
5695         .vlan_tpid_set          = hns3_vlan_tpid_set,
5696         .vlan_offload_set       = hns3_vlan_offload_set,
5697         .vlan_pvid_set          = hns3_vlan_pvid_set,
5698         .get_reg                = hns3_get_regs,
5699         .get_dcb_info           = hns3_get_dcb_info,
5700         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5701 };
5702
5703 static const struct hns3_reset_ops hns3_reset_ops = {
5704         .reset_service       = hns3_reset_service,
5705         .stop_service        = hns3_stop_service,
5706         .prepare_reset       = hns3_prepare_reset,
5707         .wait_hardware_ready = hns3_wait_hardware_ready,
5708         .reinit_dev          = hns3_reinit_dev,
5709         .restore_conf        = hns3_restore_conf,
5710         .start_service       = hns3_start_service,
5711 };
5712
5713 static int
5714 hns3_dev_init(struct rte_eth_dev *eth_dev)
5715 {
5716         struct hns3_adapter *hns = eth_dev->data->dev_private;
5717         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
5718         struct rte_ether_addr *eth_addr;
5719         struct hns3_hw *hw = &hns->hw;
5720         int ret;
5721
5722         PMD_INIT_FUNC_TRACE();
5723
5724         eth_dev->process_private = (struct hns3_process_private *)
5725             rte_zmalloc_socket("hns3_filter_list",
5726                                sizeof(struct hns3_process_private),
5727                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5728         if (eth_dev->process_private == NULL) {
5729                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5730                 return -ENOMEM;
5731         }
5732         /* initialize flow filter lists */
5733         hns3_filterlist_init(eth_dev);
5734
5735         hns3_set_rxtx_function(eth_dev);
5736         eth_dev->dev_ops = &hns3_eth_dev_ops;
5737         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5738                 ret = hns3_mp_init_secondary();
5739                 if (ret) {
5740                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
5741                                      "process, ret = %d", ret);
5742                         goto err_mp_init_secondary;
5743                 }
5744
5745                 hw->secondary_cnt++;
5746                 return 0;
5747         }
5748
5749         ret = hns3_mp_init_primary();
5750         if (ret) {
5751                 PMD_INIT_LOG(ERR,
5752                              "Failed to init for primary process, ret = %d",
5753                              ret);
5754                 goto err_mp_init_primary;
5755         }
5756
5757         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5758         hns->is_vf = false;
5759         hw->data = eth_dev->data;
5760
5761         /*
5762          * Set default max packet size according to the mtu
5763          * default vale in DPDK frame.
5764          */
5765         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5766
5767         ret = hns3_reset_init(hw);
5768         if (ret)
5769                 goto err_init_reset;
5770         hw->reset.ops = &hns3_reset_ops;
5771
5772         ret = hns3_init_pf(eth_dev);
5773         if (ret) {
5774                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5775                 goto err_init_pf;
5776         }
5777
5778         /* Allocate memory for storing MAC addresses */
5779         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5780                                                sizeof(struct rte_ether_addr) *
5781                                                HNS3_UC_MACADDR_NUM, 0);
5782         if (eth_dev->data->mac_addrs == NULL) {
5783                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5784                              "to store MAC addresses",
5785                              sizeof(struct rte_ether_addr) *
5786                              HNS3_UC_MACADDR_NUM);
5787                 ret = -ENOMEM;
5788                 goto err_rte_zmalloc;
5789         }
5790
5791         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
5792         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
5793                 rte_eth_random_addr(hw->mac.mac_addr);
5794                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
5795                                 (struct rte_ether_addr *)hw->mac.mac_addr);
5796                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
5797                           "unicast address, using random MAC address %s",
5798                           mac_str);
5799         }
5800         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5801                             &eth_dev->data->mac_addrs[0]);
5802
5803         hw->adapter_state = HNS3_NIC_INITIALIZED;
5804
5805         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5806                 hns3_err(hw, "Reschedule reset service after dev_init");
5807                 hns3_schedule_reset(hns);
5808         } else {
5809                 /* IMP will wait ready flag before reset */
5810                 hns3_notify_reset_ready(hw, false);
5811         }
5812
5813         hns3_info(hw, "hns3 dev initialization successful!");
5814         return 0;
5815
5816 err_rte_zmalloc:
5817         hns3_uninit_pf(eth_dev);
5818
5819 err_init_pf:
5820         rte_free(hw->reset.wait_data);
5821
5822 err_init_reset:
5823         hns3_mp_uninit_primary();
5824
5825 err_mp_init_primary:
5826 err_mp_init_secondary:
5827         eth_dev->dev_ops = NULL;
5828         eth_dev->rx_pkt_burst = NULL;
5829         eth_dev->tx_pkt_burst = NULL;
5830         eth_dev->tx_pkt_prepare = NULL;
5831         rte_free(eth_dev->process_private);
5832         eth_dev->process_private = NULL;
5833         return ret;
5834 }
5835
5836 static int
5837 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5838 {
5839         struct hns3_adapter *hns = eth_dev->data->dev_private;
5840         struct hns3_hw *hw = &hns->hw;
5841
5842         PMD_INIT_FUNC_TRACE();
5843
5844         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5845                 return -EPERM;
5846
5847         eth_dev->dev_ops = NULL;
5848         eth_dev->rx_pkt_burst = NULL;
5849         eth_dev->tx_pkt_burst = NULL;
5850         eth_dev->tx_pkt_prepare = NULL;
5851         if (hw->adapter_state < HNS3_NIC_CLOSING)
5852                 hns3_dev_close(eth_dev);
5853
5854         hw->adapter_state = HNS3_NIC_REMOVED;
5855         return 0;
5856 }
5857
5858 static int
5859 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5860                    struct rte_pci_device *pci_dev)
5861 {
5862         return rte_eth_dev_pci_generic_probe(pci_dev,
5863                                              sizeof(struct hns3_adapter),
5864                                              hns3_dev_init);
5865 }
5866
5867 static int
5868 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5869 {
5870         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5871 }
5872
5873 static const struct rte_pci_id pci_id_hns3_map[] = {
5874         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5875         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5876         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5877         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5878         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5879         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5880         { .vendor_id = 0, /* sentinel */ },
5881 };
5882
5883 static struct rte_pci_driver rte_hns3_pmd = {
5884         .id_table = pci_id_hns3_map,
5885         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5886         .probe = eth_hns3_pci_probe,
5887         .remove = eth_hns3_pci_remove,
5888 };
5889
5890 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5891 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5892 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5893 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5894 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);