drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, just need to configure parameters for PF vport.
 478          */
 479         vport_id = HNS3_PF_FUNC_ID;
 480         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 481         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 482         req->vf_bitmap[req->vf_offset] = bitmap;
 483
 484         ret = hns3_cmd_send(hw, &desc, 1);
 485         if (ret)
 486                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 487         return ret;
 488 }
 489
 490 static void
 491 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 492                            struct hns3_rx_vtag_cfg *vcfg)
 493 {
 494         struct hns3_pf *pf = &hns->pf;
 495         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 496 }
 497
 498 static void
 499 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 500                            struct hns3_tx_vtag_cfg *vcfg)
 501 {
 502         struct hns3_pf *pf = &hns->pf;
 503         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 504 }
 505
 506 static int
 507 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 508 {
 509         struct hns3_rx_vtag_cfg rxvlan_cfg;
 510         struct hns3_pf *pf = &hns->pf;
 511         struct hns3_hw *hw = &hns->hw;
 512         int ret;
 513
 514         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 515                 rxvlan_cfg.strip_tag1_en = false;
 516                 rxvlan_cfg.strip_tag2_en = enable;
 517         } else {
 518                 rxvlan_cfg.strip_tag1_en = enable;
 519                 rxvlan_cfg.strip_tag2_en = true;
 520         }
 521
 522         rxvlan_cfg.vlan1_vlan_prionly = false;
 523         rxvlan_cfg.vlan2_vlan_prionly = false;
 524         rxvlan_cfg.rx_vlan_offload_en = enable;
 525
 526         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 527         if (ret) {
 528                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 529                 return ret;
 530         }
 531
 532         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 533
 534         return ret;
 535 }
 536
 537 static int
 538 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 539                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 540 {
 541         struct hns3_vlan_filter_ctrl_cmd *req;
 542         struct hns3_cmd_desc desc;
 543         int ret;
 544
 545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 546
 547         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 548         req->vlan_type = vlan_type;
 549         req->vlan_fe = filter_en ? fe_type : 0;
 550         req->vf_id = vf_id;
 551
 552         ret = hns3_cmd_send(hw, &desc, 1);
 553         if (ret)
 554                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 555
 556         return ret;
 557 }
 558
 559 static int
 560 hns3_vlan_filter_init(struct hns3_adapter *hns)
 561 {
 562         struct hns3_hw *hw = &hns->hw;
 563         int ret;
 564
 565         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 566                                         HNS3_FILTER_FE_EGRESS, false,
 567                                         HNS3_PF_FUNC_ID);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false,
 575                                         HNS3_PF_FUNC_ID);
 576         if (ret)
 577                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 578
 579         return ret;
 580 }
 581
 582 static int
 583 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 584 {
 585         struct hns3_hw *hw = &hns->hw;
 586         int ret;
 587
 588         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 589                                         HNS3_FILTER_FE_INGRESS, enable,
 590                                         HNS3_PF_FUNC_ID);
 591         if (ret)
 592                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 593                          enable ? "enable" : "disable", ret);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 600 {
 601         struct hns3_adapter *hns = dev->data->dev_private;
 602         struct hns3_hw *hw = &hns->hw;
 603         struct rte_eth_rxmode *rxmode;
 604         unsigned int tmp_mask;
 605         bool enable;
 606         int ret = 0;
 607
 608         rte_spinlock_lock(&hw->lock);
 609         rxmode = &dev->data->dev_conf.rxmode;
 610         tmp_mask = (unsigned int)mask;
 611         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 612                 /* ignore vlan filter configuration during promiscuous mode */
 613                 if (!dev->data->promiscuous) {
 614                         /* Enable or disable VLAN filter */
 615                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 616                                  true : false;
 617
 618                         ret = hns3_enable_vlan_filter(hns, enable);
 619                         if (ret) {
 620                                 rte_spinlock_unlock(&hw->lock);
 621                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 622                                          enable ? "enable" : "disable", ret);
 623                                 return ret;
 624                         }
 625                 }
 626         }
 627
 628         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 629                 /* Enable or disable VLAN stripping */
 630                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 631                     true : false;
 632
 633                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 634                 if (ret) {
 635                         rte_spinlock_unlock(&hw->lock);
 636                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 637                                  enable ? "enable" : "disable", ret);
 638                         return ret;
 639                 }
 640         }
 641
 642         rte_spinlock_unlock(&hw->lock);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 649                              struct hns3_tx_vtag_cfg *vcfg)
 650 {
 651         struct hns3_vport_vtag_tx_cfg_cmd *req;
 652         struct hns3_cmd_desc desc;
 653         struct hns3_hw *hw = &hns->hw;
 654         uint16_t vport_id;
 655         uint8_t bitmap;
 656         int ret;
 657
 658         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 659
 660         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 661         req->def_vlan_tag1 = vcfg->default_tag1;
 662         req->def_vlan_tag2 = vcfg->default_tag2;
 663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 664                      vcfg->accept_tag1 ? 1 : 0);
 665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 666                      vcfg->accept_untag1 ? 1 : 0);
 667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 668                      vcfg->accept_tag2 ? 1 : 0);
 669         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 670                      vcfg->accept_untag2 ? 1 : 0);
 671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 672                      vcfg->insert_tag1_en ? 1 : 0);
 673         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 674                      vcfg->insert_tag2_en ? 1 : 0);
 675         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 676
 677         /*
 678          * In current version VF is not supported when PF is driven by DPDK
 679          * driver, just need to configure parameters for PF vport.
 680          */
 681         vport_id = HNS3_PF_FUNC_ID;
 682         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 683         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 684         req->vf_bitmap[req->vf_offset] = bitmap;
 685
 686         ret = hns3_cmd_send(hw, &desc, 1);
 687         if (ret)
 688                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 695                      uint16_t pvid)
 696 {
 697         struct hns3_hw *hw = &hns->hw;
 698         struct hns3_tx_vtag_cfg txvlan_cfg;
 699         int ret;
 700
 701         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 702                 txvlan_cfg.accept_tag1 = true;
 703                 txvlan_cfg.insert_tag1_en = false;
 704                 txvlan_cfg.default_tag1 = 0;
 705         } else {
 706                 txvlan_cfg.accept_tag1 = false;
 707                 txvlan_cfg.insert_tag1_en = true;
 708                 txvlan_cfg.default_tag1 = pvid;
 709         }
 710
 711         txvlan_cfg.accept_untag1 = true;
 712         txvlan_cfg.accept_tag2 = true;
 713         txvlan_cfg.accept_untag2 = true;
 714         txvlan_cfg.insert_tag2_en = false;
 715         txvlan_cfg.default_tag2 = 0;
 716
 717         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 718         if (ret) {
 719                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 720                          ret);
 721                 return ret;
 722         }
 723
 724         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 725         return ret;
 726 }
 727
 728 static void
 729 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 730 {
 731         struct hns3_pf *pf = &hns->pf;
 732
 733         pf->port_base_vlan_cfg.state = on ?
 734             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 735
 736         pf->port_base_vlan_cfg.pvid = pvid;
 737 }
 738
 739 static void
 740 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 741 {
 742         struct hns3_user_vlan_table *vlan_entry;
 743         struct hns3_pf *pf = &hns->pf;
 744
 745         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 746                 if (vlan_entry->hd_tbl_status)
 747                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 748
 749                 vlan_entry->hd_tbl_status = false;
 750         }
 751
 752         if (is_del_list) {
 753                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 754                 while (vlan_entry) {
 755                         LIST_REMOVE(vlan_entry, next);
 756                         rte_free(vlan_entry);
 757                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 758                 }
 759         }
 760 }
 761
 762 static void
 763 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 764 {
 765         struct hns3_user_vlan_table *vlan_entry;
 766         struct hns3_pf *pf = &hns->pf;
 767
 768         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 769                 if (!vlan_entry->hd_tbl_status)
 770                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 771
 772                 vlan_entry->hd_tbl_status = true;
 773         }
 774 }
 775
 776 static void
 777 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 778 {
 779         struct hns3_hw *hw = &hns->hw;
 780         struct hns3_pf *pf = &hns->pf;
 781         int ret;
 782
 783         hns3_rm_all_vlan_table(hns, true);
 784         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 785                 ret = hns3_set_port_vlan_filter(hns,
 786                                                 pf->port_base_vlan_cfg.pvid, 0);
 787                 if (ret) {
 788                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 789                                  ret);
 790                         return;
 791                 }
 792         }
 793 }
 794
 795 static int
 796 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 797                                 uint16_t port_base_vlan_state,
 798                                 uint16_t new_pvid, uint16_t old_pvid)
 799 {
 800         struct hns3_pf *pf = &hns->pf;
 801         struct hns3_hw *hw = &hns->hw;
 802         int ret = 0;
 803
 804         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 805                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 806                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 807                         if (ret) {
 808                                 hns3_err(hw,
 809                                          "Failed to clear clear old pvid filter, ret =%d",
 810                                          ret);
 811                                 return ret;
 812                         }
 813                 }
 814
 815                 hns3_rm_all_vlan_table(hns, false);
 816                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 817         }
 818
 819         if (new_pvid != 0) {
 820                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 821                 if (ret) {
 822                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 823                                  ret);
 824                         return ret;
 825                 }
 826         }
 827
 828         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 829                 hns3_add_all_vlan_table(hns);
 830
 831         return ret;
 832 }
 833
 834 static int
 835 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 836 {
 837         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 838         struct hns3_hw *hw = &hns->hw;
 839         bool rx_strip_en;
 840         int ret;
 841
 842         rx_strip_en = on ? true : false;
 843         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 844         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 845         rx_vlan_cfg.vlan1_vlan_prionly = false;
 846         rx_vlan_cfg.vlan2_vlan_prionly = false;
 847         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 848
 849         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 850         if (ret) {
 851                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 852                 return ret;
 853         }
 854
 855         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 856         return ret;
 857 }
 858
 859 static int
 860 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 861 {
 862         struct hns3_pf *pf = &hns->pf;
 863         struct hns3_hw *hw = &hns->hw;
 864         uint16_t port_base_vlan_state;
 865         uint16_t old_pvid;
 866         int ret;
 867
 868         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 869                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 870                         hns3_warn(hw, "Invalid operation! As current pvid set "
 871                                   "is %u, disable pvid %u is invalid",
 872                                   pf->port_base_vlan_cfg.pvid, pvid);
 873                 return 0;
 874         }
 875
 876         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 877                                     HNS3_PORT_BASE_VLAN_DISABLE;
 878         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 879         if (ret) {
 880                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 881                 return ret;
 882         }
 883
 884         ret = hns3_en_rx_strip_all(hns, on);
 885         if (ret) {
 886                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 887                 return ret;
 888         }
 889
 890         if (pvid == HNS3_INVLID_PVID)
 891                 goto out;
 892         old_pvid = pf->port_base_vlan_cfg.pvid;
 893         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 894                                               old_pvid);
 895         if (ret) {
 896                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 897                          ret);
 898                 return ret;
 899         }
 900
 901 out:
 902         hns3_store_port_base_vlan_info(hns, pvid, on);
 903         return ret;
 904 }
 905
 906 static int
 907 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 908 {
 909         struct hns3_adapter *hns = dev->data->dev_private;
 910         struct hns3_hw *hw = &hns->hw;
 911         int ret;
 912
 913         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 914                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 915                          RTE_ETHER_MAX_VLAN_ID);
 916                 return -EINVAL;
 917         }
 918
 919         rte_spinlock_lock(&hw->lock);
 920         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 921         rte_spinlock_unlock(&hw->lock);
 922         return ret;
 923 }
 924
 925 static void
 926 init_port_base_vlan_info(struct hns3_hw *hw)
 927 {
 928         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 929         struct hns3_pf *pf = &hns->pf;
 930
 931         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 932         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 933 }
 934
 935 static int
 936 hns3_default_vlan_config(struct hns3_adapter *hns)
 937 {
 938         struct hns3_hw *hw = &hns->hw;
 939         int ret;
 940
 941         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 942         if (ret)
 943                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 944         return ret;
 945 }
 946
 947 static int
 948 hns3_init_vlan_config(struct hns3_adapter *hns)
 949 {
 950         struct hns3_hw *hw = &hns->hw;
 951         int ret;
 952
 953         /*
 954          * This function can be called in the initialization and reset process,
 955          * when in reset process, it means that hardware had been reseted
 956          * successfully and we need to restore the hardware configuration to
 957          * ensure that the hardware configuration remains unchanged before and
 958          * after reset.
 959          */
 960         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 961                 init_port_base_vlan_info(hw);
 962
 963         ret = hns3_vlan_filter_init(hns);
 964         if (ret) {
 965                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 966                 return ret;
 967         }
 968
 969         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 970                                        RTE_ETHER_TYPE_VLAN);
 971         if (ret) {
 972                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 973                 return ret;
 974         }
 975
 976         /*
 977          * When in the reinit dev stage of the reset process, the following
 978          * vlan-related configurations may differ from those at initialization,
 979          * we will restore configurations to hardware in hns3_restore_vlan_table
 980          * and hns3_restore_vlan_conf later.
 981          */
 982         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 983                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 984                 if (ret) {
 985                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 986                         return ret;
 987                 }
 988
 989                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 990                 if (ret) {
 991                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 992                                  ret);
 993                         return ret;
 994                 }
 995         }
 996
 997         return hns3_default_vlan_config(hns);
 998 }
 999
1000 static int
1001 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1002 {
1003         struct hns3_pf *pf = &hns->pf;
1004         struct hns3_hw *hw = &hns->hw;
1005         uint64_t offloads;
1006         bool enable;
1007         int ret;
1008
1009         if (!hw->data->promiscuous) {
1010                 /* restore vlan filter states */
1011                 offloads = hw->data->dev_conf.rxmode.offloads;
1012                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1013                 ret = hns3_enable_vlan_filter(hns, enable);
1014                 if (ret) {
1015                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1016                                  "ret = %d", ret);
1017                         return ret;
1018                 }
1019         }
1020
1021         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1022         if (ret) {
1023                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1024                 return ret;
1025         }
1026
1027         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1028         if (ret)
1029                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1030
1031         return ret;
1032 }
1033
1034 static int
1035 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1036 {
1037         struct hns3_adapter *hns = dev->data->dev_private;
1038         struct rte_eth_dev_data *data = dev->data;
1039         struct rte_eth_txmode *txmode;
1040         struct hns3_hw *hw = &hns->hw;
1041         int mask;
1042         int ret;
1043
1044         txmode = &data->dev_conf.txmode;
1045         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1046                 hns3_warn(hw,
1047                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1048                           "configuration is not supported! Ignore these two "
1049                           "parameters: hw_vlan_reject_tagged(%d), "
1050                           "hw_vlan_reject_untagged(%d)",
1051                           txmode->hw_vlan_reject_tagged,
1052                           txmode->hw_vlan_reject_untagged);
1053
1054         /* Apply vlan offload setting */
1055         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1056         ret = hns3_vlan_offload_set(dev, mask);
1057         if (ret) {
1058                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1059                          ret);
1060                 return ret;
1061         }
1062
1063         /*
1064          * If pvid config is not set in rte_eth_conf, driver needn't to set
1065          * VLAN pvid related configuration to hardware.
1066          */
1067         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1068                 return 0;
1069
1070         /* Apply pvid setting */
1071         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1072                                  txmode->hw_vlan_insert_pvid);
1073         if (ret)
1074                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1075                          txmode->pvid, ret);
1076
1077         return ret;
1078 }
1079
1080 static int
1081 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1082                 unsigned int tso_mss_max)
1083 {
1084         struct hns3_cfg_tso_status_cmd *req;
1085         struct hns3_cmd_desc desc;
1086         uint16_t tso_mss;
1087
1088         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1089
1090         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1091
1092         tso_mss = 0;
1093         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1094                        tso_mss_min);
1095         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1096
1097         tso_mss = 0;
1098         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1099                        tso_mss_max);
1100         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1101
1102         return hns3_cmd_send(hw, &desc, 1);
1103 }
1104
1105 int
1106 hns3_config_gro(struct hns3_hw *hw, bool en)
1107 {
1108         struct hns3_cfg_gro_status_cmd *req;
1109         struct hns3_cmd_desc desc;
1110         int ret;
1111
1112         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1113         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1114
1115         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1116
1117         ret = hns3_cmd_send(hw, &desc, 1);
1118         if (ret)
1119                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1120
1121         return ret;
1122 }
1123
1124 static int
1125 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1126                    uint16_t *allocated_size, bool is_alloc)
1127 {
1128         struct hns3_umv_spc_alc_cmd *req;
1129         struct hns3_cmd_desc desc;
1130         int ret;
1131
1132         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1133         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1134         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1135         req->space_size = rte_cpu_to_le_32(space_size);
1136
1137         ret = hns3_cmd_send(hw, &desc, 1);
1138         if (ret) {
1139                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1140                              is_alloc ? "allocate" : "free", ret);
1141                 return ret;
1142         }
1143
1144         if (is_alloc && allocated_size)
1145                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1146
1147         return 0;
1148 }
1149
1150 static int
1151 hns3_init_umv_space(struct hns3_hw *hw)
1152 {
1153         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1154         struct hns3_pf *pf = &hns->pf;
1155         uint16_t allocated_size = 0;
1156         int ret;
1157
1158         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1159                                  true);
1160         if (ret)
1161                 return ret;
1162
1163         if (allocated_size < pf->wanted_umv_size)
1164                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1165                              pf->wanted_umv_size, allocated_size);
1166
1167         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1168                                                 pf->wanted_umv_size;
1169         pf->used_umv_size = 0;
1170         return 0;
1171 }
1172
1173 static int
1174 hns3_uninit_umv_space(struct hns3_hw *hw)
1175 {
1176         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1177         struct hns3_pf *pf = &hns->pf;
1178         int ret;
1179
1180         if (pf->max_umv_size == 0)
1181                 return 0;
1182
1183         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1184         if (ret)
1185                 return ret;
1186
1187         pf->max_umv_size = 0;
1188
1189         return 0;
1190 }
1191
1192 static bool
1193 hns3_is_umv_space_full(struct hns3_hw *hw)
1194 {
1195         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1196         struct hns3_pf *pf = &hns->pf;
1197         bool is_full;
1198
1199         is_full = (pf->used_umv_size >= pf->max_umv_size);
1200
1201         return is_full;
1202 }
1203
1204 static void
1205 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1206 {
1207         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1208         struct hns3_pf *pf = &hns->pf;
1209
1210         if (is_free) {
1211                 if (pf->used_umv_size > 0)
1212                         pf->used_umv_size--;
1213         } else
1214                 pf->used_umv_size++;
1215 }
1216
1217 static void
1218 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1219                       const uint8_t *addr, bool is_mc)
1220 {
1221         const unsigned char *mac_addr = addr;
1222         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1223                             ((uint32_t)mac_addr[2] << 16) |
1224                             ((uint32_t)mac_addr[1] << 8) |
1225                             (uint32_t)mac_addr[0];
1226         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1227
1228         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1229         if (is_mc) {
1230                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1231                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1232                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1233         }
1234
1235         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1236         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1237 }
1238
1239 static int
1240 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1241                              uint8_t resp_code,
1242                              enum hns3_mac_vlan_tbl_opcode op)
1243 {
1244         if (cmdq_resp) {
1245                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1246                          cmdq_resp);
1247                 return -EIO;
1248         }
1249
1250         if (op == HNS3_MAC_VLAN_ADD) {
1251                 if (resp_code == 0 || resp_code == 1) {
1252                         return 0;
1253                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1254                         hns3_err(hw, "add mac addr failed for uc_overflow");
1255                         return -ENOSPC;
1256                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1257                         hns3_err(hw, "add mac addr failed for mc_overflow");
1258                         return -ENOSPC;
1259                 }
1260
1261                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1262                          resp_code);
1263                 return -EIO;
1264         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1265                 if (resp_code == 0) {
1266                         return 0;
1267                 } else if (resp_code == 1) {
1268                         hns3_dbg(hw, "remove mac addr failed for miss");
1269                         return -ENOENT;
1270                 }
1271
1272                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1273                          resp_code);
1274                 return -EIO;
1275         } else if (op == HNS3_MAC_VLAN_LKUP) {
1276                 if (resp_code == 0) {
1277                         return 0;
1278                 } else if (resp_code == 1) {
1279                         hns3_dbg(hw, "lookup mac addr failed for miss");
1280                         return -ENOENT;
1281                 }
1282
1283                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1284                          resp_code);
1285                 return -EIO;
1286         }
1287
1288         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1289                  op);
1290
1291         return -EINVAL;
1292 }
1293
1294 static int
1295 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1296                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1297                          struct hns3_cmd_desc *desc, bool is_mc)
1298 {
1299         uint8_t resp_code;
1300         uint16_t retval;
1301         int ret;
1302
1303         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1304         if (is_mc) {
1305                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1306                 memcpy(desc[0].data, req,
1307                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1308                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1309                                           true);
1310                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1311                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1312                                           true);
1313                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1314         } else {
1315                 memcpy(desc[0].data, req,
1316                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1317                 ret = hns3_cmd_send(hw, desc, 1);
1318         }
1319         if (ret) {
1320                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1321                          ret);
1322                 return ret;
1323         }
1324         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1325         retval = rte_le_to_cpu_16(desc[0].retval);
1326
1327         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1328                                             HNS3_MAC_VLAN_LKUP);
1329 }
1330
1331 static int
1332 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1333                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1334                       struct hns3_cmd_desc *mc_desc)
1335 {
1336         uint8_t resp_code;
1337         uint16_t retval;
1338         int cfg_status;
1339         int ret;
1340
1341         if (mc_desc == NULL) {
1342                 struct hns3_cmd_desc desc;
1343
1344                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1345                 memcpy(desc.data, req,
1346                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1347                 ret = hns3_cmd_send(hw, &desc, 1);
1348                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1349                 retval = rte_le_to_cpu_16(desc.retval);
1350
1351                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1352                                                           HNS3_MAC_VLAN_ADD);
1353         } else {
1354                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1355                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1356                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1357                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1358                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1359                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1360                 memcpy(mc_desc[0].data, req,
1361                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362                 mc_desc[0].retval = 0;
1363                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1364                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1365                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1366
1367                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1368                                                           HNS3_MAC_VLAN_ADD);
1369         }
1370
1371         if (ret) {
1372                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1373                 return ret;
1374         }
1375
1376         return cfg_status;
1377 }
1378
1379 static int
1380 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1381                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1382 {
1383         struct hns3_cmd_desc desc;
1384         uint8_t resp_code;
1385         uint16_t retval;
1386         int ret;
1387
1388         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1389
1390         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1391
1392         ret = hns3_cmd_send(hw, &desc, 1);
1393         if (ret) {
1394                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1395                 return ret;
1396         }
1397         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1398         retval = rte_le_to_cpu_16(desc.retval);
1399
1400         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1401                                             HNS3_MAC_VLAN_REMOVE);
1402 }
1403
1404 static int
1405 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1406 {
1407         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1408         struct hns3_mac_vlan_tbl_entry_cmd req;
1409         struct hns3_pf *pf = &hns->pf;
1410         struct hns3_cmd_desc desc;
1411         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1412         uint16_t egress_port = 0;
1413         uint8_t vf_id;
1414         int ret;
1415
1416         /* check if mac addr is valid */
1417         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1418                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1419                                       mac_addr);
1420                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1421                          mac_str);
1422                 return -EINVAL;
1423         }
1424
1425         memset(&req, 0, sizeof(req));
1426
1427         /*
1428          * In current version VF is not supported when PF is driven by DPDK
1429          * driver, just need to configure parameters for PF vport.
1430          */
1431         vf_id = HNS3_PF_FUNC_ID;
1432         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1433                        HNS3_MAC_EPORT_VFID_S, vf_id);
1434
1435         req.egress_port = rte_cpu_to_le_16(egress_port);
1436
1437         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1438
1439         /*
1440          * Lookup the mac address in the mac_vlan table, and add
1441          * it if the entry is inexistent. Repeated unicast entry
1442          * is not allowed in the mac vlan table.
1443          */
1444         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1445         if (ret == -ENOENT) {
1446                 if (!hns3_is_umv_space_full(hw)) {
1447                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1448                         if (!ret)
1449                                 hns3_update_umv_space(hw, false);
1450                         return ret;
1451                 }
1452
1453                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1454
1455                 return -ENOSPC;
1456         }
1457
1458         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1459
1460         /* check if we just hit the duplicate */
1461         if (ret == 0) {
1462                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1463                 return 0;
1464         }
1465
1466         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1467                  mac_str);
1468
1469         return ret;
1470 }
1471
1472 static int
1473 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1474 {
1475         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1476         struct rte_ether_addr *addr;
1477         int ret;
1478         int i;
1479
1480         for (i = 0; i < hw->mc_addrs_num; i++) {
1481                 addr = &hw->mc_addrs[i];
1482                 /* Check if there are duplicate addresses */
1483                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1484                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485                                               addr);
1486                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1487                                  "(%s) is added by the set_mc_mac_addr_list "
1488                                  "API", mac_str);
1489                         return -EINVAL;
1490                 }
1491         }
1492
1493         ret = hns3_add_mc_addr(hw, mac_addr);
1494         if (ret) {
1495                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1496                                       mac_addr);
1497                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1498                          mac_str, ret);
1499         }
1500         return ret;
1501 }
1502
1503 static int
1504 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1505 {
1506         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1507         int ret;
1508
1509         ret = hns3_remove_mc_addr(hw, mac_addr);
1510         if (ret) {
1511                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                       mac_addr);
1513                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1514                          mac_str, ret);
1515         }
1516         return ret;
1517 }
1518
1519 static int
1520 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1521                   uint32_t idx, __rte_unused uint32_t pool)
1522 {
1523         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1525         int ret;
1526
1527         rte_spinlock_lock(&hw->lock);
1528
1529         /*
1530          * In hns3 network engine adding UC and MC mac address with different
1531          * commands with firmware. We need to determine whether the input
1532          * address is a UC or a MC address to call different commands.
1533          * By the way, it is recommended calling the API function named
1534          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1535          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1536          * may affect the specifications of UC mac addresses.
1537          */
1538         if (rte_is_multicast_ether_addr(mac_addr))
1539                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1540         else
1541                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1542
1543         if (ret) {
1544                 rte_spinlock_unlock(&hw->lock);
1545                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                       mac_addr);
1547                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1548                          ret);
1549                 return ret;
1550         }
1551
1552         if (idx == 0)
1553                 hw->mac.default_addr_setted = true;
1554         rte_spinlock_unlock(&hw->lock);
1555
1556         return ret;
1557 }
1558
1559 static int
1560 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1561 {
1562         struct hns3_mac_vlan_tbl_entry_cmd req;
1563         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1564         int ret;
1565
1566         /* check if mac addr is valid */
1567         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1568                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1569                                       mac_addr);
1570                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1571                          mac_str);
1572                 return -EINVAL;
1573         }
1574
1575         memset(&req, 0, sizeof(req));
1576         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1577         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1578         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1579         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1580                 return 0;
1581         else if (ret == 0)
1582                 hns3_update_umv_space(hw, true);
1583
1584         return ret;
1585 }
1586
1587 static void
1588 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1589 {
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         /* index will be checked by upper level rte interface */
1592         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1593         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1594         int ret;
1595
1596         rte_spinlock_lock(&hw->lock);
1597
1598         if (rte_is_multicast_ether_addr(mac_addr))
1599                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1600         else
1601                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1602         rte_spinlock_unlock(&hw->lock);
1603         if (ret) {
1604                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1605                                       mac_addr);
1606                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1607                          ret);
1608         }
1609 }
1610
1611 static int
1612 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1613                           struct rte_ether_addr *mac_addr)
1614 {
1615         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616         struct rte_ether_addr *oaddr;
1617         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1618         bool default_addr_setted;
1619         bool rm_succes = false;
1620         int ret, ret_val;
1621
1622         /*
1623          * It has been guaranteed that input parameter named mac_addr is valid
1624          * address in the rte layer of DPDK framework.
1625          */
1626         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1627         default_addr_setted = hw->mac.default_addr_setted;
1628         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1629                 return 0;
1630
1631         rte_spinlock_lock(&hw->lock);
1632         if (default_addr_setted) {
1633                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1634                 if (ret) {
1635                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636                                               oaddr);
1637                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1638                                   mac_str, ret);
1639                         rm_succes = false;
1640                 } else
1641                         rm_succes = true;
1642         }
1643
1644         ret = hns3_add_uc_addr_common(hw, mac_addr);
1645         if (ret) {
1646                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1649                 goto err_add_uc_addr;
1650         }
1651
1652         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1653         if (ret) {
1654                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1655                 goto err_pause_addr_cfg;
1656         }
1657
1658         rte_ether_addr_copy(mac_addr,
1659                             (struct rte_ether_addr *)hw->mac.mac_addr);
1660         hw->mac.default_addr_setted = true;
1661         rte_spinlock_unlock(&hw->lock);
1662
1663         return 0;
1664
1665 err_pause_addr_cfg:
1666         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1667         if (ret_val) {
1668                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1669                                       mac_addr);
1670                 hns3_warn(hw,
1671                           "Failed to roll back to del setted mac addr(%s): %d",
1672                           mac_str, ret_val);
1673         }
1674
1675 err_add_uc_addr:
1676         if (rm_succes) {
1677                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1678                 if (ret_val) {
1679                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                               oaddr);
1681                         hns3_warn(hw,
1682                                   "Failed to restore old uc mac addr(%s): %d",
1683                                   mac_str, ret_val);
1684                         hw->mac.default_addr_setted = false;
1685                 }
1686         }
1687         rte_spinlock_unlock(&hw->lock);
1688
1689         return ret;
1690 }
1691
1692 static int
1693 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1694 {
1695         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1696         struct hns3_hw *hw = &hns->hw;
1697         struct rte_ether_addr *addr;
1698         int err = 0;
1699         int ret;
1700         int i;
1701
1702         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1703                 addr = &hw->data->mac_addrs[i];
1704                 if (rte_is_zero_ether_addr(addr))
1705                         continue;
1706                 if (rte_is_multicast_ether_addr(addr))
1707                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1708                               hns3_add_mc_addr(hw, addr);
1709                 else
1710                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1711                               hns3_add_uc_addr_common(hw, addr);
1712
1713                 if (ret) {
1714                         err = ret;
1715                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1716                                               addr);
1717                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1718                                  "ret = %d.", del ? "remove" : "restore",
1719                                  mac_str, i, ret);
1720                 }
1721         }
1722         return err;
1723 }
1724
1725 static void
1726 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1727 {
1728 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1729         uint8_t word_num;
1730         uint8_t bit_num;
1731
1732         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1733                 word_num = vfid / 32;
1734                 bit_num = vfid % 32;
1735                 if (clr)
1736                         desc[1].data[word_num] &=
1737                             rte_cpu_to_le_32(~(1UL << bit_num));
1738                 else
1739                         desc[1].data[word_num] |=
1740                             rte_cpu_to_le_32(1UL << bit_num);
1741         } else {
1742                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1743                 bit_num = vfid % 32;
1744                 if (clr)
1745                         desc[2].data[word_num] &=
1746                             rte_cpu_to_le_32(~(1UL << bit_num));
1747                 else
1748                         desc[2].data[word_num] |=
1749                             rte_cpu_to_le_32(1UL << bit_num);
1750         }
1751 }
1752
1753 static int
1754 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1755 {
1756         struct hns3_mac_vlan_tbl_entry_cmd req;
1757         struct hns3_cmd_desc desc[3];
1758         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759         uint8_t vf_id;
1760         int ret;
1761
1762         /* Check if mac addr is valid */
1763         if (!rte_is_multicast_ether_addr(mac_addr)) {
1764                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1765                                       mac_addr);
1766                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1767                          mac_str);
1768                 return -EINVAL;
1769         }
1770
1771         memset(&req, 0, sizeof(req));
1772         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1773         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1774         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1775         if (ret) {
1776                 /* This mac addr do not exist, add new entry for it */
1777                 memset(desc[0].data, 0, sizeof(desc[0].data));
1778                 memset(desc[1].data, 0, sizeof(desc[0].data));
1779                 memset(desc[2].data, 0, sizeof(desc[0].data));
1780         }
1781
1782         /*
1783          * In current version VF is not supported when PF is driven by DPDK
1784          * driver, just need to configure parameters for PF vport.
1785          */
1786         vf_id = HNS3_PF_FUNC_ID;
1787         hns3_update_desc_vfid(desc, vf_id, false);
1788         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1789         if (ret) {
1790                 if (ret == -ENOSPC)
1791                         hns3_err(hw, "mc mac vlan table is full");
1792                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1793                                       mac_addr);
1794                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1795         }
1796
1797         return ret;
1798 }
1799
1800 static int
1801 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1802 {
1803         struct hns3_mac_vlan_tbl_entry_cmd req;
1804         struct hns3_cmd_desc desc[3];
1805         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1806         uint8_t vf_id;
1807         int ret;
1808
1809         /* Check if mac addr is valid */
1810         if (!rte_is_multicast_ether_addr(mac_addr)) {
1811                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1812                                       mac_addr);
1813                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1814                          mac_str);
1815                 return -EINVAL;
1816         }
1817
1818         memset(&req, 0, sizeof(req));
1819         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1820         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1821         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1822         if (ret == 0) {
1823                 /*
1824                  * This mac addr exist, remove this handle's VFID for it.
1825                  * In current version VF is not supported when PF is driven by
1826                  * DPDK driver, just need to configure parameters for PF vport.
1827                  */
1828                 vf_id = HNS3_PF_FUNC_ID;
1829                 hns3_update_desc_vfid(desc, vf_id, true);
1830
1831                 /* All the vfid is zero, so need to delete this entry */
1832                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1833         } else if (ret == -ENOENT) {
1834                 /* This mac addr doesn't exist. */
1835                 return 0;
1836         }
1837
1838         if (ret) {
1839                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1840                                       mac_addr);
1841                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1842         }
1843
1844         return ret;
1845 }
1846
1847 static int
1848 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1849                            struct rte_ether_addr *mc_addr_set,
1850                            uint32_t nb_mc_addr)
1851 {
1852         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1853         struct rte_ether_addr *addr;
1854         uint32_t i;
1855         uint32_t j;
1856
1857         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1858                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1859                          "invalid. valid range: 0~%d",
1860                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1861                 return -EINVAL;
1862         }
1863
1864         /* Check if input mac addresses are valid */
1865         for (i = 0; i < nb_mc_addr; i++) {
1866                 addr = &mc_addr_set[i];
1867                 if (!rte_is_multicast_ether_addr(addr)) {
1868                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1869                                               addr);
1870                         hns3_err(hw,
1871                                  "failed to set mc mac addr, addr(%s) invalid.",
1872                                  mac_str);
1873                         return -EINVAL;
1874                 }
1875
1876                 /* Check if there are duplicate addresses */
1877                 for (j = i + 1; j < nb_mc_addr; j++) {
1878                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1879                                 rte_ether_format_addr(mac_str,
1880                                                       RTE_ETHER_ADDR_FMT_SIZE,
1881                                                       addr);
1882                                 hns3_err(hw, "failed to set mc mac addr, "
1883                                          "addrs invalid. two same addrs(%s).",
1884                                          mac_str);
1885                                 return -EINVAL;
1886                         }
1887                 }
1888
1889                 /*
1890                  * Check if there are duplicate addresses between mac_addrs
1891                  * and mc_addr_set
1892                  */
1893                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1894                         if (rte_is_same_ether_addr(addr,
1895                                                    &hw->data->mac_addrs[j])) {
1896                                 rte_ether_format_addr(mac_str,
1897                                                       RTE_ETHER_ADDR_FMT_SIZE,
1898                                                       addr);
1899                                 hns3_err(hw, "failed to set mc mac addr, "
1900                                          "addrs invalid. addrs(%s) has already "
1901                                          "configured in mac_addr add API",
1902                                          mac_str);
1903                                 return -EINVAL;
1904                         }
1905                 }
1906         }
1907
1908         return 0;
1909 }
1910
1911 static void
1912 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1913                            struct rte_ether_addr *mc_addr_set,
1914                            int mc_addr_num,
1915                            struct rte_ether_addr *reserved_addr_list,
1916                            int *reserved_addr_num,
1917                            struct rte_ether_addr *add_addr_list,
1918                            int *add_addr_num,
1919                            struct rte_ether_addr *rm_addr_list,
1920                            int *rm_addr_num)
1921 {
1922         struct rte_ether_addr *addr;
1923         int current_addr_num;
1924         int reserved_num = 0;
1925         int add_num = 0;
1926         int rm_num = 0;
1927         int num;
1928         int i;
1929         int j;
1930         bool same_addr;
1931
1932         /* Calculate the mc mac address list that should be removed */
1933         current_addr_num = hw->mc_addrs_num;
1934         for (i = 0; i < current_addr_num; i++) {
1935                 addr = &hw->mc_addrs[i];
1936                 same_addr = false;
1937                 for (j = 0; j < mc_addr_num; j++) {
1938                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1939                                 same_addr = true;
1940                                 break;
1941                         }
1942                 }
1943
1944                 if (!same_addr) {
1945                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1946                         rm_num++;
1947                 } else {
1948                         rte_ether_addr_copy(addr,
1949                                             &reserved_addr_list[reserved_num]);
1950                         reserved_num++;
1951                 }
1952         }
1953
1954         /* Calculate the mc mac address list that should be added */
1955         for (i = 0; i < mc_addr_num; i++) {
1956                 addr = &mc_addr_set[i];
1957                 same_addr = false;
1958                 for (j = 0; j < current_addr_num; j++) {
1959                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1960                                 same_addr = true;
1961                                 break;
1962                         }
1963                 }
1964
1965                 if (!same_addr) {
1966                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1967                         add_num++;
1968                 }
1969         }
1970
1971         /* Reorder the mc mac address list maintained by driver */
1972         for (i = 0; i < reserved_num; i++)
1973                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1974
1975         for (i = 0; i < rm_num; i++) {
1976                 num = reserved_num + i;
1977                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1978         }
1979
1980         *reserved_addr_num = reserved_num;
1981         *add_addr_num = add_num;
1982         *rm_addr_num = rm_num;
1983 }
1984
1985 static int
1986 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1987                           struct rte_ether_addr *mc_addr_set,
1988                           uint32_t nb_mc_addr)
1989 {
1990         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1992         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1993         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1994         struct rte_ether_addr *addr;
1995         int reserved_addr_num;
1996         int add_addr_num;
1997         int rm_addr_num;
1998         int mc_addr_num;
1999         int num;
2000         int ret;
2001         int i;
2002
2003         /* Check if input parameters are valid */
2004         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2005         if (ret)
2006                 return ret;
2007
2008         rte_spinlock_lock(&hw->lock);
2009
2010         /*
2011          * Calculate the mc mac address lists those should be removed and be
2012          * added, Reorder the mc mac address list maintained by driver.
2013          */
2014         mc_addr_num = (int)nb_mc_addr;
2015         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2016                                    reserved_addr_list, &reserved_addr_num,
2017                                    add_addr_list, &add_addr_num,
2018                                    rm_addr_list, &rm_addr_num);
2019
2020         /* Remove mc mac addresses */
2021         for (i = 0; i < rm_addr_num; i++) {
2022                 num = rm_addr_num - i - 1;
2023                 addr = &rm_addr_list[num];
2024                 ret = hns3_remove_mc_addr(hw, addr);
2025                 if (ret) {
2026                         rte_spinlock_unlock(&hw->lock);
2027                         return ret;
2028                 }
2029                 hw->mc_addrs_num--;
2030         }
2031
2032         /* Add mc mac addresses */
2033         for (i = 0; i < add_addr_num; i++) {
2034                 addr = &add_addr_list[i];
2035                 ret = hns3_add_mc_addr(hw, addr);
2036                 if (ret) {
2037                         rte_spinlock_unlock(&hw->lock);
2038                         return ret;
2039                 }
2040
2041                 num = reserved_addr_num + i;
2042                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2043                 hw->mc_addrs_num++;
2044         }
2045         rte_spinlock_unlock(&hw->lock);
2046
2047         return 0;
2048 }
2049
2050 static int
2051 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2052 {
2053         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2054         struct hns3_hw *hw = &hns->hw;
2055         struct rte_ether_addr *addr;
2056         int err = 0;
2057         int ret;
2058         int i;
2059
2060         for (i = 0; i < hw->mc_addrs_num; i++) {
2061                 addr = &hw->mc_addrs[i];
2062                 if (!rte_is_multicast_ether_addr(addr))
2063                         continue;
2064                 if (del)
2065                         ret = hns3_remove_mc_addr(hw, addr);
2066                 else
2067                         ret = hns3_add_mc_addr(hw, addr);
2068                 if (ret) {
2069                         err = ret;
2070                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2071                                               addr);
2072                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2073                                  del ? "Remove" : "Restore", mac_str, ret);
2074                 }
2075         }
2076         return err;
2077 }
2078
2079 static int
2080 hns3_check_mq_mode(struct rte_eth_dev *dev)
2081 {
2082         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2083         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2084         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2086         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2087         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2088         uint8_t num_tc;
2089         int max_tc = 0;
2090         int i;
2091
2092         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2093         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2096                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2097                          "rx_mq_mode = %d", rx_mq_mode);
2098                 return -EINVAL;
2099         }
2100
2101         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2102             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2103                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2104                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2105                          rx_mq_mode, tx_mq_mode);
2106                 return -EINVAL;
2107         }
2108
2109         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2110                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2111                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2112                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2113                         return -EINVAL;
2114                 }
2115
2116                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2117                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2118                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2119                                  "nb_tcs(%d) != %d or %d in rx direction.",
2120                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2121                         return -EINVAL;
2122                 }
2123
2124                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2125                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2126                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2127                         return -EINVAL;
2128                 }
2129
2130                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2131                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2132                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2133                                          "is not equal to one in tx direction.",
2134                                          i, dcb_rx_conf->dcb_tc[i]);
2135                                 return -EINVAL;
2136                         }
2137                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2138                                 max_tc = dcb_rx_conf->dcb_tc[i];
2139                 }
2140
2141                 num_tc = max_tc + 1;
2142                 if (num_tc > dcb_rx_conf->nb_tcs) {
2143                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2144                                  num_tc, dcb_rx_conf->nb_tcs);
2145                         return -EINVAL;
2146                 }
2147         }
2148
2149         return 0;
2150 }
2151
2152 static int
2153 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2154 {
2155         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156
2157         if (!hns3_dev_dcb_supported(hw)) {
2158                 hns3_err(hw, "this port does not support dcb configurations.");
2159                 return -EOPNOTSUPP;
2160         }
2161
2162         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2163                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2164                 return -EOPNOTSUPP;
2165         }
2166
2167         /* Check multiple queue mode */
2168         return hns3_check_mq_mode(dev);
2169 }
2170
2171 static int
2172 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2173                            enum hns3_ring_type queue_type, uint16_t queue_id)
2174 {
2175         struct hns3_cmd_desc desc;
2176         struct hns3_ctrl_vector_chain_cmd *req =
2177                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2178         enum hns3_cmd_status status;
2179         enum hns3_opcode_type op;
2180         uint16_t tqp_type_and_id = 0;
2181         const char *op_str;
2182         uint16_t type;
2183         uint16_t gl;
2184
2185         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2186         hns3_cmd_setup_basic_desc(&desc, op, false);
2187         req->int_vector_id = vector_id;
2188
2189         if (queue_type == HNS3_RING_TYPE_RX)
2190                 gl = HNS3_RING_GL_RX;
2191         else
2192                 gl = HNS3_RING_GL_TX;
2193
2194         type = queue_type;
2195
2196         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2197                        type);
2198         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2199         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2200                        gl);
2201         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2202         req->int_cause_num = 1;
2203         op_str = mmap ? "Map" : "Unmap";
2204         status = hns3_cmd_send(hw, &desc, 1);
2205         if (status) {
2206                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2207                          op_str, queue_id, req->int_vector_id, status);
2208                 return status;
2209         }
2210
2211         return 0;
2212 }
2213
2214 static int
2215 hns3_init_ring_with_vector(struct hns3_hw *hw)
2216 {
2217         uint8_t vec;
2218         int ret;
2219         int i;
2220
2221         /*
2222          * In hns3 network engine, vector 0 is always the misc interrupt of this
2223          * function, vector 1~N can be used respectively for the queues of the
2224          * function. Tx and Rx queues with the same number share the interrupt
2225          * vector. In the initialization clearing the all hardware mapping
2226          * relationship configurations between queues and interrupt vectors is
2227          * needed, so some error caused by the residual configurations, such as
2228          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2229          * constraints in hns3 hardware engine, we have to implement clearing
2230          * the mapping relationship configurations by binding all queues to the
2231          * last interrupt vector and reserving the last interrupt vector. This
2232          * method results in a decrease of the maximum queues when upper
2233          * applications call the rte_eth_dev_configure API function to enable
2234          * Rx interrupt.
2235          */
2236         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2237         /* vec - 1: the last interrupt is reserved */
2238         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2239         for (i = 0; i < hw->intr_tqps_num; i++) {
2240                 /*
2241                  * Set gap limiter and rate limiter configuration of queue's
2242                  * interrupt.
2243                  */
2244                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2245                                        HNS3_TQP_INTR_GL_DEFAULT);
2246                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2247                                        HNS3_TQP_INTR_GL_DEFAULT);
2248                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2249
2250                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2251                                                  HNS3_RING_TYPE_TX, i);
2252                 if (ret) {
2253                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2254                                           "vector: %d, ret=%d", i, vec, ret);
2255                         return ret;
2256                 }
2257
2258                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2259                                                  HNS3_RING_TYPE_RX, i);
2260                 if (ret) {
2261                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2262                                           "vector: %d, ret=%d", i, vec, ret);
2263                         return ret;
2264                 }
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int
2271 hns3_dev_configure(struct rte_eth_dev *dev)
2272 {
2273         struct hns3_adapter *hns = dev->data->dev_private;
2274         struct rte_eth_conf *conf = &dev->data->dev_conf;
2275         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2276         struct hns3_hw *hw = &hns->hw;
2277         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2278         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2279         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2280         struct rte_eth_rss_conf rss_conf;
2281         uint16_t mtu;
2282         int ret;
2283
2284         /*
2285          * Hardware does not support individually enable/disable/reset the Tx or
2286          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2287          * and Rx queues at the same time. When the numbers of Tx queues
2288          * allocated by upper applications are not equal to the numbers of Rx
2289          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2290          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2291          * these fake queues are imperceptible, and can not be used by upper
2292          * applications.
2293          */
2294         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2295         if (ret) {
2296                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2297                 return ret;
2298         }
2299
2300         hw->adapter_state = HNS3_NIC_CONFIGURING;
2301         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2302                 hns3_err(hw, "setting link speed/duplex not supported");
2303                 ret = -EINVAL;
2304                 goto cfg_err;
2305         }
2306
2307         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2308                 ret = hns3_check_dcb_cfg(dev);
2309                 if (ret)
2310                         goto cfg_err;
2311         }
2312
2313         /* When RSS is not configured, redirect the packet queue 0 */
2314         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2315                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2316                 rss_conf = conf->rx_adv_conf.rss_conf;
2317                 if (rss_conf.rss_key == NULL) {
2318                         rss_conf.rss_key = rss_cfg->key;
2319                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2320                 }
2321
2322                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2323                 if (ret)
2324                         goto cfg_err;
2325         }
2326
2327         /*
2328          * If jumbo frames are enabled, MTU needs to be refreshed
2329          * according to the maximum RX packet length.
2330          */
2331         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2332                 /*
2333                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2334                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2335                  * can safely assign to "uint16_t" type variable.
2336                  */
2337                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2338                 ret = hns3_dev_mtu_set(dev, mtu);
2339                 if (ret)
2340                         goto cfg_err;
2341                 dev->data->mtu = mtu;
2342         }
2343
2344         ret = hns3_dev_configure_vlan(dev);
2345         if (ret)
2346                 goto cfg_err;
2347
2348         hw->adapter_state = HNS3_NIC_CONFIGURED;
2349
2350         return 0;
2351
2352 cfg_err:
2353         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2354         hw->adapter_state = HNS3_NIC_INITIALIZED;
2355
2356         return ret;
2357 }
2358
2359 static int
2360 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2361 {
2362         struct hns3_config_max_frm_size_cmd *req;
2363         struct hns3_cmd_desc desc;
2364
2365         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2366
2367         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2368         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2369         req->min_frm_size = RTE_ETHER_MIN_LEN;
2370
2371         return hns3_cmd_send(hw, &desc, 1);
2372 }
2373
2374 static int
2375 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2376 {
2377         int ret;
2378
2379         ret = hns3_set_mac_mtu(hw, mps);
2380         if (ret) {
2381                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2382                 return ret;
2383         }
2384
2385         ret = hns3_buffer_alloc(hw);
2386         if (ret)
2387                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2388
2389         return ret;
2390 }
2391
2392 static int
2393 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2394 {
2395         struct hns3_adapter *hns = dev->data->dev_private;
2396         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2397         struct hns3_hw *hw = &hns->hw;
2398         bool is_jumbo_frame;
2399         int ret;
2400
2401         if (dev->data->dev_started) {
2402                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2403                          "before configuration", dev->data->port_id);
2404                 return -EBUSY;
2405         }
2406
2407         rte_spinlock_lock(&hw->lock);
2408         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2409         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2410
2411         /*
2412          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2413          * assign to "uint16_t" type variable.
2414          */
2415         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2416         if (ret) {
2417                 rte_spinlock_unlock(&hw->lock);
2418                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2419                          dev->data->port_id, mtu, ret);
2420                 return ret;
2421         }
2422         hns->pf.mps = (uint16_t)frame_size;
2423         if (is_jumbo_frame)
2424                 dev->data->dev_conf.rxmode.offloads |=
2425                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2426         else
2427                 dev->data->dev_conf.rxmode.offloads &=
2428                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2429         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2430         rte_spinlock_unlock(&hw->lock);
2431
2432         return 0;
2433 }
2434
2435 static int
2436 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2437 {
2438         struct hns3_adapter *hns = eth_dev->data->dev_private;
2439         struct hns3_hw *hw = &hns->hw;
2440         uint16_t queue_num = hw->tqps_num;
2441
2442         /*
2443          * In interrupt mode, 'max_rx_queues' is set based on the number of
2444          * MSI-X interrupt resources of the hardware.
2445          */
2446         if (hw->data->dev_conf.intr_conf.rxq == 1)
2447                 queue_num = hw->intr_tqps_num;
2448
2449         info->max_rx_queues = queue_num;
2450         info->max_tx_queues = hw->tqps_num;
2451         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2452         info->min_rx_bufsize = hw->rx_buf_len;
2453         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2454         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2455         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2456                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2457                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2458                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2459                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2460                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2461                                  DEV_RX_OFFLOAD_KEEP_CRC |
2462                                  DEV_RX_OFFLOAD_SCATTER |
2463                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2464                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2465                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2466                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2467                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2468                                  DEV_RX_OFFLOAD_RSS_HASH);
2469         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2470         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2471                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2472                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2473                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2474                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2475                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2476                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2477                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2478                                  DEV_TX_OFFLOAD_TCP_TSO |
2479                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2480                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2481                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2482                                  info->tx_queue_offload_capa);
2483
2484         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2485                 .nb_max = HNS3_MAX_RING_DESC,
2486                 .nb_min = HNS3_MIN_RING_DESC,
2487                 .nb_align = HNS3_ALIGN_RING_DESC,
2488         };
2489
2490         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2491                 .nb_max = HNS3_MAX_RING_DESC,
2492                 .nb_min = HNS3_MIN_RING_DESC,
2493                 .nb_align = HNS3_ALIGN_RING_DESC,
2494         };
2495
2496         info->vmdq_queue_num = 0;
2497
2498         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2499         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2500         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2501
2502         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2503         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2504         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2505         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2506         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2507         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2508
2509         return 0;
2510 }
2511
2512 static int
2513 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2514                     size_t fw_size)
2515 {
2516         struct hns3_adapter *hns = eth_dev->data->dev_private;
2517         struct hns3_hw *hw = &hns->hw;
2518         uint32_t version = hw->fw_version;
2519         int ret;
2520
2521         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2522                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2523                                       HNS3_FW_VERSION_BYTE3_S),
2524                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2525                                       HNS3_FW_VERSION_BYTE2_S),
2526                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2527                                       HNS3_FW_VERSION_BYTE1_S),
2528                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2529                                       HNS3_FW_VERSION_BYTE0_S));
2530         ret += 1; /* add the size of '\0' */
2531         if (fw_size < (uint32_t)ret)
2532                 return ret;
2533         else
2534                 return 0;
2535 }
2536
2537 static int
2538 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2539                      __rte_unused int wait_to_complete)
2540 {
2541         struct hns3_adapter *hns = eth_dev->data->dev_private;
2542         struct hns3_hw *hw = &hns->hw;
2543         struct hns3_mac *mac = &hw->mac;
2544         struct rte_eth_link new_link;
2545
2546         if (!hns3_is_reset_pending(hns)) {
2547                 hns3_update_speed_duplex(eth_dev);
2548                 hns3_update_link_status(hw);
2549         }
2550
2551         memset(&new_link, 0, sizeof(new_link));
2552         switch (mac->link_speed) {
2553         case ETH_SPEED_NUM_10M:
2554         case ETH_SPEED_NUM_100M:
2555         case ETH_SPEED_NUM_1G:
2556         case ETH_SPEED_NUM_10G:
2557         case ETH_SPEED_NUM_25G:
2558         case ETH_SPEED_NUM_40G:
2559         case ETH_SPEED_NUM_50G:
2560         case ETH_SPEED_NUM_100G:
2561                 new_link.link_speed = mac->link_speed;
2562                 break;
2563         default:
2564                 new_link.link_speed = ETH_SPEED_NUM_100M;
2565                 break;
2566         }
2567
2568         new_link.link_duplex = mac->link_duplex;
2569         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2570         new_link.link_autoneg =
2571             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2572
2573         return rte_eth_linkstatus_set(eth_dev, &new_link);
2574 }
2575
2576 static int
2577 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2578 {
2579         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2580         struct hns3_pf *pf = &hns->pf;
2581
2582         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2583                 return -EINVAL;
2584
2585         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2586
2587         return 0;
2588 }
2589
2590 static int
2591 hns3_query_function_status(struct hns3_hw *hw)
2592 {
2593 #define HNS3_QUERY_MAX_CNT              10
2594 #define HNS3_QUERY_SLEEP_MSCOEND        1
2595         struct hns3_func_status_cmd *req;
2596         struct hns3_cmd_desc desc;
2597         int timeout = 0;
2598         int ret;
2599
2600         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2601         req = (struct hns3_func_status_cmd *)desc.data;
2602
2603         do {
2604                 ret = hns3_cmd_send(hw, &desc, 1);
2605                 if (ret) {
2606                         PMD_INIT_LOG(ERR, "query function status failed %d",
2607                                      ret);
2608                         return ret;
2609                 }
2610
2611                 /* Check pf reset is done */
2612                 if (req->pf_state)
2613                         break;
2614
2615                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2616         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2617
2618         return hns3_parse_func_status(hw, req);
2619 }
2620
2621 static int
2622 hns3_query_pf_resource(struct hns3_hw *hw)
2623 {
2624         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2625         struct hns3_pf *pf = &hns->pf;
2626         struct hns3_pf_res_cmd *req;
2627         struct hns3_cmd_desc desc;
2628         int ret;
2629
2630         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2631         ret = hns3_cmd_send(hw, &desc, 1);
2632         if (ret) {
2633                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2634                 return ret;
2635         }
2636
2637         req = (struct hns3_pf_res_cmd *)desc.data;
2638         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2639         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2640         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2641         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2642
2643         if (req->tx_buf_size)
2644                 pf->tx_buf_size =
2645                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2646         else
2647                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2648
2649         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2650
2651         if (req->dv_buf_size)
2652                 pf->dv_buf_size =
2653                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2654         else
2655                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2656
2657         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2658
2659         hw->num_msi =
2660             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2661                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2662
2663         return 0;
2664 }
2665
2666 static void
2667 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2668 {
2669         struct hns3_cfg_param_cmd *req;
2670         uint64_t mac_addr_tmp_high;
2671         uint64_t mac_addr_tmp;
2672         uint32_t i;
2673
2674         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2675
2676         /* get the configuration */
2677         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2678                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2679         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2680                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2681         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2682                                            HNS3_CFG_TQP_DESC_N_M,
2683                                            HNS3_CFG_TQP_DESC_N_S);
2684
2685         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2686                                        HNS3_CFG_PHY_ADDR_M,
2687                                        HNS3_CFG_PHY_ADDR_S);
2688         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2689                                          HNS3_CFG_MEDIA_TP_M,
2690                                          HNS3_CFG_MEDIA_TP_S);
2691         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2692                                          HNS3_CFG_RX_BUF_LEN_M,
2693                                          HNS3_CFG_RX_BUF_LEN_S);
2694         /* get mac address */
2695         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2696         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2697                                            HNS3_CFG_MAC_ADDR_H_M,
2698                                            HNS3_CFG_MAC_ADDR_H_S);
2699
2700         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2701
2702         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2703                                             HNS3_CFG_DEFAULT_SPEED_M,
2704                                             HNS3_CFG_DEFAULT_SPEED_S);
2705         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2706                                            HNS3_CFG_RSS_SIZE_M,
2707                                            HNS3_CFG_RSS_SIZE_S);
2708
2709         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2710                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2711
2712         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2713         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2714
2715         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2716                                             HNS3_CFG_SPEED_ABILITY_M,
2717                                             HNS3_CFG_SPEED_ABILITY_S);
2718         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2719                                         HNS3_CFG_UMV_TBL_SPACE_M,
2720                                         HNS3_CFG_UMV_TBL_SPACE_S);
2721         if (!cfg->umv_space)
2722                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2723 }
2724
2725 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2726  * @hw: pointer to struct hns3_hw
2727  * @hcfg: the config structure to be getted
2728  */
2729 static int
2730 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2731 {
2732         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2733         struct hns3_cfg_param_cmd *req;
2734         uint32_t offset;
2735         uint32_t i;
2736         int ret;
2737
2738         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2739                 offset = 0;
2740                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2741                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2742                                           true);
2743                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2744                                i * HNS3_CFG_RD_LEN_BYTES);
2745                 /* Len should be divided by 4 when send to hardware */
2746                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2747                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2748                 req->offset = rte_cpu_to_le_32(offset);
2749         }
2750
2751         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2752         if (ret) {
2753                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2754                 return ret;
2755         }
2756
2757         hns3_parse_cfg(hcfg, desc);
2758
2759         return 0;
2760 }
2761
2762 static int
2763 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2764 {
2765         switch (speed_cmd) {
2766         case HNS3_CFG_SPEED_10M:
2767                 *speed = ETH_SPEED_NUM_10M;
2768                 break;
2769         case HNS3_CFG_SPEED_100M:
2770                 *speed = ETH_SPEED_NUM_100M;
2771                 break;
2772         case HNS3_CFG_SPEED_1G:
2773                 *speed = ETH_SPEED_NUM_1G;
2774                 break;
2775         case HNS3_CFG_SPEED_10G:
2776                 *speed = ETH_SPEED_NUM_10G;
2777                 break;
2778         case HNS3_CFG_SPEED_25G:
2779                 *speed = ETH_SPEED_NUM_25G;
2780                 break;
2781         case HNS3_CFG_SPEED_40G:
2782                 *speed = ETH_SPEED_NUM_40G;
2783                 break;
2784         case HNS3_CFG_SPEED_50G:
2785                 *speed = ETH_SPEED_NUM_50G;
2786                 break;
2787         case HNS3_CFG_SPEED_100G:
2788                 *speed = ETH_SPEED_NUM_100G;
2789                 break;
2790         default:
2791                 return -EINVAL;
2792         }
2793
2794         return 0;
2795 }
2796
2797 static int
2798 hns3_get_board_configuration(struct hns3_hw *hw)
2799 {
2800         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2801         struct hns3_pf *pf = &hns->pf;
2802         struct hns3_cfg cfg;
2803         int ret;
2804
2805         ret = hns3_get_board_cfg(hw, &cfg);
2806         if (ret) {
2807                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2808                 return ret;
2809         }
2810
2811         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2812                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2813                 return -EOPNOTSUPP;
2814         }
2815
2816         hw->mac.media_type = cfg.media_type;
2817         hw->rss_size_max = cfg.rss_size_max;
2818         hw->rss_dis_flag = false;
2819         hw->rx_buf_len = cfg.rx_buf_len;
2820         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2821         hw->mac.phy_addr = cfg.phy_addr;
2822         hw->mac.default_addr_setted = false;
2823         hw->num_tx_desc = cfg.tqp_desc_num;
2824         hw->num_rx_desc = cfg.tqp_desc_num;
2825         hw->dcb_info.num_pg = 1;
2826         hw->dcb_info.hw_pfc_map = 0;
2827
2828         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2829         if (ret) {
2830                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2831                              cfg.default_speed, ret);
2832                 return ret;
2833         }
2834
2835         pf->tc_max = cfg.tc_num;
2836         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2837                 PMD_INIT_LOG(WARNING,
2838                              "Get TC num(%u) from flash, set TC num to 1",
2839                              pf->tc_max);
2840                 pf->tc_max = 1;
2841         }
2842
2843         /* Dev does not support DCB */
2844         if (!hns3_dev_dcb_supported(hw)) {
2845                 pf->tc_max = 1;
2846                 pf->pfc_max = 0;
2847         } else
2848                 pf->pfc_max = pf->tc_max;
2849
2850         hw->dcb_info.num_tc = 1;
2851         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2852                                      hw->tqps_num / hw->dcb_info.num_tc);
2853         hns3_set_bit(hw->hw_tc_map, 0, 1);
2854         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2855
2856         pf->wanted_umv_size = cfg.umv_space;
2857
2858         return ret;
2859 }
2860
2861 static int
2862 hns3_get_configuration(struct hns3_hw *hw)
2863 {
2864         int ret;
2865
2866         ret = hns3_query_function_status(hw);
2867         if (ret) {
2868                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2869                 return ret;
2870         }
2871
2872         /* Get pf resource */
2873         ret = hns3_query_pf_resource(hw);
2874         if (ret) {
2875                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2876                 return ret;
2877         }
2878
2879         ret = hns3_get_board_configuration(hw);
2880         if (ret)
2881                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2882
2883         return ret;
2884 }
2885
2886 static int
2887 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2888                       uint16_t tqp_vid, bool is_pf)
2889 {
2890         struct hns3_tqp_map_cmd *req;
2891         struct hns3_cmd_desc desc;
2892         int ret;
2893
2894         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2895
2896         req = (struct hns3_tqp_map_cmd *)desc.data;
2897         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2898         req->tqp_vf = func_id;
2899         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2900         if (!is_pf)
2901                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2902         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2903
2904         ret = hns3_cmd_send(hw, &desc, 1);
2905         if (ret)
2906                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2907
2908         return ret;
2909 }
2910
2911 static int
2912 hns3_map_tqp(struct hns3_hw *hw)
2913 {
2914         uint16_t tqps_num = hw->total_tqps_num;
2915         uint16_t func_id;
2916         uint16_t tqp_id;
2917         bool is_pf;
2918         int num;
2919         int ret;
2920         int i;
2921
2922         /*
2923          * In current version VF is not supported when PF is driven by DPDK
2924          * driver, so we allocate tqps to PF as much as possible.
2925          */
2926         tqp_id = 0;
2927         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2928         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2929                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2930                 for (i = 0;
2931                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2932                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2933                                                     is_pf);
2934                         if (ret)
2935                                 return ret;
2936                 }
2937         }
2938
2939         return 0;
2940 }
2941
2942 static int
2943 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2944 {
2945         struct hns3_config_mac_speed_dup_cmd *req;
2946         struct hns3_cmd_desc desc;
2947         int ret;
2948
2949         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2950
2951         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2952
2953         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2954
2955         switch (speed) {
2956         case ETH_SPEED_NUM_10M:
2957                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2958                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2959                 break;
2960         case ETH_SPEED_NUM_100M:
2961                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2962                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2963                 break;
2964         case ETH_SPEED_NUM_1G:
2965                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2966                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2967                 break;
2968         case ETH_SPEED_NUM_10G:
2969                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2970                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2971                 break;
2972         case ETH_SPEED_NUM_25G:
2973                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2974                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2975                 break;
2976         case ETH_SPEED_NUM_40G:
2977                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2978                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2979                 break;
2980         case ETH_SPEED_NUM_50G:
2981                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2982                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2983                 break;
2984         case ETH_SPEED_NUM_100G:
2985                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2986                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2987                 break;
2988         default:
2989                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2990                 return -EINVAL;
2991         }
2992
2993         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2994
2995         ret = hns3_cmd_send(hw, &desc, 1);
2996         if (ret)
2997                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2998
2999         return ret;
3000 }
3001
3002 static int
3003 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3004 {
3005         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3006         struct hns3_pf *pf = &hns->pf;
3007         struct hns3_priv_buf *priv;
3008         uint32_t i, total_size;
3009
3010         total_size = pf->pkt_buf_size;
3011
3012         /* alloc tx buffer for all enabled tc */
3013         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3014                 priv = &buf_alloc->priv_buf[i];
3015
3016                 if (hw->hw_tc_map & BIT(i)) {
3017                         if (total_size < pf->tx_buf_size)
3018                                 return -ENOMEM;
3019
3020                         priv->tx_buf_size = pf->tx_buf_size;
3021                 } else
3022                         priv->tx_buf_size = 0;
3023
3024                 total_size -= priv->tx_buf_size;
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int
3031 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3032 {
3033 /* TX buffer size is unit by 128 byte */
3034 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3035 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3036         struct hns3_tx_buff_alloc_cmd *req;
3037         struct hns3_cmd_desc desc;
3038         uint32_t buf_size;
3039         uint32_t i;
3040         int ret;
3041
3042         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3043
3044         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3045         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3046                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3047
3048                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3049                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3050                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3051         }
3052
3053         ret = hns3_cmd_send(hw, &desc, 1);
3054         if (ret)
3055                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3056
3057         return ret;
3058 }
3059
3060 static int
3061 hns3_get_tc_num(struct hns3_hw *hw)
3062 {
3063         int cnt = 0;
3064         uint8_t i;
3065
3066         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3067                 if (hw->hw_tc_map & BIT(i))
3068                         cnt++;
3069         return cnt;
3070 }
3071
3072 static uint32_t
3073 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3074 {
3075         struct hns3_priv_buf *priv;
3076         uint32_t rx_priv = 0;
3077         int i;
3078
3079         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3080                 priv = &buf_alloc->priv_buf[i];
3081                 if (priv->enable)
3082                         rx_priv += priv->buf_size;
3083         }
3084         return rx_priv;
3085 }
3086
3087 static uint32_t
3088 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3089 {
3090         uint32_t total_tx_size = 0;
3091         uint32_t i;
3092
3093         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3094                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3095
3096         return total_tx_size;
3097 }
3098
3099 /* Get the number of pfc enabled TCs, which have private buffer */
3100 static int
3101 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3102 {
3103         struct hns3_priv_buf *priv;
3104         int cnt = 0;
3105         uint8_t i;
3106
3107         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3108                 priv = &buf_alloc->priv_buf[i];
3109                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3110                         cnt++;
3111         }
3112
3113         return cnt;
3114 }
3115
3116 /* Get the number of pfc disabled TCs, which have private buffer */
3117 static int
3118 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3119                          struct hns3_pkt_buf_alloc *buf_alloc)
3120 {
3121         struct hns3_priv_buf *priv;
3122         int cnt = 0;
3123         uint8_t i;
3124
3125         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3126                 priv = &buf_alloc->priv_buf[i];
3127                 if (hw->hw_tc_map & BIT(i) &&
3128                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3129                         cnt++;
3130         }
3131
3132         return cnt;
3133 }
3134
3135 static bool
3136 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3137                   uint32_t rx_all)
3138 {
3139         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3140         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3141         struct hns3_pf *pf = &hns->pf;
3142         uint32_t shared_buf, aligned_mps;
3143         uint32_t rx_priv;
3144         uint8_t tc_num;
3145         uint8_t i;
3146
3147         tc_num = hns3_get_tc_num(hw);
3148         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3149
3150         if (hns3_dev_dcb_supported(hw))
3151                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3152                                         pf->dv_buf_size;
3153         else
3154                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3155                                         + pf->dv_buf_size;
3156
3157         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3158         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3159                              HNS3_BUF_SIZE_UNIT);
3160
3161         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3162         if (rx_all < rx_priv + shared_std)
3163                 return false;
3164
3165         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3166         buf_alloc->s_buf.buf_size = shared_buf;
3167         if (hns3_dev_dcb_supported(hw)) {
3168                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3169                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3170                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3171                                   HNS3_BUF_SIZE_UNIT);
3172         } else {
3173                 buf_alloc->s_buf.self.high =
3174                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3175                 buf_alloc->s_buf.self.low = aligned_mps;
3176         }
3177
3178         if (hns3_dev_dcb_supported(hw)) {
3179                 hi_thrd = shared_buf - pf->dv_buf_size;
3180
3181                 if (tc_num <= NEED_RESERVE_TC_NUM)
3182                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3183                                         / BUF_MAX_PERCENT;
3184
3185                 if (tc_num)
3186                         hi_thrd = hi_thrd / tc_num;
3187
3188                 hi_thrd = max_t(uint32_t, hi_thrd,
3189                                 HNS3_BUF_MUL_BY * aligned_mps);
3190                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3191                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3192         } else {
3193                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3194                 lo_thrd = aligned_mps;
3195         }
3196
3197         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3198                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3199                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3200         }
3201
3202         return true;
3203 }
3204
3205 static bool
3206 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3207                      struct hns3_pkt_buf_alloc *buf_alloc)
3208 {
3209         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3210         struct hns3_pf *pf = &hns->pf;
3211         struct hns3_priv_buf *priv;
3212         uint32_t aligned_mps;
3213         uint32_t rx_all;
3214         uint8_t i;
3215
3216         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3217         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3218
3219         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3220                 priv = &buf_alloc->priv_buf[i];
3221
3222                 priv->enable = 0;
3223                 priv->wl.low = 0;
3224                 priv->wl.high = 0;
3225                 priv->buf_size = 0;
3226
3227                 if (!(hw->hw_tc_map & BIT(i)))
3228                         continue;
3229
3230                 priv->enable = 1;
3231                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3232                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3233                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3234                                                 HNS3_BUF_SIZE_UNIT);
3235                 } else {
3236                         priv->wl.low = 0;
3237                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3238                                         aligned_mps;
3239                 }
3240
3241                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3242         }
3243
3244         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3245 }
3246
3247 static bool
3248 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3249                              struct hns3_pkt_buf_alloc *buf_alloc)
3250 {
3251         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3252         struct hns3_pf *pf = &hns->pf;
3253         struct hns3_priv_buf *priv;
3254         int no_pfc_priv_num;
3255         uint32_t rx_all;
3256         uint8_t mask;
3257         int i;
3258
3259         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3260         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3261
3262         /* let the last to be cleared first */
3263         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3264                 priv = &buf_alloc->priv_buf[i];
3265                 mask = BIT((uint8_t)i);
3266
3267                 if (hw->hw_tc_map & mask &&
3268                     !(hw->dcb_info.hw_pfc_map & mask)) {
3269                         /* Clear the no pfc TC private buffer */
3270                         priv->wl.low = 0;
3271                         priv->wl.high = 0;
3272                         priv->buf_size = 0;
3273                         priv->enable = 0;
3274                         no_pfc_priv_num--;
3275                 }
3276
3277                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3278                     no_pfc_priv_num == 0)
3279                         break;
3280         }
3281
3282         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3283 }
3284
3285 static bool
3286 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3287                            struct hns3_pkt_buf_alloc *buf_alloc)
3288 {
3289         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3290         struct hns3_pf *pf = &hns->pf;
3291         struct hns3_priv_buf *priv;
3292         uint32_t rx_all;
3293         int pfc_priv_num;
3294         uint8_t mask;
3295         int i;
3296
3297         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3298         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3299
3300         /* let the last to be cleared first */
3301         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3302                 priv = &buf_alloc->priv_buf[i];
3303                 mask = BIT((uint8_t)i);
3304
3305                 if (hw->hw_tc_map & mask &&
3306                     hw->dcb_info.hw_pfc_map & mask) {
3307                         /* Reduce the number of pfc TC with private buffer */
3308                         priv->wl.low = 0;
3309                         priv->enable = 0;
3310                         priv->wl.high = 0;
3311                         priv->buf_size = 0;
3312                         pfc_priv_num--;
3313                 }
3314                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3315                     pfc_priv_num == 0)
3316                         break;
3317         }
3318
3319         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3320 }
3321
3322 static bool
3323 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3324                           struct hns3_pkt_buf_alloc *buf_alloc)
3325 {
3326 #define COMPENSATE_BUFFER       0x3C00
3327 #define COMPENSATE_HALF_MPS_NUM 5
3328 #define PRIV_WL_GAP             0x1800
3329         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3330         struct hns3_pf *pf = &hns->pf;
3331         uint32_t tc_num = hns3_get_tc_num(hw);
3332         uint32_t half_mps = pf->mps >> 1;
3333         struct hns3_priv_buf *priv;
3334         uint32_t min_rx_priv;
3335         uint32_t rx_priv;
3336         uint8_t i;
3337
3338         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3339         if (tc_num)
3340                 rx_priv = rx_priv / tc_num;
3341
3342         if (tc_num <= NEED_RESERVE_TC_NUM)
3343                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3344
3345         /*
3346          * Minimum value of private buffer in rx direction (min_rx_priv) is
3347          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3348          * buffer if rx_priv is greater than min_rx_priv.
3349          */
3350         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3351                         COMPENSATE_HALF_MPS_NUM * half_mps;
3352         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3353         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3354
3355         if (rx_priv < min_rx_priv)
3356                 return false;
3357
3358         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3359                 priv = &buf_alloc->priv_buf[i];
3360
3361                 priv->enable = 0;
3362                 priv->wl.low = 0;
3363                 priv->wl.high = 0;
3364                 priv->buf_size = 0;
3365
3366                 if (!(hw->hw_tc_map & BIT(i)))
3367                         continue;
3368
3369                 priv->enable = 1;
3370                 priv->buf_size = rx_priv;
3371                 priv->wl.high = rx_priv - pf->dv_buf_size;
3372                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3373         }
3374
3375         buf_alloc->s_buf.buf_size = 0;
3376
3377         return true;
3378 }
3379
3380 /*
3381  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3382  * @hw: pointer to struct hns3_hw
3383  * @buf_alloc: pointer to buffer calculation data
3384  * @return: 0: calculate sucessful, negative: fail
3385  */
3386 static int
3387 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3388 {
3389         /* When DCB is not supported, rx private buffer is not allocated. */
3390         if (!hns3_dev_dcb_supported(hw)) {
3391                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3392                 struct hns3_pf *pf = &hns->pf;
3393                 uint32_t rx_all = pf->pkt_buf_size;
3394
3395                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3396                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3397                         return -ENOMEM;
3398
3399                 return 0;
3400         }
3401
3402         /*
3403          * Try to allocate privated packet buffer for all TCs without share
3404          * buffer.
3405          */
3406         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3407                 return 0;
3408
3409         /*
3410          * Try to allocate privated packet buffer for all TCs with share
3411          * buffer.
3412          */
3413         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3414                 return 0;
3415
3416         /*
3417          * For different application scenes, the enabled port number, TC number
3418          * and no_drop TC number are different. In order to obtain the better
3419          * performance, software could allocate the buffer size and configure
3420          * the waterline by tring to decrease the private buffer size according
3421          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3422          * enabled tc.
3423          */
3424         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3425                 return 0;
3426
3427         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3428                 return 0;
3429
3430         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3431                 return 0;
3432
3433         return -ENOMEM;
3434 }
3435
3436 static int
3437 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3438 {
3439         struct hns3_rx_priv_buff_cmd *req;
3440         struct hns3_cmd_desc desc;
3441         uint32_t buf_size;
3442         int ret;
3443         int i;
3444
3445         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3446         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3447
3448         /* Alloc private buffer TCs */
3449         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3450                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3451
3452                 req->buf_num[i] =
3453                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3454                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3455         }
3456
3457         buf_size = buf_alloc->s_buf.buf_size;
3458         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3459                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3460
3461         ret = hns3_cmd_send(hw, &desc, 1);
3462         if (ret)
3463                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3464
3465         return ret;
3466 }
3467
3468 static int
3469 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3470 {
3471 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3472         struct hns3_rx_priv_wl_buf *req;
3473         struct hns3_priv_buf *priv;
3474         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3475         int i, j;
3476         int ret;
3477
3478         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3479                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3480                                           false);
3481                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3482
3483                 /* The first descriptor set the NEXT bit to 1 */
3484                 if (i == 0)
3485                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3486                 else
3487                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3488
3489                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3490                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3491
3492                         priv = &buf_alloc->priv_buf[idx];
3493                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3494                                                         HNS3_BUF_UNIT_S);
3495                         req->tc_wl[j].high |=
3496                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3497                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3498                                                         HNS3_BUF_UNIT_S);
3499                         req->tc_wl[j].low |=
3500                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3501                 }
3502         }
3503
3504         /* Send 2 descriptor at one time */
3505         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3506         if (ret)
3507                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3508                              ret);
3509         return ret;
3510 }
3511
3512 static int
3513 hns3_common_thrd_config(struct hns3_hw *hw,
3514                         struct hns3_pkt_buf_alloc *buf_alloc)
3515 {
3516 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3517         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3518         struct hns3_rx_com_thrd *req;
3519         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3520         struct hns3_tc_thrd *tc;
3521         int tc_idx;
3522         int i, j;
3523         int ret;
3524
3525         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3526                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3527                                           false);
3528                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3529
3530                 /* The first descriptor set the NEXT bit to 1 */
3531                 if (i == 0)
3532                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3533                 else
3534                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3535
3536                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3537                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3538                         tc = &s_buf->tc_thrd[tc_idx];
3539
3540                         req->com_thrd[j].high =
3541                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3542                         req->com_thrd[j].high |=
3543                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3544                         req->com_thrd[j].low =
3545                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3546                         req->com_thrd[j].low |=
3547                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3548                 }
3549         }
3550
3551         /* Send 2 descriptors at one time */
3552         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3553         if (ret)
3554                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3555
3556         return ret;
3557 }
3558
3559 static int
3560 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3561 {
3562         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3563         struct hns3_rx_com_wl *req;
3564         struct hns3_cmd_desc desc;
3565         int ret;
3566
3567         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3568
3569         req = (struct hns3_rx_com_wl *)desc.data;
3570         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3571         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3572
3573         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3574         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3575
3576         ret = hns3_cmd_send(hw, &desc, 1);
3577         if (ret)
3578                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3579
3580         return ret;
3581 }
3582
3583 int
3584 hns3_buffer_alloc(struct hns3_hw *hw)
3585 {
3586         struct hns3_pkt_buf_alloc pkt_buf;
3587         int ret;
3588
3589         memset(&pkt_buf, 0, sizeof(pkt_buf));
3590         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3591         if (ret) {
3592                 PMD_INIT_LOG(ERR,
3593                              "could not calc tx buffer size for all TCs %d",
3594                              ret);
3595                 return ret;
3596         }
3597
3598         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3599         if (ret) {
3600                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3601                 return ret;
3602         }
3603
3604         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3605         if (ret) {
3606                 PMD_INIT_LOG(ERR,
3607                              "could not calc rx priv buffer size for all TCs %d",
3608                              ret);
3609                 return ret;
3610         }
3611
3612         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3613         if (ret) {
3614                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3615                 return ret;
3616         }
3617
3618         if (hns3_dev_dcb_supported(hw)) {
3619                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3620                 if (ret) {
3621                         PMD_INIT_LOG(ERR,
3622                                      "could not configure rx private waterline %d",
3623                                      ret);
3624                         return ret;
3625                 }
3626
3627                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3628                 if (ret) {
3629                         PMD_INIT_LOG(ERR,
3630                                      "could not configure common threshold %d",
3631                                      ret);
3632                         return ret;
3633                 }
3634         }
3635
3636         ret = hns3_common_wl_config(hw, &pkt_buf);
3637         if (ret)
3638                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3639                              ret);
3640
3641         return ret;
3642 }
3643
3644 static int
3645 hns3_mac_init(struct hns3_hw *hw)
3646 {
3647         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3648         struct hns3_mac *mac = &hw->mac;
3649         struct hns3_pf *pf = &hns->pf;
3650         int ret;
3651
3652         pf->support_sfp_query = true;
3653         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3654         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3655         if (ret) {
3656                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3657                 return ret;
3658         }
3659
3660         mac->link_status = ETH_LINK_DOWN;
3661
3662         return hns3_config_mtu(hw, pf->mps);
3663 }
3664
3665 static int
3666 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3667 {
3668 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3669 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3670 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3671 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3672         int return_status;
3673
3674         if (cmdq_resp) {
3675                 PMD_INIT_LOG(ERR,
3676                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3677                              cmdq_resp);
3678                 return -EIO;
3679         }
3680
3681         switch (resp_code) {
3682         case HNS3_ETHERTYPE_SUCCESS_ADD:
3683         case HNS3_ETHERTYPE_ALREADY_ADD:
3684                 return_status = 0;
3685                 break;
3686         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3687                 PMD_INIT_LOG(ERR,
3688                              "add mac ethertype failed for manager table overflow.");
3689                 return_status = -EIO;
3690                 break;
3691         case HNS3_ETHERTYPE_KEY_CONFLICT:
3692                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3693                 return_status = -EIO;
3694                 break;
3695         default:
3696                 PMD_INIT_LOG(ERR,
3697                              "add mac ethertype failed for undefined, code=%d.",
3698                              resp_code);
3699                 return_status = -EIO;
3700                 break;
3701         }
3702
3703         return return_status;
3704 }
3705
3706 static int
3707 hns3_add_mgr_tbl(struct hns3_hw *hw,
3708                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3709 {
3710         struct hns3_cmd_desc desc;
3711         uint8_t resp_code;
3712         uint16_t retval;
3713         int ret;
3714
3715         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3716         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3717
3718         ret = hns3_cmd_send(hw, &desc, 1);
3719         if (ret) {
3720                 PMD_INIT_LOG(ERR,
3721                              "add mac ethertype failed for cmd_send, ret =%d.",
3722                              ret);
3723                 return ret;
3724         }
3725
3726         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3727         retval = rte_le_to_cpu_16(desc.retval);
3728
3729         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3730 }
3731
3732 static void
3733 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3734                      int *table_item_num)
3735 {
3736         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3737
3738         /*
3739          * In current version, we add one item in management table as below:
3740          * 0x0180C200000E -- LLDP MC address
3741          */
3742         tbl = mgr_table;
3743         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3744         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3745         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3746         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3747         tbl->i_port_bitmap = 0x1;
3748         *table_item_num = 1;
3749 }
3750
3751 static int
3752 hns3_init_mgr_tbl(struct hns3_hw *hw)
3753 {
3754 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3755         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3756         int table_item_num;
3757         int ret;
3758         int i;
3759
3760         memset(mgr_table, 0, sizeof(mgr_table));
3761         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3762         for (i = 0; i < table_item_num; i++) {
3763                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3764                 if (ret) {
3765                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3766                                      ret);
3767                         return ret;
3768                 }
3769         }
3770
3771         return 0;
3772 }
3773
3774 static void
3775 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3776                         bool en_mc, bool en_bc, int vport_id)
3777 {
3778         if (!param)
3779                 return;
3780
3781         memset(param, 0, sizeof(struct hns3_promisc_param));
3782         if (en_uc)
3783                 param->enable = HNS3_PROMISC_EN_UC;
3784         if (en_mc)
3785                 param->enable |= HNS3_PROMISC_EN_MC;
3786         if (en_bc)
3787                 param->enable |= HNS3_PROMISC_EN_BC;
3788         param->vf_id = vport_id;
3789 }
3790
3791 static int
3792 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3793 {
3794         struct hns3_promisc_cfg_cmd *req;
3795         struct hns3_cmd_desc desc;
3796         int ret;
3797
3798         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3799
3800         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3801         req->vf_id = param->vf_id;
3802         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3803             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3804
3805         ret = hns3_cmd_send(hw, &desc, 1);
3806         if (ret)
3807                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3808
3809         return ret;
3810 }
3811
3812 static int
3813 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3814 {
3815         struct hns3_promisc_param param;
3816         bool en_bc_pmc = true;
3817         uint8_t vf_id;
3818
3819         /*
3820          * In current version VF is not supported when PF is driven by DPDK
3821          * driver, just need to configure parameters for PF vport.
3822          */
3823         vf_id = HNS3_PF_FUNC_ID;
3824
3825         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3826         return hns3_cmd_set_promisc_mode(hw, &param);
3827 }
3828
3829 static int
3830 hns3_promisc_init(struct hns3_hw *hw)
3831 {
3832         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3833         struct hns3_pf *pf = &hns->pf;
3834         struct hns3_promisc_param param;
3835         uint16_t func_id;
3836         int ret;
3837
3838         ret = hns3_set_promisc_mode(hw, false, false);
3839         if (ret) {
3840                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3841                 return ret;
3842         }
3843
3844         /*
3845          * In current version VFs are not supported when PF is driven by DPDK
3846          * driver. After PF has been taken over by DPDK, the original VF will
3847          * be invalid. So, there is a possibility of entry residues. It should
3848          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3849          * during init.
3850          */
3851         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3852                 hns3_promisc_param_init(&param, false, false, false, func_id);
3853                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3854                 if (ret) {
3855                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3856                                         " ret = %d", func_id, ret);
3857                         return ret;
3858                 }
3859         }
3860
3861         return 0;
3862 }
3863
3864 static void
3865 hns3_promisc_uninit(struct hns3_hw *hw)
3866 {
3867         struct hns3_promisc_param param;
3868         uint16_t func_id;
3869         int ret;
3870
3871         func_id = HNS3_PF_FUNC_ID;
3872
3873         /*
3874          * In current version VFs are not supported when PF is driven by
3875          * DPDK driver, and VFs' promisc mode status has been cleared during
3876          * init and their status will not change. So just clear PF's promisc
3877          * mode status during uninit.
3878          */
3879         hns3_promisc_param_init(&param, false, false, false, func_id);
3880         ret = hns3_cmd_set_promisc_mode(hw, &param);
3881         if (ret)
3882                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3883                                 " uninit, ret = %d", ret);
3884 }
3885
3886 static int
3887 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3888 {
3889         bool allmulti = dev->data->all_multicast ? true : false;
3890         struct hns3_adapter *hns = dev->data->dev_private;
3891         struct hns3_hw *hw = &hns->hw;
3892         uint64_t offloads;
3893         int err;
3894         int ret;
3895
3896         rte_spinlock_lock(&hw->lock);
3897         ret = hns3_set_promisc_mode(hw, true, true);
3898         if (ret) {
3899                 rte_spinlock_unlock(&hw->lock);
3900                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3901                          ret);
3902                 return ret;
3903         }
3904
3905         /*
3906          * When promiscuous mode was enabled, disable the vlan filter to let
3907          * all packets coming in in the receiving direction.
3908          */
3909         offloads = dev->data->dev_conf.rxmode.offloads;
3910         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3911                 ret = hns3_enable_vlan_filter(hns, false);
3912                 if (ret) {
3913                         hns3_err(hw, "failed to enable promiscuous mode due to "
3914                                      "failure to disable vlan filter, ret = %d",
3915                                  ret);
3916                         err = hns3_set_promisc_mode(hw, false, allmulti);
3917                         if (err)
3918                                 hns3_err(hw, "failed to restore promiscuous "
3919                                          "status after disable vlan filter "
3920                                          "failed during enabling promiscuous "
3921                                          "mode, ret = %d", ret);
3922                 }
3923         }
3924
3925         rte_spinlock_unlock(&hw->lock);
3926
3927         return ret;
3928 }
3929
3930 static int
3931 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3932 {
3933         bool allmulti = dev->data->all_multicast ? true : false;
3934         struct hns3_adapter *hns = dev->data->dev_private;
3935         struct hns3_hw *hw = &hns->hw;
3936         uint64_t offloads;
3937         int err;
3938         int ret;
3939
3940         /* If now in all_multicast mode, must remain in all_multicast mode. */
3941         rte_spinlock_lock(&hw->lock);
3942         ret = hns3_set_promisc_mode(hw, false, allmulti);
3943         if (ret) {
3944                 rte_spinlock_unlock(&hw->lock);
3945                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3946                          ret);
3947                 return ret;
3948         }
3949         /* when promiscuous mode was disabled, restore the vlan filter status */
3950         offloads = dev->data->dev_conf.rxmode.offloads;
3951         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3952                 ret = hns3_enable_vlan_filter(hns, true);
3953                 if (ret) {
3954                         hns3_err(hw, "failed to disable promiscuous mode due to"
3955                                  " failure to restore vlan filter, ret = %d",
3956                                  ret);
3957                         err = hns3_set_promisc_mode(hw, true, true);
3958                         if (err)
3959                                 hns3_err(hw, "failed to restore promiscuous "
3960                                          "status after enabling vlan filter "
3961                                          "failed during disabling promiscuous "
3962                                          "mode, ret = %d", ret);
3963                 }
3964         }
3965         rte_spinlock_unlock(&hw->lock);
3966
3967         return ret;
3968 }
3969
3970 static int
3971 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3972 {
3973         struct hns3_adapter *hns = dev->data->dev_private;
3974         struct hns3_hw *hw = &hns->hw;
3975         int ret;
3976
3977         if (dev->data->promiscuous)
3978                 return 0;
3979
3980         rte_spinlock_lock(&hw->lock);
3981         ret = hns3_set_promisc_mode(hw, false, true);
3982         rte_spinlock_unlock(&hw->lock);
3983         if (ret)
3984                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3985                          ret);
3986
3987         return ret;
3988 }
3989
3990 static int
3991 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3992 {
3993         struct hns3_adapter *hns = dev->data->dev_private;
3994         struct hns3_hw *hw = &hns->hw;
3995         int ret;
3996
3997         /* If now in promiscuous mode, must remain in all_multicast mode. */
3998         if (dev->data->promiscuous)
3999                 return 0;
4000
4001         rte_spinlock_lock(&hw->lock);
4002         ret = hns3_set_promisc_mode(hw, false, false);
4003         rte_spinlock_unlock(&hw->lock);
4004         if (ret)
4005                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4006                          ret);
4007
4008         return ret;
4009 }
4010
4011 static int
4012 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4013 {
4014         struct hns3_hw *hw = &hns->hw;
4015         bool allmulti = hw->data->all_multicast ? true : false;
4016         int ret;
4017
4018         if (hw->data->promiscuous) {
4019                 ret = hns3_set_promisc_mode(hw, true, true);
4020                 if (ret)
4021                         hns3_err(hw, "failed to restore promiscuous mode, "
4022                                  "ret = %d", ret);
4023                 return ret;
4024         }
4025
4026         ret = hns3_set_promisc_mode(hw, false, allmulti);
4027         if (ret)
4028                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4029                          ret);
4030         return ret;
4031 }
4032
4033 static int
4034 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4035 {
4036         struct hns3_sfp_speed_cmd *resp;
4037         struct hns3_cmd_desc desc;
4038         int ret;
4039
4040         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4041         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4042         ret = hns3_cmd_send(hw, &desc, 1);
4043         if (ret == -EOPNOTSUPP) {
4044                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4045                 return ret;
4046         } else if (ret) {
4047                 hns3_err(hw, "get sfp speed failed %d", ret);
4048                 return ret;
4049         }
4050
4051         *speed = resp->sfp_speed;
4052
4053         return 0;
4054 }
4055
4056 static uint8_t
4057 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4058 {
4059         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4060                 duplex = ETH_LINK_FULL_DUPLEX;
4061
4062         return duplex;
4063 }
4064
4065 static int
4066 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4067 {
4068         struct hns3_mac *mac = &hw->mac;
4069         int ret;
4070
4071         duplex = hns3_check_speed_dup(duplex, speed);
4072         if (mac->link_speed == speed && mac->link_duplex == duplex)
4073                 return 0;
4074
4075         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4076         if (ret)
4077                 return ret;
4078
4079         mac->link_speed = speed;
4080         mac->link_duplex = duplex;
4081
4082         return 0;
4083 }
4084
4085 static int
4086 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4087 {
4088         struct hns3_adapter *hns = eth_dev->data->dev_private;
4089         struct hns3_hw *hw = &hns->hw;
4090         struct hns3_pf *pf = &hns->pf;
4091         uint32_t speed;
4092         int ret;
4093
4094         /* If IMP do not support get SFP/qSFP speed, return directly */
4095         if (!pf->support_sfp_query)
4096                 return 0;
4097
4098         ret = hns3_get_sfp_speed(hw, &speed);
4099         if (ret == -EOPNOTSUPP) {
4100                 pf->support_sfp_query = false;
4101                 return ret;
4102         } else if (ret)
4103                 return ret;
4104
4105         if (speed == ETH_SPEED_NUM_NONE)
4106                 return 0; /* do nothing if no SFP */
4107
4108         /* Config full duplex for SFP */
4109         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4110 }
4111
4112 static int
4113 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4114 {
4115         struct hns3_config_mac_mode_cmd *req;
4116         struct hns3_cmd_desc desc;
4117         uint32_t loop_en = 0;
4118         uint8_t val = 0;
4119         int ret;
4120
4121         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4122
4123         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4124         if (enable)
4125                 val = 1;
4126         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4127         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4128         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4129         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4130         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4131         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4132         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4133         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4134         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4135         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4136         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4137         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4138         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4139         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4140         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4141
4142         ret = hns3_cmd_send(hw, &desc, 1);
4143         if (ret)
4144                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4145
4146         return ret;
4147 }
4148
4149 static int
4150 hns3_get_mac_link_status(struct hns3_hw *hw)
4151 {
4152         struct hns3_link_status_cmd *req;
4153         struct hns3_cmd_desc desc;
4154         int link_status;
4155         int ret;
4156
4157         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4158         ret = hns3_cmd_send(hw, &desc, 1);
4159         if (ret) {
4160                 hns3_err(hw, "get link status cmd failed %d", ret);
4161                 return ETH_LINK_DOWN;
4162         }
4163
4164         req = (struct hns3_link_status_cmd *)desc.data;
4165         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4166
4167         return !!link_status;
4168 }
4169
4170 void
4171 hns3_update_link_status(struct hns3_hw *hw)
4172 {
4173         int state;
4174
4175         state = hns3_get_mac_link_status(hw);
4176         if (state != hw->mac.link_status) {
4177                 hw->mac.link_status = state;
4178                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4179         }
4180 }
4181
4182 static void
4183 hns3_service_handler(void *param)
4184 {
4185         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4186         struct hns3_adapter *hns = eth_dev->data->dev_private;
4187         struct hns3_hw *hw = &hns->hw;
4188
4189         if (!hns3_is_reset_pending(hns)) {
4190                 hns3_update_speed_duplex(eth_dev);
4191                 hns3_update_link_status(hw);
4192         } else
4193                 hns3_warn(hw, "Cancel the query when reset is pending");
4194
4195         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4196 }
4197
4198 static int
4199 hns3_init_hardware(struct hns3_adapter *hns)
4200 {
4201         struct hns3_hw *hw = &hns->hw;
4202         int ret;
4203
4204         ret = hns3_map_tqp(hw);
4205         if (ret) {
4206                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4207                 return ret;
4208         }
4209
4210         ret = hns3_init_umv_space(hw);
4211         if (ret) {
4212                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4213                 return ret;
4214         }
4215
4216         ret = hns3_mac_init(hw);
4217         if (ret) {
4218                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4219                 goto err_mac_init;
4220         }
4221
4222         ret = hns3_init_mgr_tbl(hw);
4223         if (ret) {
4224                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4225                 goto err_mac_init;
4226         }
4227
4228         ret = hns3_promisc_init(hw);
4229         if (ret) {
4230                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4231                              ret);
4232                 goto err_mac_init;
4233         }
4234
4235         ret = hns3_init_vlan_config(hns);
4236         if (ret) {
4237                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4238                 goto err_mac_init;
4239         }
4240
4241         ret = hns3_dcb_init(hw);
4242         if (ret) {
4243                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4244                 goto err_mac_init;
4245         }
4246
4247         ret = hns3_init_fd_config(hns);
4248         if (ret) {
4249                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4250                 goto err_mac_init;
4251         }
4252
4253         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4254         if (ret) {
4255                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4256                 goto err_mac_init;
4257         }
4258
4259         ret = hns3_config_gro(hw, false);
4260         if (ret) {
4261                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4262                 goto err_mac_init;
4263         }
4264
4265         /*
4266          * In the initialization clearing the all hardware mapping relationship
4267          * configurations between queues and interrupt vectors is needed, so
4268          * some error caused by the residual configurations, such as the
4269          * unexpected interrupt, can be avoid.
4270          */
4271         ret = hns3_init_ring_with_vector(hw);
4272         if (ret) {
4273                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4274                 goto err_mac_init;
4275         }
4276
4277         return 0;
4278
4279 err_mac_init:
4280         hns3_uninit_umv_space(hw);
4281         return ret;
4282 }
4283
4284 static int
4285 hns3_init_pf(struct rte_eth_dev *eth_dev)
4286 {
4287         struct rte_device *dev = eth_dev->device;
4288         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4289         struct hns3_adapter *hns = eth_dev->data->dev_private;
4290         struct hns3_hw *hw = &hns->hw;
4291         int ret;
4292
4293         PMD_INIT_FUNC_TRACE();
4294
4295         /* Get hardware io base address from pcie BAR2 IO space */
4296         hw->io_base = pci_dev->mem_resource[2].addr;
4297
4298         /* Firmware command queue initialize */
4299         ret = hns3_cmd_init_queue(hw);
4300         if (ret) {
4301                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4302                 goto err_cmd_init_queue;
4303         }
4304
4305         hns3_clear_all_event_cause(hw);
4306
4307         /* Firmware command initialize */
4308         ret = hns3_cmd_init(hw);
4309         if (ret) {
4310                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4311                 goto err_cmd_init;
4312         }
4313
4314         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4315                                          hns3_interrupt_handler,
4316                                          eth_dev);
4317         if (ret) {
4318                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4319                 goto err_intr_callback_register;
4320         }
4321
4322         /* Enable interrupt */
4323         rte_intr_enable(&pci_dev->intr_handle);
4324         hns3_pf_enable_irq0(hw);
4325
4326         /* Get configuration */
4327         ret = hns3_get_configuration(hw);
4328         if (ret) {
4329                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4330                 goto err_get_config;
4331         }
4332
4333         ret = hns3_init_hardware(hns);
4334         if (ret) {
4335                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4336                 goto err_get_config;
4337         }
4338
4339         /* Initialize flow director filter list & hash */
4340         ret = hns3_fdir_filter_init(hns);
4341         if (ret) {
4342                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4343                 goto err_hw_init;
4344         }
4345
4346         hns3_set_default_rss_args(hw);
4347
4348         ret = hns3_enable_hw_error_intr(hns, true);
4349         if (ret) {
4350                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4351                              ret);
4352                 goto err_fdir;
4353         }
4354
4355         return 0;
4356
4357 err_fdir:
4358         hns3_fdir_filter_uninit(hns);
4359 err_hw_init:
4360         hns3_uninit_umv_space(hw);
4361
4362 err_get_config:
4363         hns3_pf_disable_irq0(hw);
4364         rte_intr_disable(&pci_dev->intr_handle);
4365         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4366                              eth_dev);
4367 err_intr_callback_register:
4368 err_cmd_init:
4369         hns3_cmd_uninit(hw);
4370         hns3_cmd_destroy_queue(hw);
4371 err_cmd_init_queue:
4372         hw->io_base = NULL;
4373
4374         return ret;
4375 }
4376
4377 static void
4378 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4379 {
4380         struct hns3_adapter *hns = eth_dev->data->dev_private;
4381         struct rte_device *dev = eth_dev->device;
4382         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4383         struct hns3_hw *hw = &hns->hw;
4384
4385         PMD_INIT_FUNC_TRACE();
4386
4387         hns3_enable_hw_error_intr(hns, false);
4388         hns3_rss_uninit(hns);
4389         hns3_promisc_uninit(hw);
4390         hns3_fdir_filter_uninit(hns);
4391         hns3_uninit_umv_space(hw);
4392         hns3_pf_disable_irq0(hw);
4393         rte_intr_disable(&pci_dev->intr_handle);
4394         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4395                              eth_dev);
4396         hns3_cmd_uninit(hw);
4397         hns3_cmd_destroy_queue(hw);
4398         hw->io_base = NULL;
4399 }
4400
4401 static int
4402 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4403 {
4404         struct hns3_hw *hw = &hns->hw;
4405         int ret;
4406
4407         ret = hns3_dcb_cfg_update(hns);
4408         if (ret)
4409                 return ret;
4410
4411         /* Enable queues */
4412         ret = hns3_start_queues(hns, reset_queue);
4413         if (ret) {
4414                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4415                 return ret;
4416         }
4417
4418         /* Enable MAC */
4419         ret = hns3_cfg_mac_mode(hw, true);
4420         if (ret) {
4421                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4422                 goto err_config_mac_mode;
4423         }
4424         return 0;
4425
4426 err_config_mac_mode:
4427         hns3_stop_queues(hns, true);
4428         return ret;
4429 }
4430
4431 static int
4432 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4433 {
4434         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4435         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4436         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4437         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4438         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4439         uint32_t intr_vector;
4440         uint16_t q_id;
4441         int ret;
4442
4443         if (dev->data->dev_conf.intr_conf.rxq == 0)
4444                 return 0;
4445
4446         /* disable uio/vfio intr/eventfd mapping */
4447         rte_intr_disable(intr_handle);
4448
4449         /* check and configure queue intr-vector mapping */
4450         if (rte_intr_cap_multiple(intr_handle) ||
4451             !RTE_ETH_DEV_SRIOV(dev).active) {
4452                 intr_vector = hw->used_rx_queues;
4453                 /* creates event fd for each intr vector when MSIX is used */
4454                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4455                         return -EINVAL;
4456         }
4457         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4458                 intr_handle->intr_vec =
4459                         rte_zmalloc("intr_vec",
4460                                     hw->used_rx_queues * sizeof(int), 0);
4461                 if (intr_handle->intr_vec == NULL) {
4462                         hns3_err(hw, "Failed to allocate %d rx_queues"
4463                                      " intr_vec", hw->used_rx_queues);
4464                         ret = -ENOMEM;
4465                         goto alloc_intr_vec_error;
4466                 }
4467         }
4468
4469         if (rte_intr_allow_others(intr_handle)) {
4470                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4471                 base = RTE_INTR_VEC_RXTX_OFFSET;
4472         }
4473         if (rte_intr_dp_is_en(intr_handle)) {
4474                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4475                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4476                                                          HNS3_RING_TYPE_RX,
4477                                                          q_id);
4478                         if (ret)
4479                                 goto bind_vector_error;
4480                         intr_handle->intr_vec[q_id] = vec;
4481                         if (vec < base + intr_handle->nb_efd - 1)
4482                                 vec++;
4483                 }
4484         }
4485         rte_intr_enable(intr_handle);
4486         return 0;
4487
4488 bind_vector_error:
4489         rte_intr_efd_disable(intr_handle);
4490         if (intr_handle->intr_vec) {
4491                 free(intr_handle->intr_vec);
4492                 intr_handle->intr_vec = NULL;
4493         }
4494         return ret;
4495 alloc_intr_vec_error:
4496         rte_intr_efd_disable(intr_handle);
4497         return ret;
4498 }
4499
4500 static int
4501 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4502 {
4503         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4504         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4505         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4506         uint16_t q_id;
4507         int ret;
4508
4509         if (dev->data->dev_conf.intr_conf.rxq == 0)
4510                 return 0;
4511
4512         if (rte_intr_dp_is_en(intr_handle)) {
4513                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4514                         ret = hns3_bind_ring_with_vector(hw,
4515                                         intr_handle->intr_vec[q_id], true,
4516                                         HNS3_RING_TYPE_RX, q_id);
4517                         if (ret)
4518                                 return ret;
4519                 }
4520         }
4521
4522         return 0;
4523 }
4524
4525 static void
4526 hns3_restore_filter(struct rte_eth_dev *dev)
4527 {
4528         hns3_restore_rss_filter(dev);
4529 }
4530
4531 static int
4532 hns3_dev_start(struct rte_eth_dev *dev)
4533 {
4534         struct hns3_adapter *hns = dev->data->dev_private;
4535         struct hns3_hw *hw = &hns->hw;
4536         int ret;
4537
4538         PMD_INIT_FUNC_TRACE();
4539         if (rte_atomic16_read(&hw->reset.resetting))
4540                 return -EBUSY;
4541
4542         rte_spinlock_lock(&hw->lock);
4543         hw->adapter_state = HNS3_NIC_STARTING;
4544
4545         ret = hns3_do_start(hns, true);
4546         if (ret) {
4547                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4548                 rte_spinlock_unlock(&hw->lock);
4549                 return ret;
4550         }
4551         ret = hns3_map_rx_interrupt(dev);
4552         if (ret) {
4553                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4554                 rte_spinlock_unlock(&hw->lock);
4555                 return ret;
4556         }
4557
4558         hw->adapter_state = HNS3_NIC_STARTED;
4559         rte_spinlock_unlock(&hw->lock);
4560
4561         hns3_set_rxtx_function(dev);
4562         hns3_mp_req_start_rxtx(dev);
4563         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4564
4565         hns3_restore_filter(dev);
4566
4567         /* Enable interrupt of all rx queues before enabling queues */
4568         hns3_dev_all_rx_queue_intr_enable(hw, true);
4569         /*
4570          * When finished the initialization, enable queues to receive/transmit
4571          * packets.
4572          */
4573         hns3_enable_all_queues(hw, true);
4574
4575         hns3_info(hw, "hns3 dev start successful!");
4576         return 0;
4577 }
4578
4579 static int
4580 hns3_do_stop(struct hns3_adapter *hns)
4581 {
4582         struct hns3_hw *hw = &hns->hw;
4583         bool reset_queue;
4584         int ret;
4585
4586         ret = hns3_cfg_mac_mode(hw, false);
4587         if (ret)
4588                 return ret;
4589         hw->mac.link_status = ETH_LINK_DOWN;
4590
4591         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4592                 hns3_configure_all_mac_addr(hns, true);
4593                 reset_queue = true;
4594         } else
4595                 reset_queue = false;
4596         hw->mac.default_addr_setted = false;
4597         return hns3_stop_queues(hns, reset_queue);
4598 }
4599
4600 static void
4601 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4602 {
4603         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4605         struct hns3_adapter *hns = dev->data->dev_private;
4606         struct hns3_hw *hw = &hns->hw;
4607         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4608         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4609         uint16_t q_id;
4610
4611         if (dev->data->dev_conf.intr_conf.rxq == 0)
4612                 return;
4613
4614         /* unmap the ring with vector */
4615         if (rte_intr_allow_others(intr_handle)) {
4616                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4617                 base = RTE_INTR_VEC_RXTX_OFFSET;
4618         }
4619         if (rte_intr_dp_is_en(intr_handle)) {
4620                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4621                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4622                                                          HNS3_RING_TYPE_RX,
4623                                                          q_id);
4624                         if (vec < base + intr_handle->nb_efd - 1)
4625                                 vec++;
4626                 }
4627         }
4628         /* Clean datapath event and queue/vec mapping */
4629         rte_intr_efd_disable(intr_handle);
4630         if (intr_handle->intr_vec) {
4631                 rte_free(intr_handle->intr_vec);
4632                 intr_handle->intr_vec = NULL;
4633         }
4634 }
4635
4636 static void
4637 hns3_dev_stop(struct rte_eth_dev *dev)
4638 {
4639         struct hns3_adapter *hns = dev->data->dev_private;
4640         struct hns3_hw *hw = &hns->hw;
4641
4642         PMD_INIT_FUNC_TRACE();
4643
4644         hw->adapter_state = HNS3_NIC_STOPPING;
4645         hns3_set_rxtx_function(dev);
4646         rte_wmb();
4647         /* Disable datapath on secondary process. */
4648         hns3_mp_req_stop_rxtx(dev);
4649         /* Prevent crashes when queues are still in use. */
4650         rte_delay_ms(hw->tqps_num);
4651
4652         rte_spinlock_lock(&hw->lock);
4653         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4654                 hns3_do_stop(hns);
4655                 hns3_unmap_rx_interrupt(dev);
4656                 hns3_dev_release_mbufs(hns);
4657                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4658         }
4659         rte_eal_alarm_cancel(hns3_service_handler, dev);
4660         rte_spinlock_unlock(&hw->lock);
4661 }
4662
4663 static void
4664 hns3_dev_close(struct rte_eth_dev *eth_dev)
4665 {
4666         struct hns3_adapter *hns = eth_dev->data->dev_private;
4667         struct hns3_hw *hw = &hns->hw;
4668
4669         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4670                 rte_free(eth_dev->process_private);
4671                 eth_dev->process_private = NULL;
4672                 return;
4673         }
4674
4675         if (hw->adapter_state == HNS3_NIC_STARTED)
4676                 hns3_dev_stop(eth_dev);
4677
4678         hw->adapter_state = HNS3_NIC_CLOSING;
4679         hns3_reset_abort(hns);
4680         hw->adapter_state = HNS3_NIC_CLOSED;
4681
4682         hns3_configure_all_mc_mac_addr(hns, true);
4683         hns3_remove_all_vlan_table(hns);
4684         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4685         hns3_uninit_pf(eth_dev);
4686         hns3_free_all_queues(eth_dev);
4687         rte_free(hw->reset.wait_data);
4688         rte_free(eth_dev->process_private);
4689         eth_dev->process_private = NULL;
4690         hns3_mp_uninit_primary();
4691         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4692 }
4693
4694 static int
4695 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4696 {
4697         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4699
4700         fc_conf->pause_time = pf->pause_time;
4701
4702         /* return fc current mode */
4703         switch (hw->current_mode) {
4704         case HNS3_FC_FULL:
4705                 fc_conf->mode = RTE_FC_FULL;
4706                 break;
4707         case HNS3_FC_TX_PAUSE:
4708                 fc_conf->mode = RTE_FC_TX_PAUSE;
4709                 break;
4710         case HNS3_FC_RX_PAUSE:
4711                 fc_conf->mode = RTE_FC_RX_PAUSE;
4712                 break;
4713         case HNS3_FC_NONE:
4714         default:
4715                 fc_conf->mode = RTE_FC_NONE;
4716                 break;
4717         }
4718
4719         return 0;
4720 }
4721
4722 static void
4723 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4724 {
4725         switch (mode) {
4726         case RTE_FC_NONE:
4727                 hw->requested_mode = HNS3_FC_NONE;
4728                 break;
4729         case RTE_FC_RX_PAUSE:
4730                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4731                 break;
4732         case RTE_FC_TX_PAUSE:
4733                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4734                 break;
4735         case RTE_FC_FULL:
4736                 hw->requested_mode = HNS3_FC_FULL;
4737                 break;
4738         default:
4739                 hw->requested_mode = HNS3_FC_NONE;
4740                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4741                           "configured to RTE_FC_NONE", mode);
4742                 break;
4743         }
4744 }
4745
4746 static int
4747 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4748 {
4749         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4751         int ret;
4752
4753         if (fc_conf->high_water || fc_conf->low_water ||
4754             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4755                 hns3_err(hw, "Unsupported flow control settings specified, "
4756                          "high_water(%u), low_water(%u), send_xon(%u) and "
4757                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4758                          fc_conf->high_water, fc_conf->low_water,
4759                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4760                 return -EINVAL;
4761         }
4762         if (fc_conf->autoneg) {
4763                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4764                 return -EINVAL;
4765         }
4766         if (!fc_conf->pause_time) {
4767                 hns3_err(hw, "Invalid pause time %d setting.",
4768                          fc_conf->pause_time);
4769                 return -EINVAL;
4770         }
4771
4772         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4773             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4774                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4775                          "current_fc_status = %d", hw->current_fc_status);
4776                 return -EOPNOTSUPP;
4777         }
4778
4779         hns3_get_fc_mode(hw, fc_conf->mode);
4780         if (hw->requested_mode == hw->current_mode &&
4781             pf->pause_time == fc_conf->pause_time)
4782                 return 0;
4783
4784         rte_spinlock_lock(&hw->lock);
4785         ret = hns3_fc_enable(dev, fc_conf);
4786         rte_spinlock_unlock(&hw->lock);
4787
4788         return ret;
4789 }
4790
4791 static int
4792 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4793                             struct rte_eth_pfc_conf *pfc_conf)
4794 {
4795         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4797         uint8_t priority;
4798         int ret;
4799
4800         if (!hns3_dev_dcb_supported(hw)) {
4801                 hns3_err(hw, "This port does not support dcb configurations.");
4802                 return -EOPNOTSUPP;
4803         }
4804
4805         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4806             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4807                 hns3_err(hw, "Unsupported flow control settings specified, "
4808                          "high_water(%u), low_water(%u), send_xon(%u) and "
4809                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4810                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4811                          pfc_conf->fc.send_xon,
4812                          pfc_conf->fc.mac_ctrl_frame_fwd);
4813                 return -EINVAL;
4814         }
4815         if (pfc_conf->fc.autoneg) {
4816                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4817                 return -EINVAL;
4818         }
4819         if (pfc_conf->fc.pause_time == 0) {
4820                 hns3_err(hw, "Invalid pause time %d setting.",
4821                          pfc_conf->fc.pause_time);
4822                 return -EINVAL;
4823         }
4824
4825         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4826             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4827                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4828                              "current_fc_status = %d", hw->current_fc_status);
4829                 return -EOPNOTSUPP;
4830         }
4831
4832         priority = pfc_conf->priority;
4833         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4834         if (hw->dcb_info.pfc_en & BIT(priority) &&
4835             hw->requested_mode == hw->current_mode &&
4836             pfc_conf->fc.pause_time == pf->pause_time)
4837                 return 0;
4838
4839         rte_spinlock_lock(&hw->lock);
4840         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4841         rte_spinlock_unlock(&hw->lock);
4842
4843         return ret;
4844 }
4845
4846 static int
4847 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4848 {
4849         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4851         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4852         int i;
4853
4854         rte_spinlock_lock(&hw->lock);
4855         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4856                 dcb_info->nb_tcs = pf->local_max_tc;
4857         else
4858                 dcb_info->nb_tcs = 1;
4859
4860         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4861                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4862         for (i = 0; i < dcb_info->nb_tcs; i++)
4863                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4864
4865         for (i = 0; i < hw->num_tc; i++) {
4866                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4867                 dcb_info->tc_queue.tc_txq[0][i].base =
4868                                                 hw->tc_queue[i].tqp_offset;
4869                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4870                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4871                                                 hw->tc_queue[i].tqp_count;
4872         }
4873         rte_spinlock_unlock(&hw->lock);
4874
4875         return 0;
4876 }
4877
4878 static int
4879 hns3_reinit_dev(struct hns3_adapter *hns)
4880 {
4881         struct hns3_hw *hw = &hns->hw;
4882         int ret;
4883
4884         ret = hns3_cmd_init(hw);
4885         if (ret) {
4886                 hns3_err(hw, "Failed to init cmd: %d", ret);
4887                 return ret;
4888         }
4889
4890         ret = hns3_reset_all_queues(hns);
4891         if (ret) {
4892                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4893                 return ret;
4894         }
4895
4896         ret = hns3_init_hardware(hns);
4897         if (ret) {
4898                 hns3_err(hw, "Failed to init hardware: %d", ret);
4899                 return ret;
4900         }
4901
4902         ret = hns3_enable_hw_error_intr(hns, true);
4903         if (ret) {
4904                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4905                              ret);
4906                 return ret;
4907         }
4908         hns3_info(hw, "Reset done, driver initialization finished.");
4909
4910         return 0;
4911 }
4912
4913 static bool
4914 is_pf_reset_done(struct hns3_hw *hw)
4915 {
4916         uint32_t val, reg, reg_bit;
4917
4918         switch (hw->reset.level) {
4919         case HNS3_IMP_RESET:
4920                 reg = HNS3_GLOBAL_RESET_REG;
4921                 reg_bit = HNS3_IMP_RESET_BIT;
4922                 break;
4923         case HNS3_GLOBAL_RESET:
4924                 reg = HNS3_GLOBAL_RESET_REG;
4925                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4926                 break;
4927         case HNS3_FUNC_RESET:
4928                 reg = HNS3_FUN_RST_ING;
4929                 reg_bit = HNS3_FUN_RST_ING_B;
4930                 break;
4931         case HNS3_FLR_RESET:
4932         default:
4933                 hns3_err(hw, "Wait for unsupported reset level: %d",
4934                          hw->reset.level);
4935                 return true;
4936         }
4937         val = hns3_read_dev(hw, reg);
4938         if (hns3_get_bit(val, reg_bit))
4939                 return false;
4940         else
4941                 return true;
4942 }
4943
4944 bool
4945 hns3_is_reset_pending(struct hns3_adapter *hns)
4946 {
4947         struct hns3_hw *hw = &hns->hw;
4948         enum hns3_reset_level reset;
4949
4950         hns3_check_event_cause(hns, NULL);
4951         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4952         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4953                 hns3_warn(hw, "High level reset %d is pending", reset);
4954                 return true;
4955         }
4956         reset = hns3_get_reset_level(hns, &hw->reset.request);
4957         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4958                 hns3_warn(hw, "High level reset %d is request", reset);
4959                 return true;
4960         }
4961         return false;
4962 }
4963
4964 static int
4965 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4966 {
4967         struct hns3_hw *hw = &hns->hw;
4968         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4969         struct timeval tv;
4970
4971         if (wait_data->result == HNS3_WAIT_SUCCESS)
4972                 return 0;
4973         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4974                 gettimeofday(&tv, NULL);
4975                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4976                           tv.tv_sec, tv.tv_usec);
4977                 return -ETIME;
4978         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4979                 return -EAGAIN;
4980
4981         wait_data->hns = hns;
4982         wait_data->check_completion = is_pf_reset_done;
4983         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4984                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4985         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4986         wait_data->count = HNS3_RESET_WAIT_CNT;
4987         wait_data->result = HNS3_WAIT_REQUEST;
4988         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4989         return -EAGAIN;
4990 }
4991
4992 static int
4993 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4994 {
4995         struct hns3_cmd_desc desc;
4996         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4997
4998         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4999         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5000         req->fun_reset_vfid = func_id;
5001
5002         return hns3_cmd_send(hw, &desc, 1);
5003 }
5004
5005 static int
5006 hns3_imp_reset_cmd(struct hns3_hw *hw)
5007 {
5008         struct hns3_cmd_desc desc;
5009
5010         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5011         desc.data[0] = 0xeedd;
5012
5013         return hns3_cmd_send(hw, &desc, 1);
5014 }
5015
5016 static void
5017 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5018 {
5019         struct hns3_hw *hw = &hns->hw;
5020         struct timeval tv;
5021         uint32_t val;
5022
5023         gettimeofday(&tv, NULL);
5024         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5025             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5026                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5027                           tv.tv_sec, tv.tv_usec);
5028                 return;
5029         }
5030
5031         switch (reset_level) {
5032         case HNS3_IMP_RESET:
5033                 hns3_imp_reset_cmd(hw);
5034                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5035                           tv.tv_sec, tv.tv_usec);
5036                 break;
5037         case HNS3_GLOBAL_RESET:
5038                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5039                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5040                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5041                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5042                           tv.tv_sec, tv.tv_usec);
5043                 break;
5044         case HNS3_FUNC_RESET:
5045                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5046                           tv.tv_sec, tv.tv_usec);
5047                 /* schedule again to check later */
5048                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5049                 hns3_schedule_reset(hns);
5050                 break;
5051         default:
5052                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5053                 return;
5054         }
5055         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5056 }
5057
5058 static enum hns3_reset_level
5059 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5060 {
5061         struct hns3_hw *hw = &hns->hw;
5062         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5063
5064         /* Return the highest priority reset level amongst all */
5065         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5066                 reset_level = HNS3_IMP_RESET;
5067         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5068                 reset_level = HNS3_GLOBAL_RESET;
5069         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5070                 reset_level = HNS3_FUNC_RESET;
5071         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5072                 reset_level = HNS3_FLR_RESET;
5073
5074         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5075                 return HNS3_NONE_RESET;
5076
5077         return reset_level;
5078 }
5079
5080 static int
5081 hns3_prepare_reset(struct hns3_adapter *hns)
5082 {
5083         struct hns3_hw *hw = &hns->hw;
5084         uint32_t reg_val;
5085         int ret;
5086
5087         switch (hw->reset.level) {
5088         case HNS3_FUNC_RESET:
5089                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5090                 if (ret)
5091                         return ret;
5092
5093                 /*
5094                  * After performaning pf reset, it is not necessary to do the
5095                  * mailbox handling or send any command to firmware, because
5096                  * any mailbox handling or command to firmware is only valid
5097                  * after hns3_cmd_init is called.
5098                  */
5099                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5100                 hw->reset.stats.request_cnt++;
5101                 break;
5102         case HNS3_IMP_RESET:
5103                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5104                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5105                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5106                 break;
5107         default:
5108                 break;
5109         }
5110         return 0;
5111 }
5112
5113 static int
5114 hns3_set_rst_done(struct hns3_hw *hw)
5115 {
5116         struct hns3_pf_rst_done_cmd *req;
5117         struct hns3_cmd_desc desc;
5118
5119         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5120         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5121         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5122         return hns3_cmd_send(hw, &desc, 1);
5123 }
5124
5125 static int
5126 hns3_stop_service(struct hns3_adapter *hns)
5127 {
5128         struct hns3_hw *hw = &hns->hw;
5129         struct rte_eth_dev *eth_dev;
5130
5131         eth_dev = &rte_eth_devices[hw->data->port_id];
5132         if (hw->adapter_state == HNS3_NIC_STARTED)
5133                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5134         hw->mac.link_status = ETH_LINK_DOWN;
5135
5136         hns3_set_rxtx_function(eth_dev);
5137         rte_wmb();
5138         /* Disable datapath on secondary process. */
5139         hns3_mp_req_stop_rxtx(eth_dev);
5140         rte_delay_ms(hw->tqps_num);
5141
5142         rte_spinlock_lock(&hw->lock);
5143         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5144             hw->adapter_state == HNS3_NIC_STOPPING) {
5145                 hns3_do_stop(hns);
5146                 hw->reset.mbuf_deferred_free = true;
5147         } else
5148                 hw->reset.mbuf_deferred_free = false;
5149
5150         /*
5151          * It is cumbersome for hardware to pick-and-choose entries for deletion
5152          * from table space. Hence, for function reset software intervention is
5153          * required to delete the entries
5154          */
5155         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5156                 hns3_configure_all_mc_mac_addr(hns, true);
5157         rte_spinlock_unlock(&hw->lock);
5158
5159         return 0;
5160 }
5161
5162 static int
5163 hns3_start_service(struct hns3_adapter *hns)
5164 {
5165         struct hns3_hw *hw = &hns->hw;
5166         struct rte_eth_dev *eth_dev;
5167
5168         if (hw->reset.level == HNS3_IMP_RESET ||
5169             hw->reset.level == HNS3_GLOBAL_RESET)
5170                 hns3_set_rst_done(hw);
5171         eth_dev = &rte_eth_devices[hw->data->port_id];
5172         hns3_set_rxtx_function(eth_dev);
5173         hns3_mp_req_start_rxtx(eth_dev);
5174         if (hw->adapter_state == HNS3_NIC_STARTED) {
5175                 hns3_service_handler(eth_dev);
5176
5177                 /* Enable interrupt of all rx queues before enabling queues */
5178                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5179                 /*
5180                  * When finished the initialization, enable queues to receive
5181                  * and transmit packets.
5182                  */
5183                 hns3_enable_all_queues(hw, true);
5184         }
5185
5186         return 0;
5187 }
5188
5189 static int
5190 hns3_restore_conf(struct hns3_adapter *hns)
5191 {
5192         struct hns3_hw *hw = &hns->hw;
5193         int ret;
5194
5195         ret = hns3_configure_all_mac_addr(hns, false);
5196         if (ret)
5197                 return ret;
5198
5199         ret = hns3_configure_all_mc_mac_addr(hns, false);
5200         if (ret)
5201                 goto err_mc_mac;
5202
5203         ret = hns3_dev_promisc_restore(hns);
5204         if (ret)
5205                 goto err_promisc;
5206
5207         ret = hns3_restore_vlan_table(hns);
5208         if (ret)
5209                 goto err_promisc;
5210
5211         ret = hns3_restore_vlan_conf(hns);
5212         if (ret)
5213                 goto err_promisc;
5214
5215         ret = hns3_restore_all_fdir_filter(hns);
5216         if (ret)
5217                 goto err_promisc;
5218
5219         ret = hns3_restore_rx_interrupt(hw);
5220         if (ret)
5221                 goto err_promisc;
5222
5223         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5224                 ret = hns3_do_start(hns, false);
5225                 if (ret)
5226                         goto err_promisc;
5227                 hns3_info(hw, "hns3 dev restart successful!");
5228         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5229                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5230         return 0;
5231
5232 err_promisc:
5233         hns3_configure_all_mc_mac_addr(hns, true);
5234 err_mc_mac:
5235         hns3_configure_all_mac_addr(hns, true);
5236         return ret;
5237 }
5238
5239 static void
5240 hns3_reset_service(void *param)
5241 {
5242         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5243         struct hns3_hw *hw = &hns->hw;
5244         enum hns3_reset_level reset_level;
5245         struct timeval tv_delta;
5246         struct timeval tv_start;
5247         struct timeval tv;
5248         uint64_t msec;
5249         int ret;
5250
5251         /*
5252          * The interrupt is not triggered within the delay time.
5253          * The interrupt may have been lost. It is necessary to handle
5254          * the interrupt to recover from the error.
5255          */
5256         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5257                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5258                 hns3_err(hw, "Handling interrupts in delayed tasks");
5259                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5260                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5261                 if (reset_level == HNS3_NONE_RESET) {
5262                         hns3_err(hw, "No reset level is set, try IMP reset");
5263                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5264                 }
5265         }
5266         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5267
5268         /*
5269          * Check if there is any ongoing reset in the hardware. This status can
5270          * be checked from reset_pending. If there is then, we need to wait for
5271          * hardware to complete reset.
5272          *    a. If we are able to figure out in reasonable time that hardware
5273          *       has fully resetted then, we can proceed with driver, client
5274          *       reset.
5275          *    b. else, we can come back later to check this status so re-sched
5276          *       now.
5277          */
5278         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5279         if (reset_level != HNS3_NONE_RESET) {
5280                 gettimeofday(&tv_start, NULL);
5281                 ret = hns3_reset_process(hns, reset_level);
5282                 gettimeofday(&tv, NULL);
5283                 timersub(&tv, &tv_start, &tv_delta);
5284                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5285                        tv_delta.tv_usec / USEC_PER_MSEC;
5286                 if (msec > HNS3_RESET_PROCESS_MS)
5287                         hns3_err(hw, "%d handle long time delta %" PRIx64
5288                                      " ms time=%ld.%.6ld",
5289                                  hw->reset.level, msec,
5290                                  tv.tv_sec, tv.tv_usec);
5291                 if (ret == -EAGAIN)
5292                         return;
5293         }
5294
5295         /* Check if we got any *new* reset requests to be honored */
5296         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5297         if (reset_level != HNS3_NONE_RESET)
5298                 hns3_msix_process(hns, reset_level);
5299 }
5300
5301 static const struct eth_dev_ops hns3_eth_dev_ops = {
5302         .dev_start          = hns3_dev_start,
5303         .dev_stop           = hns3_dev_stop,
5304         .dev_close          = hns3_dev_close,
5305         .promiscuous_enable = hns3_dev_promiscuous_enable,
5306         .promiscuous_disable = hns3_dev_promiscuous_disable,
5307         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5308         .allmulticast_disable = hns3_dev_allmulticast_disable,
5309         .mtu_set            = hns3_dev_mtu_set,
5310         .stats_get          = hns3_stats_get,
5311         .stats_reset        = hns3_stats_reset,
5312         .xstats_get         = hns3_dev_xstats_get,
5313         .xstats_get_names   = hns3_dev_xstats_get_names,
5314         .xstats_reset       = hns3_dev_xstats_reset,
5315         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5316         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5317         .dev_infos_get          = hns3_dev_infos_get,
5318         .fw_version_get         = hns3_fw_version_get,
5319         .rx_queue_setup         = hns3_rx_queue_setup,
5320         .tx_queue_setup         = hns3_tx_queue_setup,
5321         .rx_queue_release       = hns3_dev_rx_queue_release,
5322         .tx_queue_release       = hns3_dev_tx_queue_release,
5323         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5324         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5325         .dev_configure          = hns3_dev_configure,
5326         .flow_ctrl_get          = hns3_flow_ctrl_get,
5327         .flow_ctrl_set          = hns3_flow_ctrl_set,
5328         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5329         .mac_addr_add           = hns3_add_mac_addr,
5330         .mac_addr_remove        = hns3_remove_mac_addr,
5331         .mac_addr_set           = hns3_set_default_mac_addr,
5332         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5333         .link_update            = hns3_dev_link_update,
5334         .rss_hash_update        = hns3_dev_rss_hash_update,
5335         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5336         .reta_update            = hns3_dev_rss_reta_update,
5337         .reta_query             = hns3_dev_rss_reta_query,
5338         .filter_ctrl            = hns3_dev_filter_ctrl,
5339         .vlan_filter_set        = hns3_vlan_filter_set,
5340         .vlan_tpid_set          = hns3_vlan_tpid_set,
5341         .vlan_offload_set       = hns3_vlan_offload_set,
5342         .vlan_pvid_set          = hns3_vlan_pvid_set,
5343         .get_reg                = hns3_get_regs,
5344         .get_dcb_info           = hns3_get_dcb_info,
5345         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5346 };
5347
5348 static const struct hns3_reset_ops hns3_reset_ops = {
5349         .reset_service       = hns3_reset_service,
5350         .stop_service        = hns3_stop_service,
5351         .prepare_reset       = hns3_prepare_reset,
5352         .wait_hardware_ready = hns3_wait_hardware_ready,
5353         .reinit_dev          = hns3_reinit_dev,
5354         .restore_conf        = hns3_restore_conf,
5355         .start_service       = hns3_start_service,
5356 };
5357
5358 static int
5359 hns3_dev_init(struct rte_eth_dev *eth_dev)
5360 {
5361         struct rte_device *dev = eth_dev->device;
5362         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5363         struct hns3_adapter *hns = eth_dev->data->dev_private;
5364         struct hns3_hw *hw = &hns->hw;
5365         uint16_t device_id = pci_dev->id.device_id;
5366         uint8_t revision;
5367         int ret;
5368
5369         PMD_INIT_FUNC_TRACE();
5370
5371         /* Get PCI revision id */
5372         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5373                                   HNS3_PCI_REVISION_ID);
5374         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5375                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5376                              ret);
5377                 return -EIO;
5378         }
5379         hw->revision = revision;
5380
5381         eth_dev->process_private = (struct hns3_process_private *)
5382             rte_zmalloc_socket("hns3_filter_list",
5383                                sizeof(struct hns3_process_private),
5384                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5385         if (eth_dev->process_private == NULL) {
5386                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5387                 return -ENOMEM;
5388         }
5389         /* initialize flow filter lists */
5390         hns3_filterlist_init(eth_dev);
5391
5392         hns3_set_rxtx_function(eth_dev);
5393         eth_dev->dev_ops = &hns3_eth_dev_ops;
5394         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5395                 hns3_mp_init_secondary();
5396                 hw->secondary_cnt++;
5397                 return 0;
5398         }
5399
5400         hns3_mp_init_primary();
5401         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5402
5403         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5404             device_id == HNS3_DEV_ID_50GE_RDMA ||
5405             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5406                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5407
5408         hns->is_vf = false;
5409         hw->data = eth_dev->data;
5410
5411         /*
5412          * Set default max packet size according to the mtu
5413          * default vale in DPDK frame.
5414          */
5415         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5416
5417         ret = hns3_reset_init(hw);
5418         if (ret)
5419                 goto err_init_reset;
5420         hw->reset.ops = &hns3_reset_ops;
5421
5422         ret = hns3_init_pf(eth_dev);
5423         if (ret) {
5424                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5425                 goto err_init_pf;
5426         }
5427
5428         /* Allocate memory for storing MAC addresses */
5429         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5430                                                sizeof(struct rte_ether_addr) *
5431                                                HNS3_UC_MACADDR_NUM, 0);
5432         if (eth_dev->data->mac_addrs == NULL) {
5433                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5434                              "to store MAC addresses",
5435                              sizeof(struct rte_ether_addr) *
5436                              HNS3_UC_MACADDR_NUM);
5437                 ret = -ENOMEM;
5438                 goto err_rte_zmalloc;
5439         }
5440
5441         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5442                             &eth_dev->data->mac_addrs[0]);
5443
5444         hw->adapter_state = HNS3_NIC_INITIALIZED;
5445         /*
5446          * Pass the information to the rte_eth_dev_close() that it should also
5447          * release the private port resources.
5448          */
5449         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5450
5451         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5452                 hns3_err(hw, "Reschedule reset service after dev_init");
5453                 hns3_schedule_reset(hns);
5454         } else {
5455                 /* IMP will wait ready flag before reset */
5456                 hns3_notify_reset_ready(hw, false);
5457         }
5458
5459         hns3_info(hw, "hns3 dev initialization successful!");
5460         return 0;
5461
5462 err_rte_zmalloc:
5463         hns3_uninit_pf(eth_dev);
5464
5465 err_init_pf:
5466         rte_free(hw->reset.wait_data);
5467 err_init_reset:
5468         eth_dev->dev_ops = NULL;
5469         eth_dev->rx_pkt_burst = NULL;
5470         eth_dev->tx_pkt_burst = NULL;
5471         eth_dev->tx_pkt_prepare = NULL;
5472         rte_free(eth_dev->process_private);
5473         eth_dev->process_private = NULL;
5474         return ret;
5475 }
5476
5477 static int
5478 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5479 {
5480         struct hns3_adapter *hns = eth_dev->data->dev_private;
5481         struct hns3_hw *hw = &hns->hw;
5482
5483         PMD_INIT_FUNC_TRACE();
5484
5485         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5486                 return -EPERM;
5487
5488         eth_dev->dev_ops = NULL;
5489         eth_dev->rx_pkt_burst = NULL;
5490         eth_dev->tx_pkt_burst = NULL;
5491         eth_dev->tx_pkt_prepare = NULL;
5492         if (hw->adapter_state < HNS3_NIC_CLOSING)
5493                 hns3_dev_close(eth_dev);
5494
5495         hw->adapter_state = HNS3_NIC_REMOVED;
5496         return 0;
5497 }
5498
5499 static int
5500 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5501                    struct rte_pci_device *pci_dev)
5502 {
5503         return rte_eth_dev_pci_generic_probe(pci_dev,
5504                                              sizeof(struct hns3_adapter),
5505                                              hns3_dev_init);
5506 }
5507
5508 static int
5509 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5510 {
5511         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5512 }
5513
5514 static const struct rte_pci_id pci_id_hns3_map[] = {
5515         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5516         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5517         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5518         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5519         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5520         { .vendor_id = 0, /* sentinel */ },
5521 };
5522
5523 static struct rte_pci_driver rte_hns3_pmd = {
5524         .id_table = pci_id_hns3_map,
5525         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5526         .probe = eth_hns3_pci_probe,
5527         .remove = eth_hns3_pci_remove,
5528 };
5529
5530 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5531 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5532 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5533
5534 RTE_INIT(hns3_init_log)
5535 {
5536         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5537         if (hns3_logtype_init >= 0)
5538                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5539         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5540         if (hns3_logtype_driver >= 0)
5541                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5542 }