520a56e868c8d90780c2fe70f42dbd8aee57fb9b
[dpdk.git] / drivers / net / hns3 / hns3_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018-2021 HiSilicon Limited.
3  */
4
5 #include <rte_alarm.h>
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
8 #include <rte_pci.h>
9 #include <rte_kvargs.h>
10
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
16 #include "hns3_dcb.h"
17 #include "hns3_mp.h"
18
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
21
22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
23 #define HNS3_SERVICE_QUICK_INTERVAL     10
24 #define HNS3_INVALID_PVID               0xFFFF
25
26 #define HNS3_FILTER_TYPE_VF             0
27 #define HNS3_FILTER_TYPE_PORT           1
28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
37
38 /* Reset related Registers */
39 #define HNS3_GLOBAL_RESET_BIT           0
40 #define HNS3_CORE_RESET_BIT             1
41 #define HNS3_IMP_RESET_BIT              2
42 #define HNS3_FUN_RST_ING_B              0
43
44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
48
49 #define HNS3_RESET_WAIT_MS      100
50 #define HNS3_RESET_WAIT_CNT     200
51
52 /* FEC mode order defined in HNS3 hardware */
53 #define HNS3_HW_FEC_MODE_NOFEC  0
54 #define HNS3_HW_FEC_MODE_BASER  1
55 #define HNS3_HW_FEC_MODE_RS     2
56
57 enum hns3_evt_cause {
58         HNS3_VECTOR0_EVENT_RST,
59         HNS3_VECTOR0_EVENT_MBX,
60         HNS3_VECTOR0_EVENT_ERR,
61         HNS3_VECTOR0_EVENT_PTP,
62         HNS3_VECTOR0_EVENT_OTHER,
63 };
64
65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
69
70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
74
75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
78
79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
83
84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
87
88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
91 };
92
93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
94                                                  uint64_t *levels);
95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
97                                     int on);
98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
99 static bool hns3_update_link_status(struct hns3_hw *hw);
100
101 static int hns3_add_mc_addr(struct hns3_hw *hw,
102                             struct rte_ether_addr *mac_addr);
103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
104                             struct rte_ether_addr *mac_addr);
105 static int hns3_restore_fec(struct hns3_hw *hw);
106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
107 static int hns3_do_stop(struct hns3_adapter *hns);
108
109 void hns3_ether_format_addr(char *buf, uint16_t size,
110                             const struct rte_ether_addr *ether_addr)
111 {
112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
113                 ether_addr->addr_bytes[0],
114                 ether_addr->addr_bytes[4],
115                 ether_addr->addr_bytes[5]);
116 }
117
118 static void
119 hns3_pf_disable_irq0(struct hns3_hw *hw)
120 {
121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
122 }
123
124 static void
125 hns3_pf_enable_irq0(struct hns3_hw *hw)
126 {
127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
128 }
129
130 static enum hns3_evt_cause
131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
132                           uint32_t *vec_val)
133 {
134         struct hns3_hw *hw = &hns->hw;
135
136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
139         if (!is_delay) {
140                 hw->reset.stats.imp_cnt++;
141                 hns3_warn(hw, "IMP reset detected, clear reset status");
142         } else {
143                 hns3_schedule_delayed_reset(hns);
144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
145         }
146
147         return HNS3_VECTOR0_EVENT_RST;
148 }
149
150 static enum hns3_evt_cause
151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
152                              uint32_t *vec_val)
153 {
154         struct hns3_hw *hw = &hns->hw;
155
156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
159         if (!is_delay) {
160                 hw->reset.stats.global_cnt++;
161                 hns3_warn(hw, "Global reset detected, clear reset status");
162         } else {
163                 hns3_schedule_delayed_reset(hns);
164                 hns3_warn(hw,
165                           "Global reset detected, don't clear reset status");
166         }
167
168         return HNS3_VECTOR0_EVENT_RST;
169 }
170
171 static enum hns3_evt_cause
172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
173 {
174         struct hns3_hw *hw = &hns->hw;
175         uint32_t vector0_int_stats;
176         uint32_t cmdq_src_val;
177         uint32_t hw_err_src_reg;
178         uint32_t val;
179         enum hns3_evt_cause ret;
180         bool is_delay;
181
182         /* fetch the events from their corresponding regs */
183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
186
187         is_delay = clearval == NULL ? true : false;
188         /*
189          * Assumption: If by any chance reset and mailbox events are reported
190          * together then we will only process reset event and defer the
191          * processing of the mailbox events. Since, we would have not cleared
192          * RX CMDQ event this time we would receive again another interrupt
193          * from H/W just for the mailbox.
194          */
195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
197                 goto out;
198         }
199
200         /* Global reset */
201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
203                 goto out;
204         }
205
206         /* Check for vector0 1588 event source */
207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
209                 ret = HNS3_VECTOR0_EVENT_PTP;
210                 goto out;
211         }
212
213         /* check for vector0 msix event source */
214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
216                 val = vector0_int_stats | hw_err_src_reg;
217                 ret = HNS3_VECTOR0_EVENT_ERR;
218                 goto out;
219         }
220
221         /* check for vector0 mailbox(=CMDQ RX) event source */
222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
224                 val = cmdq_src_val;
225                 ret = HNS3_VECTOR0_EVENT_MBX;
226                 goto out;
227         }
228
229         val = vector0_int_stats;
230         ret = HNS3_VECTOR0_EVENT_OTHER;
231 out:
232
233         if (clearval)
234                 *clearval = val;
235         return ret;
236 }
237
238 static bool
239 hns3_is_1588_event_type(uint32_t event_type)
240 {
241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
242 }
243
244 static void
245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
246 {
247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
248             hns3_is_1588_event_type(event_type))
249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
252 }
253
254 static void
255 hns3_clear_all_event_cause(struct hns3_hw *hw)
256 {
257         uint32_t vector0_int_stats;
258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
259
260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
261                 hns3_warn(hw, "Probe during IMP reset interrupt");
262
263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
264                 hns3_warn(hw, "Probe during Global reset interrupt");
265
266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
272                                 BIT(HNS3_VECTOR0_1588_INT_B));
273 }
274
275 static void
276 hns3_handle_mac_tnl(struct hns3_hw *hw)
277 {
278         struct hns3_cmd_desc desc;
279         uint32_t status;
280         int ret;
281
282         /* query and clear mac tnl interruptions */
283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
284         ret = hns3_cmd_send(hw, &desc, 1);
285         if (ret) {
286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
287                 return;
288         }
289
290         status = rte_le_to_cpu_32(desc.data[0]);
291         if (status) {
292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
294                                           false);
295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
296                 ret = hns3_cmd_send(hw, &desc, 1);
297                 if (ret)
298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
299                                  ret);
300         }
301 }
302
303 static void
304 hns3_interrupt_handler(void *param)
305 {
306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
307         struct hns3_adapter *hns = dev->data->dev_private;
308         struct hns3_hw *hw = &hns->hw;
309         enum hns3_evt_cause event_cause;
310         uint32_t clearval = 0;
311         uint32_t vector0_int;
312         uint32_t ras_int;
313         uint32_t cmdq_int;
314
315         /* Disable interrupt */
316         hns3_pf_disable_irq0(hw);
317
318         event_cause = hns3_check_event_cause(hns, &clearval);
319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
322         /* vector 0 interrupt is shared with reset and mailbox source events. */
323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
326                           vector0_int, ras_int, cmdq_int);
327                 hns3_handle_msix_error(hns, &hw->reset.request);
328                 hns3_handle_ras_error(hns, &hw->reset.request);
329                 hns3_handle_mac_tnl(hw);
330                 hns3_schedule_reset(hns);
331         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
332                 hns3_warn(hw, "received reset interrupt");
333                 hns3_schedule_reset(hns);
334         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
335                 hns3_dev_handle_mbx_msg(hw);
336         } else {
337                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
338                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
339                           vector0_int, ras_int, cmdq_int);
340         }
341
342         hns3_clear_event_cause(hw, event_cause, clearval);
343         /* Enable interrupt if it is not cause by reset */
344         hns3_pf_enable_irq0(hw);
345 }
346
347 static int
348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
349 {
350 #define HNS3_VLAN_ID_OFFSET_STEP        160
351 #define HNS3_VLAN_BYTE_SIZE             8
352         struct hns3_vlan_filter_pf_cfg_cmd *req;
353         struct hns3_hw *hw = &hns->hw;
354         uint8_t vlan_offset_byte_val;
355         struct hns3_cmd_desc desc;
356         uint8_t vlan_offset_byte;
357         uint8_t vlan_offset_base;
358         int ret;
359
360         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
361
362         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
363         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
364                            HNS3_VLAN_BYTE_SIZE;
365         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
366
367         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
368         req->vlan_offset = vlan_offset_base;
369         req->vlan_cfg = on ? 0 : 1;
370         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
371
372         ret = hns3_cmd_send(hw, &desc, 1);
373         if (ret)
374                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
375                          vlan_id, ret);
376
377         return ret;
378 }
379
380 static void
381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
382 {
383         struct hns3_user_vlan_table *vlan_entry;
384         struct hns3_pf *pf = &hns->pf;
385
386         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
387                 if (vlan_entry->vlan_id == vlan_id) {
388                         if (vlan_entry->hd_tbl_status)
389                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
390                         LIST_REMOVE(vlan_entry, next);
391                         rte_free(vlan_entry);
392                         break;
393                 }
394         }
395 }
396
397 static void
398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
399                         bool writen_to_tbl)
400 {
401         struct hns3_user_vlan_table *vlan_entry;
402         struct hns3_hw *hw = &hns->hw;
403         struct hns3_pf *pf = &hns->pf;
404
405         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
406                 if (vlan_entry->vlan_id == vlan_id)
407                         return;
408         }
409
410         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
411         if (vlan_entry == NULL) {
412                 hns3_err(hw, "Failed to malloc hns3 vlan table");
413                 return;
414         }
415
416         vlan_entry->hd_tbl_status = writen_to_tbl;
417         vlan_entry->vlan_id = vlan_id;
418
419         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
420 }
421
422 static int
423 hns3_restore_vlan_table(struct hns3_adapter *hns)
424 {
425         struct hns3_user_vlan_table *vlan_entry;
426         struct hns3_hw *hw = &hns->hw;
427         struct hns3_pf *pf = &hns->pf;
428         uint16_t vlan_id;
429         int ret = 0;
430
431         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
432                 return hns3_vlan_pvid_configure(hns,
433                                                 hw->port_base_vlan_cfg.pvid, 1);
434
435         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
436                 if (vlan_entry->hd_tbl_status) {
437                         vlan_id = vlan_entry->vlan_id;
438                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
439                         if (ret)
440                                 break;
441                 }
442         }
443
444         return ret;
445 }
446
447 static int
448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
449 {
450         struct hns3_hw *hw = &hns->hw;
451         bool writen_to_tbl = false;
452         int ret = 0;
453
454         /*
455          * When vlan filter is enabled, hardware regards packets without vlan
456          * as packets with vlan 0. So, to receive packets without vlan, vlan id
457          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
458          */
459         if (on == 0 && vlan_id == 0)
460                 return 0;
461
462         /*
463          * When port base vlan enabled, we use port base vlan as the vlan
464          * filter condition. In this case, we don't update vlan filter table
465          * when user add new vlan or remove exist vlan, just update the
466          * vlan list. The vlan id in vlan list will be writen in vlan filter
467          * table until port base vlan disabled
468          */
469         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
470                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
471                 writen_to_tbl = true;
472         }
473
474         if (ret == 0) {
475                 if (on)
476                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
477                 else
478                         hns3_rm_dev_vlan_table(hns, vlan_id);
479         }
480         return ret;
481 }
482
483 static int
484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
485 {
486         struct hns3_adapter *hns = dev->data->dev_private;
487         struct hns3_hw *hw = &hns->hw;
488         int ret;
489
490         rte_spinlock_lock(&hw->lock);
491         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
492         rte_spinlock_unlock(&hw->lock);
493         return ret;
494 }
495
496 static int
497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
498                          uint16_t tpid)
499 {
500         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
501         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
502         struct hns3_hw *hw = &hns->hw;
503         struct hns3_cmd_desc desc;
504         int ret;
505
506         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
507              vlan_type != ETH_VLAN_TYPE_OUTER)) {
508                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
509                 return -EINVAL;
510         }
511
512         if (tpid != RTE_ETHER_TYPE_VLAN) {
513                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
514                 return -EINVAL;
515         }
516
517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
518         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
519
520         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
523         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
524                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
525                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
526                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
527                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
528         }
529
530         ret = hns3_cmd_send(hw, &desc, 1);
531         if (ret) {
532                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
533                          ret);
534                 return ret;
535         }
536
537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
538
539         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
540         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
541         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
542
543         ret = hns3_cmd_send(hw, &desc, 1);
544         if (ret)
545                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
546                          ret);
547         return ret;
548 }
549
550 static int
551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
552                    uint16_t tpid)
553 {
554         struct hns3_adapter *hns = dev->data->dev_private;
555         struct hns3_hw *hw = &hns->hw;
556         int ret;
557
558         rte_spinlock_lock(&hw->lock);
559         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
560         rte_spinlock_unlock(&hw->lock);
561         return ret;
562 }
563
564 static int
565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
566                              struct hns3_rx_vtag_cfg *vcfg)
567 {
568         struct hns3_vport_vtag_rx_cfg_cmd *req;
569         struct hns3_hw *hw = &hns->hw;
570         struct hns3_cmd_desc desc;
571         uint16_t vport_id;
572         uint8_t bitmap;
573         int ret;
574
575         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
576
577         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
579                      vcfg->strip_tag1_en ? 1 : 0);
580         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
581                      vcfg->strip_tag2_en ? 1 : 0);
582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
583                      vcfg->vlan1_vlan_prionly ? 1 : 0);
584         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
585                      vcfg->vlan2_vlan_prionly ? 1 : 0);
586
587         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
589                      vcfg->strip_tag1_discard_en ? 1 : 0);
590         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
591                      vcfg->strip_tag2_discard_en ? 1 : 0);
592         /*
593          * In current version VF is not supported when PF is driven by DPDK
594          * driver, just need to configure parameters for PF vport.
595          */
596         vport_id = HNS3_PF_FUNC_ID;
597         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
598         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
599         req->vf_bitmap[req->vf_offset] = bitmap;
600
601         ret = hns3_cmd_send(hw, &desc, 1);
602         if (ret)
603                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
604         return ret;
605 }
606
607 static void
608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
609                            struct hns3_rx_vtag_cfg *vcfg)
610 {
611         struct hns3_pf *pf = &hns->pf;
612         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
613 }
614
615 static void
616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
617                            struct hns3_tx_vtag_cfg *vcfg)
618 {
619         struct hns3_pf *pf = &hns->pf;
620         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
621 }
622
623 static int
624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
625 {
626         struct hns3_rx_vtag_cfg rxvlan_cfg;
627         struct hns3_hw *hw = &hns->hw;
628         int ret;
629
630         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
631                 rxvlan_cfg.strip_tag1_en = false;
632                 rxvlan_cfg.strip_tag2_en = enable;
633                 rxvlan_cfg.strip_tag2_discard_en = false;
634         } else {
635                 rxvlan_cfg.strip_tag1_en = enable;
636                 rxvlan_cfg.strip_tag2_en = true;
637                 rxvlan_cfg.strip_tag2_discard_en = true;
638         }
639
640         rxvlan_cfg.strip_tag1_discard_en = false;
641         rxvlan_cfg.vlan1_vlan_prionly = false;
642         rxvlan_cfg.vlan2_vlan_prionly = false;
643         rxvlan_cfg.rx_vlan_offload_en = enable;
644
645         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
646         if (ret) {
647                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
648                 return ret;
649         }
650
651         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
652
653         return ret;
654 }
655
656 static int
657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
658                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
659 {
660         struct hns3_vlan_filter_ctrl_cmd *req;
661         struct hns3_cmd_desc desc;
662         int ret;
663
664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
665
666         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
667         req->vlan_type = vlan_type;
668         req->vlan_fe = filter_en ? fe_type : 0;
669         req->vf_id = vf_id;
670
671         ret = hns3_cmd_send(hw, &desc, 1);
672         if (ret)
673                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
674
675         return ret;
676 }
677
678 static int
679 hns3_vlan_filter_init(struct hns3_adapter *hns)
680 {
681         struct hns3_hw *hw = &hns->hw;
682         int ret;
683
684         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
685                                         HNS3_FILTER_FE_EGRESS, false,
686                                         HNS3_PF_FUNC_ID);
687         if (ret) {
688                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
689                 return ret;
690         }
691
692         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
693                                         HNS3_FILTER_FE_INGRESS, false,
694                                         HNS3_PF_FUNC_ID);
695         if (ret)
696                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
697
698         return ret;
699 }
700
701 static int
702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
703 {
704         struct hns3_hw *hw = &hns->hw;
705         int ret;
706
707         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
708                                         HNS3_FILTER_FE_INGRESS, enable,
709                                         HNS3_PF_FUNC_ID);
710         if (ret)
711                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
712                          enable ? "enable" : "disable", ret);
713
714         return ret;
715 }
716
717 static int
718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
719 {
720         struct hns3_adapter *hns = dev->data->dev_private;
721         struct hns3_hw *hw = &hns->hw;
722         struct rte_eth_rxmode *rxmode;
723         unsigned int tmp_mask;
724         bool enable;
725         int ret = 0;
726
727         rte_spinlock_lock(&hw->lock);
728         rxmode = &dev->data->dev_conf.rxmode;
729         tmp_mask = (unsigned int)mask;
730         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
731                 /* ignore vlan filter configuration during promiscuous mode */
732                 if (!dev->data->promiscuous) {
733                         /* Enable or disable VLAN filter */
734                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
735                                  true : false;
736
737                         ret = hns3_enable_vlan_filter(hns, enable);
738                         if (ret) {
739                                 rte_spinlock_unlock(&hw->lock);
740                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
741                                          enable ? "enable" : "disable", ret);
742                                 return ret;
743                         }
744                 }
745         }
746
747         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
748                 /* Enable or disable VLAN stripping */
749                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
750                     true : false;
751
752                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
753                 if (ret) {
754                         rte_spinlock_unlock(&hw->lock);
755                         hns3_err(hw, "failed to %s rx strip, ret = %d",
756                                  enable ? "enable" : "disable", ret);
757                         return ret;
758                 }
759         }
760
761         rte_spinlock_unlock(&hw->lock);
762
763         return ret;
764 }
765
766 static int
767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
768                              struct hns3_tx_vtag_cfg *vcfg)
769 {
770         struct hns3_vport_vtag_tx_cfg_cmd *req;
771         struct hns3_cmd_desc desc;
772         struct hns3_hw *hw = &hns->hw;
773         uint16_t vport_id;
774         uint8_t bitmap;
775         int ret;
776
777         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
778
779         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
780         req->def_vlan_tag1 = vcfg->default_tag1;
781         req->def_vlan_tag2 = vcfg->default_tag2;
782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
783                      vcfg->accept_tag1 ? 1 : 0);
784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
785                      vcfg->accept_untag1 ? 1 : 0);
786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
787                      vcfg->accept_tag2 ? 1 : 0);
788         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
789                      vcfg->accept_untag2 ? 1 : 0);
790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
791                      vcfg->insert_tag1_en ? 1 : 0);
792         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
793                      vcfg->insert_tag2_en ? 1 : 0);
794         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
795
796         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
797         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
798                      vcfg->tag_shift_mode_en ? 1 : 0);
799
800         /*
801          * In current version VF is not supported when PF is driven by DPDK
802          * driver, just need to configure parameters for PF vport.
803          */
804         vport_id = HNS3_PF_FUNC_ID;
805         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
806         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
807         req->vf_bitmap[req->vf_offset] = bitmap;
808
809         ret = hns3_cmd_send(hw, &desc, 1);
810         if (ret)
811                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
812
813         return ret;
814 }
815
816 static int
817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
818                      uint16_t pvid)
819 {
820         struct hns3_hw *hw = &hns->hw;
821         struct hns3_tx_vtag_cfg txvlan_cfg;
822         int ret;
823
824         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
825                 txvlan_cfg.accept_tag1 = true;
826                 txvlan_cfg.insert_tag1_en = false;
827                 txvlan_cfg.default_tag1 = 0;
828         } else {
829                 txvlan_cfg.accept_tag1 =
830                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
831                 txvlan_cfg.insert_tag1_en = true;
832                 txvlan_cfg.default_tag1 = pvid;
833         }
834
835         txvlan_cfg.accept_untag1 = true;
836         txvlan_cfg.accept_tag2 = true;
837         txvlan_cfg.accept_untag2 = true;
838         txvlan_cfg.insert_tag2_en = false;
839         txvlan_cfg.default_tag2 = 0;
840         txvlan_cfg.tag_shift_mode_en = true;
841
842         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
843         if (ret) {
844                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
845                          ret);
846                 return ret;
847         }
848
849         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
850         return ret;
851 }
852
853
854 static void
855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
856 {
857         struct hns3_user_vlan_table *vlan_entry;
858         struct hns3_pf *pf = &hns->pf;
859
860         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
861                 if (vlan_entry->hd_tbl_status) {
862                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
863                         vlan_entry->hd_tbl_status = false;
864                 }
865         }
866
867         if (is_del_list) {
868                 vlan_entry = LIST_FIRST(&pf->vlan_list);
869                 while (vlan_entry) {
870                         LIST_REMOVE(vlan_entry, next);
871                         rte_free(vlan_entry);
872                         vlan_entry = LIST_FIRST(&pf->vlan_list);
873                 }
874         }
875 }
876
877 static void
878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
879 {
880         struct hns3_user_vlan_table *vlan_entry;
881         struct hns3_pf *pf = &hns->pf;
882
883         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
884                 if (!vlan_entry->hd_tbl_status) {
885                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
886                         vlan_entry->hd_tbl_status = true;
887                 }
888         }
889 }
890
891 static void
892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
893 {
894         struct hns3_hw *hw = &hns->hw;
895         int ret;
896
897         hns3_rm_all_vlan_table(hns, true);
898         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
899                 ret = hns3_set_port_vlan_filter(hns,
900                                                 hw->port_base_vlan_cfg.pvid, 0);
901                 if (ret) {
902                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
903                                  ret);
904                         return;
905                 }
906         }
907 }
908
909 static int
910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
911                         uint16_t port_base_vlan_state, uint16_t new_pvid)
912 {
913         struct hns3_hw *hw = &hns->hw;
914         uint16_t old_pvid;
915         int ret;
916
917         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
918                 old_pvid = hw->port_base_vlan_cfg.pvid;
919                 if (old_pvid != HNS3_INVALID_PVID) {
920                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
921                         if (ret) {
922                                 hns3_err(hw, "failed to remove old pvid %u, "
923                                                 "ret = %d", old_pvid, ret);
924                                 return ret;
925                         }
926                 }
927
928                 hns3_rm_all_vlan_table(hns, false);
929                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
930                 if (ret) {
931                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
932                                         new_pvid, ret);
933                         return ret;
934                 }
935         } else {
936                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
937                 if (ret) {
938                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
939                                         new_pvid, ret);
940                         return ret;
941                 }
942
943                 hns3_add_all_vlan_table(hns);
944         }
945         return 0;
946 }
947
948 static int
949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
950 {
951         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
952         struct hns3_rx_vtag_cfg rx_vlan_cfg;
953         bool rx_strip_en;
954         int ret;
955
956         rx_strip_en = old_cfg->rx_vlan_offload_en;
957         if (on) {
958                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
959                 rx_vlan_cfg.strip_tag2_en = true;
960                 rx_vlan_cfg.strip_tag2_discard_en = true;
961         } else {
962                 rx_vlan_cfg.strip_tag1_en = false;
963                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
964                 rx_vlan_cfg.strip_tag2_discard_en = false;
965         }
966         rx_vlan_cfg.strip_tag1_discard_en = false;
967         rx_vlan_cfg.vlan1_vlan_prionly = false;
968         rx_vlan_cfg.vlan2_vlan_prionly = false;
969         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
970
971         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
972         if (ret)
973                 return ret;
974
975         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
976         return ret;
977 }
978
979 static int
980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
981 {
982         struct hns3_hw *hw = &hns->hw;
983         uint16_t port_base_vlan_state;
984         int ret, err;
985
986         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
987                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
988                         hns3_warn(hw, "Invalid operation! As current pvid set "
989                                   "is %u, disable pvid %u is invalid",
990                                   hw->port_base_vlan_cfg.pvid, pvid);
991                 return 0;
992         }
993
994         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
995                                     HNS3_PORT_BASE_VLAN_DISABLE;
996         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
997         if (ret) {
998                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
999                          ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_en_pvid_strip(hns, on);
1004         if (ret) {
1005                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006                          "ret = %d", ret);
1007                 goto pvid_vlan_strip_fail;
1008         }
1009
1010         if (pvid == HNS3_INVALID_PVID)
1011                 goto out;
1012         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013         if (ret) {
1014                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015                          ret);
1016                 goto vlan_filter_set_fail;
1017         }
1018
1019 out:
1020         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022         return ret;
1023
1024 vlan_filter_set_fail:
1025         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1026                                         HNS3_PORT_BASE_VLAN_ENABLE);
1027         if (err)
1028                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1029
1030 pvid_vlan_strip_fail:
1031         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1032                                         hw->port_base_vlan_cfg.pvid);
1033         if (err)
1034                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1041 {
1042         struct hns3_adapter *hns = dev->data->dev_private;
1043         struct hns3_hw *hw = &hns->hw;
1044         bool pvid_en_state_change;
1045         uint16_t pvid_state;
1046         int ret;
1047
1048         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1049                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1050                          RTE_ETHER_MAX_VLAN_ID);
1051                 return -EINVAL;
1052         }
1053
1054         /*
1055          * If PVID configuration state change, should refresh the PVID
1056          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1057          */
1058         pvid_state = hw->port_base_vlan_cfg.state;
1059         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1060             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1061                 pvid_en_state_change = false;
1062         else
1063                 pvid_en_state_change = true;
1064
1065         rte_spinlock_lock(&hw->lock);
1066         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1067         rte_spinlock_unlock(&hw->lock);
1068         if (ret)
1069                 return ret;
1070         /*
1071          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1072          * need be processed by PMD driver.
1073          */
1074         if (pvid_en_state_change &&
1075             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1076                 hns3_update_all_queues_pvid_proc_en(hw);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_default_vlan_config(struct hns3_adapter *hns)
1083 {
1084         struct hns3_hw *hw = &hns->hw;
1085         int ret;
1086
1087         /*
1088          * When vlan filter is enabled, hardware regards packets without vlan
1089          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1090          * table, packets without vlan won't be received. So, add vlan 0 as
1091          * the default vlan.
1092          */
1093         ret = hns3_vlan_filter_configure(hns, 0, 1);
1094         if (ret)
1095                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1096         return ret;
1097 }
1098
1099 static int
1100 hns3_init_vlan_config(struct hns3_adapter *hns)
1101 {
1102         struct hns3_hw *hw = &hns->hw;
1103         int ret;
1104
1105         /*
1106          * This function can be called in the initialization and reset process,
1107          * when in reset process, it means that hardware had been reseted
1108          * successfully and we need to restore the hardware configuration to
1109          * ensure that the hardware configuration remains unchanged before and
1110          * after reset.
1111          */
1112         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1113                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1114                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115         }
1116
1117         ret = hns3_vlan_filter_init(hns);
1118         if (ret) {
1119                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120                 return ret;
1121         }
1122
1123         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1124                                        RTE_ETHER_TYPE_VLAN);
1125         if (ret) {
1126                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1127                 return ret;
1128         }
1129
1130         /*
1131          * When in the reinit dev stage of the reset process, the following
1132          * vlan-related configurations may differ from those at initialization,
1133          * we will restore configurations to hardware in hns3_restore_vlan_table
1134          * and hns3_restore_vlan_conf later.
1135          */
1136         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1137                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1138                 if (ret) {
1139                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140                         return ret;
1141                 }
1142
1143                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1144                 if (ret) {
1145                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1146                                  ret);
1147                         return ret;
1148                 }
1149         }
1150
1151         return hns3_default_vlan_config(hns);
1152 }
1153
1154 static int
1155 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1156 {
1157         struct hns3_pf *pf = &hns->pf;
1158         struct hns3_hw *hw = &hns->hw;
1159         uint64_t offloads;
1160         bool enable;
1161         int ret;
1162
1163         if (!hw->data->promiscuous) {
1164                 /* restore vlan filter states */
1165                 offloads = hw->data->dev_conf.rxmode.offloads;
1166                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1167                 ret = hns3_enable_vlan_filter(hns, enable);
1168                 if (ret) {
1169                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1170                                  "ret = %d", ret);
1171                         return ret;
1172                 }
1173         }
1174
1175         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1176         if (ret) {
1177                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178                 return ret;
1179         }
1180
1181         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1182         if (ret)
1183                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1184
1185         return ret;
1186 }
1187
1188 static int
1189 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1190 {
1191         struct hns3_adapter *hns = dev->data->dev_private;
1192         struct rte_eth_dev_data *data = dev->data;
1193         struct rte_eth_txmode *txmode;
1194         struct hns3_hw *hw = &hns->hw;
1195         int mask;
1196         int ret;
1197
1198         txmode = &data->dev_conf.txmode;
1199         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1200                 hns3_warn(hw,
1201                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1202                           "configuration is not supported! Ignore these two "
1203                           "parameters: hw_vlan_reject_tagged(%u), "
1204                           "hw_vlan_reject_untagged(%u)",
1205                           txmode->hw_vlan_reject_tagged,
1206                           txmode->hw_vlan_reject_untagged);
1207
1208         /* Apply vlan offload setting */
1209         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1210         ret = hns3_vlan_offload_set(dev, mask);
1211         if (ret) {
1212                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1213                          ret);
1214                 return ret;
1215         }
1216
1217         /*
1218          * If pvid config is not set in rte_eth_conf, driver needn't to set
1219          * VLAN pvid related configuration to hardware.
1220          */
1221         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222                 return 0;
1223
1224         /* Apply pvid setting */
1225         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1226                                  txmode->hw_vlan_insert_pvid);
1227         if (ret)
1228                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1229                          txmode->pvid, ret);
1230
1231         return ret;
1232 }
1233
1234 static int
1235 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1236                 unsigned int tso_mss_max)
1237 {
1238         struct hns3_cfg_tso_status_cmd *req;
1239         struct hns3_cmd_desc desc;
1240         uint16_t tso_mss;
1241
1242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1243
1244         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245
1246         tso_mss = 0;
1247         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1248                        tso_mss_min);
1249         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250
1251         tso_mss = 0;
1252         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1253                        tso_mss_max);
1254         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1255
1256         return hns3_cmd_send(hw, &desc, 1);
1257 }
1258
1259 static int
1260 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1261                    uint16_t *allocated_size, bool is_alloc)
1262 {
1263         struct hns3_umv_spc_alc_cmd *req;
1264         struct hns3_cmd_desc desc;
1265         int ret;
1266
1267         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1269         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1270         req->space_size = rte_cpu_to_le_32(space_size);
1271
1272         ret = hns3_cmd_send(hw, &desc, 1);
1273         if (ret) {
1274                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1275                              is_alloc ? "allocate" : "free", ret);
1276                 return ret;
1277         }
1278
1279         if (is_alloc && allocated_size)
1280                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 hns3_init_umv_space(struct hns3_hw *hw)
1287 {
1288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1289         struct hns3_pf *pf = &hns->pf;
1290         uint16_t allocated_size = 0;
1291         int ret;
1292
1293         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1294                                  true);
1295         if (ret)
1296                 return ret;
1297
1298         if (allocated_size < pf->wanted_umv_size)
1299                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1300                              pf->wanted_umv_size, allocated_size);
1301
1302         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1303                                                 pf->wanted_umv_size;
1304         pf->used_umv_size = 0;
1305         return 0;
1306 }
1307
1308 static int
1309 hns3_uninit_umv_space(struct hns3_hw *hw)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313         int ret;
1314
1315         if (pf->max_umv_size == 0)
1316                 return 0;
1317
1318         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319         if (ret)
1320                 return ret;
1321
1322         pf->max_umv_size = 0;
1323
1324         return 0;
1325 }
1326
1327 static bool
1328 hns3_is_umv_space_full(struct hns3_hw *hw)
1329 {
1330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331         struct hns3_pf *pf = &hns->pf;
1332         bool is_full;
1333
1334         is_full = (pf->used_umv_size >= pf->max_umv_size);
1335
1336         return is_full;
1337 }
1338
1339 static void
1340 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1341 {
1342         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1343         struct hns3_pf *pf = &hns->pf;
1344
1345         if (is_free) {
1346                 if (pf->used_umv_size > 0)
1347                         pf->used_umv_size--;
1348         } else
1349                 pf->used_umv_size++;
1350 }
1351
1352 static void
1353 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1354                       const uint8_t *addr, bool is_mc)
1355 {
1356         const unsigned char *mac_addr = addr;
1357         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1358                             ((uint32_t)mac_addr[2] << 16) |
1359                             ((uint32_t)mac_addr[1] << 8) |
1360                             (uint32_t)mac_addr[0];
1361         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1362
1363         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1364         if (is_mc) {
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1366                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1367                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368         }
1369
1370         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1371         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 }
1373
1374 static int
1375 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1376                              uint8_t resp_code,
1377                              enum hns3_mac_vlan_tbl_opcode op)
1378 {
1379         if (cmdq_resp) {
1380                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1381                          cmdq_resp);
1382                 return -EIO;
1383         }
1384
1385         if (op == HNS3_MAC_VLAN_ADD) {
1386                 if (resp_code == 0 || resp_code == 1) {
1387                         return 0;
1388                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1389                         hns3_err(hw, "add mac addr failed for uc_overflow");
1390                         return -ENOSPC;
1391                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1392                         hns3_err(hw, "add mac addr failed for mc_overflow");
1393                         return -ENOSPC;
1394                 }
1395
1396                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397                          resp_code);
1398                 return -EIO;
1399         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1400                 if (resp_code == 0) {
1401                         return 0;
1402                 } else if (resp_code == 1) {
1403                         hns3_dbg(hw, "remove mac addr failed for miss");
1404                         return -ENOENT;
1405                 }
1406
1407                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408                          resp_code);
1409                 return -EIO;
1410         } else if (op == HNS3_MAC_VLAN_LKUP) {
1411                 if (resp_code == 0) {
1412                         return 0;
1413                 } else if (resp_code == 1) {
1414                         hns3_dbg(hw, "lookup mac addr failed for miss");
1415                         return -ENOENT;
1416                 }
1417
1418                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1419                          resp_code);
1420                 return -EIO;
1421         }
1422
1423         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1424                  op);
1425
1426         return -EINVAL;
1427 }
1428
1429 static int
1430 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1431                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1432                          struct hns3_cmd_desc *desc, bool is_mc)
1433 {
1434         uint8_t resp_code;
1435         uint16_t retval;
1436         int ret;
1437
1438         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1439         if (is_mc) {
1440                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1441                 memcpy(desc[0].data, req,
1442                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1443                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1444                                           true);
1445                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1446                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1449         } else {
1450                 memcpy(desc[0].data, req,
1451                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1452                 ret = hns3_cmd_send(hw, desc, 1);
1453         }
1454         if (ret) {
1455                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456                          ret);
1457                 return ret;
1458         }
1459         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1460         retval = rte_le_to_cpu_16(desc[0].retval);
1461
1462         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1463                                             HNS3_MAC_VLAN_LKUP);
1464 }
1465
1466 static int
1467 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1468                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1469                       struct hns3_cmd_desc *mc_desc)
1470 {
1471         uint8_t resp_code;
1472         uint16_t retval;
1473         int cfg_status;
1474         int ret;
1475
1476         if (mc_desc == NULL) {
1477                 struct hns3_cmd_desc desc;
1478
1479                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc.data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, &desc, 1);
1483                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc.retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1490                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1492                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1493                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1494                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1495                 memcpy(mc_desc[0].data, req,
1496                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1497                 mc_desc[0].retval = 0;
1498                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1499                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1500                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1501
1502                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1503                                                           HNS3_MAC_VLAN_ADD);
1504         }
1505
1506         if (ret) {
1507                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510
1511         return cfg_status;
1512 }
1513
1514 static int
1515 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1516                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1517 {
1518         struct hns3_cmd_desc desc;
1519         uint8_t resp_code;
1520         uint16_t retval;
1521         int ret;
1522
1523         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1524
1525         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1526
1527         ret = hns3_cmd_send(hw, &desc, 1);
1528         if (ret) {
1529                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1530                 return ret;
1531         }
1532         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1533         retval = rte_le_to_cpu_16(desc.retval);
1534
1535         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1536                                             HNS3_MAC_VLAN_REMOVE);
1537 }
1538
1539 static int
1540 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1541 {
1542         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1543         struct hns3_mac_vlan_tbl_entry_cmd req;
1544         struct hns3_pf *pf = &hns->pf;
1545         struct hns3_cmd_desc desc[3];
1546         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1547         uint16_t egress_port = 0;
1548         uint8_t vf_id;
1549         int ret;
1550
1551         /* check if mac addr is valid */
1552         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1553                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                       mac_addr);
1555                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1556                          mac_str);
1557                 return -EINVAL;
1558         }
1559
1560         memset(&req, 0, sizeof(req));
1561
1562         /*
1563          * In current version VF is not supported when PF is driven by DPDK
1564          * driver, just need to configure parameters for PF vport.
1565          */
1566         vf_id = HNS3_PF_FUNC_ID;
1567         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1568                        HNS3_MAC_EPORT_VFID_S, vf_id);
1569
1570         req.egress_port = rte_cpu_to_le_16(egress_port);
1571
1572         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1573
1574         /*
1575          * Lookup the mac address in the mac_vlan table, and add
1576          * it if the entry is inexistent. Repeated unicast entry
1577          * is not allowed in the mac vlan table.
1578          */
1579         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1580         if (ret == -ENOENT) {
1581                 if (!hns3_is_umv_space_full(hw)) {
1582                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1583                         if (!ret)
1584                                 hns3_update_umv_space(hw, false);
1585                         return ret;
1586                 }
1587
1588                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1589
1590                 return -ENOSPC;
1591         }
1592
1593         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1594
1595         /* check if we just hit the duplicate */
1596         if (ret == 0) {
1597                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598                 return 0;
1599         }
1600
1601         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1602                  mac_str);
1603
1604         return ret;
1605 }
1606
1607 static int
1608 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 {
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         struct rte_ether_addr *addr;
1612         int ret;
1613         int i;
1614
1615         for (i = 0; i < hw->mc_addrs_num; i++) {
1616                 addr = &hw->mc_addrs[i];
1617                 /* Check if there are duplicate addresses */
1618                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1619                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                               addr);
1621                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1622                                  "(%s) is added by the set_mc_mac_addr_list "
1623                                  "API", mac_str);
1624                         return -EINVAL;
1625                 }
1626         }
1627
1628         ret = hns3_add_mc_addr(hw, mac_addr);
1629         if (ret) {
1630                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631                                       mac_addr);
1632                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1633                          mac_str, ret);
1634         }
1635         return ret;
1636 }
1637
1638 static int
1639 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1640 {
1641         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1642         int ret;
1643
1644         ret = hns3_remove_mc_addr(hw, mac_addr);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1649                          mac_str, ret);
1650         }
1651         return ret;
1652 }
1653
1654 static int
1655 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1656                   uint32_t idx, __rte_unused uint32_t pool)
1657 {
1658         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         int ret;
1661
1662         rte_spinlock_lock(&hw->lock);
1663
1664         /*
1665          * In hns3 network engine adding UC and MC mac address with different
1666          * commands with firmware. We need to determine whether the input
1667          * address is a UC or a MC address to call different commands.
1668          * By the way, it is recommended calling the API function named
1669          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1670          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1671          * may affect the specifications of UC mac addresses.
1672          */
1673         if (rte_is_multicast_ether_addr(mac_addr))
1674                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1675         else
1676                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1677
1678         if (ret) {
1679                 rte_spinlock_unlock(&hw->lock);
1680                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681                                       mac_addr);
1682                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1683                          ret);
1684                 return ret;
1685         }
1686
1687         if (idx == 0)
1688                 hw->mac.default_addr_setted = true;
1689         rte_spinlock_unlock(&hw->lock);
1690
1691         return ret;
1692 }
1693
1694 static int
1695 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1696 {
1697         struct hns3_mac_vlan_tbl_entry_cmd req;
1698         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1699         int ret;
1700
1701         /* check if mac addr is valid */
1702         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1703                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704                                       mac_addr);
1705                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1706                          mac_str);
1707                 return -EINVAL;
1708         }
1709
1710         memset(&req, 0, sizeof(req));
1711         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1712         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1713         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1714         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1715                 return 0;
1716         else if (ret == 0)
1717                 hns3_update_umv_space(hw, true);
1718
1719         return ret;
1720 }
1721
1722 static void
1723 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1724 {
1725         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         /* index will be checked by upper level rte interface */
1727         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1728         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1729         int ret;
1730
1731         rte_spinlock_lock(&hw->lock);
1732
1733         if (rte_is_multicast_ether_addr(mac_addr))
1734                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1735         else
1736                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1737         rte_spinlock_unlock(&hw->lock);
1738         if (ret) {
1739                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       mac_addr);
1741                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1742                          ret);
1743         }
1744 }
1745
1746 static int
1747 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1748                           struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751         struct rte_ether_addr *oaddr;
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         bool default_addr_setted;
1754         bool rm_succes = false;
1755         int ret, ret_val;
1756
1757         /*
1758          * It has been guaranteed that input parameter named mac_addr is valid
1759          * address in the rte layer of DPDK framework.
1760          */
1761         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1762         default_addr_setted = hw->mac.default_addr_setted;
1763         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1764                 return 0;
1765
1766         rte_spinlock_lock(&hw->lock);
1767         if (default_addr_setted) {
1768                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1769                 if (ret) {
1770                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1771                                               oaddr);
1772                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1773                                   mac_str, ret);
1774                         rm_succes = false;
1775                 } else
1776                         rm_succes = true;
1777         }
1778
1779         ret = hns3_add_uc_addr_common(hw, mac_addr);
1780         if (ret) {
1781                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                       mac_addr);
1783                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1784                 goto err_add_uc_addr;
1785         }
1786
1787         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1788         if (ret) {
1789                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1790                 goto err_pause_addr_cfg;
1791         }
1792
1793         rte_ether_addr_copy(mac_addr,
1794                             (struct rte_ether_addr *)hw->mac.mac_addr);
1795         hw->mac.default_addr_setted = true;
1796         rte_spinlock_unlock(&hw->lock);
1797
1798         return 0;
1799
1800 err_pause_addr_cfg:
1801         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1802         if (ret_val) {
1803                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1804                                       mac_addr);
1805                 hns3_warn(hw,
1806                           "Failed to roll back to del setted mac addr(%s): %d",
1807                           mac_str, ret_val);
1808         }
1809
1810 err_add_uc_addr:
1811         if (rm_succes) {
1812                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1813                 if (ret_val) {
1814                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                               oaddr);
1816                         hns3_warn(hw,
1817                                   "Failed to restore old uc mac addr(%s): %d",
1818                                   mac_str, ret_val);
1819                         hw->mac.default_addr_setted = false;
1820                 }
1821         }
1822         rte_spinlock_unlock(&hw->lock);
1823
1824         return ret;
1825 }
1826
1827 static int
1828 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1829 {
1830         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1831         struct hns3_hw *hw = &hns->hw;
1832         struct rte_ether_addr *addr;
1833         int err = 0;
1834         int ret;
1835         int i;
1836
1837         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1838                 addr = &hw->data->mac_addrs[i];
1839                 if (rte_is_zero_ether_addr(addr))
1840                         continue;
1841                 if (rte_is_multicast_ether_addr(addr))
1842                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1843                               hns3_add_mc_addr(hw, addr);
1844                 else
1845                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1846                               hns3_add_uc_addr_common(hw, addr);
1847
1848                 if (ret) {
1849                         err = ret;
1850                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1851                                               addr);
1852                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1853                                  "ret = %d.", del ? "remove" : "restore",
1854                                  mac_str, i, ret);
1855                 }
1856         }
1857         return err;
1858 }
1859
1860 static void
1861 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1862 {
1863 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864         uint8_t word_num;
1865         uint8_t bit_num;
1866
1867         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1868                 word_num = vfid / 32;
1869                 bit_num = vfid % 32;
1870                 if (clr)
1871                         desc[1].data[word_num] &=
1872                             rte_cpu_to_le_32(~(1UL << bit_num));
1873                 else
1874                         desc[1].data[word_num] |=
1875                             rte_cpu_to_le_32(1UL << bit_num);
1876         } else {
1877                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1878                 bit_num = vfid % 32;
1879                 if (clr)
1880                         desc[2].data[word_num] &=
1881                             rte_cpu_to_le_32(~(1UL << bit_num));
1882                 else
1883                         desc[2].data[word_num] |=
1884                             rte_cpu_to_le_32(1UL << bit_num);
1885         }
1886 }
1887
1888 static int
1889 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1890 {
1891         struct hns3_mac_vlan_tbl_entry_cmd req;
1892         struct hns3_cmd_desc desc[3];
1893         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894         uint8_t vf_id;
1895         int ret;
1896
1897         /* Check if mac addr is valid */
1898         if (!rte_is_multicast_ether_addr(mac_addr)) {
1899                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1900                                       mac_addr);
1901                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1902                          mac_str);
1903                 return -EINVAL;
1904         }
1905
1906         memset(&req, 0, sizeof(req));
1907         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1908         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1909         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1910         if (ret) {
1911                 /* This mac addr do not exist, add new entry for it */
1912                 memset(desc[0].data, 0, sizeof(desc[0].data));
1913                 memset(desc[1].data, 0, sizeof(desc[0].data));
1914                 memset(desc[2].data, 0, sizeof(desc[0].data));
1915         }
1916
1917         /*
1918          * In current version VF is not supported when PF is driven by DPDK
1919          * driver, just need to configure parameters for PF vport.
1920          */
1921         vf_id = HNS3_PF_FUNC_ID;
1922         hns3_update_desc_vfid(desc, vf_id, false);
1923         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1924         if (ret) {
1925                 if (ret == -ENOSPC)
1926                         hns3_err(hw, "mc mac vlan table is full");
1927                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                       mac_addr);
1929                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1930         }
1931
1932         return ret;
1933 }
1934
1935 static int
1936 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 {
1938         struct hns3_mac_vlan_tbl_entry_cmd req;
1939         struct hns3_cmd_desc desc[3];
1940         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1941         uint8_t vf_id;
1942         int ret;
1943
1944         /* Check if mac addr is valid */
1945         if (!rte_is_multicast_ether_addr(mac_addr)) {
1946                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947                                       mac_addr);
1948                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1949                          mac_str);
1950                 return -EINVAL;
1951         }
1952
1953         memset(&req, 0, sizeof(req));
1954         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1955         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1956         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1957         if (ret == 0) {
1958                 /*
1959                  * This mac addr exist, remove this handle's VFID for it.
1960                  * In current version VF is not supported when PF is driven by
1961                  * DPDK driver, just need to configure parameters for PF vport.
1962                  */
1963                 vf_id = HNS3_PF_FUNC_ID;
1964                 hns3_update_desc_vfid(desc, vf_id, true);
1965
1966                 /* All the vfid is zero, so need to delete this entry */
1967                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968         } else if (ret == -ENOENT) {
1969                 /* This mac addr doesn't exist. */
1970                 return 0;
1971         }
1972
1973         if (ret) {
1974                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975                                       mac_addr);
1976                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984                            struct rte_ether_addr *mc_addr_set,
1985                            uint32_t nb_mc_addr)
1986 {
1987         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988         struct rte_ether_addr *addr;
1989         uint32_t i;
1990         uint32_t j;
1991
1992         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994                          "invalid. valid range: 0~%d",
1995                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1996                 return -EINVAL;
1997         }
1998
1999         /* Check if input mac addresses are valid */
2000         for (i = 0; i < nb_mc_addr; i++) {
2001                 addr = &mc_addr_set[i];
2002                 if (!rte_is_multicast_ether_addr(addr)) {
2003                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2004                                               addr);
2005                         hns3_err(hw,
2006                                  "failed to set mc mac addr, addr(%s) invalid.",
2007                                  mac_str);
2008                         return -EINVAL;
2009                 }
2010
2011                 /* Check if there are duplicate addresses */
2012                 for (j = i + 1; j < nb_mc_addr; j++) {
2013                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014                                 hns3_ether_format_addr(mac_str,
2015                                                       RTE_ETHER_ADDR_FMT_SIZE,
2016                                                       addr);
2017                                 hns3_err(hw, "failed to set mc mac addr, "
2018                                          "addrs invalid. two same addrs(%s).",
2019                                          mac_str);
2020                                 return -EINVAL;
2021                         }
2022                 }
2023
2024                 /*
2025                  * Check if there are duplicate addresses between mac_addrs
2026                  * and mc_addr_set
2027                  */
2028                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029                         if (rte_is_same_ether_addr(addr,
2030                                                    &hw->data->mac_addrs[j])) {
2031                                 hns3_ether_format_addr(mac_str,
2032                                                       RTE_ETHER_ADDR_FMT_SIZE,
2033                                                       addr);
2034                                 hns3_err(hw, "failed to set mc mac addr, "
2035                                          "addrs invalid. addrs(%s) has already "
2036                                          "configured in mac_addr add API",
2037                                          mac_str);
2038                                 return -EINVAL;
2039                         }
2040                 }
2041         }
2042
2043         return 0;
2044 }
2045
2046 static void
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048                            struct rte_ether_addr *mc_addr_set,
2049                            int mc_addr_num,
2050                            struct rte_ether_addr *reserved_addr_list,
2051                            int *reserved_addr_num,
2052                            struct rte_ether_addr *add_addr_list,
2053                            int *add_addr_num,
2054                            struct rte_ether_addr *rm_addr_list,
2055                            int *rm_addr_num)
2056 {
2057         struct rte_ether_addr *addr;
2058         int current_addr_num;
2059         int reserved_num = 0;
2060         int add_num = 0;
2061         int rm_num = 0;
2062         int num;
2063         int i;
2064         int j;
2065         bool same_addr;
2066
2067         /* Calculate the mc mac address list that should be removed */
2068         current_addr_num = hw->mc_addrs_num;
2069         for (i = 0; i < current_addr_num; i++) {
2070                 addr = &hw->mc_addrs[i];
2071                 same_addr = false;
2072                 for (j = 0; j < mc_addr_num; j++) {
2073                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2074                                 same_addr = true;
2075                                 break;
2076                         }
2077                 }
2078
2079                 if (!same_addr) {
2080                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2081                         rm_num++;
2082                 } else {
2083                         rte_ether_addr_copy(addr,
2084                                             &reserved_addr_list[reserved_num]);
2085                         reserved_num++;
2086                 }
2087         }
2088
2089         /* Calculate the mc mac address list that should be added */
2090         for (i = 0; i < mc_addr_num; i++) {
2091                 addr = &mc_addr_set[i];
2092                 same_addr = false;
2093                 for (j = 0; j < current_addr_num; j++) {
2094                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2095                                 same_addr = true;
2096                                 break;
2097                         }
2098                 }
2099
2100                 if (!same_addr) {
2101                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2102                         add_num++;
2103                 }
2104         }
2105
2106         /* Reorder the mc mac address list maintained by driver */
2107         for (i = 0; i < reserved_num; i++)
2108                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2109
2110         for (i = 0; i < rm_num; i++) {
2111                 num = reserved_num + i;
2112                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2113         }
2114
2115         *reserved_addr_num = reserved_num;
2116         *add_addr_num = add_num;
2117         *rm_addr_num = rm_num;
2118 }
2119
2120 static int
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122                           struct rte_ether_addr *mc_addr_set,
2123                           uint32_t nb_mc_addr)
2124 {
2125         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129         struct rte_ether_addr *addr;
2130         int reserved_addr_num;
2131         int add_addr_num;
2132         int rm_addr_num;
2133         int mc_addr_num;
2134         int num;
2135         int ret;
2136         int i;
2137
2138         /* Check if input parameters are valid */
2139         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2140         if (ret)
2141                 return ret;
2142
2143         rte_spinlock_lock(&hw->lock);
2144
2145         /*
2146          * Calculate the mc mac address lists those should be removed and be
2147          * added, Reorder the mc mac address list maintained by driver.
2148          */
2149         mc_addr_num = (int)nb_mc_addr;
2150         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151                                    reserved_addr_list, &reserved_addr_num,
2152                                    add_addr_list, &add_addr_num,
2153                                    rm_addr_list, &rm_addr_num);
2154
2155         /* Remove mc mac addresses */
2156         for (i = 0; i < rm_addr_num; i++) {
2157                 num = rm_addr_num - i - 1;
2158                 addr = &rm_addr_list[num];
2159                 ret = hns3_remove_mc_addr(hw, addr);
2160                 if (ret) {
2161                         rte_spinlock_unlock(&hw->lock);
2162                         return ret;
2163                 }
2164                 hw->mc_addrs_num--;
2165         }
2166
2167         /* Add mc mac addresses */
2168         for (i = 0; i < add_addr_num; i++) {
2169                 addr = &add_addr_list[i];
2170                 ret = hns3_add_mc_addr(hw, addr);
2171                 if (ret) {
2172                         rte_spinlock_unlock(&hw->lock);
2173                         return ret;
2174                 }
2175
2176                 num = reserved_addr_num + i;
2177                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2178                 hw->mc_addrs_num++;
2179         }
2180         rte_spinlock_unlock(&hw->lock);
2181
2182         return 0;
2183 }
2184
2185 static int
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2187 {
2188         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189         struct hns3_hw *hw = &hns->hw;
2190         struct rte_ether_addr *addr;
2191         int err = 0;
2192         int ret;
2193         int i;
2194
2195         for (i = 0; i < hw->mc_addrs_num; i++) {
2196                 addr = &hw->mc_addrs[i];
2197                 if (!rte_is_multicast_ether_addr(addr))
2198                         continue;
2199                 if (del)
2200                         ret = hns3_remove_mc_addr(hw, addr);
2201                 else
2202                         ret = hns3_add_mc_addr(hw, addr);
2203                 if (ret) {
2204                         err = ret;
2205                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2206                                               addr);
2207                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208                                  del ? "Remove" : "Restore", mac_str, ret);
2209                 }
2210         }
2211         return err;
2212 }
2213
2214 static int
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2216 {
2217         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2223         uint8_t num_tc;
2224         int max_tc = 0;
2225         int i;
2226
2227         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2228         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2229
2230         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2231                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2232                          "rx_mq_mode = %d", rx_mq_mode);
2233                 return -EINVAL;
2234         }
2235
2236         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2237             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2238                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2239                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2240                          rx_mq_mode, tx_mq_mode);
2241                 return -EINVAL;
2242         }
2243
2244         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2245                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2246                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2247                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2252                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2253                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2254                                  "nb_tcs(%d) != %d or %d in rx direction.",
2255                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2256                         return -EINVAL;
2257                 }
2258
2259                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2260                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2261                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2262                         return -EINVAL;
2263                 }
2264
2265                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2266                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2267                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2268                                          "is not equal to one in tx direction.",
2269                                          i, dcb_rx_conf->dcb_tc[i]);
2270                                 return -EINVAL;
2271                         }
2272                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2273                                 max_tc = dcb_rx_conf->dcb_tc[i];
2274                 }
2275
2276                 num_tc = max_tc + 1;
2277                 if (num_tc > dcb_rx_conf->nb_tcs) {
2278                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2279                                  num_tc, dcb_rx_conf->nb_tcs);
2280                         return -EINVAL;
2281                 }
2282         }
2283
2284         return 0;
2285 }
2286
2287 static int
2288 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2289 {
2290         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291
2292         if (!hns3_dev_dcb_supported(hw)) {
2293                 hns3_err(hw, "this port does not support dcb configurations.");
2294                 return -EOPNOTSUPP;
2295         }
2296
2297         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2298                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2299                 return -EOPNOTSUPP;
2300         }
2301
2302         /* Check multiple queue mode */
2303         return hns3_check_mq_mode(dev);
2304 }
2305
2306 static int
2307 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2308                            enum hns3_ring_type queue_type, uint16_t queue_id)
2309 {
2310         struct hns3_cmd_desc desc;
2311         struct hns3_ctrl_vector_chain_cmd *req =
2312                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2313         enum hns3_opcode_type op;
2314         uint16_t tqp_type_and_id = 0;
2315         uint16_t type;
2316         uint16_t gl;
2317         int ret;
2318
2319         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2320         hns3_cmd_setup_basic_desc(&desc, op, false);
2321         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2322                                               HNS3_TQP_INT_ID_L_S);
2323         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2324                                               HNS3_TQP_INT_ID_H_S);
2325
2326         if (queue_type == HNS3_RING_TYPE_RX)
2327                 gl = HNS3_RING_GL_RX;
2328         else
2329                 gl = HNS3_RING_GL_TX;
2330
2331         type = queue_type;
2332
2333         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2334                        type);
2335         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2336         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2337                        gl);
2338         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2339         req->int_cause_num = 1;
2340         ret = hns3_cmd_send(hw, &desc, 1);
2341         if (ret) {
2342                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2343                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2344                 return ret;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int
2351 hns3_init_ring_with_vector(struct hns3_hw *hw)
2352 {
2353         uint16_t vec;
2354         int ret;
2355         int i;
2356
2357         /*
2358          * In hns3 network engine, vector 0 is always the misc interrupt of this
2359          * function, vector 1~N can be used respectively for the queues of the
2360          * function. Tx and Rx queues with the same number share the interrupt
2361          * vector. In the initialization clearing the all hardware mapping
2362          * relationship configurations between queues and interrupt vectors is
2363          * needed, so some error caused by the residual configurations, such as
2364          * the unexpected Tx interrupt, can be avoid.
2365          */
2366         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2367         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2368                 vec = vec - 1; /* the last interrupt is reserved */
2369         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2370         for (i = 0; i < hw->intr_tqps_num; i++) {
2371                 /*
2372                  * Set gap limiter/rate limiter/quanity limiter algorithm
2373                  * configuration for interrupt coalesce of queue's interrupt.
2374                  */
2375                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2376                                        HNS3_TQP_INTR_GL_DEFAULT);
2377                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2378                                        HNS3_TQP_INTR_GL_DEFAULT);
2379                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2380                 /*
2381                  * QL(quantity limiter) is not used currently, just set 0 to
2382                  * close it.
2383                  */
2384                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2385
2386                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2387                                                  HNS3_RING_TYPE_TX, i);
2388                 if (ret) {
2389                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2390                                           "vector: %u, ret=%d", i, vec, ret);
2391                         return ret;
2392                 }
2393
2394                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2395                                                  HNS3_RING_TYPE_RX, i);
2396                 if (ret) {
2397                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2398                                           "vector: %u, ret=%d", i, vec, ret);
2399                         return ret;
2400                 }
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int
2407 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2408 {
2409         struct hns3_adapter *hns = dev->data->dev_private;
2410         struct hns3_hw *hw = &hns->hw;
2411         uint32_t max_rx_pkt_len;
2412         uint16_t mtu;
2413         int ret;
2414
2415         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2416                 return 0;
2417
2418         /*
2419          * If jumbo frames are enabled, MTU needs to be refreshed
2420          * according to the maximum RX packet length.
2421          */
2422         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2423         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2424             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2425                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2426                          "and no more than %u when jumbo frame enabled.",
2427                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2428                          (uint16_t)HNS3_MAX_FRAME_LEN);
2429                 return -EINVAL;
2430         }
2431
2432         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2433         ret = hns3_dev_mtu_set(dev, mtu);
2434         if (ret)
2435                 return ret;
2436         dev->data->mtu = mtu;
2437
2438         return 0;
2439 }
2440
2441 static int
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2443 {
2444         struct hns3_adapter *hns = dev->data->dev_private;
2445         struct rte_eth_conf *conf = &dev->data->dev_conf;
2446         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447         struct hns3_hw *hw = &hns->hw;
2448         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450         struct rte_eth_rss_conf rss_conf;
2451         bool gro_en;
2452         int ret;
2453
2454         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2455
2456         /*
2457          * Some versions of hardware network engine does not support
2458          * individually enable/disable/reset the Tx or Rx queue. These devices
2459          * must enable/disable/reset Tx and Rx queues at the same time. When the
2460          * numbers of Tx queues allocated by upper applications are not equal to
2461          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463          * work as usual. But these fake queues are imperceptible, and can not
2464          * be used by upper applications.
2465          */
2466         if (!hns3_dev_indep_txrx_supported(hw)) {
2467                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2468                 if (ret) {
2469                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2470                                  ret);
2471                         return ret;
2472                 }
2473         }
2474
2475         hw->adapter_state = HNS3_NIC_CONFIGURING;
2476         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2477                 hns3_err(hw, "setting link speed/duplex not supported");
2478                 ret = -EINVAL;
2479                 goto cfg_err;
2480         }
2481
2482         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2483                 ret = hns3_check_dcb_cfg(dev);
2484                 if (ret)
2485                         goto cfg_err;
2486         }
2487
2488         /* When RSS is not configured, redirect the packet queue 0 */
2489         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2490                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2491                 rss_conf = conf->rx_adv_conf.rss_conf;
2492                 hw->rss_dis_flag = false;
2493                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2494                 if (ret)
2495                         goto cfg_err;
2496         }
2497
2498         ret = hns3_refresh_mtu(dev, conf);
2499         if (ret)
2500                 goto cfg_err;
2501
2502         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2503         if (ret)
2504                 goto cfg_err;
2505
2506         ret = hns3_dev_configure_vlan(dev);
2507         if (ret)
2508                 goto cfg_err;
2509
2510         /* config hardware GRO */
2511         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2512         ret = hns3_config_gro(hw, gro_en);
2513         if (ret)
2514                 goto cfg_err;
2515
2516         hns3_init_rx_ptype_tble(dev);
2517         hw->adapter_state = HNS3_NIC_CONFIGURED;
2518
2519         return 0;
2520
2521 cfg_err:
2522         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2523         hw->adapter_state = HNS3_NIC_INITIALIZED;
2524
2525         return ret;
2526 }
2527
2528 static int
2529 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2530 {
2531         struct hns3_config_max_frm_size_cmd *req;
2532         struct hns3_cmd_desc desc;
2533
2534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2535
2536         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2537         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2538         req->min_frm_size = RTE_ETHER_MIN_LEN;
2539
2540         return hns3_cmd_send(hw, &desc, 1);
2541 }
2542
2543 static int
2544 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2545 {
2546         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2547         uint16_t original_mps = hns->pf.mps;
2548         int err;
2549         int ret;
2550
2551         ret = hns3_set_mac_mtu(hw, mps);
2552         if (ret) {
2553                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2554                 return ret;
2555         }
2556
2557         hns->pf.mps = mps;
2558         ret = hns3_buffer_alloc(hw);
2559         if (ret) {
2560                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2561                 goto rollback;
2562         }
2563
2564         return 0;
2565
2566 rollback:
2567         err = hns3_set_mac_mtu(hw, original_mps);
2568         if (err) {
2569                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2570                 return ret;
2571         }
2572         hns->pf.mps = original_mps;
2573
2574         return ret;
2575 }
2576
2577 static int
2578 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2579 {
2580         struct hns3_adapter *hns = dev->data->dev_private;
2581         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2582         struct hns3_hw *hw = &hns->hw;
2583         bool is_jumbo_frame;
2584         int ret;
2585
2586         if (dev->data->dev_started) {
2587                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2588                          "before configuration", dev->data->port_id);
2589                 return -EBUSY;
2590         }
2591
2592         rte_spinlock_lock(&hw->lock);
2593         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2594         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2595
2596         /*
2597          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2598          * assign to "uint16_t" type variable.
2599          */
2600         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2601         if (ret) {
2602                 rte_spinlock_unlock(&hw->lock);
2603                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2604                          dev->data->port_id, mtu, ret);
2605                 return ret;
2606         }
2607
2608         if (is_jumbo_frame)
2609                 dev->data->dev_conf.rxmode.offloads |=
2610                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2611         else
2612                 dev->data->dev_conf.rxmode.offloads &=
2613                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2614         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2615         rte_spinlock_unlock(&hw->lock);
2616
2617         return 0;
2618 }
2619
2620 static uint32_t
2621 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2622 {
2623         uint32_t speed_capa = 0;
2624
2625         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2626                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2627         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2628                 speed_capa |= ETH_LINK_SPEED_10M;
2629         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2630                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2631         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2632                 speed_capa |= ETH_LINK_SPEED_100M;
2633         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2634                 speed_capa |= ETH_LINK_SPEED_1G;
2635
2636         return speed_capa;
2637 }
2638
2639 static uint32_t
2640 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2641 {
2642         uint32_t speed_capa = 0;
2643
2644         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2645                 speed_capa |= ETH_LINK_SPEED_1G;
2646         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2647                 speed_capa |= ETH_LINK_SPEED_10G;
2648         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2649                 speed_capa |= ETH_LINK_SPEED_25G;
2650         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2651                 speed_capa |= ETH_LINK_SPEED_40G;
2652         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2653                 speed_capa |= ETH_LINK_SPEED_50G;
2654         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2655                 speed_capa |= ETH_LINK_SPEED_100G;
2656         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2657                 speed_capa |= ETH_LINK_SPEED_200G;
2658
2659         return speed_capa;
2660 }
2661
2662 static uint32_t
2663 hns3_get_speed_capa(struct hns3_hw *hw)
2664 {
2665         struct hns3_mac *mac = &hw->mac;
2666         uint32_t speed_capa;
2667
2668         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2669                 speed_capa =
2670                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2671         else
2672                 speed_capa =
2673                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2674
2675         if (mac->support_autoneg == 0)
2676                 speed_capa |= ETH_LINK_SPEED_FIXED;
2677
2678         return speed_capa;
2679 }
2680
2681 int
2682 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2683 {
2684         struct hns3_adapter *hns = eth_dev->data->dev_private;
2685         struct hns3_hw *hw = &hns->hw;
2686         uint16_t queue_num = hw->tqps_num;
2687
2688         /*
2689          * In interrupt mode, 'max_rx_queues' is set based on the number of
2690          * MSI-X interrupt resources of the hardware.
2691          */
2692         if (hw->data->dev_conf.intr_conf.rxq == 1)
2693                 queue_num = hw->intr_tqps_num;
2694
2695         info->max_rx_queues = queue_num;
2696         info->max_tx_queues = hw->tqps_num;
2697         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2698         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2699         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2700         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2701         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2702         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2703                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2704                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2705                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2706                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2707                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2708                                  DEV_RX_OFFLOAD_KEEP_CRC |
2709                                  DEV_RX_OFFLOAD_SCATTER |
2710                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2711                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2712                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2713                                  DEV_RX_OFFLOAD_RSS_HASH |
2714                                  DEV_RX_OFFLOAD_TCP_LRO);
2715         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2716                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2717                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2718                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2719                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2720                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2721                                  DEV_TX_OFFLOAD_TCP_TSO |
2722                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2723                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2724                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2725                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2726                                  hns3_txvlan_cap_get(hw));
2727
2728         if (hns3_dev_outer_udp_cksum_supported(hw))
2729                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2730
2731         if (hns3_dev_indep_txrx_supported(hw))
2732                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2733                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2734
2735         if (hns3_dev_ptp_supported(hw))
2736                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2737
2738         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2739                 .nb_max = HNS3_MAX_RING_DESC,
2740                 .nb_min = HNS3_MIN_RING_DESC,
2741                 .nb_align = HNS3_ALIGN_RING_DESC,
2742         };
2743
2744         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2745                 .nb_max = HNS3_MAX_RING_DESC,
2746                 .nb_min = HNS3_MIN_RING_DESC,
2747                 .nb_align = HNS3_ALIGN_RING_DESC,
2748                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2749                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2750         };
2751
2752         info->speed_capa = hns3_get_speed_capa(hw);
2753         info->default_rxconf = (struct rte_eth_rxconf) {
2754                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2755                 /*
2756                  * If there are no available Rx buffer descriptors, incoming
2757                  * packets are always dropped by hardware based on hns3 network
2758                  * engine.
2759                  */
2760                 .rx_drop_en = 1,
2761                 .offloads = 0,
2762         };
2763         info->default_txconf = (struct rte_eth_txconf) {
2764                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2765                 .offloads = 0,
2766         };
2767
2768         info->vmdq_queue_num = 0;
2769
2770         info->reta_size = hw->rss_ind_tbl_size;
2771         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2772         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2773
2774         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2775         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2776         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2777         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2778         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2779         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2780
2781         return 0;
2782 }
2783
2784 static int
2785 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2786                     size_t fw_size)
2787 {
2788         struct hns3_adapter *hns = eth_dev->data->dev_private;
2789         struct hns3_hw *hw = &hns->hw;
2790         uint32_t version = hw->fw_version;
2791         int ret;
2792
2793         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2794                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2795                                       HNS3_FW_VERSION_BYTE3_S),
2796                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2797                                       HNS3_FW_VERSION_BYTE2_S),
2798                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2799                                       HNS3_FW_VERSION_BYTE1_S),
2800                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2801                                       HNS3_FW_VERSION_BYTE0_S));
2802         ret += 1; /* add the size of '\0' */
2803         if (fw_size < (uint32_t)ret)
2804                 return ret;
2805         else
2806                 return 0;
2807 }
2808
2809 static int
2810 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2811 {
2812         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2813         int ret;
2814
2815         (void)hns3_update_link_status(hw);
2816
2817         ret = hns3_update_link_info(eth_dev);
2818         if (ret)
2819                 hw->mac.link_status = ETH_LINK_DOWN;
2820
2821         return ret;
2822 }
2823
2824 static void
2825 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2826                       struct rte_eth_link *new_link)
2827 {
2828         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2829         struct hns3_mac *mac = &hw->mac;
2830
2831         switch (mac->link_speed) {
2832         case ETH_SPEED_NUM_10M:
2833         case ETH_SPEED_NUM_100M:
2834         case ETH_SPEED_NUM_1G:
2835         case ETH_SPEED_NUM_10G:
2836         case ETH_SPEED_NUM_25G:
2837         case ETH_SPEED_NUM_40G:
2838         case ETH_SPEED_NUM_50G:
2839         case ETH_SPEED_NUM_100G:
2840         case ETH_SPEED_NUM_200G:
2841                 new_link->link_speed = mac->link_speed;
2842                 break;
2843         default:
2844                 if (mac->link_status)
2845                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2846                 else
2847                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2848                 break;
2849         }
2850
2851         new_link->link_duplex = mac->link_duplex;
2852         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2853         new_link->link_autoneg = mac->link_autoneg;
2854 }
2855
2856 static int
2857 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2858 {
2859 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2860 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2861
2862         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2863         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2864         struct hns3_mac *mac = &hw->mac;
2865         struct rte_eth_link new_link;
2866         int ret;
2867
2868         do {
2869                 ret = hns3_update_port_link_info(eth_dev);
2870                 if (ret) {
2871                         hns3_err(hw, "failed to get port link info, ret = %d.",
2872                                  ret);
2873                         break;
2874                 }
2875
2876                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2877                         break;
2878
2879                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2880         } while (retry_cnt--);
2881
2882         memset(&new_link, 0, sizeof(new_link));
2883         hns3_setup_linkstatus(eth_dev, &new_link);
2884
2885         return rte_eth_linkstatus_set(eth_dev, &new_link);
2886 }
2887
2888 static int
2889 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2890 {
2891         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2892         struct hns3_pf *pf = &hns->pf;
2893
2894         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2895                 return -EINVAL;
2896
2897         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2898
2899         return 0;
2900 }
2901
2902 static int
2903 hns3_query_function_status(struct hns3_hw *hw)
2904 {
2905 #define HNS3_QUERY_MAX_CNT              10
2906 #define HNS3_QUERY_SLEEP_MSCOEND        1
2907         struct hns3_func_status_cmd *req;
2908         struct hns3_cmd_desc desc;
2909         int timeout = 0;
2910         int ret;
2911
2912         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2913         req = (struct hns3_func_status_cmd *)desc.data;
2914
2915         do {
2916                 ret = hns3_cmd_send(hw, &desc, 1);
2917                 if (ret) {
2918                         PMD_INIT_LOG(ERR, "query function status failed %d",
2919                                      ret);
2920                         return ret;
2921                 }
2922
2923                 /* Check pf reset is done */
2924                 if (req->pf_state)
2925                         break;
2926
2927                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2928         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2929
2930         return hns3_parse_func_status(hw, req);
2931 }
2932
2933 static int
2934 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2935 {
2936         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2937         struct hns3_pf *pf = &hns->pf;
2938
2939         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2940                 /*
2941                  * The total_tqps_num obtained from firmware is maximum tqp
2942                  * numbers of this port, which should be used for PF and VFs.
2943                  * There is no need for pf to have so many tqp numbers in
2944                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2945                  * coming from config file, is assigned to maximum queue number
2946                  * for the PF of this port by user. So users can modify the
2947                  * maximum queue number of PF according to their own application
2948                  * scenarios, which is more flexible to use. In addition, many
2949                  * memories can be saved due to allocating queue statistics
2950                  * room according to the actual number of queues required. The
2951                  * maximum queue number of PF for network engine with
2952                  * revision_id greater than 0x30 is assigned by config file.
2953                  */
2954                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2955                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2956                                  "must be greater than 0.",
2957                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2958                         return -EINVAL;
2959                 }
2960
2961                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2962                                        hw->total_tqps_num);
2963         } else {
2964                 /*
2965                  * Due to the limitation on the number of PF interrupts
2966                  * available, the maximum queue number assigned to PF on
2967                  * the network engine with revision_id 0x21 is 64.
2968                  */
2969                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2970                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2971         }
2972
2973         return 0;
2974 }
2975
2976 static int
2977 hns3_query_pf_resource(struct hns3_hw *hw)
2978 {
2979         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2980         struct hns3_pf *pf = &hns->pf;
2981         struct hns3_pf_res_cmd *req;
2982         struct hns3_cmd_desc desc;
2983         int ret;
2984
2985         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2986         ret = hns3_cmd_send(hw, &desc, 1);
2987         if (ret) {
2988                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2989                 return ret;
2990         }
2991
2992         req = (struct hns3_pf_res_cmd *)desc.data;
2993         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2994                              rte_le_to_cpu_16(req->ext_tqp_num);
2995         ret = hns3_get_pf_max_tqp_num(hw);
2996         if (ret)
2997                 return ret;
2998
2999         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3000         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3001
3002         if (req->tx_buf_size)
3003                 pf->tx_buf_size =
3004                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3005         else
3006                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3007
3008         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3009
3010         if (req->dv_buf_size)
3011                 pf->dv_buf_size =
3012                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3013         else
3014                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3015
3016         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3017
3018         hw->num_msi =
3019                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3020                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3021
3022         return 0;
3023 }
3024
3025 static void
3026 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3027 {
3028         struct hns3_cfg_param_cmd *req;
3029         uint64_t mac_addr_tmp_high;
3030         uint8_t ext_rss_size_max;
3031         uint64_t mac_addr_tmp;
3032         uint32_t i;
3033
3034         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3035
3036         /* get the configuration */
3037         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3038                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3039         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3040                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3041         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3042                                            HNS3_CFG_TQP_DESC_N_M,
3043                                            HNS3_CFG_TQP_DESC_N_S);
3044
3045         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3046                                        HNS3_CFG_PHY_ADDR_M,
3047                                        HNS3_CFG_PHY_ADDR_S);
3048         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3049                                          HNS3_CFG_MEDIA_TP_M,
3050                                          HNS3_CFG_MEDIA_TP_S);
3051         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3052                                          HNS3_CFG_RX_BUF_LEN_M,
3053                                          HNS3_CFG_RX_BUF_LEN_S);
3054         /* get mac address */
3055         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3056         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3057                                            HNS3_CFG_MAC_ADDR_H_M,
3058                                            HNS3_CFG_MAC_ADDR_H_S);
3059
3060         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3061
3062         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3063                                             HNS3_CFG_DEFAULT_SPEED_M,
3064                                             HNS3_CFG_DEFAULT_SPEED_S);
3065         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3066                                            HNS3_CFG_RSS_SIZE_M,
3067                                            HNS3_CFG_RSS_SIZE_S);
3068
3069         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3070                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3071
3072         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3073         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3074
3075         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3076                                             HNS3_CFG_SPEED_ABILITY_M,
3077                                             HNS3_CFG_SPEED_ABILITY_S);
3078         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3079                                         HNS3_CFG_UMV_TBL_SPACE_M,
3080                                         HNS3_CFG_UMV_TBL_SPACE_S);
3081         if (!cfg->umv_space)
3082                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3083
3084         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3085                                                HNS3_CFG_EXT_RSS_SIZE_M,
3086                                                HNS3_CFG_EXT_RSS_SIZE_S);
3087
3088         /*
3089          * Field ext_rss_size_max obtained from firmware will be more flexible
3090          * for future changes and expansions, which is an exponent of 2, instead
3091          * of reading out directly. If this field is not zero, hns3 PF PMD
3092          * driver uses it as rss_size_max under one TC. Device, whose revision
3093          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3094          * maximum number of queues supported under a TC through this field.
3095          */
3096         if (ext_rss_size_max)
3097                 cfg->rss_size_max = 1U << ext_rss_size_max;
3098 }
3099
3100 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3101  * @hw: pointer to struct hns3_hw
3102  * @hcfg: the config structure to be getted
3103  */
3104 static int
3105 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3106 {
3107         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3108         struct hns3_cfg_param_cmd *req;
3109         uint32_t offset;
3110         uint32_t i;
3111         int ret;
3112
3113         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3114                 offset = 0;
3115                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3116                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3117                                           true);
3118                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3119                                i * HNS3_CFG_RD_LEN_BYTES);
3120                 /* Len should be divided by 4 when send to hardware */
3121                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3122                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3123                 req->offset = rte_cpu_to_le_32(offset);
3124         }
3125
3126         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3127         if (ret) {
3128                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3129                 return ret;
3130         }
3131
3132         hns3_parse_cfg(hcfg, desc);
3133
3134         return 0;
3135 }
3136
3137 static int
3138 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3139 {
3140         switch (speed_cmd) {
3141         case HNS3_CFG_SPEED_10M:
3142                 *speed = ETH_SPEED_NUM_10M;
3143                 break;
3144         case HNS3_CFG_SPEED_100M:
3145                 *speed = ETH_SPEED_NUM_100M;
3146                 break;
3147         case HNS3_CFG_SPEED_1G:
3148                 *speed = ETH_SPEED_NUM_1G;
3149                 break;
3150         case HNS3_CFG_SPEED_10G:
3151                 *speed = ETH_SPEED_NUM_10G;
3152                 break;
3153         case HNS3_CFG_SPEED_25G:
3154                 *speed = ETH_SPEED_NUM_25G;
3155                 break;
3156         case HNS3_CFG_SPEED_40G:
3157                 *speed = ETH_SPEED_NUM_40G;
3158                 break;
3159         case HNS3_CFG_SPEED_50G:
3160                 *speed = ETH_SPEED_NUM_50G;
3161                 break;
3162         case HNS3_CFG_SPEED_100G:
3163                 *speed = ETH_SPEED_NUM_100G;
3164                 break;
3165         case HNS3_CFG_SPEED_200G:
3166                 *speed = ETH_SPEED_NUM_200G;
3167                 break;
3168         default:
3169                 return -EINVAL;
3170         }
3171
3172         return 0;
3173 }
3174
3175 static void
3176 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3177 {
3178         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3179         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3180         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3181         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3182         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3183 }
3184
3185 static void
3186 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3187 {
3188         struct hns3_dev_specs_0_cmd *req0;
3189
3190         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3191
3192         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3193         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3194         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3195         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3196         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3197 }
3198
3199 static int
3200 hns3_check_dev_specifications(struct hns3_hw *hw)
3201 {
3202         if (hw->rss_ind_tbl_size == 0 ||
3203             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3204                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3205                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3206                               HNS3_RSS_IND_TBL_SIZE_MAX);
3207                 return -EINVAL;
3208         }
3209
3210         return 0;
3211 }
3212
3213 static int
3214 hns3_query_dev_specifications(struct hns3_hw *hw)
3215 {
3216         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3217         int ret;
3218         int i;
3219
3220         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3221                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3222                                           true);
3223                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3224         }
3225         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3226
3227         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3228         if (ret)
3229                 return ret;
3230
3231         hns3_parse_dev_specifications(hw, desc);
3232
3233         return hns3_check_dev_specifications(hw);
3234 }
3235
3236 static int
3237 hns3_get_capability(struct hns3_hw *hw)
3238 {
3239         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3240         struct rte_pci_device *pci_dev;
3241         struct hns3_pf *pf = &hns->pf;
3242         struct rte_eth_dev *eth_dev;
3243         uint16_t device_id;
3244         uint8_t revision;
3245         int ret;
3246
3247         eth_dev = &rte_eth_devices[hw->data->port_id];
3248         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3249         device_id = pci_dev->id.device_id;
3250
3251         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3252             device_id == HNS3_DEV_ID_50GE_RDMA ||
3253             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3254             device_id == HNS3_DEV_ID_200G_RDMA)
3255                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3256
3257         /* Get PCI revision id */
3258         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3259                                   HNS3_PCI_REVISION_ID);
3260         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3261                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3262                              ret);
3263                 return -EIO;
3264         }
3265         hw->revision = revision;
3266
3267         if (revision < PCI_REVISION_ID_HIP09_A) {
3268                 hns3_set_default_dev_specifications(hw);
3269                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3270                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3271                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3272                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3273                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3274                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3275                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3276                 hw->rss_info.ipv6_sctp_offload_supported = false;
3277                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3278                 return 0;
3279         }
3280
3281         ret = hns3_query_dev_specifications(hw);
3282         if (ret) {
3283                 PMD_INIT_LOG(ERR,
3284                              "failed to query dev specifications, ret = %d",
3285                              ret);
3286                 return ret;
3287         }
3288
3289         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3290         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3291         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3292         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3293         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3294         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3295         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3296         hw->rss_info.ipv6_sctp_offload_supported = true;
3297         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3298
3299         return 0;
3300 }
3301
3302 static int
3303 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3304 {
3305         int ret;
3306
3307         switch (media_type) {
3308         case HNS3_MEDIA_TYPE_COPPER:
3309                 if (!hns3_dev_copper_supported(hw)) {
3310                         PMD_INIT_LOG(ERR,
3311                                      "Media type is copper, not supported.");
3312                         ret = -EOPNOTSUPP;
3313                 } else {
3314                         ret = 0;
3315                 }
3316                 break;
3317         case HNS3_MEDIA_TYPE_FIBER:
3318                 ret = 0;
3319                 break;
3320         case HNS3_MEDIA_TYPE_BACKPLANE:
3321                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3322                 ret = -EOPNOTSUPP;
3323                 break;
3324         default:
3325                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3326                 ret = -EINVAL;
3327                 break;
3328         }
3329
3330         return ret;
3331 }
3332
3333 static int
3334 hns3_get_board_configuration(struct hns3_hw *hw)
3335 {
3336         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3337         struct hns3_pf *pf = &hns->pf;
3338         struct hns3_cfg cfg;
3339         int ret;
3340
3341         ret = hns3_get_board_cfg(hw, &cfg);
3342         if (ret) {
3343                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3344                 return ret;
3345         }
3346
3347         ret = hns3_check_media_type(hw, cfg.media_type);
3348         if (ret)
3349                 return ret;
3350
3351         hw->mac.media_type = cfg.media_type;
3352         hw->rss_size_max = cfg.rss_size_max;
3353         hw->rss_dis_flag = false;
3354         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3355         hw->mac.phy_addr = cfg.phy_addr;
3356         hw->mac.default_addr_setted = false;
3357         hw->num_tx_desc = cfg.tqp_desc_num;
3358         hw->num_rx_desc = cfg.tqp_desc_num;
3359         hw->dcb_info.num_pg = 1;
3360         hw->dcb_info.hw_pfc_map = 0;
3361
3362         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3363         if (ret) {
3364                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3365                              cfg.default_speed, ret);
3366                 return ret;
3367         }
3368
3369         pf->tc_max = cfg.tc_num;
3370         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3371                 PMD_INIT_LOG(WARNING,
3372                              "Get TC num(%u) from flash, set TC num to 1",
3373                              pf->tc_max);
3374                 pf->tc_max = 1;
3375         }
3376
3377         /* Dev does not support DCB */
3378         if (!hns3_dev_dcb_supported(hw)) {
3379                 pf->tc_max = 1;
3380                 pf->pfc_max = 0;
3381         } else
3382                 pf->pfc_max = pf->tc_max;
3383
3384         hw->dcb_info.num_tc = 1;
3385         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3386                                      hw->tqps_num / hw->dcb_info.num_tc);
3387         hns3_set_bit(hw->hw_tc_map, 0, 1);
3388         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3389
3390         pf->wanted_umv_size = cfg.umv_space;
3391
3392         return ret;
3393 }
3394
3395 static int
3396 hns3_get_configuration(struct hns3_hw *hw)
3397 {
3398         int ret;
3399
3400         ret = hns3_query_function_status(hw);
3401         if (ret) {
3402                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3403                 return ret;
3404         }
3405
3406         /* Get device capability */
3407         ret = hns3_get_capability(hw);
3408         if (ret) {
3409                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3410                 return ret;
3411         }
3412
3413         /* Get pf resource */
3414         ret = hns3_query_pf_resource(hw);
3415         if (ret) {
3416                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3417                 return ret;
3418         }
3419
3420         ret = hns3_get_board_configuration(hw);
3421         if (ret) {
3422                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3423                 return ret;
3424         }
3425
3426         ret = hns3_query_dev_fec_info(hw);
3427         if (ret)
3428                 PMD_INIT_LOG(ERR,
3429                              "failed to query FEC information, ret = %d", ret);
3430
3431         return ret;
3432 }
3433
3434 static int
3435 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3436                       uint16_t tqp_vid, bool is_pf)
3437 {
3438         struct hns3_tqp_map_cmd *req;
3439         struct hns3_cmd_desc desc;
3440         int ret;
3441
3442         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3443
3444         req = (struct hns3_tqp_map_cmd *)desc.data;
3445         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3446         req->tqp_vf = func_id;
3447         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3448         if (!is_pf)
3449                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3450         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3451
3452         ret = hns3_cmd_send(hw, &desc, 1);
3453         if (ret)
3454                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3455
3456         return ret;
3457 }
3458
3459 static int
3460 hns3_map_tqp(struct hns3_hw *hw)
3461 {
3462         int ret;
3463         int i;
3464
3465         /*
3466          * In current version, VF is not supported when PF is driven by DPDK
3467          * driver, so we assign total tqps_num tqps allocated to this port
3468          * to PF.
3469          */
3470         for (i = 0; i < hw->total_tqps_num; i++) {
3471                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3472                 if (ret)
3473                         return ret;
3474         }
3475
3476         return 0;
3477 }
3478
3479 static int
3480 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3481 {
3482         struct hns3_config_mac_speed_dup_cmd *req;
3483         struct hns3_cmd_desc desc;
3484         int ret;
3485
3486         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3487
3488         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3489
3490         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3491
3492         switch (speed) {
3493         case ETH_SPEED_NUM_10M:
3494                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3495                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3496                 break;
3497         case ETH_SPEED_NUM_100M:
3498                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3499                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3500                 break;
3501         case ETH_SPEED_NUM_1G:
3502                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3503                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3504                 break;
3505         case ETH_SPEED_NUM_10G:
3506                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3507                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3508                 break;
3509         case ETH_SPEED_NUM_25G:
3510                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3511                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3512                 break;
3513         case ETH_SPEED_NUM_40G:
3514                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3515                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3516                 break;
3517         case ETH_SPEED_NUM_50G:
3518                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3519                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3520                 break;
3521         case ETH_SPEED_NUM_100G:
3522                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3523                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3524                 break;
3525         case ETH_SPEED_NUM_200G:
3526                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3527                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3528                 break;
3529         default:
3530                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3531                 return -EINVAL;
3532         }
3533
3534         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3535
3536         ret = hns3_cmd_send(hw, &desc, 1);
3537         if (ret)
3538                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3539
3540         return ret;
3541 }
3542
3543 static int
3544 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3545 {
3546         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3547         struct hns3_pf *pf = &hns->pf;
3548         struct hns3_priv_buf *priv;
3549         uint32_t i, total_size;
3550
3551         total_size = pf->pkt_buf_size;
3552
3553         /* alloc tx buffer for all enabled tc */
3554         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3555                 priv = &buf_alloc->priv_buf[i];
3556
3557                 if (hw->hw_tc_map & BIT(i)) {
3558                         if (total_size < pf->tx_buf_size)
3559                                 return -ENOMEM;
3560
3561                         priv->tx_buf_size = pf->tx_buf_size;
3562                 } else
3563                         priv->tx_buf_size = 0;
3564
3565                 total_size -= priv->tx_buf_size;
3566         }
3567
3568         return 0;
3569 }
3570
3571 static int
3572 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3573 {
3574 /* TX buffer size is unit by 128 byte */
3575 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3576 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3577         struct hns3_tx_buff_alloc_cmd *req;
3578         struct hns3_cmd_desc desc;
3579         uint32_t buf_size;
3580         uint32_t i;
3581         int ret;
3582
3583         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3584
3585         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3586         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3587                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3588
3589                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3590                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3591                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3592         }
3593
3594         ret = hns3_cmd_send(hw, &desc, 1);
3595         if (ret)
3596                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3597
3598         return ret;
3599 }
3600
3601 static int
3602 hns3_get_tc_num(struct hns3_hw *hw)
3603 {
3604         int cnt = 0;
3605         uint8_t i;
3606
3607         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3608                 if (hw->hw_tc_map & BIT(i))
3609                         cnt++;
3610         return cnt;
3611 }
3612
3613 static uint32_t
3614 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3615 {
3616         struct hns3_priv_buf *priv;
3617         uint32_t rx_priv = 0;
3618         int i;
3619
3620         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3621                 priv = &buf_alloc->priv_buf[i];
3622                 if (priv->enable)
3623                         rx_priv += priv->buf_size;
3624         }
3625         return rx_priv;
3626 }
3627
3628 static uint32_t
3629 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3630 {
3631         uint32_t total_tx_size = 0;
3632         uint32_t i;
3633
3634         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3635                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3636
3637         return total_tx_size;
3638 }
3639
3640 /* Get the number of pfc enabled TCs, which have private buffer */
3641 static int
3642 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3643 {
3644         struct hns3_priv_buf *priv;
3645         int cnt = 0;
3646         uint8_t i;
3647
3648         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3649                 priv = &buf_alloc->priv_buf[i];
3650                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3651                         cnt++;
3652         }
3653
3654         return cnt;
3655 }
3656
3657 /* Get the number of pfc disabled TCs, which have private buffer */
3658 static int
3659 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3660                          struct hns3_pkt_buf_alloc *buf_alloc)
3661 {
3662         struct hns3_priv_buf *priv;
3663         int cnt = 0;
3664         uint8_t i;
3665
3666         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3667                 priv = &buf_alloc->priv_buf[i];
3668                 if (hw->hw_tc_map & BIT(i) &&
3669                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3670                         cnt++;
3671         }
3672
3673         return cnt;
3674 }
3675
3676 static bool
3677 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3678                   uint32_t rx_all)
3679 {
3680         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3681         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3682         struct hns3_pf *pf = &hns->pf;
3683         uint32_t shared_buf, aligned_mps;
3684         uint32_t rx_priv;
3685         uint8_t tc_num;
3686         uint8_t i;
3687
3688         tc_num = hns3_get_tc_num(hw);
3689         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3690
3691         if (hns3_dev_dcb_supported(hw))
3692                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3693                                         pf->dv_buf_size;
3694         else
3695                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3696                                         + pf->dv_buf_size;
3697
3698         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3699         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3700                              HNS3_BUF_SIZE_UNIT);
3701
3702         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3703         if (rx_all < rx_priv + shared_std)
3704                 return false;
3705
3706         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3707         buf_alloc->s_buf.buf_size = shared_buf;
3708         if (hns3_dev_dcb_supported(hw)) {
3709                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3710                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3711                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3712                                   HNS3_BUF_SIZE_UNIT);
3713         } else {
3714                 buf_alloc->s_buf.self.high =
3715                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3716                 buf_alloc->s_buf.self.low = aligned_mps;
3717         }
3718
3719         if (hns3_dev_dcb_supported(hw)) {
3720                 hi_thrd = shared_buf - pf->dv_buf_size;
3721
3722                 if (tc_num <= NEED_RESERVE_TC_NUM)
3723                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3724                                   BUF_MAX_PERCENT;
3725
3726                 if (tc_num)
3727                         hi_thrd = hi_thrd / tc_num;
3728
3729                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3730                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3731                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3732         } else {
3733                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3734                 lo_thrd = aligned_mps;
3735         }
3736
3737         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3738                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3739                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3740         }
3741
3742         return true;
3743 }
3744
3745 static bool
3746 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3747                      struct hns3_pkt_buf_alloc *buf_alloc)
3748 {
3749         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3750         struct hns3_pf *pf = &hns->pf;
3751         struct hns3_priv_buf *priv;
3752         uint32_t aligned_mps;
3753         uint32_t rx_all;
3754         uint8_t i;
3755
3756         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3757         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3758
3759         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3760                 priv = &buf_alloc->priv_buf[i];
3761
3762                 priv->enable = 0;
3763                 priv->wl.low = 0;
3764                 priv->wl.high = 0;
3765                 priv->buf_size = 0;
3766
3767                 if (!(hw->hw_tc_map & BIT(i)))
3768                         continue;
3769
3770                 priv->enable = 1;
3771                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3772                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3773                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3774                                                 HNS3_BUF_SIZE_UNIT);
3775                 } else {
3776                         priv->wl.low = 0;
3777                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3778                                         aligned_mps;
3779                 }
3780
3781                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3782         }
3783
3784         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3785 }
3786
3787 static bool
3788 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3789                              struct hns3_pkt_buf_alloc *buf_alloc)
3790 {
3791         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3792         struct hns3_pf *pf = &hns->pf;
3793         struct hns3_priv_buf *priv;
3794         int no_pfc_priv_num;
3795         uint32_t rx_all;
3796         uint8_t mask;
3797         int i;
3798
3799         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3800         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3801
3802         /* let the last to be cleared first */
3803         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3804                 priv = &buf_alloc->priv_buf[i];
3805                 mask = BIT((uint8_t)i);
3806
3807                 if (hw->hw_tc_map & mask &&
3808                     !(hw->dcb_info.hw_pfc_map & mask)) {
3809                         /* Clear the no pfc TC private buffer */
3810                         priv->wl.low = 0;
3811                         priv->wl.high = 0;
3812                         priv->buf_size = 0;
3813                         priv->enable = 0;
3814                         no_pfc_priv_num--;
3815                 }
3816
3817                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3818                     no_pfc_priv_num == 0)
3819                         break;
3820         }
3821
3822         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3823 }
3824
3825 static bool
3826 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3827                            struct hns3_pkt_buf_alloc *buf_alloc)
3828 {
3829         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3830         struct hns3_pf *pf = &hns->pf;
3831         struct hns3_priv_buf *priv;
3832         uint32_t rx_all;
3833         int pfc_priv_num;
3834         uint8_t mask;
3835         int i;
3836
3837         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3838         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3839
3840         /* let the last to be cleared first */
3841         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3842                 priv = &buf_alloc->priv_buf[i];
3843                 mask = BIT((uint8_t)i);
3844                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3845                         /* Reduce the number of pfc TC with private buffer */
3846                         priv->wl.low = 0;
3847                         priv->enable = 0;
3848                         priv->wl.high = 0;
3849                         priv->buf_size = 0;
3850                         pfc_priv_num--;
3851                 }
3852                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3853                     pfc_priv_num == 0)
3854                         break;
3855         }
3856
3857         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3858 }
3859
3860 static bool
3861 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3862                           struct hns3_pkt_buf_alloc *buf_alloc)
3863 {
3864 #define COMPENSATE_BUFFER       0x3C00
3865 #define COMPENSATE_HALF_MPS_NUM 5
3866 #define PRIV_WL_GAP             0x1800
3867         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3868         struct hns3_pf *pf = &hns->pf;
3869         uint32_t tc_num = hns3_get_tc_num(hw);
3870         uint32_t half_mps = pf->mps >> 1;
3871         struct hns3_priv_buf *priv;
3872         uint32_t min_rx_priv;
3873         uint32_t rx_priv;
3874         uint8_t i;
3875
3876         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3877         if (tc_num)
3878                 rx_priv = rx_priv / tc_num;
3879
3880         if (tc_num <= NEED_RESERVE_TC_NUM)
3881                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3882
3883         /*
3884          * Minimum value of private buffer in rx direction (min_rx_priv) is
3885          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3886          * buffer if rx_priv is greater than min_rx_priv.
3887          */
3888         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3889                         COMPENSATE_HALF_MPS_NUM * half_mps;
3890         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3891         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3892
3893         if (rx_priv < min_rx_priv)
3894                 return false;
3895
3896         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3897                 priv = &buf_alloc->priv_buf[i];
3898                 priv->enable = 0;
3899                 priv->wl.low = 0;
3900                 priv->wl.high = 0;
3901                 priv->buf_size = 0;
3902
3903                 if (!(hw->hw_tc_map & BIT(i)))
3904                         continue;
3905
3906                 priv->enable = 1;
3907                 priv->buf_size = rx_priv;
3908                 priv->wl.high = rx_priv - pf->dv_buf_size;
3909                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3910         }
3911
3912         buf_alloc->s_buf.buf_size = 0;
3913
3914         return true;
3915 }
3916
3917 /*
3918  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3919  * @hw: pointer to struct hns3_hw
3920  * @buf_alloc: pointer to buffer calculation data
3921  * @return: 0: calculate sucessful, negative: fail
3922  */
3923 static int
3924 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3925 {
3926         /* When DCB is not supported, rx private buffer is not allocated. */
3927         if (!hns3_dev_dcb_supported(hw)) {
3928                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3929                 struct hns3_pf *pf = &hns->pf;
3930                 uint32_t rx_all = pf->pkt_buf_size;
3931
3932                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3933                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3934                         return -ENOMEM;
3935
3936                 return 0;
3937         }
3938
3939         /*
3940          * Try to allocate privated packet buffer for all TCs without share
3941          * buffer.
3942          */
3943         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3944                 return 0;
3945
3946         /*
3947          * Try to allocate privated packet buffer for all TCs with share
3948          * buffer.
3949          */
3950         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3951                 return 0;
3952
3953         /*
3954          * For different application scenes, the enabled port number, TC number
3955          * and no_drop TC number are different. In order to obtain the better
3956          * performance, software could allocate the buffer size and configure
3957          * the waterline by tring to decrease the private buffer size according
3958          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3959          * enabled tc.
3960          */
3961         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3962                 return 0;
3963
3964         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3965                 return 0;
3966
3967         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3968                 return 0;
3969
3970         return -ENOMEM;
3971 }
3972
3973 static int
3974 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3975 {
3976         struct hns3_rx_priv_buff_cmd *req;
3977         struct hns3_cmd_desc desc;
3978         uint32_t buf_size;
3979         int ret;
3980         int i;
3981
3982         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3983         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3984
3985         /* Alloc private buffer TCs */
3986         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3987                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3988
3989                 req->buf_num[i] =
3990                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3991                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3992         }
3993
3994         buf_size = buf_alloc->s_buf.buf_size;
3995         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3996                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3997
3998         ret = hns3_cmd_send(hw, &desc, 1);
3999         if (ret)
4000                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4001
4002         return ret;
4003 }
4004
4005 static int
4006 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4007 {
4008 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4009         struct hns3_rx_priv_wl_buf *req;
4010         struct hns3_priv_buf *priv;
4011         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4012         int i, j;
4013         int ret;
4014
4015         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4016                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4017                                           false);
4018                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4019
4020                 /* The first descriptor set the NEXT bit to 1 */
4021                 if (i == 0)
4022                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4023                 else
4024                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4025
4026                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4027                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4028
4029                         priv = &buf_alloc->priv_buf[idx];
4030                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4031                                                         HNS3_BUF_UNIT_S);
4032                         req->tc_wl[j].high |=
4033                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4034                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4035                                                         HNS3_BUF_UNIT_S);
4036                         req->tc_wl[j].low |=
4037                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4038                 }
4039         }
4040
4041         /* Send 2 descriptor at one time */
4042         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4043         if (ret)
4044                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4045                              ret);
4046         return ret;
4047 }
4048
4049 static int
4050 hns3_common_thrd_config(struct hns3_hw *hw,
4051                         struct hns3_pkt_buf_alloc *buf_alloc)
4052 {
4053 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4054         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4055         struct hns3_rx_com_thrd *req;
4056         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4057         struct hns3_tc_thrd *tc;
4058         int tc_idx;
4059         int i, j;
4060         int ret;
4061
4062         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4063                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4064                                           false);
4065                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4066
4067                 /* The first descriptor set the NEXT bit to 1 */
4068                 if (i == 0)
4069                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4070                 else
4071                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4072
4073                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4074                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4075                         tc = &s_buf->tc_thrd[tc_idx];
4076
4077                         req->com_thrd[j].high =
4078                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4079                         req->com_thrd[j].high |=
4080                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4081                         req->com_thrd[j].low =
4082                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4083                         req->com_thrd[j].low |=
4084                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4085                 }
4086         }
4087
4088         /* Send 2 descriptors at one time */
4089         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4090         if (ret)
4091                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4092
4093         return ret;
4094 }
4095
4096 static int
4097 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4098 {
4099         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4100         struct hns3_rx_com_wl *req;
4101         struct hns3_cmd_desc desc;
4102         int ret;
4103
4104         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4105
4106         req = (struct hns3_rx_com_wl *)desc.data;
4107         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4108         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4109
4110         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4111         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4112
4113         ret = hns3_cmd_send(hw, &desc, 1);
4114         if (ret)
4115                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4116
4117         return ret;
4118 }
4119
4120 int
4121 hns3_buffer_alloc(struct hns3_hw *hw)
4122 {
4123         struct hns3_pkt_buf_alloc pkt_buf;
4124         int ret;
4125
4126         memset(&pkt_buf, 0, sizeof(pkt_buf));
4127         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4128         if (ret) {
4129                 PMD_INIT_LOG(ERR,
4130                              "could not calc tx buffer size for all TCs %d",
4131                              ret);
4132                 return ret;
4133         }
4134
4135         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4136         if (ret) {
4137                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4138                 return ret;
4139         }
4140
4141         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4142         if (ret) {
4143                 PMD_INIT_LOG(ERR,
4144                              "could not calc rx priv buffer size for all TCs %d",
4145                              ret);
4146                 return ret;
4147         }
4148
4149         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4150         if (ret) {
4151                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4152                 return ret;
4153         }
4154
4155         if (hns3_dev_dcb_supported(hw)) {
4156                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4157                 if (ret) {
4158                         PMD_INIT_LOG(ERR,
4159                                      "could not configure rx private waterline %d",
4160                                      ret);
4161                         return ret;
4162                 }
4163
4164                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4165                 if (ret) {
4166                         PMD_INIT_LOG(ERR,
4167                                      "could not configure common threshold %d",
4168                                      ret);
4169                         return ret;
4170                 }
4171         }
4172
4173         ret = hns3_common_wl_config(hw, &pkt_buf);
4174         if (ret)
4175                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4176                              ret);
4177
4178         return ret;
4179 }
4180
4181 static int
4182 hns3_mac_init(struct hns3_hw *hw)
4183 {
4184         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4185         struct hns3_mac *mac = &hw->mac;
4186         struct hns3_pf *pf = &hns->pf;
4187         int ret;
4188
4189         pf->support_sfp_query = true;
4190         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4191         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4192         if (ret) {
4193                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4194                 return ret;
4195         }
4196
4197         mac->link_status = ETH_LINK_DOWN;
4198
4199         return hns3_config_mtu(hw, pf->mps);
4200 }
4201
4202 static int
4203 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4204 {
4205 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4206 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4207 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4208 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4209         int return_status;
4210
4211         if (cmdq_resp) {
4212                 PMD_INIT_LOG(ERR,
4213                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4214                              cmdq_resp);
4215                 return -EIO;
4216         }
4217
4218         switch (resp_code) {
4219         case HNS3_ETHERTYPE_SUCCESS_ADD:
4220         case HNS3_ETHERTYPE_ALREADY_ADD:
4221                 return_status = 0;
4222                 break;
4223         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4224                 PMD_INIT_LOG(ERR,
4225                              "add mac ethertype failed for manager table overflow.");
4226                 return_status = -EIO;
4227                 break;
4228         case HNS3_ETHERTYPE_KEY_CONFLICT:
4229                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4230                 return_status = -EIO;
4231                 break;
4232         default:
4233                 PMD_INIT_LOG(ERR,
4234                              "add mac ethertype failed for undefined, code=%u.",
4235                              resp_code);
4236                 return_status = -EIO;
4237                 break;
4238         }
4239
4240         return return_status;
4241 }
4242
4243 static int
4244 hns3_add_mgr_tbl(struct hns3_hw *hw,
4245                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4246 {
4247         struct hns3_cmd_desc desc;
4248         uint8_t resp_code;
4249         uint16_t retval;
4250         int ret;
4251
4252         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4253         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4254
4255         ret = hns3_cmd_send(hw, &desc, 1);
4256         if (ret) {
4257                 PMD_INIT_LOG(ERR,
4258                              "add mac ethertype failed for cmd_send, ret =%d.",
4259                              ret);
4260                 return ret;
4261         }
4262
4263         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4264         retval = rte_le_to_cpu_16(desc.retval);
4265
4266         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4267 }
4268
4269 static void
4270 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4271                      int *table_item_num)
4272 {
4273         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4274
4275         /*
4276          * In current version, we add one item in management table as below:
4277          * 0x0180C200000E -- LLDP MC address
4278          */
4279         tbl = mgr_table;
4280         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4281         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4282         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4283         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4284         tbl->i_port_bitmap = 0x1;
4285         *table_item_num = 1;
4286 }
4287
4288 static int
4289 hns3_init_mgr_tbl(struct hns3_hw *hw)
4290 {
4291 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4292         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4293         int table_item_num;
4294         int ret;
4295         int i;
4296
4297         memset(mgr_table, 0, sizeof(mgr_table));
4298         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4299         for (i = 0; i < table_item_num; i++) {
4300                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4301                 if (ret) {
4302                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4303                                      ret);
4304                         return ret;
4305                 }
4306         }
4307
4308         return 0;
4309 }
4310
4311 static void
4312 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4313                         bool en_mc, bool en_bc, int vport_id)
4314 {
4315         if (!param)
4316                 return;
4317
4318         memset(param, 0, sizeof(struct hns3_promisc_param));
4319         if (en_uc)
4320                 param->enable = HNS3_PROMISC_EN_UC;
4321         if (en_mc)
4322                 param->enable |= HNS3_PROMISC_EN_MC;
4323         if (en_bc)
4324                 param->enable |= HNS3_PROMISC_EN_BC;
4325         param->vf_id = vport_id;
4326 }
4327
4328 static int
4329 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4330 {
4331         struct hns3_promisc_cfg_cmd *req;
4332         struct hns3_cmd_desc desc;
4333         int ret;
4334
4335         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4336
4337         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4338         req->vf_id = param->vf_id;
4339         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4340             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4341
4342         ret = hns3_cmd_send(hw, &desc, 1);
4343         if (ret)
4344                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4345
4346         return ret;
4347 }
4348
4349 static int
4350 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4351 {
4352         struct hns3_promisc_param param;
4353         bool en_bc_pmc = true;
4354         uint8_t vf_id;
4355
4356         /*
4357          * In current version VF is not supported when PF is driven by DPDK
4358          * driver, just need to configure parameters for PF vport.
4359          */
4360         vf_id = HNS3_PF_FUNC_ID;
4361
4362         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4363         return hns3_cmd_set_promisc_mode(hw, &param);
4364 }
4365
4366 static int
4367 hns3_promisc_init(struct hns3_hw *hw)
4368 {
4369         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4370         struct hns3_pf *pf = &hns->pf;
4371         struct hns3_promisc_param param;
4372         uint16_t func_id;
4373         int ret;
4374
4375         ret = hns3_set_promisc_mode(hw, false, false);
4376         if (ret) {
4377                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4378                 return ret;
4379         }
4380
4381         /*
4382          * In current version VFs are not supported when PF is driven by DPDK
4383          * driver. After PF has been taken over by DPDK, the original VF will
4384          * be invalid. So, there is a possibility of entry residues. It should
4385          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4386          * during init.
4387          */
4388         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4389                 hns3_promisc_param_init(&param, false, false, false, func_id);
4390                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4391                 if (ret) {
4392                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4393                                         " ret = %d", func_id, ret);
4394                         return ret;
4395                 }
4396         }
4397
4398         return 0;
4399 }
4400
4401 static void
4402 hns3_promisc_uninit(struct hns3_hw *hw)
4403 {
4404         struct hns3_promisc_param param;
4405         uint16_t func_id;
4406         int ret;
4407
4408         func_id = HNS3_PF_FUNC_ID;
4409
4410         /*
4411          * In current version VFs are not supported when PF is driven by
4412          * DPDK driver, and VFs' promisc mode status has been cleared during
4413          * init and their status will not change. So just clear PF's promisc
4414          * mode status during uninit.
4415          */
4416         hns3_promisc_param_init(&param, false, false, false, func_id);
4417         ret = hns3_cmd_set_promisc_mode(hw, &param);
4418         if (ret)
4419                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4420                                 " uninit, ret = %d", ret);
4421 }
4422
4423 static int
4424 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4425 {
4426         bool allmulti = dev->data->all_multicast ? true : false;
4427         struct hns3_adapter *hns = dev->data->dev_private;
4428         struct hns3_hw *hw = &hns->hw;
4429         uint64_t offloads;
4430         int err;
4431         int ret;
4432
4433         rte_spinlock_lock(&hw->lock);
4434         ret = hns3_set_promisc_mode(hw, true, true);
4435         if (ret) {
4436                 rte_spinlock_unlock(&hw->lock);
4437                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4438                          ret);
4439                 return ret;
4440         }
4441
4442         /*
4443          * When promiscuous mode was enabled, disable the vlan filter to let
4444          * all packets coming in in the receiving direction.
4445          */
4446         offloads = dev->data->dev_conf.rxmode.offloads;
4447         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4448                 ret = hns3_enable_vlan_filter(hns, false);
4449                 if (ret) {
4450                         hns3_err(hw, "failed to enable promiscuous mode due to "
4451                                      "failure to disable vlan filter, ret = %d",
4452                                  ret);
4453                         err = hns3_set_promisc_mode(hw, false, allmulti);
4454                         if (err)
4455                                 hns3_err(hw, "failed to restore promiscuous "
4456                                          "status after disable vlan filter "
4457                                          "failed during enabling promiscuous "
4458                                          "mode, ret = %d", ret);
4459                 }
4460         }
4461
4462         rte_spinlock_unlock(&hw->lock);
4463
4464         return ret;
4465 }
4466
4467 static int
4468 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4469 {
4470         bool allmulti = dev->data->all_multicast ? true : false;
4471         struct hns3_adapter *hns = dev->data->dev_private;
4472         struct hns3_hw *hw = &hns->hw;
4473         uint64_t offloads;
4474         int err;
4475         int ret;
4476
4477         /* If now in all_multicast mode, must remain in all_multicast mode. */
4478         rte_spinlock_lock(&hw->lock);
4479         ret = hns3_set_promisc_mode(hw, false, allmulti);
4480         if (ret) {
4481                 rte_spinlock_unlock(&hw->lock);
4482                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4483                          ret);
4484                 return ret;
4485         }
4486         /* when promiscuous mode was disabled, restore the vlan filter status */
4487         offloads = dev->data->dev_conf.rxmode.offloads;
4488         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4489                 ret = hns3_enable_vlan_filter(hns, true);
4490                 if (ret) {
4491                         hns3_err(hw, "failed to disable promiscuous mode due to"
4492                                  " failure to restore vlan filter, ret = %d",
4493                                  ret);
4494                         err = hns3_set_promisc_mode(hw, true, true);
4495                         if (err)
4496                                 hns3_err(hw, "failed to restore promiscuous "
4497                                          "status after enabling vlan filter "
4498                                          "failed during disabling promiscuous "
4499                                          "mode, ret = %d", ret);
4500                 }
4501         }
4502         rte_spinlock_unlock(&hw->lock);
4503
4504         return ret;
4505 }
4506
4507 static int
4508 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4509 {
4510         struct hns3_adapter *hns = dev->data->dev_private;
4511         struct hns3_hw *hw = &hns->hw;
4512         int ret;
4513
4514         if (dev->data->promiscuous)
4515                 return 0;
4516
4517         rte_spinlock_lock(&hw->lock);
4518         ret = hns3_set_promisc_mode(hw, false, true);
4519         rte_spinlock_unlock(&hw->lock);
4520         if (ret)
4521                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4522                          ret);
4523
4524         return ret;
4525 }
4526
4527 static int
4528 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4529 {
4530         struct hns3_adapter *hns = dev->data->dev_private;
4531         struct hns3_hw *hw = &hns->hw;
4532         int ret;
4533
4534         /* If now in promiscuous mode, must remain in all_multicast mode. */
4535         if (dev->data->promiscuous)
4536                 return 0;
4537
4538         rte_spinlock_lock(&hw->lock);
4539         ret = hns3_set_promisc_mode(hw, false, false);
4540         rte_spinlock_unlock(&hw->lock);
4541         if (ret)
4542                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4543                          ret);
4544
4545         return ret;
4546 }
4547
4548 static int
4549 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4550 {
4551         struct hns3_hw *hw = &hns->hw;
4552         bool allmulti = hw->data->all_multicast ? true : false;
4553         int ret;
4554
4555         if (hw->data->promiscuous) {
4556                 ret = hns3_set_promisc_mode(hw, true, true);
4557                 if (ret)
4558                         hns3_err(hw, "failed to restore promiscuous mode, "
4559                                  "ret = %d", ret);
4560                 return ret;
4561         }
4562
4563         ret = hns3_set_promisc_mode(hw, false, allmulti);
4564         if (ret)
4565                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4566                          ret);
4567         return ret;
4568 }
4569
4570 static int
4571 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4572 {
4573         struct hns3_sfp_info_cmd *resp;
4574         struct hns3_cmd_desc desc;
4575         int ret;
4576
4577         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4578         resp = (struct hns3_sfp_info_cmd *)desc.data;
4579         resp->query_type = HNS3_ACTIVE_QUERY;
4580
4581         ret = hns3_cmd_send(hw, &desc, 1);
4582         if (ret == -EOPNOTSUPP) {
4583                 hns3_warn(hw, "firmware does not support get SFP info,"
4584                           " ret = %d.", ret);
4585                 return ret;
4586         } else if (ret) {
4587                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4588                 return ret;
4589         }
4590
4591         /*
4592          * In some case, the speed of MAC obtained from firmware may be 0, it
4593          * shouldn't be set to mac->speed.
4594          */
4595         if (!rte_le_to_cpu_32(resp->sfp_speed))
4596                 return 0;
4597
4598         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4599         /*
4600          * if resp->supported_speed is 0, it means it's an old version
4601          * firmware, do not update these params.
4602          */
4603         if (resp->supported_speed) {
4604                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4605                 mac_info->supported_speed =
4606                                         rte_le_to_cpu_32(resp->supported_speed);
4607                 mac_info->support_autoneg = resp->autoneg_ability;
4608                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4609                                         : ETH_LINK_AUTONEG;
4610         } else {
4611                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4612         }
4613
4614         return 0;
4615 }
4616
4617 static uint8_t
4618 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4619 {
4620         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4621                 duplex = ETH_LINK_FULL_DUPLEX;
4622
4623         return duplex;
4624 }
4625
4626 static int
4627 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4628 {
4629         struct hns3_mac *mac = &hw->mac;
4630         int ret;
4631
4632         duplex = hns3_check_speed_dup(duplex, speed);
4633         if (mac->link_speed == speed && mac->link_duplex == duplex)
4634                 return 0;
4635
4636         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4637         if (ret)
4638                 return ret;
4639
4640         ret = hns3_port_shaper_update(hw, speed);
4641         if (ret)
4642                 return ret;
4643
4644         mac->link_speed = speed;
4645         mac->link_duplex = duplex;
4646
4647         return 0;
4648 }
4649
4650 static int
4651 hns3_update_fiber_link_info(struct hns3_hw *hw)
4652 {
4653         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4654         struct hns3_mac *mac = &hw->mac;
4655         struct hns3_mac mac_info;
4656         int ret;
4657
4658         /* If firmware do not support get SFP/qSFP speed, return directly */
4659         if (!pf->support_sfp_query)
4660                 return 0;
4661
4662         memset(&mac_info, 0, sizeof(struct hns3_mac));
4663         ret = hns3_get_sfp_info(hw, &mac_info);
4664         if (ret == -EOPNOTSUPP) {
4665                 pf->support_sfp_query = false;
4666                 return ret;
4667         } else if (ret)
4668                 return ret;
4669
4670         /* Do nothing if no SFP */
4671         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4672                 return 0;
4673
4674         /*
4675          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4676          * to reconfigure the speed of MAC. Otherwise, it indicates
4677          * that the current firmware only supports to obtain the
4678          * speed of the SFP, and the speed of MAC needs to reconfigure.
4679          */
4680         mac->query_type = mac_info.query_type;
4681         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4682                 if (mac_info.link_speed != mac->link_speed) {
4683                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4684                         if (ret)
4685                                 return ret;
4686                 }
4687
4688                 mac->link_speed = mac_info.link_speed;
4689                 mac->supported_speed = mac_info.supported_speed;
4690                 mac->support_autoneg = mac_info.support_autoneg;
4691                 mac->link_autoneg = mac_info.link_autoneg;
4692
4693                 return 0;
4694         }
4695
4696         /* Config full duplex for SFP */
4697         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4698                                       ETH_LINK_FULL_DUPLEX);
4699 }
4700
4701 static void
4702 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4703 {
4704 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4705
4706         struct hns3_phy_params_bd0_cmd *req;
4707         uint32_t supported;
4708
4709         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4710         mac->link_speed = rte_le_to_cpu_32(req->speed);
4711         mac->link_duplex = hns3_get_bit(req->duplex,
4712                                            HNS3_PHY_DUPLEX_CFG_B);
4713         mac->link_autoneg = hns3_get_bit(req->autoneg,
4714                                            HNS3_PHY_AUTONEG_CFG_B);
4715         mac->advertising = rte_le_to_cpu_32(req->advertising);
4716         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4717         supported = rte_le_to_cpu_32(req->supported);
4718         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4719         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4720 }
4721
4722 static int
4723 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4724 {
4725         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4726         uint16_t i;
4727         int ret;
4728
4729         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4730                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4731                                           true);
4732                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4733         }
4734         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4735
4736         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4737         if (ret) {
4738                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4739                 return ret;
4740         }
4741
4742         hns3_parse_copper_phy_params(desc, mac);
4743
4744         return 0;
4745 }
4746
4747 static int
4748 hns3_update_copper_link_info(struct hns3_hw *hw)
4749 {
4750         struct hns3_mac *mac = &hw->mac;
4751         struct hns3_mac mac_info;
4752         int ret;
4753
4754         memset(&mac_info, 0, sizeof(struct hns3_mac));
4755         ret = hns3_get_copper_phy_params(hw, &mac_info);
4756         if (ret)
4757                 return ret;
4758
4759         if (mac_info.link_speed != mac->link_speed) {
4760                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4761                 if (ret)
4762                         return ret;
4763         }
4764
4765         mac->link_speed = mac_info.link_speed;
4766         mac->link_duplex = mac_info.link_duplex;
4767         mac->link_autoneg = mac_info.link_autoneg;
4768         mac->supported_speed = mac_info.supported_speed;
4769         mac->advertising = mac_info.advertising;
4770         mac->lp_advertising = mac_info.lp_advertising;
4771         mac->support_autoneg = mac_info.support_autoneg;
4772
4773         return 0;
4774 }
4775
4776 static int
4777 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4778 {
4779         struct hns3_adapter *hns = eth_dev->data->dev_private;
4780         struct hns3_hw *hw = &hns->hw;
4781         int ret = 0;
4782
4783         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4784                 ret = hns3_update_copper_link_info(hw);
4785         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4786                 ret = hns3_update_fiber_link_info(hw);
4787
4788         return ret;
4789 }
4790
4791 static int
4792 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4793 {
4794         struct hns3_config_mac_mode_cmd *req;
4795         struct hns3_cmd_desc desc;
4796         uint32_t loop_en = 0;
4797         uint8_t val = 0;
4798         int ret;
4799
4800         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4801
4802         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4803         if (enable)
4804                 val = 1;
4805         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4806         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4807         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4808         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4809         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4810         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4811         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4812         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4813         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4814         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4815
4816         /*
4817          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4818          * when receiving frames. Otherwise, CRC will be stripped.
4819          */
4820         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4821                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4822         else
4823                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4824         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4825         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4826         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4827         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4828
4829         ret = hns3_cmd_send(hw, &desc, 1);
4830         if (ret)
4831                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4832
4833         return ret;
4834 }
4835
4836 static int
4837 hns3_get_mac_link_status(struct hns3_hw *hw)
4838 {
4839         struct hns3_link_status_cmd *req;
4840         struct hns3_cmd_desc desc;
4841         int link_status;
4842         int ret;
4843
4844         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4845         ret = hns3_cmd_send(hw, &desc, 1);
4846         if (ret) {
4847                 hns3_err(hw, "get link status cmd failed %d", ret);
4848                 return ETH_LINK_DOWN;
4849         }
4850
4851         req = (struct hns3_link_status_cmd *)desc.data;
4852         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4853
4854         return !!link_status;
4855 }
4856
4857 static bool
4858 hns3_update_link_status(struct hns3_hw *hw)
4859 {
4860         int state;
4861
4862         state = hns3_get_mac_link_status(hw);
4863         if (state != hw->mac.link_status) {
4864                 hw->mac.link_status = state;
4865                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4866                 hns3_config_mac_tnl_int(hw,
4867                                         state == ETH_LINK_UP ? true : false);
4868                 return true;
4869         }
4870
4871         return false;
4872 }
4873
4874 void
4875 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4876 {
4877         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4878         struct rte_eth_link new_link;
4879         int ret;
4880
4881         if (query)
4882                 hns3_update_port_link_info(dev);
4883
4884         memset(&new_link, 0, sizeof(new_link));
4885         hns3_setup_linkstatus(dev, &new_link);
4886
4887         ret = rte_eth_linkstatus_set(dev, &new_link);
4888         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4889                 hns3_start_report_lse(dev);
4890 }
4891
4892 static void
4893 hns3_service_handler(void *param)
4894 {
4895         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4896         struct hns3_adapter *hns = eth_dev->data->dev_private;
4897         struct hns3_hw *hw = &hns->hw;
4898
4899         if (!hns3_is_reset_pending(hns))
4900                 hns3_update_linkstatus_and_event(hw, true);
4901         else
4902                 hns3_warn(hw, "Cancel the query when reset is pending");
4903
4904         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4905 }
4906
4907 static int
4908 hns3_init_hardware(struct hns3_adapter *hns)
4909 {
4910         struct hns3_hw *hw = &hns->hw;
4911         int ret;
4912
4913         ret = hns3_map_tqp(hw);
4914         if (ret) {
4915                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4916                 return ret;
4917         }
4918
4919         ret = hns3_init_umv_space(hw);
4920         if (ret) {
4921                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4922                 return ret;
4923         }
4924
4925         ret = hns3_mac_init(hw);
4926         if (ret) {
4927                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4928                 goto err_mac_init;
4929         }
4930
4931         ret = hns3_init_mgr_tbl(hw);
4932         if (ret) {
4933                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4934                 goto err_mac_init;
4935         }
4936
4937         ret = hns3_promisc_init(hw);
4938         if (ret) {
4939                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4940                              ret);
4941                 goto err_mac_init;
4942         }
4943
4944         ret = hns3_init_vlan_config(hns);
4945         if (ret) {
4946                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4947                 goto err_mac_init;
4948         }
4949
4950         ret = hns3_dcb_init(hw);
4951         if (ret) {
4952                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4953                 goto err_mac_init;
4954         }
4955
4956         ret = hns3_init_fd_config(hns);
4957         if (ret) {
4958                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4959                 goto err_mac_init;
4960         }
4961
4962         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4963         if (ret) {
4964                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4965                 goto err_mac_init;
4966         }
4967
4968         ret = hns3_config_gro(hw, false);
4969         if (ret) {
4970                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4971                 goto err_mac_init;
4972         }
4973
4974         /*
4975          * In the initialization clearing the all hardware mapping relationship
4976          * configurations between queues and interrupt vectors is needed, so
4977          * some error caused by the residual configurations, such as the
4978          * unexpected interrupt, can be avoid.
4979          */
4980         ret = hns3_init_ring_with_vector(hw);
4981         if (ret) {
4982                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4983                 goto err_mac_init;
4984         }
4985
4986         return 0;
4987
4988 err_mac_init:
4989         hns3_uninit_umv_space(hw);
4990         return ret;
4991 }
4992
4993 static int
4994 hns3_clear_hw(struct hns3_hw *hw)
4995 {
4996         struct hns3_cmd_desc desc;
4997         int ret;
4998
4999         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5000
5001         ret = hns3_cmd_send(hw, &desc, 1);
5002         if (ret && ret != -EOPNOTSUPP)
5003                 return ret;
5004
5005         return 0;
5006 }
5007
5008 static void
5009 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5010 {
5011         uint32_t val;
5012
5013         /*
5014          * The new firmware support report more hardware error types by
5015          * msix mode. These errors are defined as RAS errors in hardware
5016          * and belong to a different type from the MSI-x errors processed
5017          * by the network driver.
5018          *
5019          * Network driver should open the new error report on initialition
5020          */
5021         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5022         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5023         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5024 }
5025
5026 static uint32_t
5027 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5028 {
5029         struct hns3_mac *mac = &hw->mac;
5030
5031         switch (mac->link_speed) {
5032         case ETH_SPEED_NUM_1G:
5033                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5034         case ETH_SPEED_NUM_10G:
5035                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5036         case ETH_SPEED_NUM_25G:
5037                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5038         case ETH_SPEED_NUM_40G:
5039                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5040         case ETH_SPEED_NUM_50G:
5041                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5042         case ETH_SPEED_NUM_100G:
5043                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5044         case ETH_SPEED_NUM_200G:
5045                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5046         default:
5047                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5048                 return 0;
5049         }
5050 }
5051
5052 /*
5053  * Validity of supported_speed for firber and copper media type can be
5054  * guaranteed by the following policy:
5055  * Copper:
5056  *       Although the initialization of the phy in the firmware may not be
5057  *       completed, the firmware can guarantees that the supported_speed is
5058  *       an valid value.
5059  * Firber:
5060  *       If the version of firmware supports the acitive query way of the
5061  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5062  *       through it. If unsupported, use the SFP's speed as the value of the
5063  *       supported_speed.
5064  */
5065 static int
5066 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5067 {
5068         struct hns3_adapter *hns = eth_dev->data->dev_private;
5069         struct hns3_hw *hw = &hns->hw;
5070         struct hns3_mac *mac = &hw->mac;
5071         int ret;
5072
5073         ret = hns3_update_link_info(eth_dev);
5074         if (ret)
5075                 return ret;
5076
5077         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5078                 /*
5079                  * Some firmware does not support the report of supported_speed,
5080                  * and only report the effective speed of SFP. In this case, it
5081                  * is necessary to use the SFP's speed as the supported_speed.
5082                  */
5083                 if (mac->supported_speed == 0)
5084                         mac->supported_speed =
5085                                 hns3_set_firber_default_support_speed(hw);
5086         }
5087
5088         return 0;
5089 }
5090
5091 static void
5092 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5093 {
5094         struct hns3_mac *mac = &hns->hw.mac;
5095
5096         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5097                 hns->pf.support_fc_autoneg = true;
5098                 return;
5099         }
5100
5101         /*
5102          * Flow control auto-negotiation requires the cooperation of the driver
5103          * and firmware. Currently, the optical port does not support flow
5104          * control auto-negotiation.
5105          */
5106         hns->pf.support_fc_autoneg = false;
5107 }
5108
5109 static int
5110 hns3_init_pf(struct rte_eth_dev *eth_dev)
5111 {
5112         struct rte_device *dev = eth_dev->device;
5113         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5114         struct hns3_adapter *hns = eth_dev->data->dev_private;
5115         struct hns3_hw *hw = &hns->hw;
5116         int ret;
5117
5118         PMD_INIT_FUNC_TRACE();
5119
5120         /* Get hardware io base address from pcie BAR2 IO space */
5121         hw->io_base = pci_dev->mem_resource[2].addr;
5122
5123         /* Firmware command queue initialize */
5124         ret = hns3_cmd_init_queue(hw);
5125         if (ret) {
5126                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5127                 goto err_cmd_init_queue;
5128         }
5129
5130         hns3_clear_all_event_cause(hw);
5131
5132         /* Firmware command initialize */
5133         ret = hns3_cmd_init(hw);
5134         if (ret) {
5135                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5136                 goto err_cmd_init;
5137         }
5138
5139         /*
5140          * To ensure that the hardware environment is clean during
5141          * initialization, the driver actively clear the hardware environment
5142          * during initialization, including PF and corresponding VFs' vlan, mac,
5143          * flow table configurations, etc.
5144          */
5145         ret = hns3_clear_hw(hw);
5146         if (ret) {
5147                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5148                 goto err_cmd_init;
5149         }
5150
5151         /* Hardware statistics of imissed registers cleared. */
5152         ret = hns3_update_imissed_stats(hw, true);
5153         if (ret) {
5154                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5155                 goto err_cmd_init;
5156         }
5157
5158         hns3_config_all_msix_error(hw, true);
5159
5160         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5161                                          hns3_interrupt_handler,
5162                                          eth_dev);
5163         if (ret) {
5164                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5165                 goto err_intr_callback_register;
5166         }
5167
5168         ret = hns3_ptp_init(hw);
5169         if (ret)
5170                 goto err_get_config;
5171
5172         /* Enable interrupt */
5173         rte_intr_enable(&pci_dev->intr_handle);
5174         hns3_pf_enable_irq0(hw);
5175
5176         /* Get configuration */
5177         ret = hns3_get_configuration(hw);
5178         if (ret) {
5179                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5180                 goto err_get_config;
5181         }
5182
5183         ret = hns3_tqp_stats_init(hw);
5184         if (ret)
5185                 goto err_get_config;
5186
5187         ret = hns3_init_hardware(hns);
5188         if (ret) {
5189                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5190                 goto err_init_hw;
5191         }
5192
5193         /* Initialize flow director filter list & hash */
5194         ret = hns3_fdir_filter_init(hns);
5195         if (ret) {
5196                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5197                 goto err_fdir;
5198         }
5199
5200         hns3_rss_set_default_args(hw);
5201
5202         ret = hns3_enable_hw_error_intr(hns, true);
5203         if (ret) {
5204                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5205                              ret);
5206                 goto err_enable_intr;
5207         }
5208
5209         ret = hns3_get_port_supported_speed(eth_dev);
5210         if (ret) {
5211                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5212                              "by device, ret = %d.", ret);
5213                 goto err_supported_speed;
5214         }
5215
5216         hns3_get_fc_autoneg_capability(hns);
5217
5218         hns3_tm_conf_init(eth_dev);
5219
5220         return 0;
5221
5222 err_supported_speed:
5223         (void)hns3_enable_hw_error_intr(hns, false);
5224 err_enable_intr:
5225         hns3_fdir_filter_uninit(hns);
5226 err_fdir:
5227         hns3_uninit_umv_space(hw);
5228 err_init_hw:
5229         hns3_tqp_stats_uninit(hw);
5230 err_get_config:
5231         hns3_pf_disable_irq0(hw);
5232         rte_intr_disable(&pci_dev->intr_handle);
5233         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5234                              eth_dev);
5235 err_intr_callback_register:
5236 err_cmd_init:
5237         hns3_cmd_uninit(hw);
5238         hns3_cmd_destroy_queue(hw);
5239 err_cmd_init_queue:
5240         hw->io_base = NULL;
5241
5242         return ret;
5243 }
5244
5245 static void
5246 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5247 {
5248         struct hns3_adapter *hns = eth_dev->data->dev_private;
5249         struct rte_device *dev = eth_dev->device;
5250         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5251         struct hns3_hw *hw = &hns->hw;
5252
5253         PMD_INIT_FUNC_TRACE();
5254
5255         hns3_tm_conf_uninit(eth_dev);
5256         hns3_enable_hw_error_intr(hns, false);
5257         hns3_rss_uninit(hns);
5258         (void)hns3_config_gro(hw, false);
5259         hns3_promisc_uninit(hw);
5260         hns3_fdir_filter_uninit(hns);
5261         hns3_uninit_umv_space(hw);
5262         hns3_tqp_stats_uninit(hw);
5263         hns3_config_mac_tnl_int(hw, false);
5264         hns3_pf_disable_irq0(hw);
5265         rte_intr_disable(&pci_dev->intr_handle);
5266         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5267                              eth_dev);
5268         hns3_config_all_msix_error(hw, false);
5269         hns3_cmd_uninit(hw);
5270         hns3_cmd_destroy_queue(hw);
5271         hw->io_base = NULL;
5272 }
5273
5274 static int
5275 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5276                                 struct hns3_set_link_speed_cfg *cfg)
5277 {
5278         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5279         struct hns3_phy_params_bd0_cmd *req;
5280         uint16_t i;
5281
5282         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5283                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5284                                           false);
5285                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5286         }
5287         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5288         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5289         req->autoneg = cfg->autoneg;
5290
5291         /*
5292          * The full speed capability is used to negotiate when
5293          * auto-negotiation is enabled.
5294          */
5295         if (cfg->autoneg) {
5296                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5297                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5298                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5299                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5300                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5301         }
5302
5303         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5304 }
5305
5306 static int
5307 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5308 {
5309         struct hns3_config_auto_neg_cmd *req;
5310         struct hns3_cmd_desc desc;
5311         uint32_t flag = 0;
5312         int ret;
5313
5314         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5315
5316         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5317         if (enable)
5318                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5319         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5320
5321         ret = hns3_cmd_send(hw, &desc, 1);
5322         if (ret)
5323                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5324
5325         return ret;
5326 }
5327
5328 static int
5329 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5330                                struct hns3_set_link_speed_cfg *cfg)
5331 {
5332         int ret;
5333
5334         if (hw->mac.support_autoneg) {
5335                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5336                 if (ret) {
5337                         hns3_err(hw, "failed to configure auto-negotiation.");
5338                         return ret;
5339                 }
5340
5341                 /*
5342                  * To enable auto-negotiation, we only need to open the switch
5343                  * of auto-negotiation, then firmware sets all speed
5344                  * capabilities.
5345                  */
5346                 if (cfg->autoneg)
5347                         return 0;
5348         }
5349
5350         /*
5351          * Some hardware doesn't support auto-negotiation, but users may not
5352          * configure link_speeds (default 0), which means auto-negotiation
5353          * In this case, a warning message need to be printed, instead of
5354          * an error.
5355          */
5356         if (cfg->autoneg) {
5357                 hns3_warn(hw, "auto-negotiation is not supported.");
5358                 return 0;
5359         }
5360
5361         return 0;
5362 }
5363
5364 static int
5365 hns3_set_port_link_speed(struct hns3_hw *hw,
5366                          struct hns3_set_link_speed_cfg *cfg)
5367 {
5368         int ret;
5369
5370         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5371 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5372                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5373                 if (pf->is_tmp_phy)
5374                         return 0;
5375 #endif
5376
5377                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5378                 if (ret) {
5379                         hns3_err(hw, "failed to set copper port link speed,"
5380                                  "ret = %d.", ret);
5381                         return ret;
5382                 }
5383         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5384                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5385                 if (ret) {
5386                         hns3_err(hw, "failed to set fiber port link speed,"
5387                                  "ret = %d.", ret);
5388                         return ret;
5389                 }
5390         }
5391
5392         return 0;
5393 }
5394
5395 static int
5396 hns3_apply_link_speed(struct hns3_hw *hw)
5397 {
5398         struct rte_eth_conf *conf = &hw->data->dev_conf;
5399         struct hns3_set_link_speed_cfg cfg;
5400
5401         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5402         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5403                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5404         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5405                 hns3_err(hw, "device doesn't support to force link speed.");
5406                 return -EOPNOTSUPP;
5407         }
5408
5409         return hns3_set_port_link_speed(hw, &cfg);
5410 }
5411
5412 static int
5413 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5414 {
5415         struct hns3_hw *hw = &hns->hw;
5416         int ret;
5417
5418         ret = hns3_dcb_cfg_update(hns);
5419         if (ret)
5420                 return ret;
5421
5422         /*
5423          * The hns3_dcb_cfg_update may configure TM module, so
5424          * hns3_tm_conf_update must called later.
5425          */
5426         ret = hns3_tm_conf_update(hw);
5427         if (ret) {
5428                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5429                 return ret;
5430         }
5431
5432         hns3_enable_rxd_adv_layout(hw);
5433
5434         ret = hns3_init_queues(hns, reset_queue);
5435         if (ret) {
5436                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5437                 return ret;
5438         }
5439
5440         ret = hns3_cfg_mac_mode(hw, true);
5441         if (ret) {
5442                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5443                 goto err_config_mac_mode;
5444         }
5445
5446         ret = hns3_apply_link_speed(hw);
5447         if (ret)
5448                 goto err_config_mac_mode;
5449
5450         return 0;
5451
5452 err_config_mac_mode:
5453         (void)hns3_cfg_mac_mode(hw, false);
5454         hns3_dev_release_mbufs(hns);
5455         /*
5456          * Here is exception handling, hns3_reset_all_tqps will have the
5457          * corresponding error message if it is handled incorrectly, so it is
5458          * not necessary to check hns3_reset_all_tqps return value, here keep
5459          * ret as the error code causing the exception.
5460          */
5461         (void)hns3_reset_all_tqps(hns);
5462         return ret;
5463 }
5464
5465 static int
5466 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5467 {
5468         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5469         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5470         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5471         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5472         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5473         uint32_t intr_vector;
5474         uint16_t q_id;
5475         int ret;
5476
5477         /*
5478          * hns3 needs a separate interrupt to be used as event interrupt which
5479          * could not be shared with task queue pair, so KERNEL drivers need
5480          * support multiple interrupt vectors.
5481          */
5482         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5483             !rte_intr_cap_multiple(intr_handle))
5484                 return 0;
5485
5486         rte_intr_disable(intr_handle);
5487         intr_vector = hw->used_rx_queues;
5488         /* creates event fd for each intr vector when MSIX is used */
5489         if (rte_intr_efd_enable(intr_handle, intr_vector))
5490                 return -EINVAL;
5491
5492         if (intr_handle->intr_vec == NULL) {
5493                 intr_handle->intr_vec =
5494                         rte_zmalloc("intr_vec",
5495                                     hw->used_rx_queues * sizeof(int), 0);
5496                 if (intr_handle->intr_vec == NULL) {
5497                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5498                                         hw->used_rx_queues);
5499                         ret = -ENOMEM;
5500                         goto alloc_intr_vec_error;
5501                 }
5502         }
5503
5504         if (rte_intr_allow_others(intr_handle)) {
5505                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5506                 base = RTE_INTR_VEC_RXTX_OFFSET;
5507         }
5508
5509         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5510                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5511                                                  HNS3_RING_TYPE_RX, q_id);
5512                 if (ret)
5513                         goto bind_vector_error;
5514                 intr_handle->intr_vec[q_id] = vec;
5515                 /*
5516                  * If there are not enough efds (e.g. not enough interrupt),
5517                  * remaining queues will be bond to the last interrupt.
5518                  */
5519                 if (vec < base + intr_handle->nb_efd - 1)
5520                         vec++;
5521         }
5522         rte_intr_enable(intr_handle);
5523         return 0;
5524
5525 bind_vector_error:
5526         rte_free(intr_handle->intr_vec);
5527         intr_handle->intr_vec = NULL;
5528 alloc_intr_vec_error:
5529         rte_intr_efd_disable(intr_handle);
5530         return ret;
5531 }
5532
5533 static int
5534 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5535 {
5536         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5537         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5539         uint16_t q_id;
5540         int ret;
5541
5542         if (dev->data->dev_conf.intr_conf.rxq == 0)
5543                 return 0;
5544
5545         if (rte_intr_dp_is_en(intr_handle)) {
5546                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5547                         ret = hns3_bind_ring_with_vector(hw,
5548                                         intr_handle->intr_vec[q_id], true,
5549                                         HNS3_RING_TYPE_RX, q_id);
5550                         if (ret)
5551                                 return ret;
5552                 }
5553         }
5554
5555         return 0;
5556 }
5557
5558 static void
5559 hns3_restore_filter(struct rte_eth_dev *dev)
5560 {
5561         hns3_restore_rss_filter(dev);
5562 }
5563
5564 static int
5565 hns3_dev_start(struct rte_eth_dev *dev)
5566 {
5567         struct hns3_adapter *hns = dev->data->dev_private;
5568         struct hns3_hw *hw = &hns->hw;
5569         int ret;
5570
5571         PMD_INIT_FUNC_TRACE();
5572         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5573                 return -EBUSY;
5574
5575         rte_spinlock_lock(&hw->lock);
5576         hw->adapter_state = HNS3_NIC_STARTING;
5577
5578         ret = hns3_do_start(hns, true);
5579         if (ret) {
5580                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5581                 rte_spinlock_unlock(&hw->lock);
5582                 return ret;
5583         }
5584         ret = hns3_map_rx_interrupt(dev);
5585         if (ret)
5586                 goto map_rx_inter_err;
5587
5588         /*
5589          * There are three register used to control the status of a TQP
5590          * (contains a pair of Tx queue and Rx queue) in the new version network
5591          * engine. One is used to control the enabling of Tx queue, the other is
5592          * used to control the enabling of Rx queue, and the last is the master
5593          * switch used to control the enabling of the tqp. The Tx register and
5594          * TQP register must be enabled at the same time to enable a Tx queue.
5595          * The same applies to the Rx queue. For the older network engine, this
5596          * function only refresh the enabled flag, and it is used to update the
5597          * status of queue in the dpdk framework.
5598          */
5599         ret = hns3_start_all_txqs(dev);
5600         if (ret)
5601                 goto map_rx_inter_err;
5602
5603         ret = hns3_start_all_rxqs(dev);
5604         if (ret)
5605                 goto start_all_rxqs_fail;
5606
5607         hw->adapter_state = HNS3_NIC_STARTED;
5608         rte_spinlock_unlock(&hw->lock);
5609
5610         hns3_rx_scattered_calc(dev);
5611         hns3_set_rxtx_function(dev);
5612         hns3_mp_req_start_rxtx(dev);
5613
5614         hns3_restore_filter(dev);
5615
5616         /* Enable interrupt of all rx queues before enabling queues */
5617         hns3_dev_all_rx_queue_intr_enable(hw, true);
5618
5619         /*
5620          * After finished the initialization, enable tqps to receive/transmit
5621          * packets and refresh all queue status.
5622          */
5623         hns3_start_tqps(hw);
5624
5625         hns3_tm_dev_start_proc(hw);
5626
5627         if (dev->data->dev_conf.intr_conf.lsc != 0)
5628                 hns3_dev_link_update(dev, 0);
5629         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5630
5631         hns3_info(hw, "hns3 dev start successful!");
5632
5633         return 0;
5634
5635 start_all_rxqs_fail:
5636         hns3_stop_all_txqs(dev);
5637 map_rx_inter_err:
5638         (void)hns3_do_stop(hns);
5639         hw->adapter_state = HNS3_NIC_CONFIGURED;
5640         rte_spinlock_unlock(&hw->lock);
5641
5642         return ret;
5643 }
5644
5645 static int
5646 hns3_do_stop(struct hns3_adapter *hns)
5647 {
5648         struct hns3_hw *hw = &hns->hw;
5649         int ret;
5650
5651         /*
5652          * The "hns3_do_stop" function will also be called by .stop_service to
5653          * prepare reset. At the time of global or IMP reset, the command cannot
5654          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5655          * accessed during the reset process. So the mbuf can not be released
5656          * during reset and is required to be released after the reset is
5657          * completed.
5658          */
5659         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5660                 hns3_dev_release_mbufs(hns);
5661
5662         ret = hns3_cfg_mac_mode(hw, false);
5663         if (ret)
5664                 return ret;
5665         hw->mac.link_status = ETH_LINK_DOWN;
5666
5667         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5668                 hns3_configure_all_mac_addr(hns, true);
5669                 ret = hns3_reset_all_tqps(hns);
5670                 if (ret) {
5671                         hns3_err(hw, "failed to reset all queues ret = %d.",
5672                                  ret);
5673                         return ret;
5674                 }
5675         }
5676         hw->mac.default_addr_setted = false;
5677         return 0;
5678 }
5679
5680 static void
5681 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5682 {
5683         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5684         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5685         struct hns3_adapter *hns = dev->data->dev_private;
5686         struct hns3_hw *hw = &hns->hw;
5687         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5688         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5689         uint16_t q_id;
5690
5691         if (dev->data->dev_conf.intr_conf.rxq == 0)
5692                 return;
5693
5694         /* unmap the ring with vector */
5695         if (rte_intr_allow_others(intr_handle)) {
5696                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5697                 base = RTE_INTR_VEC_RXTX_OFFSET;
5698         }
5699         if (rte_intr_dp_is_en(intr_handle)) {
5700                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5701                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5702                                                          HNS3_RING_TYPE_RX,
5703                                                          q_id);
5704                         if (vec < base + intr_handle->nb_efd - 1)
5705                                 vec++;
5706                 }
5707         }
5708         /* Clean datapath event and queue/vec mapping */
5709         rte_intr_efd_disable(intr_handle);
5710         if (intr_handle->intr_vec) {
5711                 rte_free(intr_handle->intr_vec);
5712                 intr_handle->intr_vec = NULL;
5713         }
5714 }
5715
5716 static int
5717 hns3_dev_stop(struct rte_eth_dev *dev)
5718 {
5719         struct hns3_adapter *hns = dev->data->dev_private;
5720         struct hns3_hw *hw = &hns->hw;
5721
5722         PMD_INIT_FUNC_TRACE();
5723         dev->data->dev_started = 0;
5724
5725         hw->adapter_state = HNS3_NIC_STOPPING;
5726         hns3_set_rxtx_function(dev);
5727         rte_wmb();
5728         /* Disable datapath on secondary process. */
5729         hns3_mp_req_stop_rxtx(dev);
5730         /* Prevent crashes when queues are still in use. */
5731         rte_delay_ms(hw->tqps_num);
5732
5733         rte_spinlock_lock(&hw->lock);
5734         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5735                 hns3_tm_dev_stop_proc(hw);
5736                 hns3_config_mac_tnl_int(hw, false);
5737                 hns3_stop_tqps(hw);
5738                 hns3_do_stop(hns);
5739                 hns3_unmap_rx_interrupt(dev);
5740                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5741         }
5742         hns3_rx_scattered_reset(dev);
5743         rte_eal_alarm_cancel(hns3_service_handler, dev);
5744         hns3_stop_report_lse(dev);
5745         rte_spinlock_unlock(&hw->lock);
5746
5747         return 0;
5748 }
5749
5750 static int
5751 hns3_dev_close(struct rte_eth_dev *eth_dev)
5752 {
5753         struct hns3_adapter *hns = eth_dev->data->dev_private;
5754         struct hns3_hw *hw = &hns->hw;
5755         int ret = 0;
5756
5757         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5758                 rte_free(eth_dev->process_private);
5759                 eth_dev->process_private = NULL;
5760                 return 0;
5761         }
5762
5763         if (hw->adapter_state == HNS3_NIC_STARTED)
5764                 ret = hns3_dev_stop(eth_dev);
5765
5766         hw->adapter_state = HNS3_NIC_CLOSING;
5767         hns3_reset_abort(hns);
5768         hw->adapter_state = HNS3_NIC_CLOSED;
5769
5770         hns3_configure_all_mc_mac_addr(hns, true);
5771         hns3_remove_all_vlan_table(hns);
5772         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5773         hns3_uninit_pf(eth_dev);
5774         hns3_free_all_queues(eth_dev);
5775         rte_free(hw->reset.wait_data);
5776         rte_free(eth_dev->process_private);
5777         eth_dev->process_private = NULL;
5778         hns3_mp_uninit_primary();
5779         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5780
5781         return ret;
5782 }
5783
5784 static void
5785 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5786                                    bool *tx_pause)
5787 {
5788         struct hns3_mac *mac = &hw->mac;
5789         uint32_t advertising = mac->advertising;
5790         uint32_t lp_advertising = mac->lp_advertising;
5791         *rx_pause = false;
5792         *tx_pause = false;
5793
5794         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5795                 *rx_pause = true;
5796                 *tx_pause = true;
5797         } else if (advertising & lp_advertising &
5798                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5799                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5800                         *rx_pause = true;
5801                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5802                         *tx_pause = true;
5803         }
5804 }
5805
5806 static enum hns3_fc_mode
5807 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5808 {
5809         enum hns3_fc_mode current_mode;
5810         bool rx_pause = false;
5811         bool tx_pause = false;
5812
5813         switch (hw->mac.media_type) {
5814         case HNS3_MEDIA_TYPE_COPPER:
5815                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5816                 break;
5817
5818         /*
5819          * Flow control auto-negotiation is not supported for fiber and
5820          * backpalne media type.
5821          */
5822         case HNS3_MEDIA_TYPE_FIBER:
5823         case HNS3_MEDIA_TYPE_BACKPLANE:
5824                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5825                 current_mode = hw->requested_fc_mode;
5826                 goto out;
5827         default:
5828                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5829                          hw->mac.media_type);
5830                 current_mode = HNS3_FC_NONE;
5831                 goto out;
5832         }
5833
5834         if (rx_pause && tx_pause)
5835                 current_mode = HNS3_FC_FULL;
5836         else if (rx_pause)
5837                 current_mode = HNS3_FC_RX_PAUSE;
5838         else if (tx_pause)
5839                 current_mode = HNS3_FC_TX_PAUSE;
5840         else
5841                 current_mode = HNS3_FC_NONE;
5842
5843 out:
5844         return current_mode;
5845 }
5846
5847 static enum hns3_fc_mode
5848 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5849 {
5850         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5851         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5852         struct hns3_mac *mac = &hw->mac;
5853
5854         /*
5855          * When the flow control mode is obtained, the device may not complete
5856          * auto-negotiation. It is necessary to wait for link establishment.
5857          */
5858         (void)hns3_dev_link_update(dev, 1);
5859
5860         /*
5861          * If the link auto-negotiation of the nic is disabled, or the flow
5862          * control auto-negotiation is not supported, the forced flow control
5863          * mode is used.
5864          */
5865         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5866                 return hw->requested_fc_mode;
5867
5868         return hns3_get_autoneg_fc_mode(hw);
5869 }
5870
5871 static int
5872 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5873 {
5874         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5875         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5876         enum hns3_fc_mode current_mode;
5877
5878         current_mode = hns3_get_current_fc_mode(dev);
5879         switch (current_mode) {
5880         case HNS3_FC_FULL:
5881                 fc_conf->mode = RTE_FC_FULL;
5882                 break;
5883         case HNS3_FC_TX_PAUSE:
5884                 fc_conf->mode = RTE_FC_TX_PAUSE;
5885                 break;
5886         case HNS3_FC_RX_PAUSE:
5887                 fc_conf->mode = RTE_FC_RX_PAUSE;
5888                 break;
5889         case HNS3_FC_NONE:
5890         default:
5891                 fc_conf->mode = RTE_FC_NONE;
5892                 break;
5893         }
5894
5895         fc_conf->pause_time = pf->pause_time;
5896         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
5897
5898         return 0;
5899 }
5900
5901 static void
5902 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5903 {
5904         switch (mode) {
5905         case RTE_FC_NONE:
5906                 hw->requested_fc_mode = HNS3_FC_NONE;
5907                 break;
5908         case RTE_FC_RX_PAUSE:
5909                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
5910                 break;
5911         case RTE_FC_TX_PAUSE:
5912                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
5913                 break;
5914         case RTE_FC_FULL:
5915                 hw->requested_fc_mode = HNS3_FC_FULL;
5916                 break;
5917         default:
5918                 hw->requested_fc_mode = HNS3_FC_NONE;
5919                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5920                           "configured to RTE_FC_NONE", mode);
5921                 break;
5922         }
5923 }
5924
5925 static int
5926 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
5927 {
5928         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5929
5930         if (!pf->support_fc_autoneg) {
5931                 if (autoneg != 0) {
5932                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
5933                         return -EOPNOTSUPP;
5934                 }
5935
5936                 /*
5937                  * Flow control auto-negotiation of the NIC is not supported,
5938                  * but other auto-negotiation features may be supported.
5939                  */
5940                 if (autoneg != hw->mac.link_autoneg) {
5941                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
5942                         return -EOPNOTSUPP;
5943                 }
5944
5945                 return 0;
5946         }
5947
5948         /*
5949          * If flow control auto-negotiation of the NIC is supported, all
5950          * auto-negotiation features are supported.
5951          */
5952         if (autoneg != hw->mac.link_autoneg) {
5953                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
5954                 return -EOPNOTSUPP;
5955         }
5956
5957         return 0;
5958 }
5959
5960 static int
5961 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5962 {
5963         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964         int ret;
5965
5966         if (fc_conf->high_water || fc_conf->low_water ||
5967             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5968                 hns3_err(hw, "Unsupported flow control settings specified, "
5969                          "high_water(%u), low_water(%u), send_xon(%u) and "
5970                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5971                          fc_conf->high_water, fc_conf->low_water,
5972                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5973                 return -EINVAL;
5974         }
5975
5976         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
5977         if (ret)
5978                 return ret;
5979
5980         if (!fc_conf->pause_time) {
5981                 hns3_err(hw, "Invalid pause time %u setting.",
5982                          fc_conf->pause_time);
5983                 return -EINVAL;
5984         }
5985
5986         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5987             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5988                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5989                          "current_fc_status = %d", hw->current_fc_status);
5990                 return -EOPNOTSUPP;
5991         }
5992
5993         if (hw->num_tc > 1) {
5994                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5995                 return -EOPNOTSUPP;
5996         }
5997
5998         hns3_get_fc_mode(hw, fc_conf->mode);
5999
6000         rte_spinlock_lock(&hw->lock);
6001         ret = hns3_fc_enable(dev, fc_conf);
6002         rte_spinlock_unlock(&hw->lock);
6003
6004         return ret;
6005 }
6006
6007 static int
6008 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6009                             struct rte_eth_pfc_conf *pfc_conf)
6010 {
6011         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         int ret;
6013
6014         if (!hns3_dev_dcb_supported(hw)) {
6015                 hns3_err(hw, "This port does not support dcb configurations.");
6016                 return -EOPNOTSUPP;
6017         }
6018
6019         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6020             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6021                 hns3_err(hw, "Unsupported flow control settings specified, "
6022                          "high_water(%u), low_water(%u), send_xon(%u) and "
6023                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6024                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6025                          pfc_conf->fc.send_xon,
6026                          pfc_conf->fc.mac_ctrl_frame_fwd);
6027                 return -EINVAL;
6028         }
6029         if (pfc_conf->fc.autoneg) {
6030                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6031                 return -EINVAL;
6032         }
6033         if (pfc_conf->fc.pause_time == 0) {
6034                 hns3_err(hw, "Invalid pause time %u setting.",
6035                          pfc_conf->fc.pause_time);
6036                 return -EINVAL;
6037         }
6038
6039         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6040             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6041                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6042                              "current_fc_status = %d", hw->current_fc_status);
6043                 return -EOPNOTSUPP;
6044         }
6045
6046         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6047
6048         rte_spinlock_lock(&hw->lock);
6049         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6050         rte_spinlock_unlock(&hw->lock);
6051
6052         return ret;
6053 }
6054
6055 static int
6056 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6057 {
6058         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6059         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6060         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6061         int i;
6062
6063         rte_spinlock_lock(&hw->lock);
6064         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6065                 dcb_info->nb_tcs = pf->local_max_tc;
6066         else
6067                 dcb_info->nb_tcs = 1;
6068
6069         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6070                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6071         for (i = 0; i < dcb_info->nb_tcs; i++)
6072                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6073
6074         for (i = 0; i < hw->num_tc; i++) {
6075                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6076                 dcb_info->tc_queue.tc_txq[0][i].base =
6077                                                 hw->tc_queue[i].tqp_offset;
6078                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6079                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6080                                                 hw->tc_queue[i].tqp_count;
6081         }
6082         rte_spinlock_unlock(&hw->lock);
6083
6084         return 0;
6085 }
6086
6087 static int
6088 hns3_reinit_dev(struct hns3_adapter *hns)
6089 {
6090         struct hns3_hw *hw = &hns->hw;
6091         int ret;
6092
6093         ret = hns3_cmd_init(hw);
6094         if (ret) {
6095                 hns3_err(hw, "Failed to init cmd: %d", ret);
6096                 return ret;
6097         }
6098
6099         ret = hns3_reset_all_tqps(hns);
6100         if (ret) {
6101                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6102                 return ret;
6103         }
6104
6105         ret = hns3_init_hardware(hns);
6106         if (ret) {
6107                 hns3_err(hw, "Failed to init hardware: %d", ret);
6108                 return ret;
6109         }
6110
6111         ret = hns3_enable_hw_error_intr(hns, true);
6112         if (ret) {
6113                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6114                              ret);
6115                 return ret;
6116         }
6117         hns3_info(hw, "Reset done, driver initialization finished.");
6118
6119         return 0;
6120 }
6121
6122 static bool
6123 is_pf_reset_done(struct hns3_hw *hw)
6124 {
6125         uint32_t val, reg, reg_bit;
6126
6127         switch (hw->reset.level) {
6128         case HNS3_IMP_RESET:
6129                 reg = HNS3_GLOBAL_RESET_REG;
6130                 reg_bit = HNS3_IMP_RESET_BIT;
6131                 break;
6132         case HNS3_GLOBAL_RESET:
6133                 reg = HNS3_GLOBAL_RESET_REG;
6134                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6135                 break;
6136         case HNS3_FUNC_RESET:
6137                 reg = HNS3_FUN_RST_ING;
6138                 reg_bit = HNS3_FUN_RST_ING_B;
6139                 break;
6140         case HNS3_FLR_RESET:
6141         default:
6142                 hns3_err(hw, "Wait for unsupported reset level: %d",
6143                          hw->reset.level);
6144                 return true;
6145         }
6146         val = hns3_read_dev(hw, reg);
6147         if (hns3_get_bit(val, reg_bit))
6148                 return false;
6149         else
6150                 return true;
6151 }
6152
6153 bool
6154 hns3_is_reset_pending(struct hns3_adapter *hns)
6155 {
6156         struct hns3_hw *hw = &hns->hw;
6157         enum hns3_reset_level reset;
6158
6159         hns3_check_event_cause(hns, NULL);
6160         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6161         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
6162                 hns3_warn(hw, "High level reset %d is pending", reset);
6163                 return true;
6164         }
6165         reset = hns3_get_reset_level(hns, &hw->reset.request);
6166         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
6167                 hns3_warn(hw, "High level reset %d is request", reset);
6168                 return true;
6169         }
6170         return false;
6171 }
6172
6173 static int
6174 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6175 {
6176         struct hns3_hw *hw = &hns->hw;
6177         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6178         struct timeval tv;
6179
6180         if (wait_data->result == HNS3_WAIT_SUCCESS)
6181                 return 0;
6182         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6183                 gettimeofday(&tv, NULL);
6184                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6185                           tv.tv_sec, tv.tv_usec);
6186                 return -ETIME;
6187         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6188                 return -EAGAIN;
6189
6190         wait_data->hns = hns;
6191         wait_data->check_completion = is_pf_reset_done;
6192         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6193                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6194         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6195         wait_data->count = HNS3_RESET_WAIT_CNT;
6196         wait_data->result = HNS3_WAIT_REQUEST;
6197         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6198         return -EAGAIN;
6199 }
6200
6201 static int
6202 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6203 {
6204         struct hns3_cmd_desc desc;
6205         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6206
6207         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6208         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6209         req->fun_reset_vfid = func_id;
6210
6211         return hns3_cmd_send(hw, &desc, 1);
6212 }
6213
6214 static int
6215 hns3_imp_reset_cmd(struct hns3_hw *hw)
6216 {
6217         struct hns3_cmd_desc desc;
6218
6219         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6220         desc.data[0] = 0xeedd;
6221
6222         return hns3_cmd_send(hw, &desc, 1);
6223 }
6224
6225 static void
6226 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6227 {
6228         struct hns3_hw *hw = &hns->hw;
6229         struct timeval tv;
6230         uint32_t val;
6231
6232         gettimeofday(&tv, NULL);
6233         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6234             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6235                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6236                           tv.tv_sec, tv.tv_usec);
6237                 return;
6238         }
6239
6240         switch (reset_level) {
6241         case HNS3_IMP_RESET:
6242                 hns3_imp_reset_cmd(hw);
6243                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6244                           tv.tv_sec, tv.tv_usec);
6245                 break;
6246         case HNS3_GLOBAL_RESET:
6247                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6248                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6249                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6250                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6251                           tv.tv_sec, tv.tv_usec);
6252                 break;
6253         case HNS3_FUNC_RESET:
6254                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6255                           tv.tv_sec, tv.tv_usec);
6256                 /* schedule again to check later */
6257                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6258                 hns3_schedule_reset(hns);
6259                 break;
6260         default:
6261                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6262                 return;
6263         }
6264         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6265 }
6266
6267 static enum hns3_reset_level
6268 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6269 {
6270         struct hns3_hw *hw = &hns->hw;
6271         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6272
6273         /* Return the highest priority reset level amongst all */
6274         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6275                 reset_level = HNS3_IMP_RESET;
6276         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6277                 reset_level = HNS3_GLOBAL_RESET;
6278         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6279                 reset_level = HNS3_FUNC_RESET;
6280         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6281                 reset_level = HNS3_FLR_RESET;
6282
6283         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6284                 return HNS3_NONE_RESET;
6285
6286         return reset_level;
6287 }
6288
6289 static void
6290 hns3_record_imp_error(struct hns3_adapter *hns)
6291 {
6292         struct hns3_hw *hw = &hns->hw;
6293         uint32_t reg_val;
6294
6295         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6296         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6297                 hns3_warn(hw, "Detected IMP RD poison!");
6298                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6299                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6300         }
6301
6302         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6303                 hns3_warn(hw, "Detected IMP CMDQ error!");
6304                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6305                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6306         }
6307 }
6308
6309 static int
6310 hns3_prepare_reset(struct hns3_adapter *hns)
6311 {
6312         struct hns3_hw *hw = &hns->hw;
6313         uint32_t reg_val;
6314         int ret;
6315
6316         switch (hw->reset.level) {
6317         case HNS3_FUNC_RESET:
6318                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6319                 if (ret)
6320                         return ret;
6321
6322                 /*
6323                  * After performaning pf reset, it is not necessary to do the
6324                  * mailbox handling or send any command to firmware, because
6325                  * any mailbox handling or command to firmware is only valid
6326                  * after hns3_cmd_init is called.
6327                  */
6328                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6329                 hw->reset.stats.request_cnt++;
6330                 break;
6331         case HNS3_IMP_RESET:
6332                 hns3_record_imp_error(hns);
6333                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6334                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6335                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6336                 break;
6337         default:
6338                 break;
6339         }
6340         return 0;
6341 }
6342
6343 static int
6344 hns3_set_rst_done(struct hns3_hw *hw)
6345 {
6346         struct hns3_pf_rst_done_cmd *req;
6347         struct hns3_cmd_desc desc;
6348
6349         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6350         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6351         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6352         return hns3_cmd_send(hw, &desc, 1);
6353 }
6354
6355 static int
6356 hns3_stop_service(struct hns3_adapter *hns)
6357 {
6358         struct hns3_hw *hw = &hns->hw;
6359         struct rte_eth_dev *eth_dev;
6360
6361         eth_dev = &rte_eth_devices[hw->data->port_id];
6362         hw->mac.link_status = ETH_LINK_DOWN;
6363         if (hw->adapter_state == HNS3_NIC_STARTED) {
6364                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6365                 hns3_update_linkstatus_and_event(hw, false);
6366         }
6367
6368         hns3_set_rxtx_function(eth_dev);
6369         rte_wmb();
6370         /* Disable datapath on secondary process. */
6371         hns3_mp_req_stop_rxtx(eth_dev);
6372         rte_delay_ms(hw->tqps_num);
6373
6374         rte_spinlock_lock(&hw->lock);
6375         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6376             hw->adapter_state == HNS3_NIC_STOPPING) {
6377                 hns3_enable_all_queues(hw, false);
6378                 hns3_do_stop(hns);
6379                 hw->reset.mbuf_deferred_free = true;
6380         } else
6381                 hw->reset.mbuf_deferred_free = false;
6382
6383         /*
6384          * It is cumbersome for hardware to pick-and-choose entries for deletion
6385          * from table space. Hence, for function reset software intervention is
6386          * required to delete the entries
6387          */
6388         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6389                 hns3_configure_all_mc_mac_addr(hns, true);
6390         rte_spinlock_unlock(&hw->lock);
6391
6392         return 0;
6393 }
6394
6395 static int
6396 hns3_start_service(struct hns3_adapter *hns)
6397 {
6398         struct hns3_hw *hw = &hns->hw;
6399         struct rte_eth_dev *eth_dev;
6400
6401         if (hw->reset.level == HNS3_IMP_RESET ||
6402             hw->reset.level == HNS3_GLOBAL_RESET)
6403                 hns3_set_rst_done(hw);
6404         eth_dev = &rte_eth_devices[hw->data->port_id];
6405         hns3_set_rxtx_function(eth_dev);
6406         hns3_mp_req_start_rxtx(eth_dev);
6407         if (hw->adapter_state == HNS3_NIC_STARTED) {
6408                 /*
6409                  * This API parent function already hold the hns3_hw.lock, the
6410                  * hns3_service_handler may report lse, in bonding application
6411                  * it will call driver's ops which may acquire the hns3_hw.lock
6412                  * again, thus lead to deadlock.
6413                  * We defer calls hns3_service_handler to avoid the deadlock.
6414                  */
6415                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6416                                   hns3_service_handler, eth_dev);
6417
6418                 /* Enable interrupt of all rx queues before enabling queues */
6419                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6420                 /*
6421                  * Enable state of each rxq and txq will be recovered after
6422                  * reset, so we need to restore them before enable all tqps;
6423                  */
6424                 hns3_restore_tqp_enable_state(hw);
6425                 /*
6426                  * When finished the initialization, enable queues to receive
6427                  * and transmit packets.
6428                  */
6429                 hns3_enable_all_queues(hw, true);
6430         }
6431
6432         return 0;
6433 }
6434
6435 static int
6436 hns3_restore_conf(struct hns3_adapter *hns)
6437 {
6438         struct hns3_hw *hw = &hns->hw;
6439         int ret;
6440
6441         ret = hns3_configure_all_mac_addr(hns, false);
6442         if (ret)
6443                 return ret;
6444
6445         ret = hns3_configure_all_mc_mac_addr(hns, false);
6446         if (ret)
6447                 goto err_mc_mac;
6448
6449         ret = hns3_dev_promisc_restore(hns);
6450         if (ret)
6451                 goto err_promisc;
6452
6453         ret = hns3_restore_vlan_table(hns);
6454         if (ret)
6455                 goto err_promisc;
6456
6457         ret = hns3_restore_vlan_conf(hns);
6458         if (ret)
6459                 goto err_promisc;
6460
6461         ret = hns3_restore_all_fdir_filter(hns);
6462         if (ret)
6463                 goto err_promisc;
6464
6465         ret = hns3_restore_ptp(hns);
6466         if (ret)
6467                 goto err_promisc;
6468
6469         ret = hns3_restore_rx_interrupt(hw);
6470         if (ret)
6471                 goto err_promisc;
6472
6473         ret = hns3_restore_gro_conf(hw);
6474         if (ret)
6475                 goto err_promisc;
6476
6477         ret = hns3_restore_fec(hw);
6478         if (ret)
6479                 goto err_promisc;
6480
6481         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6482                 ret = hns3_do_start(hns, false);
6483                 if (ret)
6484                         goto err_promisc;
6485                 hns3_info(hw, "hns3 dev restart successful!");
6486         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6487                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6488         return 0;
6489
6490 err_promisc:
6491         hns3_configure_all_mc_mac_addr(hns, true);
6492 err_mc_mac:
6493         hns3_configure_all_mac_addr(hns, true);
6494         return ret;
6495 }
6496
6497 static void
6498 hns3_reset_service(void *param)
6499 {
6500         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6501         struct hns3_hw *hw = &hns->hw;
6502         enum hns3_reset_level reset_level;
6503         struct timeval tv_delta;
6504         struct timeval tv_start;
6505         struct timeval tv;
6506         uint64_t msec;
6507         int ret;
6508
6509         /*
6510          * The interrupt is not triggered within the delay time.
6511          * The interrupt may have been lost. It is necessary to handle
6512          * the interrupt to recover from the error.
6513          */
6514         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6515                             SCHEDULE_DEFERRED) {
6516                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6517                                   __ATOMIC_RELAXED);
6518                 hns3_err(hw, "Handling interrupts in delayed tasks");
6519                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6520                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6521                 if (reset_level == HNS3_NONE_RESET) {
6522                         hns3_err(hw, "No reset level is set, try IMP reset");
6523                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6524                 }
6525         }
6526         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6527
6528         /*
6529          * Check if there is any ongoing reset in the hardware. This status can
6530          * be checked from reset_pending. If there is then, we need to wait for
6531          * hardware to complete reset.
6532          *    a. If we are able to figure out in reasonable time that hardware
6533          *       has fully resetted then, we can proceed with driver, client
6534          *       reset.
6535          *    b. else, we can come back later to check this status so re-sched
6536          *       now.
6537          */
6538         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6539         if (reset_level != HNS3_NONE_RESET) {
6540                 gettimeofday(&tv_start, NULL);
6541                 ret = hns3_reset_process(hns, reset_level);
6542                 gettimeofday(&tv, NULL);
6543                 timersub(&tv, &tv_start, &tv_delta);
6544                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6545                        tv_delta.tv_usec / USEC_PER_MSEC;
6546                 if (msec > HNS3_RESET_PROCESS_MS)
6547                         hns3_err(hw, "%d handle long time delta %" PRIx64
6548                                      " ms time=%ld.%.6ld",
6549                                  hw->reset.level, msec,
6550                                  tv.tv_sec, tv.tv_usec);
6551                 if (ret == -EAGAIN)
6552                         return;
6553         }
6554
6555         /* Check if we got any *new* reset requests to be honored */
6556         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6557         if (reset_level != HNS3_NONE_RESET)
6558                 hns3_msix_process(hns, reset_level);
6559 }
6560
6561 static unsigned int
6562 hns3_get_speed_capa_num(uint16_t device_id)
6563 {
6564         unsigned int num;
6565
6566         switch (device_id) {
6567         case HNS3_DEV_ID_25GE:
6568         case HNS3_DEV_ID_25GE_RDMA:
6569                 num = 2;
6570                 break;
6571         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6572         case HNS3_DEV_ID_200G_RDMA:
6573                 num = 1;
6574                 break;
6575         default:
6576                 num = 0;
6577                 break;
6578         }
6579
6580         return num;
6581 }
6582
6583 static int
6584 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6585                         uint16_t device_id)
6586 {
6587         switch (device_id) {
6588         case HNS3_DEV_ID_25GE:
6589         /* fallthrough */
6590         case HNS3_DEV_ID_25GE_RDMA:
6591                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6592                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6593
6594                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6595                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6596                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6597                 break;
6598         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6599                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6600                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6601                 break;
6602         case HNS3_DEV_ID_200G_RDMA:
6603                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6604                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6605                 break;
6606         default:
6607                 return -ENOTSUP;
6608         }
6609
6610         return 0;
6611 }
6612
6613 static int
6614 hns3_fec_get_capability(struct rte_eth_dev *dev,
6615                         struct rte_eth_fec_capa *speed_fec_capa,
6616                         unsigned int num)
6617 {
6618         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6620         uint16_t device_id = pci_dev->id.device_id;
6621         unsigned int capa_num;
6622         int ret;
6623
6624         capa_num = hns3_get_speed_capa_num(device_id);
6625         if (capa_num == 0) {
6626                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6627                          device_id);
6628                 return -ENOTSUP;
6629         }
6630
6631         if (speed_fec_capa == NULL || num < capa_num)
6632                 return capa_num;
6633
6634         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6635         if (ret)
6636                 return -ENOTSUP;
6637
6638         return capa_num;
6639 }
6640
6641 static int
6642 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6643 {
6644         struct hns3_config_fec_cmd *req;
6645         struct hns3_cmd_desc desc;
6646         int ret;
6647
6648         /*
6649          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6650          * in device of link speed
6651          * below 10 Gbps.
6652          */
6653         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6654                 *state = 0;
6655                 return 0;
6656         }
6657
6658         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6659         req = (struct hns3_config_fec_cmd *)desc.data;
6660         ret = hns3_cmd_send(hw, &desc, 1);
6661         if (ret) {
6662                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6663                          ret);
6664                 return ret;
6665         }
6666
6667         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6668         return 0;
6669 }
6670
6671 static int
6672 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6673 {
6674         struct hns3_sfp_info_cmd *resp;
6675         uint32_t tmp_fec_capa;
6676         uint8_t auto_state;
6677         struct hns3_cmd_desc desc;
6678         int ret;
6679
6680         /*
6681          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6682          * configured FEC mode is returned.
6683          * If link is up, current FEC mode is returned.
6684          */
6685         if (hw->mac.link_status == ETH_LINK_DOWN) {
6686                 ret = get_current_fec_auto_state(hw, &auto_state);
6687                 if (ret)
6688                         return ret;
6689
6690                 if (auto_state == 0x1) {
6691                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6692                         return 0;
6693                 }
6694         }
6695
6696         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6697         resp = (struct hns3_sfp_info_cmd *)desc.data;
6698         resp->query_type = HNS3_ACTIVE_QUERY;
6699
6700         ret = hns3_cmd_send(hw, &desc, 1);
6701         if (ret == -EOPNOTSUPP) {
6702                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6703                 return ret;
6704         } else if (ret) {
6705                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6706                 return ret;
6707         }
6708
6709         /*
6710          * FEC mode order defined in hns3 hardware is inconsistend with
6711          * that defined in the ethdev library. So the sequence needs
6712          * to be converted.
6713          */
6714         switch (resp->active_fec) {
6715         case HNS3_HW_FEC_MODE_NOFEC:
6716                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6717                 break;
6718         case HNS3_HW_FEC_MODE_BASER:
6719                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6720                 break;
6721         case HNS3_HW_FEC_MODE_RS:
6722                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6723                 break;
6724         default:
6725                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6726                 break;
6727         }
6728
6729         *fec_capa = tmp_fec_capa;
6730         return 0;
6731 }
6732
6733 static int
6734 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6735 {
6736         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6737
6738         return hns3_fec_get_internal(hw, fec_capa);
6739 }
6740
6741 static int
6742 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6743 {
6744         struct hns3_config_fec_cmd *req;
6745         struct hns3_cmd_desc desc;
6746         int ret;
6747
6748         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6749
6750         req = (struct hns3_config_fec_cmd *)desc.data;
6751         switch (mode) {
6752         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6753                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6754                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6755                 break;
6756         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6757                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6758                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6759                 break;
6760         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6761                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6762                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6763                 break;
6764         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6765                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6766                 break;
6767         default:
6768                 return 0;
6769         }
6770         ret = hns3_cmd_send(hw, &desc, 1);
6771         if (ret)
6772                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6773
6774         return ret;
6775 }
6776
6777 static uint32_t
6778 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6779 {
6780         struct hns3_mac *mac = &hw->mac;
6781         uint32_t cur_capa;
6782
6783         switch (mac->link_speed) {
6784         case ETH_SPEED_NUM_10G:
6785                 cur_capa = fec_capa[1].capa;
6786                 break;
6787         case ETH_SPEED_NUM_25G:
6788         case ETH_SPEED_NUM_100G:
6789         case ETH_SPEED_NUM_200G:
6790                 cur_capa = fec_capa[0].capa;
6791                 break;
6792         default:
6793                 cur_capa = 0;
6794                 break;
6795         }
6796
6797         return cur_capa;
6798 }
6799
6800 static bool
6801 is_fec_mode_one_bit_set(uint32_t mode)
6802 {
6803         int cnt = 0;
6804         uint8_t i;
6805
6806         for (i = 0; i < sizeof(mode); i++)
6807                 if (mode >> i & 0x1)
6808                         cnt++;
6809
6810         return cnt == 1 ? true : false;
6811 }
6812
6813 static int
6814 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6815 {
6816 #define FEC_CAPA_NUM 2
6817         struct hns3_adapter *hns = dev->data->dev_private;
6818         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6819         struct hns3_pf *pf = &hns->pf;
6820
6821         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6822         uint32_t cur_capa;
6823         uint32_t num = FEC_CAPA_NUM;
6824         int ret;
6825
6826         ret = hns3_fec_get_capability(dev, fec_capa, num);
6827         if (ret < 0)
6828                 return ret;
6829
6830         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6831         if (!is_fec_mode_one_bit_set(mode))
6832                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6833                              "FEC mode should be only one bit set", mode);
6834
6835         /*
6836          * Check whether the configured mode is within the FEC capability.
6837          * If not, the configured mode will not be supported.
6838          */
6839         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6840         if (!(cur_capa & mode)) {
6841                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6842                 return -EINVAL;
6843         }
6844
6845         rte_spinlock_lock(&hw->lock);
6846         ret = hns3_set_fec_hw(hw, mode);
6847         if (ret) {
6848                 rte_spinlock_unlock(&hw->lock);
6849                 return ret;
6850         }
6851
6852         pf->fec_mode = mode;
6853         rte_spinlock_unlock(&hw->lock);
6854
6855         return 0;
6856 }
6857
6858 static int
6859 hns3_restore_fec(struct hns3_hw *hw)
6860 {
6861         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6862         struct hns3_pf *pf = &hns->pf;
6863         uint32_t mode = pf->fec_mode;
6864         int ret;
6865
6866         ret = hns3_set_fec_hw(hw, mode);
6867         if (ret)
6868                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6869                          mode, ret);
6870
6871         return ret;
6872 }
6873
6874 static int
6875 hns3_query_dev_fec_info(struct hns3_hw *hw)
6876 {
6877         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6878         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6879         int ret;
6880
6881         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6882         if (ret)
6883                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6884
6885         return ret;
6886 }
6887
6888 static bool
6889 hns3_optical_module_existed(struct hns3_hw *hw)
6890 {
6891         struct hns3_cmd_desc desc;
6892         bool existed;
6893         int ret;
6894
6895         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6896         ret = hns3_cmd_send(hw, &desc, 1);
6897         if (ret) {
6898                 hns3_err(hw,
6899                          "fail to get optical module exist state, ret = %d.\n",
6900                          ret);
6901                 return false;
6902         }
6903         existed = !!desc.data[0];
6904
6905         return existed;
6906 }
6907
6908 static int
6909 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6910                                 uint32_t len, uint8_t *data)
6911 {
6912 #define HNS3_SFP_INFO_CMD_NUM 6
6913 #define HNS3_SFP_INFO_MAX_LEN \
6914         (HNS3_SFP_INFO_BD0_LEN + \
6915         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6916         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6917         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6918         uint16_t read_len;
6919         uint16_t copy_len;
6920         int ret;
6921         int i;
6922
6923         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6924                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6925                                           true);
6926                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6927                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6928         }
6929
6930         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6931         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6932         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6933         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6934
6935         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6936         if (ret) {
6937                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6938                                 ret);
6939                 return ret;
6940         }
6941
6942         /* The data format in BD0 is different with the others. */
6943         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6944         memcpy(data, sfp_info_bd0->data, copy_len);
6945         read_len = copy_len;
6946
6947         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6948                 if (read_len >= len)
6949                         break;
6950
6951                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6952                 memcpy(data + read_len, desc[i].data, copy_len);
6953                 read_len += copy_len;
6954         }
6955
6956         return (int)read_len;
6957 }
6958
6959 static int
6960 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6961                        struct rte_dev_eeprom_info *info)
6962 {
6963         struct hns3_adapter *hns = dev->data->dev_private;
6964         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6965         uint32_t offset = info->offset;
6966         uint32_t len = info->length;
6967         uint8_t *data = info->data;
6968         uint32_t read_len = 0;
6969
6970         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6971                 return -ENOTSUP;
6972
6973         if (!hns3_optical_module_existed(hw)) {
6974                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6975                 return -EIO;
6976         }
6977
6978         while (read_len < len) {
6979                 int ret;
6980                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6981                                                   len - read_len,
6982                                                   data + read_len);
6983                 if (ret < 0)
6984                         return -EIO;
6985                 read_len += ret;
6986         }
6987
6988         return 0;
6989 }
6990
6991 static int
6992 hns3_get_module_info(struct rte_eth_dev *dev,
6993                      struct rte_eth_dev_module_info *modinfo)
6994 {
6995 #define HNS3_SFF8024_ID_SFP             0x03
6996 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6997 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6998 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6999 #define HNS3_SFF_8636_V1_3              0x03
7000         struct hns3_adapter *hns = dev->data->dev_private;
7001         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7002         struct rte_dev_eeprom_info info;
7003         struct hns3_sfp_type sfp_type;
7004         int ret;
7005
7006         memset(&sfp_type, 0, sizeof(sfp_type));
7007         memset(&info, 0, sizeof(info));
7008         info.data = (uint8_t *)&sfp_type;
7009         info.length = sizeof(sfp_type);
7010         ret = hns3_get_module_eeprom(dev, &info);
7011         if (ret)
7012                 return ret;
7013
7014         switch (sfp_type.type) {
7015         case HNS3_SFF8024_ID_SFP:
7016                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7017                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7018                 break;
7019         case HNS3_SFF8024_ID_QSFP_8438:
7020                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7021                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7022                 break;
7023         case HNS3_SFF8024_ID_QSFP_8436_8636:
7024                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7025                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7026                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7027                 } else {
7028                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7029                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7030                 }
7031                 break;
7032         case HNS3_SFF8024_ID_QSFP28_8636:
7033                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7034                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7035                 break;
7036         default:
7037                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7038                          sfp_type.type, sfp_type.ext_type);
7039                 return -EINVAL;
7040         }
7041
7042         return 0;
7043 }
7044
7045 static int
7046 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7047 {
7048         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7049
7050         RTE_SET_USED(key);
7051
7052         if (strcmp(value, "vec") == 0)
7053                 hint = HNS3_IO_FUNC_HINT_VEC;
7054         else if (strcmp(value, "sve") == 0)
7055                 hint = HNS3_IO_FUNC_HINT_SVE;
7056         else if (strcmp(value, "simple") == 0)
7057                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7058         else if (strcmp(value, "common") == 0)
7059                 hint = HNS3_IO_FUNC_HINT_COMMON;
7060
7061         /* If the hint is valid then update output parameters */
7062         if (hint != HNS3_IO_FUNC_HINT_NONE)
7063                 *(uint32_t *)extra_args = hint;
7064
7065         return 0;
7066 }
7067
7068 static const char *
7069 hns3_get_io_hint_func_name(uint32_t hint)
7070 {
7071         switch (hint) {
7072         case HNS3_IO_FUNC_HINT_VEC:
7073                 return "vec";
7074         case HNS3_IO_FUNC_HINT_SVE:
7075                 return "sve";
7076         case HNS3_IO_FUNC_HINT_SIMPLE:
7077                 return "simple";
7078         case HNS3_IO_FUNC_HINT_COMMON:
7079                 return "common";
7080         default:
7081                 return "none";
7082         }
7083 }
7084
7085 void
7086 hns3_parse_devargs(struct rte_eth_dev *dev)
7087 {
7088         struct hns3_adapter *hns = dev->data->dev_private;
7089         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7090         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7091         struct hns3_hw *hw = &hns->hw;
7092         struct rte_kvargs *kvlist;
7093
7094         if (dev->device->devargs == NULL)
7095                 return;
7096
7097         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7098         if (!kvlist)
7099                 return;
7100
7101         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7102                            &hns3_parse_io_hint_func, &rx_func_hint);
7103         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7104                            &hns3_parse_io_hint_func, &tx_func_hint);
7105         rte_kvargs_free(kvlist);
7106
7107         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7108                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7109                           hns3_get_io_hint_func_name(rx_func_hint));
7110         hns->rx_func_hint = rx_func_hint;
7111         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7112                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7113                           hns3_get_io_hint_func_name(tx_func_hint));
7114         hns->tx_func_hint = tx_func_hint;
7115 }
7116
7117 static const struct eth_dev_ops hns3_eth_dev_ops = {
7118         .dev_configure      = hns3_dev_configure,
7119         .dev_start          = hns3_dev_start,
7120         .dev_stop           = hns3_dev_stop,
7121         .dev_close          = hns3_dev_close,
7122         .promiscuous_enable = hns3_dev_promiscuous_enable,
7123         .promiscuous_disable = hns3_dev_promiscuous_disable,
7124         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7125         .allmulticast_disable = hns3_dev_allmulticast_disable,
7126         .mtu_set            = hns3_dev_mtu_set,
7127         .stats_get          = hns3_stats_get,
7128         .stats_reset        = hns3_stats_reset,
7129         .xstats_get         = hns3_dev_xstats_get,
7130         .xstats_get_names   = hns3_dev_xstats_get_names,
7131         .xstats_reset       = hns3_dev_xstats_reset,
7132         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7133         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7134         .dev_infos_get          = hns3_dev_infos_get,
7135         .fw_version_get         = hns3_fw_version_get,
7136         .rx_queue_setup         = hns3_rx_queue_setup,
7137         .tx_queue_setup         = hns3_tx_queue_setup,
7138         .rx_queue_release       = hns3_dev_rx_queue_release,
7139         .tx_queue_release       = hns3_dev_tx_queue_release,
7140         .rx_queue_start         = hns3_dev_rx_queue_start,
7141         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7142         .tx_queue_start         = hns3_dev_tx_queue_start,
7143         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7144         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7145         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7146         .rxq_info_get           = hns3_rxq_info_get,
7147         .txq_info_get           = hns3_txq_info_get,
7148         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7149         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7150         .flow_ctrl_get          = hns3_flow_ctrl_get,
7151         .flow_ctrl_set          = hns3_flow_ctrl_set,
7152         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7153         .mac_addr_add           = hns3_add_mac_addr,
7154         .mac_addr_remove        = hns3_remove_mac_addr,
7155         .mac_addr_set           = hns3_set_default_mac_addr,
7156         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7157         .link_update            = hns3_dev_link_update,
7158         .rss_hash_update        = hns3_dev_rss_hash_update,
7159         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7160         .reta_update            = hns3_dev_rss_reta_update,
7161         .reta_query             = hns3_dev_rss_reta_query,
7162         .flow_ops_get           = hns3_dev_flow_ops_get,
7163         .vlan_filter_set        = hns3_vlan_filter_set,
7164         .vlan_tpid_set          = hns3_vlan_tpid_set,
7165         .vlan_offload_set       = hns3_vlan_offload_set,
7166         .vlan_pvid_set          = hns3_vlan_pvid_set,
7167         .get_reg                = hns3_get_regs,
7168         .get_module_info        = hns3_get_module_info,
7169         .get_module_eeprom      = hns3_get_module_eeprom,
7170         .get_dcb_info           = hns3_get_dcb_info,
7171         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7172         .fec_get_capability     = hns3_fec_get_capability,
7173         .fec_get                = hns3_fec_get,
7174         .fec_set                = hns3_fec_set,
7175         .tm_ops_get             = hns3_tm_ops_get,
7176         .tx_done_cleanup        = hns3_tx_done_cleanup,
7177         .timesync_enable            = hns3_timesync_enable,
7178         .timesync_disable           = hns3_timesync_disable,
7179         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7180         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7181         .timesync_adjust_time       = hns3_timesync_adjust_time,
7182         .timesync_read_time         = hns3_timesync_read_time,
7183         .timesync_write_time        = hns3_timesync_write_time,
7184 };
7185
7186 static const struct hns3_reset_ops hns3_reset_ops = {
7187         .reset_service       = hns3_reset_service,
7188         .stop_service        = hns3_stop_service,
7189         .prepare_reset       = hns3_prepare_reset,
7190         .wait_hardware_ready = hns3_wait_hardware_ready,
7191         .reinit_dev          = hns3_reinit_dev,
7192         .restore_conf        = hns3_restore_conf,
7193         .start_service       = hns3_start_service,
7194 };
7195
7196 static int
7197 hns3_dev_init(struct rte_eth_dev *eth_dev)
7198 {
7199         struct hns3_adapter *hns = eth_dev->data->dev_private;
7200         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7201         struct rte_ether_addr *eth_addr;
7202         struct hns3_hw *hw = &hns->hw;
7203         int ret;
7204
7205         PMD_INIT_FUNC_TRACE();
7206
7207         eth_dev->process_private = (struct hns3_process_private *)
7208             rte_zmalloc_socket("hns3_filter_list",
7209                                sizeof(struct hns3_process_private),
7210                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7211         if (eth_dev->process_private == NULL) {
7212                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7213                 return -ENOMEM;
7214         }
7215         /* initialize flow filter lists */
7216         hns3_filterlist_init(eth_dev);
7217
7218         hns3_set_rxtx_function(eth_dev);
7219         eth_dev->dev_ops = &hns3_eth_dev_ops;
7220         eth_dev->rx_queue_count = hns3_rx_queue_count;
7221         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7222                 ret = hns3_mp_init_secondary();
7223                 if (ret) {
7224                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7225                                      "process, ret = %d", ret);
7226                         goto err_mp_init_secondary;
7227                 }
7228
7229                 hw->secondary_cnt++;
7230                 return 0;
7231         }
7232
7233         ret = hns3_mp_init_primary();
7234         if (ret) {
7235                 PMD_INIT_LOG(ERR,
7236                              "Failed to init for primary process, ret = %d",
7237                              ret);
7238                 goto err_mp_init_primary;
7239         }
7240
7241         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7242         hns->is_vf = false;
7243         hw->data = eth_dev->data;
7244         hns3_parse_devargs(eth_dev);
7245
7246         /*
7247          * Set default max packet size according to the mtu
7248          * default vale in DPDK frame.
7249          */
7250         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7251
7252         ret = hns3_reset_init(hw);
7253         if (ret)
7254                 goto err_init_reset;
7255         hw->reset.ops = &hns3_reset_ops;
7256
7257         ret = hns3_init_pf(eth_dev);
7258         if (ret) {
7259                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7260                 goto err_init_pf;
7261         }
7262
7263         /* Allocate memory for storing MAC addresses */
7264         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7265                                                sizeof(struct rte_ether_addr) *
7266                                                HNS3_UC_MACADDR_NUM, 0);
7267         if (eth_dev->data->mac_addrs == NULL) {
7268                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7269                              "to store MAC addresses",
7270                              sizeof(struct rte_ether_addr) *
7271                              HNS3_UC_MACADDR_NUM);
7272                 ret = -ENOMEM;
7273                 goto err_rte_zmalloc;
7274         }
7275
7276         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7277         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7278                 rte_eth_random_addr(hw->mac.mac_addr);
7279                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7280                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7281                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7282                           "unicast address, using random MAC address %s",
7283                           mac_str);
7284         }
7285         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7286                             &eth_dev->data->mac_addrs[0]);
7287
7288         hw->adapter_state = HNS3_NIC_INITIALIZED;
7289
7290         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7291                             SCHEDULE_PENDING) {
7292                 hns3_err(hw, "Reschedule reset service after dev_init");
7293                 hns3_schedule_reset(hns);
7294         } else {
7295                 /* IMP will wait ready flag before reset */
7296                 hns3_notify_reset_ready(hw, false);
7297         }
7298
7299         hns3_info(hw, "hns3 dev initialization successful!");
7300         return 0;
7301
7302 err_rte_zmalloc:
7303         hns3_uninit_pf(eth_dev);
7304
7305 err_init_pf:
7306         rte_free(hw->reset.wait_data);
7307
7308 err_init_reset:
7309         hns3_mp_uninit_primary();
7310
7311 err_mp_init_primary:
7312 err_mp_init_secondary:
7313         eth_dev->dev_ops = NULL;
7314         eth_dev->rx_pkt_burst = NULL;
7315         eth_dev->rx_descriptor_status = NULL;
7316         eth_dev->tx_pkt_burst = NULL;
7317         eth_dev->tx_pkt_prepare = NULL;
7318         eth_dev->tx_descriptor_status = NULL;
7319         rte_free(eth_dev->process_private);
7320         eth_dev->process_private = NULL;
7321         return ret;
7322 }
7323
7324 static int
7325 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7326 {
7327         struct hns3_adapter *hns = eth_dev->data->dev_private;
7328         struct hns3_hw *hw = &hns->hw;
7329
7330         PMD_INIT_FUNC_TRACE();
7331
7332         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7333                 rte_free(eth_dev->process_private);
7334                 eth_dev->process_private = NULL;
7335                 return 0;
7336         }
7337
7338         if (hw->adapter_state < HNS3_NIC_CLOSING)
7339                 hns3_dev_close(eth_dev);
7340
7341         hw->adapter_state = HNS3_NIC_REMOVED;
7342         return 0;
7343 }
7344
7345 static int
7346 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7347                    struct rte_pci_device *pci_dev)
7348 {
7349         return rte_eth_dev_pci_generic_probe(pci_dev,
7350                                              sizeof(struct hns3_adapter),
7351                                              hns3_dev_init);
7352 }
7353
7354 static int
7355 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7356 {
7357         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7358 }
7359
7360 static const struct rte_pci_id pci_id_hns3_map[] = {
7361         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7362         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7363         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7364         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7365         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7366         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7367         { .vendor_id = 0, }, /* sentinel */
7368 };
7369
7370 static struct rte_pci_driver rte_hns3_pmd = {
7371         .id_table = pci_id_hns3_map,
7372         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7373         .probe = eth_hns3_pci_probe,
7374         .remove = eth_hns3_pci_remove,
7375 };
7376
7377 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7378 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7379 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7380 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7381                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7382                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
7383 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7384 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);