drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_INVALID_PVID               0xFFFF
  23
  24 #define HNS3_FILTER_TYPE_VF             0
  25 #define HNS3_FILTER_TYPE_PORT           1
  26 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  27 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  28 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  29 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  30 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  31 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  32                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  33 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  35
  36 /* Reset related Registers */
  37 #define HNS3_GLOBAL_RESET_BIT           0
  38 #define HNS3_CORE_RESET_BIT             1
  39 #define HNS3_IMP_RESET_BIT              2
  40 #define HNS3_FUN_RST_ING_B              0
  41
  42 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  44 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  46
  47 #define HNS3_RESET_WAIT_MS      100
  48 #define HNS3_RESET_WAIT_CNT     200
  49
  50 /* FEC mode order defined in HNS3 hardware */
  51 #define HNS3_HW_FEC_MODE_NOFEC  0
  52 #define HNS3_HW_FEC_MODE_BASER  1
  53 #define HNS3_HW_FEC_MODE_RS     2
  54
  55 enum hns3_evt_cause {
  56         HNS3_VECTOR0_EVENT_RST,
  57         HNS3_VECTOR0_EVENT_MBX,
  58         HNS3_VECTOR0_EVENT_ERR,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  96
  97 static int hns3_add_mc_addr(struct hns3_hw *hw,
  98                             struct rte_ether_addr *mac_addr);
  99 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_restore_fec(struct hns3_hw *hw);
 102 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 103
 104 void hns3_ether_format_addr(char *buf, uint16_t size,
 105                             const struct rte_ether_addr *ether_addr)
 106 {
 107         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 108                 ether_addr->addr_bytes[0],
 109                 ether_addr->addr_bytes[4],
 110                 ether_addr->addr_bytes[5]);
 111 }
 112
 113 static void
 114 hns3_pf_disable_irq0(struct hns3_hw *hw)
 115 {
 116         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 117 }
 118
 119 static void
 120 hns3_pf_enable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 123 }
 124
 125 static enum hns3_evt_cause
 126 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 127                           uint32_t *vec_val)
 128 {
 129         struct hns3_hw *hw = &hns->hw;
 130
 131         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 132         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 133         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 134         if (!is_delay) {
 135                 hw->reset.stats.imp_cnt++;
 136                 hns3_warn(hw, "IMP reset detected, clear reset status");
 137         } else {
 138                 hns3_schedule_delayed_reset(hns);
 139                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 140         }
 141
 142         return HNS3_VECTOR0_EVENT_RST;
 143 }
 144
 145 static enum hns3_evt_cause
 146 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 147                              uint32_t *vec_val)
 148 {
 149         struct hns3_hw *hw = &hns->hw;
 150
 151         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 152         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 153         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 154         if (!is_delay) {
 155                 hw->reset.stats.global_cnt++;
 156                 hns3_warn(hw, "Global reset detected, clear reset status");
 157         } else {
 158                 hns3_schedule_delayed_reset(hns);
 159                 hns3_warn(hw,
 160                           "Global reset detected, don't clear reset status");
 161         }
 162
 163         return HNS3_VECTOR0_EVENT_RST;
 164 }
 165
 166 static enum hns3_evt_cause
 167 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 168 {
 169         struct hns3_hw *hw = &hns->hw;
 170         uint32_t vector0_int_stats;
 171         uint32_t cmdq_src_val;
 172         uint32_t hw_err_src_reg;
 173         uint32_t val;
 174         enum hns3_evt_cause ret;
 175         bool is_delay;
 176
 177         /* fetch the events from their corresponding regs */
 178         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 179         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 180         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 181
 182         is_delay = clearval == NULL ? true : false;
 183         /*
 184          * Assumption: If by any chance reset and mailbox events are reported
 185          * together then we will only process reset event and defer the
 186          * processing of the mailbox events. Since, we would have not cleared
 187          * RX CMDQ event this time we would receive again another interrupt
 188          * from H/W just for the mailbox.
 189          */
 190         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 191                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 192                 goto out;
 193         }
 194
 195         /* Global reset */
 196         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 197                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 198                 goto out;
 199         }
 200
 201         /* check for vector0 msix event source */
 202         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 203             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 204                 val = vector0_int_stats | hw_err_src_reg;
 205                 ret = HNS3_VECTOR0_EVENT_ERR;
 206                 goto out;
 207         }
 208
 209         /* check for vector0 mailbox(=CMDQ RX) event source */
 210         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 211                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 212                 val = cmdq_src_val;
 213                 ret = HNS3_VECTOR0_EVENT_MBX;
 214                 goto out;
 215         }
 216
 217         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 218                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 219                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static void
 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 231 {
 232         if (event_type == HNS3_VECTOR0_EVENT_RST)
 233                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 234         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 235                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 236 }
 237
 238 static void
 239 hns3_clear_all_event_cause(struct hns3_hw *hw)
 240 {
 241         uint32_t vector0_int_stats;
 242         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 243
 244         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 245                 hns3_warn(hw, "Probe during IMP reset interrupt");
 246
 247         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 248                 hns3_warn(hw, "Probe during Global reset interrupt");
 249
 250         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 251                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 252                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 254         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 255 }
 256
 257 static void
 258 hns3_interrupt_handler(void *param)
 259 {
 260         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 261         struct hns3_adapter *hns = dev->data->dev_private;
 262         struct hns3_hw *hw = &hns->hw;
 263         enum hns3_evt_cause event_cause;
 264         uint32_t clearval = 0;
 265
 266         /* Disable interrupt */
 267         hns3_pf_disable_irq0(hw);
 268
 269         event_cause = hns3_check_event_cause(hns, &clearval);
 270         /* vector 0 interrupt is shared with reset and mailbox source events. */
 271         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 272                 hns3_warn(hw, "Received err interrupt");
 273                 hns3_handle_msix_error(hns, &hw->reset.request);
 274                 hns3_handle_ras_error(hns, &hw->reset.request);
 275                 hns3_schedule_reset(hns);
 276         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 277                 hns3_warn(hw, "Received reset interrupt");
 278                 hns3_schedule_reset(hns);
 279         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 280                 hns3_dev_handle_mbx_msg(hw);
 281         else
 282                 hns3_err(hw, "Received unknown event");
 283
 284         hns3_clear_event_cause(hw, event_cause, clearval);
 285         /* Enable interrupt if it is not cause by reset */
 286         hns3_pf_enable_irq0(hw);
 287 }
 288
 289 static int
 290 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 291 {
 292 #define HNS3_VLAN_ID_OFFSET_STEP        160
 293 #define HNS3_VLAN_BYTE_SIZE             8
 294         struct hns3_vlan_filter_pf_cfg_cmd *req;
 295         struct hns3_hw *hw = &hns->hw;
 296         uint8_t vlan_offset_byte_val;
 297         struct hns3_cmd_desc desc;
 298         uint8_t vlan_offset_byte;
 299         uint8_t vlan_offset_base;
 300         int ret;
 301
 302         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 303
 304         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 305         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 306                            HNS3_VLAN_BYTE_SIZE;
 307         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 308
 309         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 310         req->vlan_offset = vlan_offset_base;
 311         req->vlan_cfg = on ? 0 : 1;
 312         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 313
 314         ret = hns3_cmd_send(hw, &desc, 1);
 315         if (ret)
 316                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 317                          vlan_id, ret);
 318
 319         return ret;
 320 }
 321
 322 static void
 323 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 324 {
 325         struct hns3_user_vlan_table *vlan_entry;
 326         struct hns3_pf *pf = &hns->pf;
 327
 328         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 329                 if (vlan_entry->vlan_id == vlan_id) {
 330                         if (vlan_entry->hd_tbl_status)
 331                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 332                         LIST_REMOVE(vlan_entry, next);
 333                         rte_free(vlan_entry);
 334                         break;
 335                 }
 336         }
 337 }
 338
 339 static void
 340 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 341                         bool writen_to_tbl)
 342 {
 343         struct hns3_user_vlan_table *vlan_entry;
 344         struct hns3_hw *hw = &hns->hw;
 345         struct hns3_pf *pf = &hns->pf;
 346
 347         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 348                 if (vlan_entry->vlan_id == vlan_id)
 349                         return;
 350         }
 351
 352         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 353         if (vlan_entry == NULL) {
 354                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 355                 return;
 356         }
 357
 358         vlan_entry->hd_tbl_status = writen_to_tbl;
 359         vlan_entry->vlan_id = vlan_id;
 360
 361         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 362 }
 363
 364 static int
 365 hns3_restore_vlan_table(struct hns3_adapter *hns)
 366 {
 367         struct hns3_user_vlan_table *vlan_entry;
 368         struct hns3_hw *hw = &hns->hw;
 369         struct hns3_pf *pf = &hns->pf;
 370         uint16_t vlan_id;
 371         int ret = 0;
 372
 373         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 374                 return hns3_vlan_pvid_configure(hns,
 375                                                 hw->port_base_vlan_cfg.pvid, 1);
 376
 377         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 378                 if (vlan_entry->hd_tbl_status) {
 379                         vlan_id = vlan_entry->vlan_id;
 380                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 381                         if (ret)
 382                                 break;
 383                 }
 384         }
 385
 386         return ret;
 387 }
 388
 389 static int
 390 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 391 {
 392         struct hns3_hw *hw = &hns->hw;
 393         bool writen_to_tbl = false;
 394         int ret = 0;
 395
 396         /*
 397          * When vlan filter is enabled, hardware regards packets without vlan
 398          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 399          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 400          */
 401         if (on == 0 && vlan_id == 0)
 402                 return 0;
 403
 404         /*
 405          * When port base vlan enabled, we use port base vlan as the vlan
 406          * filter condition. In this case, we don't update vlan filter table
 407          * when user add new vlan or remove exist vlan, just update the
 408          * vlan list. The vlan id in vlan list will be writen in vlan filter
 409          * table until port base vlan disabled
 410          */
 411         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 412                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 413                 writen_to_tbl = true;
 414         }
 415
 416         if (ret == 0) {
 417                 if (on)
 418                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 419                 else
 420                         hns3_rm_dev_vlan_table(hns, vlan_id);
 421         }
 422         return ret;
 423 }
 424
 425 static int
 426 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 427 {
 428         struct hns3_adapter *hns = dev->data->dev_private;
 429         struct hns3_hw *hw = &hns->hw;
 430         int ret;
 431
 432         rte_spinlock_lock(&hw->lock);
 433         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 434         rte_spinlock_unlock(&hw->lock);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 440                          uint16_t tpid)
 441 {
 442         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 443         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 444         struct hns3_hw *hw = &hns->hw;
 445         struct hns3_cmd_desc desc;
 446         int ret;
 447
 448         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 449              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 450                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 451                 return -EINVAL;
 452         }
 453
 454         if (tpid != RTE_ETHER_TYPE_VLAN) {
 455                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 456                 return -EINVAL;
 457         }
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 460         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 461
 462         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 463                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 464                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 465         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 466                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 467                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 468                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470         }
 471
 472         ret = hns3_cmd_send(hw, &desc, 1);
 473         if (ret) {
 474                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 475                          ret);
 476                 return ret;
 477         }
 478
 479         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 480
 481         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 482         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 483         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 488                          ret);
 489         return ret;
 490 }
 491
 492 static int
 493 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 494                    uint16_t tpid)
 495 {
 496         struct hns3_adapter *hns = dev->data->dev_private;
 497         struct hns3_hw *hw = &hns->hw;
 498         int ret;
 499
 500         rte_spinlock_lock(&hw->lock);
 501         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 502         rte_spinlock_unlock(&hw->lock);
 503         return ret;
 504 }
 505
 506 static int
 507 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 508                              struct hns3_rx_vtag_cfg *vcfg)
 509 {
 510         struct hns3_vport_vtag_rx_cfg_cmd *req;
 511         struct hns3_hw *hw = &hns->hw;
 512         struct hns3_cmd_desc desc;
 513         uint16_t vport_id;
 514         uint8_t bitmap;
 515         int ret;
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 518
 519         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 520         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 521                      vcfg->strip_tag1_en ? 1 : 0);
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 523                      vcfg->strip_tag2_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 525                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 527                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 528
 529         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 530         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 531                      vcfg->strip_tag1_discard_en ? 1 : 0);
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 533                      vcfg->strip_tag2_discard_en ? 1 : 0);
 534         /*
 535          * In current version VF is not supported when PF is driven by DPDK
 536          * driver, just need to configure parameters for PF vport.
 537          */
 538         vport_id = HNS3_PF_FUNC_ID;
 539         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 540         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 541         req->vf_bitmap[req->vf_offset] = bitmap;
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 546         return ret;
 547 }
 548
 549 static void
 550 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 551                            struct hns3_rx_vtag_cfg *vcfg)
 552 {
 553         struct hns3_pf *pf = &hns->pf;
 554         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 555 }
 556
 557 static void
 558 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 559                            struct hns3_tx_vtag_cfg *vcfg)
 560 {
 561         struct hns3_pf *pf = &hns->pf;
 562         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 563 }
 564
 565 static int
 566 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 567 {
 568         struct hns3_rx_vtag_cfg rxvlan_cfg;
 569         struct hns3_hw *hw = &hns->hw;
 570         int ret;
 571
 572         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 573                 rxvlan_cfg.strip_tag1_en = false;
 574                 rxvlan_cfg.strip_tag2_en = enable;
 575                 rxvlan_cfg.strip_tag2_discard_en = false;
 576         } else {
 577                 rxvlan_cfg.strip_tag1_en = enable;
 578                 rxvlan_cfg.strip_tag2_en = true;
 579                 rxvlan_cfg.strip_tag2_discard_en = true;
 580         }
 581
 582         rxvlan_cfg.strip_tag1_discard_en = false;
 583         rxvlan_cfg.vlan1_vlan_prionly = false;
 584         rxvlan_cfg.vlan2_vlan_prionly = false;
 585         rxvlan_cfg.rx_vlan_offload_en = enable;
 586
 587         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 588         if (ret) {
 589                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 590                 return ret;
 591         }
 592
 593         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 600                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 601 {
 602         struct hns3_vlan_filter_ctrl_cmd *req;
 603         struct hns3_cmd_desc desc;
 604         int ret;
 605
 606         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 607
 608         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 609         req->vlan_type = vlan_type;
 610         req->vlan_fe = filter_en ? fe_type : 0;
 611         req->vf_id = vf_id;
 612
 613         ret = hns3_cmd_send(hw, &desc, 1);
 614         if (ret)
 615                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 616
 617         return ret;
 618 }
 619
 620 static int
 621 hns3_vlan_filter_init(struct hns3_adapter *hns)
 622 {
 623         struct hns3_hw *hw = &hns->hw;
 624         int ret;
 625
 626         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 627                                         HNS3_FILTER_FE_EGRESS, false,
 628                                         HNS3_PF_FUNC_ID);
 629         if (ret) {
 630                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 631                 return ret;
 632         }
 633
 634         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 635                                         HNS3_FILTER_FE_INGRESS, false,
 636                                         HNS3_PF_FUNC_ID);
 637         if (ret)
 638                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 639
 640         return ret;
 641 }
 642
 643 static int
 644 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 645 {
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 650                                         HNS3_FILTER_FE_INGRESS, enable,
 651                                         HNS3_PF_FUNC_ID);
 652         if (ret)
 653                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 654                          enable ? "enable" : "disable", ret);
 655
 656         return ret;
 657 }
 658
 659 static int
 660 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         struct rte_eth_rxmode *rxmode;
 665         unsigned int tmp_mask;
 666         bool enable;
 667         int ret = 0;
 668
 669         rte_spinlock_lock(&hw->lock);
 670         rxmode = &dev->data->dev_conf.rxmode;
 671         tmp_mask = (unsigned int)mask;
 672         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 673                 /* ignore vlan filter configuration during promiscuous mode */
 674                 if (!dev->data->promiscuous) {
 675                         /* Enable or disable VLAN filter */
 676                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 677                                  true : false;
 678
 679                         ret = hns3_enable_vlan_filter(hns, enable);
 680                         if (ret) {
 681                                 rte_spinlock_unlock(&hw->lock);
 682                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 683                                          enable ? "enable" : "disable", ret);
 684                                 return ret;
 685                         }
 686                 }
 687         }
 688
 689         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 690                 /* Enable or disable VLAN stripping */
 691                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 692                     true : false;
 693
 694                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 695                 if (ret) {
 696                         rte_spinlock_unlock(&hw->lock);
 697                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 698                                  enable ? "enable" : "disable", ret);
 699                         return ret;
 700                 }
 701         }
 702
 703         rte_spinlock_unlock(&hw->lock);
 704
 705         return ret;
 706 }
 707
 708 static int
 709 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 710                              struct hns3_tx_vtag_cfg *vcfg)
 711 {
 712         struct hns3_vport_vtag_tx_cfg_cmd *req;
 713         struct hns3_cmd_desc desc;
 714         struct hns3_hw *hw = &hns->hw;
 715         uint16_t vport_id;
 716         uint8_t bitmap;
 717         int ret;
 718
 719         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 720
 721         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 722         req->def_vlan_tag1 = vcfg->default_tag1;
 723         req->def_vlan_tag2 = vcfg->default_tag2;
 724         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 725                      vcfg->accept_tag1 ? 1 : 0);
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 727                      vcfg->accept_untag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 729                      vcfg->accept_tag2 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 731                      vcfg->accept_untag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 733                      vcfg->insert_tag1_en ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 735                      vcfg->insert_tag2_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 737
 738         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 739         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 740                      vcfg->tag_shift_mode_en ? 1 : 0);
 741
 742         /*
 743          * In current version VF is not supported when PF is driven by DPDK
 744          * driver, just need to configure parameters for PF vport.
 745          */
 746         vport_id = HNS3_PF_FUNC_ID;
 747         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 748         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 749         req->vf_bitmap[req->vf_offset] = bitmap;
 750
 751         ret = hns3_cmd_send(hw, &desc, 1);
 752         if (ret)
 753                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 754
 755         return ret;
 756 }
 757
 758 static int
 759 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 760                      uint16_t pvid)
 761 {
 762         struct hns3_hw *hw = &hns->hw;
 763         struct hns3_tx_vtag_cfg txvlan_cfg;
 764         int ret;
 765
 766         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 767                 txvlan_cfg.accept_tag1 = true;
 768                 txvlan_cfg.insert_tag1_en = false;
 769                 txvlan_cfg.default_tag1 = 0;
 770         } else {
 771                 txvlan_cfg.accept_tag1 =
 772                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 773                 txvlan_cfg.insert_tag1_en = true;
 774                 txvlan_cfg.default_tag1 = pvid;
 775         }
 776
 777         txvlan_cfg.accept_untag1 = true;
 778         txvlan_cfg.accept_tag2 = true;
 779         txvlan_cfg.accept_untag2 = true;
 780         txvlan_cfg.insert_tag2_en = false;
 781         txvlan_cfg.default_tag2 = 0;
 782         txvlan_cfg.tag_shift_mode_en = true;
 783
 784         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 785         if (ret) {
 786                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 787                          ret);
 788                 return ret;
 789         }
 790
 791         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 792         return ret;
 793 }
 794
 795
 796 static void
 797 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 798 {
 799         struct hns3_user_vlan_table *vlan_entry;
 800         struct hns3_pf *pf = &hns->pf;
 801
 802         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 803                 if (vlan_entry->hd_tbl_status) {
 804                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 805                         vlan_entry->hd_tbl_status = false;
 806                 }
 807         }
 808
 809         if (is_del_list) {
 810                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 811                 while (vlan_entry) {
 812                         LIST_REMOVE(vlan_entry, next);
 813                         rte_free(vlan_entry);
 814                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 815                 }
 816         }
 817 }
 818
 819 static void
 820 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 821 {
 822         struct hns3_user_vlan_table *vlan_entry;
 823         struct hns3_pf *pf = &hns->pf;
 824
 825         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 826                 if (!vlan_entry->hd_tbl_status) {
 827                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 828                         vlan_entry->hd_tbl_status = true;
 829                 }
 830         }
 831 }
 832
 833 static void
 834 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 835 {
 836         struct hns3_hw *hw = &hns->hw;
 837         int ret;
 838
 839         hns3_rm_all_vlan_table(hns, true);
 840         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 841                 ret = hns3_set_port_vlan_filter(hns,
 842                                                 hw->port_base_vlan_cfg.pvid, 0);
 843                 if (ret) {
 844                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 845                                  ret);
 846                         return;
 847                 }
 848         }
 849 }
 850
 851 static int
 852 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 853                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 854 {
 855         struct hns3_hw *hw = &hns->hw;
 856         uint16_t old_pvid;
 857         int ret;
 858
 859         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 860                 old_pvid = hw->port_base_vlan_cfg.pvid;
 861                 if (old_pvid != HNS3_INVALID_PVID) {
 862                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 863                         if (ret) {
 864                                 hns3_err(hw, "failed to remove old pvid %u, "
 865                                                 "ret = %d", old_pvid, ret);
 866                                 return ret;
 867                         }
 868                 }
 869
 870                 hns3_rm_all_vlan_table(hns, false);
 871                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 872                 if (ret) {
 873                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 874                                         new_pvid, ret);
 875                         return ret;
 876                 }
 877         } else {
 878                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 879                 if (ret) {
 880                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 881                                         new_pvid, ret);
 882                         return ret;
 883                 }
 884
 885                 hns3_add_all_vlan_table(hns);
 886         }
 887         return 0;
 888 }
 889
 890 static int
 891 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 892 {
 893         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 894         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 895         bool rx_strip_en;
 896         int ret;
 897
 898         rx_strip_en = old_cfg->rx_vlan_offload_en;
 899         if (on) {
 900                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 901                 rx_vlan_cfg.strip_tag2_en = true;
 902                 rx_vlan_cfg.strip_tag2_discard_en = true;
 903         } else {
 904                 rx_vlan_cfg.strip_tag1_en = false;
 905                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 906                 rx_vlan_cfg.strip_tag2_discard_en = false;
 907         }
 908         rx_vlan_cfg.strip_tag1_discard_en = false;
 909         rx_vlan_cfg.vlan1_vlan_prionly = false;
 910         rx_vlan_cfg.vlan2_vlan_prionly = false;
 911         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 912
 913         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 914         if (ret)
 915                 return ret;
 916
 917         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 918         return ret;
 919 }
 920
 921 static int
 922 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 923 {
 924         struct hns3_hw *hw = &hns->hw;
 925         uint16_t port_base_vlan_state;
 926         int ret;
 927
 928         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 929                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 930                         hns3_warn(hw, "Invalid operation! As current pvid set "
 931                                   "is %u, disable pvid %u is invalid",
 932                                   hw->port_base_vlan_cfg.pvid, pvid);
 933                 return 0;
 934         }
 935
 936         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 937                                     HNS3_PORT_BASE_VLAN_DISABLE;
 938         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 939         if (ret) {
 940                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 941                          ret);
 942                 return ret;
 943         }
 944
 945         ret = hns3_en_pvid_strip(hns, on);
 946         if (ret) {
 947                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 948                          "ret = %d", ret);
 949                 return ret;
 950         }
 951
 952         if (pvid == HNS3_INVALID_PVID)
 953                 goto out;
 954         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 955         if (ret) {
 956                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 957                          ret);
 958                 return ret;
 959         }
 960
 961 out:
 962         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 963         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 964         return ret;
 965 }
 966
 967 static int
 968 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 969 {
 970         struct hns3_adapter *hns = dev->data->dev_private;
 971         struct hns3_hw *hw = &hns->hw;
 972         bool pvid_en_state_change;
 973         uint16_t pvid_state;
 974         int ret;
 975
 976         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 977                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 978                          RTE_ETHER_MAX_VLAN_ID);
 979                 return -EINVAL;
 980         }
 981
 982         /*
 983          * If PVID configuration state change, should refresh the PVID
 984          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 985          */
 986         pvid_state = hw->port_base_vlan_cfg.state;
 987         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 988             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 989                 pvid_en_state_change = false;
 990         else
 991                 pvid_en_state_change = true;
 992
 993         rte_spinlock_lock(&hw->lock);
 994         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 995         rte_spinlock_unlock(&hw->lock);
 996         if (ret)
 997                 return ret;
 998         /*
 999          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1000          * need be processed by PMD driver.
1001          */
1002         if (pvid_en_state_change &&
1003             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1004                 hns3_update_all_queues_pvid_proc_en(hw);
1005
1006         return 0;
1007 }
1008
1009 static int
1010 hns3_default_vlan_config(struct hns3_adapter *hns)
1011 {
1012         struct hns3_hw *hw = &hns->hw;
1013         int ret;
1014
1015         /*
1016          * When vlan filter is enabled, hardware regards packets without vlan
1017          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1018          * table, packets without vlan won't be received. So, add vlan 0 as
1019          * the default vlan.
1020          */
1021         ret = hns3_vlan_filter_configure(hns, 0, 1);
1022         if (ret)
1023                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1024         return ret;
1025 }
1026
1027 static int
1028 hns3_init_vlan_config(struct hns3_adapter *hns)
1029 {
1030         struct hns3_hw *hw = &hns->hw;
1031         int ret;
1032
1033         /*
1034          * This function can be called in the initialization and reset process,
1035          * when in reset process, it means that hardware had been reseted
1036          * successfully and we need to restore the hardware configuration to
1037          * ensure that the hardware configuration remains unchanged before and
1038          * after reset.
1039          */
1040         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1041                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1042                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1043         }
1044
1045         ret = hns3_vlan_filter_init(hns);
1046         if (ret) {
1047                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1048                 return ret;
1049         }
1050
1051         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1052                                        RTE_ETHER_TYPE_VLAN);
1053         if (ret) {
1054                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1055                 return ret;
1056         }
1057
1058         /*
1059          * When in the reinit dev stage of the reset process, the following
1060          * vlan-related configurations may differ from those at initialization,
1061          * we will restore configurations to hardware in hns3_restore_vlan_table
1062          * and hns3_restore_vlan_conf later.
1063          */
1064         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1065                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1066                 if (ret) {
1067                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1068                         return ret;
1069                 }
1070
1071                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1072                 if (ret) {
1073                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1074                                  ret);
1075                         return ret;
1076                 }
1077         }
1078
1079         return hns3_default_vlan_config(hns);
1080 }
1081
1082 static int
1083 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1084 {
1085         struct hns3_pf *pf = &hns->pf;
1086         struct hns3_hw *hw = &hns->hw;
1087         uint64_t offloads;
1088         bool enable;
1089         int ret;
1090
1091         if (!hw->data->promiscuous) {
1092                 /* restore vlan filter states */
1093                 offloads = hw->data->dev_conf.rxmode.offloads;
1094                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1095                 ret = hns3_enable_vlan_filter(hns, enable);
1096                 if (ret) {
1097                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1098                                  "ret = %d", ret);
1099                         return ret;
1100                 }
1101         }
1102
1103         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1104         if (ret) {
1105                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1106                 return ret;
1107         }
1108
1109         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1110         if (ret)
1111                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1112
1113         return ret;
1114 }
1115
1116 static int
1117 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1118 {
1119         struct hns3_adapter *hns = dev->data->dev_private;
1120         struct rte_eth_dev_data *data = dev->data;
1121         struct rte_eth_txmode *txmode;
1122         struct hns3_hw *hw = &hns->hw;
1123         int mask;
1124         int ret;
1125
1126         txmode = &data->dev_conf.txmode;
1127         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1128                 hns3_warn(hw,
1129                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1130                           "configuration is not supported! Ignore these two "
1131                           "parameters: hw_vlan_reject_tagged(%u), "
1132                           "hw_vlan_reject_untagged(%u)",
1133                           txmode->hw_vlan_reject_tagged,
1134                           txmode->hw_vlan_reject_untagged);
1135
1136         /* Apply vlan offload setting */
1137         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1138         ret = hns3_vlan_offload_set(dev, mask);
1139         if (ret) {
1140                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1141                          ret);
1142                 return ret;
1143         }
1144
1145         /*
1146          * If pvid config is not set in rte_eth_conf, driver needn't to set
1147          * VLAN pvid related configuration to hardware.
1148          */
1149         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1150                 return 0;
1151
1152         /* Apply pvid setting */
1153         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1154                                  txmode->hw_vlan_insert_pvid);
1155         if (ret)
1156                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1157                          txmode->pvid, ret);
1158
1159         return ret;
1160 }
1161
1162 static int
1163 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1164                 unsigned int tso_mss_max)
1165 {
1166         struct hns3_cfg_tso_status_cmd *req;
1167         struct hns3_cmd_desc desc;
1168         uint16_t tso_mss;
1169
1170         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1171
1172         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1173
1174         tso_mss = 0;
1175         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1176                        tso_mss_min);
1177         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1178
1179         tso_mss = 0;
1180         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1181                        tso_mss_max);
1182         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1183
1184         return hns3_cmd_send(hw, &desc, 1);
1185 }
1186
1187 static int
1188 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1189                    uint16_t *allocated_size, bool is_alloc)
1190 {
1191         struct hns3_umv_spc_alc_cmd *req;
1192         struct hns3_cmd_desc desc;
1193         int ret;
1194
1195         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1196         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1197         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1198         req->space_size = rte_cpu_to_le_32(space_size);
1199
1200         ret = hns3_cmd_send(hw, &desc, 1);
1201         if (ret) {
1202                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1203                              is_alloc ? "allocate" : "free", ret);
1204                 return ret;
1205         }
1206
1207         if (is_alloc && allocated_size)
1208                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1209
1210         return 0;
1211 }
1212
1213 static int
1214 hns3_init_umv_space(struct hns3_hw *hw)
1215 {
1216         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1217         struct hns3_pf *pf = &hns->pf;
1218         uint16_t allocated_size = 0;
1219         int ret;
1220
1221         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1222                                  true);
1223         if (ret)
1224                 return ret;
1225
1226         if (allocated_size < pf->wanted_umv_size)
1227                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1228                              pf->wanted_umv_size, allocated_size);
1229
1230         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1231                                                 pf->wanted_umv_size;
1232         pf->used_umv_size = 0;
1233         return 0;
1234 }
1235
1236 static int
1237 hns3_uninit_umv_space(struct hns3_hw *hw)
1238 {
1239         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1240         struct hns3_pf *pf = &hns->pf;
1241         int ret;
1242
1243         if (pf->max_umv_size == 0)
1244                 return 0;
1245
1246         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1247         if (ret)
1248                 return ret;
1249
1250         pf->max_umv_size = 0;
1251
1252         return 0;
1253 }
1254
1255 static bool
1256 hns3_is_umv_space_full(struct hns3_hw *hw)
1257 {
1258         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1259         struct hns3_pf *pf = &hns->pf;
1260         bool is_full;
1261
1262         is_full = (pf->used_umv_size >= pf->max_umv_size);
1263
1264         return is_full;
1265 }
1266
1267 static void
1268 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1269 {
1270         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1271         struct hns3_pf *pf = &hns->pf;
1272
1273         if (is_free) {
1274                 if (pf->used_umv_size > 0)
1275                         pf->used_umv_size--;
1276         } else
1277                 pf->used_umv_size++;
1278 }
1279
1280 static void
1281 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1282                       const uint8_t *addr, bool is_mc)
1283 {
1284         const unsigned char *mac_addr = addr;
1285         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1286                             ((uint32_t)mac_addr[2] << 16) |
1287                             ((uint32_t)mac_addr[1] << 8) |
1288                             (uint32_t)mac_addr[0];
1289         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1290
1291         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1292         if (is_mc) {
1293                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1294                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1295                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1296         }
1297
1298         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1299         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1300 }
1301
1302 static int
1303 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1304                              uint8_t resp_code,
1305                              enum hns3_mac_vlan_tbl_opcode op)
1306 {
1307         if (cmdq_resp) {
1308                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1309                          cmdq_resp);
1310                 return -EIO;
1311         }
1312
1313         if (op == HNS3_MAC_VLAN_ADD) {
1314                 if (resp_code == 0 || resp_code == 1) {
1315                         return 0;
1316                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1317                         hns3_err(hw, "add mac addr failed for uc_overflow");
1318                         return -ENOSPC;
1319                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1320                         hns3_err(hw, "add mac addr failed for mc_overflow");
1321                         return -ENOSPC;
1322                 }
1323
1324                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1325                          resp_code);
1326                 return -EIO;
1327         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1328                 if (resp_code == 0) {
1329                         return 0;
1330                 } else if (resp_code == 1) {
1331                         hns3_dbg(hw, "remove mac addr failed for miss");
1332                         return -ENOENT;
1333                 }
1334
1335                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1336                          resp_code);
1337                 return -EIO;
1338         } else if (op == HNS3_MAC_VLAN_LKUP) {
1339                 if (resp_code == 0) {
1340                         return 0;
1341                 } else if (resp_code == 1) {
1342                         hns3_dbg(hw, "lookup mac addr failed for miss");
1343                         return -ENOENT;
1344                 }
1345
1346                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1347                          resp_code);
1348                 return -EIO;
1349         }
1350
1351         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1352                  op);
1353
1354         return -EINVAL;
1355 }
1356
1357 static int
1358 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1359                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1360                          struct hns3_cmd_desc *desc, bool is_mc)
1361 {
1362         uint8_t resp_code;
1363         uint16_t retval;
1364         int ret;
1365
1366         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1367         if (is_mc) {
1368                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1369                 memcpy(desc[0].data, req,
1370                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1371                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1372                                           true);
1373                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1374                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1375                                           true);
1376                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1377         } else {
1378                 memcpy(desc[0].data, req,
1379                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1380                 ret = hns3_cmd_send(hw, desc, 1);
1381         }
1382         if (ret) {
1383                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1384                          ret);
1385                 return ret;
1386         }
1387         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1388         retval = rte_le_to_cpu_16(desc[0].retval);
1389
1390         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1391                                             HNS3_MAC_VLAN_LKUP);
1392 }
1393
1394 static int
1395 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1396                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1397                       struct hns3_cmd_desc *mc_desc)
1398 {
1399         uint8_t resp_code;
1400         uint16_t retval;
1401         int cfg_status;
1402         int ret;
1403
1404         if (mc_desc == NULL) {
1405                 struct hns3_cmd_desc desc;
1406
1407                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1408                 memcpy(desc.data, req,
1409                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1410                 ret = hns3_cmd_send(hw, &desc, 1);
1411                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1412                 retval = rte_le_to_cpu_16(desc.retval);
1413
1414                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1415                                                           HNS3_MAC_VLAN_ADD);
1416         } else {
1417                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1418                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1419                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1420                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1422                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1423                 memcpy(mc_desc[0].data, req,
1424                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1425                 mc_desc[0].retval = 0;
1426                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1427                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1428                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1429
1430                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1431                                                           HNS3_MAC_VLAN_ADD);
1432         }
1433
1434         if (ret) {
1435                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1436                 return ret;
1437         }
1438
1439         return cfg_status;
1440 }
1441
1442 static int
1443 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1444                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1445 {
1446         struct hns3_cmd_desc desc;
1447         uint8_t resp_code;
1448         uint16_t retval;
1449         int ret;
1450
1451         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1452
1453         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1454
1455         ret = hns3_cmd_send(hw, &desc, 1);
1456         if (ret) {
1457                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1458                 return ret;
1459         }
1460         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1461         retval = rte_le_to_cpu_16(desc.retval);
1462
1463         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464                                             HNS3_MAC_VLAN_REMOVE);
1465 }
1466
1467 static int
1468 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1469 {
1470         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1471         struct hns3_mac_vlan_tbl_entry_cmd req;
1472         struct hns3_pf *pf = &hns->pf;
1473         struct hns3_cmd_desc desc[3];
1474         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1475         uint16_t egress_port = 0;
1476         uint8_t vf_id;
1477         int ret;
1478
1479         /* check if mac addr is valid */
1480         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1481                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1482                                       mac_addr);
1483                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1484                          mac_str);
1485                 return -EINVAL;
1486         }
1487
1488         memset(&req, 0, sizeof(req));
1489
1490         /*
1491          * In current version VF is not supported when PF is driven by DPDK
1492          * driver, just need to configure parameters for PF vport.
1493          */
1494         vf_id = HNS3_PF_FUNC_ID;
1495         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1496                        HNS3_MAC_EPORT_VFID_S, vf_id);
1497
1498         req.egress_port = rte_cpu_to_le_16(egress_port);
1499
1500         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1501
1502         /*
1503          * Lookup the mac address in the mac_vlan table, and add
1504          * it if the entry is inexistent. Repeated unicast entry
1505          * is not allowed in the mac vlan table.
1506          */
1507         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1508         if (ret == -ENOENT) {
1509                 if (!hns3_is_umv_space_full(hw)) {
1510                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1511                         if (!ret)
1512                                 hns3_update_umv_space(hw, false);
1513                         return ret;
1514                 }
1515
1516                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1517
1518                 return -ENOSPC;
1519         }
1520
1521         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1522
1523         /* check if we just hit the duplicate */
1524         if (ret == 0) {
1525                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1526                 return 0;
1527         }
1528
1529         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1530                  mac_str);
1531
1532         return ret;
1533 }
1534
1535 static int
1536 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1537 {
1538         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1539         struct rte_ether_addr *addr;
1540         int ret;
1541         int i;
1542
1543         for (i = 0; i < hw->mc_addrs_num; i++) {
1544                 addr = &hw->mc_addrs[i];
1545                 /* Check if there are duplicate addresses */
1546                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1547                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1548                                               addr);
1549                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1550                                  "(%s) is added by the set_mc_mac_addr_list "
1551                                  "API", mac_str);
1552                         return -EINVAL;
1553                 }
1554         }
1555
1556         ret = hns3_add_mc_addr(hw, mac_addr);
1557         if (ret) {
1558                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1559                                       mac_addr);
1560                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1561                          mac_str, ret);
1562         }
1563         return ret;
1564 }
1565
1566 static int
1567 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1568 {
1569         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1570         int ret;
1571
1572         ret = hns3_remove_mc_addr(hw, mac_addr);
1573         if (ret) {
1574                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1575                                       mac_addr);
1576                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1577                          mac_str, ret);
1578         }
1579         return ret;
1580 }
1581
1582 static int
1583 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1584                   uint32_t idx, __rte_unused uint32_t pool)
1585 {
1586         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         /*
1593          * In hns3 network engine adding UC and MC mac address with different
1594          * commands with firmware. We need to determine whether the input
1595          * address is a UC or a MC address to call different commands.
1596          * By the way, it is recommended calling the API function named
1597          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1598          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1599          * may affect the specifications of UC mac addresses.
1600          */
1601         if (rte_is_multicast_ether_addr(mac_addr))
1602                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1603         else
1604                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1605
1606         if (ret) {
1607                 rte_spinlock_unlock(&hw->lock);
1608                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1609                                       mac_addr);
1610                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1611                          ret);
1612                 return ret;
1613         }
1614
1615         if (idx == 0)
1616                 hw->mac.default_addr_setted = true;
1617         rte_spinlock_unlock(&hw->lock);
1618
1619         return ret;
1620 }
1621
1622 static int
1623 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1624 {
1625         struct hns3_mac_vlan_tbl_entry_cmd req;
1626         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1627         int ret;
1628
1629         /* check if mac addr is valid */
1630         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1631                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1632                                       mac_addr);
1633                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1634                          mac_str);
1635                 return -EINVAL;
1636         }
1637
1638         memset(&req, 0, sizeof(req));
1639         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1640         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1641         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1642         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1643                 return 0;
1644         else if (ret == 0)
1645                 hns3_update_umv_space(hw, true);
1646
1647         return ret;
1648 }
1649
1650 static void
1651 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1652 {
1653         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         /* index will be checked by upper level rte interface */
1655         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1656         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1657         int ret;
1658
1659         rte_spinlock_lock(&hw->lock);
1660
1661         if (rte_is_multicast_ether_addr(mac_addr))
1662                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1663         else
1664                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1665         rte_spinlock_unlock(&hw->lock);
1666         if (ret) {
1667                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668                                       mac_addr);
1669                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1670                          ret);
1671         }
1672 }
1673
1674 static int
1675 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1676                           struct rte_ether_addr *mac_addr)
1677 {
1678         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679         struct rte_ether_addr *oaddr;
1680         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1681         bool default_addr_setted;
1682         bool rm_succes = false;
1683         int ret, ret_val;
1684
1685         /*
1686          * It has been guaranteed that input parameter named mac_addr is valid
1687          * address in the rte layer of DPDK framework.
1688          */
1689         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1690         default_addr_setted = hw->mac.default_addr_setted;
1691         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1692                 return 0;
1693
1694         rte_spinlock_lock(&hw->lock);
1695         if (default_addr_setted) {
1696                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1697                 if (ret) {
1698                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1699                                               oaddr);
1700                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1701                                   mac_str, ret);
1702                         rm_succes = false;
1703                 } else
1704                         rm_succes = true;
1705         }
1706
1707         ret = hns3_add_uc_addr_common(hw, mac_addr);
1708         if (ret) {
1709                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                       mac_addr);
1711                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1712                 goto err_add_uc_addr;
1713         }
1714
1715         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1716         if (ret) {
1717                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1718                 goto err_pause_addr_cfg;
1719         }
1720
1721         rte_ether_addr_copy(mac_addr,
1722                             (struct rte_ether_addr *)hw->mac.mac_addr);
1723         hw->mac.default_addr_setted = true;
1724         rte_spinlock_unlock(&hw->lock);
1725
1726         return 0;
1727
1728 err_pause_addr_cfg:
1729         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1730         if (ret_val) {
1731                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1732                                       mac_addr);
1733                 hns3_warn(hw,
1734                           "Failed to roll back to del setted mac addr(%s): %d",
1735                           mac_str, ret_val);
1736         }
1737
1738 err_add_uc_addr:
1739         if (rm_succes) {
1740                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1741                 if (ret_val) {
1742                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1743                                               oaddr);
1744                         hns3_warn(hw,
1745                                   "Failed to restore old uc mac addr(%s): %d",
1746                                   mac_str, ret_val);
1747                         hw->mac.default_addr_setted = false;
1748                 }
1749         }
1750         rte_spinlock_unlock(&hw->lock);
1751
1752         return ret;
1753 }
1754
1755 static int
1756 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1757 {
1758         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759         struct hns3_hw *hw = &hns->hw;
1760         struct rte_ether_addr *addr;
1761         int err = 0;
1762         int ret;
1763         int i;
1764
1765         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1766                 addr = &hw->data->mac_addrs[i];
1767                 if (rte_is_zero_ether_addr(addr))
1768                         continue;
1769                 if (rte_is_multicast_ether_addr(addr))
1770                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1771                               hns3_add_mc_addr(hw, addr);
1772                 else
1773                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1774                               hns3_add_uc_addr_common(hw, addr);
1775
1776                 if (ret) {
1777                         err = ret;
1778                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1779                                               addr);
1780                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1781                                  "ret = %d.", del ? "remove" : "restore",
1782                                  mac_str, i, ret);
1783                 }
1784         }
1785         return err;
1786 }
1787
1788 static void
1789 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1790 {
1791 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1792         uint8_t word_num;
1793         uint8_t bit_num;
1794
1795         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1796                 word_num = vfid / 32;
1797                 bit_num = vfid % 32;
1798                 if (clr)
1799                         desc[1].data[word_num] &=
1800                             rte_cpu_to_le_32(~(1UL << bit_num));
1801                 else
1802                         desc[1].data[word_num] |=
1803                             rte_cpu_to_le_32(1UL << bit_num);
1804         } else {
1805                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1806                 bit_num = vfid % 32;
1807                 if (clr)
1808                         desc[2].data[word_num] &=
1809                             rte_cpu_to_le_32(~(1UL << bit_num));
1810                 else
1811                         desc[2].data[word_num] |=
1812                             rte_cpu_to_le_32(1UL << bit_num);
1813         }
1814 }
1815
1816 static int
1817 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1818 {
1819         struct hns3_mac_vlan_tbl_entry_cmd req;
1820         struct hns3_cmd_desc desc[3];
1821         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1822         uint8_t vf_id;
1823         int ret;
1824
1825         /* Check if mac addr is valid */
1826         if (!rte_is_multicast_ether_addr(mac_addr)) {
1827                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1828                                       mac_addr);
1829                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1830                          mac_str);
1831                 return -EINVAL;
1832         }
1833
1834         memset(&req, 0, sizeof(req));
1835         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1836         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1837         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1838         if (ret) {
1839                 /* This mac addr do not exist, add new entry for it */
1840                 memset(desc[0].data, 0, sizeof(desc[0].data));
1841                 memset(desc[1].data, 0, sizeof(desc[0].data));
1842                 memset(desc[2].data, 0, sizeof(desc[0].data));
1843         }
1844
1845         /*
1846          * In current version VF is not supported when PF is driven by DPDK
1847          * driver, just need to configure parameters for PF vport.
1848          */
1849         vf_id = HNS3_PF_FUNC_ID;
1850         hns3_update_desc_vfid(desc, vf_id, false);
1851         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1852         if (ret) {
1853                 if (ret == -ENOSPC)
1854                         hns3_err(hw, "mc mac vlan table is full");
1855                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1856                                       mac_addr);
1857                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1858         }
1859
1860         return ret;
1861 }
1862
1863 static int
1864 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1865 {
1866         struct hns3_mac_vlan_tbl_entry_cmd req;
1867         struct hns3_cmd_desc desc[3];
1868         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1869         uint8_t vf_id;
1870         int ret;
1871
1872         /* Check if mac addr is valid */
1873         if (!rte_is_multicast_ether_addr(mac_addr)) {
1874                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1875                                       mac_addr);
1876                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1877                          mac_str);
1878                 return -EINVAL;
1879         }
1880
1881         memset(&req, 0, sizeof(req));
1882         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1883         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1884         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1885         if (ret == 0) {
1886                 /*
1887                  * This mac addr exist, remove this handle's VFID for it.
1888                  * In current version VF is not supported when PF is driven by
1889                  * DPDK driver, just need to configure parameters for PF vport.
1890                  */
1891                 vf_id = HNS3_PF_FUNC_ID;
1892                 hns3_update_desc_vfid(desc, vf_id, true);
1893
1894                 /* All the vfid is zero, so need to delete this entry */
1895                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1896         } else if (ret == -ENOENT) {
1897                 /* This mac addr doesn't exist. */
1898                 return 0;
1899         }
1900
1901         if (ret) {
1902                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1903                                       mac_addr);
1904                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1905         }
1906
1907         return ret;
1908 }
1909
1910 static int
1911 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1912                            struct rte_ether_addr *mc_addr_set,
1913                            uint32_t nb_mc_addr)
1914 {
1915         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1916         struct rte_ether_addr *addr;
1917         uint32_t i;
1918         uint32_t j;
1919
1920         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1921                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1922                          "invalid. valid range: 0~%d",
1923                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1924                 return -EINVAL;
1925         }
1926
1927         /* Check if input mac addresses are valid */
1928         for (i = 0; i < nb_mc_addr; i++) {
1929                 addr = &mc_addr_set[i];
1930                 if (!rte_is_multicast_ether_addr(addr)) {
1931                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1932                                               addr);
1933                         hns3_err(hw,
1934                                  "failed to set mc mac addr, addr(%s) invalid.",
1935                                  mac_str);
1936                         return -EINVAL;
1937                 }
1938
1939                 /* Check if there are duplicate addresses */
1940                 for (j = i + 1; j < nb_mc_addr; j++) {
1941                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1942                                 hns3_ether_format_addr(mac_str,
1943                                                       RTE_ETHER_ADDR_FMT_SIZE,
1944                                                       addr);
1945                                 hns3_err(hw, "failed to set mc mac addr, "
1946                                          "addrs invalid. two same addrs(%s).",
1947                                          mac_str);
1948                                 return -EINVAL;
1949                         }
1950                 }
1951
1952                 /*
1953                  * Check if there are duplicate addresses between mac_addrs
1954                  * and mc_addr_set
1955                  */
1956                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1957                         if (rte_is_same_ether_addr(addr,
1958                                                    &hw->data->mac_addrs[j])) {
1959                                 hns3_ether_format_addr(mac_str,
1960                                                       RTE_ETHER_ADDR_FMT_SIZE,
1961                                                       addr);
1962                                 hns3_err(hw, "failed to set mc mac addr, "
1963                                          "addrs invalid. addrs(%s) has already "
1964                                          "configured in mac_addr add API",
1965                                          mac_str);
1966                                 return -EINVAL;
1967                         }
1968                 }
1969         }
1970
1971         return 0;
1972 }
1973
1974 static void
1975 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1976                            struct rte_ether_addr *mc_addr_set,
1977                            int mc_addr_num,
1978                            struct rte_ether_addr *reserved_addr_list,
1979                            int *reserved_addr_num,
1980                            struct rte_ether_addr *add_addr_list,
1981                            int *add_addr_num,
1982                            struct rte_ether_addr *rm_addr_list,
1983                            int *rm_addr_num)
1984 {
1985         struct rte_ether_addr *addr;
1986         int current_addr_num;
1987         int reserved_num = 0;
1988         int add_num = 0;
1989         int rm_num = 0;
1990         int num;
1991         int i;
1992         int j;
1993         bool same_addr;
1994
1995         /* Calculate the mc mac address list that should be removed */
1996         current_addr_num = hw->mc_addrs_num;
1997         for (i = 0; i < current_addr_num; i++) {
1998                 addr = &hw->mc_addrs[i];
1999                 same_addr = false;
2000                 for (j = 0; j < mc_addr_num; j++) {
2001                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2002                                 same_addr = true;
2003                                 break;
2004                         }
2005                 }
2006
2007                 if (!same_addr) {
2008                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2009                         rm_num++;
2010                 } else {
2011                         rte_ether_addr_copy(addr,
2012                                             &reserved_addr_list[reserved_num]);
2013                         reserved_num++;
2014                 }
2015         }
2016
2017         /* Calculate the mc mac address list that should be added */
2018         for (i = 0; i < mc_addr_num; i++) {
2019                 addr = &mc_addr_set[i];
2020                 same_addr = false;
2021                 for (j = 0; j < current_addr_num; j++) {
2022                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2023                                 same_addr = true;
2024                                 break;
2025                         }
2026                 }
2027
2028                 if (!same_addr) {
2029                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2030                         add_num++;
2031                 }
2032         }
2033
2034         /* Reorder the mc mac address list maintained by driver */
2035         for (i = 0; i < reserved_num; i++)
2036                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2037
2038         for (i = 0; i < rm_num; i++) {
2039                 num = reserved_num + i;
2040                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2041         }
2042
2043         *reserved_addr_num = reserved_num;
2044         *add_addr_num = add_num;
2045         *rm_addr_num = rm_num;
2046 }
2047
2048 static int
2049 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2050                           struct rte_ether_addr *mc_addr_set,
2051                           uint32_t nb_mc_addr)
2052 {
2053         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2055         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2056         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr *addr;
2058         int reserved_addr_num;
2059         int add_addr_num;
2060         int rm_addr_num;
2061         int mc_addr_num;
2062         int num;
2063         int ret;
2064         int i;
2065
2066         /* Check if input parameters are valid */
2067         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2068         if (ret)
2069                 return ret;
2070
2071         rte_spinlock_lock(&hw->lock);
2072
2073         /*
2074          * Calculate the mc mac address lists those should be removed and be
2075          * added, Reorder the mc mac address list maintained by driver.
2076          */
2077         mc_addr_num = (int)nb_mc_addr;
2078         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2079                                    reserved_addr_list, &reserved_addr_num,
2080                                    add_addr_list, &add_addr_num,
2081                                    rm_addr_list, &rm_addr_num);
2082
2083         /* Remove mc mac addresses */
2084         for (i = 0; i < rm_addr_num; i++) {
2085                 num = rm_addr_num - i - 1;
2086                 addr = &rm_addr_list[num];
2087                 ret = hns3_remove_mc_addr(hw, addr);
2088                 if (ret) {
2089                         rte_spinlock_unlock(&hw->lock);
2090                         return ret;
2091                 }
2092                 hw->mc_addrs_num--;
2093         }
2094
2095         /* Add mc mac addresses */
2096         for (i = 0; i < add_addr_num; i++) {
2097                 addr = &add_addr_list[i];
2098                 ret = hns3_add_mc_addr(hw, addr);
2099                 if (ret) {
2100                         rte_spinlock_unlock(&hw->lock);
2101                         return ret;
2102                 }
2103
2104                 num = reserved_addr_num + i;
2105                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2106                 hw->mc_addrs_num++;
2107         }
2108         rte_spinlock_unlock(&hw->lock);
2109
2110         return 0;
2111 }
2112
2113 static int
2114 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2115 {
2116         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2117         struct hns3_hw *hw = &hns->hw;
2118         struct rte_ether_addr *addr;
2119         int err = 0;
2120         int ret;
2121         int i;
2122
2123         for (i = 0; i < hw->mc_addrs_num; i++) {
2124                 addr = &hw->mc_addrs[i];
2125                 if (!rte_is_multicast_ether_addr(addr))
2126                         continue;
2127                 if (del)
2128                         ret = hns3_remove_mc_addr(hw, addr);
2129                 else
2130                         ret = hns3_add_mc_addr(hw, addr);
2131                 if (ret) {
2132                         err = ret;
2133                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2134                                               addr);
2135                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2136                                  del ? "Remove" : "Restore", mac_str, ret);
2137                 }
2138         }
2139         return err;
2140 }
2141
2142 static int
2143 hns3_check_mq_mode(struct rte_eth_dev *dev)
2144 {
2145         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2146         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2147         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2150         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2151         uint8_t num_tc;
2152         int max_tc = 0;
2153         int i;
2154
2155         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2156         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2157
2158         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2159                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2160                          "rx_mq_mode = %d", rx_mq_mode);
2161                 return -EINVAL;
2162         }
2163
2164         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2165             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2166                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2167                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2168                          rx_mq_mode, tx_mq_mode);
2169                 return -EINVAL;
2170         }
2171
2172         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2173                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2174                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2175                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2176                         return -EINVAL;
2177                 }
2178
2179                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2180                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2181                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2182                                  "nb_tcs(%d) != %d or %d in rx direction.",
2183                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2184                         return -EINVAL;
2185                 }
2186
2187                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2188                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2189                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2190                         return -EINVAL;
2191                 }
2192
2193                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2194                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2195                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2196                                          "is not equal to one in tx direction.",
2197                                          i, dcb_rx_conf->dcb_tc[i]);
2198                                 return -EINVAL;
2199                         }
2200                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2201                                 max_tc = dcb_rx_conf->dcb_tc[i];
2202                 }
2203
2204                 num_tc = max_tc + 1;
2205                 if (num_tc > dcb_rx_conf->nb_tcs) {
2206                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2207                                  num_tc, dcb_rx_conf->nb_tcs);
2208                         return -EINVAL;
2209                 }
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int
2216 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2217 {
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219
2220         if (!hns3_dev_dcb_supported(hw)) {
2221                 hns3_err(hw, "this port does not support dcb configurations.");
2222                 return -EOPNOTSUPP;
2223         }
2224
2225         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2226                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2227                 return -EOPNOTSUPP;
2228         }
2229
2230         /* Check multiple queue mode */
2231         return hns3_check_mq_mode(dev);
2232 }
2233
2234 static int
2235 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2236                            enum hns3_ring_type queue_type, uint16_t queue_id)
2237 {
2238         struct hns3_cmd_desc desc;
2239         struct hns3_ctrl_vector_chain_cmd *req =
2240                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2241         enum hns3_cmd_status status;
2242         enum hns3_opcode_type op;
2243         uint16_t tqp_type_and_id = 0;
2244         uint16_t type;
2245         uint16_t gl;
2246
2247         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2248         hns3_cmd_setup_basic_desc(&desc, op, false);
2249         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2250                                               HNS3_TQP_INT_ID_L_S);
2251         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2252                                               HNS3_TQP_INT_ID_H_S);
2253
2254         if (queue_type == HNS3_RING_TYPE_RX)
2255                 gl = HNS3_RING_GL_RX;
2256         else
2257                 gl = HNS3_RING_GL_TX;
2258
2259         type = queue_type;
2260
2261         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2262                        type);
2263         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2264         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2265                        gl);
2266         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2267         req->int_cause_num = 1;
2268         status = hns3_cmd_send(hw, &desc, 1);
2269         if (status) {
2270                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2271                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2272                 return status;
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int
2279 hns3_init_ring_with_vector(struct hns3_hw *hw)
2280 {
2281         uint16_t vec;
2282         int ret;
2283         int i;
2284
2285         /*
2286          * In hns3 network engine, vector 0 is always the misc interrupt of this
2287          * function, vector 1~N can be used respectively for the queues of the
2288          * function. Tx and Rx queues with the same number share the interrupt
2289          * vector. In the initialization clearing the all hardware mapping
2290          * relationship configurations between queues and interrupt vectors is
2291          * needed, so some error caused by the residual configurations, such as
2292          * the unexpected Tx interrupt, can be avoid.
2293          */
2294         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2295         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2296                 vec = vec - 1; /* the last interrupt is reserved */
2297         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2298         for (i = 0; i < hw->intr_tqps_num; i++) {
2299                 /*
2300                  * Set gap limiter/rate limiter/quanity limiter algorithm
2301                  * configuration for interrupt coalesce of queue's interrupt.
2302                  */
2303                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2304                                        HNS3_TQP_INTR_GL_DEFAULT);
2305                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2306                                        HNS3_TQP_INTR_GL_DEFAULT);
2307                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2308                 /*
2309                  * QL(quantity limiter) is not used currently, just set 0 to
2310                  * close it.
2311                  */
2312                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2313
2314                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2315                                                  HNS3_RING_TYPE_TX, i);
2316                 if (ret) {
2317                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2318                                           "vector: %u, ret=%d", i, vec, ret);
2319                         return ret;
2320                 }
2321
2322                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2323                                                  HNS3_RING_TYPE_RX, i);
2324                 if (ret) {
2325                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2326                                           "vector: %u, ret=%d", i, vec, ret);
2327                         return ret;
2328                 }
2329         }
2330
2331         return 0;
2332 }
2333
2334 static int
2335 hns3_dev_configure(struct rte_eth_dev *dev)
2336 {
2337         struct hns3_adapter *hns = dev->data->dev_private;
2338         struct rte_eth_conf *conf = &dev->data->dev_conf;
2339         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2340         struct hns3_hw *hw = &hns->hw;
2341         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2342         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2343         struct rte_eth_rss_conf rss_conf;
2344         uint16_t mtu;
2345         bool gro_en;
2346         int ret;
2347
2348         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2349
2350         /*
2351          * Some versions of hardware network engine does not support
2352          * individually enable/disable/reset the Tx or Rx queue. These devices
2353          * must enable/disable/reset Tx and Rx queues at the same time. When the
2354          * numbers of Tx queues allocated by upper applications are not equal to
2355          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2356          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2357          * work as usual. But these fake queues are imperceptible, and can not
2358          * be used by upper applications.
2359          */
2360         if (!hns3_dev_indep_txrx_supported(hw)) {
2361                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2362                 if (ret) {
2363                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2364                                  ret);
2365                         return ret;
2366                 }
2367         }
2368
2369         hw->adapter_state = HNS3_NIC_CONFIGURING;
2370         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2371                 hns3_err(hw, "setting link speed/duplex not supported");
2372                 ret = -EINVAL;
2373                 goto cfg_err;
2374         }
2375
2376         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2377                 ret = hns3_check_dcb_cfg(dev);
2378                 if (ret)
2379                         goto cfg_err;
2380         }
2381
2382         /* When RSS is not configured, redirect the packet queue 0 */
2383         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2384                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2385                 rss_conf = conf->rx_adv_conf.rss_conf;
2386                 hw->rss_dis_flag = false;
2387                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2388                 if (ret)
2389                         goto cfg_err;
2390         }
2391
2392         /*
2393          * If jumbo frames are enabled, MTU needs to be refreshed
2394          * according to the maximum RX packet length.
2395          */
2396         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2397                 /*
2398                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2399                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2400                  * can safely assign to "uint16_t" type variable.
2401                  */
2402                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2403                 ret = hns3_dev_mtu_set(dev, mtu);
2404                 if (ret)
2405                         goto cfg_err;
2406                 dev->data->mtu = mtu;
2407         }
2408
2409         ret = hns3_dev_configure_vlan(dev);
2410         if (ret)
2411                 goto cfg_err;
2412
2413         /* config hardware GRO */
2414         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2415         ret = hns3_config_gro(hw, gro_en);
2416         if (ret)
2417                 goto cfg_err;
2418
2419         hns->rx_simple_allowed = true;
2420         hns->rx_vec_allowed = true;
2421         hns->tx_simple_allowed = true;
2422         hns->tx_vec_allowed = true;
2423
2424         hns3_init_rx_ptype_tble(dev);
2425         hw->adapter_state = HNS3_NIC_CONFIGURED;
2426
2427         return 0;
2428
2429 cfg_err:
2430         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2431         hw->adapter_state = HNS3_NIC_INITIALIZED;
2432
2433         return ret;
2434 }
2435
2436 static int
2437 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2438 {
2439         struct hns3_config_max_frm_size_cmd *req;
2440         struct hns3_cmd_desc desc;
2441
2442         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2443
2444         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2445         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2446         req->min_frm_size = RTE_ETHER_MIN_LEN;
2447
2448         return hns3_cmd_send(hw, &desc, 1);
2449 }
2450
2451 static int
2452 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2453 {
2454         int ret;
2455
2456         ret = hns3_set_mac_mtu(hw, mps);
2457         if (ret) {
2458                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2459                 return ret;
2460         }
2461
2462         ret = hns3_buffer_alloc(hw);
2463         if (ret)
2464                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2465
2466         return ret;
2467 }
2468
2469 static int
2470 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2471 {
2472         struct hns3_adapter *hns = dev->data->dev_private;
2473         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2474         struct hns3_hw *hw = &hns->hw;
2475         bool is_jumbo_frame;
2476         int ret;
2477
2478         if (dev->data->dev_started) {
2479                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2480                          "before configuration", dev->data->port_id);
2481                 return -EBUSY;
2482         }
2483
2484         rte_spinlock_lock(&hw->lock);
2485         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2486         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2487
2488         /*
2489          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2490          * assign to "uint16_t" type variable.
2491          */
2492         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2493         if (ret) {
2494                 rte_spinlock_unlock(&hw->lock);
2495                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2496                          dev->data->port_id, mtu, ret);
2497                 return ret;
2498         }
2499         hns->pf.mps = (uint16_t)frame_size;
2500         if (is_jumbo_frame)
2501                 dev->data->dev_conf.rxmode.offloads |=
2502                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2503         else
2504                 dev->data->dev_conf.rxmode.offloads &=
2505                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2506         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2507         rte_spinlock_unlock(&hw->lock);
2508
2509         return 0;
2510 }
2511
2512 int
2513 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2514 {
2515         struct hns3_adapter *hns = eth_dev->data->dev_private;
2516         struct hns3_hw *hw = &hns->hw;
2517         uint16_t queue_num = hw->tqps_num;
2518
2519         /*
2520          * In interrupt mode, 'max_rx_queues' is set based on the number of
2521          * MSI-X interrupt resources of the hardware.
2522          */
2523         if (hw->data->dev_conf.intr_conf.rxq == 1)
2524                 queue_num = hw->intr_tqps_num;
2525
2526         info->max_rx_queues = queue_num;
2527         info->max_tx_queues = hw->tqps_num;
2528         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2529         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2530         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2531         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2532         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2533         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2534                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2535                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2536                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2537                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2538                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2539                                  DEV_RX_OFFLOAD_KEEP_CRC |
2540                                  DEV_RX_OFFLOAD_SCATTER |
2541                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2542                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2543                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2544                                  DEV_RX_OFFLOAD_RSS_HASH |
2545                                  DEV_RX_OFFLOAD_TCP_LRO);
2546         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2547                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2548                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2549                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2550                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2551                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2552                                  DEV_TX_OFFLOAD_TCP_TSO |
2553                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2554                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2555                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2556                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2557                                  hns3_txvlan_cap_get(hw));
2558
2559         if (hns3_dev_indep_txrx_supported(hw))
2560                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2561                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2562
2563         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2564                 .nb_max = HNS3_MAX_RING_DESC,
2565                 .nb_min = HNS3_MIN_RING_DESC,
2566                 .nb_align = HNS3_ALIGN_RING_DESC,
2567         };
2568
2569         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2570                 .nb_max = HNS3_MAX_RING_DESC,
2571                 .nb_min = HNS3_MIN_RING_DESC,
2572                 .nb_align = HNS3_ALIGN_RING_DESC,
2573                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2574                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2575         };
2576
2577         info->default_rxconf = (struct rte_eth_rxconf) {
2578                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2579                 /*
2580                  * If there are no available Rx buffer descriptors, incoming
2581                  * packets are always dropped by hardware based on hns3 network
2582                  * engine.
2583                  */
2584                 .rx_drop_en = 1,
2585                 .offloads = 0,
2586         };
2587         info->default_txconf = (struct rte_eth_txconf) {
2588                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2589                 .offloads = 0,
2590         };
2591
2592         info->vmdq_queue_num = 0;
2593
2594         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2595         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2596         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2597
2598         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2599         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2600         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2601         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2602         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2603         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2604
2605         return 0;
2606 }
2607
2608 static int
2609 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2610                     size_t fw_size)
2611 {
2612         struct hns3_adapter *hns = eth_dev->data->dev_private;
2613         struct hns3_hw *hw = &hns->hw;
2614         uint32_t version = hw->fw_version;
2615         int ret;
2616
2617         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2618                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2619                                       HNS3_FW_VERSION_BYTE3_S),
2620                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2621                                       HNS3_FW_VERSION_BYTE2_S),
2622                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2623                                       HNS3_FW_VERSION_BYTE1_S),
2624                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2625                                       HNS3_FW_VERSION_BYTE0_S));
2626         ret += 1; /* add the size of '\0' */
2627         if (fw_size < (uint32_t)ret)
2628                 return ret;
2629         else
2630                 return 0;
2631 }
2632
2633 static int
2634 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2635                      __rte_unused int wait_to_complete)
2636 {
2637         struct hns3_adapter *hns = eth_dev->data->dev_private;
2638         struct hns3_hw *hw = &hns->hw;
2639         struct hns3_mac *mac = &hw->mac;
2640         struct rte_eth_link new_link;
2641
2642         if (!hns3_is_reset_pending(hns)) {
2643                 hns3_update_speed_duplex(eth_dev);
2644                 hns3_update_link_status(hw);
2645         }
2646
2647         memset(&new_link, 0, sizeof(new_link));
2648         switch (mac->link_speed) {
2649         case ETH_SPEED_NUM_10M:
2650         case ETH_SPEED_NUM_100M:
2651         case ETH_SPEED_NUM_1G:
2652         case ETH_SPEED_NUM_10G:
2653         case ETH_SPEED_NUM_25G:
2654         case ETH_SPEED_NUM_40G:
2655         case ETH_SPEED_NUM_50G:
2656         case ETH_SPEED_NUM_100G:
2657         case ETH_SPEED_NUM_200G:
2658                 new_link.link_speed = mac->link_speed;
2659                 break;
2660         default:
2661                 new_link.link_speed = ETH_SPEED_NUM_100M;
2662                 break;
2663         }
2664
2665         new_link.link_duplex = mac->link_duplex;
2666         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2667         new_link.link_autoneg =
2668             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2669
2670         return rte_eth_linkstatus_set(eth_dev, &new_link);
2671 }
2672
2673 static int
2674 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2675 {
2676         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2677         struct hns3_pf *pf = &hns->pf;
2678
2679         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2680                 return -EINVAL;
2681
2682         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2683
2684         return 0;
2685 }
2686
2687 static int
2688 hns3_query_function_status(struct hns3_hw *hw)
2689 {
2690 #define HNS3_QUERY_MAX_CNT              10
2691 #define HNS3_QUERY_SLEEP_MSCOEND        1
2692         struct hns3_func_status_cmd *req;
2693         struct hns3_cmd_desc desc;
2694         int timeout = 0;
2695         int ret;
2696
2697         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2698         req = (struct hns3_func_status_cmd *)desc.data;
2699
2700         do {
2701                 ret = hns3_cmd_send(hw, &desc, 1);
2702                 if (ret) {
2703                         PMD_INIT_LOG(ERR, "query function status failed %d",
2704                                      ret);
2705                         return ret;
2706                 }
2707
2708                 /* Check pf reset is done */
2709                 if (req->pf_state)
2710                         break;
2711
2712                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2713         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2714
2715         return hns3_parse_func_status(hw, req);
2716 }
2717
2718 static int
2719 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2720 {
2721         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2722         struct hns3_pf *pf = &hns->pf;
2723
2724         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2725                 /*
2726                  * The total_tqps_num obtained from firmware is maximum tqp
2727                  * numbers of this port, which should be used for PF and VFs.
2728                  * There is no need for pf to have so many tqp numbers in
2729                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2730                  * coming from config file, is assigned to maximum queue number
2731                  * for the PF of this port by user. So users can modify the
2732                  * maximum queue number of PF according to their own application
2733                  * scenarios, which is more flexible to use. In addition, many
2734                  * memories can be saved due to allocating queue statistics
2735                  * room according to the actual number of queues required. The
2736                  * maximum queue number of PF for network engine with
2737                  * revision_id greater than 0x30 is assigned by config file.
2738                  */
2739                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2740                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2741                                  "must be greater than 0.",
2742                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2743                         return -EINVAL;
2744                 }
2745
2746                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2747                                        hw->total_tqps_num);
2748         } else {
2749                 /*
2750                  * Due to the limitation on the number of PF interrupts
2751                  * available, the maximum queue number assigned to PF on
2752                  * the network engine with revision_id 0x21 is 64.
2753                  */
2754                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2755                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2756         }
2757
2758         return 0;
2759 }
2760
2761 static int
2762 hns3_query_pf_resource(struct hns3_hw *hw)
2763 {
2764         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2765         struct hns3_pf *pf = &hns->pf;
2766         struct hns3_pf_res_cmd *req;
2767         struct hns3_cmd_desc desc;
2768         int ret;
2769
2770         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2771         ret = hns3_cmd_send(hw, &desc, 1);
2772         if (ret) {
2773                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2774                 return ret;
2775         }
2776
2777         req = (struct hns3_pf_res_cmd *)desc.data;
2778         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2779                              rte_le_to_cpu_16(req->ext_tqp_num);
2780         ret = hns3_get_pf_max_tqp_num(hw);
2781         if (ret)
2782                 return ret;
2783
2784         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2785         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2786
2787         if (req->tx_buf_size)
2788                 pf->tx_buf_size =
2789                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2790         else
2791                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2792
2793         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2794
2795         if (req->dv_buf_size)
2796                 pf->dv_buf_size =
2797                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2798         else
2799                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2800
2801         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2802
2803         hw->num_msi =
2804                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2805                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2806
2807         return 0;
2808 }
2809
2810 static void
2811 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2812 {
2813         struct hns3_cfg_param_cmd *req;
2814         uint64_t mac_addr_tmp_high;
2815         uint8_t ext_rss_size_max;
2816         uint64_t mac_addr_tmp;
2817         uint32_t i;
2818
2819         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2820
2821         /* get the configuration */
2822         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2823                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2824         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2825                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2826         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2827                                            HNS3_CFG_TQP_DESC_N_M,
2828                                            HNS3_CFG_TQP_DESC_N_S);
2829
2830         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2831                                        HNS3_CFG_PHY_ADDR_M,
2832                                        HNS3_CFG_PHY_ADDR_S);
2833         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2834                                          HNS3_CFG_MEDIA_TP_M,
2835                                          HNS3_CFG_MEDIA_TP_S);
2836         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2837                                          HNS3_CFG_RX_BUF_LEN_M,
2838                                          HNS3_CFG_RX_BUF_LEN_S);
2839         /* get mac address */
2840         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2841         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2842                                            HNS3_CFG_MAC_ADDR_H_M,
2843                                            HNS3_CFG_MAC_ADDR_H_S);
2844
2845         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2846
2847         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2848                                             HNS3_CFG_DEFAULT_SPEED_M,
2849                                             HNS3_CFG_DEFAULT_SPEED_S);
2850         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2851                                            HNS3_CFG_RSS_SIZE_M,
2852                                            HNS3_CFG_RSS_SIZE_S);
2853
2854         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2855                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2856
2857         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2858         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2859
2860         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2861                                             HNS3_CFG_SPEED_ABILITY_M,
2862                                             HNS3_CFG_SPEED_ABILITY_S);
2863         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2864                                         HNS3_CFG_UMV_TBL_SPACE_M,
2865                                         HNS3_CFG_UMV_TBL_SPACE_S);
2866         if (!cfg->umv_space)
2867                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2868
2869         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2870                                                HNS3_CFG_EXT_RSS_SIZE_M,
2871                                                HNS3_CFG_EXT_RSS_SIZE_S);
2872
2873         /*
2874          * Field ext_rss_size_max obtained from firmware will be more flexible
2875          * for future changes and expansions, which is an exponent of 2, instead
2876          * of reading out directly. If this field is not zero, hns3 PF PMD
2877          * driver uses it as rss_size_max under one TC. Device, whose revision
2878          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2879          * maximum number of queues supported under a TC through this field.
2880          */
2881         if (ext_rss_size_max)
2882                 cfg->rss_size_max = 1U << ext_rss_size_max;
2883 }
2884
2885 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2886  * @hw: pointer to struct hns3_hw
2887  * @hcfg: the config structure to be getted
2888  */
2889 static int
2890 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2891 {
2892         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2893         struct hns3_cfg_param_cmd *req;
2894         uint32_t offset;
2895         uint32_t i;
2896         int ret;
2897
2898         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2899                 offset = 0;
2900                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2901                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2902                                           true);
2903                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2904                                i * HNS3_CFG_RD_LEN_BYTES);
2905                 /* Len should be divided by 4 when send to hardware */
2906                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2907                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2908                 req->offset = rte_cpu_to_le_32(offset);
2909         }
2910
2911         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2912         if (ret) {
2913                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2914                 return ret;
2915         }
2916
2917         hns3_parse_cfg(hcfg, desc);
2918
2919         return 0;
2920 }
2921
2922 static int
2923 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2924 {
2925         switch (speed_cmd) {
2926         case HNS3_CFG_SPEED_10M:
2927                 *speed = ETH_SPEED_NUM_10M;
2928                 break;
2929         case HNS3_CFG_SPEED_100M:
2930                 *speed = ETH_SPEED_NUM_100M;
2931                 break;
2932         case HNS3_CFG_SPEED_1G:
2933                 *speed = ETH_SPEED_NUM_1G;
2934                 break;
2935         case HNS3_CFG_SPEED_10G:
2936                 *speed = ETH_SPEED_NUM_10G;
2937                 break;
2938         case HNS3_CFG_SPEED_25G:
2939                 *speed = ETH_SPEED_NUM_25G;
2940                 break;
2941         case HNS3_CFG_SPEED_40G:
2942                 *speed = ETH_SPEED_NUM_40G;
2943                 break;
2944         case HNS3_CFG_SPEED_50G:
2945                 *speed = ETH_SPEED_NUM_50G;
2946                 break;
2947         case HNS3_CFG_SPEED_100G:
2948                 *speed = ETH_SPEED_NUM_100G;
2949                 break;
2950         case HNS3_CFG_SPEED_200G:
2951                 *speed = ETH_SPEED_NUM_200G;
2952                 break;
2953         default:
2954                 return -EINVAL;
2955         }
2956
2957         return 0;
2958 }
2959
2960 static void
2961 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2962 {
2963         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2964         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2965         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2966         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2967         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2968 }
2969
2970 static void
2971 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2972 {
2973         struct hns3_dev_specs_0_cmd *req0;
2974
2975         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2976
2977         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2978         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2979         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2980         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2981         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2982 }
2983
2984 static int
2985 hns3_query_dev_specifications(struct hns3_hw *hw)
2986 {
2987         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2988         int ret;
2989         int i;
2990
2991         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2992                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2993                                           true);
2994                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2995         }
2996         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2997
2998         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2999         if (ret)
3000                 return ret;
3001
3002         hns3_parse_dev_specifications(hw, desc);
3003
3004         return 0;
3005 }
3006
3007 static int
3008 hns3_get_capability(struct hns3_hw *hw)
3009 {
3010         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3011         struct rte_pci_device *pci_dev;
3012         struct hns3_pf *pf = &hns->pf;
3013         struct rte_eth_dev *eth_dev;
3014         uint16_t device_id;
3015         uint8_t revision;
3016         int ret;
3017
3018         eth_dev = &rte_eth_devices[hw->data->port_id];
3019         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3020         device_id = pci_dev->id.device_id;
3021
3022         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3023             device_id == HNS3_DEV_ID_50GE_RDMA ||
3024             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3025             device_id == HNS3_DEV_ID_200G_RDMA)
3026                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3027
3028         /* Get PCI revision id */
3029         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3030                                   HNS3_PCI_REVISION_ID);
3031         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3032                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3033                              ret);
3034                 return -EIO;
3035         }
3036         hw->revision = revision;
3037
3038         if (revision < PCI_REVISION_ID_HIP09_A) {
3039                 hns3_set_default_dev_specifications(hw);
3040                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3041                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3042                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3043                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3044                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3045                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3046                 hw->rss_info.ipv6_sctp_offload_supported = false;
3047                 return 0;
3048         }
3049
3050         ret = hns3_query_dev_specifications(hw);
3051         if (ret) {
3052                 PMD_INIT_LOG(ERR,
3053                              "failed to query dev specifications, ret = %d",
3054                              ret);
3055                 return ret;
3056         }
3057
3058         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3059         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3060         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3061         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3062         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3063         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3064         hw->rss_info.ipv6_sctp_offload_supported = true;
3065
3066         return 0;
3067 }
3068
3069 static int
3070 hns3_get_board_configuration(struct hns3_hw *hw)
3071 {
3072         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3073         struct hns3_pf *pf = &hns->pf;
3074         struct hns3_cfg cfg;
3075         int ret;
3076
3077         ret = hns3_get_board_cfg(hw, &cfg);
3078         if (ret) {
3079                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3080                 return ret;
3081         }
3082
3083         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3084             !hns3_dev_copper_supported(hw)) {
3085                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3086                 return -EOPNOTSUPP;
3087         }
3088
3089         hw->mac.media_type = cfg.media_type;
3090         hw->rss_size_max = cfg.rss_size_max;
3091         hw->rss_dis_flag = false;
3092         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3093         hw->mac.phy_addr = cfg.phy_addr;
3094         hw->mac.default_addr_setted = false;
3095         hw->num_tx_desc = cfg.tqp_desc_num;
3096         hw->num_rx_desc = cfg.tqp_desc_num;
3097         hw->dcb_info.num_pg = 1;
3098         hw->dcb_info.hw_pfc_map = 0;
3099
3100         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3101         if (ret) {
3102                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3103                              cfg.default_speed, ret);
3104                 return ret;
3105         }
3106
3107         pf->tc_max = cfg.tc_num;
3108         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3109                 PMD_INIT_LOG(WARNING,
3110                              "Get TC num(%u) from flash, set TC num to 1",
3111                              pf->tc_max);
3112                 pf->tc_max = 1;
3113         }
3114
3115         /* Dev does not support DCB */
3116         if (!hns3_dev_dcb_supported(hw)) {
3117                 pf->tc_max = 1;
3118                 pf->pfc_max = 0;
3119         } else
3120                 pf->pfc_max = pf->tc_max;
3121
3122         hw->dcb_info.num_tc = 1;
3123         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3124                                      hw->tqps_num / hw->dcb_info.num_tc);
3125         hns3_set_bit(hw->hw_tc_map, 0, 1);
3126         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3127
3128         pf->wanted_umv_size = cfg.umv_space;
3129
3130         return ret;
3131 }
3132
3133 static int
3134 hns3_get_configuration(struct hns3_hw *hw)
3135 {
3136         int ret;
3137
3138         ret = hns3_query_function_status(hw);
3139         if (ret) {
3140                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3141                 return ret;
3142         }
3143
3144         /* Get device capability */
3145         ret = hns3_get_capability(hw);
3146         if (ret) {
3147                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3148                 return ret;
3149         }
3150
3151         /* Get pf resource */
3152         ret = hns3_query_pf_resource(hw);
3153         if (ret) {
3154                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3155                 return ret;
3156         }
3157
3158         ret = hns3_get_board_configuration(hw);
3159         if (ret) {
3160                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3161                 return ret;
3162         }
3163
3164         ret = hns3_query_dev_fec_info(hw);
3165         if (ret)
3166                 PMD_INIT_LOG(ERR,
3167                              "failed to query FEC information, ret = %d", ret);
3168
3169         return ret;
3170 }
3171
3172 static int
3173 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3174                       uint16_t tqp_vid, bool is_pf)
3175 {
3176         struct hns3_tqp_map_cmd *req;
3177         struct hns3_cmd_desc desc;
3178         int ret;
3179
3180         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3181
3182         req = (struct hns3_tqp_map_cmd *)desc.data;
3183         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3184         req->tqp_vf = func_id;
3185         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3186         if (!is_pf)
3187                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3188         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3189
3190         ret = hns3_cmd_send(hw, &desc, 1);
3191         if (ret)
3192                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3193
3194         return ret;
3195 }
3196
3197 static int
3198 hns3_map_tqp(struct hns3_hw *hw)
3199 {
3200         int ret;
3201         int i;
3202
3203         /*
3204          * In current version, VF is not supported when PF is driven by DPDK
3205          * driver, so we assign total tqps_num tqps allocated to this port
3206          * to PF.
3207          */
3208         for (i = 0; i < hw->total_tqps_num; i++) {
3209                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3210                 if (ret)
3211                         return ret;
3212         }
3213
3214         return 0;
3215 }
3216
3217 static int
3218 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3219 {
3220         struct hns3_config_mac_speed_dup_cmd *req;
3221         struct hns3_cmd_desc desc;
3222         int ret;
3223
3224         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3225
3226         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3227
3228         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3229
3230         switch (speed) {
3231         case ETH_SPEED_NUM_10M:
3232                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3234                 break;
3235         case ETH_SPEED_NUM_100M:
3236                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3238                 break;
3239         case ETH_SPEED_NUM_1G:
3240                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3242                 break;
3243         case ETH_SPEED_NUM_10G:
3244                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3245                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3246                 break;
3247         case ETH_SPEED_NUM_25G:
3248                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3250                 break;
3251         case ETH_SPEED_NUM_40G:
3252                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3253                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3254                 break;
3255         case ETH_SPEED_NUM_50G:
3256                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3257                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3258                 break;
3259         case ETH_SPEED_NUM_100G:
3260                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3261                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3262                 break;
3263         case ETH_SPEED_NUM_200G:
3264                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3265                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3266                 break;
3267         default:
3268                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3269                 return -EINVAL;
3270         }
3271
3272         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3273
3274         ret = hns3_cmd_send(hw, &desc, 1);
3275         if (ret)
3276                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3277
3278         return ret;
3279 }
3280
3281 static int
3282 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3283 {
3284         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3285         struct hns3_pf *pf = &hns->pf;
3286         struct hns3_priv_buf *priv;
3287         uint32_t i, total_size;
3288
3289         total_size = pf->pkt_buf_size;
3290
3291         /* alloc tx buffer for all enabled tc */
3292         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3293                 priv = &buf_alloc->priv_buf[i];
3294
3295                 if (hw->hw_tc_map & BIT(i)) {
3296                         if (total_size < pf->tx_buf_size)
3297                                 return -ENOMEM;
3298
3299                         priv->tx_buf_size = pf->tx_buf_size;
3300                 } else
3301                         priv->tx_buf_size = 0;
3302
3303                 total_size -= priv->tx_buf_size;
3304         }
3305
3306         return 0;
3307 }
3308
3309 static int
3310 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3311 {
3312 /* TX buffer size is unit by 128 byte */
3313 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3314 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3315         struct hns3_tx_buff_alloc_cmd *req;
3316         struct hns3_cmd_desc desc;
3317         uint32_t buf_size;
3318         uint32_t i;
3319         int ret;
3320
3321         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3322
3323         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3324         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3325                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3326
3327                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3328                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3329                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3330         }
3331
3332         ret = hns3_cmd_send(hw, &desc, 1);
3333         if (ret)
3334                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3335
3336         return ret;
3337 }
3338
3339 static int
3340 hns3_get_tc_num(struct hns3_hw *hw)
3341 {
3342         int cnt = 0;
3343         uint8_t i;
3344
3345         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3346                 if (hw->hw_tc_map & BIT(i))
3347                         cnt++;
3348         return cnt;
3349 }
3350
3351 static uint32_t
3352 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3353 {
3354         struct hns3_priv_buf *priv;
3355         uint32_t rx_priv = 0;
3356         int i;
3357
3358         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3359                 priv = &buf_alloc->priv_buf[i];
3360                 if (priv->enable)
3361                         rx_priv += priv->buf_size;
3362         }
3363         return rx_priv;
3364 }
3365
3366 static uint32_t
3367 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3368 {
3369         uint32_t total_tx_size = 0;
3370         uint32_t i;
3371
3372         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3373                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3374
3375         return total_tx_size;
3376 }
3377
3378 /* Get the number of pfc enabled TCs, which have private buffer */
3379 static int
3380 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3381 {
3382         struct hns3_priv_buf *priv;
3383         int cnt = 0;
3384         uint8_t i;
3385
3386         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3387                 priv = &buf_alloc->priv_buf[i];
3388                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3389                         cnt++;
3390         }
3391
3392         return cnt;
3393 }
3394
3395 /* Get the number of pfc disabled TCs, which have private buffer */
3396 static int
3397 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3398                          struct hns3_pkt_buf_alloc *buf_alloc)
3399 {
3400         struct hns3_priv_buf *priv;
3401         int cnt = 0;
3402         uint8_t i;
3403
3404         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3405                 priv = &buf_alloc->priv_buf[i];
3406                 if (hw->hw_tc_map & BIT(i) &&
3407                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3408                         cnt++;
3409         }
3410
3411         return cnt;
3412 }
3413
3414 static bool
3415 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3416                   uint32_t rx_all)
3417 {
3418         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3419         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3420         struct hns3_pf *pf = &hns->pf;
3421         uint32_t shared_buf, aligned_mps;
3422         uint32_t rx_priv;
3423         uint8_t tc_num;
3424         uint8_t i;
3425
3426         tc_num = hns3_get_tc_num(hw);
3427         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3428
3429         if (hns3_dev_dcb_supported(hw))
3430                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3431                                         pf->dv_buf_size;
3432         else
3433                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3434                                         + pf->dv_buf_size;
3435
3436         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3437         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3438                              HNS3_BUF_SIZE_UNIT);
3439
3440         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3441         if (rx_all < rx_priv + shared_std)
3442                 return false;
3443
3444         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3445         buf_alloc->s_buf.buf_size = shared_buf;
3446         if (hns3_dev_dcb_supported(hw)) {
3447                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3448                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3449                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3450                                   HNS3_BUF_SIZE_UNIT);
3451         } else {
3452                 buf_alloc->s_buf.self.high =
3453                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3454                 buf_alloc->s_buf.self.low = aligned_mps;
3455         }
3456
3457         if (hns3_dev_dcb_supported(hw)) {
3458                 hi_thrd = shared_buf - pf->dv_buf_size;
3459
3460                 if (tc_num <= NEED_RESERVE_TC_NUM)
3461                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3462                                   BUF_MAX_PERCENT;
3463
3464                 if (tc_num)
3465                         hi_thrd = hi_thrd / tc_num;
3466
3467                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3468                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3469                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3470         } else {
3471                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3472                 lo_thrd = aligned_mps;
3473         }
3474
3475         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3476                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3477                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3478         }
3479
3480         return true;
3481 }
3482
3483 static bool
3484 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3485                      struct hns3_pkt_buf_alloc *buf_alloc)
3486 {
3487         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3488         struct hns3_pf *pf = &hns->pf;
3489         struct hns3_priv_buf *priv;
3490         uint32_t aligned_mps;
3491         uint32_t rx_all;
3492         uint8_t i;
3493
3494         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3495         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3496
3497         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3498                 priv = &buf_alloc->priv_buf[i];
3499
3500                 priv->enable = 0;
3501                 priv->wl.low = 0;
3502                 priv->wl.high = 0;
3503                 priv->buf_size = 0;
3504
3505                 if (!(hw->hw_tc_map & BIT(i)))
3506                         continue;
3507
3508                 priv->enable = 1;
3509                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3510                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3511                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3512                                                 HNS3_BUF_SIZE_UNIT);
3513                 } else {
3514                         priv->wl.low = 0;
3515                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3516                                         aligned_mps;
3517                 }
3518
3519                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3520         }
3521
3522         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3523 }
3524
3525 static bool
3526 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3527                              struct hns3_pkt_buf_alloc *buf_alloc)
3528 {
3529         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3530         struct hns3_pf *pf = &hns->pf;
3531         struct hns3_priv_buf *priv;
3532         int no_pfc_priv_num;
3533         uint32_t rx_all;
3534         uint8_t mask;
3535         int i;
3536
3537         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3538         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3539
3540         /* let the last to be cleared first */
3541         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3542                 priv = &buf_alloc->priv_buf[i];
3543                 mask = BIT((uint8_t)i);
3544
3545                 if (hw->hw_tc_map & mask &&
3546                     !(hw->dcb_info.hw_pfc_map & mask)) {
3547                         /* Clear the no pfc TC private buffer */
3548                         priv->wl.low = 0;
3549                         priv->wl.high = 0;
3550                         priv->buf_size = 0;
3551                         priv->enable = 0;
3552                         no_pfc_priv_num--;
3553                 }
3554
3555                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3556                     no_pfc_priv_num == 0)
3557                         break;
3558         }
3559
3560         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3561 }
3562
3563 static bool
3564 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3565                            struct hns3_pkt_buf_alloc *buf_alloc)
3566 {
3567         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3568         struct hns3_pf *pf = &hns->pf;
3569         struct hns3_priv_buf *priv;
3570         uint32_t rx_all;
3571         int pfc_priv_num;
3572         uint8_t mask;
3573         int i;
3574
3575         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3576         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3577
3578         /* let the last to be cleared first */
3579         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3580                 priv = &buf_alloc->priv_buf[i];
3581                 mask = BIT((uint8_t)i);
3582                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3583                         /* Reduce the number of pfc TC with private buffer */
3584                         priv->wl.low = 0;
3585                         priv->enable = 0;
3586                         priv->wl.high = 0;
3587                         priv->buf_size = 0;
3588                         pfc_priv_num--;
3589                 }
3590                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3591                     pfc_priv_num == 0)
3592                         break;
3593         }
3594
3595         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3596 }
3597
3598 static bool
3599 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3600                           struct hns3_pkt_buf_alloc *buf_alloc)
3601 {
3602 #define COMPENSATE_BUFFER       0x3C00
3603 #define COMPENSATE_HALF_MPS_NUM 5
3604 #define PRIV_WL_GAP             0x1800
3605         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3606         struct hns3_pf *pf = &hns->pf;
3607         uint32_t tc_num = hns3_get_tc_num(hw);
3608         uint32_t half_mps = pf->mps >> 1;
3609         struct hns3_priv_buf *priv;
3610         uint32_t min_rx_priv;
3611         uint32_t rx_priv;
3612         uint8_t i;
3613
3614         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3615         if (tc_num)
3616                 rx_priv = rx_priv / tc_num;
3617
3618         if (tc_num <= NEED_RESERVE_TC_NUM)
3619                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3620
3621         /*
3622          * Minimum value of private buffer in rx direction (min_rx_priv) is
3623          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3624          * buffer if rx_priv is greater than min_rx_priv.
3625          */
3626         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3627                         COMPENSATE_HALF_MPS_NUM * half_mps;
3628         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3629         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3630
3631         if (rx_priv < min_rx_priv)
3632                 return false;
3633
3634         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3635                 priv = &buf_alloc->priv_buf[i];
3636                 priv->enable = 0;
3637                 priv->wl.low = 0;
3638                 priv->wl.high = 0;
3639                 priv->buf_size = 0;
3640
3641                 if (!(hw->hw_tc_map & BIT(i)))
3642                         continue;
3643
3644                 priv->enable = 1;
3645                 priv->buf_size = rx_priv;
3646                 priv->wl.high = rx_priv - pf->dv_buf_size;
3647                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3648         }
3649
3650         buf_alloc->s_buf.buf_size = 0;
3651
3652         return true;
3653 }
3654
3655 /*
3656  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3657  * @hw: pointer to struct hns3_hw
3658  * @buf_alloc: pointer to buffer calculation data
3659  * @return: 0: calculate sucessful, negative: fail
3660  */
3661 static int
3662 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3663 {
3664         /* When DCB is not supported, rx private buffer is not allocated. */
3665         if (!hns3_dev_dcb_supported(hw)) {
3666                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3667                 struct hns3_pf *pf = &hns->pf;
3668                 uint32_t rx_all = pf->pkt_buf_size;
3669
3670                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3671                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3672                         return -ENOMEM;
3673
3674                 return 0;
3675         }
3676
3677         /*
3678          * Try to allocate privated packet buffer for all TCs without share
3679          * buffer.
3680          */
3681         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3682                 return 0;
3683
3684         /*
3685          * Try to allocate privated packet buffer for all TCs with share
3686          * buffer.
3687          */
3688         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3689                 return 0;
3690
3691         /*
3692          * For different application scenes, the enabled port number, TC number
3693          * and no_drop TC number are different. In order to obtain the better
3694          * performance, software could allocate the buffer size and configure
3695          * the waterline by tring to decrease the private buffer size according
3696          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3697          * enabled tc.
3698          */
3699         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3700                 return 0;
3701
3702         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3703                 return 0;
3704
3705         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3706                 return 0;
3707
3708         return -ENOMEM;
3709 }
3710
3711 static int
3712 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3713 {
3714         struct hns3_rx_priv_buff_cmd *req;
3715         struct hns3_cmd_desc desc;
3716         uint32_t buf_size;
3717         int ret;
3718         int i;
3719
3720         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3721         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3722
3723         /* Alloc private buffer TCs */
3724         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3725                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3726
3727                 req->buf_num[i] =
3728                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3729                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3730         }
3731
3732         buf_size = buf_alloc->s_buf.buf_size;
3733         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3734                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3735
3736         ret = hns3_cmd_send(hw, &desc, 1);
3737         if (ret)
3738                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3739
3740         return ret;
3741 }
3742
3743 static int
3744 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3745 {
3746 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3747         struct hns3_rx_priv_wl_buf *req;
3748         struct hns3_priv_buf *priv;
3749         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3750         int i, j;
3751         int ret;
3752
3753         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3754                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3755                                           false);
3756                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3757
3758                 /* The first descriptor set the NEXT bit to 1 */
3759                 if (i == 0)
3760                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3761                 else
3762                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3763
3764                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3765                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3766
3767                         priv = &buf_alloc->priv_buf[idx];
3768                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3769                                                         HNS3_BUF_UNIT_S);
3770                         req->tc_wl[j].high |=
3771                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3772                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3773                                                         HNS3_BUF_UNIT_S);
3774                         req->tc_wl[j].low |=
3775                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3776                 }
3777         }
3778
3779         /* Send 2 descriptor at one time */
3780         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3781         if (ret)
3782                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3783                              ret);
3784         return ret;
3785 }
3786
3787 static int
3788 hns3_common_thrd_config(struct hns3_hw *hw,
3789                         struct hns3_pkt_buf_alloc *buf_alloc)
3790 {
3791 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3792         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3793         struct hns3_rx_com_thrd *req;
3794         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3795         struct hns3_tc_thrd *tc;
3796         int tc_idx;
3797         int i, j;
3798         int ret;
3799
3800         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3801                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3802                                           false);
3803                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3804
3805                 /* The first descriptor set the NEXT bit to 1 */
3806                 if (i == 0)
3807                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3808                 else
3809                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3810
3811                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3812                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3813                         tc = &s_buf->tc_thrd[tc_idx];
3814
3815                         req->com_thrd[j].high =
3816                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3817                         req->com_thrd[j].high |=
3818                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3819                         req->com_thrd[j].low =
3820                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3821                         req->com_thrd[j].low |=
3822                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3823                 }
3824         }
3825
3826         /* Send 2 descriptors at one time */
3827         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3828         if (ret)
3829                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3830
3831         return ret;
3832 }
3833
3834 static int
3835 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3836 {
3837         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3838         struct hns3_rx_com_wl *req;
3839         struct hns3_cmd_desc desc;
3840         int ret;
3841
3842         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3843
3844         req = (struct hns3_rx_com_wl *)desc.data;
3845         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3846         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3847
3848         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3849         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3850
3851         ret = hns3_cmd_send(hw, &desc, 1);
3852         if (ret)
3853                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3854
3855         return ret;
3856 }
3857
3858 int
3859 hns3_buffer_alloc(struct hns3_hw *hw)
3860 {
3861         struct hns3_pkt_buf_alloc pkt_buf;
3862         int ret;
3863
3864         memset(&pkt_buf, 0, sizeof(pkt_buf));
3865         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3866         if (ret) {
3867                 PMD_INIT_LOG(ERR,
3868                              "could not calc tx buffer size for all TCs %d",
3869                              ret);
3870                 return ret;
3871         }
3872
3873         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3874         if (ret) {
3875                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3876                 return ret;
3877         }
3878
3879         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3880         if (ret) {
3881                 PMD_INIT_LOG(ERR,
3882                              "could not calc rx priv buffer size for all TCs %d",
3883                              ret);
3884                 return ret;
3885         }
3886
3887         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3888         if (ret) {
3889                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3890                 return ret;
3891         }
3892
3893         if (hns3_dev_dcb_supported(hw)) {
3894                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3895                 if (ret) {
3896                         PMD_INIT_LOG(ERR,
3897                                      "could not configure rx private waterline %d",
3898                                      ret);
3899                         return ret;
3900                 }
3901
3902                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3903                 if (ret) {
3904                         PMD_INIT_LOG(ERR,
3905                                      "could not configure common threshold %d",
3906                                      ret);
3907                         return ret;
3908                 }
3909         }
3910
3911         ret = hns3_common_wl_config(hw, &pkt_buf);
3912         if (ret)
3913                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3914                              ret);
3915
3916         return ret;
3917 }
3918
3919 static int
3920 hns3_mac_init(struct hns3_hw *hw)
3921 {
3922         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3923         struct hns3_mac *mac = &hw->mac;
3924         struct hns3_pf *pf = &hns->pf;
3925         int ret;
3926
3927         pf->support_sfp_query = true;
3928         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3929         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3930         if (ret) {
3931                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3932                 return ret;
3933         }
3934
3935         mac->link_status = ETH_LINK_DOWN;
3936
3937         return hns3_config_mtu(hw, pf->mps);
3938 }
3939
3940 static int
3941 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3942 {
3943 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3944 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3945 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3946 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3947         int return_status;
3948
3949         if (cmdq_resp) {
3950                 PMD_INIT_LOG(ERR,
3951                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3952                              cmdq_resp);
3953                 return -EIO;
3954         }
3955
3956         switch (resp_code) {
3957         case HNS3_ETHERTYPE_SUCCESS_ADD:
3958         case HNS3_ETHERTYPE_ALREADY_ADD:
3959                 return_status = 0;
3960                 break;
3961         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3962                 PMD_INIT_LOG(ERR,
3963                              "add mac ethertype failed for manager table overflow.");
3964                 return_status = -EIO;
3965                 break;
3966         case HNS3_ETHERTYPE_KEY_CONFLICT:
3967                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3968                 return_status = -EIO;
3969                 break;
3970         default:
3971                 PMD_INIT_LOG(ERR,
3972                              "add mac ethertype failed for undefined, code=%u.",
3973                              resp_code);
3974                 return_status = -EIO;
3975                 break;
3976         }
3977
3978         return return_status;
3979 }
3980
3981 static int
3982 hns3_add_mgr_tbl(struct hns3_hw *hw,
3983                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3984 {
3985         struct hns3_cmd_desc desc;
3986         uint8_t resp_code;
3987         uint16_t retval;
3988         int ret;
3989
3990         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3991         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3992
3993         ret = hns3_cmd_send(hw, &desc, 1);
3994         if (ret) {
3995                 PMD_INIT_LOG(ERR,
3996                              "add mac ethertype failed for cmd_send, ret =%d.",
3997                              ret);
3998                 return ret;
3999         }
4000
4001         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4002         retval = rte_le_to_cpu_16(desc.retval);
4003
4004         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4005 }
4006
4007 static void
4008 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4009                      int *table_item_num)
4010 {
4011         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4012
4013         /*
4014          * In current version, we add one item in management table as below:
4015          * 0x0180C200000E -- LLDP MC address
4016          */
4017         tbl = mgr_table;
4018         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4019         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4020         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4021         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4022         tbl->i_port_bitmap = 0x1;
4023         *table_item_num = 1;
4024 }
4025
4026 static int
4027 hns3_init_mgr_tbl(struct hns3_hw *hw)
4028 {
4029 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4030         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4031         int table_item_num;
4032         int ret;
4033         int i;
4034
4035         memset(mgr_table, 0, sizeof(mgr_table));
4036         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4037         for (i = 0; i < table_item_num; i++) {
4038                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4039                 if (ret) {
4040                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4041                                      ret);
4042                         return ret;
4043                 }
4044         }
4045
4046         return 0;
4047 }
4048
4049 static void
4050 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4051                         bool en_mc, bool en_bc, int vport_id)
4052 {
4053         if (!param)
4054                 return;
4055
4056         memset(param, 0, sizeof(struct hns3_promisc_param));
4057         if (en_uc)
4058                 param->enable = HNS3_PROMISC_EN_UC;
4059         if (en_mc)
4060                 param->enable |= HNS3_PROMISC_EN_MC;
4061         if (en_bc)
4062                 param->enable |= HNS3_PROMISC_EN_BC;
4063         param->vf_id = vport_id;
4064 }
4065
4066 static int
4067 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4068 {
4069         struct hns3_promisc_cfg_cmd *req;
4070         struct hns3_cmd_desc desc;
4071         int ret;
4072
4073         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4074
4075         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4076         req->vf_id = param->vf_id;
4077         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4078             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4079
4080         ret = hns3_cmd_send(hw, &desc, 1);
4081         if (ret)
4082                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4083
4084         return ret;
4085 }
4086
4087 static int
4088 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4089 {
4090         struct hns3_promisc_param param;
4091         bool en_bc_pmc = true;
4092         uint8_t vf_id;
4093
4094         /*
4095          * In current version VF is not supported when PF is driven by DPDK
4096          * driver, just need to configure parameters for PF vport.
4097          */
4098         vf_id = HNS3_PF_FUNC_ID;
4099
4100         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4101         return hns3_cmd_set_promisc_mode(hw, &param);
4102 }
4103
4104 static int
4105 hns3_promisc_init(struct hns3_hw *hw)
4106 {
4107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4108         struct hns3_pf *pf = &hns->pf;
4109         struct hns3_promisc_param param;
4110         uint16_t func_id;
4111         int ret;
4112
4113         ret = hns3_set_promisc_mode(hw, false, false);
4114         if (ret) {
4115                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4116                 return ret;
4117         }
4118
4119         /*
4120          * In current version VFs are not supported when PF is driven by DPDK
4121          * driver. After PF has been taken over by DPDK, the original VF will
4122          * be invalid. So, there is a possibility of entry residues. It should
4123          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4124          * during init.
4125          */
4126         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4127                 hns3_promisc_param_init(&param, false, false, false, func_id);
4128                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4129                 if (ret) {
4130                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4131                                         " ret = %d", func_id, ret);
4132                         return ret;
4133                 }
4134         }
4135
4136         return 0;
4137 }
4138
4139 static void
4140 hns3_promisc_uninit(struct hns3_hw *hw)
4141 {
4142         struct hns3_promisc_param param;
4143         uint16_t func_id;
4144         int ret;
4145
4146         func_id = HNS3_PF_FUNC_ID;
4147
4148         /*
4149          * In current version VFs are not supported when PF is driven by
4150          * DPDK driver, and VFs' promisc mode status has been cleared during
4151          * init and their status will not change. So just clear PF's promisc
4152          * mode status during uninit.
4153          */
4154         hns3_promisc_param_init(&param, false, false, false, func_id);
4155         ret = hns3_cmd_set_promisc_mode(hw, &param);
4156         if (ret)
4157                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4158                                 " uninit, ret = %d", ret);
4159 }
4160
4161 static int
4162 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4163 {
4164         bool allmulti = dev->data->all_multicast ? true : false;
4165         struct hns3_adapter *hns = dev->data->dev_private;
4166         struct hns3_hw *hw = &hns->hw;
4167         uint64_t offloads;
4168         int err;
4169         int ret;
4170
4171         rte_spinlock_lock(&hw->lock);
4172         ret = hns3_set_promisc_mode(hw, true, true);
4173         if (ret) {
4174                 rte_spinlock_unlock(&hw->lock);
4175                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4176                          ret);
4177                 return ret;
4178         }
4179
4180         /*
4181          * When promiscuous mode was enabled, disable the vlan filter to let
4182          * all packets coming in in the receiving direction.
4183          */
4184         offloads = dev->data->dev_conf.rxmode.offloads;
4185         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4186                 ret = hns3_enable_vlan_filter(hns, false);
4187                 if (ret) {
4188                         hns3_err(hw, "failed to enable promiscuous mode due to "
4189                                      "failure to disable vlan filter, ret = %d",
4190                                  ret);
4191                         err = hns3_set_promisc_mode(hw, false, allmulti);
4192                         if (err)
4193                                 hns3_err(hw, "failed to restore promiscuous "
4194                                          "status after disable vlan filter "
4195                                          "failed during enabling promiscuous "
4196                                          "mode, ret = %d", ret);
4197                 }
4198         }
4199
4200         rte_spinlock_unlock(&hw->lock);
4201
4202         return ret;
4203 }
4204
4205 static int
4206 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4207 {
4208         bool allmulti = dev->data->all_multicast ? true : false;
4209         struct hns3_adapter *hns = dev->data->dev_private;
4210         struct hns3_hw *hw = &hns->hw;
4211         uint64_t offloads;
4212         int err;
4213         int ret;
4214
4215         /* If now in all_multicast mode, must remain in all_multicast mode. */
4216         rte_spinlock_lock(&hw->lock);
4217         ret = hns3_set_promisc_mode(hw, false, allmulti);
4218         if (ret) {
4219                 rte_spinlock_unlock(&hw->lock);
4220                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4221                          ret);
4222                 return ret;
4223         }
4224         /* when promiscuous mode was disabled, restore the vlan filter status */
4225         offloads = dev->data->dev_conf.rxmode.offloads;
4226         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4227                 ret = hns3_enable_vlan_filter(hns, true);
4228                 if (ret) {
4229                         hns3_err(hw, "failed to disable promiscuous mode due to"
4230                                  " failure to restore vlan filter, ret = %d",
4231                                  ret);
4232                         err = hns3_set_promisc_mode(hw, true, true);
4233                         if (err)
4234                                 hns3_err(hw, "failed to restore promiscuous "
4235                                          "status after enabling vlan filter "
4236                                          "failed during disabling promiscuous "
4237                                          "mode, ret = %d", ret);
4238                 }
4239         }
4240         rte_spinlock_unlock(&hw->lock);
4241
4242         return ret;
4243 }
4244
4245 static int
4246 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4247 {
4248         struct hns3_adapter *hns = dev->data->dev_private;
4249         struct hns3_hw *hw = &hns->hw;
4250         int ret;
4251
4252         if (dev->data->promiscuous)
4253                 return 0;
4254
4255         rte_spinlock_lock(&hw->lock);
4256         ret = hns3_set_promisc_mode(hw, false, true);
4257         rte_spinlock_unlock(&hw->lock);
4258         if (ret)
4259                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4260                          ret);
4261
4262         return ret;
4263 }
4264
4265 static int
4266 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4267 {
4268         struct hns3_adapter *hns = dev->data->dev_private;
4269         struct hns3_hw *hw = &hns->hw;
4270         int ret;
4271
4272         /* If now in promiscuous mode, must remain in all_multicast mode. */
4273         if (dev->data->promiscuous)
4274                 return 0;
4275
4276         rte_spinlock_lock(&hw->lock);
4277         ret = hns3_set_promisc_mode(hw, false, false);
4278         rte_spinlock_unlock(&hw->lock);
4279         if (ret)
4280                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4281                          ret);
4282
4283         return ret;
4284 }
4285
4286 static int
4287 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4288 {
4289         struct hns3_hw *hw = &hns->hw;
4290         bool allmulti = hw->data->all_multicast ? true : false;
4291         int ret;
4292
4293         if (hw->data->promiscuous) {
4294                 ret = hns3_set_promisc_mode(hw, true, true);
4295                 if (ret)
4296                         hns3_err(hw, "failed to restore promiscuous mode, "
4297                                  "ret = %d", ret);
4298                 return ret;
4299         }
4300
4301         ret = hns3_set_promisc_mode(hw, false, allmulti);
4302         if (ret)
4303                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4304                          ret);
4305         return ret;
4306 }
4307
4308 static int
4309 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4310 {
4311         struct hns3_sfp_speed_cmd *resp;
4312         struct hns3_cmd_desc desc;
4313         int ret;
4314
4315         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4316         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4317         ret = hns3_cmd_send(hw, &desc, 1);
4318         if (ret == -EOPNOTSUPP) {
4319                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4320                 return ret;
4321         } else if (ret) {
4322                 hns3_err(hw, "get sfp speed failed %d", ret);
4323                 return ret;
4324         }
4325
4326         *speed = resp->sfp_speed;
4327
4328         return 0;
4329 }
4330
4331 static uint8_t
4332 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4333 {
4334         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4335                 duplex = ETH_LINK_FULL_DUPLEX;
4336
4337         return duplex;
4338 }
4339
4340 static int
4341 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4342 {
4343         struct hns3_mac *mac = &hw->mac;
4344         uint32_t cur_speed = mac->link_speed;
4345         int ret;
4346
4347         duplex = hns3_check_speed_dup(duplex, speed);
4348         if (mac->link_speed == speed && mac->link_duplex == duplex)
4349                 return 0;
4350
4351         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4352         if (ret)
4353                 return ret;
4354
4355         mac->link_speed = speed;
4356         ret = hns3_dcb_port_shaper_cfg(hw);
4357         if (ret) {
4358                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4359                 mac->link_speed = cur_speed;
4360                 return ret;
4361         }
4362
4363         mac->link_duplex = duplex;
4364
4365         return 0;
4366 }
4367
4368 static int
4369 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4370 {
4371         struct hns3_adapter *hns = eth_dev->data->dev_private;
4372         struct hns3_hw *hw = &hns->hw;
4373         struct hns3_pf *pf = &hns->pf;
4374         uint32_t speed;
4375         int ret;
4376
4377         /* If IMP do not support get SFP/qSFP speed, return directly */
4378         if (!pf->support_sfp_query)
4379                 return 0;
4380
4381         ret = hns3_get_sfp_speed(hw, &speed);
4382         if (ret == -EOPNOTSUPP) {
4383                 pf->support_sfp_query = false;
4384                 return ret;
4385         } else if (ret)
4386                 return ret;
4387
4388         if (speed == ETH_SPEED_NUM_NONE)
4389                 return 0; /* do nothing if no SFP */
4390
4391         /* Config full duplex for SFP */
4392         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4393 }
4394
4395 static int
4396 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4397 {
4398         struct hns3_config_mac_mode_cmd *req;
4399         struct hns3_cmd_desc desc;
4400         uint32_t loop_en = 0;
4401         uint8_t val = 0;
4402         int ret;
4403
4404         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4405
4406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4407         if (enable)
4408                 val = 1;
4409         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4410         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4411         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4412         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4413         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4414         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4415         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4416         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4417         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4418         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4419
4420         /*
4421          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4422          * when receiving frames. Otherwise, CRC will be stripped.
4423          */
4424         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4425                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4426         else
4427                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4428         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4429         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4430         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4431         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4432
4433         ret = hns3_cmd_send(hw, &desc, 1);
4434         if (ret)
4435                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4436
4437         return ret;
4438 }
4439
4440 static int
4441 hns3_get_mac_link_status(struct hns3_hw *hw)
4442 {
4443         struct hns3_link_status_cmd *req;
4444         struct hns3_cmd_desc desc;
4445         int link_status;
4446         int ret;
4447
4448         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4449         ret = hns3_cmd_send(hw, &desc, 1);
4450         if (ret) {
4451                 hns3_err(hw, "get link status cmd failed %d", ret);
4452                 return ETH_LINK_DOWN;
4453         }
4454
4455         req = (struct hns3_link_status_cmd *)desc.data;
4456         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4457
4458         return !!link_status;
4459 }
4460
4461 void
4462 hns3_update_link_status(struct hns3_hw *hw)
4463 {
4464         int state;
4465
4466         state = hns3_get_mac_link_status(hw);
4467         if (state != hw->mac.link_status) {
4468                 hw->mac.link_status = state;
4469                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4470         }
4471 }
4472
4473 static void
4474 hns3_service_handler(void *param)
4475 {
4476         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4477         struct hns3_adapter *hns = eth_dev->data->dev_private;
4478         struct hns3_hw *hw = &hns->hw;
4479
4480         if (!hns3_is_reset_pending(hns)) {
4481                 hns3_update_speed_duplex(eth_dev);
4482                 hns3_update_link_status(hw);
4483         } else
4484                 hns3_warn(hw, "Cancel the query when reset is pending");
4485
4486         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4487 }
4488
4489 static int
4490 hns3_init_hardware(struct hns3_adapter *hns)
4491 {
4492         struct hns3_hw *hw = &hns->hw;
4493         int ret;
4494
4495         ret = hns3_map_tqp(hw);
4496         if (ret) {
4497                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4498                 return ret;
4499         }
4500
4501         ret = hns3_init_umv_space(hw);
4502         if (ret) {
4503                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4504                 return ret;
4505         }
4506
4507         ret = hns3_mac_init(hw);
4508         if (ret) {
4509                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4510                 goto err_mac_init;
4511         }
4512
4513         ret = hns3_init_mgr_tbl(hw);
4514         if (ret) {
4515                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4516                 goto err_mac_init;
4517         }
4518
4519         ret = hns3_promisc_init(hw);
4520         if (ret) {
4521                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4522                              ret);
4523                 goto err_mac_init;
4524         }
4525
4526         ret = hns3_init_vlan_config(hns);
4527         if (ret) {
4528                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4529                 goto err_mac_init;
4530         }
4531
4532         ret = hns3_dcb_init(hw);
4533         if (ret) {
4534                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4535                 goto err_mac_init;
4536         }
4537
4538         ret = hns3_init_fd_config(hns);
4539         if (ret) {
4540                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4541                 goto err_mac_init;
4542         }
4543
4544         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4545         if (ret) {
4546                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4547                 goto err_mac_init;
4548         }
4549
4550         ret = hns3_config_gro(hw, false);
4551         if (ret) {
4552                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4553                 goto err_mac_init;
4554         }
4555
4556         /*
4557          * In the initialization clearing the all hardware mapping relationship
4558          * configurations between queues and interrupt vectors is needed, so
4559          * some error caused by the residual configurations, such as the
4560          * unexpected interrupt, can be avoid.
4561          */
4562         ret = hns3_init_ring_with_vector(hw);
4563         if (ret) {
4564                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4565                 goto err_mac_init;
4566         }
4567
4568         return 0;
4569
4570 err_mac_init:
4571         hns3_uninit_umv_space(hw);
4572         return ret;
4573 }
4574
4575 static int
4576 hns3_clear_hw(struct hns3_hw *hw)
4577 {
4578         struct hns3_cmd_desc desc;
4579         int ret;
4580
4581         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4582
4583         ret = hns3_cmd_send(hw, &desc, 1);
4584         if (ret && ret != -EOPNOTSUPP)
4585                 return ret;
4586
4587         return 0;
4588 }
4589
4590 static void
4591 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4592 {
4593         uint32_t val;
4594
4595         /*
4596          * The new firmware support report more hardware error types by
4597          * msix mode. These errors are defined as RAS errors in hardware
4598          * and belong to a different type from the MSI-x errors processed
4599          * by the network driver.
4600          *
4601          * Network driver should open the new error report on initialition
4602          */
4603         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4604         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4605         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4606 }
4607
4608 static int
4609 hns3_init_pf(struct rte_eth_dev *eth_dev)
4610 {
4611         struct rte_device *dev = eth_dev->device;
4612         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4613         struct hns3_adapter *hns = eth_dev->data->dev_private;
4614         struct hns3_hw *hw = &hns->hw;
4615         int ret;
4616
4617         PMD_INIT_FUNC_TRACE();
4618
4619         /* Get hardware io base address from pcie BAR2 IO space */
4620         hw->io_base = pci_dev->mem_resource[2].addr;
4621
4622         /* Firmware command queue initialize */
4623         ret = hns3_cmd_init_queue(hw);
4624         if (ret) {
4625                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4626                 goto err_cmd_init_queue;
4627         }
4628
4629         hns3_clear_all_event_cause(hw);
4630
4631         /* Firmware command initialize */
4632         ret = hns3_cmd_init(hw);
4633         if (ret) {
4634                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4635                 goto err_cmd_init;
4636         }
4637
4638         /*
4639          * To ensure that the hardware environment is clean during
4640          * initialization, the driver actively clear the hardware environment
4641          * during initialization, including PF and corresponding VFs' vlan, mac,
4642          * flow table configurations, etc.
4643          */
4644         ret = hns3_clear_hw(hw);
4645         if (ret) {
4646                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4647                 goto err_cmd_init;
4648         }
4649
4650         hns3_config_all_msix_error(hw, true);
4651
4652         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4653                                          hns3_interrupt_handler,
4654                                          eth_dev);
4655         if (ret) {
4656                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4657                 goto err_intr_callback_register;
4658         }
4659
4660         /* Enable interrupt */
4661         rte_intr_enable(&pci_dev->intr_handle);
4662         hns3_pf_enable_irq0(hw);
4663
4664         /* Get configuration */
4665         ret = hns3_get_configuration(hw);
4666         if (ret) {
4667                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4668                 goto err_get_config;
4669         }
4670
4671         ret = hns3_tqp_stats_init(hw);
4672         if (ret)
4673                 goto err_get_config;
4674
4675         ret = hns3_init_hardware(hns);
4676         if (ret) {
4677                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4678                 goto err_init_hw;
4679         }
4680
4681         /* Initialize flow director filter list & hash */
4682         ret = hns3_fdir_filter_init(hns);
4683         if (ret) {
4684                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4685                 goto err_fdir;
4686         }
4687
4688         hns3_set_default_rss_args(hw);
4689
4690         ret = hns3_enable_hw_error_intr(hns, true);
4691         if (ret) {
4692                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4693                              ret);
4694                 goto err_enable_intr;
4695         }
4696
4697         hns3_tm_conf_init(eth_dev);
4698
4699         return 0;
4700
4701 err_enable_intr:
4702         hns3_fdir_filter_uninit(hns);
4703 err_fdir:
4704         hns3_uninit_umv_space(hw);
4705 err_init_hw:
4706         hns3_tqp_stats_uninit(hw);
4707 err_get_config:
4708         hns3_pf_disable_irq0(hw);
4709         rte_intr_disable(&pci_dev->intr_handle);
4710         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4711                              eth_dev);
4712 err_intr_callback_register:
4713 err_cmd_init:
4714         hns3_cmd_uninit(hw);
4715         hns3_cmd_destroy_queue(hw);
4716 err_cmd_init_queue:
4717         hw->io_base = NULL;
4718
4719         return ret;
4720 }
4721
4722 static void
4723 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4724 {
4725         struct hns3_adapter *hns = eth_dev->data->dev_private;
4726         struct rte_device *dev = eth_dev->device;
4727         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4728         struct hns3_hw *hw = &hns->hw;
4729
4730         PMD_INIT_FUNC_TRACE();
4731
4732         hns3_tm_conf_uninit(eth_dev);
4733         hns3_enable_hw_error_intr(hns, false);
4734         hns3_rss_uninit(hns);
4735         (void)hns3_config_gro(hw, false);
4736         hns3_promisc_uninit(hw);
4737         hns3_fdir_filter_uninit(hns);
4738         hns3_uninit_umv_space(hw);
4739         hns3_tqp_stats_uninit(hw);
4740         hns3_pf_disable_irq0(hw);
4741         rte_intr_disable(&pci_dev->intr_handle);
4742         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4743                              eth_dev);
4744         hns3_config_all_msix_error(hw, false);
4745         hns3_cmd_uninit(hw);
4746         hns3_cmd_destroy_queue(hw);
4747         hw->io_base = NULL;
4748 }
4749
4750 static int
4751 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4752 {
4753         struct hns3_hw *hw = &hns->hw;
4754         int ret;
4755
4756         ret = hns3_dcb_cfg_update(hns);
4757         if (ret)
4758                 return ret;
4759
4760         /*
4761          * The hns3_dcb_cfg_update may configure TM module, so
4762          * hns3_tm_conf_update must called later.
4763          */
4764         ret = hns3_tm_conf_update(hw);
4765         if (ret) {
4766                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4767                 return ret;
4768         }
4769
4770         ret = hns3_init_queues(hns, reset_queue);
4771         if (ret) {
4772                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4773                 return ret;
4774         }
4775
4776         ret = hns3_cfg_mac_mode(hw, true);
4777         if (ret) {
4778                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4779                 goto err_config_mac_mode;
4780         }
4781         return 0;
4782
4783 err_config_mac_mode:
4784         hns3_dev_release_mbufs(hns);
4785         /*
4786          * Here is exception handling, hns3_reset_all_tqps will have the
4787          * corresponding error message if it is handled incorrectly, so it is
4788          * not necessary to check hns3_reset_all_tqps return value, here keep
4789          * ret as the error code causing the exception.
4790          */
4791         (void)hns3_reset_all_tqps(hns);
4792         return ret;
4793 }
4794
4795 static int
4796 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4797 {
4798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4799         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4800         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
4802         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4803         uint32_t intr_vector;
4804         uint16_t q_id;
4805         int ret;
4806
4807         /*
4808          * hns3 needs a separate interrupt to be used as event interrupt which
4809          * could not be shared with task queue pair, so KERNEL drivers need
4810          * support multiple interrupt vectors.
4811          */
4812         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4813             !rte_intr_cap_multiple(intr_handle))
4814                 return 0;
4815
4816         rte_intr_disable(intr_handle);
4817         intr_vector = hw->used_rx_queues;
4818         /* creates event fd for each intr vector when MSIX is used */
4819         if (rte_intr_efd_enable(intr_handle, intr_vector))
4820                 return -EINVAL;
4821
4822         if (intr_handle->intr_vec == NULL) {
4823                 intr_handle->intr_vec =
4824                         rte_zmalloc("intr_vec",
4825                                     hw->used_rx_queues * sizeof(int), 0);
4826                 if (intr_handle->intr_vec == NULL) {
4827                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4828                                         hw->used_rx_queues);
4829                         ret = -ENOMEM;
4830                         goto alloc_intr_vec_error;
4831                 }
4832         }
4833
4834         if (rte_intr_allow_others(intr_handle)) {
4835                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4836                 base = RTE_INTR_VEC_RXTX_OFFSET;
4837         }
4838
4839         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4840                 ret = hns3_bind_ring_with_vector(hw, vec, true,
4841                                                  HNS3_RING_TYPE_RX, q_id);
4842                 if (ret)
4843                         goto bind_vector_error;
4844                 intr_handle->intr_vec[q_id] = vec;
4845                 /*
4846                  * If there are not enough efds (e.g. not enough interrupt),
4847                  * remaining queues will be bond to the last interrupt.
4848                  */
4849                 if (vec < base + intr_handle->nb_efd - 1)
4850                         vec++;
4851         }
4852         rte_intr_enable(intr_handle);
4853         return 0;
4854
4855 bind_vector_error:
4856         rte_free(intr_handle->intr_vec);
4857         intr_handle->intr_vec = NULL;
4858 alloc_intr_vec_error:
4859         rte_intr_efd_disable(intr_handle);
4860         return ret;
4861 }
4862
4863 static int
4864 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4865 {
4866         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4869         uint16_t q_id;
4870         int ret;
4871
4872         if (dev->data->dev_conf.intr_conf.rxq == 0)
4873                 return 0;
4874
4875         if (rte_intr_dp_is_en(intr_handle)) {
4876                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4877                         ret = hns3_bind_ring_with_vector(hw,
4878                                         intr_handle->intr_vec[q_id], true,
4879                                         HNS3_RING_TYPE_RX, q_id);
4880                         if (ret)
4881                                 return ret;
4882                 }
4883         }
4884
4885         return 0;
4886 }
4887
4888 static void
4889 hns3_restore_filter(struct rte_eth_dev *dev)
4890 {
4891         hns3_restore_rss_filter(dev);
4892 }
4893
4894 static int
4895 hns3_dev_start(struct rte_eth_dev *dev)
4896 {
4897         struct hns3_adapter *hns = dev->data->dev_private;
4898         struct hns3_hw *hw = &hns->hw;
4899         int ret;
4900
4901         PMD_INIT_FUNC_TRACE();
4902         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4903                 return -EBUSY;
4904
4905         rte_spinlock_lock(&hw->lock);
4906         hw->adapter_state = HNS3_NIC_STARTING;
4907
4908         ret = hns3_do_start(hns, true);
4909         if (ret) {
4910                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4911                 rte_spinlock_unlock(&hw->lock);
4912                 return ret;
4913         }
4914         ret = hns3_map_rx_interrupt(dev);
4915         if (ret) {
4916                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4917                 rte_spinlock_unlock(&hw->lock);
4918                 return ret;
4919         }
4920
4921         /*
4922          * There are three register used to control the status of a TQP
4923          * (contains a pair of Tx queue and Rx queue) in the new version network
4924          * engine. One is used to control the enabling of Tx queue, the other is
4925          * used to control the enabling of Rx queue, and the last is the master
4926          * switch used to control the enabling of the tqp. The Tx register and
4927          * TQP register must be enabled at the same time to enable a Tx queue.
4928          * The same applies to the Rx queue. For the older network engine, this
4929          * function only refresh the enabled flag, and it is used to update the
4930          * status of queue in the dpdk framework.
4931          */
4932         ret = hns3_start_all_txqs(dev);
4933         if (ret) {
4934                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4935                 rte_spinlock_unlock(&hw->lock);
4936                 return ret;
4937         }
4938
4939         ret = hns3_start_all_rxqs(dev);
4940         if (ret) {
4941                 hns3_stop_all_txqs(dev);
4942                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4943                 rte_spinlock_unlock(&hw->lock);
4944                 return ret;
4945         }
4946
4947         hw->adapter_state = HNS3_NIC_STARTED;
4948         rte_spinlock_unlock(&hw->lock);
4949
4950         hns3_rx_scattered_calc(dev);
4951         hns3_set_rxtx_function(dev);
4952         hns3_mp_req_start_rxtx(dev);
4953         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4954
4955         hns3_restore_filter(dev);
4956
4957         /* Enable interrupt of all rx queues before enabling queues */
4958         hns3_dev_all_rx_queue_intr_enable(hw, true);
4959
4960         /*
4961          * After finished the initialization, enable tqps to receive/transmit
4962          * packets and refresh all queue status.
4963          */
4964         hns3_start_tqps(hw);
4965
4966         hns3_tm_dev_start_proc(hw);
4967
4968         hns3_info(hw, "hns3 dev start successful!");
4969         return 0;
4970 }
4971
4972 static int
4973 hns3_do_stop(struct hns3_adapter *hns)
4974 {
4975         struct hns3_hw *hw = &hns->hw;
4976         int ret;
4977
4978         ret = hns3_cfg_mac_mode(hw, false);
4979         if (ret)
4980                 return ret;
4981         hw->mac.link_status = ETH_LINK_DOWN;
4982
4983         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4984                 hns3_configure_all_mac_addr(hns, true);
4985                 ret = hns3_reset_all_tqps(hns);
4986                 if (ret) {
4987                         hns3_err(hw, "failed to reset all queues ret = %d.",
4988                                  ret);
4989                         return ret;
4990                 }
4991         }
4992         hw->mac.default_addr_setted = false;
4993         return 0;
4994 }
4995
4996 static void
4997 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4998 {
4999         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5000         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5001         struct hns3_adapter *hns = dev->data->dev_private;
5002         struct hns3_hw *hw = &hns->hw;
5003         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5004         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5005         uint16_t q_id;
5006
5007         if (dev->data->dev_conf.intr_conf.rxq == 0)
5008                 return;
5009
5010         /* unmap the ring with vector */
5011         if (rte_intr_allow_others(intr_handle)) {
5012                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5013                 base = RTE_INTR_VEC_RXTX_OFFSET;
5014         }
5015         if (rte_intr_dp_is_en(intr_handle)) {
5016                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5017                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5018                                                          HNS3_RING_TYPE_RX,
5019                                                          q_id);
5020                         if (vec < base + intr_handle->nb_efd - 1)
5021                                 vec++;
5022                 }
5023         }
5024         /* Clean datapath event and queue/vec mapping */
5025         rte_intr_efd_disable(intr_handle);
5026         if (intr_handle->intr_vec) {
5027                 rte_free(intr_handle->intr_vec);
5028                 intr_handle->intr_vec = NULL;
5029         }
5030 }
5031
5032 static int
5033 hns3_dev_stop(struct rte_eth_dev *dev)
5034 {
5035         struct hns3_adapter *hns = dev->data->dev_private;
5036         struct hns3_hw *hw = &hns->hw;
5037
5038         PMD_INIT_FUNC_TRACE();
5039         dev->data->dev_started = 0;
5040
5041         hw->adapter_state = HNS3_NIC_STOPPING;
5042         hns3_set_rxtx_function(dev);
5043         rte_wmb();
5044         /* Disable datapath on secondary process. */
5045         hns3_mp_req_stop_rxtx(dev);
5046         /* Prevent crashes when queues are still in use. */
5047         rte_delay_ms(hw->tqps_num);
5048
5049         rte_spinlock_lock(&hw->lock);
5050         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5051                 hns3_tm_dev_stop_proc(hw);
5052                 hns3_stop_tqps(hw);
5053                 hns3_do_stop(hns);
5054                 hns3_unmap_rx_interrupt(dev);
5055                 hns3_dev_release_mbufs(hns);
5056                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5057         }
5058         hns3_rx_scattered_reset(dev);
5059         rte_eal_alarm_cancel(hns3_service_handler, dev);
5060         rte_spinlock_unlock(&hw->lock);
5061
5062         return 0;
5063 }
5064
5065 static int
5066 hns3_dev_close(struct rte_eth_dev *eth_dev)
5067 {
5068         struct hns3_adapter *hns = eth_dev->data->dev_private;
5069         struct hns3_hw *hw = &hns->hw;
5070         int ret = 0;
5071
5072         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5073                 rte_free(eth_dev->process_private);
5074                 eth_dev->process_private = NULL;
5075                 return 0;
5076         }
5077
5078         if (hw->adapter_state == HNS3_NIC_STARTED)
5079                 ret = hns3_dev_stop(eth_dev);
5080
5081         hw->adapter_state = HNS3_NIC_CLOSING;
5082         hns3_reset_abort(hns);
5083         hw->adapter_state = HNS3_NIC_CLOSED;
5084
5085         hns3_configure_all_mc_mac_addr(hns, true);
5086         hns3_remove_all_vlan_table(hns);
5087         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5088         hns3_uninit_pf(eth_dev);
5089         hns3_free_all_queues(eth_dev);
5090         rte_free(hw->reset.wait_data);
5091         rte_free(eth_dev->process_private);
5092         eth_dev->process_private = NULL;
5093         hns3_mp_uninit_primary();
5094         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5095
5096         return ret;
5097 }
5098
5099 static int
5100 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5101 {
5102         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5104
5105         fc_conf->pause_time = pf->pause_time;
5106
5107         /* return fc current mode */
5108         switch (hw->current_mode) {
5109         case HNS3_FC_FULL:
5110                 fc_conf->mode = RTE_FC_FULL;
5111                 break;
5112         case HNS3_FC_TX_PAUSE:
5113                 fc_conf->mode = RTE_FC_TX_PAUSE;
5114                 break;
5115         case HNS3_FC_RX_PAUSE:
5116                 fc_conf->mode = RTE_FC_RX_PAUSE;
5117                 break;
5118         case HNS3_FC_NONE:
5119         default:
5120                 fc_conf->mode = RTE_FC_NONE;
5121                 break;
5122         }
5123
5124         return 0;
5125 }
5126
5127 static void
5128 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5129 {
5130         switch (mode) {
5131         case RTE_FC_NONE:
5132                 hw->requested_mode = HNS3_FC_NONE;
5133                 break;
5134         case RTE_FC_RX_PAUSE:
5135                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5136                 break;
5137         case RTE_FC_TX_PAUSE:
5138                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5139                 break;
5140         case RTE_FC_FULL:
5141                 hw->requested_mode = HNS3_FC_FULL;
5142                 break;
5143         default:
5144                 hw->requested_mode = HNS3_FC_NONE;
5145                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5146                           "configured to RTE_FC_NONE", mode);
5147                 break;
5148         }
5149 }
5150
5151 static int
5152 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5153 {
5154         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5156         int ret;
5157
5158         if (fc_conf->high_water || fc_conf->low_water ||
5159             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5160                 hns3_err(hw, "Unsupported flow control settings specified, "
5161                          "high_water(%u), low_water(%u), send_xon(%u) and "
5162                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5163                          fc_conf->high_water, fc_conf->low_water,
5164                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5165                 return -EINVAL;
5166         }
5167         if (fc_conf->autoneg) {
5168                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5169                 return -EINVAL;
5170         }
5171         if (!fc_conf->pause_time) {
5172                 hns3_err(hw, "Invalid pause time %u setting.",
5173                          fc_conf->pause_time);
5174                 return -EINVAL;
5175         }
5176
5177         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5178             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5179                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5180                          "current_fc_status = %d", hw->current_fc_status);
5181                 return -EOPNOTSUPP;
5182         }
5183
5184         hns3_get_fc_mode(hw, fc_conf->mode);
5185         if (hw->requested_mode == hw->current_mode &&
5186             pf->pause_time == fc_conf->pause_time)
5187                 return 0;
5188
5189         rte_spinlock_lock(&hw->lock);
5190         ret = hns3_fc_enable(dev, fc_conf);
5191         rte_spinlock_unlock(&hw->lock);
5192
5193         return ret;
5194 }
5195
5196 static int
5197 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5198                             struct rte_eth_pfc_conf *pfc_conf)
5199 {
5200         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5202         uint8_t priority;
5203         int ret;
5204
5205         if (!hns3_dev_dcb_supported(hw)) {
5206                 hns3_err(hw, "This port does not support dcb configurations.");
5207                 return -EOPNOTSUPP;
5208         }
5209
5210         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5211             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5212                 hns3_err(hw, "Unsupported flow control settings specified, "
5213                          "high_water(%u), low_water(%u), send_xon(%u) and "
5214                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5215                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5216                          pfc_conf->fc.send_xon,
5217                          pfc_conf->fc.mac_ctrl_frame_fwd);
5218                 return -EINVAL;
5219         }
5220         if (pfc_conf->fc.autoneg) {
5221                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5222                 return -EINVAL;
5223         }
5224         if (pfc_conf->fc.pause_time == 0) {
5225                 hns3_err(hw, "Invalid pause time %u setting.",
5226                          pfc_conf->fc.pause_time);
5227                 return -EINVAL;
5228         }
5229
5230         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5231             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5232                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5233                              "current_fc_status = %d", hw->current_fc_status);
5234                 return -EOPNOTSUPP;
5235         }
5236
5237         priority = pfc_conf->priority;
5238         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5239         if (hw->dcb_info.pfc_en & BIT(priority) &&
5240             hw->requested_mode == hw->current_mode &&
5241             pfc_conf->fc.pause_time == pf->pause_time)
5242                 return 0;
5243
5244         rte_spinlock_lock(&hw->lock);
5245         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5246         rte_spinlock_unlock(&hw->lock);
5247
5248         return ret;
5249 }
5250
5251 static int
5252 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5253 {
5254         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5256         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5257         int i;
5258
5259         rte_spinlock_lock(&hw->lock);
5260         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5261                 dcb_info->nb_tcs = pf->local_max_tc;
5262         else
5263                 dcb_info->nb_tcs = 1;
5264
5265         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5266                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5267         for (i = 0; i < dcb_info->nb_tcs; i++)
5268                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5269
5270         for (i = 0; i < hw->num_tc; i++) {
5271                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5272                 dcb_info->tc_queue.tc_txq[0][i].base =
5273                                                 hw->tc_queue[i].tqp_offset;
5274                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5275                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5276                                                 hw->tc_queue[i].tqp_count;
5277         }
5278         rte_spinlock_unlock(&hw->lock);
5279
5280         return 0;
5281 }
5282
5283 static int
5284 hns3_reinit_dev(struct hns3_adapter *hns)
5285 {
5286         struct hns3_hw *hw = &hns->hw;
5287         int ret;
5288
5289         ret = hns3_cmd_init(hw);
5290         if (ret) {
5291                 hns3_err(hw, "Failed to init cmd: %d", ret);
5292                 return ret;
5293         }
5294
5295         ret = hns3_reset_all_tqps(hns);
5296         if (ret) {
5297                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5298                 return ret;
5299         }
5300
5301         ret = hns3_init_hardware(hns);
5302         if (ret) {
5303                 hns3_err(hw, "Failed to init hardware: %d", ret);
5304                 return ret;
5305         }
5306
5307         ret = hns3_enable_hw_error_intr(hns, true);
5308         if (ret) {
5309                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5310                              ret);
5311                 return ret;
5312         }
5313         hns3_info(hw, "Reset done, driver initialization finished.");
5314
5315         return 0;
5316 }
5317
5318 static bool
5319 is_pf_reset_done(struct hns3_hw *hw)
5320 {
5321         uint32_t val, reg, reg_bit;
5322
5323         switch (hw->reset.level) {
5324         case HNS3_IMP_RESET:
5325                 reg = HNS3_GLOBAL_RESET_REG;
5326                 reg_bit = HNS3_IMP_RESET_BIT;
5327                 break;
5328         case HNS3_GLOBAL_RESET:
5329                 reg = HNS3_GLOBAL_RESET_REG;
5330                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5331                 break;
5332         case HNS3_FUNC_RESET:
5333                 reg = HNS3_FUN_RST_ING;
5334                 reg_bit = HNS3_FUN_RST_ING_B;
5335                 break;
5336         case HNS3_FLR_RESET:
5337         default:
5338                 hns3_err(hw, "Wait for unsupported reset level: %d",
5339                          hw->reset.level);
5340                 return true;
5341         }
5342         val = hns3_read_dev(hw, reg);
5343         if (hns3_get_bit(val, reg_bit))
5344                 return false;
5345         else
5346                 return true;
5347 }
5348
5349 bool
5350 hns3_is_reset_pending(struct hns3_adapter *hns)
5351 {
5352         struct hns3_hw *hw = &hns->hw;
5353         enum hns3_reset_level reset;
5354
5355         hns3_check_event_cause(hns, NULL);
5356         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5357         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5358                 hns3_warn(hw, "High level reset %d is pending", reset);
5359                 return true;
5360         }
5361         reset = hns3_get_reset_level(hns, &hw->reset.request);
5362         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5363                 hns3_warn(hw, "High level reset %d is request", reset);
5364                 return true;
5365         }
5366         return false;
5367 }
5368
5369 static int
5370 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5371 {
5372         struct hns3_hw *hw = &hns->hw;
5373         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5374         struct timeval tv;
5375
5376         if (wait_data->result == HNS3_WAIT_SUCCESS)
5377                 return 0;
5378         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5379                 gettimeofday(&tv, NULL);
5380                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5381                           tv.tv_sec, tv.tv_usec);
5382                 return -ETIME;
5383         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5384                 return -EAGAIN;
5385
5386         wait_data->hns = hns;
5387         wait_data->check_completion = is_pf_reset_done;
5388         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5389                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5390         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5391         wait_data->count = HNS3_RESET_WAIT_CNT;
5392         wait_data->result = HNS3_WAIT_REQUEST;
5393         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5394         return -EAGAIN;
5395 }
5396
5397 static int
5398 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5399 {
5400         struct hns3_cmd_desc desc;
5401         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5402
5403         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5404         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5405         req->fun_reset_vfid = func_id;
5406
5407         return hns3_cmd_send(hw, &desc, 1);
5408 }
5409
5410 static int
5411 hns3_imp_reset_cmd(struct hns3_hw *hw)
5412 {
5413         struct hns3_cmd_desc desc;
5414
5415         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5416         desc.data[0] = 0xeedd;
5417
5418         return hns3_cmd_send(hw, &desc, 1);
5419 }
5420
5421 static void
5422 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5423 {
5424         struct hns3_hw *hw = &hns->hw;
5425         struct timeval tv;
5426         uint32_t val;
5427
5428         gettimeofday(&tv, NULL);
5429         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5430             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5431                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5432                           tv.tv_sec, tv.tv_usec);
5433                 return;
5434         }
5435
5436         switch (reset_level) {
5437         case HNS3_IMP_RESET:
5438                 hns3_imp_reset_cmd(hw);
5439                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5440                           tv.tv_sec, tv.tv_usec);
5441                 break;
5442         case HNS3_GLOBAL_RESET:
5443                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5444                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5445                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5446                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5447                           tv.tv_sec, tv.tv_usec);
5448                 break;
5449         case HNS3_FUNC_RESET:
5450                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5451                           tv.tv_sec, tv.tv_usec);
5452                 /* schedule again to check later */
5453                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5454                 hns3_schedule_reset(hns);
5455                 break;
5456         default:
5457                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5458                 return;
5459         }
5460         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5461 }
5462
5463 static enum hns3_reset_level
5464 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5465 {
5466         struct hns3_hw *hw = &hns->hw;
5467         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5468
5469         /* Return the highest priority reset level amongst all */
5470         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5471                 reset_level = HNS3_IMP_RESET;
5472         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5473                 reset_level = HNS3_GLOBAL_RESET;
5474         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5475                 reset_level = HNS3_FUNC_RESET;
5476         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5477                 reset_level = HNS3_FLR_RESET;
5478
5479         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5480                 return HNS3_NONE_RESET;
5481
5482         return reset_level;
5483 }
5484
5485 static void
5486 hns3_record_imp_error(struct hns3_adapter *hns)
5487 {
5488         struct hns3_hw *hw = &hns->hw;
5489         uint32_t reg_val;
5490
5491         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5492         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5493                 hns3_warn(hw, "Detected IMP RD poison!");
5494                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5495                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5496                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5497         }
5498
5499         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5500                 hns3_warn(hw, "Detected IMP CMDQ error!");
5501                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5502                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5503                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5504         }
5505 }
5506
5507 static int
5508 hns3_prepare_reset(struct hns3_adapter *hns)
5509 {
5510         struct hns3_hw *hw = &hns->hw;
5511         uint32_t reg_val;
5512         int ret;
5513
5514         switch (hw->reset.level) {
5515         case HNS3_FUNC_RESET:
5516                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5517                 if (ret)
5518                         return ret;
5519
5520                 /*
5521                  * After performaning pf reset, it is not necessary to do the
5522                  * mailbox handling or send any command to firmware, because
5523                  * any mailbox handling or command to firmware is only valid
5524                  * after hns3_cmd_init is called.
5525                  */
5526                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5527                 hw->reset.stats.request_cnt++;
5528                 break;
5529         case HNS3_IMP_RESET:
5530                 hns3_record_imp_error(hns);
5531                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5532                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5533                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5534                 break;
5535         default:
5536                 break;
5537         }
5538         return 0;
5539 }
5540
5541 static int
5542 hns3_set_rst_done(struct hns3_hw *hw)
5543 {
5544         struct hns3_pf_rst_done_cmd *req;
5545         struct hns3_cmd_desc desc;
5546
5547         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5548         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5549         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5550         return hns3_cmd_send(hw, &desc, 1);
5551 }
5552
5553 static int
5554 hns3_stop_service(struct hns3_adapter *hns)
5555 {
5556         struct hns3_hw *hw = &hns->hw;
5557         struct rte_eth_dev *eth_dev;
5558
5559         eth_dev = &rte_eth_devices[hw->data->port_id];
5560         if (hw->adapter_state == HNS3_NIC_STARTED)
5561                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5562         hw->mac.link_status = ETH_LINK_DOWN;
5563
5564         hns3_set_rxtx_function(eth_dev);
5565         rte_wmb();
5566         /* Disable datapath on secondary process. */
5567         hns3_mp_req_stop_rxtx(eth_dev);
5568         rte_delay_ms(hw->tqps_num);
5569
5570         rte_spinlock_lock(&hw->lock);
5571         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5572             hw->adapter_state == HNS3_NIC_STOPPING) {
5573                 hns3_enable_all_queues(hw, false);
5574                 hns3_do_stop(hns);
5575                 hw->reset.mbuf_deferred_free = true;
5576         } else
5577                 hw->reset.mbuf_deferred_free = false;
5578
5579         /*
5580          * It is cumbersome for hardware to pick-and-choose entries for deletion
5581          * from table space. Hence, for function reset software intervention is
5582          * required to delete the entries
5583          */
5584         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5585                 hns3_configure_all_mc_mac_addr(hns, true);
5586         rte_spinlock_unlock(&hw->lock);
5587
5588         return 0;
5589 }
5590
5591 static int
5592 hns3_start_service(struct hns3_adapter *hns)
5593 {
5594         struct hns3_hw *hw = &hns->hw;
5595         struct rte_eth_dev *eth_dev;
5596
5597         if (hw->reset.level == HNS3_IMP_RESET ||
5598             hw->reset.level == HNS3_GLOBAL_RESET)
5599                 hns3_set_rst_done(hw);
5600         eth_dev = &rte_eth_devices[hw->data->port_id];
5601         hns3_set_rxtx_function(eth_dev);
5602         hns3_mp_req_start_rxtx(eth_dev);
5603         if (hw->adapter_state == HNS3_NIC_STARTED) {
5604                 hns3_service_handler(eth_dev);
5605
5606                 /* Enable interrupt of all rx queues before enabling queues */
5607                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5608                 /*
5609                  * Enable state of each rxq and txq will be recovered after
5610                  * reset, so we need to restore them before enable all tqps;
5611                  */
5612                 hns3_restore_tqp_enable_state(hw);
5613                 /*
5614                  * When finished the initialization, enable queues to receive
5615                  * and transmit packets.
5616                  */
5617                 hns3_enable_all_queues(hw, true);
5618         }
5619
5620         return 0;
5621 }
5622
5623 static int
5624 hns3_restore_conf(struct hns3_adapter *hns)
5625 {
5626         struct hns3_hw *hw = &hns->hw;
5627         int ret;
5628
5629         ret = hns3_configure_all_mac_addr(hns, false);
5630         if (ret)
5631                 return ret;
5632
5633         ret = hns3_configure_all_mc_mac_addr(hns, false);
5634         if (ret)
5635                 goto err_mc_mac;
5636
5637         ret = hns3_dev_promisc_restore(hns);
5638         if (ret)
5639                 goto err_promisc;
5640
5641         ret = hns3_restore_vlan_table(hns);
5642         if (ret)
5643                 goto err_promisc;
5644
5645         ret = hns3_restore_vlan_conf(hns);
5646         if (ret)
5647                 goto err_promisc;
5648
5649         ret = hns3_restore_all_fdir_filter(hns);
5650         if (ret)
5651                 goto err_promisc;
5652
5653         ret = hns3_restore_rx_interrupt(hw);
5654         if (ret)
5655                 goto err_promisc;
5656
5657         ret = hns3_restore_gro_conf(hw);
5658         if (ret)
5659                 goto err_promisc;
5660
5661         ret = hns3_restore_fec(hw);
5662         if (ret)
5663                 goto err_promisc;
5664
5665         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5666                 ret = hns3_do_start(hns, false);
5667                 if (ret)
5668                         goto err_promisc;
5669                 hns3_info(hw, "hns3 dev restart successful!");
5670         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5671                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5672         return 0;
5673
5674 err_promisc:
5675         hns3_configure_all_mc_mac_addr(hns, true);
5676 err_mc_mac:
5677         hns3_configure_all_mac_addr(hns, true);
5678         return ret;
5679 }
5680
5681 static void
5682 hns3_reset_service(void *param)
5683 {
5684         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5685         struct hns3_hw *hw = &hns->hw;
5686         enum hns3_reset_level reset_level;
5687         struct timeval tv_delta;
5688         struct timeval tv_start;
5689         struct timeval tv;
5690         uint64_t msec;
5691         int ret;
5692
5693         /*
5694          * The interrupt is not triggered within the delay time.
5695          * The interrupt may have been lost. It is necessary to handle
5696          * the interrupt to recover from the error.
5697          */
5698         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5699                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5700                 hns3_err(hw, "Handling interrupts in delayed tasks");
5701                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5702                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5703                 if (reset_level == HNS3_NONE_RESET) {
5704                         hns3_err(hw, "No reset level is set, try IMP reset");
5705                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5706                 }
5707         }
5708         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5709
5710         /*
5711          * Check if there is any ongoing reset in the hardware. This status can
5712          * be checked from reset_pending. If there is then, we need to wait for
5713          * hardware to complete reset.
5714          *    a. If we are able to figure out in reasonable time that hardware
5715          *       has fully resetted then, we can proceed with driver, client
5716          *       reset.
5717          *    b. else, we can come back later to check this status so re-sched
5718          *       now.
5719          */
5720         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5721         if (reset_level != HNS3_NONE_RESET) {
5722                 gettimeofday(&tv_start, NULL);
5723                 ret = hns3_reset_process(hns, reset_level);
5724                 gettimeofday(&tv, NULL);
5725                 timersub(&tv, &tv_start, &tv_delta);
5726                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5727                        tv_delta.tv_usec / USEC_PER_MSEC;
5728                 if (msec > HNS3_RESET_PROCESS_MS)
5729                         hns3_err(hw, "%d handle long time delta %" PRIx64
5730                                      " ms time=%ld.%.6ld",
5731                                  hw->reset.level, msec,
5732                                  tv.tv_sec, tv.tv_usec);
5733                 if (ret == -EAGAIN)
5734                         return;
5735         }
5736
5737         /* Check if we got any *new* reset requests to be honored */
5738         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5739         if (reset_level != HNS3_NONE_RESET)
5740                 hns3_msix_process(hns, reset_level);
5741 }
5742
5743 static unsigned int
5744 hns3_get_speed_capa_num(uint16_t device_id)
5745 {
5746         unsigned int num;
5747
5748         switch (device_id) {
5749         case HNS3_DEV_ID_25GE:
5750         case HNS3_DEV_ID_25GE_RDMA:
5751                 num = 2;
5752                 break;
5753         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5754         case HNS3_DEV_ID_200G_RDMA:
5755                 num = 1;
5756                 break;
5757         default:
5758                 num = 0;
5759                 break;
5760         }
5761
5762         return num;
5763 }
5764
5765 static int
5766 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5767                         uint16_t device_id)
5768 {
5769         switch (device_id) {
5770         case HNS3_DEV_ID_25GE:
5771         /* fallthrough */
5772         case HNS3_DEV_ID_25GE_RDMA:
5773                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5774                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5775
5776                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5777                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5778                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5779                 break;
5780         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5781                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5782                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5783                 break;
5784         case HNS3_DEV_ID_200G_RDMA:
5785                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5786                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5787                 break;
5788         default:
5789                 return -ENOTSUP;
5790         }
5791
5792         return 0;
5793 }
5794
5795 static int
5796 hns3_fec_get_capability(struct rte_eth_dev *dev,
5797                         struct rte_eth_fec_capa *speed_fec_capa,
5798                         unsigned int num)
5799 {
5800         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5802         uint16_t device_id = pci_dev->id.device_id;
5803         unsigned int capa_num;
5804         int ret;
5805
5806         capa_num = hns3_get_speed_capa_num(device_id);
5807         if (capa_num == 0) {
5808                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5809                          device_id);
5810                 return -ENOTSUP;
5811         }
5812
5813         if (speed_fec_capa == NULL || num < capa_num)
5814                 return capa_num;
5815
5816         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5817         if (ret)
5818                 return -ENOTSUP;
5819
5820         return capa_num;
5821 }
5822
5823 static int
5824 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5825 {
5826         struct hns3_config_fec_cmd *req;
5827         struct hns3_cmd_desc desc;
5828         int ret;
5829
5830         /*
5831          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5832          * in device of link speed
5833          * below 10 Gbps.
5834          */
5835         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5836                 *state = 0;
5837                 return 0;
5838         }
5839
5840         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5841         req = (struct hns3_config_fec_cmd *)desc.data;
5842         ret = hns3_cmd_send(hw, &desc, 1);
5843         if (ret) {
5844                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5845                          ret);
5846                 return ret;
5847         }
5848
5849         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5850         return 0;
5851 }
5852
5853 static int
5854 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5855 {
5856 #define QUERY_ACTIVE_SPEED      1
5857         struct hns3_sfp_speed_cmd *resp;
5858         uint32_t tmp_fec_capa;
5859         uint8_t auto_state;
5860         struct hns3_cmd_desc desc;
5861         int ret;
5862
5863         /*
5864          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5865          * configured FEC mode is returned.
5866          * If link is up, current FEC mode is returned.
5867          */
5868         if (hw->mac.link_status == ETH_LINK_DOWN) {
5869                 ret = get_current_fec_auto_state(hw, &auto_state);
5870                 if (ret)
5871                         return ret;
5872
5873                 if (auto_state == 0x1) {
5874                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5875                         return 0;
5876                 }
5877         }
5878
5879         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5880         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5881         resp->query_type = QUERY_ACTIVE_SPEED;
5882
5883         ret = hns3_cmd_send(hw, &desc, 1);
5884         if (ret == -EOPNOTSUPP) {
5885                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5886                 return ret;
5887         } else if (ret) {
5888                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5889                 return ret;
5890         }
5891
5892         /*
5893          * FEC mode order defined in hns3 hardware is inconsistend with
5894          * that defined in the ethdev library. So the sequence needs
5895          * to be converted.
5896          */
5897         switch (resp->active_fec) {
5898         case HNS3_HW_FEC_MODE_NOFEC:
5899                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5900                 break;
5901         case HNS3_HW_FEC_MODE_BASER:
5902                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5903                 break;
5904         case HNS3_HW_FEC_MODE_RS:
5905                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5906                 break;
5907         default:
5908                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5909                 break;
5910         }
5911
5912         *fec_capa = tmp_fec_capa;
5913         return 0;
5914 }
5915
5916 static int
5917 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5918 {
5919         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5920
5921         return hns3_fec_get_internal(hw, fec_capa);
5922 }
5923
5924 static int
5925 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5926 {
5927         struct hns3_config_fec_cmd *req;
5928         struct hns3_cmd_desc desc;
5929         int ret;
5930
5931         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5932
5933         req = (struct hns3_config_fec_cmd *)desc.data;
5934         switch (mode) {
5935         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5936                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5937                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5938                 break;
5939         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5940                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5941                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5942                 break;
5943         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5944                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5945                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5946                 break;
5947         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5948                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5949                 break;
5950         default:
5951                 return 0;
5952         }
5953         ret = hns3_cmd_send(hw, &desc, 1);
5954         if (ret)
5955                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5956
5957         return ret;
5958 }
5959
5960 static uint32_t
5961 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5962 {
5963         struct hns3_mac *mac = &hw->mac;
5964         uint32_t cur_capa;
5965
5966         switch (mac->link_speed) {
5967         case ETH_SPEED_NUM_10G:
5968                 cur_capa = fec_capa[1].capa;
5969                 break;
5970         case ETH_SPEED_NUM_25G:
5971         case ETH_SPEED_NUM_100G:
5972         case ETH_SPEED_NUM_200G:
5973                 cur_capa = fec_capa[0].capa;
5974                 break;
5975         default:
5976                 cur_capa = 0;
5977                 break;
5978         }
5979
5980         return cur_capa;
5981 }
5982
5983 static bool
5984 is_fec_mode_one_bit_set(uint32_t mode)
5985 {
5986         int cnt = 0;
5987         uint8_t i;
5988
5989         for (i = 0; i < sizeof(mode); i++)
5990                 if (mode >> i & 0x1)
5991                         cnt++;
5992
5993         return cnt == 1 ? true : false;
5994 }
5995
5996 static int
5997 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5998 {
5999 #define FEC_CAPA_NUM 2
6000         struct hns3_adapter *hns = dev->data->dev_private;
6001         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6002         struct hns3_pf *pf = &hns->pf;
6003
6004         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6005         uint32_t cur_capa;
6006         uint32_t num = FEC_CAPA_NUM;
6007         int ret;
6008
6009         ret = hns3_fec_get_capability(dev, fec_capa, num);
6010         if (ret < 0)
6011                 return ret;
6012
6013         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6014         if (!is_fec_mode_one_bit_set(mode))
6015                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6016                              "FEC mode should be only one bit set", mode);
6017
6018         /*
6019          * Check whether the configured mode is within the FEC capability.
6020          * If not, the configured mode will not be supported.
6021          */
6022         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6023         if (!(cur_capa & mode)) {
6024                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6025                 return -EINVAL;
6026         }
6027
6028         ret = hns3_set_fec_hw(hw, mode);
6029         if (ret)
6030                 return ret;
6031
6032         pf->fec_mode = mode;
6033         return 0;
6034 }
6035
6036 static int
6037 hns3_restore_fec(struct hns3_hw *hw)
6038 {
6039         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6040         struct hns3_pf *pf = &hns->pf;
6041         uint32_t mode = pf->fec_mode;
6042         int ret;
6043
6044         ret = hns3_set_fec_hw(hw, mode);
6045         if (ret)
6046                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6047                          mode, ret);
6048
6049         return ret;
6050 }
6051
6052 static int
6053 hns3_query_dev_fec_info(struct hns3_hw *hw)
6054 {
6055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6056         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6057         int ret;
6058
6059         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6060         if (ret)
6061                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6062
6063         return ret;
6064 }
6065
6066 static const struct eth_dev_ops hns3_eth_dev_ops = {
6067         .dev_configure      = hns3_dev_configure,
6068         .dev_start          = hns3_dev_start,
6069         .dev_stop           = hns3_dev_stop,
6070         .dev_close          = hns3_dev_close,
6071         .promiscuous_enable = hns3_dev_promiscuous_enable,
6072         .promiscuous_disable = hns3_dev_promiscuous_disable,
6073         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6074         .allmulticast_disable = hns3_dev_allmulticast_disable,
6075         .mtu_set            = hns3_dev_mtu_set,
6076         .stats_get          = hns3_stats_get,
6077         .stats_reset        = hns3_stats_reset,
6078         .xstats_get         = hns3_dev_xstats_get,
6079         .xstats_get_names   = hns3_dev_xstats_get_names,
6080         .xstats_reset       = hns3_dev_xstats_reset,
6081         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6082         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6083         .dev_infos_get          = hns3_dev_infos_get,
6084         .fw_version_get         = hns3_fw_version_get,
6085         .rx_queue_setup         = hns3_rx_queue_setup,
6086         .tx_queue_setup         = hns3_tx_queue_setup,
6087         .rx_queue_release       = hns3_dev_rx_queue_release,
6088         .tx_queue_release       = hns3_dev_tx_queue_release,
6089         .rx_queue_start         = hns3_dev_rx_queue_start,
6090         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6091         .tx_queue_start         = hns3_dev_tx_queue_start,
6092         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6093         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6094         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6095         .rxq_info_get           = hns3_rxq_info_get,
6096         .txq_info_get           = hns3_txq_info_get,
6097         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6098         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6099         .flow_ctrl_get          = hns3_flow_ctrl_get,
6100         .flow_ctrl_set          = hns3_flow_ctrl_set,
6101         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6102         .mac_addr_add           = hns3_add_mac_addr,
6103         .mac_addr_remove        = hns3_remove_mac_addr,
6104         .mac_addr_set           = hns3_set_default_mac_addr,
6105         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6106         .link_update            = hns3_dev_link_update,
6107         .rss_hash_update        = hns3_dev_rss_hash_update,
6108         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6109         .reta_update            = hns3_dev_rss_reta_update,
6110         .reta_query             = hns3_dev_rss_reta_query,
6111         .filter_ctrl            = hns3_dev_filter_ctrl,
6112         .vlan_filter_set        = hns3_vlan_filter_set,
6113         .vlan_tpid_set          = hns3_vlan_tpid_set,
6114         .vlan_offload_set       = hns3_vlan_offload_set,
6115         .vlan_pvid_set          = hns3_vlan_pvid_set,
6116         .get_reg                = hns3_get_regs,
6117         .get_dcb_info           = hns3_get_dcb_info,
6118         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6119         .fec_get_capability     = hns3_fec_get_capability,
6120         .fec_get                = hns3_fec_get,
6121         .fec_set                = hns3_fec_set,
6122         .tm_ops_get             = hns3_tm_ops_get,
6123 };
6124
6125 static const struct hns3_reset_ops hns3_reset_ops = {
6126         .reset_service       = hns3_reset_service,
6127         .stop_service        = hns3_stop_service,
6128         .prepare_reset       = hns3_prepare_reset,
6129         .wait_hardware_ready = hns3_wait_hardware_ready,
6130         .reinit_dev          = hns3_reinit_dev,
6131         .restore_conf        = hns3_restore_conf,
6132         .start_service       = hns3_start_service,
6133 };
6134
6135 static int
6136 hns3_dev_init(struct rte_eth_dev *eth_dev)
6137 {
6138         struct hns3_adapter *hns = eth_dev->data->dev_private;
6139         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6140         struct rte_ether_addr *eth_addr;
6141         struct hns3_hw *hw = &hns->hw;
6142         int ret;
6143
6144         PMD_INIT_FUNC_TRACE();
6145
6146         eth_dev->process_private = (struct hns3_process_private *)
6147             rte_zmalloc_socket("hns3_filter_list",
6148                                sizeof(struct hns3_process_private),
6149                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6150         if (eth_dev->process_private == NULL) {
6151                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6152                 return -ENOMEM;
6153         }
6154         /* initialize flow filter lists */
6155         hns3_filterlist_init(eth_dev);
6156
6157         hns3_set_rxtx_function(eth_dev);
6158         eth_dev->dev_ops = &hns3_eth_dev_ops;
6159         eth_dev->rx_queue_count = hns3_rx_queue_count;
6160         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6161                 ret = hns3_mp_init_secondary();
6162                 if (ret) {
6163                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6164                                      "process, ret = %d", ret);
6165                         goto err_mp_init_secondary;
6166                 }
6167
6168                 hw->secondary_cnt++;
6169                 return 0;
6170         }
6171
6172         ret = hns3_mp_init_primary();
6173         if (ret) {
6174                 PMD_INIT_LOG(ERR,
6175                              "Failed to init for primary process, ret = %d",
6176                              ret);
6177                 goto err_mp_init_primary;
6178         }
6179
6180         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6181         hns->is_vf = false;
6182         hw->data = eth_dev->data;
6183
6184         /*
6185          * Set default max packet size according to the mtu
6186          * default vale in DPDK frame.
6187          */
6188         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6189
6190         ret = hns3_reset_init(hw);
6191         if (ret)
6192                 goto err_init_reset;
6193         hw->reset.ops = &hns3_reset_ops;
6194
6195         ret = hns3_init_pf(eth_dev);
6196         if (ret) {
6197                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6198                 goto err_init_pf;
6199         }
6200
6201         /* Allocate memory for storing MAC addresses */
6202         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6203                                                sizeof(struct rte_ether_addr) *
6204                                                HNS3_UC_MACADDR_NUM, 0);
6205         if (eth_dev->data->mac_addrs == NULL) {
6206                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6207                              "to store MAC addresses",
6208                              sizeof(struct rte_ether_addr) *
6209                              HNS3_UC_MACADDR_NUM);
6210                 ret = -ENOMEM;
6211                 goto err_rte_zmalloc;
6212         }
6213
6214         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6215         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6216                 rte_eth_random_addr(hw->mac.mac_addr);
6217                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6218                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6219                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6220                           "unicast address, using random MAC address %s",
6221                           mac_str);
6222         }
6223         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6224                             &eth_dev->data->mac_addrs[0]);
6225
6226         hw->adapter_state = HNS3_NIC_INITIALIZED;
6227
6228         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6229                 hns3_err(hw, "Reschedule reset service after dev_init");
6230                 hns3_schedule_reset(hns);
6231         } else {
6232                 /* IMP will wait ready flag before reset */
6233                 hns3_notify_reset_ready(hw, false);
6234         }
6235
6236         hns3_info(hw, "hns3 dev initialization successful!");
6237         return 0;
6238
6239 err_rte_zmalloc:
6240         hns3_uninit_pf(eth_dev);
6241
6242 err_init_pf:
6243         rte_free(hw->reset.wait_data);
6244
6245 err_init_reset:
6246         hns3_mp_uninit_primary();
6247
6248 err_mp_init_primary:
6249 err_mp_init_secondary:
6250         eth_dev->dev_ops = NULL;
6251         eth_dev->rx_pkt_burst = NULL;
6252         eth_dev->tx_pkt_burst = NULL;
6253         eth_dev->tx_pkt_prepare = NULL;
6254         rte_free(eth_dev->process_private);
6255         eth_dev->process_private = NULL;
6256         return ret;
6257 }
6258
6259 static int
6260 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6261 {
6262         struct hns3_adapter *hns = eth_dev->data->dev_private;
6263         struct hns3_hw *hw = &hns->hw;
6264
6265         PMD_INIT_FUNC_TRACE();
6266
6267         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6268                 rte_free(eth_dev->process_private);
6269                 eth_dev->process_private = NULL;
6270                 return 0;
6271         }
6272
6273         if (hw->adapter_state < HNS3_NIC_CLOSING)
6274                 hns3_dev_close(eth_dev);
6275
6276         hw->adapter_state = HNS3_NIC_REMOVED;
6277         return 0;
6278 }
6279
6280 static int
6281 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6282                    struct rte_pci_device *pci_dev)
6283 {
6284         return rte_eth_dev_pci_generic_probe(pci_dev,
6285                                              sizeof(struct hns3_adapter),
6286                                              hns3_dev_init);
6287 }
6288
6289 static int
6290 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6291 {
6292         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6293 }
6294
6295 static const struct rte_pci_id pci_id_hns3_map[] = {
6296         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6297         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6298         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6299         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6300         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6301         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6302         { .vendor_id = 0, }, /* sentinel */
6303 };
6304
6305 static struct rte_pci_driver rte_hns3_pmd = {
6306         .id_table = pci_id_hns3_map,
6307         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6308         .probe = eth_hns3_pci_probe,
6309         .remove = eth_hns3_pci_remove,
6310 };
6311
6312 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6313 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6314 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6315 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6316 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);