drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 109
 110 void hns3_ether_format_addr(char *buf, uint16_t size,
 111                             const struct rte_ether_addr *ether_addr)
 112 {
 113         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 114                 ether_addr->addr_bytes[0],
 115                 ether_addr->addr_bytes[4],
 116                 ether_addr->addr_bytes[5]);
 117 }
 118
 119 static void
 120 hns3_pf_disable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 123 }
 124
 125 static void
 126 hns3_pf_enable_irq0(struct hns3_hw *hw)
 127 {
 128         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 129 }
 130
 131 static enum hns3_evt_cause
 132 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 133                           uint32_t *vec_val)
 134 {
 135         struct hns3_hw *hw = &hns->hw;
 136
 137         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 138         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 139         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 140         if (!is_delay) {
 141                 hw->reset.stats.imp_cnt++;
 142                 hns3_warn(hw, "IMP reset detected, clear reset status");
 143         } else {
 144                 hns3_schedule_delayed_reset(hns);
 145                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 146         }
 147
 148         return HNS3_VECTOR0_EVENT_RST;
 149 }
 150
 151 static enum hns3_evt_cause
 152 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 153                              uint32_t *vec_val)
 154 {
 155         struct hns3_hw *hw = &hns->hw;
 156
 157         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 158         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 159         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 160         if (!is_delay) {
 161                 hw->reset.stats.global_cnt++;
 162                 hns3_warn(hw, "Global reset detected, clear reset status");
 163         } else {
 164                 hns3_schedule_delayed_reset(hns);
 165                 hns3_warn(hw,
 166                           "Global reset detected, don't clear reset status");
 167         }
 168
 169         return HNS3_VECTOR0_EVENT_RST;
 170 }
 171
 172 static enum hns3_evt_cause
 173 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 174 {
 175         struct hns3_hw *hw = &hns->hw;
 176         uint32_t vector0_int_stats;
 177         uint32_t cmdq_src_val;
 178         uint32_t hw_err_src_reg;
 179         uint32_t val;
 180         enum hns3_evt_cause ret;
 181         bool is_delay;
 182
 183         /* fetch the events from their corresponding regs */
 184         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 185         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 186         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 187
 188         is_delay = clearval == NULL ? true : false;
 189         /*
 190          * Assumption: If by any chance reset and mailbox events are reported
 191          * together then we will only process reset event and defer the
 192          * processing of the mailbox events. Since, we would have not cleared
 193          * RX CMDQ event this time we would receive again another interrupt
 194          * from H/W just for the mailbox.
 195          */
 196         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 197                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 198                 goto out;
 199         }
 200
 201         /* Global reset */
 202         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 203                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 204                 goto out;
 205         }
 206
 207         /* Check for vector0 1588 event source */
 208         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 209                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 210                 ret = HNS3_VECTOR0_EVENT_PTP;
 211                 goto out;
 212         }
 213
 214         /* check for vector0 msix event source */
 215         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 216             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 217                 val = vector0_int_stats | hw_err_src_reg;
 218                 ret = HNS3_VECTOR0_EVENT_ERR;
 219                 goto out;
 220         }
 221
 222         /* check for vector0 mailbox(=CMDQ RX) event source */
 223         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 224                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 225                 val = cmdq_src_val;
 226                 ret = HNS3_VECTOR0_EVENT_MBX;
 227                 goto out;
 228         }
 229
 230         val = vector0_int_stats;
 231         ret = HNS3_VECTOR0_EVENT_OTHER;
 232 out:
 233
 234         if (clearval)
 235                 *clearval = val;
 236         return ret;
 237 }
 238
 239 static bool
 240 hns3_is_1588_event_type(uint32_t event_type)
 241 {
 242         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 243 }
 244
 245 static void
 246 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 247 {
 248         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 249             hns3_is_1588_event_type(event_type))
 250                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 251         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 252                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 253 }
 254
 255 static void
 256 hns3_clear_all_event_cause(struct hns3_hw *hw)
 257 {
 258         uint32_t vector0_int_stats;
 259         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 260
 261         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 262                 hns3_warn(hw, "Probe during IMP reset interrupt");
 263
 264         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 265                 hns3_warn(hw, "Probe during Global reset interrupt");
 266
 267         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 268                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 270                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 272         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 273                                 BIT(HNS3_VECTOR0_1588_INT_B));
 274 }
 275
 276 static void
 277 hns3_handle_mac_tnl(struct hns3_hw *hw)
 278 {
 279         struct hns3_cmd_desc desc;
 280         uint32_t status;
 281         int ret;
 282
 283         /* query and clear mac tnl interrupt */
 284         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 285         ret = hns3_cmd_send(hw, &desc, 1);
 286         if (ret) {
 287                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 288                 return;
 289         }
 290
 291         status = rte_le_to_cpu_32(desc.data[0]);
 292         if (status) {
 293                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 294                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 295                                           false);
 296                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 297                 ret = hns3_cmd_send(hw, &desc, 1);
 298                 if (ret)
 299                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 300                                  ret);
 301         }
 302 }
 303
 304 static void
 305 hns3_interrupt_handler(void *param)
 306 {
 307         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 308         struct hns3_adapter *hns = dev->data->dev_private;
 309         struct hns3_hw *hw = &hns->hw;
 310         enum hns3_evt_cause event_cause;
 311         uint32_t clearval = 0;
 312         uint32_t vector0_int;
 313         uint32_t ras_int;
 314         uint32_t cmdq_int;
 315
 316         /* Disable interrupt */
 317         hns3_pf_disable_irq0(hw);
 318
 319         event_cause = hns3_check_event_cause(hns, &clearval);
 320         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 321         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 322         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 323         /* vector 0 interrupt is shared with reset and mailbox source events. */
 324         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 325                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 326                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 327                           vector0_int, ras_int, cmdq_int);
 328                 hns3_handle_mac_tnl(hw);
 329                 hns3_handle_error(hns);
 330         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 331                 hns3_warn(hw, "received reset interrupt");
 332                 hns3_schedule_reset(hns);
 333         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 334                 hns3_dev_handle_mbx_msg(hw);
 335         } else {
 336                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 337                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 338                           vector0_int, ras_int, cmdq_int);
 339         }
 340
 341         hns3_clear_event_cause(hw, event_cause, clearval);
 342         /* Enable interrupt if it is not cause by reset */
 343         hns3_pf_enable_irq0(hw);
 344 }
 345
 346 static int
 347 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 348 {
 349 #define HNS3_VLAN_ID_OFFSET_STEP        160
 350 #define HNS3_VLAN_BYTE_SIZE             8
 351         struct hns3_vlan_filter_pf_cfg_cmd *req;
 352         struct hns3_hw *hw = &hns->hw;
 353         uint8_t vlan_offset_byte_val;
 354         struct hns3_cmd_desc desc;
 355         uint8_t vlan_offset_byte;
 356         uint8_t vlan_offset_base;
 357         int ret;
 358
 359         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 360
 361         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 362         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 363                            HNS3_VLAN_BYTE_SIZE;
 364         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 365
 366         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 367         req->vlan_offset = vlan_offset_base;
 368         req->vlan_cfg = on ? 0 : 1;
 369         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 370
 371         ret = hns3_cmd_send(hw, &desc, 1);
 372         if (ret)
 373                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 374                          vlan_id, ret);
 375
 376         return ret;
 377 }
 378
 379 static void
 380 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 381 {
 382         struct hns3_user_vlan_table *vlan_entry;
 383         struct hns3_pf *pf = &hns->pf;
 384
 385         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 386                 if (vlan_entry->vlan_id == vlan_id) {
 387                         if (vlan_entry->hd_tbl_status)
 388                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 389                         LIST_REMOVE(vlan_entry, next);
 390                         rte_free(vlan_entry);
 391                         break;
 392                 }
 393         }
 394 }
 395
 396 static void
 397 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 398                         bool writen_to_tbl)
 399 {
 400         struct hns3_user_vlan_table *vlan_entry;
 401         struct hns3_hw *hw = &hns->hw;
 402         struct hns3_pf *pf = &hns->pf;
 403
 404         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 405                 if (vlan_entry->vlan_id == vlan_id)
 406                         return;
 407         }
 408
 409         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 410         if (vlan_entry == NULL) {
 411                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 412                 return;
 413         }
 414
 415         vlan_entry->hd_tbl_status = writen_to_tbl;
 416         vlan_entry->vlan_id = vlan_id;
 417
 418         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 419 }
 420
 421 static int
 422 hns3_restore_vlan_table(struct hns3_adapter *hns)
 423 {
 424         struct hns3_user_vlan_table *vlan_entry;
 425         struct hns3_hw *hw = &hns->hw;
 426         struct hns3_pf *pf = &hns->pf;
 427         uint16_t vlan_id;
 428         int ret = 0;
 429
 430         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 431                 return hns3_vlan_pvid_configure(hns,
 432                                                 hw->port_base_vlan_cfg.pvid, 1);
 433
 434         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 435                 if (vlan_entry->hd_tbl_status) {
 436                         vlan_id = vlan_entry->vlan_id;
 437                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 438                         if (ret)
 439                                 break;
 440                 }
 441         }
 442
 443         return ret;
 444 }
 445
 446 static int
 447 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 448 {
 449         struct hns3_hw *hw = &hns->hw;
 450         bool writen_to_tbl = false;
 451         int ret = 0;
 452
 453         /*
 454          * When vlan filter is enabled, hardware regards packets without vlan
 455          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 456          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 457          */
 458         if (on == 0 && vlan_id == 0)
 459                 return 0;
 460
 461         /*
 462          * When port base vlan enabled, we use port base vlan as the vlan
 463          * filter condition. In this case, we don't update vlan filter table
 464          * when user add new vlan or remove exist vlan, just update the
 465          * vlan list. The vlan id in vlan list will be written in vlan filter
 466          * table until port base vlan disabled
 467          */
 468         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 469                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 470                 writen_to_tbl = true;
 471         }
 472
 473         if (ret == 0) {
 474                 if (on)
 475                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 476                 else
 477                         hns3_rm_dev_vlan_table(hns, vlan_id);
 478         }
 479         return ret;
 480 }
 481
 482 static int
 483 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 484 {
 485         struct hns3_adapter *hns = dev->data->dev_private;
 486         struct hns3_hw *hw = &hns->hw;
 487         int ret;
 488
 489         rte_spinlock_lock(&hw->lock);
 490         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 491         rte_spinlock_unlock(&hw->lock);
 492         return ret;
 493 }
 494
 495 static int
 496 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 497                          uint16_t tpid)
 498 {
 499         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 500         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 501         struct hns3_hw *hw = &hns->hw;
 502         struct hns3_cmd_desc desc;
 503         int ret;
 504
 505         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 506              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 507                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 508                 return -EINVAL;
 509         }
 510
 511         if (tpid != RTE_ETHER_TYPE_VLAN) {
 512                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 513                 return -EINVAL;
 514         }
 515
 516         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 517         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 518
 519         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 520                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 521                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 522         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 523                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 527         }
 528
 529         ret = hns3_cmd_send(hw, &desc, 1);
 530         if (ret) {
 531                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 532                          ret);
 533                 return ret;
 534         }
 535
 536         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 537
 538         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 539         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 540         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 541
 542         ret = hns3_cmd_send(hw, &desc, 1);
 543         if (ret)
 544                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 545                          ret);
 546         return ret;
 547 }
 548
 549 static int
 550 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 551                    uint16_t tpid)
 552 {
 553         struct hns3_adapter *hns = dev->data->dev_private;
 554         struct hns3_hw *hw = &hns->hw;
 555         int ret;
 556
 557         rte_spinlock_lock(&hw->lock);
 558         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 559         rte_spinlock_unlock(&hw->lock);
 560         return ret;
 561 }
 562
 563 static int
 564 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 565                              struct hns3_rx_vtag_cfg *vcfg)
 566 {
 567         struct hns3_vport_vtag_rx_cfg_cmd *req;
 568         struct hns3_hw *hw = &hns->hw;
 569         struct hns3_cmd_desc desc;
 570         uint16_t vport_id;
 571         uint8_t bitmap;
 572         int ret;
 573
 574         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 575
 576         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 578                      vcfg->strip_tag1_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 580                      vcfg->strip_tag2_en ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 582                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 583         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 584                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 585
 586         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 588                      vcfg->strip_tag1_discard_en ? 1 : 0);
 589         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 590                      vcfg->strip_tag2_discard_en ? 1 : 0);
 591         /*
 592          * In current version VF is not supported when PF is driven by DPDK
 593          * driver, just need to configure parameters for PF vport.
 594          */
 595         vport_id = HNS3_PF_FUNC_ID;
 596         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 597         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 598         req->vf_bitmap[req->vf_offset] = bitmap;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 603         return ret;
 604 }
 605
 606 static void
 607 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 608                            struct hns3_rx_vtag_cfg *vcfg)
 609 {
 610         struct hns3_pf *pf = &hns->pf;
 611         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 612 }
 613
 614 static void
 615 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 616                            struct hns3_tx_vtag_cfg *vcfg)
 617 {
 618         struct hns3_pf *pf = &hns->pf;
 619         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 620 }
 621
 622 static int
 623 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 624 {
 625         struct hns3_rx_vtag_cfg rxvlan_cfg;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 630                 rxvlan_cfg.strip_tag1_en = false;
 631                 rxvlan_cfg.strip_tag2_en = enable;
 632                 rxvlan_cfg.strip_tag2_discard_en = false;
 633         } else {
 634                 rxvlan_cfg.strip_tag1_en = enable;
 635                 rxvlan_cfg.strip_tag2_en = true;
 636                 rxvlan_cfg.strip_tag2_discard_en = true;
 637         }
 638
 639         rxvlan_cfg.strip_tag1_discard_en = false;
 640         rxvlan_cfg.vlan1_vlan_prionly = false;
 641         rxvlan_cfg.vlan2_vlan_prionly = false;
 642         rxvlan_cfg.rx_vlan_offload_en = enable;
 643
 644         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 645         if (ret) {
 646                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 647                 return ret;
 648         }
 649
 650         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 651
 652         return ret;
 653 }
 654
 655 static int
 656 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 657                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 658 {
 659         struct hns3_vlan_filter_ctrl_cmd *req;
 660         struct hns3_cmd_desc desc;
 661         int ret;
 662
 663         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 664
 665         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 666         req->vlan_type = vlan_type;
 667         req->vlan_fe = filter_en ? fe_type : 0;
 668         req->vf_id = vf_id;
 669
 670         ret = hns3_cmd_send(hw, &desc, 1);
 671         if (ret)
 672                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 673
 674         return ret;
 675 }
 676
 677 static int
 678 hns3_vlan_filter_init(struct hns3_adapter *hns)
 679 {
 680         struct hns3_hw *hw = &hns->hw;
 681         int ret;
 682
 683         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 684                                         HNS3_FILTER_FE_EGRESS, false,
 685                                         HNS3_PF_FUNC_ID);
 686         if (ret) {
 687                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 688                 return ret;
 689         }
 690
 691         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 692                                         HNS3_FILTER_FE_INGRESS, false,
 693                                         HNS3_PF_FUNC_ID);
 694         if (ret)
 695                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 702 {
 703         struct hns3_hw *hw = &hns->hw;
 704         int ret;
 705
 706         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 707                                         HNS3_FILTER_FE_INGRESS, enable,
 708                                         HNS3_PF_FUNC_ID);
 709         if (ret)
 710                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 711                          enable ? "enable" : "disable", ret);
 712
 713         return ret;
 714 }
 715
 716 static int
 717 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 718 {
 719         struct hns3_adapter *hns = dev->data->dev_private;
 720         struct hns3_hw *hw = &hns->hw;
 721         struct rte_eth_rxmode *rxmode;
 722         unsigned int tmp_mask;
 723         bool enable;
 724         int ret = 0;
 725
 726         rte_spinlock_lock(&hw->lock);
 727         rxmode = &dev->data->dev_conf.rxmode;
 728         tmp_mask = (unsigned int)mask;
 729         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 730                 /* ignore vlan filter configuration during promiscuous mode */
 731                 if (!dev->data->promiscuous) {
 732                         /* Enable or disable VLAN filter */
 733                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 734                                  true : false;
 735
 736                         ret = hns3_enable_vlan_filter(hns, enable);
 737                         if (ret) {
 738                                 rte_spinlock_unlock(&hw->lock);
 739                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 740                                          enable ? "enable" : "disable", ret);
 741                                 return ret;
 742                         }
 743                 }
 744         }
 745
 746         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 747                 /* Enable or disable VLAN stripping */
 748                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 749                     true : false;
 750
 751                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 752                 if (ret) {
 753                         rte_spinlock_unlock(&hw->lock);
 754                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 755                                  enable ? "enable" : "disable", ret);
 756                         return ret;
 757                 }
 758         }
 759
 760         rte_spinlock_unlock(&hw->lock);
 761
 762         return ret;
 763 }
 764
 765 static int
 766 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 767                              struct hns3_tx_vtag_cfg *vcfg)
 768 {
 769         struct hns3_vport_vtag_tx_cfg_cmd *req;
 770         struct hns3_cmd_desc desc;
 771         struct hns3_hw *hw = &hns->hw;
 772         uint16_t vport_id;
 773         uint8_t bitmap;
 774         int ret;
 775
 776         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 777
 778         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 779         req->def_vlan_tag1 = vcfg->default_tag1;
 780         req->def_vlan_tag2 = vcfg->default_tag2;
 781         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 782                      vcfg->accept_tag1 ? 1 : 0);
 783         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 784                      vcfg->accept_untag1 ? 1 : 0);
 785         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 786                      vcfg->accept_tag2 ? 1 : 0);
 787         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 788                      vcfg->accept_untag2 ? 1 : 0);
 789         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 790                      vcfg->insert_tag1_en ? 1 : 0);
 791         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 792                      vcfg->insert_tag2_en ? 1 : 0);
 793         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 794
 795         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 796         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 797                      vcfg->tag_shift_mode_en ? 1 : 0);
 798
 799         /*
 800          * In current version VF is not supported when PF is driven by DPDK
 801          * driver, just need to configure parameters for PF vport.
 802          */
 803         vport_id = HNS3_PF_FUNC_ID;
 804         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 805         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 806         req->vf_bitmap[req->vf_offset] = bitmap;
 807
 808         ret = hns3_cmd_send(hw, &desc, 1);
 809         if (ret)
 810                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 811
 812         return ret;
 813 }
 814
 815 static int
 816 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 817                      uint16_t pvid)
 818 {
 819         struct hns3_hw *hw = &hns->hw;
 820         struct hns3_tx_vtag_cfg txvlan_cfg;
 821         int ret;
 822
 823         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 824                 txvlan_cfg.accept_tag1 = true;
 825                 txvlan_cfg.insert_tag1_en = false;
 826                 txvlan_cfg.default_tag1 = 0;
 827         } else {
 828                 txvlan_cfg.accept_tag1 =
 829                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 830                 txvlan_cfg.insert_tag1_en = true;
 831                 txvlan_cfg.default_tag1 = pvid;
 832         }
 833
 834         txvlan_cfg.accept_untag1 = true;
 835         txvlan_cfg.accept_tag2 = true;
 836         txvlan_cfg.accept_untag2 = true;
 837         txvlan_cfg.insert_tag2_en = false;
 838         txvlan_cfg.default_tag2 = 0;
 839         txvlan_cfg.tag_shift_mode_en = true;
 840
 841         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 842         if (ret) {
 843                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 844                          ret);
 845                 return ret;
 846         }
 847
 848         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 849         return ret;
 850 }
 851
 852
 853 static void
 854 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 855 {
 856         struct hns3_user_vlan_table *vlan_entry;
 857         struct hns3_pf *pf = &hns->pf;
 858
 859         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 860                 if (vlan_entry->hd_tbl_status) {
 861                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 862                         vlan_entry->hd_tbl_status = false;
 863                 }
 864         }
 865
 866         if (is_del_list) {
 867                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 868                 while (vlan_entry) {
 869                         LIST_REMOVE(vlan_entry, next);
 870                         rte_free(vlan_entry);
 871                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 872                 }
 873         }
 874 }
 875
 876 static void
 877 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 878 {
 879         struct hns3_user_vlan_table *vlan_entry;
 880         struct hns3_pf *pf = &hns->pf;
 881
 882         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 883                 if (!vlan_entry->hd_tbl_status) {
 884                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 885                         vlan_entry->hd_tbl_status = true;
 886                 }
 887         }
 888 }
 889
 890 static void
 891 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         hns3_rm_all_vlan_table(hns, true);
 897         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 898                 ret = hns3_set_port_vlan_filter(hns,
 899                                                 hw->port_base_vlan_cfg.pvid, 0);
 900                 if (ret) {
 901                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 902                                  ret);
 903                         return;
 904                 }
 905         }
 906 }
 907
 908 static int
 909 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 910                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 911 {
 912         struct hns3_hw *hw = &hns->hw;
 913         uint16_t old_pvid;
 914         int ret;
 915
 916         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 917                 old_pvid = hw->port_base_vlan_cfg.pvid;
 918                 if (old_pvid != HNS3_INVALID_PVID) {
 919                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 920                         if (ret) {
 921                                 hns3_err(hw, "failed to remove old pvid %u, "
 922                                                 "ret = %d", old_pvid, ret);
 923                                 return ret;
 924                         }
 925                 }
 926
 927                 hns3_rm_all_vlan_table(hns, false);
 928                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 929                 if (ret) {
 930                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 931                                         new_pvid, ret);
 932                         return ret;
 933                 }
 934         } else {
 935                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 936                 if (ret) {
 937                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 938                                         new_pvid, ret);
 939                         return ret;
 940                 }
 941
 942                 hns3_add_all_vlan_table(hns);
 943         }
 944         return 0;
 945 }
 946
 947 static int
 948 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 949 {
 950         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 951         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 952         bool rx_strip_en;
 953         int ret;
 954
 955         rx_strip_en = old_cfg->rx_vlan_offload_en;
 956         if (on) {
 957                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 958                 rx_vlan_cfg.strip_tag2_en = true;
 959                 rx_vlan_cfg.strip_tag2_discard_en = true;
 960         } else {
 961                 rx_vlan_cfg.strip_tag1_en = false;
 962                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 963                 rx_vlan_cfg.strip_tag2_discard_en = false;
 964         }
 965         rx_vlan_cfg.strip_tag1_discard_en = false;
 966         rx_vlan_cfg.vlan1_vlan_prionly = false;
 967         rx_vlan_cfg.vlan2_vlan_prionly = false;
 968         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 969
 970         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 971         if (ret)
 972                 return ret;
 973
 974         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 975         return ret;
 976 }
 977
 978 static int
 979 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 980 {
 981         struct hns3_hw *hw = &hns->hw;
 982         uint16_t port_base_vlan_state;
 983         int ret, err;
 984
 985         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 986                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 987                         hns3_warn(hw, "Invalid operation! As current pvid set "
 988                                   "is %u, disable pvid %u is invalid",
 989                                   hw->port_base_vlan_cfg.pvid, pvid);
 990                 return 0;
 991         }
 992
 993         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 994                                     HNS3_PORT_BASE_VLAN_DISABLE;
 995         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 996         if (ret) {
 997                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 998                          ret);
 999                 return ret;
1000         }
1001
1002         ret = hns3_en_pvid_strip(hns, on);
1003         if (ret) {
1004                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1005                          "ret = %d", ret);
1006                 goto pvid_vlan_strip_fail;
1007         }
1008
1009         if (pvid == HNS3_INVALID_PVID)
1010                 goto out;
1011         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1012         if (ret) {
1013                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1014                          ret);
1015                 goto vlan_filter_set_fail;
1016         }
1017
1018 out:
1019         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1020         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1021         return ret;
1022
1023 vlan_filter_set_fail:
1024         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1025                                         HNS3_PORT_BASE_VLAN_ENABLE);
1026         if (err)
1027                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1028
1029 pvid_vlan_strip_fail:
1030         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1031                                         hw->port_base_vlan_cfg.pvid);
1032         if (err)
1033                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1034
1035         return ret;
1036 }
1037
1038 static int
1039 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1040 {
1041         struct hns3_adapter *hns = dev->data->dev_private;
1042         struct hns3_hw *hw = &hns->hw;
1043         bool pvid_en_state_change;
1044         uint16_t pvid_state;
1045         int ret;
1046
1047         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1048                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1049                          RTE_ETHER_MAX_VLAN_ID);
1050                 return -EINVAL;
1051         }
1052
1053         /*
1054          * If PVID configuration state change, should refresh the PVID
1055          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1056          */
1057         pvid_state = hw->port_base_vlan_cfg.state;
1058         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1059             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1060                 pvid_en_state_change = false;
1061         else
1062                 pvid_en_state_change = true;
1063
1064         rte_spinlock_lock(&hw->lock);
1065         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1066         rte_spinlock_unlock(&hw->lock);
1067         if (ret)
1068                 return ret;
1069         /*
1070          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1071          * need be processed by PMD driver.
1072          */
1073         if (pvid_en_state_change &&
1074             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1075                 hns3_update_all_queues_pvid_proc_en(hw);
1076
1077         return 0;
1078 }
1079
1080 static int
1081 hns3_default_vlan_config(struct hns3_adapter *hns)
1082 {
1083         struct hns3_hw *hw = &hns->hw;
1084         int ret;
1085
1086         /*
1087          * When vlan filter is enabled, hardware regards packets without vlan
1088          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1089          * table, packets without vlan won't be received. So, add vlan 0 as
1090          * the default vlan.
1091          */
1092         ret = hns3_vlan_filter_configure(hns, 0, 1);
1093         if (ret)
1094                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1095         return ret;
1096 }
1097
1098 static int
1099 hns3_init_vlan_config(struct hns3_adapter *hns)
1100 {
1101         struct hns3_hw *hw = &hns->hw;
1102         int ret;
1103
1104         /*
1105          * This function can be called in the initialization and reset process,
1106          * when in reset process, it means that hardware had been reseted
1107          * successfully and we need to restore the hardware configuration to
1108          * ensure that the hardware configuration remains unchanged before and
1109          * after reset.
1110          */
1111         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1112                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1113                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1114         }
1115
1116         ret = hns3_vlan_filter_init(hns);
1117         if (ret) {
1118                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1119                 return ret;
1120         }
1121
1122         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1123                                        RTE_ETHER_TYPE_VLAN);
1124         if (ret) {
1125                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1126                 return ret;
1127         }
1128
1129         /*
1130          * When in the reinit dev stage of the reset process, the following
1131          * vlan-related configurations may differ from those at initialization,
1132          * we will restore configurations to hardware in hns3_restore_vlan_table
1133          * and hns3_restore_vlan_conf later.
1134          */
1135         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1136                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1137                 if (ret) {
1138                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1139                         return ret;
1140                 }
1141
1142                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1143                 if (ret) {
1144                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1145                                  ret);
1146                         return ret;
1147                 }
1148         }
1149
1150         return hns3_default_vlan_config(hns);
1151 }
1152
1153 static int
1154 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1155 {
1156         struct hns3_pf *pf = &hns->pf;
1157         struct hns3_hw *hw = &hns->hw;
1158         uint64_t offloads;
1159         bool enable;
1160         int ret;
1161
1162         if (!hw->data->promiscuous) {
1163                 /* restore vlan filter states */
1164                 offloads = hw->data->dev_conf.rxmode.offloads;
1165                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1166                 ret = hns3_enable_vlan_filter(hns, enable);
1167                 if (ret) {
1168                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1169                                  "ret = %d", ret);
1170                         return ret;
1171                 }
1172         }
1173
1174         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1175         if (ret) {
1176                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1177                 return ret;
1178         }
1179
1180         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1181         if (ret)
1182                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1183
1184         return ret;
1185 }
1186
1187 static int
1188 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1189 {
1190         struct hns3_adapter *hns = dev->data->dev_private;
1191         struct rte_eth_dev_data *data = dev->data;
1192         struct rte_eth_txmode *txmode;
1193         struct hns3_hw *hw = &hns->hw;
1194         int mask;
1195         int ret;
1196
1197         txmode = &data->dev_conf.txmode;
1198         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1199                 hns3_warn(hw,
1200                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1201                           "configuration is not supported! Ignore these two "
1202                           "parameters: hw_vlan_reject_tagged(%u), "
1203                           "hw_vlan_reject_untagged(%u)",
1204                           txmode->hw_vlan_reject_tagged,
1205                           txmode->hw_vlan_reject_untagged);
1206
1207         /* Apply vlan offload setting */
1208         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1209         ret = hns3_vlan_offload_set(dev, mask);
1210         if (ret) {
1211                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1212                          ret);
1213                 return ret;
1214         }
1215
1216         /*
1217          * If pvid config is not set in rte_eth_conf, driver needn't to set
1218          * VLAN pvid related configuration to hardware.
1219          */
1220         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1221                 return 0;
1222
1223         /* Apply pvid setting */
1224         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1225                                  txmode->hw_vlan_insert_pvid);
1226         if (ret)
1227                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1228                          txmode->pvid, ret);
1229
1230         return ret;
1231 }
1232
1233 static int
1234 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1235                 unsigned int tso_mss_max)
1236 {
1237         struct hns3_cfg_tso_status_cmd *req;
1238         struct hns3_cmd_desc desc;
1239         uint16_t tso_mss;
1240
1241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1242
1243         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1244
1245         tso_mss = 0;
1246         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1247                        tso_mss_min);
1248         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1249
1250         tso_mss = 0;
1251         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1252                        tso_mss_max);
1253         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1254
1255         return hns3_cmd_send(hw, &desc, 1);
1256 }
1257
1258 static int
1259 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1260                    uint16_t *allocated_size, bool is_alloc)
1261 {
1262         struct hns3_umv_spc_alc_cmd *req;
1263         struct hns3_cmd_desc desc;
1264         int ret;
1265
1266         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1267         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1268         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1269         req->space_size = rte_cpu_to_le_32(space_size);
1270
1271         ret = hns3_cmd_send(hw, &desc, 1);
1272         if (ret) {
1273                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1274                              is_alloc ? "allocate" : "free", ret);
1275                 return ret;
1276         }
1277
1278         if (is_alloc && allocated_size)
1279                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 hns3_init_umv_space(struct hns3_hw *hw)
1286 {
1287         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1288         struct hns3_pf *pf = &hns->pf;
1289         uint16_t allocated_size = 0;
1290         int ret;
1291
1292         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1293                                  true);
1294         if (ret)
1295                 return ret;
1296
1297         if (allocated_size < pf->wanted_umv_size)
1298                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1299                              pf->wanted_umv_size, allocated_size);
1300
1301         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1302                                                 pf->wanted_umv_size;
1303         pf->used_umv_size = 0;
1304         return 0;
1305 }
1306
1307 static int
1308 hns3_uninit_umv_space(struct hns3_hw *hw)
1309 {
1310         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1311         struct hns3_pf *pf = &hns->pf;
1312         int ret;
1313
1314         if (pf->max_umv_size == 0)
1315                 return 0;
1316
1317         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1318         if (ret)
1319                 return ret;
1320
1321         pf->max_umv_size = 0;
1322
1323         return 0;
1324 }
1325
1326 static bool
1327 hns3_is_umv_space_full(struct hns3_hw *hw)
1328 {
1329         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1330         struct hns3_pf *pf = &hns->pf;
1331         bool is_full;
1332
1333         is_full = (pf->used_umv_size >= pf->max_umv_size);
1334
1335         return is_full;
1336 }
1337
1338 static void
1339 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1340 {
1341         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1342         struct hns3_pf *pf = &hns->pf;
1343
1344         if (is_free) {
1345                 if (pf->used_umv_size > 0)
1346                         pf->used_umv_size--;
1347         } else
1348                 pf->used_umv_size++;
1349 }
1350
1351 static void
1352 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1353                       const uint8_t *addr, bool is_mc)
1354 {
1355         const unsigned char *mac_addr = addr;
1356         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1357                             ((uint32_t)mac_addr[2] << 16) |
1358                             ((uint32_t)mac_addr[1] << 8) |
1359                             (uint32_t)mac_addr[0];
1360         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1361
1362         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1363         if (is_mc) {
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1366                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1367         }
1368
1369         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1370         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1371 }
1372
1373 static int
1374 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1375                              uint8_t resp_code,
1376                              enum hns3_mac_vlan_tbl_opcode op)
1377 {
1378         if (cmdq_resp) {
1379                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1380                          cmdq_resp);
1381                 return -EIO;
1382         }
1383
1384         if (op == HNS3_MAC_VLAN_ADD) {
1385                 if (resp_code == 0 || resp_code == 1) {
1386                         return 0;
1387                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1388                         hns3_err(hw, "add mac addr failed for uc_overflow");
1389                         return -ENOSPC;
1390                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1391                         hns3_err(hw, "add mac addr failed for mc_overflow");
1392                         return -ENOSPC;
1393                 }
1394
1395                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1396                          resp_code);
1397                 return -EIO;
1398         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1399                 if (resp_code == 0) {
1400                         return 0;
1401                 } else if (resp_code == 1) {
1402                         hns3_dbg(hw, "remove mac addr failed for miss");
1403                         return -ENOENT;
1404                 }
1405
1406                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1407                          resp_code);
1408                 return -EIO;
1409         } else if (op == HNS3_MAC_VLAN_LKUP) {
1410                 if (resp_code == 0) {
1411                         return 0;
1412                 } else if (resp_code == 1) {
1413                         hns3_dbg(hw, "lookup mac addr failed for miss");
1414                         return -ENOENT;
1415                 }
1416
1417                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1418                          resp_code);
1419                 return -EIO;
1420         }
1421
1422         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1423                  op);
1424
1425         return -EINVAL;
1426 }
1427
1428 static int
1429 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1430                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1431                          struct hns3_cmd_desc *desc, bool is_mc)
1432 {
1433         uint8_t resp_code;
1434         uint16_t retval;
1435         int ret;
1436
1437         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1438         if (is_mc) {
1439                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1440                 memcpy(desc[0].data, req,
1441                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1442                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1443                                           true);
1444                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1445                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1446                                           true);
1447                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1448         } else {
1449                 memcpy(desc[0].data, req,
1450                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451                 ret = hns3_cmd_send(hw, desc, 1);
1452         }
1453         if (ret) {
1454                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1455                          ret);
1456                 return ret;
1457         }
1458         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1459         retval = rte_le_to_cpu_16(desc[0].retval);
1460
1461         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462                                             HNS3_MAC_VLAN_LKUP);
1463 }
1464
1465 static int
1466 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1467                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1468                       struct hns3_cmd_desc *mc_desc)
1469 {
1470         uint8_t resp_code;
1471         uint16_t retval;
1472         int cfg_status;
1473         int ret;
1474
1475         if (mc_desc == NULL) {
1476                 struct hns3_cmd_desc desc;
1477
1478                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1479                 memcpy(desc.data, req,
1480                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1481                 ret = hns3_cmd_send(hw, &desc, 1);
1482                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1483                 retval = rte_le_to_cpu_16(desc.retval);
1484
1485                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1486                                                           HNS3_MAC_VLAN_ADD);
1487         } else {
1488                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1489                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1491                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1492                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1493                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494                 memcpy(mc_desc[0].data, req,
1495                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1496                 mc_desc[0].retval = 0;
1497                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1498                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1499                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1500
1501                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1502                                                           HNS3_MAC_VLAN_ADD);
1503         }
1504
1505         if (ret) {
1506                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1507                 return ret;
1508         }
1509
1510         return cfg_status;
1511 }
1512
1513 static int
1514 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1515                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1516 {
1517         struct hns3_cmd_desc desc;
1518         uint8_t resp_code;
1519         uint16_t retval;
1520         int ret;
1521
1522         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1523
1524         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1525
1526         ret = hns3_cmd_send(hw, &desc, 1);
1527         if (ret) {
1528                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1529                 return ret;
1530         }
1531         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1532         retval = rte_le_to_cpu_16(desc.retval);
1533
1534         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1535                                             HNS3_MAC_VLAN_REMOVE);
1536 }
1537
1538 static int
1539 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1540 {
1541         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1542         struct hns3_mac_vlan_tbl_entry_cmd req;
1543         struct hns3_pf *pf = &hns->pf;
1544         struct hns3_cmd_desc desc[3];
1545         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1546         uint16_t egress_port = 0;
1547         uint8_t vf_id;
1548         int ret;
1549
1550         /* check if mac addr is valid */
1551         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1552                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                       mac_addr);
1554                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1555                          mac_str);
1556                 return -EINVAL;
1557         }
1558
1559         memset(&req, 0, sizeof(req));
1560
1561         /*
1562          * In current version VF is not supported when PF is driven by DPDK
1563          * driver, just need to configure parameters for PF vport.
1564          */
1565         vf_id = HNS3_PF_FUNC_ID;
1566         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1567                        HNS3_MAC_EPORT_VFID_S, vf_id);
1568
1569         req.egress_port = rte_cpu_to_le_16(egress_port);
1570
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572
1573         /*
1574          * Lookup the mac address in the mac_vlan table, and add
1575          * it if the entry is inexistent. Repeated unicast entry
1576          * is not allowed in the mac vlan table.
1577          */
1578         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1579         if (ret == -ENOENT) {
1580                 if (!hns3_is_umv_space_full(hw)) {
1581                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1582                         if (!ret)
1583                                 hns3_update_umv_space(hw, false);
1584                         return ret;
1585                 }
1586
1587                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1588
1589                 return -ENOSPC;
1590         }
1591
1592         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1593
1594         /* check if we just hit the duplicate */
1595         if (ret == 0) {
1596                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1597                 return 0;
1598         }
1599
1600         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1601                  mac_str);
1602
1603         return ret;
1604 }
1605
1606 static int
1607 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1608 {
1609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610         struct rte_ether_addr *addr;
1611         int ret;
1612         int i;
1613
1614         for (i = 0; i < hw->mc_addrs_num; i++) {
1615                 addr = &hw->mc_addrs[i];
1616                 /* Check if there are duplicate addresses */
1617                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1618                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1619                                               addr);
1620                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1621                                  "(%s) is added by the set_mc_mac_addr_list "
1622                                  "API", mac_str);
1623                         return -EINVAL;
1624                 }
1625         }
1626
1627         ret = hns3_add_mc_addr(hw, mac_addr);
1628         if (ret) {
1629                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                       mac_addr);
1631                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1632                          mac_str, ret);
1633         }
1634         return ret;
1635 }
1636
1637 static int
1638 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1639 {
1640         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641         int ret;
1642
1643         ret = hns3_remove_mc_addr(hw, mac_addr);
1644         if (ret) {
1645                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1646                                       mac_addr);
1647                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1648                          mac_str, ret);
1649         }
1650         return ret;
1651 }
1652
1653 static int
1654 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1655                   uint32_t idx, __rte_unused uint32_t pool)
1656 {
1657         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         /*
1664          * In hns3 network engine adding UC and MC mac address with different
1665          * commands with firmware. We need to determine whether the input
1666          * address is a UC or a MC address to call different commands.
1667          * By the way, it is recommended calling the API function named
1668          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1669          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1670          * may affect the specifications of UC mac addresses.
1671          */
1672         if (rte_is_multicast_ether_addr(mac_addr))
1673                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1674         else
1675                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1676
1677         if (ret) {
1678                 rte_spinlock_unlock(&hw->lock);
1679                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                       mac_addr);
1681                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1682                          ret);
1683                 return ret;
1684         }
1685
1686         if (idx == 0)
1687                 hw->mac.default_addr_setted = true;
1688         rte_spinlock_unlock(&hw->lock);
1689
1690         return ret;
1691 }
1692
1693 static int
1694 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1695 {
1696         struct hns3_mac_vlan_tbl_entry_cmd req;
1697         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698         int ret;
1699
1700         /* check if mac addr is valid */
1701         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1702                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1703                                       mac_addr);
1704                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1705                          mac_str);
1706                 return -EINVAL;
1707         }
1708
1709         memset(&req, 0, sizeof(req));
1710         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1711         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1712         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1713         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1714                 return 0;
1715         else if (ret == 0)
1716                 hns3_update_umv_space(hw, true);
1717
1718         return ret;
1719 }
1720
1721 static void
1722 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1723 {
1724         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         /* index will be checked by upper level rte interface */
1726         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1727         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728         int ret;
1729
1730         rte_spinlock_lock(&hw->lock);
1731
1732         if (rte_is_multicast_ether_addr(mac_addr))
1733                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1734         else
1735                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1736         rte_spinlock_unlock(&hw->lock);
1737         if (ret) {
1738                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1739                                       mac_addr);
1740                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1741                          ret);
1742         }
1743 }
1744
1745 static int
1746 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1747                           struct rte_ether_addr *mac_addr)
1748 {
1749         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         struct rte_ether_addr *oaddr;
1751         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752         bool default_addr_setted;
1753         bool rm_succes = false;
1754         int ret, ret_val;
1755
1756         /*
1757          * It has been guaranteed that input parameter named mac_addr is valid
1758          * address in the rte layer of DPDK framework.
1759          */
1760         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1761         default_addr_setted = hw->mac.default_addr_setted;
1762         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1763                 return 0;
1764
1765         rte_spinlock_lock(&hw->lock);
1766         if (default_addr_setted) {
1767                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1768                 if (ret) {
1769                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1770                                               oaddr);
1771                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1772                                   mac_str, ret);
1773                         rm_succes = false;
1774                 } else
1775                         rm_succes = true;
1776         }
1777
1778         ret = hns3_add_uc_addr_common(hw, mac_addr);
1779         if (ret) {
1780                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                       mac_addr);
1782                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1783                 goto err_add_uc_addr;
1784         }
1785
1786         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1787         if (ret) {
1788                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1789                 goto err_pause_addr_cfg;
1790         }
1791
1792         rte_ether_addr_copy(mac_addr,
1793                             (struct rte_ether_addr *)hw->mac.mac_addr);
1794         hw->mac.default_addr_setted = true;
1795         rte_spinlock_unlock(&hw->lock);
1796
1797         return 0;
1798
1799 err_pause_addr_cfg:
1800         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1801         if (ret_val) {
1802                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803                                       mac_addr);
1804                 hns3_warn(hw,
1805                           "Failed to roll back to del setted mac addr(%s): %d",
1806                           mac_str, ret_val);
1807         }
1808
1809 err_add_uc_addr:
1810         if (rm_succes) {
1811                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1812                 if (ret_val) {
1813                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                               oaddr);
1815                         hns3_warn(hw,
1816                                   "Failed to restore old uc mac addr(%s): %d",
1817                                   mac_str, ret_val);
1818                         hw->mac.default_addr_setted = false;
1819                 }
1820         }
1821         rte_spinlock_unlock(&hw->lock);
1822
1823         return ret;
1824 }
1825
1826 static int
1827 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1828 {
1829         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1830         struct hns3_hw *hw = &hns->hw;
1831         struct rte_ether_addr *addr;
1832         int err = 0;
1833         int ret;
1834         int i;
1835
1836         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1837                 addr = &hw->data->mac_addrs[i];
1838                 if (rte_is_zero_ether_addr(addr))
1839                         continue;
1840                 if (rte_is_multicast_ether_addr(addr))
1841                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1842                               hns3_add_mc_addr(hw, addr);
1843                 else
1844                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1845                               hns3_add_uc_addr_common(hw, addr);
1846
1847                 if (ret) {
1848                         err = ret;
1849                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1850                                               addr);
1851                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1852                                  "ret = %d.", del ? "remove" : "restore",
1853                                  mac_str, i, ret);
1854                 }
1855         }
1856         return err;
1857 }
1858
1859 static void
1860 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1861 {
1862 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1863         uint8_t word_num;
1864         uint8_t bit_num;
1865
1866         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1867                 word_num = vfid / 32;
1868                 bit_num = vfid % 32;
1869                 if (clr)
1870                         desc[1].data[word_num] &=
1871                             rte_cpu_to_le_32(~(1UL << bit_num));
1872                 else
1873                         desc[1].data[word_num] |=
1874                             rte_cpu_to_le_32(1UL << bit_num);
1875         } else {
1876                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1877                 bit_num = vfid % 32;
1878                 if (clr)
1879                         desc[2].data[word_num] &=
1880                             rte_cpu_to_le_32(~(1UL << bit_num));
1881                 else
1882                         desc[2].data[word_num] |=
1883                             rte_cpu_to_le_32(1UL << bit_num);
1884         }
1885 }
1886
1887 static int
1888 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1889 {
1890         struct hns3_mac_vlan_tbl_entry_cmd req;
1891         struct hns3_cmd_desc desc[3];
1892         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1893         uint8_t vf_id;
1894         int ret;
1895
1896         /* Check if mac addr is valid */
1897         if (!rte_is_multicast_ether_addr(mac_addr)) {
1898                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1899                                       mac_addr);
1900                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1901                          mac_str);
1902                 return -EINVAL;
1903         }
1904
1905         memset(&req, 0, sizeof(req));
1906         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1907         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1908         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1909         if (ret) {
1910                 /* This mac addr do not exist, add new entry for it */
1911                 memset(desc[0].data, 0, sizeof(desc[0].data));
1912                 memset(desc[1].data, 0, sizeof(desc[0].data));
1913                 memset(desc[2].data, 0, sizeof(desc[0].data));
1914         }
1915
1916         /*
1917          * In current version VF is not supported when PF is driven by DPDK
1918          * driver, just need to configure parameters for PF vport.
1919          */
1920         vf_id = HNS3_PF_FUNC_ID;
1921         hns3_update_desc_vfid(desc, vf_id, false);
1922         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1923         if (ret) {
1924                 if (ret == -ENOSPC)
1925                         hns3_err(hw, "mc mac vlan table is full");
1926                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1927                                       mac_addr);
1928                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1929         }
1930
1931         return ret;
1932 }
1933
1934 static int
1935 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1936 {
1937         struct hns3_mac_vlan_tbl_entry_cmd req;
1938         struct hns3_cmd_desc desc[3];
1939         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1940         uint8_t vf_id;
1941         int ret;
1942
1943         /* Check if mac addr is valid */
1944         if (!rte_is_multicast_ether_addr(mac_addr)) {
1945                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1946                                       mac_addr);
1947                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1948                          mac_str);
1949                 return -EINVAL;
1950         }
1951
1952         memset(&req, 0, sizeof(req));
1953         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1954         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1955         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1956         if (ret == 0) {
1957                 /*
1958                  * This mac addr exist, remove this handle's VFID for it.
1959                  * In current version VF is not supported when PF is driven by
1960                  * DPDK driver, just need to configure parameters for PF vport.
1961                  */
1962                 vf_id = HNS3_PF_FUNC_ID;
1963                 hns3_update_desc_vfid(desc, vf_id, true);
1964
1965                 /* All the vfid is zero, so need to delete this entry */
1966                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1967         } else if (ret == -ENOENT) {
1968                 /* This mac addr doesn't exist. */
1969                 return 0;
1970         }
1971
1972         if (ret) {
1973                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1974                                       mac_addr);
1975                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1976         }
1977
1978         return ret;
1979 }
1980
1981 static int
1982 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1983                            struct rte_ether_addr *mc_addr_set,
1984                            uint32_t nb_mc_addr)
1985 {
1986         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1987         struct rte_ether_addr *addr;
1988         uint32_t i;
1989         uint32_t j;
1990
1991         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1992                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1993                          "invalid. valid range: 0~%d",
1994                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1995                 return -EINVAL;
1996         }
1997
1998         /* Check if input mac addresses are valid */
1999         for (i = 0; i < nb_mc_addr; i++) {
2000                 addr = &mc_addr_set[i];
2001                 if (!rte_is_multicast_ether_addr(addr)) {
2002                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2003                                               addr);
2004                         hns3_err(hw,
2005                                  "failed to set mc mac addr, addr(%s) invalid.",
2006                                  mac_str);
2007                         return -EINVAL;
2008                 }
2009
2010                 /* Check if there are duplicate addresses */
2011                 for (j = i + 1; j < nb_mc_addr; j++) {
2012                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2013                                 hns3_ether_format_addr(mac_str,
2014                                                       RTE_ETHER_ADDR_FMT_SIZE,
2015                                                       addr);
2016                                 hns3_err(hw, "failed to set mc mac addr, "
2017                                          "addrs invalid. two same addrs(%s).",
2018                                          mac_str);
2019                                 return -EINVAL;
2020                         }
2021                 }
2022
2023                 /*
2024                  * Check if there are duplicate addresses between mac_addrs
2025                  * and mc_addr_set
2026                  */
2027                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2028                         if (rte_is_same_ether_addr(addr,
2029                                                    &hw->data->mac_addrs[j])) {
2030                                 hns3_ether_format_addr(mac_str,
2031                                                       RTE_ETHER_ADDR_FMT_SIZE,
2032                                                       addr);
2033                                 hns3_err(hw, "failed to set mc mac addr, "
2034                                          "addrs invalid. addrs(%s) has already "
2035                                          "configured in mac_addr add API",
2036                                          mac_str);
2037                                 return -EINVAL;
2038                         }
2039                 }
2040         }
2041
2042         return 0;
2043 }
2044
2045 static void
2046 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2047                            struct rte_ether_addr *mc_addr_set,
2048                            int mc_addr_num,
2049                            struct rte_ether_addr *reserved_addr_list,
2050                            int *reserved_addr_num,
2051                            struct rte_ether_addr *add_addr_list,
2052                            int *add_addr_num,
2053                            struct rte_ether_addr *rm_addr_list,
2054                            int *rm_addr_num)
2055 {
2056         struct rte_ether_addr *addr;
2057         int current_addr_num;
2058         int reserved_num = 0;
2059         int add_num = 0;
2060         int rm_num = 0;
2061         int num;
2062         int i;
2063         int j;
2064         bool same_addr;
2065
2066         /* Calculate the mc mac address list that should be removed */
2067         current_addr_num = hw->mc_addrs_num;
2068         for (i = 0; i < current_addr_num; i++) {
2069                 addr = &hw->mc_addrs[i];
2070                 same_addr = false;
2071                 for (j = 0; j < mc_addr_num; j++) {
2072                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2073                                 same_addr = true;
2074                                 break;
2075                         }
2076                 }
2077
2078                 if (!same_addr) {
2079                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2080                         rm_num++;
2081                 } else {
2082                         rte_ether_addr_copy(addr,
2083                                             &reserved_addr_list[reserved_num]);
2084                         reserved_num++;
2085                 }
2086         }
2087
2088         /* Calculate the mc mac address list that should be added */
2089         for (i = 0; i < mc_addr_num; i++) {
2090                 addr = &mc_addr_set[i];
2091                 same_addr = false;
2092                 for (j = 0; j < current_addr_num; j++) {
2093                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2094                                 same_addr = true;
2095                                 break;
2096                         }
2097                 }
2098
2099                 if (!same_addr) {
2100                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2101                         add_num++;
2102                 }
2103         }
2104
2105         /* Reorder the mc mac address list maintained by driver */
2106         for (i = 0; i < reserved_num; i++)
2107                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2108
2109         for (i = 0; i < rm_num; i++) {
2110                 num = reserved_num + i;
2111                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2112         }
2113
2114         *reserved_addr_num = reserved_num;
2115         *add_addr_num = add_num;
2116         *rm_addr_num = rm_num;
2117 }
2118
2119 static int
2120 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2121                           struct rte_ether_addr *mc_addr_set,
2122                           uint32_t nb_mc_addr)
2123 {
2124         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2126         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr *addr;
2129         int reserved_addr_num;
2130         int add_addr_num;
2131         int rm_addr_num;
2132         int mc_addr_num;
2133         int num;
2134         int ret;
2135         int i;
2136
2137         /* Check if input parameters are valid */
2138         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2139         if (ret)
2140                 return ret;
2141
2142         rte_spinlock_lock(&hw->lock);
2143
2144         /*
2145          * Calculate the mc mac address lists those should be removed and be
2146          * added, Reorder the mc mac address list maintained by driver.
2147          */
2148         mc_addr_num = (int)nb_mc_addr;
2149         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2150                                    reserved_addr_list, &reserved_addr_num,
2151                                    add_addr_list, &add_addr_num,
2152                                    rm_addr_list, &rm_addr_num);
2153
2154         /* Remove mc mac addresses */
2155         for (i = 0; i < rm_addr_num; i++) {
2156                 num = rm_addr_num - i - 1;
2157                 addr = &rm_addr_list[num];
2158                 ret = hns3_remove_mc_addr(hw, addr);
2159                 if (ret) {
2160                         rte_spinlock_unlock(&hw->lock);
2161                         return ret;
2162                 }
2163                 hw->mc_addrs_num--;
2164         }
2165
2166         /* Add mc mac addresses */
2167         for (i = 0; i < add_addr_num; i++) {
2168                 addr = &add_addr_list[i];
2169                 ret = hns3_add_mc_addr(hw, addr);
2170                 if (ret) {
2171                         rte_spinlock_unlock(&hw->lock);
2172                         return ret;
2173                 }
2174
2175                 num = reserved_addr_num + i;
2176                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2177                 hw->mc_addrs_num++;
2178         }
2179         rte_spinlock_unlock(&hw->lock);
2180
2181         return 0;
2182 }
2183
2184 static int
2185 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2186 {
2187         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2188         struct hns3_hw *hw = &hns->hw;
2189         struct rte_ether_addr *addr;
2190         int err = 0;
2191         int ret;
2192         int i;
2193
2194         for (i = 0; i < hw->mc_addrs_num; i++) {
2195                 addr = &hw->mc_addrs[i];
2196                 if (!rte_is_multicast_ether_addr(addr))
2197                         continue;
2198                 if (del)
2199                         ret = hns3_remove_mc_addr(hw, addr);
2200                 else
2201                         ret = hns3_add_mc_addr(hw, addr);
2202                 if (ret) {
2203                         err = ret;
2204                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2205                                               addr);
2206                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2207                                  del ? "Remove" : "Restore", mac_str, ret);
2208                 }
2209         }
2210         return err;
2211 }
2212
2213 static int
2214 hns3_check_mq_mode(struct rte_eth_dev *dev)
2215 {
2216         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2217         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2221         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2222         uint8_t num_tc;
2223         int max_tc = 0;
2224         int i;
2225
2226         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2227             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2228              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2229                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2230                          rx_mq_mode, tx_mq_mode);
2231                 return -EOPNOTSUPP;
2232         }
2233
2234         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2235         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2236         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2237                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2238                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2239                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2240                         return -EINVAL;
2241                 }
2242
2243                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2244                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2245                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2246                                  "nb_tcs(%d) != %d or %d in rx direction.",
2247                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2252                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2253                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2254                         return -EINVAL;
2255                 }
2256
2257                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2258                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2259                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2260                                          "is not equal to one in tx direction.",
2261                                          i, dcb_rx_conf->dcb_tc[i]);
2262                                 return -EINVAL;
2263                         }
2264                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2265                                 max_tc = dcb_rx_conf->dcb_tc[i];
2266                 }
2267
2268                 num_tc = max_tc + 1;
2269                 if (num_tc > dcb_rx_conf->nb_tcs) {
2270                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2271                                  num_tc, dcb_rx_conf->nb_tcs);
2272                         return -EINVAL;
2273                 }
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int
2280 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2281 {
2282         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283
2284         if (!hns3_dev_dcb_supported(hw)) {
2285                 hns3_err(hw, "this port does not support dcb configurations.");
2286                 return -EOPNOTSUPP;
2287         }
2288
2289         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2290                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2291                 return -EOPNOTSUPP;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int
2298 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2299                            enum hns3_ring_type queue_type, uint16_t queue_id)
2300 {
2301         struct hns3_cmd_desc desc;
2302         struct hns3_ctrl_vector_chain_cmd *req =
2303                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2304         enum hns3_opcode_type op;
2305         uint16_t tqp_type_and_id = 0;
2306         uint16_t type;
2307         uint16_t gl;
2308         int ret;
2309
2310         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2311         hns3_cmd_setup_basic_desc(&desc, op, false);
2312         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2313                                               HNS3_TQP_INT_ID_L_S);
2314         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2315                                               HNS3_TQP_INT_ID_H_S);
2316
2317         if (queue_type == HNS3_RING_TYPE_RX)
2318                 gl = HNS3_RING_GL_RX;
2319         else
2320                 gl = HNS3_RING_GL_TX;
2321
2322         type = queue_type;
2323
2324         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2325                        type);
2326         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2327         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2328                        gl);
2329         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2330         req->int_cause_num = 1;
2331         ret = hns3_cmd_send(hw, &desc, 1);
2332         if (ret) {
2333                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2334                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2335                 return ret;
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int
2342 hns3_init_ring_with_vector(struct hns3_hw *hw)
2343 {
2344         uint16_t vec;
2345         int ret;
2346         int i;
2347
2348         /*
2349          * In hns3 network engine, vector 0 is always the misc interrupt of this
2350          * function, vector 1~N can be used respectively for the queues of the
2351          * function. Tx and Rx queues with the same number share the interrupt
2352          * vector. In the initialization clearing the all hardware mapping
2353          * relationship configurations between queues and interrupt vectors is
2354          * needed, so some error caused by the residual configurations, such as
2355          * the unexpected Tx interrupt, can be avoid.
2356          */
2357         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2358         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2359                 vec = vec - 1; /* the last interrupt is reserved */
2360         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2361         for (i = 0; i < hw->intr_tqps_num; i++) {
2362                 /*
2363                  * Set gap limiter/rate limiter/quanity limiter algorithm
2364                  * configuration for interrupt coalesce of queue's interrupt.
2365                  */
2366                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2367                                        HNS3_TQP_INTR_GL_DEFAULT);
2368                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2369                                        HNS3_TQP_INTR_GL_DEFAULT);
2370                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2371                 /*
2372                  * QL(quantity limiter) is not used currently, just set 0 to
2373                  * close it.
2374                  */
2375                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2376
2377                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2378                                                  HNS3_RING_TYPE_TX, i);
2379                 if (ret) {
2380                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2381                                           "vector: %u, ret=%d", i, vec, ret);
2382                         return ret;
2383                 }
2384
2385                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2386                                                  HNS3_RING_TYPE_RX, i);
2387                 if (ret) {
2388                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2389                                           "vector: %u, ret=%d", i, vec, ret);
2390                         return ret;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static int
2398 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2399 {
2400         struct hns3_adapter *hns = dev->data->dev_private;
2401         struct hns3_hw *hw = &hns->hw;
2402         uint32_t max_rx_pkt_len;
2403         uint16_t mtu;
2404         int ret;
2405
2406         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2407                 return 0;
2408
2409         /*
2410          * If jumbo frames are enabled, MTU needs to be refreshed
2411          * according to the maximum RX packet length.
2412          */
2413         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2414         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2415             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2416                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2417                          "and no more than %u when jumbo frame enabled.",
2418                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2419                          (uint16_t)HNS3_MAX_FRAME_LEN);
2420                 return -EINVAL;
2421         }
2422
2423         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2424         ret = hns3_dev_mtu_set(dev, mtu);
2425         if (ret)
2426                 return ret;
2427         dev->data->mtu = mtu;
2428
2429         return 0;
2430 }
2431
2432 static int
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2434 {
2435         int ret;
2436
2437         /*
2438          * Some hardware doesn't support auto-negotiation, but users may not
2439          * configure link_speeds (default 0), which means auto-negotiation.
2440          * In this case, a warning message need to be printed, instead of
2441          * an error.
2442          */
2443         if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2444             hw->mac.support_autoneg == 0) {
2445                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2446                 return 0;
2447         }
2448
2449         if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2450                 ret = hns3_check_port_speed(hw, link_speeds);
2451                 if (ret)
2452                         return ret;
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 hns3_check_dev_conf(struct rte_eth_dev *dev)
2460 {
2461         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct rte_eth_conf *conf = &dev->data->dev_conf;
2463         int ret;
2464
2465         ret = hns3_check_mq_mode(dev);
2466         if (ret)
2467                 return ret;
2468
2469         return hns3_check_link_speed(hw, conf->link_speeds);
2470 }
2471
2472 static int
2473 hns3_dev_configure(struct rte_eth_dev *dev)
2474 {
2475         struct hns3_adapter *hns = dev->data->dev_private;
2476         struct rte_eth_conf *conf = &dev->data->dev_conf;
2477         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2478         struct hns3_hw *hw = &hns->hw;
2479         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2480         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2481         struct rte_eth_rss_conf rss_conf;
2482         bool gro_en;
2483         int ret;
2484
2485         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2486
2487         /*
2488          * Some versions of hardware network engine does not support
2489          * individually enable/disable/reset the Tx or Rx queue. These devices
2490          * must enable/disable/reset Tx and Rx queues at the same time. When the
2491          * numbers of Tx queues allocated by upper applications are not equal to
2492          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2493          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2494          * work as usual. But these fake queues are imperceptible, and can not
2495          * be used by upper applications.
2496          */
2497         if (!hns3_dev_indep_txrx_supported(hw)) {
2498                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2499                 if (ret) {
2500                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2501                                  ret);
2502                         return ret;
2503                 }
2504         }
2505
2506         hw->adapter_state = HNS3_NIC_CONFIGURING;
2507         ret = hns3_check_dev_conf(dev);
2508         if (ret)
2509                 goto cfg_err;
2510
2511         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2512                 ret = hns3_check_dcb_cfg(dev);
2513                 if (ret)
2514                         goto cfg_err;
2515         }
2516
2517         /* When RSS is not configured, redirect the packet queue 0 */
2518         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2519                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2520                 rss_conf = conf->rx_adv_conf.rss_conf;
2521                 hw->rss_dis_flag = false;
2522                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2523                 if (ret)
2524                         goto cfg_err;
2525         }
2526
2527         ret = hns3_refresh_mtu(dev, conf);
2528         if (ret)
2529                 goto cfg_err;
2530
2531         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2532         if (ret)
2533                 goto cfg_err;
2534
2535         ret = hns3_dev_configure_vlan(dev);
2536         if (ret)
2537                 goto cfg_err;
2538
2539         /* config hardware GRO */
2540         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2541         ret = hns3_config_gro(hw, gro_en);
2542         if (ret)
2543                 goto cfg_err;
2544
2545         hns3_init_rx_ptype_tble(dev);
2546         hw->adapter_state = HNS3_NIC_CONFIGURED;
2547
2548         return 0;
2549
2550 cfg_err:
2551         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2552         hw->adapter_state = HNS3_NIC_INITIALIZED;
2553
2554         return ret;
2555 }
2556
2557 static int
2558 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2559 {
2560         struct hns3_config_max_frm_size_cmd *req;
2561         struct hns3_cmd_desc desc;
2562
2563         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2564
2565         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2566         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2567         req->min_frm_size = RTE_ETHER_MIN_LEN;
2568
2569         return hns3_cmd_send(hw, &desc, 1);
2570 }
2571
2572 static int
2573 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2574 {
2575         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2576         uint16_t original_mps = hns->pf.mps;
2577         int err;
2578         int ret;
2579
2580         ret = hns3_set_mac_mtu(hw, mps);
2581         if (ret) {
2582                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2583                 return ret;
2584         }
2585
2586         hns->pf.mps = mps;
2587         ret = hns3_buffer_alloc(hw);
2588         if (ret) {
2589                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2590                 goto rollback;
2591         }
2592
2593         return 0;
2594
2595 rollback:
2596         err = hns3_set_mac_mtu(hw, original_mps);
2597         if (err) {
2598                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2599                 return ret;
2600         }
2601         hns->pf.mps = original_mps;
2602
2603         return ret;
2604 }
2605
2606 static int
2607 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2608 {
2609         struct hns3_adapter *hns = dev->data->dev_private;
2610         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2611         struct hns3_hw *hw = &hns->hw;
2612         bool is_jumbo_frame;
2613         int ret;
2614
2615         if (dev->data->dev_started) {
2616                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2617                          "before configuration", dev->data->port_id);
2618                 return -EBUSY;
2619         }
2620
2621         rte_spinlock_lock(&hw->lock);
2622         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2623         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2624
2625         /*
2626          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2627          * assign to "uint16_t" type variable.
2628          */
2629         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2630         if (ret) {
2631                 rte_spinlock_unlock(&hw->lock);
2632                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2633                          dev->data->port_id, mtu, ret);
2634                 return ret;
2635         }
2636
2637         if (is_jumbo_frame)
2638                 dev->data->dev_conf.rxmode.offloads |=
2639                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2640         else
2641                 dev->data->dev_conf.rxmode.offloads &=
2642                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2643         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2644         rte_spinlock_unlock(&hw->lock);
2645
2646         return 0;
2647 }
2648
2649 static uint32_t
2650 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2651 {
2652         uint32_t speed_capa = 0;
2653
2654         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2655                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2656         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2657                 speed_capa |= ETH_LINK_SPEED_10M;
2658         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2659                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2660         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2661                 speed_capa |= ETH_LINK_SPEED_100M;
2662         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2663                 speed_capa |= ETH_LINK_SPEED_1G;
2664
2665         return speed_capa;
2666 }
2667
2668 static uint32_t
2669 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2670 {
2671         uint32_t speed_capa = 0;
2672
2673         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2674                 speed_capa |= ETH_LINK_SPEED_1G;
2675         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2676                 speed_capa |= ETH_LINK_SPEED_10G;
2677         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2678                 speed_capa |= ETH_LINK_SPEED_25G;
2679         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2680                 speed_capa |= ETH_LINK_SPEED_40G;
2681         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2682                 speed_capa |= ETH_LINK_SPEED_50G;
2683         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2684                 speed_capa |= ETH_LINK_SPEED_100G;
2685         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2686                 speed_capa |= ETH_LINK_SPEED_200G;
2687
2688         return speed_capa;
2689 }
2690
2691 static uint32_t
2692 hns3_get_speed_capa(struct hns3_hw *hw)
2693 {
2694         struct hns3_mac *mac = &hw->mac;
2695         uint32_t speed_capa;
2696
2697         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2698                 speed_capa =
2699                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2700         else
2701                 speed_capa =
2702                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2703
2704         if (mac->support_autoneg == 0)
2705                 speed_capa |= ETH_LINK_SPEED_FIXED;
2706
2707         return speed_capa;
2708 }
2709
2710 int
2711 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2712 {
2713         struct hns3_adapter *hns = eth_dev->data->dev_private;
2714         struct hns3_hw *hw = &hns->hw;
2715         uint16_t queue_num = hw->tqps_num;
2716
2717         /*
2718          * In interrupt mode, 'max_rx_queues' is set based on the number of
2719          * MSI-X interrupt resources of the hardware.
2720          */
2721         if (hw->data->dev_conf.intr_conf.rxq == 1)
2722                 queue_num = hw->intr_tqps_num;
2723
2724         info->max_rx_queues = queue_num;
2725         info->max_tx_queues = hw->tqps_num;
2726         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2727         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2728         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2729         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2730         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2731         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2732                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2733                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2734                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2735                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2736                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2737                                  DEV_RX_OFFLOAD_KEEP_CRC |
2738                                  DEV_RX_OFFLOAD_SCATTER |
2739                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2740                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2741                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2742                                  DEV_RX_OFFLOAD_RSS_HASH |
2743                                  DEV_RX_OFFLOAD_TCP_LRO);
2744         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2745                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2746                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2747                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2748                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2749                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2750                                  DEV_TX_OFFLOAD_TCP_TSO |
2751                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2752                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2753                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2754                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2755                                  hns3_txvlan_cap_get(hw));
2756
2757         if (hns3_dev_outer_udp_cksum_supported(hw))
2758                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2759
2760         if (hns3_dev_indep_txrx_supported(hw))
2761                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2762                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2763
2764         if (hns3_dev_ptp_supported(hw))
2765                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2766
2767         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2768                 .nb_max = HNS3_MAX_RING_DESC,
2769                 .nb_min = HNS3_MIN_RING_DESC,
2770                 .nb_align = HNS3_ALIGN_RING_DESC,
2771         };
2772
2773         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2774                 .nb_max = HNS3_MAX_RING_DESC,
2775                 .nb_min = HNS3_MIN_RING_DESC,
2776                 .nb_align = HNS3_ALIGN_RING_DESC,
2777                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2778                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2779         };
2780
2781         info->speed_capa = hns3_get_speed_capa(hw);
2782         info->default_rxconf = (struct rte_eth_rxconf) {
2783                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2784                 /*
2785                  * If there are no available Rx buffer descriptors, incoming
2786                  * packets are always dropped by hardware based on hns3 network
2787                  * engine.
2788                  */
2789                 .rx_drop_en = 1,
2790                 .offloads = 0,
2791         };
2792         info->default_txconf = (struct rte_eth_txconf) {
2793                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2794                 .offloads = 0,
2795         };
2796
2797         info->vmdq_queue_num = 0;
2798
2799         info->reta_size = hw->rss_ind_tbl_size;
2800         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2801         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2802
2803         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2804         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2805         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2806         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2807         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2808         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2809
2810         return 0;
2811 }
2812
2813 static int
2814 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2815                     size_t fw_size)
2816 {
2817         struct hns3_adapter *hns = eth_dev->data->dev_private;
2818         struct hns3_hw *hw = &hns->hw;
2819         uint32_t version = hw->fw_version;
2820         int ret;
2821
2822         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2823                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2824                                       HNS3_FW_VERSION_BYTE3_S),
2825                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2826                                       HNS3_FW_VERSION_BYTE2_S),
2827                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2828                                       HNS3_FW_VERSION_BYTE1_S),
2829                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2830                                       HNS3_FW_VERSION_BYTE0_S));
2831         if (ret < 0)
2832                 return -EINVAL;
2833
2834         ret += 1; /* add the size of '\0' */
2835         if (fw_size < (size_t)ret)
2836                 return ret;
2837         else
2838                 return 0;
2839 }
2840
2841 static int
2842 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2843 {
2844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2845         int ret;
2846
2847         (void)hns3_update_link_status(hw);
2848
2849         ret = hns3_update_link_info(eth_dev);
2850         if (ret)
2851                 hw->mac.link_status = ETH_LINK_DOWN;
2852
2853         return ret;
2854 }
2855
2856 static void
2857 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2858                       struct rte_eth_link *new_link)
2859 {
2860         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2861         struct hns3_mac *mac = &hw->mac;
2862
2863         switch (mac->link_speed) {
2864         case ETH_SPEED_NUM_10M:
2865         case ETH_SPEED_NUM_100M:
2866         case ETH_SPEED_NUM_1G:
2867         case ETH_SPEED_NUM_10G:
2868         case ETH_SPEED_NUM_25G:
2869         case ETH_SPEED_NUM_40G:
2870         case ETH_SPEED_NUM_50G:
2871         case ETH_SPEED_NUM_100G:
2872         case ETH_SPEED_NUM_200G:
2873                 new_link->link_speed = mac->link_speed;
2874                 break;
2875         default:
2876                 if (mac->link_status)
2877                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2878                 else
2879                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2880                 break;
2881         }
2882
2883         new_link->link_duplex = mac->link_duplex;
2884         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2885         new_link->link_autoneg = mac->link_autoneg;
2886 }
2887
2888 static int
2889 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2890 {
2891 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2892 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2893
2894         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2895         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2896         struct hns3_mac *mac = &hw->mac;
2897         struct rte_eth_link new_link;
2898         int ret;
2899
2900         /* When port is stopped, report link down. */
2901         if (eth_dev->data->dev_started == 0) {
2902                 new_link.link_autoneg = mac->link_autoneg;
2903                 new_link.link_duplex = mac->link_duplex;
2904                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2905                 new_link.link_status = ETH_LINK_DOWN;
2906                 goto out;
2907         }
2908
2909         do {
2910                 ret = hns3_update_port_link_info(eth_dev);
2911                 if (ret) {
2912                         hns3_err(hw, "failed to get port link info, ret = %d.",
2913                                  ret);
2914                         break;
2915                 }
2916
2917                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2918                         break;
2919
2920                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2921         } while (retry_cnt--);
2922
2923         memset(&new_link, 0, sizeof(new_link));
2924         hns3_setup_linkstatus(eth_dev, &new_link);
2925
2926 out:
2927         return rte_eth_linkstatus_set(eth_dev, &new_link);
2928 }
2929
2930 static int
2931 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2932 {
2933         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2934         struct hns3_pf *pf = &hns->pf;
2935
2936         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2937                 return -EINVAL;
2938
2939         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2940
2941         return 0;
2942 }
2943
2944 static int
2945 hns3_query_function_status(struct hns3_hw *hw)
2946 {
2947 #define HNS3_QUERY_MAX_CNT              10
2948 #define HNS3_QUERY_SLEEP_MSCOEND        1
2949         struct hns3_func_status_cmd *req;
2950         struct hns3_cmd_desc desc;
2951         int timeout = 0;
2952         int ret;
2953
2954         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2955         req = (struct hns3_func_status_cmd *)desc.data;
2956
2957         do {
2958                 ret = hns3_cmd_send(hw, &desc, 1);
2959                 if (ret) {
2960                         PMD_INIT_LOG(ERR, "query function status failed %d",
2961                                      ret);
2962                         return ret;
2963                 }
2964
2965                 /* Check pf reset is done */
2966                 if (req->pf_state)
2967                         break;
2968
2969                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2970         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2971
2972         return hns3_parse_func_status(hw, req);
2973 }
2974
2975 static int
2976 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2977 {
2978         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2979         struct hns3_pf *pf = &hns->pf;
2980
2981         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2982                 /*
2983                  * The total_tqps_num obtained from firmware is maximum tqp
2984                  * numbers of this port, which should be used for PF and VFs.
2985                  * There is no need for pf to have so many tqp numbers in
2986                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2987                  * coming from config file, is assigned to maximum queue number
2988                  * for the PF of this port by user. So users can modify the
2989                  * maximum queue number of PF according to their own application
2990                  * scenarios, which is more flexible to use. In addition, many
2991                  * memories can be saved due to allocating queue statistics
2992                  * room according to the actual number of queues required. The
2993                  * maximum queue number of PF for network engine with
2994                  * revision_id greater than 0x30 is assigned by config file.
2995                  */
2996                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2997                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2998                                  "must be greater than 0.",
2999                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3000                         return -EINVAL;
3001                 }
3002
3003                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3004                                        hw->total_tqps_num);
3005         } else {
3006                 /*
3007                  * Due to the limitation on the number of PF interrupts
3008                  * available, the maximum queue number assigned to PF on
3009                  * the network engine with revision_id 0x21 is 64.
3010                  */
3011                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3012                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3013         }
3014
3015         return 0;
3016 }
3017
3018 static int
3019 hns3_query_pf_resource(struct hns3_hw *hw)
3020 {
3021         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3022         struct hns3_pf *pf = &hns->pf;
3023         struct hns3_pf_res_cmd *req;
3024         struct hns3_cmd_desc desc;
3025         int ret;
3026
3027         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3028         ret = hns3_cmd_send(hw, &desc, 1);
3029         if (ret) {
3030                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3031                 return ret;
3032         }
3033
3034         req = (struct hns3_pf_res_cmd *)desc.data;
3035         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3036                              rte_le_to_cpu_16(req->ext_tqp_num);
3037         ret = hns3_get_pf_max_tqp_num(hw);
3038         if (ret)
3039                 return ret;
3040
3041         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3042         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3043
3044         if (req->tx_buf_size)
3045                 pf->tx_buf_size =
3046                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3047         else
3048                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3049
3050         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3051
3052         if (req->dv_buf_size)
3053                 pf->dv_buf_size =
3054                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3055         else
3056                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3057
3058         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3059
3060         hw->num_msi =
3061                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3062                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3063
3064         return 0;
3065 }
3066
3067 static void
3068 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3069 {
3070         struct hns3_cfg_param_cmd *req;
3071         uint64_t mac_addr_tmp_high;
3072         uint8_t ext_rss_size_max;
3073         uint64_t mac_addr_tmp;
3074         uint32_t i;
3075
3076         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3077
3078         /* get the configuration */
3079         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3080                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3081         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3082                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3083         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3084                                            HNS3_CFG_TQP_DESC_N_M,
3085                                            HNS3_CFG_TQP_DESC_N_S);
3086
3087         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3088                                        HNS3_CFG_PHY_ADDR_M,
3089                                        HNS3_CFG_PHY_ADDR_S);
3090         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3091                                          HNS3_CFG_MEDIA_TP_M,
3092                                          HNS3_CFG_MEDIA_TP_S);
3093         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3094                                          HNS3_CFG_RX_BUF_LEN_M,
3095                                          HNS3_CFG_RX_BUF_LEN_S);
3096         /* get mac address */
3097         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3098         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3099                                            HNS3_CFG_MAC_ADDR_H_M,
3100                                            HNS3_CFG_MAC_ADDR_H_S);
3101
3102         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3103
3104         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3105                                             HNS3_CFG_DEFAULT_SPEED_M,
3106                                             HNS3_CFG_DEFAULT_SPEED_S);
3107         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3108                                            HNS3_CFG_RSS_SIZE_M,
3109                                            HNS3_CFG_RSS_SIZE_S);
3110
3111         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3112                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3113
3114         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3115         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3116
3117         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3118                                             HNS3_CFG_SPEED_ABILITY_M,
3119                                             HNS3_CFG_SPEED_ABILITY_S);
3120         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3121                                         HNS3_CFG_UMV_TBL_SPACE_M,
3122                                         HNS3_CFG_UMV_TBL_SPACE_S);
3123         if (!cfg->umv_space)
3124                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3125
3126         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3127                                                HNS3_CFG_EXT_RSS_SIZE_M,
3128                                                HNS3_CFG_EXT_RSS_SIZE_S);
3129
3130         /*
3131          * Field ext_rss_size_max obtained from firmware will be more flexible
3132          * for future changes and expansions, which is an exponent of 2, instead
3133          * of reading out directly. If this field is not zero, hns3 PF PMD
3134          * driver uses it as rss_size_max under one TC. Device, whose revision
3135          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3136          * maximum number of queues supported under a TC through this field.
3137          */
3138         if (ext_rss_size_max)
3139                 cfg->rss_size_max = 1U << ext_rss_size_max;
3140 }
3141
3142 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3143  * @hw: pointer to struct hns3_hw
3144  * @hcfg: the config structure to be getted
3145  */
3146 static int
3147 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3148 {
3149         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3150         struct hns3_cfg_param_cmd *req;
3151         uint32_t offset;
3152         uint32_t i;
3153         int ret;
3154
3155         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3156                 offset = 0;
3157                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3158                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3159                                           true);
3160                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3161                                i * HNS3_CFG_RD_LEN_BYTES);
3162                 /* Len should be divided by 4 when send to hardware */
3163                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3164                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3165                 req->offset = rte_cpu_to_le_32(offset);
3166         }
3167
3168         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3169         if (ret) {
3170                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3171                 return ret;
3172         }
3173
3174         hns3_parse_cfg(hcfg, desc);
3175
3176         return 0;
3177 }
3178
3179 static int
3180 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3181 {
3182         switch (speed_cmd) {
3183         case HNS3_CFG_SPEED_10M:
3184                 *speed = ETH_SPEED_NUM_10M;
3185                 break;
3186         case HNS3_CFG_SPEED_100M:
3187                 *speed = ETH_SPEED_NUM_100M;
3188                 break;
3189         case HNS3_CFG_SPEED_1G:
3190                 *speed = ETH_SPEED_NUM_1G;
3191                 break;
3192         case HNS3_CFG_SPEED_10G:
3193                 *speed = ETH_SPEED_NUM_10G;
3194                 break;
3195         case HNS3_CFG_SPEED_25G:
3196                 *speed = ETH_SPEED_NUM_25G;
3197                 break;
3198         case HNS3_CFG_SPEED_40G:
3199                 *speed = ETH_SPEED_NUM_40G;
3200                 break;
3201         case HNS3_CFG_SPEED_50G:
3202                 *speed = ETH_SPEED_NUM_50G;
3203                 break;
3204         case HNS3_CFG_SPEED_100G:
3205                 *speed = ETH_SPEED_NUM_100G;
3206                 break;
3207         case HNS3_CFG_SPEED_200G:
3208                 *speed = ETH_SPEED_NUM_200G;
3209                 break;
3210         default:
3211                 return -EINVAL;
3212         }
3213
3214         return 0;
3215 }
3216
3217 static void
3218 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3219 {
3220         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3221         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3222         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3223         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3224         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3225 }
3226
3227 static void
3228 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3229 {
3230         struct hns3_dev_specs_0_cmd *req0;
3231
3232         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3233
3234         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3235         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3236         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3237         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3238         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3239 }
3240
3241 static int
3242 hns3_check_dev_specifications(struct hns3_hw *hw)
3243 {
3244         if (hw->rss_ind_tbl_size == 0 ||
3245             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3246                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3247                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3248                               HNS3_RSS_IND_TBL_SIZE_MAX);
3249                 return -EINVAL;
3250         }
3251
3252         return 0;
3253 }
3254
3255 static int
3256 hns3_query_dev_specifications(struct hns3_hw *hw)
3257 {
3258         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3259         int ret;
3260         int i;
3261
3262         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3263                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3264                                           true);
3265                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3266         }
3267         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3268
3269         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3270         if (ret)
3271                 return ret;
3272
3273         hns3_parse_dev_specifications(hw, desc);
3274
3275         return hns3_check_dev_specifications(hw);
3276 }
3277
3278 static int
3279 hns3_get_capability(struct hns3_hw *hw)
3280 {
3281         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3282         struct rte_pci_device *pci_dev;
3283         struct hns3_pf *pf = &hns->pf;
3284         struct rte_eth_dev *eth_dev;
3285         uint16_t device_id;
3286         uint8_t revision;
3287         int ret;
3288
3289         eth_dev = &rte_eth_devices[hw->data->port_id];
3290         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3291         device_id = pci_dev->id.device_id;
3292
3293         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3294             device_id == HNS3_DEV_ID_50GE_RDMA ||
3295             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3296             device_id == HNS3_DEV_ID_200G_RDMA)
3297                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3298
3299         /* Get PCI revision id */
3300         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3301                                   HNS3_PCI_REVISION_ID);
3302         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3303                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3304                              ret);
3305                 return -EIO;
3306         }
3307         hw->revision = revision;
3308
3309         if (revision < PCI_REVISION_ID_HIP09_A) {
3310                 hns3_set_default_dev_specifications(hw);
3311                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3312                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3313                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3314                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3315                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3316                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3317                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3318                 hw->rss_info.ipv6_sctp_offload_supported = false;
3319                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3320                 return 0;
3321         }
3322
3323         ret = hns3_query_dev_specifications(hw);
3324         if (ret) {
3325                 PMD_INIT_LOG(ERR,
3326                              "failed to query dev specifications, ret = %d",
3327                              ret);
3328                 return ret;
3329         }
3330
3331         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3332         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3333         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3334         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3335         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3336         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3337         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3338         hw->rss_info.ipv6_sctp_offload_supported = true;
3339         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3340
3341         return 0;
3342 }
3343
3344 static int
3345 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3346 {
3347         int ret;
3348
3349         switch (media_type) {
3350         case HNS3_MEDIA_TYPE_COPPER:
3351                 if (!hns3_dev_copper_supported(hw)) {
3352                         PMD_INIT_LOG(ERR,
3353                                      "Media type is copper, not supported.");
3354                         ret = -EOPNOTSUPP;
3355                 } else {
3356                         ret = 0;
3357                 }
3358                 break;
3359         case HNS3_MEDIA_TYPE_FIBER:
3360                 ret = 0;
3361                 break;
3362         case HNS3_MEDIA_TYPE_BACKPLANE:
3363                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3364                 ret = -EOPNOTSUPP;
3365                 break;
3366         default:
3367                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3368                 ret = -EINVAL;
3369                 break;
3370         }
3371
3372         return ret;
3373 }
3374
3375 static int
3376 hns3_get_board_configuration(struct hns3_hw *hw)
3377 {
3378         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3379         struct hns3_pf *pf = &hns->pf;
3380         struct hns3_cfg cfg;
3381         int ret;
3382
3383         ret = hns3_get_board_cfg(hw, &cfg);
3384         if (ret) {
3385                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3386                 return ret;
3387         }
3388
3389         ret = hns3_check_media_type(hw, cfg.media_type);
3390         if (ret)
3391                 return ret;
3392
3393         hw->mac.media_type = cfg.media_type;
3394         hw->rss_size_max = cfg.rss_size_max;
3395         hw->rss_dis_flag = false;
3396         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3397         hw->mac.phy_addr = cfg.phy_addr;
3398         hw->mac.default_addr_setted = false;
3399         hw->num_tx_desc = cfg.tqp_desc_num;
3400         hw->num_rx_desc = cfg.tqp_desc_num;
3401         hw->dcb_info.num_pg = 1;
3402         hw->dcb_info.hw_pfc_map = 0;
3403
3404         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3405         if (ret) {
3406                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3407                              cfg.default_speed, ret);
3408                 return ret;
3409         }
3410
3411         pf->tc_max = cfg.tc_num;
3412         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3413                 PMD_INIT_LOG(WARNING,
3414                              "Get TC num(%u) from flash, set TC num to 1",
3415                              pf->tc_max);
3416                 pf->tc_max = 1;
3417         }
3418
3419         /* Dev does not support DCB */
3420         if (!hns3_dev_dcb_supported(hw)) {
3421                 pf->tc_max = 1;
3422                 pf->pfc_max = 0;
3423         } else
3424                 pf->pfc_max = pf->tc_max;
3425
3426         hw->dcb_info.num_tc = 1;
3427         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3428                                      hw->tqps_num / hw->dcb_info.num_tc);
3429         hns3_set_bit(hw->hw_tc_map, 0, 1);
3430         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3431
3432         pf->wanted_umv_size = cfg.umv_space;
3433
3434         return ret;
3435 }
3436
3437 static int
3438 hns3_get_configuration(struct hns3_hw *hw)
3439 {
3440         int ret;
3441
3442         ret = hns3_query_function_status(hw);
3443         if (ret) {
3444                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3445                 return ret;
3446         }
3447
3448         /* Get device capability */
3449         ret = hns3_get_capability(hw);
3450         if (ret) {
3451                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3452                 return ret;
3453         }
3454
3455         /* Get pf resource */
3456         ret = hns3_query_pf_resource(hw);
3457         if (ret) {
3458                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3459                 return ret;
3460         }
3461
3462         ret = hns3_get_board_configuration(hw);
3463         if (ret) {
3464                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3465                 return ret;
3466         }
3467
3468         ret = hns3_query_dev_fec_info(hw);
3469         if (ret)
3470                 PMD_INIT_LOG(ERR,
3471                              "failed to query FEC information, ret = %d", ret);
3472
3473         return ret;
3474 }
3475
3476 static int
3477 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3478                       uint16_t tqp_vid, bool is_pf)
3479 {
3480         struct hns3_tqp_map_cmd *req;
3481         struct hns3_cmd_desc desc;
3482         int ret;
3483
3484         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3485
3486         req = (struct hns3_tqp_map_cmd *)desc.data;
3487         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3488         req->tqp_vf = func_id;
3489         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3490         if (!is_pf)
3491                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3492         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3493
3494         ret = hns3_cmd_send(hw, &desc, 1);
3495         if (ret)
3496                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3497
3498         return ret;
3499 }
3500
3501 static int
3502 hns3_map_tqp(struct hns3_hw *hw)
3503 {
3504         int ret;
3505         int i;
3506
3507         /*
3508          * In current version, VF is not supported when PF is driven by DPDK
3509          * driver, so we assign total tqps_num tqps allocated to this port
3510          * to PF.
3511          */
3512         for (i = 0; i < hw->total_tqps_num; i++) {
3513                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3514                 if (ret)
3515                         return ret;
3516         }
3517
3518         return 0;
3519 }
3520
3521 static int
3522 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3523 {
3524         struct hns3_config_mac_speed_dup_cmd *req;
3525         struct hns3_cmd_desc desc;
3526         int ret;
3527
3528         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3529
3530         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3531
3532         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3533
3534         switch (speed) {
3535         case ETH_SPEED_NUM_10M:
3536                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3537                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3538                 break;
3539         case ETH_SPEED_NUM_100M:
3540                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3541                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3542                 break;
3543         case ETH_SPEED_NUM_1G:
3544                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3545                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3546                 break;
3547         case ETH_SPEED_NUM_10G:
3548                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3549                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3550                 break;
3551         case ETH_SPEED_NUM_25G:
3552                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3553                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3554                 break;
3555         case ETH_SPEED_NUM_40G:
3556                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3557                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3558                 break;
3559         case ETH_SPEED_NUM_50G:
3560                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3561                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3562                 break;
3563         case ETH_SPEED_NUM_100G:
3564                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3565                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3566                 break;
3567         case ETH_SPEED_NUM_200G:
3568                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3569                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3570                 break;
3571         default:
3572                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3573                 return -EINVAL;
3574         }
3575
3576         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3577
3578         ret = hns3_cmd_send(hw, &desc, 1);
3579         if (ret)
3580                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3581
3582         return ret;
3583 }
3584
3585 static int
3586 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3587 {
3588         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3589         struct hns3_pf *pf = &hns->pf;
3590         struct hns3_priv_buf *priv;
3591         uint32_t i, total_size;
3592
3593         total_size = pf->pkt_buf_size;
3594
3595         /* alloc tx buffer for all enabled tc */
3596         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3597                 priv = &buf_alloc->priv_buf[i];
3598
3599                 if (hw->hw_tc_map & BIT(i)) {
3600                         if (total_size < pf->tx_buf_size)
3601                                 return -ENOMEM;
3602
3603                         priv->tx_buf_size = pf->tx_buf_size;
3604                 } else
3605                         priv->tx_buf_size = 0;
3606
3607                 total_size -= priv->tx_buf_size;
3608         }
3609
3610         return 0;
3611 }
3612
3613 static int
3614 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3615 {
3616 /* TX buffer size is unit by 128 byte */
3617 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3618 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3619         struct hns3_tx_buff_alloc_cmd *req;
3620         struct hns3_cmd_desc desc;
3621         uint32_t buf_size;
3622         uint32_t i;
3623         int ret;
3624
3625         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3626
3627         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3628         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3629                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3630
3631                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3632                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3633                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3634         }
3635
3636         ret = hns3_cmd_send(hw, &desc, 1);
3637         if (ret)
3638                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3639
3640         return ret;
3641 }
3642
3643 static int
3644 hns3_get_tc_num(struct hns3_hw *hw)
3645 {
3646         int cnt = 0;
3647         uint8_t i;
3648
3649         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3650                 if (hw->hw_tc_map & BIT(i))
3651                         cnt++;
3652         return cnt;
3653 }
3654
3655 static uint32_t
3656 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3657 {
3658         struct hns3_priv_buf *priv;
3659         uint32_t rx_priv = 0;
3660         int i;
3661
3662         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3663                 priv = &buf_alloc->priv_buf[i];
3664                 if (priv->enable)
3665                         rx_priv += priv->buf_size;
3666         }
3667         return rx_priv;
3668 }
3669
3670 static uint32_t
3671 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3672 {
3673         uint32_t total_tx_size = 0;
3674         uint32_t i;
3675
3676         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3677                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3678
3679         return total_tx_size;
3680 }
3681
3682 /* Get the number of pfc enabled TCs, which have private buffer */
3683 static int
3684 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3685 {
3686         struct hns3_priv_buf *priv;
3687         int cnt = 0;
3688         uint8_t i;
3689
3690         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3691                 priv = &buf_alloc->priv_buf[i];
3692                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3693                         cnt++;
3694         }
3695
3696         return cnt;
3697 }
3698
3699 /* Get the number of pfc disabled TCs, which have private buffer */
3700 static int
3701 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3702                          struct hns3_pkt_buf_alloc *buf_alloc)
3703 {
3704         struct hns3_priv_buf *priv;
3705         int cnt = 0;
3706         uint8_t i;
3707
3708         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3709                 priv = &buf_alloc->priv_buf[i];
3710                 if (hw->hw_tc_map & BIT(i) &&
3711                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3712                         cnt++;
3713         }
3714
3715         return cnt;
3716 }
3717
3718 static bool
3719 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3720                   uint32_t rx_all)
3721 {
3722         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3723         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3724         struct hns3_pf *pf = &hns->pf;
3725         uint32_t shared_buf, aligned_mps;
3726         uint32_t rx_priv;
3727         uint8_t tc_num;
3728         uint8_t i;
3729
3730         tc_num = hns3_get_tc_num(hw);
3731         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3732
3733         if (hns3_dev_dcb_supported(hw))
3734                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3735                                         pf->dv_buf_size;
3736         else
3737                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3738                                         + pf->dv_buf_size;
3739
3740         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3741         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3742                              HNS3_BUF_SIZE_UNIT);
3743
3744         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3745         if (rx_all < rx_priv + shared_std)
3746                 return false;
3747
3748         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3749         buf_alloc->s_buf.buf_size = shared_buf;
3750         if (hns3_dev_dcb_supported(hw)) {
3751                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3752                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3753                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3754                                   HNS3_BUF_SIZE_UNIT);
3755         } else {
3756                 buf_alloc->s_buf.self.high =
3757                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3758                 buf_alloc->s_buf.self.low = aligned_mps;
3759         }
3760
3761         if (hns3_dev_dcb_supported(hw)) {
3762                 hi_thrd = shared_buf - pf->dv_buf_size;
3763
3764                 if (tc_num <= NEED_RESERVE_TC_NUM)
3765                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3766                                   BUF_MAX_PERCENT;
3767
3768                 if (tc_num)
3769                         hi_thrd = hi_thrd / tc_num;
3770
3771                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3772                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3773                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3774         } else {
3775                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3776                 lo_thrd = aligned_mps;
3777         }
3778
3779         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3780                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3781                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3782         }
3783
3784         return true;
3785 }
3786
3787 static bool
3788 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3789                      struct hns3_pkt_buf_alloc *buf_alloc)
3790 {
3791         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3792         struct hns3_pf *pf = &hns->pf;
3793         struct hns3_priv_buf *priv;
3794         uint32_t aligned_mps;
3795         uint32_t rx_all;
3796         uint8_t i;
3797
3798         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3799         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3800
3801         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3802                 priv = &buf_alloc->priv_buf[i];
3803
3804                 priv->enable = 0;
3805                 priv->wl.low = 0;
3806                 priv->wl.high = 0;
3807                 priv->buf_size = 0;
3808
3809                 if (!(hw->hw_tc_map & BIT(i)))
3810                         continue;
3811
3812                 priv->enable = 1;
3813                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3814                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3815                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3816                                                 HNS3_BUF_SIZE_UNIT);
3817                 } else {
3818                         priv->wl.low = 0;
3819                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3820                                         aligned_mps;
3821                 }
3822
3823                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3824         }
3825
3826         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3827 }
3828
3829 static bool
3830 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3831                              struct hns3_pkt_buf_alloc *buf_alloc)
3832 {
3833         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3834         struct hns3_pf *pf = &hns->pf;
3835         struct hns3_priv_buf *priv;
3836         int no_pfc_priv_num;
3837         uint32_t rx_all;
3838         uint8_t mask;
3839         int i;
3840
3841         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3842         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3843
3844         /* let the last to be cleared first */
3845         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3846                 priv = &buf_alloc->priv_buf[i];
3847                 mask = BIT((uint8_t)i);
3848
3849                 if (hw->hw_tc_map & mask &&
3850                     !(hw->dcb_info.hw_pfc_map & mask)) {
3851                         /* Clear the no pfc TC private buffer */
3852                         priv->wl.low = 0;
3853                         priv->wl.high = 0;
3854                         priv->buf_size = 0;
3855                         priv->enable = 0;
3856                         no_pfc_priv_num--;
3857                 }
3858
3859                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3860                     no_pfc_priv_num == 0)
3861                         break;
3862         }
3863
3864         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3865 }
3866
3867 static bool
3868 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3869                            struct hns3_pkt_buf_alloc *buf_alloc)
3870 {
3871         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3872         struct hns3_pf *pf = &hns->pf;
3873         struct hns3_priv_buf *priv;
3874         uint32_t rx_all;
3875         int pfc_priv_num;
3876         uint8_t mask;
3877         int i;
3878
3879         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3880         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3881
3882         /* let the last to be cleared first */
3883         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3884                 priv = &buf_alloc->priv_buf[i];
3885                 mask = BIT((uint8_t)i);
3886                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3887                         /* Reduce the number of pfc TC with private buffer */
3888                         priv->wl.low = 0;
3889                         priv->enable = 0;
3890                         priv->wl.high = 0;
3891                         priv->buf_size = 0;
3892                         pfc_priv_num--;
3893                 }
3894                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3895                     pfc_priv_num == 0)
3896                         break;
3897         }
3898
3899         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3900 }
3901
3902 static bool
3903 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3904                           struct hns3_pkt_buf_alloc *buf_alloc)
3905 {
3906 #define COMPENSATE_BUFFER       0x3C00
3907 #define COMPENSATE_HALF_MPS_NUM 5
3908 #define PRIV_WL_GAP             0x1800
3909         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3910         struct hns3_pf *pf = &hns->pf;
3911         uint32_t tc_num = hns3_get_tc_num(hw);
3912         uint32_t half_mps = pf->mps >> 1;
3913         struct hns3_priv_buf *priv;
3914         uint32_t min_rx_priv;
3915         uint32_t rx_priv;
3916         uint8_t i;
3917
3918         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3919         if (tc_num)
3920                 rx_priv = rx_priv / tc_num;
3921
3922         if (tc_num <= NEED_RESERVE_TC_NUM)
3923                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3924
3925         /*
3926          * Minimum value of private buffer in rx direction (min_rx_priv) is
3927          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3928          * buffer if rx_priv is greater than min_rx_priv.
3929          */
3930         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3931                         COMPENSATE_HALF_MPS_NUM * half_mps;
3932         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3933         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3934
3935         if (rx_priv < min_rx_priv)
3936                 return false;
3937
3938         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3939                 priv = &buf_alloc->priv_buf[i];
3940                 priv->enable = 0;
3941                 priv->wl.low = 0;
3942                 priv->wl.high = 0;
3943                 priv->buf_size = 0;
3944
3945                 if (!(hw->hw_tc_map & BIT(i)))
3946                         continue;
3947
3948                 priv->enable = 1;
3949                 priv->buf_size = rx_priv;
3950                 priv->wl.high = rx_priv - pf->dv_buf_size;
3951                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3952         }
3953
3954         buf_alloc->s_buf.buf_size = 0;
3955
3956         return true;
3957 }
3958
3959 /*
3960  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3961  * @hw: pointer to struct hns3_hw
3962  * @buf_alloc: pointer to buffer calculation data
3963  * @return: 0: calculate sucessful, negative: fail
3964  */
3965 static int
3966 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3967 {
3968         /* When DCB is not supported, rx private buffer is not allocated. */
3969         if (!hns3_dev_dcb_supported(hw)) {
3970                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3971                 struct hns3_pf *pf = &hns->pf;
3972                 uint32_t rx_all = pf->pkt_buf_size;
3973
3974                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3975                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3976                         return -ENOMEM;
3977
3978                 return 0;
3979         }
3980
3981         /*
3982          * Try to allocate privated packet buffer for all TCs without share
3983          * buffer.
3984          */
3985         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3986                 return 0;
3987
3988         /*
3989          * Try to allocate privated packet buffer for all TCs with share
3990          * buffer.
3991          */
3992         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3993                 return 0;
3994
3995         /*
3996          * For different application scenes, the enabled port number, TC number
3997          * and no_drop TC number are different. In order to obtain the better
3998          * performance, software could allocate the buffer size and configure
3999          * the waterline by trying to decrease the private buffer size according
4000          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4001          * enabled tc.
4002          */
4003         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4004                 return 0;
4005
4006         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4007                 return 0;
4008
4009         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4010                 return 0;
4011
4012         return -ENOMEM;
4013 }
4014
4015 static int
4016 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4017 {
4018         struct hns3_rx_priv_buff_cmd *req;
4019         struct hns3_cmd_desc desc;
4020         uint32_t buf_size;
4021         int ret;
4022         int i;
4023
4024         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4025         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4026
4027         /* Alloc private buffer TCs */
4028         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4029                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4030
4031                 req->buf_num[i] =
4032                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4033                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4034         }
4035
4036         buf_size = buf_alloc->s_buf.buf_size;
4037         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4038                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4039
4040         ret = hns3_cmd_send(hw, &desc, 1);
4041         if (ret)
4042                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4043
4044         return ret;
4045 }
4046
4047 static int
4048 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4049 {
4050 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4051         struct hns3_rx_priv_wl_buf *req;
4052         struct hns3_priv_buf *priv;
4053         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4054         int i, j;
4055         int ret;
4056
4057         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4058                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4059                                           false);
4060                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4061
4062                 /* The first descriptor set the NEXT bit to 1 */
4063                 if (i == 0)
4064                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4065                 else
4066                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4067
4068                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4069                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4070
4071                         priv = &buf_alloc->priv_buf[idx];
4072                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4073                                                         HNS3_BUF_UNIT_S);
4074                         req->tc_wl[j].high |=
4075                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4076                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4077                                                         HNS3_BUF_UNIT_S);
4078                         req->tc_wl[j].low |=
4079                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4080                 }
4081         }
4082
4083         /* Send 2 descriptor at one time */
4084         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4085         if (ret)
4086                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4087                              ret);
4088         return ret;
4089 }
4090
4091 static int
4092 hns3_common_thrd_config(struct hns3_hw *hw,
4093                         struct hns3_pkt_buf_alloc *buf_alloc)
4094 {
4095 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4096         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4097         struct hns3_rx_com_thrd *req;
4098         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4099         struct hns3_tc_thrd *tc;
4100         int tc_idx;
4101         int i, j;
4102         int ret;
4103
4104         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4105                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4106                                           false);
4107                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4108
4109                 /* The first descriptor set the NEXT bit to 1 */
4110                 if (i == 0)
4111                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4112                 else
4113                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4114
4115                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4116                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4117                         tc = &s_buf->tc_thrd[tc_idx];
4118
4119                         req->com_thrd[j].high =
4120                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4121                         req->com_thrd[j].high |=
4122                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4123                         req->com_thrd[j].low =
4124                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4125                         req->com_thrd[j].low |=
4126                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4127                 }
4128         }
4129
4130         /* Send 2 descriptors at one time */
4131         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4132         if (ret)
4133                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4134
4135         return ret;
4136 }
4137
4138 static int
4139 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4140 {
4141         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4142         struct hns3_rx_com_wl *req;
4143         struct hns3_cmd_desc desc;
4144         int ret;
4145
4146         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4147
4148         req = (struct hns3_rx_com_wl *)desc.data;
4149         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4150         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4151
4152         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4153         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4154
4155         ret = hns3_cmd_send(hw, &desc, 1);
4156         if (ret)
4157                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4158
4159         return ret;
4160 }
4161
4162 int
4163 hns3_buffer_alloc(struct hns3_hw *hw)
4164 {
4165         struct hns3_pkt_buf_alloc pkt_buf;
4166         int ret;
4167
4168         memset(&pkt_buf, 0, sizeof(pkt_buf));
4169         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4170         if (ret) {
4171                 PMD_INIT_LOG(ERR,
4172                              "could not calc tx buffer size for all TCs %d",
4173                              ret);
4174                 return ret;
4175         }
4176
4177         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4178         if (ret) {
4179                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4180                 return ret;
4181         }
4182
4183         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4184         if (ret) {
4185                 PMD_INIT_LOG(ERR,
4186                              "could not calc rx priv buffer size for all TCs %d",
4187                              ret);
4188                 return ret;
4189         }
4190
4191         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4192         if (ret) {
4193                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4194                 return ret;
4195         }
4196
4197         if (hns3_dev_dcb_supported(hw)) {
4198                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4199                 if (ret) {
4200                         PMD_INIT_LOG(ERR,
4201                                      "could not configure rx private waterline %d",
4202                                      ret);
4203                         return ret;
4204                 }
4205
4206                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4207                 if (ret) {
4208                         PMD_INIT_LOG(ERR,
4209                                      "could not configure common threshold %d",
4210                                      ret);
4211                         return ret;
4212                 }
4213         }
4214
4215         ret = hns3_common_wl_config(hw, &pkt_buf);
4216         if (ret)
4217                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4218                              ret);
4219
4220         return ret;
4221 }
4222
4223 static int
4224 hns3_mac_init(struct hns3_hw *hw)
4225 {
4226         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4227         struct hns3_mac *mac = &hw->mac;
4228         struct hns3_pf *pf = &hns->pf;
4229         int ret;
4230
4231         pf->support_sfp_query = true;
4232         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4233         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4234         if (ret) {
4235                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4236                 return ret;
4237         }
4238
4239         mac->link_status = ETH_LINK_DOWN;
4240
4241         return hns3_config_mtu(hw, pf->mps);
4242 }
4243
4244 static int
4245 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4246 {
4247 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4248 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4249 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4250 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4251         int return_status;
4252
4253         if (cmdq_resp) {
4254                 PMD_INIT_LOG(ERR,
4255                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4256                              cmdq_resp);
4257                 return -EIO;
4258         }
4259
4260         switch (resp_code) {
4261         case HNS3_ETHERTYPE_SUCCESS_ADD:
4262         case HNS3_ETHERTYPE_ALREADY_ADD:
4263                 return_status = 0;
4264                 break;
4265         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4266                 PMD_INIT_LOG(ERR,
4267                              "add mac ethertype failed for manager table overflow.");
4268                 return_status = -EIO;
4269                 break;
4270         case HNS3_ETHERTYPE_KEY_CONFLICT:
4271                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4272                 return_status = -EIO;
4273                 break;
4274         default:
4275                 PMD_INIT_LOG(ERR,
4276                              "add mac ethertype failed for undefined, code=%u.",
4277                              resp_code);
4278                 return_status = -EIO;
4279                 break;
4280         }
4281
4282         return return_status;
4283 }
4284
4285 static int
4286 hns3_add_mgr_tbl(struct hns3_hw *hw,
4287                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4288 {
4289         struct hns3_cmd_desc desc;
4290         uint8_t resp_code;
4291         uint16_t retval;
4292         int ret;
4293
4294         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4295         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4296
4297         ret = hns3_cmd_send(hw, &desc, 1);
4298         if (ret) {
4299                 PMD_INIT_LOG(ERR,
4300                              "add mac ethertype failed for cmd_send, ret =%d.",
4301                              ret);
4302                 return ret;
4303         }
4304
4305         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4306         retval = rte_le_to_cpu_16(desc.retval);
4307
4308         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4309 }
4310
4311 static void
4312 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4313                      int *table_item_num)
4314 {
4315         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4316
4317         /*
4318          * In current version, we add one item in management table as below:
4319          * 0x0180C200000E -- LLDP MC address
4320          */
4321         tbl = mgr_table;
4322         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4323         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4324         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4325         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4326         tbl->i_port_bitmap = 0x1;
4327         *table_item_num = 1;
4328 }
4329
4330 static int
4331 hns3_init_mgr_tbl(struct hns3_hw *hw)
4332 {
4333 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4334         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4335         int table_item_num;
4336         int ret;
4337         int i;
4338
4339         memset(mgr_table, 0, sizeof(mgr_table));
4340         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4341         for (i = 0; i < table_item_num; i++) {
4342                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4343                 if (ret) {
4344                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4345                                      ret);
4346                         return ret;
4347                 }
4348         }
4349
4350         return 0;
4351 }
4352
4353 static void
4354 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4355                         bool en_mc, bool en_bc, int vport_id)
4356 {
4357         if (!param)
4358                 return;
4359
4360         memset(param, 0, sizeof(struct hns3_promisc_param));
4361         if (en_uc)
4362                 param->enable = HNS3_PROMISC_EN_UC;
4363         if (en_mc)
4364                 param->enable |= HNS3_PROMISC_EN_MC;
4365         if (en_bc)
4366                 param->enable |= HNS3_PROMISC_EN_BC;
4367         param->vf_id = vport_id;
4368 }
4369
4370 static int
4371 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4372 {
4373         struct hns3_promisc_cfg_cmd *req;
4374         struct hns3_cmd_desc desc;
4375         int ret;
4376
4377         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4378
4379         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4380         req->vf_id = param->vf_id;
4381         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4382             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4383
4384         ret = hns3_cmd_send(hw, &desc, 1);
4385         if (ret)
4386                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4387
4388         return ret;
4389 }
4390
4391 static int
4392 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4393 {
4394         struct hns3_promisc_param param;
4395         bool en_bc_pmc = true;
4396         uint8_t vf_id;
4397
4398         /*
4399          * In current version VF is not supported when PF is driven by DPDK
4400          * driver, just need to configure parameters for PF vport.
4401          */
4402         vf_id = HNS3_PF_FUNC_ID;
4403
4404         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4405         return hns3_cmd_set_promisc_mode(hw, &param);
4406 }
4407
4408 static int
4409 hns3_promisc_init(struct hns3_hw *hw)
4410 {
4411         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4412         struct hns3_pf *pf = &hns->pf;
4413         struct hns3_promisc_param param;
4414         uint16_t func_id;
4415         int ret;
4416
4417         ret = hns3_set_promisc_mode(hw, false, false);
4418         if (ret) {
4419                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4420                 return ret;
4421         }
4422
4423         /*
4424          * In current version VFs are not supported when PF is driven by DPDK
4425          * driver. After PF has been taken over by DPDK, the original VF will
4426          * be invalid. So, there is a possibility of entry residues. It should
4427          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4428          * during init.
4429          */
4430         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4431                 hns3_promisc_param_init(&param, false, false, false, func_id);
4432                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4433                 if (ret) {
4434                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4435                                         " ret = %d", func_id, ret);
4436                         return ret;
4437                 }
4438         }
4439
4440         return 0;
4441 }
4442
4443 static void
4444 hns3_promisc_uninit(struct hns3_hw *hw)
4445 {
4446         struct hns3_promisc_param param;
4447         uint16_t func_id;
4448         int ret;
4449
4450         func_id = HNS3_PF_FUNC_ID;
4451
4452         /*
4453          * In current version VFs are not supported when PF is driven by
4454          * DPDK driver, and VFs' promisc mode status has been cleared during
4455          * init and their status will not change. So just clear PF's promisc
4456          * mode status during uninit.
4457          */
4458         hns3_promisc_param_init(&param, false, false, false, func_id);
4459         ret = hns3_cmd_set_promisc_mode(hw, &param);
4460         if (ret)
4461                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4462                                 " uninit, ret = %d", ret);
4463 }
4464
4465 static int
4466 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4467 {
4468         bool allmulti = dev->data->all_multicast ? true : false;
4469         struct hns3_adapter *hns = dev->data->dev_private;
4470         struct hns3_hw *hw = &hns->hw;
4471         uint64_t offloads;
4472         int err;
4473         int ret;
4474
4475         rte_spinlock_lock(&hw->lock);
4476         ret = hns3_set_promisc_mode(hw, true, true);
4477         if (ret) {
4478                 rte_spinlock_unlock(&hw->lock);
4479                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4480                          ret);
4481                 return ret;
4482         }
4483
4484         /*
4485          * When promiscuous mode was enabled, disable the vlan filter to let
4486          * all packets coming in in the receiving direction.
4487          */
4488         offloads = dev->data->dev_conf.rxmode.offloads;
4489         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4490                 ret = hns3_enable_vlan_filter(hns, false);
4491                 if (ret) {
4492                         hns3_err(hw, "failed to enable promiscuous mode due to "
4493                                      "failure to disable vlan filter, ret = %d",
4494                                  ret);
4495                         err = hns3_set_promisc_mode(hw, false, allmulti);
4496                         if (err)
4497                                 hns3_err(hw, "failed to restore promiscuous "
4498                                          "status after disable vlan filter "
4499                                          "failed during enabling promiscuous "
4500                                          "mode, ret = %d", ret);
4501                 }
4502         }
4503
4504         rte_spinlock_unlock(&hw->lock);
4505
4506         return ret;
4507 }
4508
4509 static int
4510 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4511 {
4512         bool allmulti = dev->data->all_multicast ? true : false;
4513         struct hns3_adapter *hns = dev->data->dev_private;
4514         struct hns3_hw *hw = &hns->hw;
4515         uint64_t offloads;
4516         int err;
4517         int ret;
4518
4519         /* If now in all_multicast mode, must remain in all_multicast mode. */
4520         rte_spinlock_lock(&hw->lock);
4521         ret = hns3_set_promisc_mode(hw, false, allmulti);
4522         if (ret) {
4523                 rte_spinlock_unlock(&hw->lock);
4524                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4525                          ret);
4526                 return ret;
4527         }
4528         /* when promiscuous mode was disabled, restore the vlan filter status */
4529         offloads = dev->data->dev_conf.rxmode.offloads;
4530         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4531                 ret = hns3_enable_vlan_filter(hns, true);
4532                 if (ret) {
4533                         hns3_err(hw, "failed to disable promiscuous mode due to"
4534                                  " failure to restore vlan filter, ret = %d",
4535                                  ret);
4536                         err = hns3_set_promisc_mode(hw, true, true);
4537                         if (err)
4538                                 hns3_err(hw, "failed to restore promiscuous "
4539                                          "status after enabling vlan filter "
4540                                          "failed during disabling promiscuous "
4541                                          "mode, ret = %d", ret);
4542                 }
4543         }
4544         rte_spinlock_unlock(&hw->lock);
4545
4546         return ret;
4547 }
4548
4549 static int
4550 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4551 {
4552         struct hns3_adapter *hns = dev->data->dev_private;
4553         struct hns3_hw *hw = &hns->hw;
4554         int ret;
4555
4556         if (dev->data->promiscuous)
4557                 return 0;
4558
4559         rte_spinlock_lock(&hw->lock);
4560         ret = hns3_set_promisc_mode(hw, false, true);
4561         rte_spinlock_unlock(&hw->lock);
4562         if (ret)
4563                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4564                          ret);
4565
4566         return ret;
4567 }
4568
4569 static int
4570 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4571 {
4572         struct hns3_adapter *hns = dev->data->dev_private;
4573         struct hns3_hw *hw = &hns->hw;
4574         int ret;
4575
4576         /* If now in promiscuous mode, must remain in all_multicast mode. */
4577         if (dev->data->promiscuous)
4578                 return 0;
4579
4580         rte_spinlock_lock(&hw->lock);
4581         ret = hns3_set_promisc_mode(hw, false, false);
4582         rte_spinlock_unlock(&hw->lock);
4583         if (ret)
4584                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4585                          ret);
4586
4587         return ret;
4588 }
4589
4590 static int
4591 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4592 {
4593         struct hns3_hw *hw = &hns->hw;
4594         bool allmulti = hw->data->all_multicast ? true : false;
4595         int ret;
4596
4597         if (hw->data->promiscuous) {
4598                 ret = hns3_set_promisc_mode(hw, true, true);
4599                 if (ret)
4600                         hns3_err(hw, "failed to restore promiscuous mode, "
4601                                  "ret = %d", ret);
4602                 return ret;
4603         }
4604
4605         ret = hns3_set_promisc_mode(hw, false, allmulti);
4606         if (ret)
4607                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4608                          ret);
4609         return ret;
4610 }
4611
4612 static int
4613 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4614 {
4615         struct hns3_sfp_info_cmd *resp;
4616         struct hns3_cmd_desc desc;
4617         int ret;
4618
4619         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4620         resp = (struct hns3_sfp_info_cmd *)desc.data;
4621         resp->query_type = HNS3_ACTIVE_QUERY;
4622
4623         ret = hns3_cmd_send(hw, &desc, 1);
4624         if (ret == -EOPNOTSUPP) {
4625                 hns3_warn(hw, "firmware does not support get SFP info,"
4626                           " ret = %d.", ret);
4627                 return ret;
4628         } else if (ret) {
4629                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4630                 return ret;
4631         }
4632
4633         /*
4634          * In some case, the speed of MAC obtained from firmware may be 0, it
4635          * shouldn't be set to mac->speed.
4636          */
4637         if (!rte_le_to_cpu_32(resp->sfp_speed))
4638                 return 0;
4639
4640         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4641         /*
4642          * if resp->supported_speed is 0, it means it's an old version
4643          * firmware, do not update these params.
4644          */
4645         if (resp->supported_speed) {
4646                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4647                 mac_info->supported_speed =
4648                                         rte_le_to_cpu_32(resp->supported_speed);
4649                 mac_info->support_autoneg = resp->autoneg_ability;
4650                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4651                                         : ETH_LINK_AUTONEG;
4652         } else {
4653                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4654         }
4655
4656         return 0;
4657 }
4658
4659 static uint8_t
4660 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4661 {
4662         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4663                 duplex = ETH_LINK_FULL_DUPLEX;
4664
4665         return duplex;
4666 }
4667
4668 static int
4669 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4670 {
4671         struct hns3_mac *mac = &hw->mac;
4672         int ret;
4673
4674         duplex = hns3_check_speed_dup(duplex, speed);
4675         if (mac->link_speed == speed && mac->link_duplex == duplex)
4676                 return 0;
4677
4678         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4679         if (ret)
4680                 return ret;
4681
4682         ret = hns3_port_shaper_update(hw, speed);
4683         if (ret)
4684                 return ret;
4685
4686         mac->link_speed = speed;
4687         mac->link_duplex = duplex;
4688
4689         return 0;
4690 }
4691
4692 static int
4693 hns3_update_fiber_link_info(struct hns3_hw *hw)
4694 {
4695         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4696         struct hns3_mac *mac = &hw->mac;
4697         struct hns3_mac mac_info;
4698         int ret;
4699
4700         /* If firmware do not support get SFP/qSFP speed, return directly */
4701         if (!pf->support_sfp_query)
4702                 return 0;
4703
4704         memset(&mac_info, 0, sizeof(struct hns3_mac));
4705         ret = hns3_get_sfp_info(hw, &mac_info);
4706         if (ret == -EOPNOTSUPP) {
4707                 pf->support_sfp_query = false;
4708                 return ret;
4709         } else if (ret)
4710                 return ret;
4711
4712         /* Do nothing if no SFP */
4713         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4714                 return 0;
4715
4716         /*
4717          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4718          * to reconfigure the speed of MAC. Otherwise, it indicates
4719          * that the current firmware only supports to obtain the
4720          * speed of the SFP, and the speed of MAC needs to reconfigure.
4721          */
4722         mac->query_type = mac_info.query_type;
4723         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4724                 if (mac_info.link_speed != mac->link_speed) {
4725                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4726                         if (ret)
4727                                 return ret;
4728                 }
4729
4730                 mac->link_speed = mac_info.link_speed;
4731                 mac->supported_speed = mac_info.supported_speed;
4732                 mac->support_autoneg = mac_info.support_autoneg;
4733                 mac->link_autoneg = mac_info.link_autoneg;
4734
4735                 return 0;
4736         }
4737
4738         /* Config full duplex for SFP */
4739         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4740                                       ETH_LINK_FULL_DUPLEX);
4741 }
4742
4743 static void
4744 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4745 {
4746 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4747
4748         struct hns3_phy_params_bd0_cmd *req;
4749         uint32_t supported;
4750
4751         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4752         mac->link_speed = rte_le_to_cpu_32(req->speed);
4753         mac->link_duplex = hns3_get_bit(req->duplex,
4754                                            HNS3_PHY_DUPLEX_CFG_B);
4755         mac->link_autoneg = hns3_get_bit(req->autoneg,
4756                                            HNS3_PHY_AUTONEG_CFG_B);
4757         mac->advertising = rte_le_to_cpu_32(req->advertising);
4758         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4759         supported = rte_le_to_cpu_32(req->supported);
4760         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4761         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4762 }
4763
4764 static int
4765 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4766 {
4767         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4768         uint16_t i;
4769         int ret;
4770
4771         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4772                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4773                                           true);
4774                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4775         }
4776         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4777
4778         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4779         if (ret) {
4780                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4781                 return ret;
4782         }
4783
4784         hns3_parse_copper_phy_params(desc, mac);
4785
4786         return 0;
4787 }
4788
4789 static int
4790 hns3_update_copper_link_info(struct hns3_hw *hw)
4791 {
4792         struct hns3_mac *mac = &hw->mac;
4793         struct hns3_mac mac_info;
4794         int ret;
4795
4796         memset(&mac_info, 0, sizeof(struct hns3_mac));
4797         ret = hns3_get_copper_phy_params(hw, &mac_info);
4798         if (ret)
4799                 return ret;
4800
4801         if (mac_info.link_speed != mac->link_speed) {
4802                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4803                 if (ret)
4804                         return ret;
4805         }
4806
4807         mac->link_speed = mac_info.link_speed;
4808         mac->link_duplex = mac_info.link_duplex;
4809         mac->link_autoneg = mac_info.link_autoneg;
4810         mac->supported_speed = mac_info.supported_speed;
4811         mac->advertising = mac_info.advertising;
4812         mac->lp_advertising = mac_info.lp_advertising;
4813         mac->support_autoneg = mac_info.support_autoneg;
4814
4815         return 0;
4816 }
4817
4818 static int
4819 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4820 {
4821         struct hns3_adapter *hns = eth_dev->data->dev_private;
4822         struct hns3_hw *hw = &hns->hw;
4823         int ret = 0;
4824
4825         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4826                 ret = hns3_update_copper_link_info(hw);
4827         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4828                 ret = hns3_update_fiber_link_info(hw);
4829
4830         return ret;
4831 }
4832
4833 static int
4834 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4835 {
4836         struct hns3_config_mac_mode_cmd *req;
4837         struct hns3_cmd_desc desc;
4838         uint32_t loop_en = 0;
4839         uint8_t val = 0;
4840         int ret;
4841
4842         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4843
4844         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4845         if (enable)
4846                 val = 1;
4847         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4848         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4849         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4850         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4851         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4852         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4853         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4854         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4855         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4856         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4857
4858         /*
4859          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4860          * when receiving frames. Otherwise, CRC will be stripped.
4861          */
4862         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4863                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4864         else
4865                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4866         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4867         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4868         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4869         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4870
4871         ret = hns3_cmd_send(hw, &desc, 1);
4872         if (ret)
4873                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4874
4875         return ret;
4876 }
4877
4878 static int
4879 hns3_get_mac_link_status(struct hns3_hw *hw)
4880 {
4881         struct hns3_link_status_cmd *req;
4882         struct hns3_cmd_desc desc;
4883         int link_status;
4884         int ret;
4885
4886         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4887         ret = hns3_cmd_send(hw, &desc, 1);
4888         if (ret) {
4889                 hns3_err(hw, "get link status cmd failed %d", ret);
4890                 return ETH_LINK_DOWN;
4891         }
4892
4893         req = (struct hns3_link_status_cmd *)desc.data;
4894         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4895
4896         return !!link_status;
4897 }
4898
4899 static bool
4900 hns3_update_link_status(struct hns3_hw *hw)
4901 {
4902         int state;
4903
4904         state = hns3_get_mac_link_status(hw);
4905         if (state != hw->mac.link_status) {
4906                 hw->mac.link_status = state;
4907                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4908                 return true;
4909         }
4910
4911         return false;
4912 }
4913
4914 void
4915 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4916 {
4917         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4918         struct rte_eth_link new_link;
4919         int ret;
4920
4921         if (query)
4922                 hns3_update_port_link_info(dev);
4923
4924         memset(&new_link, 0, sizeof(new_link));
4925         hns3_setup_linkstatus(dev, &new_link);
4926
4927         ret = rte_eth_linkstatus_set(dev, &new_link);
4928         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4929                 hns3_start_report_lse(dev);
4930 }
4931
4932 static void
4933 hns3_service_handler(void *param)
4934 {
4935         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4936         struct hns3_adapter *hns = eth_dev->data->dev_private;
4937         struct hns3_hw *hw = &hns->hw;
4938
4939         if (!hns3_is_reset_pending(hns))
4940                 hns3_update_linkstatus_and_event(hw, true);
4941         else
4942                 hns3_warn(hw, "Cancel the query when reset is pending");
4943
4944         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4945 }
4946
4947 static int
4948 hns3_init_hardware(struct hns3_adapter *hns)
4949 {
4950         struct hns3_hw *hw = &hns->hw;
4951         int ret;
4952
4953         ret = hns3_map_tqp(hw);
4954         if (ret) {
4955                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4956                 return ret;
4957         }
4958
4959         ret = hns3_init_umv_space(hw);
4960         if (ret) {
4961                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4962                 return ret;
4963         }
4964
4965         ret = hns3_mac_init(hw);
4966         if (ret) {
4967                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4968                 goto err_mac_init;
4969         }
4970
4971         ret = hns3_init_mgr_tbl(hw);
4972         if (ret) {
4973                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4974                 goto err_mac_init;
4975         }
4976
4977         ret = hns3_promisc_init(hw);
4978         if (ret) {
4979                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4980                              ret);
4981                 goto err_mac_init;
4982         }
4983
4984         ret = hns3_init_vlan_config(hns);
4985         if (ret) {
4986                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4987                 goto err_mac_init;
4988         }
4989
4990         ret = hns3_dcb_init(hw);
4991         if (ret) {
4992                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4993                 goto err_mac_init;
4994         }
4995
4996         ret = hns3_init_fd_config(hns);
4997         if (ret) {
4998                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4999                 goto err_mac_init;
5000         }
5001
5002         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5003         if (ret) {
5004                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5005                 goto err_mac_init;
5006         }
5007
5008         ret = hns3_config_gro(hw, false);
5009         if (ret) {
5010                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5011                 goto err_mac_init;
5012         }
5013
5014         /*
5015          * In the initialization clearing the all hardware mapping relationship
5016          * configurations between queues and interrupt vectors is needed, so
5017          * some error caused by the residual configurations, such as the
5018          * unexpected interrupt, can be avoid.
5019          */
5020         ret = hns3_init_ring_with_vector(hw);
5021         if (ret) {
5022                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5023                 goto err_mac_init;
5024         }
5025
5026         return 0;
5027
5028 err_mac_init:
5029         hns3_uninit_umv_space(hw);
5030         return ret;
5031 }
5032
5033 static int
5034 hns3_clear_hw(struct hns3_hw *hw)
5035 {
5036         struct hns3_cmd_desc desc;
5037         int ret;
5038
5039         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5040
5041         ret = hns3_cmd_send(hw, &desc, 1);
5042         if (ret && ret != -EOPNOTSUPP)
5043                 return ret;
5044
5045         return 0;
5046 }
5047
5048 static void
5049 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5050 {
5051         uint32_t val;
5052
5053         /*
5054          * The new firmware support report more hardware error types by
5055          * msix mode. These errors are defined as RAS errors in hardware
5056          * and belong to a different type from the MSI-x errors processed
5057          * by the network driver.
5058          *
5059          * Network driver should open the new error report on initialization.
5060          */
5061         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5062         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5063         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5064 }
5065
5066 static uint32_t
5067 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5068 {
5069         struct hns3_mac *mac = &hw->mac;
5070
5071         switch (mac->link_speed) {
5072         case ETH_SPEED_NUM_1G:
5073                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5074         case ETH_SPEED_NUM_10G:
5075                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5076         case ETH_SPEED_NUM_25G:
5077                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5078         case ETH_SPEED_NUM_40G:
5079                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5080         case ETH_SPEED_NUM_50G:
5081                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5082         case ETH_SPEED_NUM_100G:
5083                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5084         case ETH_SPEED_NUM_200G:
5085                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5086         default:
5087                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5088                 return 0;
5089         }
5090 }
5091
5092 /*
5093  * Validity of supported_speed for firber and copper media type can be
5094  * guaranteed by the following policy:
5095  * Copper:
5096  *       Although the initialization of the phy in the firmware may not be
5097  *       completed, the firmware can guarantees that the supported_speed is
5098  *       an valid value.
5099  * Firber:
5100  *       If the version of firmware supports the acitive query way of the
5101  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5102  *       through it. If unsupported, use the SFP's speed as the value of the
5103  *       supported_speed.
5104  */
5105 static int
5106 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5107 {
5108         struct hns3_adapter *hns = eth_dev->data->dev_private;
5109         struct hns3_hw *hw = &hns->hw;
5110         struct hns3_mac *mac = &hw->mac;
5111         int ret;
5112
5113         ret = hns3_update_link_info(eth_dev);
5114         if (ret)
5115                 return ret;
5116
5117         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5118                 /*
5119                  * Some firmware does not support the report of supported_speed,
5120                  * and only report the effective speed of SFP. In this case, it
5121                  * is necessary to use the SFP's speed as the supported_speed.
5122                  */
5123                 if (mac->supported_speed == 0)
5124                         mac->supported_speed =
5125                                 hns3_set_firber_default_support_speed(hw);
5126         }
5127
5128         return 0;
5129 }
5130
5131 static void
5132 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5133 {
5134         struct hns3_mac *mac = &hns->hw.mac;
5135
5136         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5137                 hns->pf.support_fc_autoneg = true;
5138                 return;
5139         }
5140
5141         /*
5142          * Flow control auto-negotiation requires the cooperation of the driver
5143          * and firmware. Currently, the optical port does not support flow
5144          * control auto-negotiation.
5145          */
5146         hns->pf.support_fc_autoneg = false;
5147 }
5148
5149 static int
5150 hns3_init_pf(struct rte_eth_dev *eth_dev)
5151 {
5152         struct rte_device *dev = eth_dev->device;
5153         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5154         struct hns3_adapter *hns = eth_dev->data->dev_private;
5155         struct hns3_hw *hw = &hns->hw;
5156         int ret;
5157
5158         PMD_INIT_FUNC_TRACE();
5159
5160         /* Get hardware io base address from pcie BAR2 IO space */
5161         hw->io_base = pci_dev->mem_resource[2].addr;
5162
5163         /* Firmware command queue initialize */
5164         ret = hns3_cmd_init_queue(hw);
5165         if (ret) {
5166                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5167                 goto err_cmd_init_queue;
5168         }
5169
5170         hns3_clear_all_event_cause(hw);
5171
5172         /* Firmware command initialize */
5173         ret = hns3_cmd_init(hw);
5174         if (ret) {
5175                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5176                 goto err_cmd_init;
5177         }
5178
5179         /*
5180          * To ensure that the hardware environment is clean during
5181          * initialization, the driver actively clear the hardware environment
5182          * during initialization, including PF and corresponding VFs' vlan, mac,
5183          * flow table configurations, etc.
5184          */
5185         ret = hns3_clear_hw(hw);
5186         if (ret) {
5187                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5188                 goto err_cmd_init;
5189         }
5190
5191         /* Hardware statistics of imissed registers cleared. */
5192         ret = hns3_update_imissed_stats(hw, true);
5193         if (ret) {
5194                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5195                 goto err_cmd_init;
5196         }
5197
5198         hns3_config_all_msix_error(hw, true);
5199
5200         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5201                                          hns3_interrupt_handler,
5202                                          eth_dev);
5203         if (ret) {
5204                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5205                 goto err_intr_callback_register;
5206         }
5207
5208         ret = hns3_ptp_init(hw);
5209         if (ret)
5210                 goto err_get_config;
5211
5212         /* Enable interrupt */
5213         rte_intr_enable(&pci_dev->intr_handle);
5214         hns3_pf_enable_irq0(hw);
5215
5216         /* Get configuration */
5217         ret = hns3_get_configuration(hw);
5218         if (ret) {
5219                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5220                 goto err_get_config;
5221         }
5222
5223         ret = hns3_tqp_stats_init(hw);
5224         if (ret)
5225                 goto err_get_config;
5226
5227         ret = hns3_init_hardware(hns);
5228         if (ret) {
5229                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5230                 goto err_init_hw;
5231         }
5232
5233         /* Initialize flow director filter list & hash */
5234         ret = hns3_fdir_filter_init(hns);
5235         if (ret) {
5236                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5237                 goto err_fdir;
5238         }
5239
5240         hns3_rss_set_default_args(hw);
5241
5242         ret = hns3_enable_hw_error_intr(hns, true);
5243         if (ret) {
5244                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5245                              ret);
5246                 goto err_enable_intr;
5247         }
5248
5249         ret = hns3_get_port_supported_speed(eth_dev);
5250         if (ret) {
5251                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5252                              "by device, ret = %d.", ret);
5253                 goto err_supported_speed;
5254         }
5255
5256         hns3_get_fc_autoneg_capability(hns);
5257
5258         hns3_tm_conf_init(eth_dev);
5259
5260         return 0;
5261
5262 err_supported_speed:
5263         (void)hns3_enable_hw_error_intr(hns, false);
5264 err_enable_intr:
5265         hns3_fdir_filter_uninit(hns);
5266 err_fdir:
5267         hns3_uninit_umv_space(hw);
5268 err_init_hw:
5269         hns3_tqp_stats_uninit(hw);
5270 err_get_config:
5271         hns3_pf_disable_irq0(hw);
5272         rte_intr_disable(&pci_dev->intr_handle);
5273         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5274                              eth_dev);
5275 err_intr_callback_register:
5276 err_cmd_init:
5277         hns3_cmd_uninit(hw);
5278         hns3_cmd_destroy_queue(hw);
5279 err_cmd_init_queue:
5280         hw->io_base = NULL;
5281
5282         return ret;
5283 }
5284
5285 static void
5286 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5287 {
5288         struct hns3_adapter *hns = eth_dev->data->dev_private;
5289         struct rte_device *dev = eth_dev->device;
5290         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5291         struct hns3_hw *hw = &hns->hw;
5292
5293         PMD_INIT_FUNC_TRACE();
5294
5295         hns3_tm_conf_uninit(eth_dev);
5296         hns3_enable_hw_error_intr(hns, false);
5297         hns3_rss_uninit(hns);
5298         (void)hns3_config_gro(hw, false);
5299         hns3_promisc_uninit(hw);
5300         hns3_fdir_filter_uninit(hns);
5301         hns3_uninit_umv_space(hw);
5302         hns3_tqp_stats_uninit(hw);
5303         hns3_config_mac_tnl_int(hw, false);
5304         hns3_pf_disable_irq0(hw);
5305         rte_intr_disable(&pci_dev->intr_handle);
5306         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5307                              eth_dev);
5308         hns3_config_all_msix_error(hw, false);
5309         hns3_cmd_uninit(hw);
5310         hns3_cmd_destroy_queue(hw);
5311         hw->io_base = NULL;
5312 }
5313
5314 static uint32_t
5315 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5316 {
5317         uint32_t speed_bit;
5318
5319         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5320         case ETH_LINK_SPEED_10M:
5321                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5322                 break;
5323         case ETH_LINK_SPEED_10M_HD:
5324                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5325                 break;
5326         case ETH_LINK_SPEED_100M:
5327                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5328                 break;
5329         case ETH_LINK_SPEED_100M_HD:
5330                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5331                 break;
5332         case ETH_LINK_SPEED_1G:
5333                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5334                 break;
5335         default:
5336                 speed_bit = 0;
5337                 break;
5338         }
5339
5340         return speed_bit;
5341 }
5342
5343 static uint32_t
5344 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5345 {
5346         uint32_t speed_bit;
5347
5348         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5349         case ETH_LINK_SPEED_1G:
5350                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5351                 break;
5352         case ETH_LINK_SPEED_10G:
5353                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5354                 break;
5355         case ETH_LINK_SPEED_25G:
5356                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5357                 break;
5358         case ETH_LINK_SPEED_40G:
5359                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5360                 break;
5361         case ETH_LINK_SPEED_50G:
5362                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5363                 break;
5364         case ETH_LINK_SPEED_100G:
5365                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5366                 break;
5367         case ETH_LINK_SPEED_200G:
5368                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5369                 break;
5370         default:
5371                 speed_bit = 0;
5372                 break;
5373         }
5374
5375         return speed_bit;
5376 }
5377
5378 static int
5379 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5380 {
5381         struct hns3_mac *mac = &hw->mac;
5382         uint32_t supported_speed = mac->supported_speed;
5383         uint32_t speed_bit = 0;
5384
5385         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5386                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5387         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5388                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5389
5390         if (!(speed_bit & supported_speed)) {
5391                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5392                          link_speeds);
5393                 return -EINVAL;
5394         }
5395
5396         return 0;
5397 }
5398
5399 static inline uint32_t
5400 hns3_get_link_speed(uint32_t link_speeds)
5401 {
5402         uint32_t speed = ETH_SPEED_NUM_NONE;
5403
5404         if (link_speeds & ETH_LINK_SPEED_10M ||
5405             link_speeds & ETH_LINK_SPEED_10M_HD)
5406                 speed = ETH_SPEED_NUM_10M;
5407         if (link_speeds & ETH_LINK_SPEED_100M ||
5408             link_speeds & ETH_LINK_SPEED_100M_HD)
5409                 speed = ETH_SPEED_NUM_100M;
5410         if (link_speeds & ETH_LINK_SPEED_1G)
5411                 speed = ETH_SPEED_NUM_1G;
5412         if (link_speeds & ETH_LINK_SPEED_10G)
5413                 speed = ETH_SPEED_NUM_10G;
5414         if (link_speeds & ETH_LINK_SPEED_25G)
5415                 speed = ETH_SPEED_NUM_25G;
5416         if (link_speeds & ETH_LINK_SPEED_40G)
5417                 speed = ETH_SPEED_NUM_40G;
5418         if (link_speeds & ETH_LINK_SPEED_50G)
5419                 speed = ETH_SPEED_NUM_50G;
5420         if (link_speeds & ETH_LINK_SPEED_100G)
5421                 speed = ETH_SPEED_NUM_100G;
5422         if (link_speeds & ETH_LINK_SPEED_200G)
5423                 speed = ETH_SPEED_NUM_200G;
5424
5425         return speed;
5426 }
5427
5428 static uint8_t
5429 hns3_get_link_duplex(uint32_t link_speeds)
5430 {
5431         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5432             (link_speeds & ETH_LINK_SPEED_100M_HD))
5433                 return ETH_LINK_HALF_DUPLEX;
5434         else
5435                 return ETH_LINK_FULL_DUPLEX;
5436 }
5437
5438 static int
5439 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5440                                 struct hns3_set_link_speed_cfg *cfg)
5441 {
5442         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5443         struct hns3_phy_params_bd0_cmd *req;
5444         uint16_t i;
5445
5446         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5447                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5448                                           false);
5449                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5450         }
5451         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5452         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5453         req->autoneg = cfg->autoneg;
5454
5455         /*
5456          * The full speed capability is used to negotiate when
5457          * auto-negotiation is enabled.
5458          */
5459         if (cfg->autoneg) {
5460                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5461                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5462                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5463                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5464                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5465         } else {
5466                 req->speed = cfg->speed;
5467                 req->duplex = cfg->duplex;
5468         }
5469
5470         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5471 }
5472
5473 static int
5474 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5475 {
5476         struct hns3_config_auto_neg_cmd *req;
5477         struct hns3_cmd_desc desc;
5478         uint32_t flag = 0;
5479         int ret;
5480
5481         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5482
5483         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5484         if (enable)
5485                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5486         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5487
5488         ret = hns3_cmd_send(hw, &desc, 1);
5489         if (ret)
5490                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5491
5492         return ret;
5493 }
5494
5495 static int
5496 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5497                                struct hns3_set_link_speed_cfg *cfg)
5498 {
5499         int ret;
5500
5501         if (hw->mac.support_autoneg) {
5502                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5503                 if (ret) {
5504                         hns3_err(hw, "failed to configure auto-negotiation.");
5505                         return ret;
5506                 }
5507
5508                 /*
5509                  * To enable auto-negotiation, we only need to open the switch
5510                  * of auto-negotiation, then firmware sets all speed
5511                  * capabilities.
5512                  */
5513                 if (cfg->autoneg)
5514                         return 0;
5515         }
5516
5517         /*
5518          * Some hardware doesn't support auto-negotiation, but users may not
5519          * configure link_speeds (default 0), which means auto-negotiation.
5520          * In this case, it should return success.
5521          */
5522         if (cfg->autoneg)
5523                 return 0;
5524
5525         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5526 }
5527
5528 static int
5529 hns3_set_port_link_speed(struct hns3_hw *hw,
5530                          struct hns3_set_link_speed_cfg *cfg)
5531 {
5532         int ret;
5533
5534         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5535 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5536                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5537                 if (pf->is_tmp_phy)
5538                         return 0;
5539 #endif
5540
5541                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5542                 if (ret) {
5543                         hns3_err(hw, "failed to set copper port link speed,"
5544                                  "ret = %d.", ret);
5545                         return ret;
5546                 }
5547         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5548                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5549                 if (ret) {
5550                         hns3_err(hw, "failed to set fiber port link speed,"
5551                                  "ret = %d.", ret);
5552                         return ret;
5553                 }
5554         }
5555
5556         return 0;
5557 }
5558
5559 static int
5560 hns3_apply_link_speed(struct hns3_hw *hw)
5561 {
5562         struct rte_eth_conf *conf = &hw->data->dev_conf;
5563         struct hns3_set_link_speed_cfg cfg;
5564
5565         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5566         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5567                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5568         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5569                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5570                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5571         }
5572
5573         return hns3_set_port_link_speed(hw, &cfg);
5574 }
5575
5576 static int
5577 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5578 {
5579         struct hns3_hw *hw = &hns->hw;
5580         int ret;
5581
5582         ret = hns3_dcb_cfg_update(hns);
5583         if (ret)
5584                 return ret;
5585
5586         /*
5587          * The hns3_dcb_cfg_update may configure TM module, so
5588          * hns3_tm_conf_update must called later.
5589          */
5590         ret = hns3_tm_conf_update(hw);
5591         if (ret) {
5592                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5593                 return ret;
5594         }
5595
5596         hns3_enable_rxd_adv_layout(hw);
5597
5598         ret = hns3_init_queues(hns, reset_queue);
5599         if (ret) {
5600                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5601                 return ret;
5602         }
5603
5604         ret = hns3_cfg_mac_mode(hw, true);
5605         if (ret) {
5606                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5607                 goto err_config_mac_mode;
5608         }
5609
5610         ret = hns3_apply_link_speed(hw);
5611         if (ret)
5612                 goto err_config_mac_mode;
5613
5614         return 0;
5615
5616 err_config_mac_mode:
5617         (void)hns3_cfg_mac_mode(hw, false);
5618         hns3_dev_release_mbufs(hns);
5619         /*
5620          * Here is exception handling, hns3_reset_all_tqps will have the
5621          * corresponding error message if it is handled incorrectly, so it is
5622          * not necessary to check hns3_reset_all_tqps return value, here keep
5623          * ret as the error code causing the exception.
5624          */
5625         (void)hns3_reset_all_tqps(hns);
5626         return ret;
5627 }
5628
5629 static int
5630 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5631 {
5632         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5633         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5634         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5635         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5636         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5637         uint32_t intr_vector;
5638         uint16_t q_id;
5639         int ret;
5640
5641         /*
5642          * hns3 needs a separate interrupt to be used as event interrupt which
5643          * could not be shared with task queue pair, so KERNEL drivers need
5644          * support multiple interrupt vectors.
5645          */
5646         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5647             !rte_intr_cap_multiple(intr_handle))
5648                 return 0;
5649
5650         rte_intr_disable(intr_handle);
5651         intr_vector = hw->used_rx_queues;
5652         /* creates event fd for each intr vector when MSIX is used */
5653         if (rte_intr_efd_enable(intr_handle, intr_vector))
5654                 return -EINVAL;
5655
5656         if (intr_handle->intr_vec == NULL) {
5657                 intr_handle->intr_vec =
5658                         rte_zmalloc("intr_vec",
5659                                     hw->used_rx_queues * sizeof(int), 0);
5660                 if (intr_handle->intr_vec == NULL) {
5661                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5662                                         hw->used_rx_queues);
5663                         ret = -ENOMEM;
5664                         goto alloc_intr_vec_error;
5665                 }
5666         }
5667
5668         if (rte_intr_allow_others(intr_handle)) {
5669                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5670                 base = RTE_INTR_VEC_RXTX_OFFSET;
5671         }
5672
5673         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5674                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5675                                                  HNS3_RING_TYPE_RX, q_id);
5676                 if (ret)
5677                         goto bind_vector_error;
5678                 intr_handle->intr_vec[q_id] = vec;
5679                 /*
5680                  * If there are not enough efds (e.g. not enough interrupt),
5681                  * remaining queues will be bond to the last interrupt.
5682                  */
5683                 if (vec < base + intr_handle->nb_efd - 1)
5684                         vec++;
5685         }
5686         rte_intr_enable(intr_handle);
5687         return 0;
5688
5689 bind_vector_error:
5690         rte_free(intr_handle->intr_vec);
5691         intr_handle->intr_vec = NULL;
5692 alloc_intr_vec_error:
5693         rte_intr_efd_disable(intr_handle);
5694         return ret;
5695 }
5696
5697 static int
5698 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5699 {
5700         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5701         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5703         uint16_t q_id;
5704         int ret;
5705
5706         if (dev->data->dev_conf.intr_conf.rxq == 0)
5707                 return 0;
5708
5709         if (rte_intr_dp_is_en(intr_handle)) {
5710                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5711                         ret = hns3_bind_ring_with_vector(hw,
5712                                         intr_handle->intr_vec[q_id], true,
5713                                         HNS3_RING_TYPE_RX, q_id);
5714                         if (ret)
5715                                 return ret;
5716                 }
5717         }
5718
5719         return 0;
5720 }
5721
5722 static void
5723 hns3_restore_filter(struct rte_eth_dev *dev)
5724 {
5725         hns3_restore_rss_filter(dev);
5726 }
5727
5728 static int
5729 hns3_dev_start(struct rte_eth_dev *dev)
5730 {
5731         struct hns3_adapter *hns = dev->data->dev_private;
5732         struct hns3_hw *hw = &hns->hw;
5733         int ret;
5734
5735         PMD_INIT_FUNC_TRACE();
5736         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5737                 return -EBUSY;
5738
5739         rte_spinlock_lock(&hw->lock);
5740         hw->adapter_state = HNS3_NIC_STARTING;
5741
5742         ret = hns3_do_start(hns, true);
5743         if (ret) {
5744                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5745                 rte_spinlock_unlock(&hw->lock);
5746                 return ret;
5747         }
5748         ret = hns3_map_rx_interrupt(dev);
5749         if (ret)
5750                 goto map_rx_inter_err;
5751
5752         /*
5753          * There are three register used to control the status of a TQP
5754          * (contains a pair of Tx queue and Rx queue) in the new version network
5755          * engine. One is used to control the enabling of Tx queue, the other is
5756          * used to control the enabling of Rx queue, and the last is the master
5757          * switch used to control the enabling of the tqp. The Tx register and
5758          * TQP register must be enabled at the same time to enable a Tx queue.
5759          * The same applies to the Rx queue. For the older network engine, this
5760          * function only refresh the enabled flag, and it is used to update the
5761          * status of queue in the dpdk framework.
5762          */
5763         ret = hns3_start_all_txqs(dev);
5764         if (ret)
5765                 goto map_rx_inter_err;
5766
5767         ret = hns3_start_all_rxqs(dev);
5768         if (ret)
5769                 goto start_all_rxqs_fail;
5770
5771         hw->adapter_state = HNS3_NIC_STARTED;
5772         rte_spinlock_unlock(&hw->lock);
5773
5774         hns3_rx_scattered_calc(dev);
5775         hns3_set_rxtx_function(dev);
5776         hns3_mp_req_start_rxtx(dev);
5777
5778         hns3_restore_filter(dev);
5779
5780         /* Enable interrupt of all rx queues before enabling queues */
5781         hns3_dev_all_rx_queue_intr_enable(hw, true);
5782
5783         /*
5784          * After finished the initialization, enable tqps to receive/transmit
5785          * packets and refresh all queue status.
5786          */
5787         hns3_start_tqps(hw);
5788
5789         hns3_tm_dev_start_proc(hw);
5790
5791         if (dev->data->dev_conf.intr_conf.lsc != 0)
5792                 hns3_dev_link_update(dev, 0);
5793         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5794
5795         hns3_info(hw, "hns3 dev start successful!");
5796
5797         return 0;
5798
5799 start_all_rxqs_fail:
5800         hns3_stop_all_txqs(dev);
5801 map_rx_inter_err:
5802         (void)hns3_do_stop(hns);
5803         hw->adapter_state = HNS3_NIC_CONFIGURED;
5804         rte_spinlock_unlock(&hw->lock);
5805
5806         return ret;
5807 }
5808
5809 static int
5810 hns3_do_stop(struct hns3_adapter *hns)
5811 {
5812         struct hns3_hw *hw = &hns->hw;
5813         int ret;
5814
5815         /*
5816          * The "hns3_do_stop" function will also be called by .stop_service to
5817          * prepare reset. At the time of global or IMP reset, the command cannot
5818          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5819          * accessed during the reset process. So the mbuf can not be released
5820          * during reset and is required to be released after the reset is
5821          * completed.
5822          */
5823         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5824                 hns3_dev_release_mbufs(hns);
5825
5826         ret = hns3_cfg_mac_mode(hw, false);
5827         if (ret)
5828                 return ret;
5829         hw->mac.link_status = ETH_LINK_DOWN;
5830
5831         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5832                 hns3_configure_all_mac_addr(hns, true);
5833                 ret = hns3_reset_all_tqps(hns);
5834                 if (ret) {
5835                         hns3_err(hw, "failed to reset all queues ret = %d.",
5836                                  ret);
5837                         return ret;
5838                 }
5839         }
5840         hw->mac.default_addr_setted = false;
5841         return 0;
5842 }
5843
5844 static void
5845 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5846 {
5847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5849         struct hns3_adapter *hns = dev->data->dev_private;
5850         struct hns3_hw *hw = &hns->hw;
5851         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5852         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5853         uint16_t q_id;
5854
5855         if (dev->data->dev_conf.intr_conf.rxq == 0)
5856                 return;
5857
5858         /* unmap the ring with vector */
5859         if (rte_intr_allow_others(intr_handle)) {
5860                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5861                 base = RTE_INTR_VEC_RXTX_OFFSET;
5862         }
5863         if (rte_intr_dp_is_en(intr_handle)) {
5864                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5865                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5866                                                          HNS3_RING_TYPE_RX,
5867                                                          q_id);
5868                         if (vec < base + intr_handle->nb_efd - 1)
5869                                 vec++;
5870                 }
5871         }
5872         /* Clean datapath event and queue/vec mapping */
5873         rte_intr_efd_disable(intr_handle);
5874         if (intr_handle->intr_vec) {
5875                 rte_free(intr_handle->intr_vec);
5876                 intr_handle->intr_vec = NULL;
5877         }
5878 }
5879
5880 static int
5881 hns3_dev_stop(struct rte_eth_dev *dev)
5882 {
5883         struct hns3_adapter *hns = dev->data->dev_private;
5884         struct hns3_hw *hw = &hns->hw;
5885
5886         PMD_INIT_FUNC_TRACE();
5887         dev->data->dev_started = 0;
5888
5889         hw->adapter_state = HNS3_NIC_STOPPING;
5890         hns3_set_rxtx_function(dev);
5891         rte_wmb();
5892         /* Disable datapath on secondary process. */
5893         hns3_mp_req_stop_rxtx(dev);
5894         /* Prevent crashes when queues are still in use. */
5895         rte_delay_ms(hw->tqps_num);
5896
5897         rte_spinlock_lock(&hw->lock);
5898         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5899                 hns3_tm_dev_stop_proc(hw);
5900                 hns3_config_mac_tnl_int(hw, false);
5901                 hns3_stop_tqps(hw);
5902                 hns3_do_stop(hns);
5903                 hns3_unmap_rx_interrupt(dev);
5904                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5905         }
5906         hns3_rx_scattered_reset(dev);
5907         rte_eal_alarm_cancel(hns3_service_handler, dev);
5908         hns3_stop_report_lse(dev);
5909         rte_spinlock_unlock(&hw->lock);
5910
5911         return 0;
5912 }
5913
5914 static int
5915 hns3_dev_close(struct rte_eth_dev *eth_dev)
5916 {
5917         struct hns3_adapter *hns = eth_dev->data->dev_private;
5918         struct hns3_hw *hw = &hns->hw;
5919         int ret = 0;
5920
5921         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5922                 rte_free(eth_dev->process_private);
5923                 eth_dev->process_private = NULL;
5924                 return 0;
5925         }
5926
5927         if (hw->adapter_state == HNS3_NIC_STARTED)
5928                 ret = hns3_dev_stop(eth_dev);
5929
5930         hw->adapter_state = HNS3_NIC_CLOSING;
5931         hns3_reset_abort(hns);
5932         hw->adapter_state = HNS3_NIC_CLOSED;
5933
5934         hns3_configure_all_mc_mac_addr(hns, true);
5935         hns3_remove_all_vlan_table(hns);
5936         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5937         hns3_uninit_pf(eth_dev);
5938         hns3_free_all_queues(eth_dev);
5939         rte_free(hw->reset.wait_data);
5940         rte_free(eth_dev->process_private);
5941         eth_dev->process_private = NULL;
5942         hns3_mp_uninit_primary();
5943         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5944
5945         return ret;
5946 }
5947
5948 static void
5949 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5950                                    bool *tx_pause)
5951 {
5952         struct hns3_mac *mac = &hw->mac;
5953         uint32_t advertising = mac->advertising;
5954         uint32_t lp_advertising = mac->lp_advertising;
5955         *rx_pause = false;
5956         *tx_pause = false;
5957
5958         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5959                 *rx_pause = true;
5960                 *tx_pause = true;
5961         } else if (advertising & lp_advertising &
5962                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5963                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5964                         *rx_pause = true;
5965                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5966                         *tx_pause = true;
5967         }
5968 }
5969
5970 static enum hns3_fc_mode
5971 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5972 {
5973         enum hns3_fc_mode current_mode;
5974         bool rx_pause = false;
5975         bool tx_pause = false;
5976
5977         switch (hw->mac.media_type) {
5978         case HNS3_MEDIA_TYPE_COPPER:
5979                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5980                 break;
5981
5982         /*
5983          * Flow control auto-negotiation is not supported for fiber and
5984          * backpalne media type.
5985          */
5986         case HNS3_MEDIA_TYPE_FIBER:
5987         case HNS3_MEDIA_TYPE_BACKPLANE:
5988                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5989                 current_mode = hw->requested_fc_mode;
5990                 goto out;
5991         default:
5992                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5993                          hw->mac.media_type);
5994                 current_mode = HNS3_FC_NONE;
5995                 goto out;
5996         }
5997
5998         if (rx_pause && tx_pause)
5999                 current_mode = HNS3_FC_FULL;
6000         else if (rx_pause)
6001                 current_mode = HNS3_FC_RX_PAUSE;
6002         else if (tx_pause)
6003                 current_mode = HNS3_FC_TX_PAUSE;
6004         else
6005                 current_mode = HNS3_FC_NONE;
6006
6007 out:
6008         return current_mode;
6009 }
6010
6011 static enum hns3_fc_mode
6012 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6013 {
6014         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6015         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6016         struct hns3_mac *mac = &hw->mac;
6017
6018         /*
6019          * When the flow control mode is obtained, the device may not complete
6020          * auto-negotiation. It is necessary to wait for link establishment.
6021          */
6022         (void)hns3_dev_link_update(dev, 1);
6023
6024         /*
6025          * If the link auto-negotiation of the nic is disabled, or the flow
6026          * control auto-negotiation is not supported, the forced flow control
6027          * mode is used.
6028          */
6029         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6030                 return hw->requested_fc_mode;
6031
6032         return hns3_get_autoneg_fc_mode(hw);
6033 }
6034
6035 static int
6036 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6037 {
6038         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6040         enum hns3_fc_mode current_mode;
6041
6042         current_mode = hns3_get_current_fc_mode(dev);
6043         switch (current_mode) {
6044         case HNS3_FC_FULL:
6045                 fc_conf->mode = RTE_FC_FULL;
6046                 break;
6047         case HNS3_FC_TX_PAUSE:
6048                 fc_conf->mode = RTE_FC_TX_PAUSE;
6049                 break;
6050         case HNS3_FC_RX_PAUSE:
6051                 fc_conf->mode = RTE_FC_RX_PAUSE;
6052                 break;
6053         case HNS3_FC_NONE:
6054         default:
6055                 fc_conf->mode = RTE_FC_NONE;
6056                 break;
6057         }
6058
6059         fc_conf->pause_time = pf->pause_time;
6060         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6061
6062         return 0;
6063 }
6064
6065 static void
6066 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6067 {
6068         switch (mode) {
6069         case RTE_FC_NONE:
6070                 hw->requested_fc_mode = HNS3_FC_NONE;
6071                 break;
6072         case RTE_FC_RX_PAUSE:
6073                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6074                 break;
6075         case RTE_FC_TX_PAUSE:
6076                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6077                 break;
6078         case RTE_FC_FULL:
6079                 hw->requested_fc_mode = HNS3_FC_FULL;
6080                 break;
6081         default:
6082                 hw->requested_fc_mode = HNS3_FC_NONE;
6083                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6084                           "configured to RTE_FC_NONE", mode);
6085                 break;
6086         }
6087 }
6088
6089 static int
6090 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6091 {
6092         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6093
6094         if (!pf->support_fc_autoneg) {
6095                 if (autoneg != 0) {
6096                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6097                         return -EOPNOTSUPP;
6098                 }
6099
6100                 /*
6101                  * Flow control auto-negotiation of the NIC is not supported,
6102                  * but other auto-negotiation features may be supported.
6103                  */
6104                 if (autoneg != hw->mac.link_autoneg) {
6105                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6106                         return -EOPNOTSUPP;
6107                 }
6108
6109                 return 0;
6110         }
6111
6112         /*
6113          * If flow control auto-negotiation of the NIC is supported, all
6114          * auto-negotiation features are supported.
6115          */
6116         if (autoneg != hw->mac.link_autoneg) {
6117                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6118                 return -EOPNOTSUPP;
6119         }
6120
6121         return 0;
6122 }
6123
6124 static int
6125 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6126 {
6127         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6128         int ret;
6129
6130         if (fc_conf->high_water || fc_conf->low_water ||
6131             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6132                 hns3_err(hw, "Unsupported flow control settings specified, "
6133                          "high_water(%u), low_water(%u), send_xon(%u) and "
6134                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6135                          fc_conf->high_water, fc_conf->low_water,
6136                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6137                 return -EINVAL;
6138         }
6139
6140         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6141         if (ret)
6142                 return ret;
6143
6144         if (!fc_conf->pause_time) {
6145                 hns3_err(hw, "Invalid pause time %u setting.",
6146                          fc_conf->pause_time);
6147                 return -EINVAL;
6148         }
6149
6150         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6151             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6152                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6153                          "current_fc_status = %d", hw->current_fc_status);
6154                 return -EOPNOTSUPP;
6155         }
6156
6157         if (hw->num_tc > 1) {
6158                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6159                 return -EOPNOTSUPP;
6160         }
6161
6162         hns3_get_fc_mode(hw, fc_conf->mode);
6163
6164         rte_spinlock_lock(&hw->lock);
6165         ret = hns3_fc_enable(dev, fc_conf);
6166         rte_spinlock_unlock(&hw->lock);
6167
6168         return ret;
6169 }
6170
6171 static int
6172 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6173                             struct rte_eth_pfc_conf *pfc_conf)
6174 {
6175         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176         int ret;
6177
6178         if (!hns3_dev_dcb_supported(hw)) {
6179                 hns3_err(hw, "This port does not support dcb configurations.");
6180                 return -EOPNOTSUPP;
6181         }
6182
6183         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6184             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6185                 hns3_err(hw, "Unsupported flow control settings specified, "
6186                          "high_water(%u), low_water(%u), send_xon(%u) and "
6187                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6188                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6189                          pfc_conf->fc.send_xon,
6190                          pfc_conf->fc.mac_ctrl_frame_fwd);
6191                 return -EINVAL;
6192         }
6193         if (pfc_conf->fc.autoneg) {
6194                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6195                 return -EINVAL;
6196         }
6197         if (pfc_conf->fc.pause_time == 0) {
6198                 hns3_err(hw, "Invalid pause time %u setting.",
6199                          pfc_conf->fc.pause_time);
6200                 return -EINVAL;
6201         }
6202
6203         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6204             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6205                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6206                              "current_fc_status = %d", hw->current_fc_status);
6207                 return -EOPNOTSUPP;
6208         }
6209
6210         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6211
6212         rte_spinlock_lock(&hw->lock);
6213         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6214         rte_spinlock_unlock(&hw->lock);
6215
6216         return ret;
6217 }
6218
6219 static int
6220 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6221 {
6222         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6223         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6224         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6225         int i;
6226
6227         rte_spinlock_lock(&hw->lock);
6228         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6229                 dcb_info->nb_tcs = pf->local_max_tc;
6230         else
6231                 dcb_info->nb_tcs = 1;
6232
6233         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6234                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6235         for (i = 0; i < dcb_info->nb_tcs; i++)
6236                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6237
6238         for (i = 0; i < hw->num_tc; i++) {
6239                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6240                 dcb_info->tc_queue.tc_txq[0][i].base =
6241                                                 hw->tc_queue[i].tqp_offset;
6242                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6243                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6244                                                 hw->tc_queue[i].tqp_count;
6245         }
6246         rte_spinlock_unlock(&hw->lock);
6247
6248         return 0;
6249 }
6250
6251 static int
6252 hns3_reinit_dev(struct hns3_adapter *hns)
6253 {
6254         struct hns3_hw *hw = &hns->hw;
6255         int ret;
6256
6257         ret = hns3_cmd_init(hw);
6258         if (ret) {
6259                 hns3_err(hw, "Failed to init cmd: %d", ret);
6260                 return ret;
6261         }
6262
6263         ret = hns3_reset_all_tqps(hns);
6264         if (ret) {
6265                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6266                 return ret;
6267         }
6268
6269         ret = hns3_init_hardware(hns);
6270         if (ret) {
6271                 hns3_err(hw, "Failed to init hardware: %d", ret);
6272                 return ret;
6273         }
6274
6275         ret = hns3_enable_hw_error_intr(hns, true);
6276         if (ret) {
6277                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6278                              ret);
6279                 return ret;
6280         }
6281         hns3_info(hw, "Reset done, driver initialization finished.");
6282
6283         return 0;
6284 }
6285
6286 static bool
6287 is_pf_reset_done(struct hns3_hw *hw)
6288 {
6289         uint32_t val, reg, reg_bit;
6290
6291         switch (hw->reset.level) {
6292         case HNS3_IMP_RESET:
6293                 reg = HNS3_GLOBAL_RESET_REG;
6294                 reg_bit = HNS3_IMP_RESET_BIT;
6295                 break;
6296         case HNS3_GLOBAL_RESET:
6297                 reg = HNS3_GLOBAL_RESET_REG;
6298                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6299                 break;
6300         case HNS3_FUNC_RESET:
6301                 reg = HNS3_FUN_RST_ING;
6302                 reg_bit = HNS3_FUN_RST_ING_B;
6303                 break;
6304         case HNS3_FLR_RESET:
6305         default:
6306                 hns3_err(hw, "Wait for unsupported reset level: %d",
6307                          hw->reset.level);
6308                 return true;
6309         }
6310         val = hns3_read_dev(hw, reg);
6311         if (hns3_get_bit(val, reg_bit))
6312                 return false;
6313         else
6314                 return true;
6315 }
6316
6317 bool
6318 hns3_is_reset_pending(struct hns3_adapter *hns)
6319 {
6320         struct hns3_hw *hw = &hns->hw;
6321         enum hns3_reset_level reset;
6322
6323         hns3_check_event_cause(hns, NULL);
6324         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6325
6326         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6327             hw->reset.level < reset) {
6328                 hns3_warn(hw, "High level reset %d is pending", reset);
6329                 return true;
6330         }
6331         reset = hns3_get_reset_level(hns, &hw->reset.request);
6332         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6333             hw->reset.level < reset) {
6334                 hns3_warn(hw, "High level reset %d is request", reset);
6335                 return true;
6336         }
6337         return false;
6338 }
6339
6340 static int
6341 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6342 {
6343         struct hns3_hw *hw = &hns->hw;
6344         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6345         struct timeval tv;
6346
6347         if (wait_data->result == HNS3_WAIT_SUCCESS)
6348                 return 0;
6349         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6350                 gettimeofday(&tv, NULL);
6351                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6352                           tv.tv_sec, tv.tv_usec);
6353                 return -ETIME;
6354         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6355                 return -EAGAIN;
6356
6357         wait_data->hns = hns;
6358         wait_data->check_completion = is_pf_reset_done;
6359         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6360                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6361         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6362         wait_data->count = HNS3_RESET_WAIT_CNT;
6363         wait_data->result = HNS3_WAIT_REQUEST;
6364         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6365         return -EAGAIN;
6366 }
6367
6368 static int
6369 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6370 {
6371         struct hns3_cmd_desc desc;
6372         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6373
6374         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6375         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6376         req->fun_reset_vfid = func_id;
6377
6378         return hns3_cmd_send(hw, &desc, 1);
6379 }
6380
6381 static int
6382 hns3_imp_reset_cmd(struct hns3_hw *hw)
6383 {
6384         struct hns3_cmd_desc desc;
6385
6386         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6387         desc.data[0] = 0xeedd;
6388
6389         return hns3_cmd_send(hw, &desc, 1);
6390 }
6391
6392 static void
6393 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6394 {
6395         struct hns3_hw *hw = &hns->hw;
6396         struct timeval tv;
6397         uint32_t val;
6398
6399         gettimeofday(&tv, NULL);
6400         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6401             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6402                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6403                           tv.tv_sec, tv.tv_usec);
6404                 return;
6405         }
6406
6407         switch (reset_level) {
6408         case HNS3_IMP_RESET:
6409                 hns3_imp_reset_cmd(hw);
6410                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6411                           tv.tv_sec, tv.tv_usec);
6412                 break;
6413         case HNS3_GLOBAL_RESET:
6414                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6415                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6416                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6417                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6418                           tv.tv_sec, tv.tv_usec);
6419                 break;
6420         case HNS3_FUNC_RESET:
6421                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6422                           tv.tv_sec, tv.tv_usec);
6423                 /* schedule again to check later */
6424                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6425                 hns3_schedule_reset(hns);
6426                 break;
6427         default:
6428                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6429                 return;
6430         }
6431         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6432 }
6433
6434 static enum hns3_reset_level
6435 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6436 {
6437         struct hns3_hw *hw = &hns->hw;
6438         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6439
6440         /* Return the highest priority reset level amongst all */
6441         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6442                 reset_level = HNS3_IMP_RESET;
6443         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6444                 reset_level = HNS3_GLOBAL_RESET;
6445         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6446                 reset_level = HNS3_FUNC_RESET;
6447         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6448                 reset_level = HNS3_FLR_RESET;
6449
6450         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6451                 return HNS3_NONE_RESET;
6452
6453         return reset_level;
6454 }
6455
6456 static void
6457 hns3_record_imp_error(struct hns3_adapter *hns)
6458 {
6459         struct hns3_hw *hw = &hns->hw;
6460         uint32_t reg_val;
6461
6462         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6463         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6464                 hns3_warn(hw, "Detected IMP RD poison!");
6465                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6466                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6467         }
6468
6469         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6470                 hns3_warn(hw, "Detected IMP CMDQ error!");
6471                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6472                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6473         }
6474 }
6475
6476 static int
6477 hns3_prepare_reset(struct hns3_adapter *hns)
6478 {
6479         struct hns3_hw *hw = &hns->hw;
6480         uint32_t reg_val;
6481         int ret;
6482
6483         switch (hw->reset.level) {
6484         case HNS3_FUNC_RESET:
6485                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6486                 if (ret)
6487                         return ret;
6488
6489                 /*
6490                  * After performaning pf reset, it is not necessary to do the
6491                  * mailbox handling or send any command to firmware, because
6492                  * any mailbox handling or command to firmware is only valid
6493                  * after hns3_cmd_init is called.
6494                  */
6495                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6496                 hw->reset.stats.request_cnt++;
6497                 break;
6498         case HNS3_IMP_RESET:
6499                 hns3_record_imp_error(hns);
6500                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6501                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6502                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6503                 break;
6504         default:
6505                 break;
6506         }
6507         return 0;
6508 }
6509
6510 static int
6511 hns3_set_rst_done(struct hns3_hw *hw)
6512 {
6513         struct hns3_pf_rst_done_cmd *req;
6514         struct hns3_cmd_desc desc;
6515
6516         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6518         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6519         return hns3_cmd_send(hw, &desc, 1);
6520 }
6521
6522 static int
6523 hns3_stop_service(struct hns3_adapter *hns)
6524 {
6525         struct hns3_hw *hw = &hns->hw;
6526         struct rte_eth_dev *eth_dev;
6527
6528         eth_dev = &rte_eth_devices[hw->data->port_id];
6529         hw->mac.link_status = ETH_LINK_DOWN;
6530         if (hw->adapter_state == HNS3_NIC_STARTED) {
6531                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6532                 hns3_update_linkstatus_and_event(hw, false);
6533         }
6534
6535         hns3_set_rxtx_function(eth_dev);
6536         rte_wmb();
6537         /* Disable datapath on secondary process. */
6538         hns3_mp_req_stop_rxtx(eth_dev);
6539         rte_delay_ms(hw->tqps_num);
6540
6541         rte_spinlock_lock(&hw->lock);
6542         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6543             hw->adapter_state == HNS3_NIC_STOPPING) {
6544                 hns3_enable_all_queues(hw, false);
6545                 hns3_do_stop(hns);
6546                 hw->reset.mbuf_deferred_free = true;
6547         } else
6548                 hw->reset.mbuf_deferred_free = false;
6549
6550         /*
6551          * It is cumbersome for hardware to pick-and-choose entries for deletion
6552          * from table space. Hence, for function reset software intervention is
6553          * required to delete the entries
6554          */
6555         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6556                 hns3_configure_all_mc_mac_addr(hns, true);
6557         rte_spinlock_unlock(&hw->lock);
6558
6559         return 0;
6560 }
6561
6562 static int
6563 hns3_start_service(struct hns3_adapter *hns)
6564 {
6565         struct hns3_hw *hw = &hns->hw;
6566         struct rte_eth_dev *eth_dev;
6567
6568         if (hw->reset.level == HNS3_IMP_RESET ||
6569             hw->reset.level == HNS3_GLOBAL_RESET)
6570                 hns3_set_rst_done(hw);
6571         eth_dev = &rte_eth_devices[hw->data->port_id];
6572         hns3_set_rxtx_function(eth_dev);
6573         hns3_mp_req_start_rxtx(eth_dev);
6574         if (hw->adapter_state == HNS3_NIC_STARTED) {
6575                 /*
6576                  * This API parent function already hold the hns3_hw.lock, the
6577                  * hns3_service_handler may report lse, in bonding application
6578                  * it will call driver's ops which may acquire the hns3_hw.lock
6579                  * again, thus lead to deadlock.
6580                  * We defer calls hns3_service_handler to avoid the deadlock.
6581                  */
6582                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6583                                   hns3_service_handler, eth_dev);
6584
6585                 /* Enable interrupt of all rx queues before enabling queues */
6586                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6587                 /*
6588                  * Enable state of each rxq and txq will be recovered after
6589                  * reset, so we need to restore them before enable all tqps;
6590                  */
6591                 hns3_restore_tqp_enable_state(hw);
6592                 /*
6593                  * When finished the initialization, enable queues to receive
6594                  * and transmit packets.
6595                  */
6596                 hns3_enable_all_queues(hw, true);
6597         }
6598
6599         return 0;
6600 }
6601
6602 static int
6603 hns3_restore_conf(struct hns3_adapter *hns)
6604 {
6605         struct hns3_hw *hw = &hns->hw;
6606         int ret;
6607
6608         ret = hns3_configure_all_mac_addr(hns, false);
6609         if (ret)
6610                 return ret;
6611
6612         ret = hns3_configure_all_mc_mac_addr(hns, false);
6613         if (ret)
6614                 goto err_mc_mac;
6615
6616         ret = hns3_dev_promisc_restore(hns);
6617         if (ret)
6618                 goto err_promisc;
6619
6620         ret = hns3_restore_vlan_table(hns);
6621         if (ret)
6622                 goto err_promisc;
6623
6624         ret = hns3_restore_vlan_conf(hns);
6625         if (ret)
6626                 goto err_promisc;
6627
6628         ret = hns3_restore_all_fdir_filter(hns);
6629         if (ret)
6630                 goto err_promisc;
6631
6632         ret = hns3_restore_ptp(hns);
6633         if (ret)
6634                 goto err_promisc;
6635
6636         ret = hns3_restore_rx_interrupt(hw);
6637         if (ret)
6638                 goto err_promisc;
6639
6640         ret = hns3_restore_gro_conf(hw);
6641         if (ret)
6642                 goto err_promisc;
6643
6644         ret = hns3_restore_fec(hw);
6645         if (ret)
6646                 goto err_promisc;
6647
6648         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6649                 ret = hns3_do_start(hns, false);
6650                 if (ret)
6651                         goto err_promisc;
6652                 hns3_info(hw, "hns3 dev restart successful!");
6653         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6654                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6655         return 0;
6656
6657 err_promisc:
6658         hns3_configure_all_mc_mac_addr(hns, true);
6659 err_mc_mac:
6660         hns3_configure_all_mac_addr(hns, true);
6661         return ret;
6662 }
6663
6664 static void
6665 hns3_reset_service(void *param)
6666 {
6667         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6668         struct hns3_hw *hw = &hns->hw;
6669         enum hns3_reset_level reset_level;
6670         struct timeval tv_delta;
6671         struct timeval tv_start;
6672         struct timeval tv;
6673         uint64_t msec;
6674         int ret;
6675
6676         /*
6677          * The interrupt is not triggered within the delay time.
6678          * The interrupt may have been lost. It is necessary to handle
6679          * the interrupt to recover from the error.
6680          */
6681         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6682                             SCHEDULE_DEFERRED) {
6683                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6684                                   __ATOMIC_RELAXED);
6685                 hns3_err(hw, "Handling interrupts in delayed tasks");
6686                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6687                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6688                 if (reset_level == HNS3_NONE_RESET) {
6689                         hns3_err(hw, "No reset level is set, try IMP reset");
6690                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6691                 }
6692         }
6693         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6694
6695         /*
6696          * Check if there is any ongoing reset in the hardware. This status can
6697          * be checked from reset_pending. If there is then, we need to wait for
6698          * hardware to complete reset.
6699          *    a. If we are able to figure out in reasonable time that hardware
6700          *       has fully resetted then, we can proceed with driver, client
6701          *       reset.
6702          *    b. else, we can come back later to check this status so re-sched
6703          *       now.
6704          */
6705         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6706         if (reset_level != HNS3_NONE_RESET) {
6707                 gettimeofday(&tv_start, NULL);
6708                 ret = hns3_reset_process(hns, reset_level);
6709                 gettimeofday(&tv, NULL);
6710                 timersub(&tv, &tv_start, &tv_delta);
6711                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6712                        tv_delta.tv_usec / USEC_PER_MSEC;
6713                 if (msec > HNS3_RESET_PROCESS_MS)
6714                         hns3_err(hw, "%d handle long time delta %" PRIx64
6715                                      " ms time=%ld.%.6ld",
6716                                  hw->reset.level, msec,
6717                                  tv.tv_sec, tv.tv_usec);
6718                 if (ret == -EAGAIN)
6719                         return;
6720         }
6721
6722         /* Check if we got any *new* reset requests to be honored */
6723         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6724         if (reset_level != HNS3_NONE_RESET)
6725                 hns3_msix_process(hns, reset_level);
6726 }
6727
6728 static unsigned int
6729 hns3_get_speed_capa_num(uint16_t device_id)
6730 {
6731         unsigned int num;
6732
6733         switch (device_id) {
6734         case HNS3_DEV_ID_25GE:
6735         case HNS3_DEV_ID_25GE_RDMA:
6736                 num = 2;
6737                 break;
6738         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6739         case HNS3_DEV_ID_200G_RDMA:
6740                 num = 1;
6741                 break;
6742         default:
6743                 num = 0;
6744                 break;
6745         }
6746
6747         return num;
6748 }
6749
6750 static int
6751 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6752                         uint16_t device_id)
6753 {
6754         switch (device_id) {
6755         case HNS3_DEV_ID_25GE:
6756         /* fallthrough */
6757         case HNS3_DEV_ID_25GE_RDMA:
6758                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6759                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6760
6761                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6762                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6763                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6764                 break;
6765         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6766                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6767                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6768                 break;
6769         case HNS3_DEV_ID_200G_RDMA:
6770                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6771                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6772                 break;
6773         default:
6774                 return -ENOTSUP;
6775         }
6776
6777         return 0;
6778 }
6779
6780 static int
6781 hns3_fec_get_capability(struct rte_eth_dev *dev,
6782                         struct rte_eth_fec_capa *speed_fec_capa,
6783                         unsigned int num)
6784 {
6785         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6787         uint16_t device_id = pci_dev->id.device_id;
6788         unsigned int capa_num;
6789         int ret;
6790
6791         capa_num = hns3_get_speed_capa_num(device_id);
6792         if (capa_num == 0) {
6793                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6794                          device_id);
6795                 return -ENOTSUP;
6796         }
6797
6798         if (speed_fec_capa == NULL || num < capa_num)
6799                 return capa_num;
6800
6801         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6802         if (ret)
6803                 return -ENOTSUP;
6804
6805         return capa_num;
6806 }
6807
6808 static int
6809 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6810 {
6811         struct hns3_config_fec_cmd *req;
6812         struct hns3_cmd_desc desc;
6813         int ret;
6814
6815         /*
6816          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6817          * in device of link speed
6818          * below 10 Gbps.
6819          */
6820         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6821                 *state = 0;
6822                 return 0;
6823         }
6824
6825         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6826         req = (struct hns3_config_fec_cmd *)desc.data;
6827         ret = hns3_cmd_send(hw, &desc, 1);
6828         if (ret) {
6829                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6830                          ret);
6831                 return ret;
6832         }
6833
6834         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6835         return 0;
6836 }
6837
6838 static int
6839 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6840 {
6841         struct hns3_sfp_info_cmd *resp;
6842         uint32_t tmp_fec_capa;
6843         uint8_t auto_state;
6844         struct hns3_cmd_desc desc;
6845         int ret;
6846
6847         /*
6848          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6849          * configured FEC mode is returned.
6850          * If link is up, current FEC mode is returned.
6851          */
6852         if (hw->mac.link_status == ETH_LINK_DOWN) {
6853                 ret = get_current_fec_auto_state(hw, &auto_state);
6854                 if (ret)
6855                         return ret;
6856
6857                 if (auto_state == 0x1) {
6858                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6859                         return 0;
6860                 }
6861         }
6862
6863         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6864         resp = (struct hns3_sfp_info_cmd *)desc.data;
6865         resp->query_type = HNS3_ACTIVE_QUERY;
6866
6867         ret = hns3_cmd_send(hw, &desc, 1);
6868         if (ret == -EOPNOTSUPP) {
6869                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6870                 return ret;
6871         } else if (ret) {
6872                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6873                 return ret;
6874         }
6875
6876         /*
6877          * FEC mode order defined in hns3 hardware is inconsistend with
6878          * that defined in the ethdev library. So the sequence needs
6879          * to be converted.
6880          */
6881         switch (resp->active_fec) {
6882         case HNS3_HW_FEC_MODE_NOFEC:
6883                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6884                 break;
6885         case HNS3_HW_FEC_MODE_BASER:
6886                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6887                 break;
6888         case HNS3_HW_FEC_MODE_RS:
6889                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6890                 break;
6891         default:
6892                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6893                 break;
6894         }
6895
6896         *fec_capa = tmp_fec_capa;
6897         return 0;
6898 }
6899
6900 static int
6901 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6902 {
6903         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6904
6905         return hns3_fec_get_internal(hw, fec_capa);
6906 }
6907
6908 static int
6909 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6910 {
6911         struct hns3_config_fec_cmd *req;
6912         struct hns3_cmd_desc desc;
6913         int ret;
6914
6915         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6916
6917         req = (struct hns3_config_fec_cmd *)desc.data;
6918         switch (mode) {
6919         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6920                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6921                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6922                 break;
6923         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6924                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6925                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6926                 break;
6927         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6928                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6929                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6930                 break;
6931         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6932                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6933                 break;
6934         default:
6935                 return 0;
6936         }
6937         ret = hns3_cmd_send(hw, &desc, 1);
6938         if (ret)
6939                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6940
6941         return ret;
6942 }
6943
6944 static uint32_t
6945 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6946 {
6947         struct hns3_mac *mac = &hw->mac;
6948         uint32_t cur_capa;
6949
6950         switch (mac->link_speed) {
6951         case ETH_SPEED_NUM_10G:
6952                 cur_capa = fec_capa[1].capa;
6953                 break;
6954         case ETH_SPEED_NUM_25G:
6955         case ETH_SPEED_NUM_100G:
6956         case ETH_SPEED_NUM_200G:
6957                 cur_capa = fec_capa[0].capa;
6958                 break;
6959         default:
6960                 cur_capa = 0;
6961                 break;
6962         }
6963
6964         return cur_capa;
6965 }
6966
6967 static bool
6968 is_fec_mode_one_bit_set(uint32_t mode)
6969 {
6970         int cnt = 0;
6971         uint8_t i;
6972
6973         for (i = 0; i < sizeof(mode); i++)
6974                 if (mode >> i & 0x1)
6975                         cnt++;
6976
6977         return cnt == 1 ? true : false;
6978 }
6979
6980 static int
6981 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6982 {
6983 #define FEC_CAPA_NUM 2
6984         struct hns3_adapter *hns = dev->data->dev_private;
6985         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6986         struct hns3_pf *pf = &hns->pf;
6987
6988         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6989         uint32_t cur_capa;
6990         uint32_t num = FEC_CAPA_NUM;
6991         int ret;
6992
6993         ret = hns3_fec_get_capability(dev, fec_capa, num);
6994         if (ret < 0)
6995                 return ret;
6996
6997         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6998         if (!is_fec_mode_one_bit_set(mode))
6999                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
7000                              "FEC mode should be only one bit set", mode);
7001
7002         /*
7003          * Check whether the configured mode is within the FEC capability.
7004          * If not, the configured mode will not be supported.
7005          */
7006         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
7007         if (!(cur_capa & mode)) {
7008                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
7009                 return -EINVAL;
7010         }
7011
7012         rte_spinlock_lock(&hw->lock);
7013         ret = hns3_set_fec_hw(hw, mode);
7014         if (ret) {
7015                 rte_spinlock_unlock(&hw->lock);
7016                 return ret;
7017         }
7018
7019         pf->fec_mode = mode;
7020         rte_spinlock_unlock(&hw->lock);
7021
7022         return 0;
7023 }
7024
7025 static int
7026 hns3_restore_fec(struct hns3_hw *hw)
7027 {
7028         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7029         struct hns3_pf *pf = &hns->pf;
7030         uint32_t mode = pf->fec_mode;
7031         int ret;
7032
7033         ret = hns3_set_fec_hw(hw, mode);
7034         if (ret)
7035                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7036                          mode, ret);
7037
7038         return ret;
7039 }
7040
7041 static int
7042 hns3_query_dev_fec_info(struct hns3_hw *hw)
7043 {
7044         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7045         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7046         int ret;
7047
7048         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7049         if (ret)
7050                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7051
7052         return ret;
7053 }
7054
7055 static bool
7056 hns3_optical_module_existed(struct hns3_hw *hw)
7057 {
7058         struct hns3_cmd_desc desc;
7059         bool existed;
7060         int ret;
7061
7062         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7063         ret = hns3_cmd_send(hw, &desc, 1);
7064         if (ret) {
7065                 hns3_err(hw,
7066                          "fail to get optical module exist state, ret = %d.\n",
7067                          ret);
7068                 return false;
7069         }
7070         existed = !!desc.data[0];
7071
7072         return existed;
7073 }
7074
7075 static int
7076 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7077                                 uint32_t len, uint8_t *data)
7078 {
7079 #define HNS3_SFP_INFO_CMD_NUM 6
7080 #define HNS3_SFP_INFO_MAX_LEN \
7081         (HNS3_SFP_INFO_BD0_LEN + \
7082         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7083         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7084         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7085         uint16_t read_len;
7086         uint16_t copy_len;
7087         int ret;
7088         int i;
7089
7090         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7091                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7092                                           true);
7093                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7094                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7095         }
7096
7097         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7098         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7099         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7100         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7101
7102         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7103         if (ret) {
7104                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7105                                 ret);
7106                 return ret;
7107         }
7108
7109         /* The data format in BD0 is different with the others. */
7110         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7111         memcpy(data, sfp_info_bd0->data, copy_len);
7112         read_len = copy_len;
7113
7114         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7115                 if (read_len >= len)
7116                         break;
7117
7118                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7119                 memcpy(data + read_len, desc[i].data, copy_len);
7120                 read_len += copy_len;
7121         }
7122
7123         return (int)read_len;
7124 }
7125
7126 static int
7127 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7128                        struct rte_dev_eeprom_info *info)
7129 {
7130         struct hns3_adapter *hns = dev->data->dev_private;
7131         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7132         uint32_t offset = info->offset;
7133         uint32_t len = info->length;
7134         uint8_t *data = info->data;
7135         uint32_t read_len = 0;
7136
7137         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7138                 return -ENOTSUP;
7139
7140         if (!hns3_optical_module_existed(hw)) {
7141                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7142                 return -EIO;
7143         }
7144
7145         while (read_len < len) {
7146                 int ret;
7147                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7148                                                   len - read_len,
7149                                                   data + read_len);
7150                 if (ret < 0)
7151                         return -EIO;
7152                 read_len += ret;
7153         }
7154
7155         return 0;
7156 }
7157
7158 static int
7159 hns3_get_module_info(struct rte_eth_dev *dev,
7160                      struct rte_eth_dev_module_info *modinfo)
7161 {
7162 #define HNS3_SFF8024_ID_SFP             0x03
7163 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7164 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7165 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7166 #define HNS3_SFF_8636_V1_3              0x03
7167         struct hns3_adapter *hns = dev->data->dev_private;
7168         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7169         struct rte_dev_eeprom_info info;
7170         struct hns3_sfp_type sfp_type;
7171         int ret;
7172
7173         memset(&sfp_type, 0, sizeof(sfp_type));
7174         memset(&info, 0, sizeof(info));
7175         info.data = (uint8_t *)&sfp_type;
7176         info.length = sizeof(sfp_type);
7177         ret = hns3_get_module_eeprom(dev, &info);
7178         if (ret)
7179                 return ret;
7180
7181         switch (sfp_type.type) {
7182         case HNS3_SFF8024_ID_SFP:
7183                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7184                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7185                 break;
7186         case HNS3_SFF8024_ID_QSFP_8438:
7187                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7188                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7189                 break;
7190         case HNS3_SFF8024_ID_QSFP_8436_8636:
7191                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7192                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7193                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7194                 } else {
7195                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7196                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7197                 }
7198                 break;
7199         case HNS3_SFF8024_ID_QSFP28_8636:
7200                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7201                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7202                 break;
7203         default:
7204                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7205                          sfp_type.type, sfp_type.ext_type);
7206                 return -EINVAL;
7207         }
7208
7209         return 0;
7210 }
7211
7212 static int
7213 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7214 {
7215         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7216
7217         RTE_SET_USED(key);
7218
7219         if (strcmp(value, "vec") == 0)
7220                 hint = HNS3_IO_FUNC_HINT_VEC;
7221         else if (strcmp(value, "sve") == 0)
7222                 hint = HNS3_IO_FUNC_HINT_SVE;
7223         else if (strcmp(value, "simple") == 0)
7224                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7225         else if (strcmp(value, "common") == 0)
7226                 hint = HNS3_IO_FUNC_HINT_COMMON;
7227
7228         /* If the hint is valid then update output parameters */
7229         if (hint != HNS3_IO_FUNC_HINT_NONE)
7230                 *(uint32_t *)extra_args = hint;
7231
7232         return 0;
7233 }
7234
7235 static const char *
7236 hns3_get_io_hint_func_name(uint32_t hint)
7237 {
7238         switch (hint) {
7239         case HNS3_IO_FUNC_HINT_VEC:
7240                 return "vec";
7241         case HNS3_IO_FUNC_HINT_SVE:
7242                 return "sve";
7243         case HNS3_IO_FUNC_HINT_SIMPLE:
7244                 return "simple";
7245         case HNS3_IO_FUNC_HINT_COMMON:
7246                 return "common";
7247         default:
7248                 return "none";
7249         }
7250 }
7251
7252 static int
7253 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7254 {
7255         uint64_t val;
7256
7257         RTE_SET_USED(key);
7258
7259         val = strtoull(value, NULL, 16);
7260         *(uint64_t *)extra_args = val;
7261
7262         return 0;
7263 }
7264
7265 void
7266 hns3_parse_devargs(struct rte_eth_dev *dev)
7267 {
7268         struct hns3_adapter *hns = dev->data->dev_private;
7269         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7270         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7271         struct hns3_hw *hw = &hns->hw;
7272         uint64_t dev_caps_mask = 0;
7273         struct rte_kvargs *kvlist;
7274
7275         if (dev->device->devargs == NULL)
7276                 return;
7277
7278         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7279         if (!kvlist)
7280                 return;
7281
7282         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7283                            &hns3_parse_io_hint_func, &rx_func_hint);
7284         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7285                            &hns3_parse_io_hint_func, &tx_func_hint);
7286         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7287                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7288         rte_kvargs_free(kvlist);
7289
7290         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7291                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7292                           hns3_get_io_hint_func_name(rx_func_hint));
7293         hns->rx_func_hint = rx_func_hint;
7294         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7295                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7296                           hns3_get_io_hint_func_name(tx_func_hint));
7297         hns->tx_func_hint = tx_func_hint;
7298
7299         if (dev_caps_mask != 0)
7300                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7301                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7302         hns->dev_caps_mask = dev_caps_mask;
7303 }
7304
7305 static const struct eth_dev_ops hns3_eth_dev_ops = {
7306         .dev_configure      = hns3_dev_configure,
7307         .dev_start          = hns3_dev_start,
7308         .dev_stop           = hns3_dev_stop,
7309         .dev_close          = hns3_dev_close,
7310         .promiscuous_enable = hns3_dev_promiscuous_enable,
7311         .promiscuous_disable = hns3_dev_promiscuous_disable,
7312         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7313         .allmulticast_disable = hns3_dev_allmulticast_disable,
7314         .mtu_set            = hns3_dev_mtu_set,
7315         .stats_get          = hns3_stats_get,
7316         .stats_reset        = hns3_stats_reset,
7317         .xstats_get         = hns3_dev_xstats_get,
7318         .xstats_get_names   = hns3_dev_xstats_get_names,
7319         .xstats_reset       = hns3_dev_xstats_reset,
7320         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7321         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7322         .dev_infos_get          = hns3_dev_infos_get,
7323         .fw_version_get         = hns3_fw_version_get,
7324         .rx_queue_setup         = hns3_rx_queue_setup,
7325         .tx_queue_setup         = hns3_tx_queue_setup,
7326         .rx_queue_release       = hns3_dev_rx_queue_release,
7327         .tx_queue_release       = hns3_dev_tx_queue_release,
7328         .rx_queue_start         = hns3_dev_rx_queue_start,
7329         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7330         .tx_queue_start         = hns3_dev_tx_queue_start,
7331         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7332         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7333         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7334         .rxq_info_get           = hns3_rxq_info_get,
7335         .txq_info_get           = hns3_txq_info_get,
7336         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7337         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7338         .flow_ctrl_get          = hns3_flow_ctrl_get,
7339         .flow_ctrl_set          = hns3_flow_ctrl_set,
7340         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7341         .mac_addr_add           = hns3_add_mac_addr,
7342         .mac_addr_remove        = hns3_remove_mac_addr,
7343         .mac_addr_set           = hns3_set_default_mac_addr,
7344         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7345         .link_update            = hns3_dev_link_update,
7346         .rss_hash_update        = hns3_dev_rss_hash_update,
7347         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7348         .reta_update            = hns3_dev_rss_reta_update,
7349         .reta_query             = hns3_dev_rss_reta_query,
7350         .flow_ops_get           = hns3_dev_flow_ops_get,
7351         .vlan_filter_set        = hns3_vlan_filter_set,
7352         .vlan_tpid_set          = hns3_vlan_tpid_set,
7353         .vlan_offload_set       = hns3_vlan_offload_set,
7354         .vlan_pvid_set          = hns3_vlan_pvid_set,
7355         .get_reg                = hns3_get_regs,
7356         .get_module_info        = hns3_get_module_info,
7357         .get_module_eeprom      = hns3_get_module_eeprom,
7358         .get_dcb_info           = hns3_get_dcb_info,
7359         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7360         .fec_get_capability     = hns3_fec_get_capability,
7361         .fec_get                = hns3_fec_get,
7362         .fec_set                = hns3_fec_set,
7363         .tm_ops_get             = hns3_tm_ops_get,
7364         .tx_done_cleanup        = hns3_tx_done_cleanup,
7365         .timesync_enable            = hns3_timesync_enable,
7366         .timesync_disable           = hns3_timesync_disable,
7367         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7368         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7369         .timesync_adjust_time       = hns3_timesync_adjust_time,
7370         .timesync_read_time         = hns3_timesync_read_time,
7371         .timesync_write_time        = hns3_timesync_write_time,
7372 };
7373
7374 static const struct hns3_reset_ops hns3_reset_ops = {
7375         .reset_service       = hns3_reset_service,
7376         .stop_service        = hns3_stop_service,
7377         .prepare_reset       = hns3_prepare_reset,
7378         .wait_hardware_ready = hns3_wait_hardware_ready,
7379         .reinit_dev          = hns3_reinit_dev,
7380         .restore_conf        = hns3_restore_conf,
7381         .start_service       = hns3_start_service,
7382 };
7383
7384 static int
7385 hns3_dev_init(struct rte_eth_dev *eth_dev)
7386 {
7387         struct hns3_adapter *hns = eth_dev->data->dev_private;
7388         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7389         struct rte_ether_addr *eth_addr;
7390         struct hns3_hw *hw = &hns->hw;
7391         int ret;
7392
7393         PMD_INIT_FUNC_TRACE();
7394
7395         eth_dev->process_private = (struct hns3_process_private *)
7396             rte_zmalloc_socket("hns3_filter_list",
7397                                sizeof(struct hns3_process_private),
7398                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7399         if (eth_dev->process_private == NULL) {
7400                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7401                 return -ENOMEM;
7402         }
7403
7404         hns3_flow_init(eth_dev);
7405
7406         hns3_set_rxtx_function(eth_dev);
7407         eth_dev->dev_ops = &hns3_eth_dev_ops;
7408         eth_dev->rx_queue_count = hns3_rx_queue_count;
7409         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7410                 ret = hns3_mp_init_secondary();
7411                 if (ret) {
7412                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7413                                      "process, ret = %d", ret);
7414                         goto err_mp_init_secondary;
7415                 }
7416
7417                 hw->secondary_cnt++;
7418                 return 0;
7419         }
7420
7421         ret = hns3_mp_init_primary();
7422         if (ret) {
7423                 PMD_INIT_LOG(ERR,
7424                              "Failed to init for primary process, ret = %d",
7425                              ret);
7426                 goto err_mp_init_primary;
7427         }
7428
7429         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7430         hns->is_vf = false;
7431         hw->data = eth_dev->data;
7432         hns3_parse_devargs(eth_dev);
7433
7434         /*
7435          * Set default max packet size according to the mtu
7436          * default vale in DPDK frame.
7437          */
7438         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7439
7440         ret = hns3_reset_init(hw);
7441         if (ret)
7442                 goto err_init_reset;
7443         hw->reset.ops = &hns3_reset_ops;
7444
7445         ret = hns3_init_pf(eth_dev);
7446         if (ret) {
7447                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7448                 goto err_init_pf;
7449         }
7450
7451         /* Allocate memory for storing MAC addresses */
7452         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7453                                                sizeof(struct rte_ether_addr) *
7454                                                HNS3_UC_MACADDR_NUM, 0);
7455         if (eth_dev->data->mac_addrs == NULL) {
7456                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7457                              "to store MAC addresses",
7458                              sizeof(struct rte_ether_addr) *
7459                              HNS3_UC_MACADDR_NUM);
7460                 ret = -ENOMEM;
7461                 goto err_rte_zmalloc;
7462         }
7463
7464         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7465         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7466                 rte_eth_random_addr(hw->mac.mac_addr);
7467                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7468                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7469                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7470                           "unicast address, using random MAC address %s",
7471                           mac_str);
7472         }
7473         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7474                             &eth_dev->data->mac_addrs[0]);
7475
7476         hw->adapter_state = HNS3_NIC_INITIALIZED;
7477
7478         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7479                             SCHEDULE_PENDING) {
7480                 hns3_err(hw, "Reschedule reset service after dev_init");
7481                 hns3_schedule_reset(hns);
7482         } else {
7483                 /* IMP will wait ready flag before reset */
7484                 hns3_notify_reset_ready(hw, false);
7485         }
7486
7487         hns3_info(hw, "hns3 dev initialization successful!");
7488         return 0;
7489
7490 err_rte_zmalloc:
7491         hns3_uninit_pf(eth_dev);
7492
7493 err_init_pf:
7494         rte_free(hw->reset.wait_data);
7495
7496 err_init_reset:
7497         hns3_mp_uninit_primary();
7498
7499 err_mp_init_primary:
7500 err_mp_init_secondary:
7501         eth_dev->dev_ops = NULL;
7502         eth_dev->rx_pkt_burst = NULL;
7503         eth_dev->rx_descriptor_status = NULL;
7504         eth_dev->tx_pkt_burst = NULL;
7505         eth_dev->tx_pkt_prepare = NULL;
7506         eth_dev->tx_descriptor_status = NULL;
7507         rte_free(eth_dev->process_private);
7508         eth_dev->process_private = NULL;
7509         return ret;
7510 }
7511
7512 static int
7513 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7514 {
7515         struct hns3_adapter *hns = eth_dev->data->dev_private;
7516         struct hns3_hw *hw = &hns->hw;
7517
7518         PMD_INIT_FUNC_TRACE();
7519
7520         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7521                 rte_free(eth_dev->process_private);
7522                 eth_dev->process_private = NULL;
7523                 return 0;
7524         }
7525
7526         if (hw->adapter_state < HNS3_NIC_CLOSING)
7527                 hns3_dev_close(eth_dev);
7528
7529         hw->adapter_state = HNS3_NIC_REMOVED;
7530         return 0;
7531 }
7532
7533 static int
7534 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7535                    struct rte_pci_device *pci_dev)
7536 {
7537         return rte_eth_dev_pci_generic_probe(pci_dev,
7538                                              sizeof(struct hns3_adapter),
7539                                              hns3_dev_init);
7540 }
7541
7542 static int
7543 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7544 {
7545         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7546 }
7547
7548 static const struct rte_pci_id pci_id_hns3_map[] = {
7549         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7550         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7551         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7552         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7553         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7554         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7555         { .vendor_id = 0, }, /* sentinel */
7556 };
7557
7558 static struct rte_pci_driver rte_hns3_pmd = {
7559         .id_table = pci_id_hns3_map,
7560         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7561         .probe = eth_hns3_pci_probe,
7562         .remove = eth_hns3_pci_remove,
7563 };
7564
7565 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7566 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7567 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7568 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7569                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7570                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7571                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7572 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7573 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);