1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVALID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
60 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
63 #define HNS3_RESET_WAIT_MS 100
64 #define HNS3_RESET_WAIT_CNT 200
66 /* FEC mode order defined in HNS3 hardware */
67 #define HNS3_HW_FEC_MODE_NOFEC 0
68 #define HNS3_HW_FEC_MODE_BASER 1
69 #define HNS3_HW_FEC_MODE_RS 2
72 HNS3_VECTOR0_EVENT_RST,
73 HNS3_VECTOR0_EVENT_MBX,
74 HNS3_VECTOR0_EVENT_ERR,
75 HNS3_VECTOR0_EVENT_OTHER,
78 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
79 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
81 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
83 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
84 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
85 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
88 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
89 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
90 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
92 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
93 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
94 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
95 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
97 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
98 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
99 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
101 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
102 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
103 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
106 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
108 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
109 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
111 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
113 static int hns3_add_mc_addr(struct hns3_hw *hw,
114 struct rte_ether_addr *mac_addr);
115 static int hns3_remove_mc_addr(struct hns3_hw *hw,
116 struct rte_ether_addr *mac_addr);
117 static int hns3_restore_fec(struct hns3_hw *hw);
118 static int hns3_query_dev_fec_info(struct rte_eth_dev *dev);
121 hns3_pf_disable_irq0(struct hns3_hw *hw)
123 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
127 hns3_pf_enable_irq0(struct hns3_hw *hw)
129 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
132 static enum hns3_evt_cause
133 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
135 struct hns3_hw *hw = &hns->hw;
136 uint32_t vector0_int_stats;
137 uint32_t cmdq_src_val;
138 uint32_t hw_err_src_reg;
140 enum hns3_evt_cause ret;
142 /* fetch the events from their corresponding regs */
143 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
144 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
145 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
148 * Assumption: If by any chance reset and mailbox events are reported
149 * together then we will only process reset event and defer the
150 * processing of the mailbox events. Since, we would have not cleared
151 * RX CMDQ event this time we would receive again another interrupt
152 * from H/W just for the mailbox.
154 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
155 rte_atomic16_set(&hw->reset.disable_cmd, 1);
156 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
157 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
159 hw->reset.stats.imp_cnt++;
160 hns3_warn(hw, "IMP reset detected, clear reset status");
162 hns3_schedule_delayed_reset(hns);
163 hns3_warn(hw, "IMP reset detected, don't clear reset status");
166 ret = HNS3_VECTOR0_EVENT_RST;
171 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
172 rte_atomic16_set(&hw->reset.disable_cmd, 1);
173 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
174 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
176 hw->reset.stats.global_cnt++;
177 hns3_warn(hw, "Global reset detected, clear reset status");
179 hns3_schedule_delayed_reset(hns);
180 hns3_warn(hw, "Global reset detected, don't clear reset status");
183 ret = HNS3_VECTOR0_EVENT_RST;
187 /* check for vector0 msix event source */
188 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
189 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
190 val = vector0_int_stats | hw_err_src_reg;
191 ret = HNS3_VECTOR0_EVENT_ERR;
195 /* check for vector0 mailbox(=CMDQ RX) event source */
196 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
197 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
199 ret = HNS3_VECTOR0_EVENT_MBX;
203 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
204 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
205 vector0_int_stats, cmdq_src_val, hw_err_src_reg);
206 val = vector0_int_stats;
207 ret = HNS3_VECTOR0_EVENT_OTHER;
216 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
218 if (event_type == HNS3_VECTOR0_EVENT_RST)
219 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
220 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
221 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
225 hns3_clear_all_event_cause(struct hns3_hw *hw)
227 uint32_t vector0_int_stats;
228 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
230 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
231 hns3_warn(hw, "Probe during IMP reset interrupt");
233 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
234 hns3_warn(hw, "Probe during Global reset interrupt");
236 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
237 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
238 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
239 BIT(HNS3_VECTOR0_CORERESET_INT_B));
240 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
244 hns3_interrupt_handler(void *param)
246 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
247 struct hns3_adapter *hns = dev->data->dev_private;
248 struct hns3_hw *hw = &hns->hw;
249 enum hns3_evt_cause event_cause;
250 uint32_t clearval = 0;
252 /* Disable interrupt */
253 hns3_pf_disable_irq0(hw);
255 event_cause = hns3_check_event_cause(hns, &clearval);
257 /* vector 0 interrupt is shared with reset and mailbox source events. */
258 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
259 hns3_warn(hw, "Received err interrupt");
260 hns3_handle_msix_error(hns, &hw->reset.request);
261 hns3_handle_ras_error(hns, &hw->reset.request);
262 hns3_schedule_reset(hns);
263 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
264 hns3_warn(hw, "Received reset interrupt");
265 hns3_schedule_reset(hns);
266 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
267 hns3_dev_handle_mbx_msg(hw);
269 hns3_err(hw, "Received unknown event");
271 hns3_clear_event_cause(hw, event_cause, clearval);
272 /* Enable interrupt if it is not cause by reset */
273 hns3_pf_enable_irq0(hw);
277 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
279 #define HNS3_VLAN_ID_OFFSET_STEP 160
280 #define HNS3_VLAN_BYTE_SIZE 8
281 struct hns3_vlan_filter_pf_cfg_cmd *req;
282 struct hns3_hw *hw = &hns->hw;
283 uint8_t vlan_offset_byte_val;
284 struct hns3_cmd_desc desc;
285 uint8_t vlan_offset_byte;
286 uint8_t vlan_offset_base;
289 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
291 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
292 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
294 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
296 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
297 req->vlan_offset = vlan_offset_base;
298 req->vlan_cfg = on ? 0 : 1;
299 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
301 ret = hns3_cmd_send(hw, &desc, 1);
303 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
310 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
312 struct hns3_user_vlan_table *vlan_entry;
313 struct hns3_pf *pf = &hns->pf;
315 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
316 if (vlan_entry->vlan_id == vlan_id) {
317 if (vlan_entry->hd_tbl_status)
318 hns3_set_port_vlan_filter(hns, vlan_id, 0);
319 LIST_REMOVE(vlan_entry, next);
320 rte_free(vlan_entry);
327 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
330 struct hns3_user_vlan_table *vlan_entry;
331 struct hns3_hw *hw = &hns->hw;
332 struct hns3_pf *pf = &hns->pf;
334 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
335 if (vlan_entry->vlan_id == vlan_id)
339 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
340 if (vlan_entry == NULL) {
341 hns3_err(hw, "Failed to malloc hns3 vlan table");
345 vlan_entry->hd_tbl_status = writen_to_tbl;
346 vlan_entry->vlan_id = vlan_id;
348 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
352 hns3_restore_vlan_table(struct hns3_adapter *hns)
354 struct hns3_user_vlan_table *vlan_entry;
355 struct hns3_hw *hw = &hns->hw;
356 struct hns3_pf *pf = &hns->pf;
360 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
361 return hns3_vlan_pvid_configure(hns,
362 hw->port_base_vlan_cfg.pvid, 1);
364 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
365 if (vlan_entry->hd_tbl_status) {
366 vlan_id = vlan_entry->vlan_id;
367 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
377 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
379 struct hns3_hw *hw = &hns->hw;
380 bool writen_to_tbl = false;
384 * When vlan filter is enabled, hardware regards packets without vlan
385 * as packets with vlan 0. So, to receive packets without vlan, vlan id
386 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
388 if (on == 0 && vlan_id == 0)
392 * When port base vlan enabled, we use port base vlan as the vlan
393 * filter condition. In this case, we don't update vlan filter table
394 * when user add new vlan or remove exist vlan, just update the
395 * vlan list. The vlan id in vlan list will be writen in vlan filter
396 * table until port base vlan disabled
398 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
399 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
400 writen_to_tbl = true;
405 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
407 hns3_rm_dev_vlan_table(hns, vlan_id);
413 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
415 struct hns3_adapter *hns = dev->data->dev_private;
416 struct hns3_hw *hw = &hns->hw;
419 rte_spinlock_lock(&hw->lock);
420 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
421 rte_spinlock_unlock(&hw->lock);
426 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
429 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
430 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
431 struct hns3_hw *hw = &hns->hw;
432 struct hns3_cmd_desc desc;
435 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
436 vlan_type != ETH_VLAN_TYPE_OUTER)) {
437 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
441 if (tpid != RTE_ETHER_TYPE_VLAN) {
442 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
446 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
447 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
449 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
450 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
451 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
452 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
453 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
454 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
455 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
456 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
459 ret = hns3_cmd_send(hw, &desc, 1);
461 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
466 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
468 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
469 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
470 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
472 ret = hns3_cmd_send(hw, &desc, 1);
474 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
480 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
483 struct hns3_adapter *hns = dev->data->dev_private;
484 struct hns3_hw *hw = &hns->hw;
487 rte_spinlock_lock(&hw->lock);
488 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
489 rte_spinlock_unlock(&hw->lock);
494 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
495 struct hns3_rx_vtag_cfg *vcfg)
497 struct hns3_vport_vtag_rx_cfg_cmd *req;
498 struct hns3_hw *hw = &hns->hw;
499 struct hns3_cmd_desc desc;
504 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
506 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
507 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
508 vcfg->strip_tag1_en ? 1 : 0);
509 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
510 vcfg->strip_tag2_en ? 1 : 0);
511 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
512 vcfg->vlan1_vlan_prionly ? 1 : 0);
513 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
514 vcfg->vlan2_vlan_prionly ? 1 : 0);
516 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
517 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
518 vcfg->strip_tag1_discard_en ? 1 : 0);
519 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
520 vcfg->strip_tag2_discard_en ? 1 : 0);
522 * In current version VF is not supported when PF is driven by DPDK
523 * driver, just need to configure parameters for PF vport.
525 vport_id = HNS3_PF_FUNC_ID;
526 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
527 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
528 req->vf_bitmap[req->vf_offset] = bitmap;
530 ret = hns3_cmd_send(hw, &desc, 1);
532 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
537 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
538 struct hns3_rx_vtag_cfg *vcfg)
540 struct hns3_pf *pf = &hns->pf;
541 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
545 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
546 struct hns3_tx_vtag_cfg *vcfg)
548 struct hns3_pf *pf = &hns->pf;
549 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
553 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
555 struct hns3_rx_vtag_cfg rxvlan_cfg;
556 struct hns3_hw *hw = &hns->hw;
559 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
560 rxvlan_cfg.strip_tag1_en = false;
561 rxvlan_cfg.strip_tag2_en = enable;
562 rxvlan_cfg.strip_tag2_discard_en = false;
564 rxvlan_cfg.strip_tag1_en = enable;
565 rxvlan_cfg.strip_tag2_en = true;
566 rxvlan_cfg.strip_tag2_discard_en = true;
569 rxvlan_cfg.strip_tag1_discard_en = false;
570 rxvlan_cfg.vlan1_vlan_prionly = false;
571 rxvlan_cfg.vlan2_vlan_prionly = false;
572 rxvlan_cfg.rx_vlan_offload_en = enable;
574 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
576 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
580 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
586 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
587 uint8_t fe_type, bool filter_en, uint8_t vf_id)
589 struct hns3_vlan_filter_ctrl_cmd *req;
590 struct hns3_cmd_desc desc;
593 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
595 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
596 req->vlan_type = vlan_type;
597 req->vlan_fe = filter_en ? fe_type : 0;
600 ret = hns3_cmd_send(hw, &desc, 1);
602 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
608 hns3_vlan_filter_init(struct hns3_adapter *hns)
610 struct hns3_hw *hw = &hns->hw;
613 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
614 HNS3_FILTER_FE_EGRESS, false,
617 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
621 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
622 HNS3_FILTER_FE_INGRESS, false,
625 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
631 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
633 struct hns3_hw *hw = &hns->hw;
636 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
637 HNS3_FILTER_FE_INGRESS, enable,
640 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
641 enable ? "enable" : "disable", ret);
647 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
649 struct hns3_adapter *hns = dev->data->dev_private;
650 struct hns3_hw *hw = &hns->hw;
651 struct rte_eth_rxmode *rxmode;
652 unsigned int tmp_mask;
656 rte_spinlock_lock(&hw->lock);
657 rxmode = &dev->data->dev_conf.rxmode;
658 tmp_mask = (unsigned int)mask;
659 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
660 /* ignore vlan filter configuration during promiscuous mode */
661 if (!dev->data->promiscuous) {
662 /* Enable or disable VLAN filter */
663 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
666 ret = hns3_enable_vlan_filter(hns, enable);
668 rte_spinlock_unlock(&hw->lock);
669 hns3_err(hw, "failed to %s rx filter, ret = %d",
670 enable ? "enable" : "disable", ret);
676 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
677 /* Enable or disable VLAN stripping */
678 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
681 ret = hns3_en_hw_strip_rxvtag(hns, enable);
683 rte_spinlock_unlock(&hw->lock);
684 hns3_err(hw, "failed to %s rx strip, ret = %d",
685 enable ? "enable" : "disable", ret);
690 rte_spinlock_unlock(&hw->lock);
696 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
697 struct hns3_tx_vtag_cfg *vcfg)
699 struct hns3_vport_vtag_tx_cfg_cmd *req;
700 struct hns3_cmd_desc desc;
701 struct hns3_hw *hw = &hns->hw;
706 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
708 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
709 req->def_vlan_tag1 = vcfg->default_tag1;
710 req->def_vlan_tag2 = vcfg->default_tag2;
711 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
712 vcfg->accept_tag1 ? 1 : 0);
713 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
714 vcfg->accept_untag1 ? 1 : 0);
715 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
716 vcfg->accept_tag2 ? 1 : 0);
717 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
718 vcfg->accept_untag2 ? 1 : 0);
719 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
720 vcfg->insert_tag1_en ? 1 : 0);
721 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
722 vcfg->insert_tag2_en ? 1 : 0);
723 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
725 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
726 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
727 vcfg->tag_shift_mode_en ? 1 : 0);
730 * In current version VF is not supported when PF is driven by DPDK
731 * driver, just need to configure parameters for PF vport.
733 vport_id = HNS3_PF_FUNC_ID;
734 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
735 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
736 req->vf_bitmap[req->vf_offset] = bitmap;
738 ret = hns3_cmd_send(hw, &desc, 1);
740 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
746 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
749 struct hns3_hw *hw = &hns->hw;
750 struct hns3_tx_vtag_cfg txvlan_cfg;
753 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
754 txvlan_cfg.accept_tag1 = true;
755 txvlan_cfg.insert_tag1_en = false;
756 txvlan_cfg.default_tag1 = 0;
758 txvlan_cfg.accept_tag1 =
759 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
760 txvlan_cfg.insert_tag1_en = true;
761 txvlan_cfg.default_tag1 = pvid;
764 txvlan_cfg.accept_untag1 = true;
765 txvlan_cfg.accept_tag2 = true;
766 txvlan_cfg.accept_untag2 = true;
767 txvlan_cfg.insert_tag2_en = false;
768 txvlan_cfg.default_tag2 = 0;
769 txvlan_cfg.tag_shift_mode_en = true;
771 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
773 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
778 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
784 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
786 struct hns3_user_vlan_table *vlan_entry;
787 struct hns3_pf *pf = &hns->pf;
789 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
790 if (vlan_entry->hd_tbl_status) {
791 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
792 vlan_entry->hd_tbl_status = false;
797 vlan_entry = LIST_FIRST(&pf->vlan_list);
799 LIST_REMOVE(vlan_entry, next);
800 rte_free(vlan_entry);
801 vlan_entry = LIST_FIRST(&pf->vlan_list);
807 hns3_add_all_vlan_table(struct hns3_adapter *hns)
809 struct hns3_user_vlan_table *vlan_entry;
810 struct hns3_pf *pf = &hns->pf;
812 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
813 if (!vlan_entry->hd_tbl_status) {
814 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
815 vlan_entry->hd_tbl_status = true;
821 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
823 struct hns3_hw *hw = &hns->hw;
826 hns3_rm_all_vlan_table(hns, true);
827 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
828 ret = hns3_set_port_vlan_filter(hns,
829 hw->port_base_vlan_cfg.pvid, 0);
831 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
839 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
840 uint16_t port_base_vlan_state, uint16_t new_pvid)
842 struct hns3_hw *hw = &hns->hw;
846 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
847 old_pvid = hw->port_base_vlan_cfg.pvid;
848 if (old_pvid != HNS3_INVALID_PVID) {
849 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
851 hns3_err(hw, "failed to remove old pvid %u, "
852 "ret = %d", old_pvid, ret);
857 hns3_rm_all_vlan_table(hns, false);
858 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
860 hns3_err(hw, "failed to add new pvid %u, ret = %d",
865 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
867 hns3_err(hw, "failed to remove pvid %u, ret = %d",
872 hns3_add_all_vlan_table(hns);
878 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
880 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
881 struct hns3_rx_vtag_cfg rx_vlan_cfg;
885 rx_strip_en = old_cfg->rx_vlan_offload_en;
887 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
888 rx_vlan_cfg.strip_tag2_en = true;
889 rx_vlan_cfg.strip_tag2_discard_en = true;
891 rx_vlan_cfg.strip_tag1_en = false;
892 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
893 rx_vlan_cfg.strip_tag2_discard_en = false;
895 rx_vlan_cfg.strip_tag1_discard_en = false;
896 rx_vlan_cfg.vlan1_vlan_prionly = false;
897 rx_vlan_cfg.vlan2_vlan_prionly = false;
898 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
900 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
904 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
909 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
911 struct hns3_hw *hw = &hns->hw;
912 uint16_t port_base_vlan_state;
915 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
916 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
917 hns3_warn(hw, "Invalid operation! As current pvid set "
918 "is %u, disable pvid %u is invalid",
919 hw->port_base_vlan_cfg.pvid, pvid);
923 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
924 HNS3_PORT_BASE_VLAN_DISABLE;
925 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
927 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
932 ret = hns3_en_pvid_strip(hns, on);
934 hns3_err(hw, "failed to config rx vlan strip for pvid, "
939 if (pvid == HNS3_INVALID_PVID)
941 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
943 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
949 hw->port_base_vlan_cfg.state = port_base_vlan_state;
950 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
955 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
957 struct hns3_adapter *hns = dev->data->dev_private;
958 struct hns3_hw *hw = &hns->hw;
959 bool pvid_en_state_change;
963 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
964 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
965 RTE_ETHER_MAX_VLAN_ID);
970 * If PVID configuration state change, should refresh the PVID
971 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
973 pvid_state = hw->port_base_vlan_cfg.state;
974 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
975 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
976 pvid_en_state_change = false;
978 pvid_en_state_change = true;
980 rte_spinlock_lock(&hw->lock);
981 ret = hns3_vlan_pvid_configure(hns, pvid, on);
982 rte_spinlock_unlock(&hw->lock);
986 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
987 * need be processed by PMD driver.
989 if (pvid_en_state_change &&
990 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
991 hns3_update_all_queues_pvid_proc_en(hw);
997 hns3_default_vlan_config(struct hns3_adapter *hns)
999 struct hns3_hw *hw = &hns->hw;
1003 * When vlan filter is enabled, hardware regards packets without vlan
1004 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1005 * table, packets without vlan won't be received. So, add vlan 0 as
1008 ret = hns3_vlan_filter_configure(hns, 0, 1);
1010 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1015 hns3_init_vlan_config(struct hns3_adapter *hns)
1017 struct hns3_hw *hw = &hns->hw;
1021 * This function can be called in the initialization and reset process,
1022 * when in reset process, it means that hardware had been reseted
1023 * successfully and we need to restore the hardware configuration to
1024 * ensure that the hardware configuration remains unchanged before and
1027 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1028 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1029 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1032 ret = hns3_vlan_filter_init(hns);
1034 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1038 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1039 RTE_ETHER_TYPE_VLAN);
1041 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1046 * When in the reinit dev stage of the reset process, the following
1047 * vlan-related configurations may differ from those at initialization,
1048 * we will restore configurations to hardware in hns3_restore_vlan_table
1049 * and hns3_restore_vlan_conf later.
1051 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1052 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1054 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1058 ret = hns3_en_hw_strip_rxvtag(hns, false);
1060 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1066 return hns3_default_vlan_config(hns);
1070 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1072 struct hns3_pf *pf = &hns->pf;
1073 struct hns3_hw *hw = &hns->hw;
1078 if (!hw->data->promiscuous) {
1079 /* restore vlan filter states */
1080 offloads = hw->data->dev_conf.rxmode.offloads;
1081 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1082 ret = hns3_enable_vlan_filter(hns, enable);
1084 hns3_err(hw, "failed to restore vlan rx filter conf, "
1090 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1092 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1096 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1098 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1104 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1106 struct hns3_adapter *hns = dev->data->dev_private;
1107 struct rte_eth_dev_data *data = dev->data;
1108 struct rte_eth_txmode *txmode;
1109 struct hns3_hw *hw = &hns->hw;
1113 txmode = &data->dev_conf.txmode;
1114 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1116 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1117 "configuration is not supported! Ignore these two "
1118 "parameters: hw_vlan_reject_tagged(%d), "
1119 "hw_vlan_reject_untagged(%d)",
1120 txmode->hw_vlan_reject_tagged,
1121 txmode->hw_vlan_reject_untagged);
1123 /* Apply vlan offload setting */
1124 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1125 ret = hns3_vlan_offload_set(dev, mask);
1127 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1133 * If pvid config is not set in rte_eth_conf, driver needn't to set
1134 * VLAN pvid related configuration to hardware.
1136 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1139 /* Apply pvid setting */
1140 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1141 txmode->hw_vlan_insert_pvid);
1143 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1150 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1151 unsigned int tso_mss_max)
1153 struct hns3_cfg_tso_status_cmd *req;
1154 struct hns3_cmd_desc desc;
1157 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1159 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1162 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1164 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1167 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1169 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1171 return hns3_cmd_send(hw, &desc, 1);
1175 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1176 uint16_t *allocated_size, bool is_alloc)
1178 struct hns3_umv_spc_alc_cmd *req;
1179 struct hns3_cmd_desc desc;
1182 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1183 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1184 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1185 req->space_size = rte_cpu_to_le_32(space_size);
1187 ret = hns3_cmd_send(hw, &desc, 1);
1189 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1190 is_alloc ? "allocate" : "free", ret);
1194 if (is_alloc && allocated_size)
1195 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1201 hns3_init_umv_space(struct hns3_hw *hw)
1203 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1204 struct hns3_pf *pf = &hns->pf;
1205 uint16_t allocated_size = 0;
1208 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1213 if (allocated_size < pf->wanted_umv_size)
1214 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1215 pf->wanted_umv_size, allocated_size);
1217 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1218 pf->wanted_umv_size;
1219 pf->used_umv_size = 0;
1224 hns3_uninit_umv_space(struct hns3_hw *hw)
1226 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1227 struct hns3_pf *pf = &hns->pf;
1230 if (pf->max_umv_size == 0)
1233 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1237 pf->max_umv_size = 0;
1243 hns3_is_umv_space_full(struct hns3_hw *hw)
1245 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1246 struct hns3_pf *pf = &hns->pf;
1249 is_full = (pf->used_umv_size >= pf->max_umv_size);
1255 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1257 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1258 struct hns3_pf *pf = &hns->pf;
1261 if (pf->used_umv_size > 0)
1262 pf->used_umv_size--;
1264 pf->used_umv_size++;
1268 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1269 const uint8_t *addr, bool is_mc)
1271 const unsigned char *mac_addr = addr;
1272 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1273 ((uint32_t)mac_addr[2] << 16) |
1274 ((uint32_t)mac_addr[1] << 8) |
1275 (uint32_t)mac_addr[0];
1276 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1278 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1280 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1281 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1282 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1285 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1286 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1290 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1292 enum hns3_mac_vlan_tbl_opcode op)
1295 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1300 if (op == HNS3_MAC_VLAN_ADD) {
1301 if (resp_code == 0 || resp_code == 1) {
1303 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1304 hns3_err(hw, "add mac addr failed for uc_overflow");
1306 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1307 hns3_err(hw, "add mac addr failed for mc_overflow");
1311 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1314 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1315 if (resp_code == 0) {
1317 } else if (resp_code == 1) {
1318 hns3_dbg(hw, "remove mac addr failed for miss");
1322 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1325 } else if (op == HNS3_MAC_VLAN_LKUP) {
1326 if (resp_code == 0) {
1328 } else if (resp_code == 1) {
1329 hns3_dbg(hw, "lookup mac addr failed for miss");
1333 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1338 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1345 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1346 struct hns3_mac_vlan_tbl_entry_cmd *req,
1347 struct hns3_cmd_desc *desc, bool is_mc)
1353 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1355 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1356 memcpy(desc[0].data, req,
1357 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1358 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1360 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1361 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1363 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1365 memcpy(desc[0].data, req,
1366 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1367 ret = hns3_cmd_send(hw, desc, 1);
1370 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1374 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1375 retval = rte_le_to_cpu_16(desc[0].retval);
1377 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1378 HNS3_MAC_VLAN_LKUP);
1382 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1383 struct hns3_mac_vlan_tbl_entry_cmd *req,
1384 struct hns3_cmd_desc *mc_desc)
1391 if (mc_desc == NULL) {
1392 struct hns3_cmd_desc desc;
1394 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1395 memcpy(desc.data, req,
1396 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1397 ret = hns3_cmd_send(hw, &desc, 1);
1398 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1399 retval = rte_le_to_cpu_16(desc.retval);
1401 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1404 hns3_cmd_reuse_desc(&mc_desc[0], false);
1405 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1406 hns3_cmd_reuse_desc(&mc_desc[1], false);
1407 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1408 hns3_cmd_reuse_desc(&mc_desc[2], false);
1409 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1410 memcpy(mc_desc[0].data, req,
1411 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412 mc_desc[0].retval = 0;
1413 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1414 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1415 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1417 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1422 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1430 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1431 struct hns3_mac_vlan_tbl_entry_cmd *req)
1433 struct hns3_cmd_desc desc;
1438 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1440 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1442 ret = hns3_cmd_send(hw, &desc, 1);
1444 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1447 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1448 retval = rte_le_to_cpu_16(desc.retval);
1450 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1451 HNS3_MAC_VLAN_REMOVE);
1455 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1457 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1458 struct hns3_mac_vlan_tbl_entry_cmd req;
1459 struct hns3_pf *pf = &hns->pf;
1460 struct hns3_cmd_desc desc[3];
1461 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1462 uint16_t egress_port = 0;
1466 /* check if mac addr is valid */
1467 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1468 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1470 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1475 memset(&req, 0, sizeof(req));
1478 * In current version VF is not supported when PF is driven by DPDK
1479 * driver, just need to configure parameters for PF vport.
1481 vf_id = HNS3_PF_FUNC_ID;
1482 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1483 HNS3_MAC_EPORT_VFID_S, vf_id);
1485 req.egress_port = rte_cpu_to_le_16(egress_port);
1487 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1490 * Lookup the mac address in the mac_vlan table, and add
1491 * it if the entry is inexistent. Repeated unicast entry
1492 * is not allowed in the mac vlan table.
1494 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1495 if (ret == -ENOENT) {
1496 if (!hns3_is_umv_space_full(hw)) {
1497 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1499 hns3_update_umv_space(hw, false);
1503 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1508 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1510 /* check if we just hit the duplicate */
1512 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1516 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1523 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1525 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1526 struct rte_ether_addr *addr;
1530 for (i = 0; i < hw->mc_addrs_num; i++) {
1531 addr = &hw->mc_addrs[i];
1532 /* Check if there are duplicate addresses */
1533 if (rte_is_same_ether_addr(addr, mac_addr)) {
1534 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1536 hns3_err(hw, "failed to add mc mac addr, same addrs"
1537 "(%s) is added by the set_mc_mac_addr_list "
1543 ret = hns3_add_mc_addr(hw, mac_addr);
1545 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1547 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1554 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1556 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1559 ret = hns3_remove_mc_addr(hw, mac_addr);
1561 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1563 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1570 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1571 uint32_t idx, __rte_unused uint32_t pool)
1573 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1577 rte_spinlock_lock(&hw->lock);
1580 * In hns3 network engine adding UC and MC mac address with different
1581 * commands with firmware. We need to determine whether the input
1582 * address is a UC or a MC address to call different commands.
1583 * By the way, it is recommended calling the API function named
1584 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1585 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1586 * may affect the specifications of UC mac addresses.
1588 if (rte_is_multicast_ether_addr(mac_addr))
1589 ret = hns3_add_mc_addr_common(hw, mac_addr);
1591 ret = hns3_add_uc_addr_common(hw, mac_addr);
1594 rte_spinlock_unlock(&hw->lock);
1595 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1597 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1603 hw->mac.default_addr_setted = true;
1604 rte_spinlock_unlock(&hw->lock);
1610 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1612 struct hns3_mac_vlan_tbl_entry_cmd req;
1613 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1616 /* check if mac addr is valid */
1617 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1618 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1625 memset(&req, 0, sizeof(req));
1626 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1627 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1628 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1629 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1632 hns3_update_umv_space(hw, true);
1638 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1640 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641 /* index will be checked by upper level rte interface */
1642 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1643 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1646 rte_spinlock_lock(&hw->lock);
1648 if (rte_is_multicast_ether_addr(mac_addr))
1649 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1651 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1652 rte_spinlock_unlock(&hw->lock);
1654 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1656 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1662 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1663 struct rte_ether_addr *mac_addr)
1665 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666 struct rte_ether_addr *oaddr;
1667 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1668 bool default_addr_setted;
1669 bool rm_succes = false;
1673 * It has been guaranteed that input parameter named mac_addr is valid
1674 * address in the rte layer of DPDK framework.
1676 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1677 default_addr_setted = hw->mac.default_addr_setted;
1678 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1681 rte_spinlock_lock(&hw->lock);
1682 if (default_addr_setted) {
1683 ret = hns3_remove_uc_addr_common(hw, oaddr);
1685 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1687 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1694 ret = hns3_add_uc_addr_common(hw, mac_addr);
1696 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1698 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1699 goto err_add_uc_addr;
1702 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1704 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1705 goto err_pause_addr_cfg;
1708 rte_ether_addr_copy(mac_addr,
1709 (struct rte_ether_addr *)hw->mac.mac_addr);
1710 hw->mac.default_addr_setted = true;
1711 rte_spinlock_unlock(&hw->lock);
1716 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1718 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1721 "Failed to roll back to del setted mac addr(%s): %d",
1727 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1729 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1732 "Failed to restore old uc mac addr(%s): %d",
1734 hw->mac.default_addr_setted = false;
1737 rte_spinlock_unlock(&hw->lock);
1743 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1745 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1746 struct hns3_hw *hw = &hns->hw;
1747 struct rte_ether_addr *addr;
1752 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1753 addr = &hw->data->mac_addrs[i];
1754 if (rte_is_zero_ether_addr(addr))
1756 if (rte_is_multicast_ether_addr(addr))
1757 ret = del ? hns3_remove_mc_addr(hw, addr) :
1758 hns3_add_mc_addr(hw, addr);
1760 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1761 hns3_add_uc_addr_common(hw, addr);
1765 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1767 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1768 "ret = %d.", del ? "remove" : "restore",
1776 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1778 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1782 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1783 word_num = vfid / 32;
1784 bit_num = vfid % 32;
1786 desc[1].data[word_num] &=
1787 rte_cpu_to_le_32(~(1UL << bit_num));
1789 desc[1].data[word_num] |=
1790 rte_cpu_to_le_32(1UL << bit_num);
1792 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1793 bit_num = vfid % 32;
1795 desc[2].data[word_num] &=
1796 rte_cpu_to_le_32(~(1UL << bit_num));
1798 desc[2].data[word_num] |=
1799 rte_cpu_to_le_32(1UL << bit_num);
1804 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1806 struct hns3_mac_vlan_tbl_entry_cmd req;
1807 struct hns3_cmd_desc desc[3];
1808 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1812 /* Check if mac addr is valid */
1813 if (!rte_is_multicast_ether_addr(mac_addr)) {
1814 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1816 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1821 memset(&req, 0, sizeof(req));
1822 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1823 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1824 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1826 /* This mac addr do not exist, add new entry for it */
1827 memset(desc[0].data, 0, sizeof(desc[0].data));
1828 memset(desc[1].data, 0, sizeof(desc[0].data));
1829 memset(desc[2].data, 0, sizeof(desc[0].data));
1833 * In current version VF is not supported when PF is driven by DPDK
1834 * driver, just need to configure parameters for PF vport.
1836 vf_id = HNS3_PF_FUNC_ID;
1837 hns3_update_desc_vfid(desc, vf_id, false);
1838 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1841 hns3_err(hw, "mc mac vlan table is full");
1842 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1844 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1851 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1853 struct hns3_mac_vlan_tbl_entry_cmd req;
1854 struct hns3_cmd_desc desc[3];
1855 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1859 /* Check if mac addr is valid */
1860 if (!rte_is_multicast_ether_addr(mac_addr)) {
1861 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1863 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1868 memset(&req, 0, sizeof(req));
1869 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1870 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1871 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1874 * This mac addr exist, remove this handle's VFID for it.
1875 * In current version VF is not supported when PF is driven by
1876 * DPDK driver, just need to configure parameters for PF vport.
1878 vf_id = HNS3_PF_FUNC_ID;
1879 hns3_update_desc_vfid(desc, vf_id, true);
1881 /* All the vfid is zero, so need to delete this entry */
1882 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1883 } else if (ret == -ENOENT) {
1884 /* This mac addr doesn't exist. */
1889 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1891 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1898 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1899 struct rte_ether_addr *mc_addr_set,
1900 uint32_t nb_mc_addr)
1902 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1903 struct rte_ether_addr *addr;
1907 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1908 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1909 "invalid. valid range: 0~%d",
1910 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1914 /* Check if input mac addresses are valid */
1915 for (i = 0; i < nb_mc_addr; i++) {
1916 addr = &mc_addr_set[i];
1917 if (!rte_is_multicast_ether_addr(addr)) {
1918 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1921 "failed to set mc mac addr, addr(%s) invalid.",
1926 /* Check if there are duplicate addresses */
1927 for (j = i + 1; j < nb_mc_addr; j++) {
1928 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1929 rte_ether_format_addr(mac_str,
1930 RTE_ETHER_ADDR_FMT_SIZE,
1932 hns3_err(hw, "failed to set mc mac addr, "
1933 "addrs invalid. two same addrs(%s).",
1940 * Check if there are duplicate addresses between mac_addrs
1943 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1944 if (rte_is_same_ether_addr(addr,
1945 &hw->data->mac_addrs[j])) {
1946 rte_ether_format_addr(mac_str,
1947 RTE_ETHER_ADDR_FMT_SIZE,
1949 hns3_err(hw, "failed to set mc mac addr, "
1950 "addrs invalid. addrs(%s) has already "
1951 "configured in mac_addr add API",
1962 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1963 struct rte_ether_addr *mc_addr_set,
1965 struct rte_ether_addr *reserved_addr_list,
1966 int *reserved_addr_num,
1967 struct rte_ether_addr *add_addr_list,
1969 struct rte_ether_addr *rm_addr_list,
1972 struct rte_ether_addr *addr;
1973 int current_addr_num;
1974 int reserved_num = 0;
1982 /* Calculate the mc mac address list that should be removed */
1983 current_addr_num = hw->mc_addrs_num;
1984 for (i = 0; i < current_addr_num; i++) {
1985 addr = &hw->mc_addrs[i];
1987 for (j = 0; j < mc_addr_num; j++) {
1988 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1995 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1998 rte_ether_addr_copy(addr,
1999 &reserved_addr_list[reserved_num]);
2004 /* Calculate the mc mac address list that should be added */
2005 for (i = 0; i < mc_addr_num; i++) {
2006 addr = &mc_addr_set[i];
2008 for (j = 0; j < current_addr_num; j++) {
2009 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2016 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2021 /* Reorder the mc mac address list maintained by driver */
2022 for (i = 0; i < reserved_num; i++)
2023 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2025 for (i = 0; i < rm_num; i++) {
2026 num = reserved_num + i;
2027 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2030 *reserved_addr_num = reserved_num;
2031 *add_addr_num = add_num;
2032 *rm_addr_num = rm_num;
2036 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2037 struct rte_ether_addr *mc_addr_set,
2038 uint32_t nb_mc_addr)
2040 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2042 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2043 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2044 struct rte_ether_addr *addr;
2045 int reserved_addr_num;
2053 /* Check if input parameters are valid */
2054 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2058 rte_spinlock_lock(&hw->lock);
2061 * Calculate the mc mac address lists those should be removed and be
2062 * added, Reorder the mc mac address list maintained by driver.
2064 mc_addr_num = (int)nb_mc_addr;
2065 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2066 reserved_addr_list, &reserved_addr_num,
2067 add_addr_list, &add_addr_num,
2068 rm_addr_list, &rm_addr_num);
2070 /* Remove mc mac addresses */
2071 for (i = 0; i < rm_addr_num; i++) {
2072 num = rm_addr_num - i - 1;
2073 addr = &rm_addr_list[num];
2074 ret = hns3_remove_mc_addr(hw, addr);
2076 rte_spinlock_unlock(&hw->lock);
2082 /* Add mc mac addresses */
2083 for (i = 0; i < add_addr_num; i++) {
2084 addr = &add_addr_list[i];
2085 ret = hns3_add_mc_addr(hw, addr);
2087 rte_spinlock_unlock(&hw->lock);
2091 num = reserved_addr_num + i;
2092 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2095 rte_spinlock_unlock(&hw->lock);
2101 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2103 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2104 struct hns3_hw *hw = &hns->hw;
2105 struct rte_ether_addr *addr;
2110 for (i = 0; i < hw->mc_addrs_num; i++) {
2111 addr = &hw->mc_addrs[i];
2112 if (!rte_is_multicast_ether_addr(addr))
2115 ret = hns3_remove_mc_addr(hw, addr);
2117 ret = hns3_add_mc_addr(hw, addr);
2120 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2122 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2123 del ? "Remove" : "Restore", mac_str, ret);
2130 hns3_check_mq_mode(struct rte_eth_dev *dev)
2132 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2133 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2134 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2137 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2142 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2143 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2145 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2146 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2147 "rx_mq_mode = %d", rx_mq_mode);
2151 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2152 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2153 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2154 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2155 rx_mq_mode, tx_mq_mode);
2159 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2160 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2161 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2162 dcb_rx_conf->nb_tcs, pf->tc_max);
2166 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2167 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2168 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2169 "nb_tcs(%d) != %d or %d in rx direction.",
2170 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2174 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2175 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2176 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2180 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2181 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2182 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2183 "is not equal to one in tx direction.",
2184 i, dcb_rx_conf->dcb_tc[i]);
2187 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2188 max_tc = dcb_rx_conf->dcb_tc[i];
2191 num_tc = max_tc + 1;
2192 if (num_tc > dcb_rx_conf->nb_tcs) {
2193 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2194 num_tc, dcb_rx_conf->nb_tcs);
2203 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2205 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 if (!hns3_dev_dcb_supported(hw)) {
2208 hns3_err(hw, "this port does not support dcb configurations.");
2212 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2213 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2217 /* Check multiple queue mode */
2218 return hns3_check_mq_mode(dev);
2222 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2223 enum hns3_ring_type queue_type, uint16_t queue_id)
2225 struct hns3_cmd_desc desc;
2226 struct hns3_ctrl_vector_chain_cmd *req =
2227 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2228 enum hns3_cmd_status status;
2229 enum hns3_opcode_type op;
2230 uint16_t tqp_type_and_id = 0;
2235 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2236 hns3_cmd_setup_basic_desc(&desc, op, false);
2237 req->int_vector_id = vector_id;
2239 if (queue_type == HNS3_RING_TYPE_RX)
2240 gl = HNS3_RING_GL_RX;
2242 gl = HNS3_RING_GL_TX;
2246 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2248 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2249 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2251 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2252 req->int_cause_num = 1;
2253 op_str = mmap ? "Map" : "Unmap";
2254 status = hns3_cmd_send(hw, &desc, 1);
2256 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2257 op_str, queue_id, req->int_vector_id, status);
2265 hns3_init_ring_with_vector(struct hns3_hw *hw)
2272 * In hns3 network engine, vector 0 is always the misc interrupt of this
2273 * function, vector 1~N can be used respectively for the queues of the
2274 * function. Tx and Rx queues with the same number share the interrupt
2275 * vector. In the initialization clearing the all hardware mapping
2276 * relationship configurations between queues and interrupt vectors is
2277 * needed, so some error caused by the residual configurations, such as
2278 * the unexpected Tx interrupt, can be avoid.
2280 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2281 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2282 vec = vec - 1; /* the last interrupt is reserved */
2283 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2284 for (i = 0; i < hw->intr_tqps_num; i++) {
2286 * Set gap limiter/rate limiter/quanity limiter algorithm
2287 * configuration for interrupt coalesce of queue's interrupt.
2289 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2290 HNS3_TQP_INTR_GL_DEFAULT);
2291 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2292 HNS3_TQP_INTR_GL_DEFAULT);
2293 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2294 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2296 ret = hns3_bind_ring_with_vector(hw, vec, false,
2297 HNS3_RING_TYPE_TX, i);
2299 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2300 "vector: %d, ret=%d", i, vec, ret);
2304 ret = hns3_bind_ring_with_vector(hw, vec, false,
2305 HNS3_RING_TYPE_RX, i);
2307 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2308 "vector: %d, ret=%d", i, vec, ret);
2317 hns3_dev_configure(struct rte_eth_dev *dev)
2319 struct hns3_adapter *hns = dev->data->dev_private;
2320 struct rte_eth_conf *conf = &dev->data->dev_conf;
2321 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2322 struct hns3_hw *hw = &hns->hw;
2323 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2324 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2325 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2326 struct rte_eth_rss_conf rss_conf;
2331 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2334 * Some versions of hardware network engine does not support
2335 * individually enable/disable/reset the Tx or Rx queue. These devices
2336 * must enable/disable/reset Tx and Rx queues at the same time. When the
2337 * numbers of Tx queues allocated by upper applications are not equal to
2338 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2339 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2340 * work as usual. But these fake queues are imperceptible, and can not
2341 * be used by upper applications.
2343 if (!hns3_dev_indep_txrx_supported(hw)) {
2344 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2346 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2352 hw->adapter_state = HNS3_NIC_CONFIGURING;
2353 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2354 hns3_err(hw, "setting link speed/duplex not supported");
2359 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2360 ret = hns3_check_dcb_cfg(dev);
2365 /* When RSS is not configured, redirect the packet queue 0 */
2366 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2367 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2368 rss_conf = conf->rx_adv_conf.rss_conf;
2369 hw->rss_dis_flag = false;
2370 if (rss_conf.rss_key == NULL) {
2371 rss_conf.rss_key = rss_cfg->key;
2372 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2375 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2381 * If jumbo frames are enabled, MTU needs to be refreshed
2382 * according to the maximum RX packet length.
2384 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2386 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2387 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2388 * can safely assign to "uint16_t" type variable.
2390 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2391 ret = hns3_dev_mtu_set(dev, mtu);
2394 dev->data->mtu = mtu;
2397 ret = hns3_dev_configure_vlan(dev);
2401 /* config hardware GRO */
2402 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2403 ret = hns3_config_gro(hw, gro_en);
2407 hns->rx_simple_allowed = true;
2408 hns->rx_vec_allowed = true;
2409 hns->tx_simple_allowed = true;
2410 hns->tx_vec_allowed = true;
2412 hns3_init_rx_ptype_tble(dev);
2413 hw->adapter_state = HNS3_NIC_CONFIGURED;
2418 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2419 hw->adapter_state = HNS3_NIC_INITIALIZED;
2425 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2427 struct hns3_config_max_frm_size_cmd *req;
2428 struct hns3_cmd_desc desc;
2430 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2432 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2433 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2434 req->min_frm_size = RTE_ETHER_MIN_LEN;
2436 return hns3_cmd_send(hw, &desc, 1);
2440 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2444 ret = hns3_set_mac_mtu(hw, mps);
2446 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2450 ret = hns3_buffer_alloc(hw);
2452 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2458 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2460 struct hns3_adapter *hns = dev->data->dev_private;
2461 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2462 struct hns3_hw *hw = &hns->hw;
2463 bool is_jumbo_frame;
2466 if (dev->data->dev_started) {
2467 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2468 "before configuration", dev->data->port_id);
2472 rte_spinlock_lock(&hw->lock);
2473 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2474 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2477 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2478 * assign to "uint16_t" type variable.
2480 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2482 rte_spinlock_unlock(&hw->lock);
2483 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2484 dev->data->port_id, mtu, ret);
2487 hns->pf.mps = (uint16_t)frame_size;
2489 dev->data->dev_conf.rxmode.offloads |=
2490 DEV_RX_OFFLOAD_JUMBO_FRAME;
2492 dev->data->dev_conf.rxmode.offloads &=
2493 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2494 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2495 rte_spinlock_unlock(&hw->lock);
2501 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2503 struct hns3_adapter *hns = eth_dev->data->dev_private;
2504 struct hns3_hw *hw = &hns->hw;
2505 uint16_t queue_num = hw->tqps_num;
2508 * In interrupt mode, 'max_rx_queues' is set based on the number of
2509 * MSI-X interrupt resources of the hardware.
2511 if (hw->data->dev_conf.intr_conf.rxq == 1)
2512 queue_num = hw->intr_tqps_num;
2514 info->max_rx_queues = queue_num;
2515 info->max_tx_queues = hw->tqps_num;
2516 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2517 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2518 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2519 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2520 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2521 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2522 DEV_RX_OFFLOAD_TCP_CKSUM |
2523 DEV_RX_OFFLOAD_UDP_CKSUM |
2524 DEV_RX_OFFLOAD_SCTP_CKSUM |
2525 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2526 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2527 DEV_RX_OFFLOAD_KEEP_CRC |
2528 DEV_RX_OFFLOAD_SCATTER |
2529 DEV_RX_OFFLOAD_VLAN_STRIP |
2530 DEV_RX_OFFLOAD_VLAN_FILTER |
2531 DEV_RX_OFFLOAD_JUMBO_FRAME |
2532 DEV_RX_OFFLOAD_RSS_HASH |
2533 DEV_RX_OFFLOAD_TCP_LRO);
2534 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2535 DEV_TX_OFFLOAD_IPV4_CKSUM |
2536 DEV_TX_OFFLOAD_TCP_CKSUM |
2537 DEV_TX_OFFLOAD_UDP_CKSUM |
2538 DEV_TX_OFFLOAD_SCTP_CKSUM |
2539 DEV_TX_OFFLOAD_MULTI_SEGS |
2540 DEV_TX_OFFLOAD_TCP_TSO |
2541 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2542 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2543 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2544 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2545 hns3_txvlan_cap_get(hw));
2547 if (hns3_dev_indep_txrx_supported(hw))
2548 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2549 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2551 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2552 .nb_max = HNS3_MAX_RING_DESC,
2553 .nb_min = HNS3_MIN_RING_DESC,
2554 .nb_align = HNS3_ALIGN_RING_DESC,
2557 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2558 .nb_max = HNS3_MAX_RING_DESC,
2559 .nb_min = HNS3_MIN_RING_DESC,
2560 .nb_align = HNS3_ALIGN_RING_DESC,
2561 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2562 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2565 info->default_rxconf = (struct rte_eth_rxconf) {
2566 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2568 * If there are no available Rx buffer descriptors, incoming
2569 * packets are always dropped by hardware based on hns3 network
2575 info->default_txconf = (struct rte_eth_txconf) {
2576 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2580 info->vmdq_queue_num = 0;
2582 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2583 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2584 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2586 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2587 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2588 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2589 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2590 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2591 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2597 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2600 struct hns3_adapter *hns = eth_dev->data->dev_private;
2601 struct hns3_hw *hw = &hns->hw;
2602 uint32_t version = hw->fw_version;
2605 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2606 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2607 HNS3_FW_VERSION_BYTE3_S),
2608 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2609 HNS3_FW_VERSION_BYTE2_S),
2610 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2611 HNS3_FW_VERSION_BYTE1_S),
2612 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2613 HNS3_FW_VERSION_BYTE0_S));
2614 ret += 1; /* add the size of '\0' */
2615 if (fw_size < (uint32_t)ret)
2622 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2623 __rte_unused int wait_to_complete)
2625 struct hns3_adapter *hns = eth_dev->data->dev_private;
2626 struct hns3_hw *hw = &hns->hw;
2627 struct hns3_mac *mac = &hw->mac;
2628 struct rte_eth_link new_link;
2630 if (!hns3_is_reset_pending(hns)) {
2631 hns3_update_speed_duplex(eth_dev);
2632 hns3_update_link_status(hw);
2635 memset(&new_link, 0, sizeof(new_link));
2636 switch (mac->link_speed) {
2637 case ETH_SPEED_NUM_10M:
2638 case ETH_SPEED_NUM_100M:
2639 case ETH_SPEED_NUM_1G:
2640 case ETH_SPEED_NUM_10G:
2641 case ETH_SPEED_NUM_25G:
2642 case ETH_SPEED_NUM_40G:
2643 case ETH_SPEED_NUM_50G:
2644 case ETH_SPEED_NUM_100G:
2645 case ETH_SPEED_NUM_200G:
2646 new_link.link_speed = mac->link_speed;
2649 new_link.link_speed = ETH_SPEED_NUM_100M;
2653 new_link.link_duplex = mac->link_duplex;
2654 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2655 new_link.link_autoneg =
2656 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2658 return rte_eth_linkstatus_set(eth_dev, &new_link);
2662 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2664 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2665 struct hns3_pf *pf = &hns->pf;
2667 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2670 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2676 hns3_query_function_status(struct hns3_hw *hw)
2678 #define HNS3_QUERY_MAX_CNT 10
2679 #define HNS3_QUERY_SLEEP_MSCOEND 1
2680 struct hns3_func_status_cmd *req;
2681 struct hns3_cmd_desc desc;
2685 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2686 req = (struct hns3_func_status_cmd *)desc.data;
2689 ret = hns3_cmd_send(hw, &desc, 1);
2691 PMD_INIT_LOG(ERR, "query function status failed %d",
2696 /* Check pf reset is done */
2700 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2701 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2703 return hns3_parse_func_status(hw, req);
2707 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2709 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2710 struct hns3_pf *pf = &hns->pf;
2712 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2714 * The total_tqps_num obtained from firmware is maximum tqp
2715 * numbers of this port, which should be used for PF and VFs.
2716 * There is no need for pf to have so many tqp numbers in
2717 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2718 * coming from config file, is assigned to maximum queue number
2719 * for the PF of this port by user. So users can modify the
2720 * maximum queue number of PF according to their own application
2721 * scenarios, which is more flexible to use. In addition, many
2722 * memories can be saved due to allocating queue statistics
2723 * room according to the actual number of queues required. The
2724 * maximum queue number of PF for network engine with
2725 * revision_id greater than 0x30 is assigned by config file.
2727 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2728 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2729 "must be greater than 0.",
2730 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2734 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2735 hw->total_tqps_num);
2738 * Due to the limitation on the number of PF interrupts
2739 * available, the maximum queue number assigned to PF on
2740 * the network engine with revision_id 0x21 is 64.
2742 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2743 HNS3_MAX_TQP_NUM_HIP08_PF);
2750 hns3_query_pf_resource(struct hns3_hw *hw)
2752 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2753 struct hns3_pf *pf = &hns->pf;
2754 struct hns3_pf_res_cmd *req;
2755 struct hns3_cmd_desc desc;
2758 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2759 ret = hns3_cmd_send(hw, &desc, 1);
2761 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2765 req = (struct hns3_pf_res_cmd *)desc.data;
2766 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2767 rte_le_to_cpu_16(req->ext_tqp_num);
2768 ret = hns3_get_pf_max_tqp_num(hw);
2772 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2773 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2775 if (req->tx_buf_size)
2777 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2779 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2781 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2783 if (req->dv_buf_size)
2785 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2787 pf->dv_buf_size = HNS3_DEFAULT_DV;
2789 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2792 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2793 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2799 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2801 struct hns3_cfg_param_cmd *req;
2802 uint64_t mac_addr_tmp_high;
2803 uint8_t ext_rss_size_max;
2804 uint64_t mac_addr_tmp;
2807 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2809 /* get the configuration */
2810 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2811 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2812 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2813 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2814 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2815 HNS3_CFG_TQP_DESC_N_M,
2816 HNS3_CFG_TQP_DESC_N_S);
2818 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2819 HNS3_CFG_PHY_ADDR_M,
2820 HNS3_CFG_PHY_ADDR_S);
2821 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2822 HNS3_CFG_MEDIA_TP_M,
2823 HNS3_CFG_MEDIA_TP_S);
2824 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2825 HNS3_CFG_RX_BUF_LEN_M,
2826 HNS3_CFG_RX_BUF_LEN_S);
2827 /* get mac address */
2828 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2829 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2830 HNS3_CFG_MAC_ADDR_H_M,
2831 HNS3_CFG_MAC_ADDR_H_S);
2833 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2835 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2836 HNS3_CFG_DEFAULT_SPEED_M,
2837 HNS3_CFG_DEFAULT_SPEED_S);
2838 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2839 HNS3_CFG_RSS_SIZE_M,
2840 HNS3_CFG_RSS_SIZE_S);
2842 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2843 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2845 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2846 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2848 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2849 HNS3_CFG_SPEED_ABILITY_M,
2850 HNS3_CFG_SPEED_ABILITY_S);
2851 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2852 HNS3_CFG_UMV_TBL_SPACE_M,
2853 HNS3_CFG_UMV_TBL_SPACE_S);
2854 if (!cfg->umv_space)
2855 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2857 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2858 HNS3_CFG_EXT_RSS_SIZE_M,
2859 HNS3_CFG_EXT_RSS_SIZE_S);
2862 * Field ext_rss_size_max obtained from firmware will be more flexible
2863 * for future changes and expansions, which is an exponent of 2, instead
2864 * of reading out directly. If this field is not zero, hns3 PF PMD
2865 * driver uses it as rss_size_max under one TC. Device, whose revision
2866 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2867 * maximum number of queues supported under a TC through this field.
2869 if (ext_rss_size_max)
2870 cfg->rss_size_max = 1U << ext_rss_size_max;
2873 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2874 * @hw: pointer to struct hns3_hw
2875 * @hcfg: the config structure to be getted
2878 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2880 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2881 struct hns3_cfg_param_cmd *req;
2886 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2888 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2889 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2891 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2892 i * HNS3_CFG_RD_LEN_BYTES);
2893 /* Len should be divided by 4 when send to hardware */
2894 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2895 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2896 req->offset = rte_cpu_to_le_32(offset);
2899 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2901 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2905 hns3_parse_cfg(hcfg, desc);
2911 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2913 switch (speed_cmd) {
2914 case HNS3_CFG_SPEED_10M:
2915 *speed = ETH_SPEED_NUM_10M;
2917 case HNS3_CFG_SPEED_100M:
2918 *speed = ETH_SPEED_NUM_100M;
2920 case HNS3_CFG_SPEED_1G:
2921 *speed = ETH_SPEED_NUM_1G;
2923 case HNS3_CFG_SPEED_10G:
2924 *speed = ETH_SPEED_NUM_10G;
2926 case HNS3_CFG_SPEED_25G:
2927 *speed = ETH_SPEED_NUM_25G;
2929 case HNS3_CFG_SPEED_40G:
2930 *speed = ETH_SPEED_NUM_40G;
2932 case HNS3_CFG_SPEED_50G:
2933 *speed = ETH_SPEED_NUM_50G;
2935 case HNS3_CFG_SPEED_100G:
2936 *speed = ETH_SPEED_NUM_100G;
2938 case HNS3_CFG_SPEED_200G:
2939 *speed = ETH_SPEED_NUM_200G;
2949 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2951 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2952 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2953 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2954 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2958 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2960 struct hns3_dev_specs_0_cmd *req0;
2962 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2964 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2965 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2966 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2967 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2971 hns3_query_dev_specifications(struct hns3_hw *hw)
2973 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2977 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2978 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2980 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2982 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2984 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2988 hns3_parse_dev_specifications(hw, desc);
2994 hns3_get_capability(struct hns3_hw *hw)
2996 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2997 struct rte_pci_device *pci_dev;
2998 struct hns3_pf *pf = &hns->pf;
2999 struct rte_eth_dev *eth_dev;
3004 eth_dev = &rte_eth_devices[hw->data->port_id];
3005 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3006 device_id = pci_dev->id.device_id;
3008 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3009 device_id == HNS3_DEV_ID_50GE_RDMA ||
3010 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3011 device_id == HNS3_DEV_ID_200G_RDMA)
3012 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3014 ret = hns3_query_dev_fec_info(eth_dev);
3017 "failed to query FEC information, ret = %d", ret);
3021 /* Get PCI revision id */
3022 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3023 HNS3_PCI_REVISION_ID);
3024 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3025 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3029 hw->revision = revision;
3031 if (revision < PCI_REVISION_ID_HIP09_A) {
3032 hns3_set_default_dev_specifications(hw);
3033 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3034 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
3035 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3036 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3037 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3038 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3039 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3040 hw->rss_info.ipv6_sctp_offload_supported = false;
3044 ret = hns3_query_dev_specifications(hw);
3047 "failed to query dev specifications, ret = %d",
3052 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3053 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
3054 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3055 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3056 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3057 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3058 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3059 hw->rss_info.ipv6_sctp_offload_supported = true;
3065 hns3_get_board_configuration(struct hns3_hw *hw)
3067 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3068 struct hns3_pf *pf = &hns->pf;
3069 struct hns3_cfg cfg;
3072 ret = hns3_get_board_cfg(hw, &cfg);
3074 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3078 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3079 !hns3_dev_copper_supported(hw)) {
3080 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3084 hw->mac.media_type = cfg.media_type;
3085 hw->rss_size_max = cfg.rss_size_max;
3086 hw->rss_dis_flag = false;
3087 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3088 hw->mac.phy_addr = cfg.phy_addr;
3089 hw->mac.default_addr_setted = false;
3090 hw->num_tx_desc = cfg.tqp_desc_num;
3091 hw->num_rx_desc = cfg.tqp_desc_num;
3092 hw->dcb_info.num_pg = 1;
3093 hw->dcb_info.hw_pfc_map = 0;
3095 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3097 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
3098 cfg.default_speed, ret);
3102 pf->tc_max = cfg.tc_num;
3103 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3104 PMD_INIT_LOG(WARNING,
3105 "Get TC num(%u) from flash, set TC num to 1",
3110 /* Dev does not support DCB */
3111 if (!hns3_dev_dcb_supported(hw)) {
3115 pf->pfc_max = pf->tc_max;
3117 hw->dcb_info.num_tc = 1;
3118 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3119 hw->tqps_num / hw->dcb_info.num_tc);
3120 hns3_set_bit(hw->hw_tc_map, 0, 1);
3121 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3123 pf->wanted_umv_size = cfg.umv_space;
3129 hns3_get_configuration(struct hns3_hw *hw)
3133 ret = hns3_query_function_status(hw);
3135 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3139 /* Get device capability */
3140 ret = hns3_get_capability(hw);
3142 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3146 /* Get pf resource */
3147 ret = hns3_query_pf_resource(hw);
3149 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3153 ret = hns3_get_board_configuration(hw);
3155 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3161 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3162 uint16_t tqp_vid, bool is_pf)
3164 struct hns3_tqp_map_cmd *req;
3165 struct hns3_cmd_desc desc;
3168 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3170 req = (struct hns3_tqp_map_cmd *)desc.data;
3171 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3172 req->tqp_vf = func_id;
3173 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3175 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3176 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3178 ret = hns3_cmd_send(hw, &desc, 1);
3180 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3186 hns3_map_tqp(struct hns3_hw *hw)
3192 * In current version, VF is not supported when PF is driven by DPDK
3193 * driver, so we assign total tqps_num tqps allocated to this port
3196 for (i = 0; i < hw->total_tqps_num; i++) {
3197 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3206 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3208 struct hns3_config_mac_speed_dup_cmd *req;
3209 struct hns3_cmd_desc desc;
3212 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3214 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3216 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3219 case ETH_SPEED_NUM_10M:
3220 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3221 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3223 case ETH_SPEED_NUM_100M:
3224 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3225 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3227 case ETH_SPEED_NUM_1G:
3228 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3229 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3231 case ETH_SPEED_NUM_10G:
3232 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3235 case ETH_SPEED_NUM_25G:
3236 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3239 case ETH_SPEED_NUM_40G:
3240 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3243 case ETH_SPEED_NUM_50G:
3244 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3245 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3247 case ETH_SPEED_NUM_100G:
3248 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3251 case ETH_SPEED_NUM_200G:
3252 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3253 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3256 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3260 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3262 ret = hns3_cmd_send(hw, &desc, 1);
3264 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3270 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3272 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3273 struct hns3_pf *pf = &hns->pf;
3274 struct hns3_priv_buf *priv;
3275 uint32_t i, total_size;
3277 total_size = pf->pkt_buf_size;
3279 /* alloc tx buffer for all enabled tc */
3280 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3281 priv = &buf_alloc->priv_buf[i];
3283 if (hw->hw_tc_map & BIT(i)) {
3284 if (total_size < pf->tx_buf_size)
3287 priv->tx_buf_size = pf->tx_buf_size;
3289 priv->tx_buf_size = 0;
3291 total_size -= priv->tx_buf_size;
3298 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3300 /* TX buffer size is unit by 128 byte */
3301 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3302 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3303 struct hns3_tx_buff_alloc_cmd *req;
3304 struct hns3_cmd_desc desc;
3309 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3311 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3312 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3313 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3315 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3316 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3317 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3320 ret = hns3_cmd_send(hw, &desc, 1);
3322 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3328 hns3_get_tc_num(struct hns3_hw *hw)
3333 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3334 if (hw->hw_tc_map & BIT(i))
3340 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3342 struct hns3_priv_buf *priv;
3343 uint32_t rx_priv = 0;
3346 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3347 priv = &buf_alloc->priv_buf[i];
3349 rx_priv += priv->buf_size;
3355 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3357 uint32_t total_tx_size = 0;
3360 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3361 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3363 return total_tx_size;
3366 /* Get the number of pfc enabled TCs, which have private buffer */
3368 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3370 struct hns3_priv_buf *priv;
3374 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3375 priv = &buf_alloc->priv_buf[i];
3376 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3383 /* Get the number of pfc disabled TCs, which have private buffer */
3385 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3386 struct hns3_pkt_buf_alloc *buf_alloc)
3388 struct hns3_priv_buf *priv;
3392 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3393 priv = &buf_alloc->priv_buf[i];
3394 if (hw->hw_tc_map & BIT(i) &&
3395 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3403 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3406 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3407 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3408 struct hns3_pf *pf = &hns->pf;
3409 uint32_t shared_buf, aligned_mps;
3414 tc_num = hns3_get_tc_num(hw);
3415 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3417 if (hns3_dev_dcb_supported(hw))
3418 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3421 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3424 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3425 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3426 HNS3_BUF_SIZE_UNIT);
3428 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3429 if (rx_all < rx_priv + shared_std)
3432 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3433 buf_alloc->s_buf.buf_size = shared_buf;
3434 if (hns3_dev_dcb_supported(hw)) {
3435 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3436 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3437 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3438 HNS3_BUF_SIZE_UNIT);
3440 buf_alloc->s_buf.self.high =
3441 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3442 buf_alloc->s_buf.self.low = aligned_mps;
3445 if (hns3_dev_dcb_supported(hw)) {
3446 hi_thrd = shared_buf - pf->dv_buf_size;
3448 if (tc_num <= NEED_RESERVE_TC_NUM)
3449 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3453 hi_thrd = hi_thrd / tc_num;
3455 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3456 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3457 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3459 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3460 lo_thrd = aligned_mps;
3463 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3464 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3465 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3472 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3473 struct hns3_pkt_buf_alloc *buf_alloc)
3475 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3476 struct hns3_pf *pf = &hns->pf;
3477 struct hns3_priv_buf *priv;
3478 uint32_t aligned_mps;
3482 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3483 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3485 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3486 priv = &buf_alloc->priv_buf[i];
3493 if (!(hw->hw_tc_map & BIT(i)))
3497 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3498 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3499 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3500 HNS3_BUF_SIZE_UNIT);
3503 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3507 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3510 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3514 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3515 struct hns3_pkt_buf_alloc *buf_alloc)
3517 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3518 struct hns3_pf *pf = &hns->pf;
3519 struct hns3_priv_buf *priv;
3520 int no_pfc_priv_num;
3525 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3526 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3528 /* let the last to be cleared first */
3529 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3530 priv = &buf_alloc->priv_buf[i];
3531 mask = BIT((uint8_t)i);
3533 if (hw->hw_tc_map & mask &&
3534 !(hw->dcb_info.hw_pfc_map & mask)) {
3535 /* Clear the no pfc TC private buffer */
3543 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3544 no_pfc_priv_num == 0)
3548 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3552 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3553 struct hns3_pkt_buf_alloc *buf_alloc)
3555 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3556 struct hns3_pf *pf = &hns->pf;
3557 struct hns3_priv_buf *priv;
3563 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3564 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3566 /* let the last to be cleared first */
3567 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3568 priv = &buf_alloc->priv_buf[i];
3569 mask = BIT((uint8_t)i);
3571 if (hw->hw_tc_map & mask &&
3572 hw->dcb_info.hw_pfc_map & mask) {
3573 /* Reduce the number of pfc TC with private buffer */
3580 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3585 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3589 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3590 struct hns3_pkt_buf_alloc *buf_alloc)
3592 #define COMPENSATE_BUFFER 0x3C00
3593 #define COMPENSATE_HALF_MPS_NUM 5
3594 #define PRIV_WL_GAP 0x1800
3595 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3596 struct hns3_pf *pf = &hns->pf;
3597 uint32_t tc_num = hns3_get_tc_num(hw);
3598 uint32_t half_mps = pf->mps >> 1;
3599 struct hns3_priv_buf *priv;
3600 uint32_t min_rx_priv;
3604 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3606 rx_priv = rx_priv / tc_num;
3608 if (tc_num <= NEED_RESERVE_TC_NUM)
3609 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3612 * Minimum value of private buffer in rx direction (min_rx_priv) is
3613 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3614 * buffer if rx_priv is greater than min_rx_priv.
3616 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3617 COMPENSATE_HALF_MPS_NUM * half_mps;
3618 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3619 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3621 if (rx_priv < min_rx_priv)
3624 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3625 priv = &buf_alloc->priv_buf[i];
3632 if (!(hw->hw_tc_map & BIT(i)))
3636 priv->buf_size = rx_priv;
3637 priv->wl.high = rx_priv - pf->dv_buf_size;
3638 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3641 buf_alloc->s_buf.buf_size = 0;
3647 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3648 * @hw: pointer to struct hns3_hw
3649 * @buf_alloc: pointer to buffer calculation data
3650 * @return: 0: calculate sucessful, negative: fail
3653 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3655 /* When DCB is not supported, rx private buffer is not allocated. */
3656 if (!hns3_dev_dcb_supported(hw)) {
3657 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3658 struct hns3_pf *pf = &hns->pf;
3659 uint32_t rx_all = pf->pkt_buf_size;
3661 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3662 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3669 * Try to allocate privated packet buffer for all TCs without share
3672 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3676 * Try to allocate privated packet buffer for all TCs with share
3679 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3683 * For different application scenes, the enabled port number, TC number
3684 * and no_drop TC number are different. In order to obtain the better
3685 * performance, software could allocate the buffer size and configure
3686 * the waterline by tring to decrease the private buffer size according
3687 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3690 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3693 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3696 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3703 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3705 struct hns3_rx_priv_buff_cmd *req;
3706 struct hns3_cmd_desc desc;
3711 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3712 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3714 /* Alloc private buffer TCs */
3715 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3716 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3719 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3720 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3723 buf_size = buf_alloc->s_buf.buf_size;
3724 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3725 (1 << HNS3_TC0_PRI_BUF_EN_B));
3727 ret = hns3_cmd_send(hw, &desc, 1);
3729 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3735 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3737 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3738 struct hns3_rx_priv_wl_buf *req;
3739 struct hns3_priv_buf *priv;
3740 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3744 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3745 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3747 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3749 /* The first descriptor set the NEXT bit to 1 */
3751 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3753 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3755 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3756 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3758 priv = &buf_alloc->priv_buf[idx];
3759 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3761 req->tc_wl[j].high |=
3762 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3763 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3765 req->tc_wl[j].low |=
3766 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3770 /* Send 2 descriptor at one time */
3771 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3773 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3779 hns3_common_thrd_config(struct hns3_hw *hw,
3780 struct hns3_pkt_buf_alloc *buf_alloc)
3782 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3783 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3784 struct hns3_rx_com_thrd *req;
3785 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3786 struct hns3_tc_thrd *tc;
3791 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3792 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3794 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3796 /* The first descriptor set the NEXT bit to 1 */
3798 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3800 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3802 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3803 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3804 tc = &s_buf->tc_thrd[tc_idx];
3806 req->com_thrd[j].high =
3807 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3808 req->com_thrd[j].high |=
3809 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3810 req->com_thrd[j].low =
3811 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3812 req->com_thrd[j].low |=
3813 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3817 /* Send 2 descriptors at one time */
3818 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3820 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3826 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3828 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3829 struct hns3_rx_com_wl *req;
3830 struct hns3_cmd_desc desc;
3833 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3835 req = (struct hns3_rx_com_wl *)desc.data;
3836 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3837 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3839 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3840 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3842 ret = hns3_cmd_send(hw, &desc, 1);
3844 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3850 hns3_buffer_alloc(struct hns3_hw *hw)
3852 struct hns3_pkt_buf_alloc pkt_buf;
3855 memset(&pkt_buf, 0, sizeof(pkt_buf));
3856 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3859 "could not calc tx buffer size for all TCs %d",
3864 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3866 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3870 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3873 "could not calc rx priv buffer size for all TCs %d",
3878 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3880 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3884 if (hns3_dev_dcb_supported(hw)) {
3885 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3888 "could not configure rx private waterline %d",
3893 ret = hns3_common_thrd_config(hw, &pkt_buf);
3896 "could not configure common threshold %d",
3902 ret = hns3_common_wl_config(hw, &pkt_buf);
3904 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3911 hns3_mac_init(struct hns3_hw *hw)
3913 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3914 struct hns3_mac *mac = &hw->mac;
3915 struct hns3_pf *pf = &hns->pf;
3918 pf->support_sfp_query = true;
3919 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3920 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3922 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3926 mac->link_status = ETH_LINK_DOWN;
3928 return hns3_config_mtu(hw, pf->mps);
3932 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3934 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3935 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3936 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3937 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3942 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3947 switch (resp_code) {
3948 case HNS3_ETHERTYPE_SUCCESS_ADD:
3949 case HNS3_ETHERTYPE_ALREADY_ADD:
3952 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3954 "add mac ethertype failed for manager table overflow.");
3955 return_status = -EIO;
3957 case HNS3_ETHERTYPE_KEY_CONFLICT:
3958 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3959 return_status = -EIO;
3963 "add mac ethertype failed for undefined, code=%d.",
3965 return_status = -EIO;
3969 return return_status;
3973 hns3_add_mgr_tbl(struct hns3_hw *hw,
3974 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3976 struct hns3_cmd_desc desc;
3981 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3982 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3984 ret = hns3_cmd_send(hw, &desc, 1);
3987 "add mac ethertype failed for cmd_send, ret =%d.",
3992 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3993 retval = rte_le_to_cpu_16(desc.retval);
3995 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3999 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4000 int *table_item_num)
4002 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4005 * In current version, we add one item in management table as below:
4006 * 0x0180C200000E -- LLDP MC address
4009 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4010 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4011 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4012 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4013 tbl->i_port_bitmap = 0x1;
4014 *table_item_num = 1;
4018 hns3_init_mgr_tbl(struct hns3_hw *hw)
4020 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4021 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4026 memset(mgr_table, 0, sizeof(mgr_table));
4027 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4028 for (i = 0; i < table_item_num; i++) {
4029 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4031 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4041 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4042 bool en_mc, bool en_bc, int vport_id)
4047 memset(param, 0, sizeof(struct hns3_promisc_param));
4049 param->enable = HNS3_PROMISC_EN_UC;
4051 param->enable |= HNS3_PROMISC_EN_MC;
4053 param->enable |= HNS3_PROMISC_EN_BC;
4054 param->vf_id = vport_id;
4058 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4060 struct hns3_promisc_cfg_cmd *req;
4061 struct hns3_cmd_desc desc;
4064 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4066 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4067 req->vf_id = param->vf_id;
4068 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4069 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4071 ret = hns3_cmd_send(hw, &desc, 1);
4073 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4079 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4081 struct hns3_promisc_param param;
4082 bool en_bc_pmc = true;
4086 * In current version VF is not supported when PF is driven by DPDK
4087 * driver, just need to configure parameters for PF vport.
4089 vf_id = HNS3_PF_FUNC_ID;
4091 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4092 return hns3_cmd_set_promisc_mode(hw, ¶m);
4096 hns3_promisc_init(struct hns3_hw *hw)
4098 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4099 struct hns3_pf *pf = &hns->pf;
4100 struct hns3_promisc_param param;
4104 ret = hns3_set_promisc_mode(hw, false, false);
4106 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4111 * In current version VFs are not supported when PF is driven by DPDK
4112 * driver. After PF has been taken over by DPDK, the original VF will
4113 * be invalid. So, there is a possibility of entry residues. It should
4114 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4117 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4118 hns3_promisc_param_init(¶m, false, false, false, func_id);
4119 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4121 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4122 " ret = %d", func_id, ret);
4131 hns3_promisc_uninit(struct hns3_hw *hw)
4133 struct hns3_promisc_param param;
4137 func_id = HNS3_PF_FUNC_ID;
4140 * In current version VFs are not supported when PF is driven by
4141 * DPDK driver, and VFs' promisc mode status has been cleared during
4142 * init and their status will not change. So just clear PF's promisc
4143 * mode status during uninit.
4145 hns3_promisc_param_init(¶m, false, false, false, func_id);
4146 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4148 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4149 " uninit, ret = %d", ret);
4153 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4155 bool allmulti = dev->data->all_multicast ? true : false;
4156 struct hns3_adapter *hns = dev->data->dev_private;
4157 struct hns3_hw *hw = &hns->hw;
4162 rte_spinlock_lock(&hw->lock);
4163 ret = hns3_set_promisc_mode(hw, true, true);
4165 rte_spinlock_unlock(&hw->lock);
4166 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4172 * When promiscuous mode was enabled, disable the vlan filter to let
4173 * all packets coming in in the receiving direction.
4175 offloads = dev->data->dev_conf.rxmode.offloads;
4176 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4177 ret = hns3_enable_vlan_filter(hns, false);
4179 hns3_err(hw, "failed to enable promiscuous mode due to "
4180 "failure to disable vlan filter, ret = %d",
4182 err = hns3_set_promisc_mode(hw, false, allmulti);
4184 hns3_err(hw, "failed to restore promiscuous "
4185 "status after disable vlan filter "
4186 "failed during enabling promiscuous "
4187 "mode, ret = %d", ret);
4191 rte_spinlock_unlock(&hw->lock);
4197 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4199 bool allmulti = dev->data->all_multicast ? true : false;
4200 struct hns3_adapter *hns = dev->data->dev_private;
4201 struct hns3_hw *hw = &hns->hw;
4206 /* If now in all_multicast mode, must remain in all_multicast mode. */
4207 rte_spinlock_lock(&hw->lock);
4208 ret = hns3_set_promisc_mode(hw, false, allmulti);
4210 rte_spinlock_unlock(&hw->lock);
4211 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4215 /* when promiscuous mode was disabled, restore the vlan filter status */
4216 offloads = dev->data->dev_conf.rxmode.offloads;
4217 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4218 ret = hns3_enable_vlan_filter(hns, true);
4220 hns3_err(hw, "failed to disable promiscuous mode due to"
4221 " failure to restore vlan filter, ret = %d",
4223 err = hns3_set_promisc_mode(hw, true, true);
4225 hns3_err(hw, "failed to restore promiscuous "
4226 "status after enabling vlan filter "
4227 "failed during disabling promiscuous "
4228 "mode, ret = %d", ret);
4231 rte_spinlock_unlock(&hw->lock);
4237 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4239 struct hns3_adapter *hns = dev->data->dev_private;
4240 struct hns3_hw *hw = &hns->hw;
4243 if (dev->data->promiscuous)
4246 rte_spinlock_lock(&hw->lock);
4247 ret = hns3_set_promisc_mode(hw, false, true);
4248 rte_spinlock_unlock(&hw->lock);
4250 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4257 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4259 struct hns3_adapter *hns = dev->data->dev_private;
4260 struct hns3_hw *hw = &hns->hw;
4263 /* If now in promiscuous mode, must remain in all_multicast mode. */
4264 if (dev->data->promiscuous)
4267 rte_spinlock_lock(&hw->lock);
4268 ret = hns3_set_promisc_mode(hw, false, false);
4269 rte_spinlock_unlock(&hw->lock);
4271 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4278 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4280 struct hns3_hw *hw = &hns->hw;
4281 bool allmulti = hw->data->all_multicast ? true : false;
4284 if (hw->data->promiscuous) {
4285 ret = hns3_set_promisc_mode(hw, true, true);
4287 hns3_err(hw, "failed to restore promiscuous mode, "
4292 ret = hns3_set_promisc_mode(hw, false, allmulti);
4294 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4300 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4302 struct hns3_sfp_speed_cmd *resp;
4303 struct hns3_cmd_desc desc;
4306 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4307 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4308 ret = hns3_cmd_send(hw, &desc, 1);
4309 if (ret == -EOPNOTSUPP) {
4310 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4313 hns3_err(hw, "get sfp speed failed %d", ret);
4317 *speed = resp->sfp_speed;
4323 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4325 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4326 duplex = ETH_LINK_FULL_DUPLEX;
4332 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4334 struct hns3_mac *mac = &hw->mac;
4337 duplex = hns3_check_speed_dup(duplex, speed);
4338 if (mac->link_speed == speed && mac->link_duplex == duplex)
4341 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4345 mac->link_speed = speed;
4346 mac->link_duplex = duplex;
4352 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4354 struct hns3_adapter *hns = eth_dev->data->dev_private;
4355 struct hns3_hw *hw = &hns->hw;
4356 struct hns3_pf *pf = &hns->pf;
4360 /* If IMP do not support get SFP/qSFP speed, return directly */
4361 if (!pf->support_sfp_query)
4364 ret = hns3_get_sfp_speed(hw, &speed);
4365 if (ret == -EOPNOTSUPP) {
4366 pf->support_sfp_query = false;
4371 if (speed == ETH_SPEED_NUM_NONE)
4372 return 0; /* do nothing if no SFP */
4374 /* Config full duplex for SFP */
4375 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4379 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4381 struct hns3_config_mac_mode_cmd *req;
4382 struct hns3_cmd_desc desc;
4383 uint32_t loop_en = 0;
4387 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4389 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4392 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4393 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4394 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4395 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4396 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4397 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4398 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4399 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4400 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4401 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4404 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4405 * when receiving frames. Otherwise, CRC will be stripped.
4407 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4408 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4410 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4411 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4412 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4413 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4414 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4416 ret = hns3_cmd_send(hw, &desc, 1);
4418 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4424 hns3_get_mac_link_status(struct hns3_hw *hw)
4426 struct hns3_link_status_cmd *req;
4427 struct hns3_cmd_desc desc;
4431 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4432 ret = hns3_cmd_send(hw, &desc, 1);
4434 hns3_err(hw, "get link status cmd failed %d", ret);
4435 return ETH_LINK_DOWN;
4438 req = (struct hns3_link_status_cmd *)desc.data;
4439 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4441 return !!link_status;
4445 hns3_update_link_status(struct hns3_hw *hw)
4449 state = hns3_get_mac_link_status(hw);
4450 if (state != hw->mac.link_status) {
4451 hw->mac.link_status = state;
4452 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4457 hns3_service_handler(void *param)
4459 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4460 struct hns3_adapter *hns = eth_dev->data->dev_private;
4461 struct hns3_hw *hw = &hns->hw;
4463 if (!hns3_is_reset_pending(hns)) {
4464 hns3_update_speed_duplex(eth_dev);
4465 hns3_update_link_status(hw);
4467 hns3_warn(hw, "Cancel the query when reset is pending");
4469 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4473 hns3_init_hardware(struct hns3_adapter *hns)
4475 struct hns3_hw *hw = &hns->hw;
4478 ret = hns3_map_tqp(hw);
4480 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4484 ret = hns3_init_umv_space(hw);
4486 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4490 ret = hns3_mac_init(hw);
4492 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4496 ret = hns3_init_mgr_tbl(hw);
4498 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4502 ret = hns3_promisc_init(hw);
4504 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4509 ret = hns3_init_vlan_config(hns);
4511 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4515 ret = hns3_dcb_init(hw);
4517 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4521 ret = hns3_init_fd_config(hns);
4523 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4527 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4529 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4533 ret = hns3_config_gro(hw, false);
4535 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4540 * In the initialization clearing the all hardware mapping relationship
4541 * configurations between queues and interrupt vectors is needed, so
4542 * some error caused by the residual configurations, such as the
4543 * unexpected interrupt, can be avoid.
4545 ret = hns3_init_ring_with_vector(hw);
4547 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4554 hns3_uninit_umv_space(hw);
4559 hns3_clear_hw(struct hns3_hw *hw)
4561 struct hns3_cmd_desc desc;
4564 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4566 ret = hns3_cmd_send(hw, &desc, 1);
4567 if (ret && ret != -EOPNOTSUPP)
4574 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4579 * The new firmware support report more hardware error types by
4580 * msix mode. These errors are defined as RAS errors in hardware
4581 * and belong to a different type from the MSI-x errors processed
4582 * by the network driver.
4584 * Network driver should open the new error report on initialition
4586 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4587 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4588 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4592 hns3_init_pf(struct rte_eth_dev *eth_dev)
4594 struct rte_device *dev = eth_dev->device;
4595 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4596 struct hns3_adapter *hns = eth_dev->data->dev_private;
4597 struct hns3_hw *hw = &hns->hw;
4600 PMD_INIT_FUNC_TRACE();
4602 /* Get hardware io base address from pcie BAR2 IO space */
4603 hw->io_base = pci_dev->mem_resource[2].addr;
4605 /* Firmware command queue initialize */
4606 ret = hns3_cmd_init_queue(hw);
4608 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4609 goto err_cmd_init_queue;
4612 hns3_clear_all_event_cause(hw);
4614 /* Firmware command initialize */
4615 ret = hns3_cmd_init(hw);
4617 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4622 * To ensure that the hardware environment is clean during
4623 * initialization, the driver actively clear the hardware environment
4624 * during initialization, including PF and corresponding VFs' vlan, mac,
4625 * flow table configurations, etc.
4627 ret = hns3_clear_hw(hw);
4629 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4633 hns3_config_all_msix_error(hw, true);
4635 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4636 hns3_interrupt_handler,
4639 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4640 goto err_intr_callback_register;
4643 /* Enable interrupt */
4644 rte_intr_enable(&pci_dev->intr_handle);
4645 hns3_pf_enable_irq0(hw);
4647 /* Get configuration */
4648 ret = hns3_get_configuration(hw);
4650 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4651 goto err_get_config;
4654 ret = hns3_tqp_stats_init(hw);
4656 goto err_get_config;
4658 ret = hns3_init_hardware(hns);
4660 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4664 /* Initialize flow director filter list & hash */
4665 ret = hns3_fdir_filter_init(hns);
4667 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4671 hns3_set_default_rss_args(hw);
4673 ret = hns3_enable_hw_error_intr(hns, true);
4675 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4677 goto err_enable_intr;
4683 hns3_fdir_filter_uninit(hns);
4685 hns3_uninit_umv_space(hw);
4687 hns3_tqp_stats_uninit(hw);
4689 hns3_pf_disable_irq0(hw);
4690 rte_intr_disable(&pci_dev->intr_handle);
4691 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4693 err_intr_callback_register:
4695 hns3_cmd_uninit(hw);
4696 hns3_cmd_destroy_queue(hw);
4704 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4706 struct hns3_adapter *hns = eth_dev->data->dev_private;
4707 struct rte_device *dev = eth_dev->device;
4708 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4709 struct hns3_hw *hw = &hns->hw;
4711 PMD_INIT_FUNC_TRACE();
4713 hns3_enable_hw_error_intr(hns, false);
4714 hns3_rss_uninit(hns);
4715 (void)hns3_config_gro(hw, false);
4716 hns3_promisc_uninit(hw);
4717 hns3_fdir_filter_uninit(hns);
4718 hns3_uninit_umv_space(hw);
4719 hns3_tqp_stats_uninit(hw);
4720 hns3_pf_disable_irq0(hw);
4721 rte_intr_disable(&pci_dev->intr_handle);
4722 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4724 hns3_config_all_msix_error(hw, false);
4725 hns3_cmd_uninit(hw);
4726 hns3_cmd_destroy_queue(hw);
4731 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4733 struct hns3_hw *hw = &hns->hw;
4736 ret = hns3_dcb_cfg_update(hns);
4740 ret = hns3_init_queues(hns, reset_queue);
4742 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4746 ret = hns3_cfg_mac_mode(hw, true);
4748 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4749 goto err_config_mac_mode;
4753 err_config_mac_mode:
4754 hns3_dev_release_mbufs(hns);
4756 * Here is exception handling, hns3_reset_all_tqps will have the
4757 * corresponding error message if it is handled incorrectly, so it is
4758 * not necessary to check hns3_reset_all_tqps return value, here keep
4759 * ret as the error code causing the exception.
4761 (void)hns3_reset_all_tqps(hns);
4766 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4770 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4772 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4773 uint32_t intr_vector;
4777 if (dev->data->dev_conf.intr_conf.rxq == 0)
4780 /* disable uio/vfio intr/eventfd mapping */
4781 rte_intr_disable(intr_handle);
4783 /* check and configure queue intr-vector mapping */
4784 if (rte_intr_cap_multiple(intr_handle) ||
4785 !RTE_ETH_DEV_SRIOV(dev).active) {
4786 intr_vector = hw->used_rx_queues;
4787 /* creates event fd for each intr vector when MSIX is used */
4788 if (rte_intr_efd_enable(intr_handle, intr_vector))
4791 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4792 intr_handle->intr_vec =
4793 rte_zmalloc("intr_vec",
4794 hw->used_rx_queues * sizeof(int), 0);
4795 if (intr_handle->intr_vec == NULL) {
4796 hns3_err(hw, "Failed to allocate %d rx_queues"
4797 " intr_vec", hw->used_rx_queues);
4799 goto alloc_intr_vec_error;
4803 if (rte_intr_allow_others(intr_handle)) {
4804 vec = RTE_INTR_VEC_RXTX_OFFSET;
4805 base = RTE_INTR_VEC_RXTX_OFFSET;
4807 if (rte_intr_dp_is_en(intr_handle)) {
4808 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4809 ret = hns3_bind_ring_with_vector(hw, vec, true,
4813 goto bind_vector_error;
4814 intr_handle->intr_vec[q_id] = vec;
4815 if (vec < base + intr_handle->nb_efd - 1)
4819 rte_intr_enable(intr_handle);
4823 rte_intr_efd_disable(intr_handle);
4824 if (intr_handle->intr_vec) {
4825 free(intr_handle->intr_vec);
4826 intr_handle->intr_vec = NULL;
4829 alloc_intr_vec_error:
4830 rte_intr_efd_disable(intr_handle);
4835 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4837 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4838 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4839 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4843 if (dev->data->dev_conf.intr_conf.rxq == 0)
4846 if (rte_intr_dp_is_en(intr_handle)) {
4847 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4848 ret = hns3_bind_ring_with_vector(hw,
4849 intr_handle->intr_vec[q_id], true,
4850 HNS3_RING_TYPE_RX, q_id);
4860 hns3_restore_filter(struct rte_eth_dev *dev)
4862 hns3_restore_rss_filter(dev);
4866 hns3_dev_start(struct rte_eth_dev *dev)
4868 struct hns3_adapter *hns = dev->data->dev_private;
4869 struct hns3_hw *hw = &hns->hw;
4872 PMD_INIT_FUNC_TRACE();
4873 if (rte_atomic16_read(&hw->reset.resetting))
4876 rte_spinlock_lock(&hw->lock);
4877 hw->adapter_state = HNS3_NIC_STARTING;
4879 ret = hns3_do_start(hns, true);
4881 hw->adapter_state = HNS3_NIC_CONFIGURED;
4882 rte_spinlock_unlock(&hw->lock);
4885 ret = hns3_map_rx_interrupt(dev);
4887 hw->adapter_state = HNS3_NIC_CONFIGURED;
4888 rte_spinlock_unlock(&hw->lock);
4893 * There are three register used to control the status of a TQP
4894 * (contains a pair of Tx queue and Rx queue) in the new version network
4895 * engine. One is used to control the enabling of Tx queue, the other is
4896 * used to control the enabling of Rx queue, and the last is the master
4897 * switch used to control the enabling of the tqp. The Tx register and
4898 * TQP register must be enabled at the same time to enable a Tx queue.
4899 * The same applies to the Rx queue. For the older network engine, this
4900 * function only refresh the enabled flag, and it is used to update the
4901 * status of queue in the dpdk framework.
4903 ret = hns3_start_all_txqs(dev);
4905 hw->adapter_state = HNS3_NIC_CONFIGURED;
4906 rte_spinlock_unlock(&hw->lock);
4910 ret = hns3_start_all_rxqs(dev);
4912 hns3_stop_all_txqs(dev);
4913 hw->adapter_state = HNS3_NIC_CONFIGURED;
4914 rte_spinlock_unlock(&hw->lock);
4918 hw->adapter_state = HNS3_NIC_STARTED;
4919 rte_spinlock_unlock(&hw->lock);
4921 hns3_rx_scattered_calc(dev);
4922 hns3_set_rxtx_function(dev);
4923 hns3_mp_req_start_rxtx(dev);
4924 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4926 hns3_restore_filter(dev);
4928 /* Enable interrupt of all rx queues before enabling queues */
4929 hns3_dev_all_rx_queue_intr_enable(hw, true);
4932 * After finished the initialization, enable tqps to receive/transmit
4933 * packets and refresh all queue status.
4935 hns3_start_tqps(hw);
4937 hns3_info(hw, "hns3 dev start successful!");
4942 hns3_do_stop(struct hns3_adapter *hns)
4944 struct hns3_hw *hw = &hns->hw;
4947 ret = hns3_cfg_mac_mode(hw, false);
4950 hw->mac.link_status = ETH_LINK_DOWN;
4952 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4953 hns3_configure_all_mac_addr(hns, true);
4954 ret = hns3_reset_all_tqps(hns);
4956 hns3_err(hw, "failed to reset all queues ret = %d.",
4961 hw->mac.default_addr_setted = false;
4966 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4968 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4969 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4970 struct hns3_adapter *hns = dev->data->dev_private;
4971 struct hns3_hw *hw = &hns->hw;
4972 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4973 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4976 if (dev->data->dev_conf.intr_conf.rxq == 0)
4979 /* unmap the ring with vector */
4980 if (rte_intr_allow_others(intr_handle)) {
4981 vec = RTE_INTR_VEC_RXTX_OFFSET;
4982 base = RTE_INTR_VEC_RXTX_OFFSET;
4984 if (rte_intr_dp_is_en(intr_handle)) {
4985 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4986 (void)hns3_bind_ring_with_vector(hw, vec, false,
4989 if (vec < base + intr_handle->nb_efd - 1)
4993 /* Clean datapath event and queue/vec mapping */
4994 rte_intr_efd_disable(intr_handle);
4995 if (intr_handle->intr_vec) {
4996 rte_free(intr_handle->intr_vec);
4997 intr_handle->intr_vec = NULL;
5002 hns3_dev_stop(struct rte_eth_dev *dev)
5004 struct hns3_adapter *hns = dev->data->dev_private;
5005 struct hns3_hw *hw = &hns->hw;
5007 PMD_INIT_FUNC_TRACE();
5008 dev->data->dev_started = 0;
5010 hw->adapter_state = HNS3_NIC_STOPPING;
5011 hns3_set_rxtx_function(dev);
5013 /* Disable datapath on secondary process. */
5014 hns3_mp_req_stop_rxtx(dev);
5015 /* Prevent crashes when queues are still in use. */
5016 rte_delay_ms(hw->tqps_num);
5018 rte_spinlock_lock(&hw->lock);
5019 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
5022 hns3_unmap_rx_interrupt(dev);
5023 hns3_dev_release_mbufs(hns);
5024 hw->adapter_state = HNS3_NIC_CONFIGURED;
5026 hns3_rx_scattered_reset(dev);
5027 rte_eal_alarm_cancel(hns3_service_handler, dev);
5028 rte_spinlock_unlock(&hw->lock);
5034 hns3_dev_close(struct rte_eth_dev *eth_dev)
5036 struct hns3_adapter *hns = eth_dev->data->dev_private;
5037 struct hns3_hw *hw = &hns->hw;
5040 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5041 rte_free(eth_dev->process_private);
5042 eth_dev->process_private = NULL;
5046 if (hw->adapter_state == HNS3_NIC_STARTED)
5047 ret = hns3_dev_stop(eth_dev);
5049 hw->adapter_state = HNS3_NIC_CLOSING;
5050 hns3_reset_abort(hns);
5051 hw->adapter_state = HNS3_NIC_CLOSED;
5053 hns3_configure_all_mc_mac_addr(hns, true);
5054 hns3_remove_all_vlan_table(hns);
5055 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5056 hns3_uninit_pf(eth_dev);
5057 hns3_free_all_queues(eth_dev);
5058 rte_free(hw->reset.wait_data);
5059 rte_free(eth_dev->process_private);
5060 eth_dev->process_private = NULL;
5061 hns3_mp_uninit_primary();
5062 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
5068 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5070 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5073 fc_conf->pause_time = pf->pause_time;
5075 /* return fc current mode */
5076 switch (hw->current_mode) {
5078 fc_conf->mode = RTE_FC_FULL;
5080 case HNS3_FC_TX_PAUSE:
5081 fc_conf->mode = RTE_FC_TX_PAUSE;
5083 case HNS3_FC_RX_PAUSE:
5084 fc_conf->mode = RTE_FC_RX_PAUSE;
5088 fc_conf->mode = RTE_FC_NONE;
5096 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5100 hw->requested_mode = HNS3_FC_NONE;
5102 case RTE_FC_RX_PAUSE:
5103 hw->requested_mode = HNS3_FC_RX_PAUSE;
5105 case RTE_FC_TX_PAUSE:
5106 hw->requested_mode = HNS3_FC_TX_PAUSE;
5109 hw->requested_mode = HNS3_FC_FULL;
5112 hw->requested_mode = HNS3_FC_NONE;
5113 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5114 "configured to RTE_FC_NONE", mode);
5120 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5122 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5126 if (fc_conf->high_water || fc_conf->low_water ||
5127 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5128 hns3_err(hw, "Unsupported flow control settings specified, "
5129 "high_water(%u), low_water(%u), send_xon(%u) and "
5130 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5131 fc_conf->high_water, fc_conf->low_water,
5132 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5135 if (fc_conf->autoneg) {
5136 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5139 if (!fc_conf->pause_time) {
5140 hns3_err(hw, "Invalid pause time %d setting.",
5141 fc_conf->pause_time);
5145 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5146 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5147 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5148 "current_fc_status = %d", hw->current_fc_status);
5152 hns3_get_fc_mode(hw, fc_conf->mode);
5153 if (hw->requested_mode == hw->current_mode &&
5154 pf->pause_time == fc_conf->pause_time)
5157 rte_spinlock_lock(&hw->lock);
5158 ret = hns3_fc_enable(dev, fc_conf);
5159 rte_spinlock_unlock(&hw->lock);
5165 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5166 struct rte_eth_pfc_conf *pfc_conf)
5168 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5173 if (!hns3_dev_dcb_supported(hw)) {
5174 hns3_err(hw, "This port does not support dcb configurations.");
5178 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5179 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5180 hns3_err(hw, "Unsupported flow control settings specified, "
5181 "high_water(%u), low_water(%u), send_xon(%u) and "
5182 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5183 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5184 pfc_conf->fc.send_xon,
5185 pfc_conf->fc.mac_ctrl_frame_fwd);
5188 if (pfc_conf->fc.autoneg) {
5189 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5192 if (pfc_conf->fc.pause_time == 0) {
5193 hns3_err(hw, "Invalid pause time %d setting.",
5194 pfc_conf->fc.pause_time);
5198 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5199 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5200 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5201 "current_fc_status = %d", hw->current_fc_status);
5205 priority = pfc_conf->priority;
5206 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5207 if (hw->dcb_info.pfc_en & BIT(priority) &&
5208 hw->requested_mode == hw->current_mode &&
5209 pfc_conf->fc.pause_time == pf->pause_time)
5212 rte_spinlock_lock(&hw->lock);
5213 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5214 rte_spinlock_unlock(&hw->lock);
5220 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5222 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5223 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5224 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5227 rte_spinlock_lock(&hw->lock);
5228 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5229 dcb_info->nb_tcs = pf->local_max_tc;
5231 dcb_info->nb_tcs = 1;
5233 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5234 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5235 for (i = 0; i < dcb_info->nb_tcs; i++)
5236 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5238 for (i = 0; i < hw->num_tc; i++) {
5239 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5240 dcb_info->tc_queue.tc_txq[0][i].base =
5241 hw->tc_queue[i].tqp_offset;
5242 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5243 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5244 hw->tc_queue[i].tqp_count;
5246 rte_spinlock_unlock(&hw->lock);
5252 hns3_reinit_dev(struct hns3_adapter *hns)
5254 struct hns3_hw *hw = &hns->hw;
5257 ret = hns3_cmd_init(hw);
5259 hns3_err(hw, "Failed to init cmd: %d", ret);
5263 ret = hns3_reset_all_tqps(hns);
5265 hns3_err(hw, "Failed to reset all queues: %d", ret);
5269 ret = hns3_init_hardware(hns);
5271 hns3_err(hw, "Failed to init hardware: %d", ret);
5275 ret = hns3_enable_hw_error_intr(hns, true);
5277 hns3_err(hw, "fail to enable hw error interrupts: %d",
5281 hns3_info(hw, "Reset done, driver initialization finished.");
5287 is_pf_reset_done(struct hns3_hw *hw)
5289 uint32_t val, reg, reg_bit;
5291 switch (hw->reset.level) {
5292 case HNS3_IMP_RESET:
5293 reg = HNS3_GLOBAL_RESET_REG;
5294 reg_bit = HNS3_IMP_RESET_BIT;
5296 case HNS3_GLOBAL_RESET:
5297 reg = HNS3_GLOBAL_RESET_REG;
5298 reg_bit = HNS3_GLOBAL_RESET_BIT;
5300 case HNS3_FUNC_RESET:
5301 reg = HNS3_FUN_RST_ING;
5302 reg_bit = HNS3_FUN_RST_ING_B;
5304 case HNS3_FLR_RESET:
5306 hns3_err(hw, "Wait for unsupported reset level: %d",
5310 val = hns3_read_dev(hw, reg);
5311 if (hns3_get_bit(val, reg_bit))
5318 hns3_is_reset_pending(struct hns3_adapter *hns)
5320 struct hns3_hw *hw = &hns->hw;
5321 enum hns3_reset_level reset;
5323 hns3_check_event_cause(hns, NULL);
5324 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5325 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5326 hns3_warn(hw, "High level reset %d is pending", reset);
5329 reset = hns3_get_reset_level(hns, &hw->reset.request);
5330 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5331 hns3_warn(hw, "High level reset %d is request", reset);
5338 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5340 struct hns3_hw *hw = &hns->hw;
5341 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5344 if (wait_data->result == HNS3_WAIT_SUCCESS)
5346 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5347 gettimeofday(&tv, NULL);
5348 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5349 tv.tv_sec, tv.tv_usec);
5351 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5354 wait_data->hns = hns;
5355 wait_data->check_completion = is_pf_reset_done;
5356 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5357 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5358 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5359 wait_data->count = HNS3_RESET_WAIT_CNT;
5360 wait_data->result = HNS3_WAIT_REQUEST;
5361 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5366 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5368 struct hns3_cmd_desc desc;
5369 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5371 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5372 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5373 req->fun_reset_vfid = func_id;
5375 return hns3_cmd_send(hw, &desc, 1);
5379 hns3_imp_reset_cmd(struct hns3_hw *hw)
5381 struct hns3_cmd_desc desc;
5383 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5384 desc.data[0] = 0xeedd;
5386 return hns3_cmd_send(hw, &desc, 1);
5390 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5392 struct hns3_hw *hw = &hns->hw;
5396 gettimeofday(&tv, NULL);
5397 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5398 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5399 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5400 tv.tv_sec, tv.tv_usec);
5404 switch (reset_level) {
5405 case HNS3_IMP_RESET:
5406 hns3_imp_reset_cmd(hw);
5407 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5408 tv.tv_sec, tv.tv_usec);
5410 case HNS3_GLOBAL_RESET:
5411 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5412 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5413 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5414 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5415 tv.tv_sec, tv.tv_usec);
5417 case HNS3_FUNC_RESET:
5418 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5419 tv.tv_sec, tv.tv_usec);
5420 /* schedule again to check later */
5421 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5422 hns3_schedule_reset(hns);
5425 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5428 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5431 static enum hns3_reset_level
5432 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5434 struct hns3_hw *hw = &hns->hw;
5435 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5437 /* Return the highest priority reset level amongst all */
5438 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5439 reset_level = HNS3_IMP_RESET;
5440 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5441 reset_level = HNS3_GLOBAL_RESET;
5442 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5443 reset_level = HNS3_FUNC_RESET;
5444 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5445 reset_level = HNS3_FLR_RESET;
5447 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5448 return HNS3_NONE_RESET;
5454 hns3_record_imp_error(struct hns3_adapter *hns)
5456 struct hns3_hw *hw = &hns->hw;
5459 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5460 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5461 hns3_warn(hw, "Detected IMP RD poison!");
5462 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5463 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5464 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5467 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5468 hns3_warn(hw, "Detected IMP CMDQ error!");
5469 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5470 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5471 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5476 hns3_prepare_reset(struct hns3_adapter *hns)
5478 struct hns3_hw *hw = &hns->hw;
5482 switch (hw->reset.level) {
5483 case HNS3_FUNC_RESET:
5484 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5489 * After performaning pf reset, it is not necessary to do the
5490 * mailbox handling or send any command to firmware, because
5491 * any mailbox handling or command to firmware is only valid
5492 * after hns3_cmd_init is called.
5494 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5495 hw->reset.stats.request_cnt++;
5497 case HNS3_IMP_RESET:
5498 hns3_record_imp_error(hns);
5499 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5500 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5501 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5510 hns3_set_rst_done(struct hns3_hw *hw)
5512 struct hns3_pf_rst_done_cmd *req;
5513 struct hns3_cmd_desc desc;
5515 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5516 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5517 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5518 return hns3_cmd_send(hw, &desc, 1);
5522 hns3_stop_service(struct hns3_adapter *hns)
5524 struct hns3_hw *hw = &hns->hw;
5525 struct rte_eth_dev *eth_dev;
5527 eth_dev = &rte_eth_devices[hw->data->port_id];
5528 if (hw->adapter_state == HNS3_NIC_STARTED)
5529 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5530 hw->mac.link_status = ETH_LINK_DOWN;
5532 hns3_set_rxtx_function(eth_dev);
5534 /* Disable datapath on secondary process. */
5535 hns3_mp_req_stop_rxtx(eth_dev);
5536 rte_delay_ms(hw->tqps_num);
5538 rte_spinlock_lock(&hw->lock);
5539 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5540 hw->adapter_state == HNS3_NIC_STOPPING) {
5541 hns3_enable_all_queues(hw, false);
5543 hw->reset.mbuf_deferred_free = true;
5545 hw->reset.mbuf_deferred_free = false;
5548 * It is cumbersome for hardware to pick-and-choose entries for deletion
5549 * from table space. Hence, for function reset software intervention is
5550 * required to delete the entries
5552 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5553 hns3_configure_all_mc_mac_addr(hns, true);
5554 rte_spinlock_unlock(&hw->lock);
5560 hns3_start_service(struct hns3_adapter *hns)
5562 struct hns3_hw *hw = &hns->hw;
5563 struct rte_eth_dev *eth_dev;
5565 if (hw->reset.level == HNS3_IMP_RESET ||
5566 hw->reset.level == HNS3_GLOBAL_RESET)
5567 hns3_set_rst_done(hw);
5568 eth_dev = &rte_eth_devices[hw->data->port_id];
5569 hns3_set_rxtx_function(eth_dev);
5570 hns3_mp_req_start_rxtx(eth_dev);
5571 if (hw->adapter_state == HNS3_NIC_STARTED) {
5572 hns3_service_handler(eth_dev);
5574 /* Enable interrupt of all rx queues before enabling queues */
5575 hns3_dev_all_rx_queue_intr_enable(hw, true);
5577 * When finished the initialization, enable queues to receive
5578 * and transmit packets.
5580 hns3_enable_all_queues(hw, true);
5587 hns3_restore_conf(struct hns3_adapter *hns)
5589 struct hns3_hw *hw = &hns->hw;
5592 ret = hns3_configure_all_mac_addr(hns, false);
5596 ret = hns3_configure_all_mc_mac_addr(hns, false);
5600 ret = hns3_dev_promisc_restore(hns);
5604 ret = hns3_restore_vlan_table(hns);
5608 ret = hns3_restore_vlan_conf(hns);
5612 ret = hns3_restore_all_fdir_filter(hns);
5616 ret = hns3_restore_rx_interrupt(hw);
5620 ret = hns3_restore_gro_conf(hw);
5624 ret = hns3_restore_fec(hw);
5628 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5629 ret = hns3_do_start(hns, false);
5632 hns3_info(hw, "hns3 dev restart successful!");
5633 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5634 hw->adapter_state = HNS3_NIC_CONFIGURED;
5638 hns3_configure_all_mc_mac_addr(hns, true);
5640 hns3_configure_all_mac_addr(hns, true);
5645 hns3_reset_service(void *param)
5647 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5648 struct hns3_hw *hw = &hns->hw;
5649 enum hns3_reset_level reset_level;
5650 struct timeval tv_delta;
5651 struct timeval tv_start;
5657 * The interrupt is not triggered within the delay time.
5658 * The interrupt may have been lost. It is necessary to handle
5659 * the interrupt to recover from the error.
5661 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5662 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5663 hns3_err(hw, "Handling interrupts in delayed tasks");
5664 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5665 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5666 if (reset_level == HNS3_NONE_RESET) {
5667 hns3_err(hw, "No reset level is set, try IMP reset");
5668 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5671 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5674 * Check if there is any ongoing reset in the hardware. This status can
5675 * be checked from reset_pending. If there is then, we need to wait for
5676 * hardware to complete reset.
5677 * a. If we are able to figure out in reasonable time that hardware
5678 * has fully resetted then, we can proceed with driver, client
5680 * b. else, we can come back later to check this status so re-sched
5683 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5684 if (reset_level != HNS3_NONE_RESET) {
5685 gettimeofday(&tv_start, NULL);
5686 ret = hns3_reset_process(hns, reset_level);
5687 gettimeofday(&tv, NULL);
5688 timersub(&tv, &tv_start, &tv_delta);
5689 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5690 tv_delta.tv_usec / USEC_PER_MSEC;
5691 if (msec > HNS3_RESET_PROCESS_MS)
5692 hns3_err(hw, "%d handle long time delta %" PRIx64
5693 " ms time=%ld.%.6ld",
5694 hw->reset.level, msec,
5695 tv.tv_sec, tv.tv_usec);
5700 /* Check if we got any *new* reset requests to be honored */
5701 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5702 if (reset_level != HNS3_NONE_RESET)
5703 hns3_msix_process(hns, reset_level);
5707 hns3_get_speed_capa_num(uint16_t device_id)
5711 switch (device_id) {
5712 case HNS3_DEV_ID_25GE:
5713 case HNS3_DEV_ID_25GE_RDMA:
5716 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5717 case HNS3_DEV_ID_200G_RDMA:
5729 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5732 switch (device_id) {
5733 case HNS3_DEV_ID_25GE:
5735 case HNS3_DEV_ID_25GE_RDMA:
5736 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5737 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5739 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5740 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5741 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5743 case HNS3_DEV_ID_100G_RDMA_MACSEC:
5744 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5745 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5747 case HNS3_DEV_ID_200G_RDMA:
5748 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5749 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5759 hns3_fec_get_capability(struct rte_eth_dev *dev,
5760 struct rte_eth_fec_capa *speed_fec_capa,
5763 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5764 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5765 uint16_t device_id = pci_dev->id.device_id;
5766 unsigned int capa_num;
5769 capa_num = hns3_get_speed_capa_num(device_id);
5770 if (capa_num == 0) {
5771 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5776 if (speed_fec_capa == NULL || num < capa_num)
5779 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5787 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5789 struct hns3_config_fec_cmd *req;
5790 struct hns3_cmd_desc desc;
5793 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5794 req = (struct hns3_config_fec_cmd *)desc.data;
5795 ret = hns3_cmd_send(hw, &desc, 1);
5797 hns3_err(hw, "get current fec auto state failed, ret = %d",
5802 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5807 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5809 #define QUERY_ACTIVE_SPEED 1
5810 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811 struct hns3_sfp_speed_cmd *resp;
5812 uint32_t tmp_fec_capa;
5814 struct hns3_cmd_desc desc;
5818 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5819 * configured FEC mode is returned.
5820 * If link is up, current FEC mode is returned.
5822 if (hw->mac.link_status == ETH_LINK_DOWN) {
5823 ret = get_current_fec_auto_state(hw, &auto_state);
5827 if (auto_state == 0x1) {
5828 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5833 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5834 resp = (struct hns3_sfp_speed_cmd *)desc.data;
5835 resp->query_type = QUERY_ACTIVE_SPEED;
5837 ret = hns3_cmd_send(hw, &desc, 1);
5838 if (ret == -EOPNOTSUPP) {
5839 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5842 hns3_err(hw, "get FEC failed, ret = %d", ret);
5847 * FEC mode order defined in hns3 hardware is inconsistend with
5848 * that defined in the ethdev library. So the sequence needs
5851 switch (resp->active_fec) {
5852 case HNS3_HW_FEC_MODE_NOFEC:
5853 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5855 case HNS3_HW_FEC_MODE_BASER:
5856 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5858 case HNS3_HW_FEC_MODE_RS:
5859 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5862 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5866 *fec_capa = tmp_fec_capa;
5871 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5873 struct hns3_config_fec_cmd *req;
5874 struct hns3_cmd_desc desc;
5877 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5879 req = (struct hns3_config_fec_cmd *)desc.data;
5881 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5882 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5883 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5885 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5886 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5887 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5889 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5890 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5891 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5893 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5894 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5899 ret = hns3_cmd_send(hw, &desc, 1);
5901 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5907 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5909 struct hns3_mac *mac = &hw->mac;
5912 switch (mac->link_speed) {
5913 case ETH_SPEED_NUM_10G:
5914 cur_capa = fec_capa[1].capa;
5916 case ETH_SPEED_NUM_25G:
5917 case ETH_SPEED_NUM_100G:
5918 case ETH_SPEED_NUM_200G:
5919 cur_capa = fec_capa[0].capa;
5930 is_fec_mode_one_bit_set(uint32_t mode)
5935 for (i = 0; i < sizeof(mode); i++)
5936 if (mode >> i & 0x1)
5939 return cnt == 1 ? true : false;
5943 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5945 #define FEC_CAPA_NUM 2
5946 struct hns3_adapter *hns = dev->data->dev_private;
5947 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5948 struct hns3_pf *pf = &hns->pf;
5950 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5952 uint32_t num = FEC_CAPA_NUM;
5955 ret = hns3_fec_get_capability(dev, fec_capa, num);
5959 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5960 if (!is_fec_mode_one_bit_set(mode))
5961 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
5962 "FEC mode should be only one bit set", mode);
5965 * Check whether the configured mode is within the FEC capability.
5966 * If not, the configured mode will not be supported.
5968 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
5969 if (!(cur_capa & mode)) {
5970 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
5974 ret = hns3_set_fec_hw(hw, mode);
5978 pf->fec_mode = mode;
5983 hns3_restore_fec(struct hns3_hw *hw)
5985 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
5986 struct hns3_pf *pf = &hns->pf;
5987 uint32_t mode = pf->fec_mode;
5990 ret = hns3_set_fec_hw(hw, mode);
5992 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
5999 hns3_query_dev_fec_info(struct rte_eth_dev *dev)
6001 struct hns3_adapter *hns = dev->data->dev_private;
6002 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6003 struct hns3_pf *pf = &hns->pf;
6006 ret = hns3_fec_get(dev, &pf->fec_mode);
6008 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6013 static const struct eth_dev_ops hns3_eth_dev_ops = {
6014 .dev_configure = hns3_dev_configure,
6015 .dev_start = hns3_dev_start,
6016 .dev_stop = hns3_dev_stop,
6017 .dev_close = hns3_dev_close,
6018 .promiscuous_enable = hns3_dev_promiscuous_enable,
6019 .promiscuous_disable = hns3_dev_promiscuous_disable,
6020 .allmulticast_enable = hns3_dev_allmulticast_enable,
6021 .allmulticast_disable = hns3_dev_allmulticast_disable,
6022 .mtu_set = hns3_dev_mtu_set,
6023 .stats_get = hns3_stats_get,
6024 .stats_reset = hns3_stats_reset,
6025 .xstats_get = hns3_dev_xstats_get,
6026 .xstats_get_names = hns3_dev_xstats_get_names,
6027 .xstats_reset = hns3_dev_xstats_reset,
6028 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6029 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6030 .dev_infos_get = hns3_dev_infos_get,
6031 .fw_version_get = hns3_fw_version_get,
6032 .rx_queue_setup = hns3_rx_queue_setup,
6033 .tx_queue_setup = hns3_tx_queue_setup,
6034 .rx_queue_release = hns3_dev_rx_queue_release,
6035 .tx_queue_release = hns3_dev_tx_queue_release,
6036 .rx_queue_start = hns3_dev_rx_queue_start,
6037 .rx_queue_stop = hns3_dev_rx_queue_stop,
6038 .tx_queue_start = hns3_dev_tx_queue_start,
6039 .tx_queue_stop = hns3_dev_tx_queue_stop,
6040 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6041 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6042 .rxq_info_get = hns3_rxq_info_get,
6043 .txq_info_get = hns3_txq_info_get,
6044 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6045 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6046 .flow_ctrl_get = hns3_flow_ctrl_get,
6047 .flow_ctrl_set = hns3_flow_ctrl_set,
6048 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6049 .mac_addr_add = hns3_add_mac_addr,
6050 .mac_addr_remove = hns3_remove_mac_addr,
6051 .mac_addr_set = hns3_set_default_mac_addr,
6052 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6053 .link_update = hns3_dev_link_update,
6054 .rss_hash_update = hns3_dev_rss_hash_update,
6055 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6056 .reta_update = hns3_dev_rss_reta_update,
6057 .reta_query = hns3_dev_rss_reta_query,
6058 .filter_ctrl = hns3_dev_filter_ctrl,
6059 .vlan_filter_set = hns3_vlan_filter_set,
6060 .vlan_tpid_set = hns3_vlan_tpid_set,
6061 .vlan_offload_set = hns3_vlan_offload_set,
6062 .vlan_pvid_set = hns3_vlan_pvid_set,
6063 .get_reg = hns3_get_regs,
6064 .get_dcb_info = hns3_get_dcb_info,
6065 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6066 .fec_get_capability = hns3_fec_get_capability,
6067 .fec_get = hns3_fec_get,
6068 .fec_set = hns3_fec_set,
6071 static const struct hns3_reset_ops hns3_reset_ops = {
6072 .reset_service = hns3_reset_service,
6073 .stop_service = hns3_stop_service,
6074 .prepare_reset = hns3_prepare_reset,
6075 .wait_hardware_ready = hns3_wait_hardware_ready,
6076 .reinit_dev = hns3_reinit_dev,
6077 .restore_conf = hns3_restore_conf,
6078 .start_service = hns3_start_service,
6082 hns3_dev_init(struct rte_eth_dev *eth_dev)
6084 struct hns3_adapter *hns = eth_dev->data->dev_private;
6085 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6086 struct rte_ether_addr *eth_addr;
6087 struct hns3_hw *hw = &hns->hw;
6090 PMD_INIT_FUNC_TRACE();
6092 eth_dev->process_private = (struct hns3_process_private *)
6093 rte_zmalloc_socket("hns3_filter_list",
6094 sizeof(struct hns3_process_private),
6095 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6096 if (eth_dev->process_private == NULL) {
6097 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6100 /* initialize flow filter lists */
6101 hns3_filterlist_init(eth_dev);
6103 hns3_set_rxtx_function(eth_dev);
6104 eth_dev->dev_ops = &hns3_eth_dev_ops;
6105 eth_dev->rx_queue_count = hns3_rx_queue_count;
6106 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6107 ret = hns3_mp_init_secondary();
6109 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6110 "process, ret = %d", ret);
6111 goto err_mp_init_secondary;
6114 hw->secondary_cnt++;
6118 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6120 ret = hns3_mp_init_primary();
6123 "Failed to init for primary process, ret = %d",
6125 goto err_mp_init_primary;
6128 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6130 hw->data = eth_dev->data;
6133 * Set default max packet size according to the mtu
6134 * default vale in DPDK frame.
6136 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6138 ret = hns3_reset_init(hw);
6140 goto err_init_reset;
6141 hw->reset.ops = &hns3_reset_ops;
6143 ret = hns3_init_pf(eth_dev);
6145 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6149 /* Allocate memory for storing MAC addresses */
6150 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6151 sizeof(struct rte_ether_addr) *
6152 HNS3_UC_MACADDR_NUM, 0);
6153 if (eth_dev->data->mac_addrs == NULL) {
6154 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6155 "to store MAC addresses",
6156 sizeof(struct rte_ether_addr) *
6157 HNS3_UC_MACADDR_NUM);
6159 goto err_rte_zmalloc;
6162 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6163 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6164 rte_eth_random_addr(hw->mac.mac_addr);
6165 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6166 (struct rte_ether_addr *)hw->mac.mac_addr);
6167 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6168 "unicast address, using random MAC address %s",
6171 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6172 ð_dev->data->mac_addrs[0]);
6174 hw->adapter_state = HNS3_NIC_INITIALIZED;
6176 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6177 hns3_err(hw, "Reschedule reset service after dev_init");
6178 hns3_schedule_reset(hns);
6180 /* IMP will wait ready flag before reset */
6181 hns3_notify_reset_ready(hw, false);
6184 hns3_info(hw, "hns3 dev initialization successful!");
6188 hns3_uninit_pf(eth_dev);
6191 rte_free(hw->reset.wait_data);
6194 hns3_mp_uninit_primary();
6196 err_mp_init_primary:
6197 err_mp_init_secondary:
6198 eth_dev->dev_ops = NULL;
6199 eth_dev->rx_pkt_burst = NULL;
6200 eth_dev->tx_pkt_burst = NULL;
6201 eth_dev->tx_pkt_prepare = NULL;
6202 rte_free(eth_dev->process_private);
6203 eth_dev->process_private = NULL;
6208 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6210 struct hns3_adapter *hns = eth_dev->data->dev_private;
6211 struct hns3_hw *hw = &hns->hw;
6213 PMD_INIT_FUNC_TRACE();
6215 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6218 if (hw->adapter_state < HNS3_NIC_CLOSING)
6219 hns3_dev_close(eth_dev);
6221 hw->adapter_state = HNS3_NIC_REMOVED;
6226 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6227 struct rte_pci_device *pci_dev)
6229 return rte_eth_dev_pci_generic_probe(pci_dev,
6230 sizeof(struct hns3_adapter),
6235 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6237 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6240 static const struct rte_pci_id pci_id_hns3_map[] = {
6241 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6242 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6243 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6244 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6245 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6246 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6247 { .vendor_id = 0, /* sentinel */ },
6250 static struct rte_pci_driver rte_hns3_pmd = {
6251 .id_table = pci_id_hns3_map,
6252 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6253 .probe = eth_hns3_pci_probe,
6254 .remove = eth_hns3_pci_remove,
6257 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6258 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6259 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6260 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6261 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);