drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVLID_PVID                0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59
  60 #define HNS3_RESET_WAIT_MS      100
  61 #define HNS3_RESET_WAIT_CNT     200
  62
  63 enum hns3_evt_cause {
  64         HNS3_VECTOR0_EVENT_RST,
  65         HNS3_VECTOR0_EVENT_MBX,
  66         HNS3_VECTOR0_EVENT_ERR,
  67         HNS3_VECTOR0_EVENT_OTHER,
  68 };
  69
  70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  71                                                  uint64_t *levels);
  72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  74                                     int on);
  75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  76
  77 static int hns3_add_mc_addr(struct hns3_hw *hw,
  78                             struct rte_ether_addr *mac_addr);
  79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  80                             struct rte_ether_addr *mac_addr);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_hw *hw = &hns->hw;
 312         struct hns3_pf *pf = &hns->pf;
 313         uint16_t vlan_id;
 314         int ret = 0;
 315
 316         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 317                 return hns3_vlan_pvid_configure(hns,
 318                                                 hw->port_base_vlan_cfg.pvid, 1);
 319
 320         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 321                 if (vlan_entry->hd_tbl_status) {
 322                         vlan_id = vlan_entry->vlan_id;
 323                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 324                         if (ret)
 325                                 break;
 326                 }
 327         }
 328
 329         return ret;
 330 }
 331
 332 static int
 333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 334 {
 335         struct hns3_hw *hw = &hns->hw;
 336         bool writen_to_tbl = false;
 337         int ret = 0;
 338
 339         /*
 340          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 341          * for normal packet, deleting vlan id 0 is not allowed.
 342          */
 343         if (on == 0 && vlan_id == 0)
 344                 return 0;
 345
 346         /*
 347          * When port base vlan enabled, we use port base vlan as the vlan
 348          * filter condition. In this case, we don't update vlan filter table
 349          * when user add new vlan or remove exist vlan, just update the
 350          * vlan list. The vlan id in vlan list will be writen in vlan filter
 351          * table until port base vlan disabled
 352          */
 353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 354                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 355                 writen_to_tbl = true;
 356         }
 357
 358         if (ret == 0 && vlan_id) {
 359                 if (on)
 360                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 361                 else
 362                         hns3_rm_dev_vlan_table(hns, vlan_id);
 363         }
 364         return ret;
 365 }
 366
 367 static int
 368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 369 {
 370         struct hns3_adapter *hns = dev->data->dev_private;
 371         struct hns3_hw *hw = &hns->hw;
 372         int ret;
 373
 374         rte_spinlock_lock(&hw->lock);
 375         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 376         rte_spinlock_unlock(&hw->lock);
 377         return ret;
 378 }
 379
 380 static int
 381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 382                          uint16_t tpid)
 383 {
 384         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 385         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 386         struct hns3_hw *hw = &hns->hw;
 387         struct hns3_cmd_desc desc;
 388         int ret;
 389
 390         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 391              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 392                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 393                 return -EINVAL;
 394         }
 395
 396         if (tpid != RTE_ETHER_TYPE_VLAN) {
 397                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 398                 return -EINVAL;
 399         }
 400
 401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 402         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 403
 404         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 405                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 406                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 407         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 408                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 412         }
 413
 414         ret = hns3_cmd_send(hw, &desc, 1);
 415         if (ret) {
 416                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 417                          ret);
 418                 return ret;
 419         }
 420
 421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 422
 423         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 424         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 425         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 426
 427         ret = hns3_cmd_send(hw, &desc, 1);
 428         if (ret)
 429                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 430                          ret);
 431         return ret;
 432 }
 433
 434 static int
 435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 436                    uint16_t tpid)
 437 {
 438         struct hns3_adapter *hns = dev->data->dev_private;
 439         struct hns3_hw *hw = &hns->hw;
 440         int ret;
 441
 442         rte_spinlock_lock(&hw->lock);
 443         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 444         rte_spinlock_unlock(&hw->lock);
 445         return ret;
 446 }
 447
 448 static int
 449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 450                              struct hns3_rx_vtag_cfg *vcfg)
 451 {
 452         struct hns3_vport_vtag_rx_cfg_cmd *req;
 453         struct hns3_hw *hw = &hns->hw;
 454         struct hns3_cmd_desc desc;
 455         uint16_t vport_id;
 456         uint8_t bitmap;
 457         int ret;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 460
 461         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 462         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 463                      vcfg->strip_tag1_en ? 1 : 0);
 464         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 465                      vcfg->strip_tag2_en ? 1 : 0);
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 467                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 469                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 470
 471         /*
 472          * In current version VF is not supported when PF is driven by DPDK
 473          * driver, just need to configure parameters for PF vport.
 474          */
 475         vport_id = HNS3_PF_FUNC_ID;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_hw *hw = &hns->hw;
 507         int ret;
 508
 509         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 510                 rxvlan_cfg.strip_tag1_en = false;
 511                 rxvlan_cfg.strip_tag2_en = enable;
 512         } else {
 513                 rxvlan_cfg.strip_tag1_en = enable;
 514                 rxvlan_cfg.strip_tag2_en = true;
 515         }
 516
 517         rxvlan_cfg.vlan1_vlan_prionly = false;
 518         rxvlan_cfg.vlan2_vlan_prionly = false;
 519         rxvlan_cfg.rx_vlan_offload_en = enable;
 520
 521         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 522         if (ret) {
 523                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 524                 return ret;
 525         }
 526
 527         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 534                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 535 {
 536         struct hns3_vlan_filter_ctrl_cmd *req;
 537         struct hns3_cmd_desc desc;
 538         int ret;
 539
 540         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 541
 542         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 543         req->vlan_type = vlan_type;
 544         req->vlan_fe = filter_en ? fe_type : 0;
 545         req->vf_id = vf_id;
 546
 547         ret = hns3_cmd_send(hw, &desc, 1);
 548         if (ret)
 549                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 550
 551         return ret;
 552 }
 553
 554 static int
 555 hns3_vlan_filter_init(struct hns3_adapter *hns)
 556 {
 557         struct hns3_hw *hw = &hns->hw;
 558         int ret;
 559
 560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 561                                         HNS3_FILTER_FE_EGRESS, false,
 562                                         HNS3_PF_FUNC_ID);
 563         if (ret) {
 564                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, false,
 570                                         HNS3_PF_FUNC_ID);
 571         if (ret)
 572                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 573
 574         return ret;
 575 }
 576
 577 static int
 578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 579 {
 580         struct hns3_hw *hw = &hns->hw;
 581         int ret;
 582
 583         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 584                                         HNS3_FILTER_FE_INGRESS, enable,
 585                                         HNS3_PF_FUNC_ID);
 586         if (ret)
 587                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 588                          enable ? "enable" : "disable", ret);
 589
 590         return ret;
 591 }
 592
 593 static int
 594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 595 {
 596         struct hns3_adapter *hns = dev->data->dev_private;
 597         struct hns3_hw *hw = &hns->hw;
 598         struct rte_eth_rxmode *rxmode;
 599         unsigned int tmp_mask;
 600         bool enable;
 601         int ret = 0;
 602
 603         rte_spinlock_lock(&hw->lock);
 604         rxmode = &dev->data->dev_conf.rxmode;
 605         tmp_mask = (unsigned int)mask;
 606         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 607                 /* ignore vlan filter configuration during promiscuous mode */
 608                 if (!dev->data->promiscuous) {
 609                         /* Enable or disable VLAN filter */
 610                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 611                                  true : false;
 612
 613                         ret = hns3_enable_vlan_filter(hns, enable);
 614                         if (ret) {
 615                                 rte_spinlock_unlock(&hw->lock);
 616                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 617                                          enable ? "enable" : "disable", ret);
 618                                 return ret;
 619                         }
 620                 }
 621         }
 622
 623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 624                 /* Enable or disable VLAN stripping */
 625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 626                     true : false;
 627
 628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 629                 if (ret) {
 630                         rte_spinlock_unlock(&hw->lock);
 631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 632                                  enable ? "enable" : "disable", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         rte_spinlock_unlock(&hw->lock);
 638
 639         return ret;
 640 }
 641
 642 static int
 643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 644                              struct hns3_tx_vtag_cfg *vcfg)
 645 {
 646         struct hns3_vport_vtag_tx_cfg_cmd *req;
 647         struct hns3_cmd_desc desc;
 648         struct hns3_hw *hw = &hns->hw;
 649         uint16_t vport_id;
 650         uint8_t bitmap;
 651         int ret;
 652
 653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 654
 655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 656         req->def_vlan_tag1 = vcfg->default_tag1;
 657         req->def_vlan_tag2 = vcfg->default_tag2;
 658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 659                      vcfg->accept_tag1 ? 1 : 0);
 660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 661                      vcfg->accept_untag1 ? 1 : 0);
 662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 663                      vcfg->accept_tag2 ? 1 : 0);
 664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 665                      vcfg->accept_untag2 ? 1 : 0);
 666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 667                      vcfg->insert_tag1_en ? 1 : 0);
 668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 669                      vcfg->insert_tag2_en ? 1 : 0);
 670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 671
 672         /*
 673          * In current version VF is not supported when PF is driven by DPDK
 674          * driver, just need to configure parameters for PF vport.
 675          */
 676         vport_id = HNS3_PF_FUNC_ID;
 677         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 678         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 679         req->vf_bitmap[req->vf_offset] = bitmap;
 680
 681         ret = hns3_cmd_send(hw, &desc, 1);
 682         if (ret)
 683                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 684
 685         return ret;
 686 }
 687
 688 static int
 689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 690                      uint16_t pvid)
 691 {
 692         struct hns3_hw *hw = &hns->hw;
 693         struct hns3_tx_vtag_cfg txvlan_cfg;
 694         int ret;
 695
 696         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 697                 txvlan_cfg.accept_tag1 = true;
 698                 txvlan_cfg.insert_tag1_en = false;
 699                 txvlan_cfg.default_tag1 = 0;
 700         } else {
 701                 txvlan_cfg.accept_tag1 = false;
 702                 txvlan_cfg.insert_tag1_en = true;
 703                 txvlan_cfg.default_tag1 = pvid;
 704         }
 705
 706         txvlan_cfg.accept_untag1 = true;
 707         txvlan_cfg.accept_tag2 = true;
 708         txvlan_cfg.accept_untag2 = true;
 709         txvlan_cfg.insert_tag2_en = false;
 710         txvlan_cfg.default_tag2 = 0;
 711
 712         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 713         if (ret) {
 714                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 715                          ret);
 716                 return ret;
 717         }
 718
 719         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 720         return ret;
 721 }
 722
 723 static void
 724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 725 {
 726         struct hns3_hw *hw = &hns->hw;
 727
 728         hw->port_base_vlan_cfg.state = on ?
 729             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 730
 731         hw->port_base_vlan_cfg.pvid = pvid;
 732 }
 733
 734 static void
 735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 736 {
 737         struct hns3_user_vlan_table *vlan_entry;
 738         struct hns3_pf *pf = &hns->pf;
 739
 740         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 741                 if (vlan_entry->hd_tbl_status)
 742                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 743
 744                 vlan_entry->hd_tbl_status = false;
 745         }
 746
 747         if (is_del_list) {
 748                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 749                 while (vlan_entry) {
 750                         LIST_REMOVE(vlan_entry, next);
 751                         rte_free(vlan_entry);
 752                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 }
 754         }
 755 }
 756
 757 static void
 758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 759 {
 760         struct hns3_user_vlan_table *vlan_entry;
 761         struct hns3_pf *pf = &hns->pf;
 762
 763         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 764                 if (!vlan_entry->hd_tbl_status)
 765                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 766
 767                 vlan_entry->hd_tbl_status = true;
 768         }
 769 }
 770
 771 static void
 772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_hw *hw = &hns->hw;
 775         int ret;
 776
 777         hns3_rm_all_vlan_table(hns, true);
 778         if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 779                 ret = hns3_set_port_vlan_filter(hns,
 780                                                 hw->port_base_vlan_cfg.pvid, 0);
 781                 if (ret) {
 782                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 783                                  ret);
 784                         return;
 785                 }
 786         }
 787 }
 788
 789 static int
 790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 791                                 uint16_t port_base_vlan_state,
 792                                 uint16_t new_pvid, uint16_t old_pvid)
 793 {
 794         struct hns3_hw *hw = &hns->hw;
 795         int ret = 0;
 796
 797         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 798                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 799                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 800                         if (ret) {
 801                                 hns3_err(hw,
 802                                          "Failed to clear clear old pvid filter, ret =%d",
 803                                          ret);
 804                                 return ret;
 805                         }
 806                 }
 807
 808                 hns3_rm_all_vlan_table(hns, false);
 809                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 810         }
 811
 812         if (new_pvid != 0) {
 813                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 814                 if (ret) {
 815                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 816                                  ret);
 817                         return ret;
 818                 }
 819         }
 820
 821         if (new_pvid == hw->port_base_vlan_cfg.pvid)
 822                 hns3_add_all_vlan_table(hns);
 823
 824         return ret;
 825 }
 826
 827 static int
 828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 829 {
 830         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 831         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 832         bool rx_strip_en;
 833         int ret;
 834
 835         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
 836         if (on) {
 837                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 838                 rx_vlan_cfg.strip_tag2_en = true;
 839         } else {
 840                 rx_vlan_cfg.strip_tag1_en = false;
 841                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 842         }
 843         rx_vlan_cfg.vlan1_vlan_prionly = false;
 844         rx_vlan_cfg.vlan2_vlan_prionly = false;
 845         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 846
 847         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 848         if (ret)
 849                 return ret;
 850
 851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 852         return ret;
 853 }
 854
 855 static int
 856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 857 {
 858         struct hns3_hw *hw = &hns->hw;
 859         uint16_t port_base_vlan_state;
 860         uint16_t old_pvid;
 861         int ret;
 862
 863         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 864                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 865                         hns3_warn(hw, "Invalid operation! As current pvid set "
 866                                   "is %u, disable pvid %u is invalid",
 867                                   hw->port_base_vlan_cfg.pvid, pvid);
 868                 return 0;
 869         }
 870
 871         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 872                                     HNS3_PORT_BASE_VLAN_DISABLE;
 873         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 874         if (ret) {
 875                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 876                          ret);
 877                 return ret;
 878         }
 879
 880         ret = hns3_en_pvid_strip(hns, on);
 881         if (ret) {
 882                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 883                          "ret = %d", ret);
 884                 return ret;
 885         }
 886
 887         if (pvid == HNS3_INVLID_PVID)
 888                 goto out;
 889         old_pvid = hw->port_base_vlan_cfg.pvid;
 890         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 891                                               old_pvid);
 892         if (ret) {
 893                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 894                          ret);
 895                 return ret;
 896         }
 897
 898 out:
 899         hns3_store_port_base_vlan_info(hns, pvid, on);
 900         return ret;
 901 }
 902
 903 static int
 904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 905 {
 906         struct hns3_adapter *hns = dev->data->dev_private;
 907         struct hns3_hw *hw = &hns->hw;
 908         bool pvid_en_state_change;
 909         uint16_t pvid_state;
 910         int ret;
 911
 912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 914                          RTE_ETHER_MAX_VLAN_ID);
 915                 return -EINVAL;
 916         }
 917
 918         /*
 919          * If PVID configuration state change, should refresh the PVID
 920          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 921          */
 922         pvid_state = hw->port_base_vlan_cfg.state;
 923         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 924             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 925                 pvid_en_state_change = false;
 926         else
 927                 pvid_en_state_change = true;
 928
 929         rte_spinlock_lock(&hw->lock);
 930         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 931         rte_spinlock_unlock(&hw->lock);
 932         if (ret)
 933                 return ret;
 934
 935         if (pvid_en_state_change)
 936                 hns3_update_all_queues_pvid_state(hw);
 937
 938         return 0;
 939 }
 940
 941 static void
 942 init_port_base_vlan_info(struct hns3_hw *hw)
 943 {
 944         hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 945         hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 946 }
 947
 948 static int
 949 hns3_default_vlan_config(struct hns3_adapter *hns)
 950 {
 951         struct hns3_hw *hw = &hns->hw;
 952         int ret;
 953
 954         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 955         if (ret)
 956                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 957         return ret;
 958 }
 959
 960 static int
 961 hns3_init_vlan_config(struct hns3_adapter *hns)
 962 {
 963         struct hns3_hw *hw = &hns->hw;
 964         int ret;
 965
 966         /*
 967          * This function can be called in the initialization and reset process,
 968          * when in reset process, it means that hardware had been reseted
 969          * successfully and we need to restore the hardware configuration to
 970          * ensure that the hardware configuration remains unchanged before and
 971          * after reset.
 972          */
 973         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 974                 init_port_base_vlan_info(hw);
 975
 976         ret = hns3_vlan_filter_init(hns);
 977         if (ret) {
 978                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 979                 return ret;
 980         }
 981
 982         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 983                                        RTE_ETHER_TYPE_VLAN);
 984         if (ret) {
 985                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 986                 return ret;
 987         }
 988
 989         /*
 990          * When in the reinit dev stage of the reset process, the following
 991          * vlan-related configurations may differ from those at initialization,
 992          * we will restore configurations to hardware in hns3_restore_vlan_table
 993          * and hns3_restore_vlan_conf later.
 994          */
 995         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 996                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 997                 if (ret) {
 998                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 999                         return ret;
1000                 }
1001
1002                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1003                 if (ret) {
1004                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1005                                  ret);
1006                         return ret;
1007                 }
1008         }
1009
1010         return hns3_default_vlan_config(hns);
1011 }
1012
1013 static int
1014 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1015 {
1016         struct hns3_pf *pf = &hns->pf;
1017         struct hns3_hw *hw = &hns->hw;
1018         uint64_t offloads;
1019         bool enable;
1020         int ret;
1021
1022         if (!hw->data->promiscuous) {
1023                 /* restore vlan filter states */
1024                 offloads = hw->data->dev_conf.rxmode.offloads;
1025                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1026                 ret = hns3_enable_vlan_filter(hns, enable);
1027                 if (ret) {
1028                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1029                                  "ret = %d", ret);
1030                         return ret;
1031                 }
1032         }
1033
1034         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1035         if (ret) {
1036                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1037                 return ret;
1038         }
1039
1040         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1041         if (ret)
1042                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1043
1044         return ret;
1045 }
1046
1047 static int
1048 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1049 {
1050         struct hns3_adapter *hns = dev->data->dev_private;
1051         struct rte_eth_dev_data *data = dev->data;
1052         struct rte_eth_txmode *txmode;
1053         struct hns3_hw *hw = &hns->hw;
1054         int mask;
1055         int ret;
1056
1057         txmode = &data->dev_conf.txmode;
1058         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1059                 hns3_warn(hw,
1060                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1061                           "configuration is not supported! Ignore these two "
1062                           "parameters: hw_vlan_reject_tagged(%d), "
1063                           "hw_vlan_reject_untagged(%d)",
1064                           txmode->hw_vlan_reject_tagged,
1065                           txmode->hw_vlan_reject_untagged);
1066
1067         /* Apply vlan offload setting */
1068         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1069         ret = hns3_vlan_offload_set(dev, mask);
1070         if (ret) {
1071                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1072                          ret);
1073                 return ret;
1074         }
1075
1076         /*
1077          * If pvid config is not set in rte_eth_conf, driver needn't to set
1078          * VLAN pvid related configuration to hardware.
1079          */
1080         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1081                 return 0;
1082
1083         /* Apply pvid setting */
1084         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1085                                  txmode->hw_vlan_insert_pvid);
1086         if (ret)
1087                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1088                          txmode->pvid, ret);
1089
1090         return ret;
1091 }
1092
1093 static int
1094 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1095                 unsigned int tso_mss_max)
1096 {
1097         struct hns3_cfg_tso_status_cmd *req;
1098         struct hns3_cmd_desc desc;
1099         uint16_t tso_mss;
1100
1101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1102
1103         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1104
1105         tso_mss = 0;
1106         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1107                        tso_mss_min);
1108         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1109
1110         tso_mss = 0;
1111         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1112                        tso_mss_max);
1113         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1114
1115         return hns3_cmd_send(hw, &desc, 1);
1116 }
1117
1118 static int
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120                    uint16_t *allocated_size, bool is_alloc)
1121 {
1122         struct hns3_umv_spc_alc_cmd *req;
1123         struct hns3_cmd_desc desc;
1124         int ret;
1125
1126         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129         req->space_size = rte_cpu_to_le_32(space_size);
1130
1131         ret = hns3_cmd_send(hw, &desc, 1);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134                              is_alloc ? "allocate" : "free", ret);
1135                 return ret;
1136         }
1137
1138         if (is_alloc && allocated_size)
1139                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1140
1141         return 0;
1142 }
1143
1144 static int
1145 hns3_init_umv_space(struct hns3_hw *hw)
1146 {
1147         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148         struct hns3_pf *pf = &hns->pf;
1149         uint16_t allocated_size = 0;
1150         int ret;
1151
1152         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1153                                  true);
1154         if (ret)
1155                 return ret;
1156
1157         if (allocated_size < pf->wanted_umv_size)
1158                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159                              pf->wanted_umv_size, allocated_size);
1160
1161         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162                                                 pf->wanted_umv_size;
1163         pf->used_umv_size = 0;
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         int ret;
1173
1174         if (pf->max_umv_size == 0)
1175                 return 0;
1176
1177         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1178         if (ret)
1179                 return ret;
1180
1181         pf->max_umv_size = 0;
1182
1183         return 0;
1184 }
1185
1186 static bool
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1188 {
1189         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190         struct hns3_pf *pf = &hns->pf;
1191         bool is_full;
1192
1193         is_full = (pf->used_umv_size >= pf->max_umv_size);
1194
1195         return is_full;
1196 }
1197
1198 static void
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1200 {
1201         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202         struct hns3_pf *pf = &hns->pf;
1203
1204         if (is_free) {
1205                 if (pf->used_umv_size > 0)
1206                         pf->used_umv_size--;
1207         } else
1208                 pf->used_umv_size++;
1209 }
1210
1211 static void
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213                       const uint8_t *addr, bool is_mc)
1214 {
1215         const unsigned char *mac_addr = addr;
1216         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217                             ((uint32_t)mac_addr[2] << 16) |
1218                             ((uint32_t)mac_addr[1] << 8) |
1219                             (uint32_t)mac_addr[0];
1220         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1221
1222         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1223         if (is_mc) {
1224                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1227         }
1228
1229         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1231 }
1232
1233 static int
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1235                              uint8_t resp_code,
1236                              enum hns3_mac_vlan_tbl_opcode op)
1237 {
1238         if (cmdq_resp) {
1239                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1240                          cmdq_resp);
1241                 return -EIO;
1242         }
1243
1244         if (op == HNS3_MAC_VLAN_ADD) {
1245                 if (resp_code == 0 || resp_code == 1) {
1246                         return 0;
1247                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248                         hns3_err(hw, "add mac addr failed for uc_overflow");
1249                         return -ENOSPC;
1250                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251                         hns3_err(hw, "add mac addr failed for mc_overflow");
1252                         return -ENOSPC;
1253                 }
1254
1255                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1256                          resp_code);
1257                 return -EIO;
1258         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259                 if (resp_code == 0) {
1260                         return 0;
1261                 } else if (resp_code == 1) {
1262                         hns3_dbg(hw, "remove mac addr failed for miss");
1263                         return -ENOENT;
1264                 }
1265
1266                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1267                          resp_code);
1268                 return -EIO;
1269         } else if (op == HNS3_MAC_VLAN_LKUP) {
1270                 if (resp_code == 0) {
1271                         return 0;
1272                 } else if (resp_code == 1) {
1273                         hns3_dbg(hw, "lookup mac addr failed for miss");
1274                         return -ENOENT;
1275                 }
1276
1277                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1278                          resp_code);
1279                 return -EIO;
1280         }
1281
1282         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1283                  op);
1284
1285         return -EINVAL;
1286 }
1287
1288 static int
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1291                          struct hns3_cmd_desc *desc, bool is_mc)
1292 {
1293         uint8_t resp_code;
1294         uint16_t retval;
1295         int ret;
1296
1297         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1298         if (is_mc) {
1299                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 memcpy(desc[0].data, req,
1301                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1303                                           true);
1304                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1306                                           true);
1307                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1308         } else {
1309                 memcpy(desc[0].data, req,
1310                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311                 ret = hns3_cmd_send(hw, desc, 1);
1312         }
1313         if (ret) {
1314                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1315                          ret);
1316                 return ret;
1317         }
1318         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319         retval = rte_le_to_cpu_16(desc[0].retval);
1320
1321         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322                                             HNS3_MAC_VLAN_LKUP);
1323 }
1324
1325 static int
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1328                       struct hns3_cmd_desc *mc_desc)
1329 {
1330         uint8_t resp_code;
1331         uint16_t retval;
1332         int cfg_status;
1333         int ret;
1334
1335         if (mc_desc == NULL) {
1336                 struct hns3_cmd_desc desc;
1337
1338                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339                 memcpy(desc.data, req,
1340                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341                 ret = hns3_cmd_send(hw, &desc, 1);
1342                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343                 retval = rte_le_to_cpu_16(desc.retval);
1344
1345                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1346                                                           HNS3_MAC_VLAN_ADD);
1347         } else {
1348                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354                 memcpy(mc_desc[0].data, req,
1355                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356                 mc_desc[0].retval = 0;
1357                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1360
1361                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1362                                                           HNS3_MAC_VLAN_ADD);
1363         }
1364
1365         if (ret) {
1366                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1367                 return ret;
1368         }
1369
1370         return cfg_status;
1371 }
1372
1373 static int
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1376 {
1377         struct hns3_cmd_desc desc;
1378         uint8_t resp_code;
1379         uint16_t retval;
1380         int ret;
1381
1382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1383
1384         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1385
1386         ret = hns3_cmd_send(hw, &desc, 1);
1387         if (ret) {
1388                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1389                 return ret;
1390         }
1391         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392         retval = rte_le_to_cpu_16(desc.retval);
1393
1394         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395                                             HNS3_MAC_VLAN_REMOVE);
1396 }
1397
1398 static int
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1400 {
1401         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402         struct hns3_mac_vlan_tbl_entry_cmd req;
1403         struct hns3_pf *pf = &hns->pf;
1404         struct hns3_cmd_desc desc;
1405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406         uint16_t egress_port = 0;
1407         uint8_t vf_id;
1408         int ret;
1409
1410         /* check if mac addr is valid */
1411         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1413                                       mac_addr);
1414                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1415                          mac_str);
1416                 return -EINVAL;
1417         }
1418
1419         memset(&req, 0, sizeof(req));
1420
1421         /*
1422          * In current version VF is not supported when PF is driven by DPDK
1423          * driver, just need to configure parameters for PF vport.
1424          */
1425         vf_id = HNS3_PF_FUNC_ID;
1426         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427                        HNS3_MAC_EPORT_VFID_S, vf_id);
1428
1429         req.egress_port = rte_cpu_to_le_16(egress_port);
1430
1431         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1432
1433         /*
1434          * Lookup the mac address in the mac_vlan table, and add
1435          * it if the entry is inexistent. Repeated unicast entry
1436          * is not allowed in the mac vlan table.
1437          */
1438         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439         if (ret == -ENOENT) {
1440                 if (!hns3_is_umv_space_full(hw)) {
1441                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1442                         if (!ret)
1443                                 hns3_update_umv_space(hw, false);
1444                         return ret;
1445                 }
1446
1447                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1448
1449                 return -ENOSPC;
1450         }
1451
1452         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1453
1454         /* check if we just hit the duplicate */
1455         if (ret == 0) {
1456                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1457                 return 0;
1458         }
1459
1460         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1461                  mac_str);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1468 {
1469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470         struct rte_ether_addr *addr;
1471         int ret;
1472         int i;
1473
1474         for (i = 0; i < hw->mc_addrs_num; i++) {
1475                 addr = &hw->mc_addrs[i];
1476                 /* Check if there are duplicate addresses */
1477                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                               addr);
1480                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1481                                  "(%s) is added by the set_mc_mac_addr_list "
1482                                  "API", mac_str);
1483                         return -EINVAL;
1484                 }
1485         }
1486
1487         ret = hns3_add_mc_addr(hw, mac_addr);
1488         if (ret) {
1489                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490                                       mac_addr);
1491                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1492                          mac_str, ret);
1493         }
1494         return ret;
1495 }
1496
1497 static int
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1499 {
1500         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1501         int ret;
1502
1503         ret = hns3_remove_mc_addr(hw, mac_addr);
1504         if (ret) {
1505                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1506                                       mac_addr);
1507                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1508                          mac_str, ret);
1509         }
1510         return ret;
1511 }
1512
1513 static int
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515                   uint32_t idx, __rte_unused uint32_t pool)
1516 {
1517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519         int ret;
1520
1521         rte_spinlock_lock(&hw->lock);
1522
1523         /*
1524          * In hns3 network engine adding UC and MC mac address with different
1525          * commands with firmware. We need to determine whether the input
1526          * address is a UC or a MC address to call different commands.
1527          * By the way, it is recommended calling the API function named
1528          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530          * may affect the specifications of UC mac addresses.
1531          */
1532         if (rte_is_multicast_ether_addr(mac_addr))
1533                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1534         else
1535                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1536
1537         if (ret) {
1538                 rte_spinlock_unlock(&hw->lock);
1539                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540                                       mac_addr);
1541                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1542                          ret);
1543                 return ret;
1544         }
1545
1546         if (idx == 0)
1547                 hw->mac.default_addr_setted = true;
1548         rte_spinlock_unlock(&hw->lock);
1549
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1555 {
1556         struct hns3_mac_vlan_tbl_entry_cmd req;
1557         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1558         int ret;
1559
1560         /* check if mac addr is valid */
1561         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1563                                       mac_addr);
1564                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1565                          mac_str);
1566                 return -EINVAL;
1567         }
1568
1569         memset(&req, 0, sizeof(req));
1570         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1574                 return 0;
1575         else if (ret == 0)
1576                 hns3_update_umv_space(hw, true);
1577
1578         return ret;
1579 }
1580
1581 static void
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1583 {
1584         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         /* index will be checked by upper level rte interface */
1586         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         if (rte_is_multicast_ether_addr(mac_addr))
1593                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1594         else
1595                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596         rte_spinlock_unlock(&hw->lock);
1597         if (ret) {
1598                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                       mac_addr);
1600                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1601                          ret);
1602         }
1603 }
1604
1605 static int
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607                           struct rte_ether_addr *mac_addr)
1608 {
1609         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct rte_ether_addr *oaddr;
1611         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612         bool default_addr_setted;
1613         bool rm_succes = false;
1614         int ret, ret_val;
1615
1616         /*
1617          * It has been guaranteed that input parameter named mac_addr is valid
1618          * address in the rte layer of DPDK framework.
1619          */
1620         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621         default_addr_setted = hw->mac.default_addr_setted;
1622         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1623                 return 0;
1624
1625         rte_spinlock_lock(&hw->lock);
1626         if (default_addr_setted) {
1627                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1628                 if (ret) {
1629                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                               oaddr);
1631                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1632                                   mac_str, ret);
1633                         rm_succes = false;
1634                 } else
1635                         rm_succes = true;
1636         }
1637
1638         ret = hns3_add_uc_addr_common(hw, mac_addr);
1639         if (ret) {
1640                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1641                                       mac_addr);
1642                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643                 goto err_add_uc_addr;
1644         }
1645
1646         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1647         if (ret) {
1648                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649                 goto err_pause_addr_cfg;
1650         }
1651
1652         rte_ether_addr_copy(mac_addr,
1653                             (struct rte_ether_addr *)hw->mac.mac_addr);
1654         hw->mac.default_addr_setted = true;
1655         rte_spinlock_unlock(&hw->lock);
1656
1657         return 0;
1658
1659 err_pause_addr_cfg:
1660         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1661         if (ret_val) {
1662                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663                                       mac_addr);
1664                 hns3_warn(hw,
1665                           "Failed to roll back to del setted mac addr(%s): %d",
1666                           mac_str, ret_val);
1667         }
1668
1669 err_add_uc_addr:
1670         if (rm_succes) {
1671                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1672                 if (ret_val) {
1673                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674                                               oaddr);
1675                         hns3_warn(hw,
1676                                   "Failed to restore old uc mac addr(%s): %d",
1677                                   mac_str, ret_val);
1678                         hw->mac.default_addr_setted = false;
1679                 }
1680         }
1681         rte_spinlock_unlock(&hw->lock);
1682
1683         return ret;
1684 }
1685
1686 static int
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1688 {
1689         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690         struct hns3_hw *hw = &hns->hw;
1691         struct rte_ether_addr *addr;
1692         int err = 0;
1693         int ret;
1694         int i;
1695
1696         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697                 addr = &hw->data->mac_addrs[i];
1698                 if (rte_is_zero_ether_addr(addr))
1699                         continue;
1700                 if (rte_is_multicast_ether_addr(addr))
1701                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1702                               hns3_add_mc_addr(hw, addr);
1703                 else
1704                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705                               hns3_add_uc_addr_common(hw, addr);
1706
1707                 if (ret) {
1708                         err = ret;
1709                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                               addr);
1711                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712                                  "ret = %d.", del ? "remove" : "restore",
1713                                  mac_str, i, ret);
1714                 }
1715         }
1716         return err;
1717 }
1718
1719 static void
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1721 {
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1723         uint8_t word_num;
1724         uint8_t bit_num;
1725
1726         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727                 word_num = vfid / 32;
1728                 bit_num = vfid % 32;
1729                 if (clr)
1730                         desc[1].data[word_num] &=
1731                             rte_cpu_to_le_32(~(1UL << bit_num));
1732                 else
1733                         desc[1].data[word_num] |=
1734                             rte_cpu_to_le_32(1UL << bit_num);
1735         } else {
1736                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737                 bit_num = vfid % 32;
1738                 if (clr)
1739                         desc[2].data[word_num] &=
1740                             rte_cpu_to_le_32(~(1UL << bit_num));
1741                 else
1742                         desc[2].data[word_num] |=
1743                             rte_cpu_to_le_32(1UL << bit_num);
1744         }
1745 }
1746
1747 static int
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_mac_vlan_tbl_entry_cmd req;
1751         struct hns3_cmd_desc desc[3];
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         uint8_t vf_id;
1754         int ret;
1755
1756         /* Check if mac addr is valid */
1757         if (!rte_is_multicast_ether_addr(mac_addr)) {
1758                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1759                                       mac_addr);
1760                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1761                          mac_str);
1762                 return -EINVAL;
1763         }
1764
1765         memset(&req, 0, sizeof(req));
1766         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1769         if (ret) {
1770                 /* This mac addr do not exist, add new entry for it */
1771                 memset(desc[0].data, 0, sizeof(desc[0].data));
1772                 memset(desc[1].data, 0, sizeof(desc[0].data));
1773                 memset(desc[2].data, 0, sizeof(desc[0].data));
1774         }
1775
1776         /*
1777          * In current version VF is not supported when PF is driven by DPDK
1778          * driver, just need to configure parameters for PF vport.
1779          */
1780         vf_id = HNS3_PF_FUNC_ID;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, just need to configure parameters for PF vport.
1821                  */
1822                 vf_id = HNS3_PF_FUNC_ID;
1823                 hns3_update_desc_vfid(desc, vf_id, true);
1824
1825                 /* All the vfid is zero, so need to delete this entry */
1826                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827         } else if (ret == -ENOENT) {
1828                 /* This mac addr doesn't exist. */
1829                 return 0;
1830         }
1831
1832         if (ret) {
1833                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1834                                       mac_addr);
1835                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1836         }
1837
1838         return ret;
1839 }
1840
1841 static int
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843                            struct rte_ether_addr *mc_addr_set,
1844                            uint32_t nb_mc_addr)
1845 {
1846         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847         struct rte_ether_addr *addr;
1848         uint32_t i;
1849         uint32_t j;
1850
1851         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853                          "invalid. valid range: 0~%d",
1854                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1855                 return -EINVAL;
1856         }
1857
1858         /* Check if input mac addresses are valid */
1859         for (i = 0; i < nb_mc_addr; i++) {
1860                 addr = &mc_addr_set[i];
1861                 if (!rte_is_multicast_ether_addr(addr)) {
1862                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1863                                               addr);
1864                         hns3_err(hw,
1865                                  "failed to set mc mac addr, addr(%s) invalid.",
1866                                  mac_str);
1867                         return -EINVAL;
1868                 }
1869
1870                 /* Check if there are duplicate addresses */
1871                 for (j = i + 1; j < nb_mc_addr; j++) {
1872                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873                                 rte_ether_format_addr(mac_str,
1874                                                       RTE_ETHER_ADDR_FMT_SIZE,
1875                                                       addr);
1876                                 hns3_err(hw, "failed to set mc mac addr, "
1877                                          "addrs invalid. two same addrs(%s).",
1878                                          mac_str);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882
1883                 /*
1884                  * Check if there are duplicate addresses between mac_addrs
1885                  * and mc_addr_set
1886                  */
1887                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888                         if (rte_is_same_ether_addr(addr,
1889                                                    &hw->data->mac_addrs[j])) {
1890                                 rte_ether_format_addr(mac_str,
1891                                                       RTE_ETHER_ADDR_FMT_SIZE,
1892                                                       addr);
1893                                 hns3_err(hw, "failed to set mc mac addr, "
1894                                          "addrs invalid. addrs(%s) has already "
1895                                          "configured in mac_addr add API",
1896                                          mac_str);
1897                                 return -EINVAL;
1898                         }
1899                 }
1900         }
1901
1902         return 0;
1903 }
1904
1905 static void
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907                            struct rte_ether_addr *mc_addr_set,
1908                            int mc_addr_num,
1909                            struct rte_ether_addr *reserved_addr_list,
1910                            int *reserved_addr_num,
1911                            struct rte_ether_addr *add_addr_list,
1912                            int *add_addr_num,
1913                            struct rte_ether_addr *rm_addr_list,
1914                            int *rm_addr_num)
1915 {
1916         struct rte_ether_addr *addr;
1917         int current_addr_num;
1918         int reserved_num = 0;
1919         int add_num = 0;
1920         int rm_num = 0;
1921         int num;
1922         int i;
1923         int j;
1924         bool same_addr;
1925
1926         /* Calculate the mc mac address list that should be removed */
1927         current_addr_num = hw->mc_addrs_num;
1928         for (i = 0; i < current_addr_num; i++) {
1929                 addr = &hw->mc_addrs[i];
1930                 same_addr = false;
1931                 for (j = 0; j < mc_addr_num; j++) {
1932                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1933                                 same_addr = true;
1934                                 break;
1935                         }
1936                 }
1937
1938                 if (!same_addr) {
1939                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1940                         rm_num++;
1941                 } else {
1942                         rte_ether_addr_copy(addr,
1943                                             &reserved_addr_list[reserved_num]);
1944                         reserved_num++;
1945                 }
1946         }
1947
1948         /* Calculate the mc mac address list that should be added */
1949         for (i = 0; i < mc_addr_num; i++) {
1950                 addr = &mc_addr_set[i];
1951                 same_addr = false;
1952                 for (j = 0; j < current_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1961                         add_num++;
1962                 }
1963         }
1964
1965         /* Reorder the mc mac address list maintained by driver */
1966         for (i = 0; i < reserved_num; i++)
1967                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1968
1969         for (i = 0; i < rm_num; i++) {
1970                 num = reserved_num + i;
1971                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1972         }
1973
1974         *reserved_addr_num = reserved_num;
1975         *add_addr_num = add_num;
1976         *rm_addr_num = rm_num;
1977 }
1978
1979 static int
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981                           struct rte_ether_addr *mc_addr_set,
1982                           uint32_t nb_mc_addr)
1983 {
1984         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr *addr;
1989         int reserved_addr_num;
1990         int add_addr_num;
1991         int rm_addr_num;
1992         int mc_addr_num;
1993         int num;
1994         int ret;
1995         int i;
1996
1997         /* Check if input parameters are valid */
1998         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1999         if (ret)
2000                 return ret;
2001
2002         rte_spinlock_lock(&hw->lock);
2003
2004         /*
2005          * Calculate the mc mac address lists those should be removed and be
2006          * added, Reorder the mc mac address list maintained by driver.
2007          */
2008         mc_addr_num = (int)nb_mc_addr;
2009         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010                                    reserved_addr_list, &reserved_addr_num,
2011                                    add_addr_list, &add_addr_num,
2012                                    rm_addr_list, &rm_addr_num);
2013
2014         /* Remove mc mac addresses */
2015         for (i = 0; i < rm_addr_num; i++) {
2016                 num = rm_addr_num - i - 1;
2017                 addr = &rm_addr_list[num];
2018                 ret = hns3_remove_mc_addr(hw, addr);
2019                 if (ret) {
2020                         rte_spinlock_unlock(&hw->lock);
2021                         return ret;
2022                 }
2023                 hw->mc_addrs_num--;
2024         }
2025
2026         /* Add mc mac addresses */
2027         for (i = 0; i < add_addr_num; i++) {
2028                 addr = &add_addr_list[i];
2029                 ret = hns3_add_mc_addr(hw, addr);
2030                 if (ret) {
2031                         rte_spinlock_unlock(&hw->lock);
2032                         return ret;
2033                 }
2034
2035                 num = reserved_addr_num + i;
2036                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2037                 hw->mc_addrs_num++;
2038         }
2039         rte_spinlock_unlock(&hw->lock);
2040
2041         return 0;
2042 }
2043
2044 static int
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2046 {
2047         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048         struct hns3_hw *hw = &hns->hw;
2049         struct rte_ether_addr *addr;
2050         int err = 0;
2051         int ret;
2052         int i;
2053
2054         for (i = 0; i < hw->mc_addrs_num; i++) {
2055                 addr = &hw->mc_addrs[i];
2056                 if (!rte_is_multicast_ether_addr(addr))
2057                         continue;
2058                 if (del)
2059                         ret = hns3_remove_mc_addr(hw, addr);
2060                 else
2061                         ret = hns3_add_mc_addr(hw, addr);
2062                 if (ret) {
2063                         err = ret;
2064                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2065                                               addr);
2066                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067                                  del ? "Remove" : "Restore", mac_str, ret);
2068                 }
2069         }
2070         return err;
2071 }
2072
2073 static int
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2075 {
2076         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2082         uint8_t num_tc;
2083         int max_tc = 0;
2084         int i;
2085
2086         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2088
2089         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091                          "rx_mq_mode = %d", rx_mq_mode);
2092                 return -EINVAL;
2093         }
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099                          rx_mq_mode, tx_mq_mode);
2100                 return -EINVAL;
2101         }
2102
2103         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2107                         return -EINVAL;
2108                 }
2109
2110                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113                                  "nb_tcs(%d) != %d or %d in rx direction.",
2114                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2115                         return -EINVAL;
2116                 }
2117
2118                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2121                         return -EINVAL;
2122                 }
2123
2124                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127                                          "is not equal to one in tx direction.",
2128                                          i, dcb_rx_conf->dcb_tc[i]);
2129                                 return -EINVAL;
2130                         }
2131                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132                                 max_tc = dcb_rx_conf->dcb_tc[i];
2133                 }
2134
2135                 num_tc = max_tc + 1;
2136                 if (num_tc > dcb_rx_conf->nb_tcs) {
2137                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138                                  num_tc, dcb_rx_conf->nb_tcs);
2139                         return -EINVAL;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2148 {
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         if (!hns3_dev_dcb_supported(hw)) {
2152                 hns3_err(hw, "this port does not support dcb configurations.");
2153                 return -EOPNOTSUPP;
2154         }
2155
2156         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2158                 return -EOPNOTSUPP;
2159         }
2160
2161         /* Check multiple queue mode */
2162         return hns3_check_mq_mode(dev);
2163 }
2164
2165 static int
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167                            enum hns3_ring_type queue_type, uint16_t queue_id)
2168 {
2169         struct hns3_cmd_desc desc;
2170         struct hns3_ctrl_vector_chain_cmd *req =
2171                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172         enum hns3_cmd_status status;
2173         enum hns3_opcode_type op;
2174         uint16_t tqp_type_and_id = 0;
2175         const char *op_str;
2176         uint16_t type;
2177         uint16_t gl;
2178
2179         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180         hns3_cmd_setup_basic_desc(&desc, op, false);
2181         req->int_vector_id = vector_id;
2182
2183         if (queue_type == HNS3_RING_TYPE_RX)
2184                 gl = HNS3_RING_GL_RX;
2185         else
2186                 gl = HNS3_RING_GL_TX;
2187
2188         type = queue_type;
2189
2190         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2191                        type);
2192         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2194                        gl);
2195         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196         req->int_cause_num = 1;
2197         op_str = mmap ? "Map" : "Unmap";
2198         status = hns3_cmd_send(hw, &desc, 1);
2199         if (status) {
2200                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201                          op_str, queue_id, req->int_vector_id, status);
2202                 return status;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2210 {
2211         uint8_t vec;
2212         int ret;
2213         int i;
2214
2215         /*
2216          * In hns3 network engine, vector 0 is always the misc interrupt of this
2217          * function, vector 1~N can be used respectively for the queues of the
2218          * function. Tx and Rx queues with the same number share the interrupt
2219          * vector. In the initialization clearing the all hardware mapping
2220          * relationship configurations between queues and interrupt vectors is
2221          * needed, so some error caused by the residual configurations, such as
2222          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2223          * constraints in hns3 hardware engine, we have to implement clearing
2224          * the mapping relationship configurations by binding all queues to the
2225          * last interrupt vector and reserving the last interrupt vector. This
2226          * method results in a decrease of the maximum queues when upper
2227          * applications call the rte_eth_dev_configure API function to enable
2228          * Rx interrupt.
2229          */
2230         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2231         /* vec - 1: the last interrupt is reserved */
2232         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2233         for (i = 0; i < hw->intr_tqps_num; i++) {
2234                 /*
2235                  * Set gap limiter and rate limiter configuration of queue's
2236                  * interrupt.
2237                  */
2238                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239                                        HNS3_TQP_INTR_GL_DEFAULT);
2240                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241                                        HNS3_TQP_INTR_GL_DEFAULT);
2242                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2243
2244                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245                                                  HNS3_RING_TYPE_TX, i);
2246                 if (ret) {
2247                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248                                           "vector: %d, ret=%d", i, vec, ret);
2249                         return ret;
2250                 }
2251
2252                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253                                                  HNS3_RING_TYPE_RX, i);
2254                 if (ret) {
2255                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256                                           "vector: %d, ret=%d", i, vec, ret);
2257                         return ret;
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2266 {
2267         struct hns3_adapter *hns = dev->data->dev_private;
2268         struct rte_eth_conf *conf = &dev->data->dev_conf;
2269         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270         struct hns3_hw *hw = &hns->hw;
2271         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274         struct rte_eth_rss_conf rss_conf;
2275         uint16_t mtu;
2276         bool gro_en;
2277         int ret;
2278
2279         /*
2280          * Hardware does not support individually enable/disable/reset the Tx or
2281          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2282          * and Rx queues at the same time. When the numbers of Tx queues
2283          * allocated by upper applications are not equal to the numbers of Rx
2284          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2285          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2286          * these fake queues are imperceptible, and can not be used by upper
2287          * applications.
2288          */
2289         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2290         if (ret) {
2291                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2292                 return ret;
2293         }
2294
2295         hw->adapter_state = HNS3_NIC_CONFIGURING;
2296         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2297                 hns3_err(hw, "setting link speed/duplex not supported");
2298                 ret = -EINVAL;
2299                 goto cfg_err;
2300         }
2301
2302         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2303                 ret = hns3_check_dcb_cfg(dev);
2304                 if (ret)
2305                         goto cfg_err;
2306         }
2307
2308         /* When RSS is not configured, redirect the packet queue 0 */
2309         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2310                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2311                 rss_conf = conf->rx_adv_conf.rss_conf;
2312                 if (rss_conf.rss_key == NULL) {
2313                         rss_conf.rss_key = rss_cfg->key;
2314                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2315                 }
2316
2317                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2318                 if (ret)
2319                         goto cfg_err;
2320         }
2321
2322         /*
2323          * If jumbo frames are enabled, MTU needs to be refreshed
2324          * according to the maximum RX packet length.
2325          */
2326         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2327                 /*
2328                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2329                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2330                  * can safely assign to "uint16_t" type variable.
2331                  */
2332                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2333                 ret = hns3_dev_mtu_set(dev, mtu);
2334                 if (ret)
2335                         goto cfg_err;
2336                 dev->data->mtu = mtu;
2337         }
2338
2339         ret = hns3_dev_configure_vlan(dev);
2340         if (ret)
2341                 goto cfg_err;
2342
2343         /* config hardware GRO */
2344         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2345         ret = hns3_config_gro(hw, gro_en);
2346         if (ret)
2347                 goto cfg_err;
2348
2349         hw->adapter_state = HNS3_NIC_CONFIGURED;
2350
2351         return 0;
2352
2353 cfg_err:
2354         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2355         hw->adapter_state = HNS3_NIC_INITIALIZED;
2356
2357         return ret;
2358 }
2359
2360 static int
2361 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2362 {
2363         struct hns3_config_max_frm_size_cmd *req;
2364         struct hns3_cmd_desc desc;
2365
2366         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2367
2368         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2369         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2370         req->min_frm_size = RTE_ETHER_MIN_LEN;
2371
2372         return hns3_cmd_send(hw, &desc, 1);
2373 }
2374
2375 static int
2376 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2377 {
2378         int ret;
2379
2380         ret = hns3_set_mac_mtu(hw, mps);
2381         if (ret) {
2382                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2383                 return ret;
2384         }
2385
2386         ret = hns3_buffer_alloc(hw);
2387         if (ret)
2388                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2389
2390         return ret;
2391 }
2392
2393 static int
2394 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2395 {
2396         struct hns3_adapter *hns = dev->data->dev_private;
2397         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2398         struct hns3_hw *hw = &hns->hw;
2399         bool is_jumbo_frame;
2400         int ret;
2401
2402         if (dev->data->dev_started) {
2403                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2404                          "before configuration", dev->data->port_id);
2405                 return -EBUSY;
2406         }
2407
2408         rte_spinlock_lock(&hw->lock);
2409         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2410         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2411
2412         /*
2413          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2414          * assign to "uint16_t" type variable.
2415          */
2416         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2417         if (ret) {
2418                 rte_spinlock_unlock(&hw->lock);
2419                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2420                          dev->data->port_id, mtu, ret);
2421                 return ret;
2422         }
2423         hns->pf.mps = (uint16_t)frame_size;
2424         if (is_jumbo_frame)
2425                 dev->data->dev_conf.rxmode.offloads |=
2426                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2427         else
2428                 dev->data->dev_conf.rxmode.offloads &=
2429                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2430         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2431         rte_spinlock_unlock(&hw->lock);
2432
2433         return 0;
2434 }
2435
2436 static int
2437 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2438 {
2439         struct hns3_adapter *hns = eth_dev->data->dev_private;
2440         struct hns3_hw *hw = &hns->hw;
2441         uint16_t queue_num = hw->tqps_num;
2442
2443         /*
2444          * In interrupt mode, 'max_rx_queues' is set based on the number of
2445          * MSI-X interrupt resources of the hardware.
2446          */
2447         if (hw->data->dev_conf.intr_conf.rxq == 1)
2448                 queue_num = hw->intr_tqps_num;
2449
2450         info->max_rx_queues = queue_num;
2451         info->max_tx_queues = hw->tqps_num;
2452         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2453         info->min_rx_bufsize = hw->rx_buf_len;
2454         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2455         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2456         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2457         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2458                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2459                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2460                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2461                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2462                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2463                                  DEV_RX_OFFLOAD_KEEP_CRC |
2464                                  DEV_RX_OFFLOAD_SCATTER |
2465                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2466                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2467                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2468                                  DEV_RX_OFFLOAD_RSS_HASH |
2469                                  DEV_RX_OFFLOAD_TCP_LRO);
2470         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2471         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2472                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2473                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2474                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2475                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2476                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2477                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2478                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2479                                  DEV_TX_OFFLOAD_TCP_TSO |
2480                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2481                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2482                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2483                                  info->tx_queue_offload_capa);
2484
2485         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2486                 .nb_max = HNS3_MAX_RING_DESC,
2487                 .nb_min = HNS3_MIN_RING_DESC,
2488                 .nb_align = HNS3_ALIGN_RING_DESC,
2489         };
2490
2491         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2492                 .nb_max = HNS3_MAX_RING_DESC,
2493                 .nb_min = HNS3_MIN_RING_DESC,
2494                 .nb_align = HNS3_ALIGN_RING_DESC,
2495         };
2496
2497         info->vmdq_queue_num = 0;
2498
2499         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2500         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2501         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2502
2503         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2504         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2505         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2506         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2507         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2508         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2509
2510         return 0;
2511 }
2512
2513 static int
2514 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2515                     size_t fw_size)
2516 {
2517         struct hns3_adapter *hns = eth_dev->data->dev_private;
2518         struct hns3_hw *hw = &hns->hw;
2519         uint32_t version = hw->fw_version;
2520         int ret;
2521
2522         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2523                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2524                                       HNS3_FW_VERSION_BYTE3_S),
2525                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2526                                       HNS3_FW_VERSION_BYTE2_S),
2527                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2528                                       HNS3_FW_VERSION_BYTE1_S),
2529                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2530                                       HNS3_FW_VERSION_BYTE0_S));
2531         ret += 1; /* add the size of '\0' */
2532         if (fw_size < (uint32_t)ret)
2533                 return ret;
2534         else
2535                 return 0;
2536 }
2537
2538 static int
2539 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2540                      __rte_unused int wait_to_complete)
2541 {
2542         struct hns3_adapter *hns = eth_dev->data->dev_private;
2543         struct hns3_hw *hw = &hns->hw;
2544         struct hns3_mac *mac = &hw->mac;
2545         struct rte_eth_link new_link;
2546
2547         if (!hns3_is_reset_pending(hns)) {
2548                 hns3_update_speed_duplex(eth_dev);
2549                 hns3_update_link_status(hw);
2550         }
2551
2552         memset(&new_link, 0, sizeof(new_link));
2553         switch (mac->link_speed) {
2554         case ETH_SPEED_NUM_10M:
2555         case ETH_SPEED_NUM_100M:
2556         case ETH_SPEED_NUM_1G:
2557         case ETH_SPEED_NUM_10G:
2558         case ETH_SPEED_NUM_25G:
2559         case ETH_SPEED_NUM_40G:
2560         case ETH_SPEED_NUM_50G:
2561         case ETH_SPEED_NUM_100G:
2562                 new_link.link_speed = mac->link_speed;
2563                 break;
2564         default:
2565                 new_link.link_speed = ETH_SPEED_NUM_100M;
2566                 break;
2567         }
2568
2569         new_link.link_duplex = mac->link_duplex;
2570         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2571         new_link.link_autoneg =
2572             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2573
2574         return rte_eth_linkstatus_set(eth_dev, &new_link);
2575 }
2576
2577 static int
2578 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2579 {
2580         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2581         struct hns3_pf *pf = &hns->pf;
2582
2583         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2584                 return -EINVAL;
2585
2586         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2587
2588         return 0;
2589 }
2590
2591 static int
2592 hns3_query_function_status(struct hns3_hw *hw)
2593 {
2594 #define HNS3_QUERY_MAX_CNT              10
2595 #define HNS3_QUERY_SLEEP_MSCOEND        1
2596         struct hns3_func_status_cmd *req;
2597         struct hns3_cmd_desc desc;
2598         int timeout = 0;
2599         int ret;
2600
2601         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2602         req = (struct hns3_func_status_cmd *)desc.data;
2603
2604         do {
2605                 ret = hns3_cmd_send(hw, &desc, 1);
2606                 if (ret) {
2607                         PMD_INIT_LOG(ERR, "query function status failed %d",
2608                                      ret);
2609                         return ret;
2610                 }
2611
2612                 /* Check pf reset is done */
2613                 if (req->pf_state)
2614                         break;
2615
2616                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2617         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2618
2619         return hns3_parse_func_status(hw, req);
2620 }
2621
2622 static int
2623 hns3_query_pf_resource(struct hns3_hw *hw)
2624 {
2625         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2626         struct hns3_pf *pf = &hns->pf;
2627         struct hns3_pf_res_cmd *req;
2628         struct hns3_cmd_desc desc;
2629         int ret;
2630
2631         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2632         ret = hns3_cmd_send(hw, &desc, 1);
2633         if (ret) {
2634                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2635                 return ret;
2636         }
2637
2638         req = (struct hns3_pf_res_cmd *)desc.data;
2639         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2640         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2641         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2642         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2643
2644         if (req->tx_buf_size)
2645                 pf->tx_buf_size =
2646                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2647         else
2648                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2649
2650         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2651
2652         if (req->dv_buf_size)
2653                 pf->dv_buf_size =
2654                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2655         else
2656                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2657
2658         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2659
2660         hw->num_msi =
2661             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2662                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2663
2664         return 0;
2665 }
2666
2667 static void
2668 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2669 {
2670         struct hns3_cfg_param_cmd *req;
2671         uint64_t mac_addr_tmp_high;
2672         uint64_t mac_addr_tmp;
2673         uint32_t i;
2674
2675         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2676
2677         /* get the configuration */
2678         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2679                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2680         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2681                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2682         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2683                                            HNS3_CFG_TQP_DESC_N_M,
2684                                            HNS3_CFG_TQP_DESC_N_S);
2685
2686         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2687                                        HNS3_CFG_PHY_ADDR_M,
2688                                        HNS3_CFG_PHY_ADDR_S);
2689         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2690                                          HNS3_CFG_MEDIA_TP_M,
2691                                          HNS3_CFG_MEDIA_TP_S);
2692         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2693                                          HNS3_CFG_RX_BUF_LEN_M,
2694                                          HNS3_CFG_RX_BUF_LEN_S);
2695         /* get mac address */
2696         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2697         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2698                                            HNS3_CFG_MAC_ADDR_H_M,
2699                                            HNS3_CFG_MAC_ADDR_H_S);
2700
2701         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2702
2703         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2704                                             HNS3_CFG_DEFAULT_SPEED_M,
2705                                             HNS3_CFG_DEFAULT_SPEED_S);
2706         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2707                                            HNS3_CFG_RSS_SIZE_M,
2708                                            HNS3_CFG_RSS_SIZE_S);
2709
2710         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2711                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2712
2713         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2714         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2715
2716         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2717                                             HNS3_CFG_SPEED_ABILITY_M,
2718                                             HNS3_CFG_SPEED_ABILITY_S);
2719         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2720                                         HNS3_CFG_UMV_TBL_SPACE_M,
2721                                         HNS3_CFG_UMV_TBL_SPACE_S);
2722         if (!cfg->umv_space)
2723                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2724 }
2725
2726 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2727  * @hw: pointer to struct hns3_hw
2728  * @hcfg: the config structure to be getted
2729  */
2730 static int
2731 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2732 {
2733         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2734         struct hns3_cfg_param_cmd *req;
2735         uint32_t offset;
2736         uint32_t i;
2737         int ret;
2738
2739         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2740                 offset = 0;
2741                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2742                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2743                                           true);
2744                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2745                                i * HNS3_CFG_RD_LEN_BYTES);
2746                 /* Len should be divided by 4 when send to hardware */
2747                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2748                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2749                 req->offset = rte_cpu_to_le_32(offset);
2750         }
2751
2752         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2753         if (ret) {
2754                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2755                 return ret;
2756         }
2757
2758         hns3_parse_cfg(hcfg, desc);
2759
2760         return 0;
2761 }
2762
2763 static int
2764 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2765 {
2766         switch (speed_cmd) {
2767         case HNS3_CFG_SPEED_10M:
2768                 *speed = ETH_SPEED_NUM_10M;
2769                 break;
2770         case HNS3_CFG_SPEED_100M:
2771                 *speed = ETH_SPEED_NUM_100M;
2772                 break;
2773         case HNS3_CFG_SPEED_1G:
2774                 *speed = ETH_SPEED_NUM_1G;
2775                 break;
2776         case HNS3_CFG_SPEED_10G:
2777                 *speed = ETH_SPEED_NUM_10G;
2778                 break;
2779         case HNS3_CFG_SPEED_25G:
2780                 *speed = ETH_SPEED_NUM_25G;
2781                 break;
2782         case HNS3_CFG_SPEED_40G:
2783                 *speed = ETH_SPEED_NUM_40G;
2784                 break;
2785         case HNS3_CFG_SPEED_50G:
2786                 *speed = ETH_SPEED_NUM_50G;
2787                 break;
2788         case HNS3_CFG_SPEED_100G:
2789                 *speed = ETH_SPEED_NUM_100G;
2790                 break;
2791         default:
2792                 return -EINVAL;
2793         }
2794
2795         return 0;
2796 }
2797
2798 static int
2799 hns3_get_board_configuration(struct hns3_hw *hw)
2800 {
2801         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2802         struct hns3_pf *pf = &hns->pf;
2803         struct hns3_cfg cfg;
2804         int ret;
2805
2806         ret = hns3_get_board_cfg(hw, &cfg);
2807         if (ret) {
2808                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2809                 return ret;
2810         }
2811
2812         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2813                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2814                 return -EOPNOTSUPP;
2815         }
2816
2817         hw->mac.media_type = cfg.media_type;
2818         hw->rss_size_max = cfg.rss_size_max;
2819         hw->rss_dis_flag = false;
2820         hw->rx_buf_len = cfg.rx_buf_len;
2821         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2822         hw->mac.phy_addr = cfg.phy_addr;
2823         hw->mac.default_addr_setted = false;
2824         hw->num_tx_desc = cfg.tqp_desc_num;
2825         hw->num_rx_desc = cfg.tqp_desc_num;
2826         hw->dcb_info.num_pg = 1;
2827         hw->dcb_info.hw_pfc_map = 0;
2828
2829         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2830         if (ret) {
2831                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2832                              cfg.default_speed, ret);
2833                 return ret;
2834         }
2835
2836         pf->tc_max = cfg.tc_num;
2837         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2838                 PMD_INIT_LOG(WARNING,
2839                              "Get TC num(%u) from flash, set TC num to 1",
2840                              pf->tc_max);
2841                 pf->tc_max = 1;
2842         }
2843
2844         /* Dev does not support DCB */
2845         if (!hns3_dev_dcb_supported(hw)) {
2846                 pf->tc_max = 1;
2847                 pf->pfc_max = 0;
2848         } else
2849                 pf->pfc_max = pf->tc_max;
2850
2851         hw->dcb_info.num_tc = 1;
2852         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2853                                      hw->tqps_num / hw->dcb_info.num_tc);
2854         hns3_set_bit(hw->hw_tc_map, 0, 1);
2855         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2856
2857         pf->wanted_umv_size = cfg.umv_space;
2858
2859         return ret;
2860 }
2861
2862 static int
2863 hns3_get_configuration(struct hns3_hw *hw)
2864 {
2865         int ret;
2866
2867         ret = hns3_query_function_status(hw);
2868         if (ret) {
2869                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2870                 return ret;
2871         }
2872
2873         /* Get pf resource */
2874         ret = hns3_query_pf_resource(hw);
2875         if (ret) {
2876                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2877                 return ret;
2878         }
2879
2880         ret = hns3_get_board_configuration(hw);
2881         if (ret)
2882                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2883
2884         return ret;
2885 }
2886
2887 static int
2888 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2889                       uint16_t tqp_vid, bool is_pf)
2890 {
2891         struct hns3_tqp_map_cmd *req;
2892         struct hns3_cmd_desc desc;
2893         int ret;
2894
2895         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2896
2897         req = (struct hns3_tqp_map_cmd *)desc.data;
2898         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2899         req->tqp_vf = func_id;
2900         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2901         if (!is_pf)
2902                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2903         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2904
2905         ret = hns3_cmd_send(hw, &desc, 1);
2906         if (ret)
2907                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2908
2909         return ret;
2910 }
2911
2912 static int
2913 hns3_map_tqp(struct hns3_hw *hw)
2914 {
2915         uint16_t tqps_num = hw->total_tqps_num;
2916         uint16_t func_id;
2917         uint16_t tqp_id;
2918         bool is_pf;
2919         int num;
2920         int ret;
2921         int i;
2922
2923         /*
2924          * In current version VF is not supported when PF is driven by DPDK
2925          * driver, so we allocate tqps to PF as much as possible.
2926          */
2927         tqp_id = 0;
2928         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2929         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2930                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2931                 for (i = 0;
2932                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2933                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2934                                                     is_pf);
2935                         if (ret)
2936                                 return ret;
2937                 }
2938         }
2939
2940         return 0;
2941 }
2942
2943 static int
2944 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2945 {
2946         struct hns3_config_mac_speed_dup_cmd *req;
2947         struct hns3_cmd_desc desc;
2948         int ret;
2949
2950         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2951
2952         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2953
2954         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2955
2956         switch (speed) {
2957         case ETH_SPEED_NUM_10M:
2958                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2959                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2960                 break;
2961         case ETH_SPEED_NUM_100M:
2962                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2963                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2964                 break;
2965         case ETH_SPEED_NUM_1G:
2966                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2967                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2968                 break;
2969         case ETH_SPEED_NUM_10G:
2970                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2971                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2972                 break;
2973         case ETH_SPEED_NUM_25G:
2974                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2975                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2976                 break;
2977         case ETH_SPEED_NUM_40G:
2978                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2979                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2980                 break;
2981         case ETH_SPEED_NUM_50G:
2982                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2983                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2984                 break;
2985         case ETH_SPEED_NUM_100G:
2986                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2987                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2988                 break;
2989         default:
2990                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2991                 return -EINVAL;
2992         }
2993
2994         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2995
2996         ret = hns3_cmd_send(hw, &desc, 1);
2997         if (ret)
2998                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2999
3000         return ret;
3001 }
3002
3003 static int
3004 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3005 {
3006         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3007         struct hns3_pf *pf = &hns->pf;
3008         struct hns3_priv_buf *priv;
3009         uint32_t i, total_size;
3010
3011         total_size = pf->pkt_buf_size;
3012
3013         /* alloc tx buffer for all enabled tc */
3014         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3015                 priv = &buf_alloc->priv_buf[i];
3016
3017                 if (hw->hw_tc_map & BIT(i)) {
3018                         if (total_size < pf->tx_buf_size)
3019                                 return -ENOMEM;
3020
3021                         priv->tx_buf_size = pf->tx_buf_size;
3022                 } else
3023                         priv->tx_buf_size = 0;
3024
3025                 total_size -= priv->tx_buf_size;
3026         }
3027
3028         return 0;
3029 }
3030
3031 static int
3032 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3033 {
3034 /* TX buffer size is unit by 128 byte */
3035 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3036 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3037         struct hns3_tx_buff_alloc_cmd *req;
3038         struct hns3_cmd_desc desc;
3039         uint32_t buf_size;
3040         uint32_t i;
3041         int ret;
3042
3043         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3044
3045         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3046         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3047                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3048
3049                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3050                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3051                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3052         }
3053
3054         ret = hns3_cmd_send(hw, &desc, 1);
3055         if (ret)
3056                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3057
3058         return ret;
3059 }
3060
3061 static int
3062 hns3_get_tc_num(struct hns3_hw *hw)
3063 {
3064         int cnt = 0;
3065         uint8_t i;
3066
3067         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3068                 if (hw->hw_tc_map & BIT(i))
3069                         cnt++;
3070         return cnt;
3071 }
3072
3073 static uint32_t
3074 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3075 {
3076         struct hns3_priv_buf *priv;
3077         uint32_t rx_priv = 0;
3078         int i;
3079
3080         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3081                 priv = &buf_alloc->priv_buf[i];
3082                 if (priv->enable)
3083                         rx_priv += priv->buf_size;
3084         }
3085         return rx_priv;
3086 }
3087
3088 static uint32_t
3089 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3090 {
3091         uint32_t total_tx_size = 0;
3092         uint32_t i;
3093
3094         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3095                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3096
3097         return total_tx_size;
3098 }
3099
3100 /* Get the number of pfc enabled TCs, which have private buffer */
3101 static int
3102 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3103 {
3104         struct hns3_priv_buf *priv;
3105         int cnt = 0;
3106         uint8_t i;
3107
3108         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3109                 priv = &buf_alloc->priv_buf[i];
3110                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3111                         cnt++;
3112         }
3113
3114         return cnt;
3115 }
3116
3117 /* Get the number of pfc disabled TCs, which have private buffer */
3118 static int
3119 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3120                          struct hns3_pkt_buf_alloc *buf_alloc)
3121 {
3122         struct hns3_priv_buf *priv;
3123         int cnt = 0;
3124         uint8_t i;
3125
3126         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3127                 priv = &buf_alloc->priv_buf[i];
3128                 if (hw->hw_tc_map & BIT(i) &&
3129                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3130                         cnt++;
3131         }
3132
3133         return cnt;
3134 }
3135
3136 static bool
3137 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3138                   uint32_t rx_all)
3139 {
3140         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3141         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3142         struct hns3_pf *pf = &hns->pf;
3143         uint32_t shared_buf, aligned_mps;
3144         uint32_t rx_priv;
3145         uint8_t tc_num;
3146         uint8_t i;
3147
3148         tc_num = hns3_get_tc_num(hw);
3149         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3150
3151         if (hns3_dev_dcb_supported(hw))
3152                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3153                                         pf->dv_buf_size;
3154         else
3155                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3156                                         + pf->dv_buf_size;
3157
3158         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3159         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3160                              HNS3_BUF_SIZE_UNIT);
3161
3162         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3163         if (rx_all < rx_priv + shared_std)
3164                 return false;
3165
3166         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3167         buf_alloc->s_buf.buf_size = shared_buf;
3168         if (hns3_dev_dcb_supported(hw)) {
3169                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3170                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3171                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3172                                   HNS3_BUF_SIZE_UNIT);
3173         } else {
3174                 buf_alloc->s_buf.self.high =
3175                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3176                 buf_alloc->s_buf.self.low = aligned_mps;
3177         }
3178
3179         if (hns3_dev_dcb_supported(hw)) {
3180                 hi_thrd = shared_buf - pf->dv_buf_size;
3181
3182                 if (tc_num <= NEED_RESERVE_TC_NUM)
3183                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3184                                         / BUF_MAX_PERCENT;
3185
3186                 if (tc_num)
3187                         hi_thrd = hi_thrd / tc_num;
3188
3189                 hi_thrd = max_t(uint32_t, hi_thrd,
3190                                 HNS3_BUF_MUL_BY * aligned_mps);
3191                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3192                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3193         } else {
3194                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3195                 lo_thrd = aligned_mps;
3196         }
3197
3198         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3199                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3200                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3201         }
3202
3203         return true;
3204 }
3205
3206 static bool
3207 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3208                      struct hns3_pkt_buf_alloc *buf_alloc)
3209 {
3210         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3211         struct hns3_pf *pf = &hns->pf;
3212         struct hns3_priv_buf *priv;
3213         uint32_t aligned_mps;
3214         uint32_t rx_all;
3215         uint8_t i;
3216
3217         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3218         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3219
3220         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3221                 priv = &buf_alloc->priv_buf[i];
3222
3223                 priv->enable = 0;
3224                 priv->wl.low = 0;
3225                 priv->wl.high = 0;
3226                 priv->buf_size = 0;
3227
3228                 if (!(hw->hw_tc_map & BIT(i)))
3229                         continue;
3230
3231                 priv->enable = 1;
3232                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3233                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3234                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3235                                                 HNS3_BUF_SIZE_UNIT);
3236                 } else {
3237                         priv->wl.low = 0;
3238                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3239                                         aligned_mps;
3240                 }
3241
3242                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3243         }
3244
3245         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3246 }
3247
3248 static bool
3249 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3250                              struct hns3_pkt_buf_alloc *buf_alloc)
3251 {
3252         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3253         struct hns3_pf *pf = &hns->pf;
3254         struct hns3_priv_buf *priv;
3255         int no_pfc_priv_num;
3256         uint32_t rx_all;
3257         uint8_t mask;
3258         int i;
3259
3260         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3261         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3262
3263         /* let the last to be cleared first */
3264         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3265                 priv = &buf_alloc->priv_buf[i];
3266                 mask = BIT((uint8_t)i);
3267
3268                 if (hw->hw_tc_map & mask &&
3269                     !(hw->dcb_info.hw_pfc_map & mask)) {
3270                         /* Clear the no pfc TC private buffer */
3271                         priv->wl.low = 0;
3272                         priv->wl.high = 0;
3273                         priv->buf_size = 0;
3274                         priv->enable = 0;
3275                         no_pfc_priv_num--;
3276                 }
3277
3278                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3279                     no_pfc_priv_num == 0)
3280                         break;
3281         }
3282
3283         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3284 }
3285
3286 static bool
3287 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3288                            struct hns3_pkt_buf_alloc *buf_alloc)
3289 {
3290         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3291         struct hns3_pf *pf = &hns->pf;
3292         struct hns3_priv_buf *priv;
3293         uint32_t rx_all;
3294         int pfc_priv_num;
3295         uint8_t mask;
3296         int i;
3297
3298         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3299         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3300
3301         /* let the last to be cleared first */
3302         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3303                 priv = &buf_alloc->priv_buf[i];
3304                 mask = BIT((uint8_t)i);
3305
3306                 if (hw->hw_tc_map & mask &&
3307                     hw->dcb_info.hw_pfc_map & mask) {
3308                         /* Reduce the number of pfc TC with private buffer */
3309                         priv->wl.low = 0;
3310                         priv->enable = 0;
3311                         priv->wl.high = 0;
3312                         priv->buf_size = 0;
3313                         pfc_priv_num--;
3314                 }
3315                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3316                     pfc_priv_num == 0)
3317                         break;
3318         }
3319
3320         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3321 }
3322
3323 static bool
3324 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3325                           struct hns3_pkt_buf_alloc *buf_alloc)
3326 {
3327 #define COMPENSATE_BUFFER       0x3C00
3328 #define COMPENSATE_HALF_MPS_NUM 5
3329 #define PRIV_WL_GAP             0x1800
3330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3331         struct hns3_pf *pf = &hns->pf;
3332         uint32_t tc_num = hns3_get_tc_num(hw);
3333         uint32_t half_mps = pf->mps >> 1;
3334         struct hns3_priv_buf *priv;
3335         uint32_t min_rx_priv;
3336         uint32_t rx_priv;
3337         uint8_t i;
3338
3339         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3340         if (tc_num)
3341                 rx_priv = rx_priv / tc_num;
3342
3343         if (tc_num <= NEED_RESERVE_TC_NUM)
3344                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3345
3346         /*
3347          * Minimum value of private buffer in rx direction (min_rx_priv) is
3348          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3349          * buffer if rx_priv is greater than min_rx_priv.
3350          */
3351         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3352                         COMPENSATE_HALF_MPS_NUM * half_mps;
3353         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3354         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3355
3356         if (rx_priv < min_rx_priv)
3357                 return false;
3358
3359         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3360                 priv = &buf_alloc->priv_buf[i];
3361
3362                 priv->enable = 0;
3363                 priv->wl.low = 0;
3364                 priv->wl.high = 0;
3365                 priv->buf_size = 0;
3366
3367                 if (!(hw->hw_tc_map & BIT(i)))
3368                         continue;
3369
3370                 priv->enable = 1;
3371                 priv->buf_size = rx_priv;
3372                 priv->wl.high = rx_priv - pf->dv_buf_size;
3373                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3374         }
3375
3376         buf_alloc->s_buf.buf_size = 0;
3377
3378         return true;
3379 }
3380
3381 /*
3382  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3383  * @hw: pointer to struct hns3_hw
3384  * @buf_alloc: pointer to buffer calculation data
3385  * @return: 0: calculate sucessful, negative: fail
3386  */
3387 static int
3388 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3389 {
3390         /* When DCB is not supported, rx private buffer is not allocated. */
3391         if (!hns3_dev_dcb_supported(hw)) {
3392                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3393                 struct hns3_pf *pf = &hns->pf;
3394                 uint32_t rx_all = pf->pkt_buf_size;
3395
3396                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3397                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3398                         return -ENOMEM;
3399
3400                 return 0;
3401         }
3402
3403         /*
3404          * Try to allocate privated packet buffer for all TCs without share
3405          * buffer.
3406          */
3407         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3408                 return 0;
3409
3410         /*
3411          * Try to allocate privated packet buffer for all TCs with share
3412          * buffer.
3413          */
3414         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3415                 return 0;
3416
3417         /*
3418          * For different application scenes, the enabled port number, TC number
3419          * and no_drop TC number are different. In order to obtain the better
3420          * performance, software could allocate the buffer size and configure
3421          * the waterline by tring to decrease the private buffer size according
3422          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3423          * enabled tc.
3424          */
3425         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3426                 return 0;
3427
3428         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3429                 return 0;
3430
3431         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3432                 return 0;
3433
3434         return -ENOMEM;
3435 }
3436
3437 static int
3438 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3439 {
3440         struct hns3_rx_priv_buff_cmd *req;
3441         struct hns3_cmd_desc desc;
3442         uint32_t buf_size;
3443         int ret;
3444         int i;
3445
3446         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3447         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3448
3449         /* Alloc private buffer TCs */
3450         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3451                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3452
3453                 req->buf_num[i] =
3454                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3455                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3456         }
3457
3458         buf_size = buf_alloc->s_buf.buf_size;
3459         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3460                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3461
3462         ret = hns3_cmd_send(hw, &desc, 1);
3463         if (ret)
3464                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3465
3466         return ret;
3467 }
3468
3469 static int
3470 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3471 {
3472 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3473         struct hns3_rx_priv_wl_buf *req;
3474         struct hns3_priv_buf *priv;
3475         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3476         int i, j;
3477         int ret;
3478
3479         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3480                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3481                                           false);
3482                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3483
3484                 /* The first descriptor set the NEXT bit to 1 */
3485                 if (i == 0)
3486                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3487                 else
3488                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3489
3490                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3491                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3492
3493                         priv = &buf_alloc->priv_buf[idx];
3494                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3495                                                         HNS3_BUF_UNIT_S);
3496                         req->tc_wl[j].high |=
3497                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3498                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3499                                                         HNS3_BUF_UNIT_S);
3500                         req->tc_wl[j].low |=
3501                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3502                 }
3503         }
3504
3505         /* Send 2 descriptor at one time */
3506         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3507         if (ret)
3508                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3509                              ret);
3510         return ret;
3511 }
3512
3513 static int
3514 hns3_common_thrd_config(struct hns3_hw *hw,
3515                         struct hns3_pkt_buf_alloc *buf_alloc)
3516 {
3517 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3518         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3519         struct hns3_rx_com_thrd *req;
3520         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3521         struct hns3_tc_thrd *tc;
3522         int tc_idx;
3523         int i, j;
3524         int ret;
3525
3526         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3527                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3528                                           false);
3529                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3530
3531                 /* The first descriptor set the NEXT bit to 1 */
3532                 if (i == 0)
3533                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3534                 else
3535                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3536
3537                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3538                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3539                         tc = &s_buf->tc_thrd[tc_idx];
3540
3541                         req->com_thrd[j].high =
3542                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3543                         req->com_thrd[j].high |=
3544                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3545                         req->com_thrd[j].low =
3546                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3547                         req->com_thrd[j].low |=
3548                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3549                 }
3550         }
3551
3552         /* Send 2 descriptors at one time */
3553         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3554         if (ret)
3555                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3556
3557         return ret;
3558 }
3559
3560 static int
3561 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3562 {
3563         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3564         struct hns3_rx_com_wl *req;
3565         struct hns3_cmd_desc desc;
3566         int ret;
3567
3568         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3569
3570         req = (struct hns3_rx_com_wl *)desc.data;
3571         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3572         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3573
3574         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3575         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3576
3577         ret = hns3_cmd_send(hw, &desc, 1);
3578         if (ret)
3579                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3580
3581         return ret;
3582 }
3583
3584 int
3585 hns3_buffer_alloc(struct hns3_hw *hw)
3586 {
3587         struct hns3_pkt_buf_alloc pkt_buf;
3588         int ret;
3589
3590         memset(&pkt_buf, 0, sizeof(pkt_buf));
3591         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3592         if (ret) {
3593                 PMD_INIT_LOG(ERR,
3594                              "could not calc tx buffer size for all TCs %d",
3595                              ret);
3596                 return ret;
3597         }
3598
3599         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3600         if (ret) {
3601                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3602                 return ret;
3603         }
3604
3605         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3606         if (ret) {
3607                 PMD_INIT_LOG(ERR,
3608                              "could not calc rx priv buffer size for all TCs %d",
3609                              ret);
3610                 return ret;
3611         }
3612
3613         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3614         if (ret) {
3615                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3616                 return ret;
3617         }
3618
3619         if (hns3_dev_dcb_supported(hw)) {
3620                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3621                 if (ret) {
3622                         PMD_INIT_LOG(ERR,
3623                                      "could not configure rx private waterline %d",
3624                                      ret);
3625                         return ret;
3626                 }
3627
3628                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3629                 if (ret) {
3630                         PMD_INIT_LOG(ERR,
3631                                      "could not configure common threshold %d",
3632                                      ret);
3633                         return ret;
3634                 }
3635         }
3636
3637         ret = hns3_common_wl_config(hw, &pkt_buf);
3638         if (ret)
3639                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3640                              ret);
3641
3642         return ret;
3643 }
3644
3645 static int
3646 hns3_mac_init(struct hns3_hw *hw)
3647 {
3648         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3649         struct hns3_mac *mac = &hw->mac;
3650         struct hns3_pf *pf = &hns->pf;
3651         int ret;
3652
3653         pf->support_sfp_query = true;
3654         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3655         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3656         if (ret) {
3657                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3658                 return ret;
3659         }
3660
3661         mac->link_status = ETH_LINK_DOWN;
3662
3663         return hns3_config_mtu(hw, pf->mps);
3664 }
3665
3666 static int
3667 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3668 {
3669 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3670 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3671 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3672 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3673         int return_status;
3674
3675         if (cmdq_resp) {
3676                 PMD_INIT_LOG(ERR,
3677                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3678                              cmdq_resp);
3679                 return -EIO;
3680         }
3681
3682         switch (resp_code) {
3683         case HNS3_ETHERTYPE_SUCCESS_ADD:
3684         case HNS3_ETHERTYPE_ALREADY_ADD:
3685                 return_status = 0;
3686                 break;
3687         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3688                 PMD_INIT_LOG(ERR,
3689                              "add mac ethertype failed for manager table overflow.");
3690                 return_status = -EIO;
3691                 break;
3692         case HNS3_ETHERTYPE_KEY_CONFLICT:
3693                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3694                 return_status = -EIO;
3695                 break;
3696         default:
3697                 PMD_INIT_LOG(ERR,
3698                              "add mac ethertype failed for undefined, code=%d.",
3699                              resp_code);
3700                 return_status = -EIO;
3701                 break;
3702         }
3703
3704         return return_status;
3705 }
3706
3707 static int
3708 hns3_add_mgr_tbl(struct hns3_hw *hw,
3709                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3710 {
3711         struct hns3_cmd_desc desc;
3712         uint8_t resp_code;
3713         uint16_t retval;
3714         int ret;
3715
3716         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3717         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3718
3719         ret = hns3_cmd_send(hw, &desc, 1);
3720         if (ret) {
3721                 PMD_INIT_LOG(ERR,
3722                              "add mac ethertype failed for cmd_send, ret =%d.",
3723                              ret);
3724                 return ret;
3725         }
3726
3727         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3728         retval = rte_le_to_cpu_16(desc.retval);
3729
3730         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3731 }
3732
3733 static void
3734 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3735                      int *table_item_num)
3736 {
3737         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3738
3739         /*
3740          * In current version, we add one item in management table as below:
3741          * 0x0180C200000E -- LLDP MC address
3742          */
3743         tbl = mgr_table;
3744         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3745         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3746         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3747         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3748         tbl->i_port_bitmap = 0x1;
3749         *table_item_num = 1;
3750 }
3751
3752 static int
3753 hns3_init_mgr_tbl(struct hns3_hw *hw)
3754 {
3755 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3756         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3757         int table_item_num;
3758         int ret;
3759         int i;
3760
3761         memset(mgr_table, 0, sizeof(mgr_table));
3762         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3763         for (i = 0; i < table_item_num; i++) {
3764                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3765                 if (ret) {
3766                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3767                                      ret);
3768                         return ret;
3769                 }
3770         }
3771
3772         return 0;
3773 }
3774
3775 static void
3776 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3777                         bool en_mc, bool en_bc, int vport_id)
3778 {
3779         if (!param)
3780                 return;
3781
3782         memset(param, 0, sizeof(struct hns3_promisc_param));
3783         if (en_uc)
3784                 param->enable = HNS3_PROMISC_EN_UC;
3785         if (en_mc)
3786                 param->enable |= HNS3_PROMISC_EN_MC;
3787         if (en_bc)
3788                 param->enable |= HNS3_PROMISC_EN_BC;
3789         param->vf_id = vport_id;
3790 }
3791
3792 static int
3793 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3794 {
3795         struct hns3_promisc_cfg_cmd *req;
3796         struct hns3_cmd_desc desc;
3797         int ret;
3798
3799         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3800
3801         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3802         req->vf_id = param->vf_id;
3803         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3804             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3805
3806         ret = hns3_cmd_send(hw, &desc, 1);
3807         if (ret)
3808                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3809
3810         return ret;
3811 }
3812
3813 static int
3814 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3815 {
3816         struct hns3_promisc_param param;
3817         bool en_bc_pmc = true;
3818         uint8_t vf_id;
3819
3820         /*
3821          * In current version VF is not supported when PF is driven by DPDK
3822          * driver, just need to configure parameters for PF vport.
3823          */
3824         vf_id = HNS3_PF_FUNC_ID;
3825
3826         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3827         return hns3_cmd_set_promisc_mode(hw, &param);
3828 }
3829
3830 static int
3831 hns3_promisc_init(struct hns3_hw *hw)
3832 {
3833         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3834         struct hns3_pf *pf = &hns->pf;
3835         struct hns3_promisc_param param;
3836         uint16_t func_id;
3837         int ret;
3838
3839         ret = hns3_set_promisc_mode(hw, false, false);
3840         if (ret) {
3841                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3842                 return ret;
3843         }
3844
3845         /*
3846          * In current version VFs are not supported when PF is driven by DPDK
3847          * driver. After PF has been taken over by DPDK, the original VF will
3848          * be invalid. So, there is a possibility of entry residues. It should
3849          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3850          * during init.
3851          */
3852         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3853                 hns3_promisc_param_init(&param, false, false, false, func_id);
3854                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3855                 if (ret) {
3856                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3857                                         " ret = %d", func_id, ret);
3858                         return ret;
3859                 }
3860         }
3861
3862         return 0;
3863 }
3864
3865 static void
3866 hns3_promisc_uninit(struct hns3_hw *hw)
3867 {
3868         struct hns3_promisc_param param;
3869         uint16_t func_id;
3870         int ret;
3871
3872         func_id = HNS3_PF_FUNC_ID;
3873
3874         /*
3875          * In current version VFs are not supported when PF is driven by
3876          * DPDK driver, and VFs' promisc mode status has been cleared during
3877          * init and their status will not change. So just clear PF's promisc
3878          * mode status during uninit.
3879          */
3880         hns3_promisc_param_init(&param, false, false, false, func_id);
3881         ret = hns3_cmd_set_promisc_mode(hw, &param);
3882         if (ret)
3883                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3884                                 " uninit, ret = %d", ret);
3885 }
3886
3887 static int
3888 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3889 {
3890         bool allmulti = dev->data->all_multicast ? true : false;
3891         struct hns3_adapter *hns = dev->data->dev_private;
3892         struct hns3_hw *hw = &hns->hw;
3893         uint64_t offloads;
3894         int err;
3895         int ret;
3896
3897         rte_spinlock_lock(&hw->lock);
3898         ret = hns3_set_promisc_mode(hw, true, true);
3899         if (ret) {
3900                 rte_spinlock_unlock(&hw->lock);
3901                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3902                          ret);
3903                 return ret;
3904         }
3905
3906         /*
3907          * When promiscuous mode was enabled, disable the vlan filter to let
3908          * all packets coming in in the receiving direction.
3909          */
3910         offloads = dev->data->dev_conf.rxmode.offloads;
3911         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3912                 ret = hns3_enable_vlan_filter(hns, false);
3913                 if (ret) {
3914                         hns3_err(hw, "failed to enable promiscuous mode due to "
3915                                      "failure to disable vlan filter, ret = %d",
3916                                  ret);
3917                         err = hns3_set_promisc_mode(hw, false, allmulti);
3918                         if (err)
3919                                 hns3_err(hw, "failed to restore promiscuous "
3920                                          "status after disable vlan filter "
3921                                          "failed during enabling promiscuous "
3922                                          "mode, ret = %d", ret);
3923                 }
3924         }
3925
3926         rte_spinlock_unlock(&hw->lock);
3927
3928         return ret;
3929 }
3930
3931 static int
3932 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3933 {
3934         bool allmulti = dev->data->all_multicast ? true : false;
3935         struct hns3_adapter *hns = dev->data->dev_private;
3936         struct hns3_hw *hw = &hns->hw;
3937         uint64_t offloads;
3938         int err;
3939         int ret;
3940
3941         /* If now in all_multicast mode, must remain in all_multicast mode. */
3942         rte_spinlock_lock(&hw->lock);
3943         ret = hns3_set_promisc_mode(hw, false, allmulti);
3944         if (ret) {
3945                 rte_spinlock_unlock(&hw->lock);
3946                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3947                          ret);
3948                 return ret;
3949         }
3950         /* when promiscuous mode was disabled, restore the vlan filter status */
3951         offloads = dev->data->dev_conf.rxmode.offloads;
3952         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3953                 ret = hns3_enable_vlan_filter(hns, true);
3954                 if (ret) {
3955                         hns3_err(hw, "failed to disable promiscuous mode due to"
3956                                  " failure to restore vlan filter, ret = %d",
3957                                  ret);
3958                         err = hns3_set_promisc_mode(hw, true, true);
3959                         if (err)
3960                                 hns3_err(hw, "failed to restore promiscuous "
3961                                          "status after enabling vlan filter "
3962                                          "failed during disabling promiscuous "
3963                                          "mode, ret = %d", ret);
3964                 }
3965         }
3966         rte_spinlock_unlock(&hw->lock);
3967
3968         return ret;
3969 }
3970
3971 static int
3972 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3973 {
3974         struct hns3_adapter *hns = dev->data->dev_private;
3975         struct hns3_hw *hw = &hns->hw;
3976         int ret;
3977
3978         if (dev->data->promiscuous)
3979                 return 0;
3980
3981         rte_spinlock_lock(&hw->lock);
3982         ret = hns3_set_promisc_mode(hw, false, true);
3983         rte_spinlock_unlock(&hw->lock);
3984         if (ret)
3985                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3986                          ret);
3987
3988         return ret;
3989 }
3990
3991 static int
3992 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3993 {
3994         struct hns3_adapter *hns = dev->data->dev_private;
3995         struct hns3_hw *hw = &hns->hw;
3996         int ret;
3997
3998         /* If now in promiscuous mode, must remain in all_multicast mode. */
3999         if (dev->data->promiscuous)
4000                 return 0;
4001
4002         rte_spinlock_lock(&hw->lock);
4003         ret = hns3_set_promisc_mode(hw, false, false);
4004         rte_spinlock_unlock(&hw->lock);
4005         if (ret)
4006                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4007                          ret);
4008
4009         return ret;
4010 }
4011
4012 static int
4013 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4014 {
4015         struct hns3_hw *hw = &hns->hw;
4016         bool allmulti = hw->data->all_multicast ? true : false;
4017         int ret;
4018
4019         if (hw->data->promiscuous) {
4020                 ret = hns3_set_promisc_mode(hw, true, true);
4021                 if (ret)
4022                         hns3_err(hw, "failed to restore promiscuous mode, "
4023                                  "ret = %d", ret);
4024                 return ret;
4025         }
4026
4027         ret = hns3_set_promisc_mode(hw, false, allmulti);
4028         if (ret)
4029                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4030                          ret);
4031         return ret;
4032 }
4033
4034 static int
4035 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4036 {
4037         struct hns3_sfp_speed_cmd *resp;
4038         struct hns3_cmd_desc desc;
4039         int ret;
4040
4041         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4042         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4043         ret = hns3_cmd_send(hw, &desc, 1);
4044         if (ret == -EOPNOTSUPP) {
4045                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4046                 return ret;
4047         } else if (ret) {
4048                 hns3_err(hw, "get sfp speed failed %d", ret);
4049                 return ret;
4050         }
4051
4052         *speed = resp->sfp_speed;
4053
4054         return 0;
4055 }
4056
4057 static uint8_t
4058 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4059 {
4060         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4061                 duplex = ETH_LINK_FULL_DUPLEX;
4062
4063         return duplex;
4064 }
4065
4066 static int
4067 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4068 {
4069         struct hns3_mac *mac = &hw->mac;
4070         int ret;
4071
4072         duplex = hns3_check_speed_dup(duplex, speed);
4073         if (mac->link_speed == speed && mac->link_duplex == duplex)
4074                 return 0;
4075
4076         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4077         if (ret)
4078                 return ret;
4079
4080         mac->link_speed = speed;
4081         mac->link_duplex = duplex;
4082
4083         return 0;
4084 }
4085
4086 static int
4087 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4088 {
4089         struct hns3_adapter *hns = eth_dev->data->dev_private;
4090         struct hns3_hw *hw = &hns->hw;
4091         struct hns3_pf *pf = &hns->pf;
4092         uint32_t speed;
4093         int ret;
4094
4095         /* If IMP do not support get SFP/qSFP speed, return directly */
4096         if (!pf->support_sfp_query)
4097                 return 0;
4098
4099         ret = hns3_get_sfp_speed(hw, &speed);
4100         if (ret == -EOPNOTSUPP) {
4101                 pf->support_sfp_query = false;
4102                 return ret;
4103         } else if (ret)
4104                 return ret;
4105
4106         if (speed == ETH_SPEED_NUM_NONE)
4107                 return 0; /* do nothing if no SFP */
4108
4109         /* Config full duplex for SFP */
4110         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4111 }
4112
4113 static int
4114 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4115 {
4116         struct hns3_config_mac_mode_cmd *req;
4117         struct hns3_cmd_desc desc;
4118         uint32_t loop_en = 0;
4119         uint8_t val = 0;
4120         int ret;
4121
4122         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4123
4124         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4125         if (enable)
4126                 val = 1;
4127         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4128         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4129         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4130         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4131         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4132         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4133         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4134         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4135         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4136         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4137         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4138         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4139         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4140         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4141         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4142
4143         ret = hns3_cmd_send(hw, &desc, 1);
4144         if (ret)
4145                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4146
4147         return ret;
4148 }
4149
4150 static int
4151 hns3_get_mac_link_status(struct hns3_hw *hw)
4152 {
4153         struct hns3_link_status_cmd *req;
4154         struct hns3_cmd_desc desc;
4155         int link_status;
4156         int ret;
4157
4158         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4159         ret = hns3_cmd_send(hw, &desc, 1);
4160         if (ret) {
4161                 hns3_err(hw, "get link status cmd failed %d", ret);
4162                 return ETH_LINK_DOWN;
4163         }
4164
4165         req = (struct hns3_link_status_cmd *)desc.data;
4166         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4167
4168         return !!link_status;
4169 }
4170
4171 void
4172 hns3_update_link_status(struct hns3_hw *hw)
4173 {
4174         int state;
4175
4176         state = hns3_get_mac_link_status(hw);
4177         if (state != hw->mac.link_status) {
4178                 hw->mac.link_status = state;
4179                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4180         }
4181 }
4182
4183 static void
4184 hns3_service_handler(void *param)
4185 {
4186         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4187         struct hns3_adapter *hns = eth_dev->data->dev_private;
4188         struct hns3_hw *hw = &hns->hw;
4189
4190         if (!hns3_is_reset_pending(hns)) {
4191                 hns3_update_speed_duplex(eth_dev);
4192                 hns3_update_link_status(hw);
4193         } else
4194                 hns3_warn(hw, "Cancel the query when reset is pending");
4195
4196         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4197 }
4198
4199 static int
4200 hns3_init_hardware(struct hns3_adapter *hns)
4201 {
4202         struct hns3_hw *hw = &hns->hw;
4203         int ret;
4204
4205         ret = hns3_map_tqp(hw);
4206         if (ret) {
4207                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4208                 return ret;
4209         }
4210
4211         ret = hns3_init_umv_space(hw);
4212         if (ret) {
4213                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4214                 return ret;
4215         }
4216
4217         ret = hns3_mac_init(hw);
4218         if (ret) {
4219                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4220                 goto err_mac_init;
4221         }
4222
4223         ret = hns3_init_mgr_tbl(hw);
4224         if (ret) {
4225                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4226                 goto err_mac_init;
4227         }
4228
4229         ret = hns3_promisc_init(hw);
4230         if (ret) {
4231                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4232                              ret);
4233                 goto err_mac_init;
4234         }
4235
4236         ret = hns3_init_vlan_config(hns);
4237         if (ret) {
4238                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4239                 goto err_mac_init;
4240         }
4241
4242         ret = hns3_dcb_init(hw);
4243         if (ret) {
4244                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4245                 goto err_mac_init;
4246         }
4247
4248         ret = hns3_init_fd_config(hns);
4249         if (ret) {
4250                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4251                 goto err_mac_init;
4252         }
4253
4254         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4255         if (ret) {
4256                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4257                 goto err_mac_init;
4258         }
4259
4260         ret = hns3_config_gro(hw, false);
4261         if (ret) {
4262                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4263                 goto err_mac_init;
4264         }
4265
4266         /*
4267          * In the initialization clearing the all hardware mapping relationship
4268          * configurations between queues and interrupt vectors is needed, so
4269          * some error caused by the residual configurations, such as the
4270          * unexpected interrupt, can be avoid.
4271          */
4272         ret = hns3_init_ring_with_vector(hw);
4273         if (ret) {
4274                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4275                 goto err_mac_init;
4276         }
4277
4278         return 0;
4279
4280 err_mac_init:
4281         hns3_uninit_umv_space(hw);
4282         return ret;
4283 }
4284
4285 static int
4286 hns3_init_pf(struct rte_eth_dev *eth_dev)
4287 {
4288         struct rte_device *dev = eth_dev->device;
4289         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4290         struct hns3_adapter *hns = eth_dev->data->dev_private;
4291         struct hns3_hw *hw = &hns->hw;
4292         int ret;
4293
4294         PMD_INIT_FUNC_TRACE();
4295
4296         /* Get hardware io base address from pcie BAR2 IO space */
4297         hw->io_base = pci_dev->mem_resource[2].addr;
4298
4299         /* Firmware command queue initialize */
4300         ret = hns3_cmd_init_queue(hw);
4301         if (ret) {
4302                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4303                 goto err_cmd_init_queue;
4304         }
4305
4306         hns3_clear_all_event_cause(hw);
4307
4308         /* Firmware command initialize */
4309         ret = hns3_cmd_init(hw);
4310         if (ret) {
4311                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4312                 goto err_cmd_init;
4313         }
4314
4315         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4316                                          hns3_interrupt_handler,
4317                                          eth_dev);
4318         if (ret) {
4319                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4320                 goto err_intr_callback_register;
4321         }
4322
4323         /* Enable interrupt */
4324         rte_intr_enable(&pci_dev->intr_handle);
4325         hns3_pf_enable_irq0(hw);
4326
4327         /* Get configuration */
4328         ret = hns3_get_configuration(hw);
4329         if (ret) {
4330                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4331                 goto err_get_config;
4332         }
4333
4334         ret = hns3_init_hardware(hns);
4335         if (ret) {
4336                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4337                 goto err_get_config;
4338         }
4339
4340         /* Initialize flow director filter list & hash */
4341         ret = hns3_fdir_filter_init(hns);
4342         if (ret) {
4343                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4344                 goto err_hw_init;
4345         }
4346
4347         hns3_set_default_rss_args(hw);
4348
4349         ret = hns3_enable_hw_error_intr(hns, true);
4350         if (ret) {
4351                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4352                              ret);
4353                 goto err_fdir;
4354         }
4355
4356         return 0;
4357
4358 err_fdir:
4359         hns3_fdir_filter_uninit(hns);
4360 err_hw_init:
4361         hns3_uninit_umv_space(hw);
4362
4363 err_get_config:
4364         hns3_pf_disable_irq0(hw);
4365         rte_intr_disable(&pci_dev->intr_handle);
4366         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4367                              eth_dev);
4368 err_intr_callback_register:
4369 err_cmd_init:
4370         hns3_cmd_uninit(hw);
4371         hns3_cmd_destroy_queue(hw);
4372 err_cmd_init_queue:
4373         hw->io_base = NULL;
4374
4375         return ret;
4376 }
4377
4378 static void
4379 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4380 {
4381         struct hns3_adapter *hns = eth_dev->data->dev_private;
4382         struct rte_device *dev = eth_dev->device;
4383         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4384         struct hns3_hw *hw = &hns->hw;
4385
4386         PMD_INIT_FUNC_TRACE();
4387
4388         hns3_enable_hw_error_intr(hns, false);
4389         hns3_rss_uninit(hns);
4390         (void)hns3_config_gro(hw, false);
4391         hns3_promisc_uninit(hw);
4392         hns3_fdir_filter_uninit(hns);
4393         hns3_uninit_umv_space(hw);
4394         hns3_pf_disable_irq0(hw);
4395         rte_intr_disable(&pci_dev->intr_handle);
4396         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4397                              eth_dev);
4398         hns3_cmd_uninit(hw);
4399         hns3_cmd_destroy_queue(hw);
4400         hw->io_base = NULL;
4401 }
4402
4403 static int
4404 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4405 {
4406         struct hns3_hw *hw = &hns->hw;
4407         int ret;
4408
4409         ret = hns3_dcb_cfg_update(hns);
4410         if (ret)
4411                 return ret;
4412
4413         /* Enable queues */
4414         ret = hns3_start_queues(hns, reset_queue);
4415         if (ret) {
4416                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4417                 return ret;
4418         }
4419
4420         /* Enable MAC */
4421         ret = hns3_cfg_mac_mode(hw, true);
4422         if (ret) {
4423                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4424                 goto err_config_mac_mode;
4425         }
4426         return 0;
4427
4428 err_config_mac_mode:
4429         hns3_stop_queues(hns, true);
4430         return ret;
4431 }
4432
4433 static int
4434 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4435 {
4436         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4438         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4440         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4441         uint32_t intr_vector;
4442         uint16_t q_id;
4443         int ret;
4444
4445         if (dev->data->dev_conf.intr_conf.rxq == 0)
4446                 return 0;
4447
4448         /* disable uio/vfio intr/eventfd mapping */
4449         rte_intr_disable(intr_handle);
4450
4451         /* check and configure queue intr-vector mapping */
4452         if (rte_intr_cap_multiple(intr_handle) ||
4453             !RTE_ETH_DEV_SRIOV(dev).active) {
4454                 intr_vector = hw->used_rx_queues;
4455                 /* creates event fd for each intr vector when MSIX is used */
4456                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4457                         return -EINVAL;
4458         }
4459         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4460                 intr_handle->intr_vec =
4461                         rte_zmalloc("intr_vec",
4462                                     hw->used_rx_queues * sizeof(int), 0);
4463                 if (intr_handle->intr_vec == NULL) {
4464                         hns3_err(hw, "Failed to allocate %d rx_queues"
4465                                      " intr_vec", hw->used_rx_queues);
4466                         ret = -ENOMEM;
4467                         goto alloc_intr_vec_error;
4468                 }
4469         }
4470
4471         if (rte_intr_allow_others(intr_handle)) {
4472                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4473                 base = RTE_INTR_VEC_RXTX_OFFSET;
4474         }
4475         if (rte_intr_dp_is_en(intr_handle)) {
4476                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4477                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4478                                                          HNS3_RING_TYPE_RX,
4479                                                          q_id);
4480                         if (ret)
4481                                 goto bind_vector_error;
4482                         intr_handle->intr_vec[q_id] = vec;
4483                         if (vec < base + intr_handle->nb_efd - 1)
4484                                 vec++;
4485                 }
4486         }
4487         rte_intr_enable(intr_handle);
4488         return 0;
4489
4490 bind_vector_error:
4491         rte_intr_efd_disable(intr_handle);
4492         if (intr_handle->intr_vec) {
4493                 free(intr_handle->intr_vec);
4494                 intr_handle->intr_vec = NULL;
4495         }
4496         return ret;
4497 alloc_intr_vec_error:
4498         rte_intr_efd_disable(intr_handle);
4499         return ret;
4500 }
4501
4502 static int
4503 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4504 {
4505         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4507         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4508         uint16_t q_id;
4509         int ret;
4510
4511         if (dev->data->dev_conf.intr_conf.rxq == 0)
4512                 return 0;
4513
4514         if (rte_intr_dp_is_en(intr_handle)) {
4515                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4516                         ret = hns3_bind_ring_with_vector(hw,
4517                                         intr_handle->intr_vec[q_id], true,
4518                                         HNS3_RING_TYPE_RX, q_id);
4519                         if (ret)
4520                                 return ret;
4521                 }
4522         }
4523
4524         return 0;
4525 }
4526
4527 static void
4528 hns3_restore_filter(struct rte_eth_dev *dev)
4529 {
4530         hns3_restore_rss_filter(dev);
4531 }
4532
4533 static int
4534 hns3_dev_start(struct rte_eth_dev *dev)
4535 {
4536         struct hns3_adapter *hns = dev->data->dev_private;
4537         struct hns3_hw *hw = &hns->hw;
4538         int ret;
4539
4540         PMD_INIT_FUNC_TRACE();
4541         if (rte_atomic16_read(&hw->reset.resetting))
4542                 return -EBUSY;
4543
4544         rte_spinlock_lock(&hw->lock);
4545         hw->adapter_state = HNS3_NIC_STARTING;
4546
4547         ret = hns3_do_start(hns, true);
4548         if (ret) {
4549                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4550                 rte_spinlock_unlock(&hw->lock);
4551                 return ret;
4552         }
4553         ret = hns3_map_rx_interrupt(dev);
4554         if (ret) {
4555                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4556                 rte_spinlock_unlock(&hw->lock);
4557                 return ret;
4558         }
4559
4560         hw->adapter_state = HNS3_NIC_STARTED;
4561         rte_spinlock_unlock(&hw->lock);
4562
4563         hns3_set_rxtx_function(dev);
4564         hns3_mp_req_start_rxtx(dev);
4565         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4566
4567         hns3_restore_filter(dev);
4568
4569         /* Enable interrupt of all rx queues before enabling queues */
4570         hns3_dev_all_rx_queue_intr_enable(hw, true);
4571         /*
4572          * When finished the initialization, enable queues to receive/transmit
4573          * packets.
4574          */
4575         hns3_enable_all_queues(hw, true);
4576
4577         hns3_info(hw, "hns3 dev start successful!");
4578         return 0;
4579 }
4580
4581 static int
4582 hns3_do_stop(struct hns3_adapter *hns)
4583 {
4584         struct hns3_hw *hw = &hns->hw;
4585         bool reset_queue;
4586         int ret;
4587
4588         ret = hns3_cfg_mac_mode(hw, false);
4589         if (ret)
4590                 return ret;
4591         hw->mac.link_status = ETH_LINK_DOWN;
4592
4593         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4594                 hns3_configure_all_mac_addr(hns, true);
4595                 reset_queue = true;
4596         } else
4597                 reset_queue = false;
4598         hw->mac.default_addr_setted = false;
4599         return hns3_stop_queues(hns, reset_queue);
4600 }
4601
4602 static void
4603 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4604 {
4605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4607         struct hns3_adapter *hns = dev->data->dev_private;
4608         struct hns3_hw *hw = &hns->hw;
4609         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4610         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4611         uint16_t q_id;
4612
4613         if (dev->data->dev_conf.intr_conf.rxq == 0)
4614                 return;
4615
4616         /* unmap the ring with vector */
4617         if (rte_intr_allow_others(intr_handle)) {
4618                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4619                 base = RTE_INTR_VEC_RXTX_OFFSET;
4620         }
4621         if (rte_intr_dp_is_en(intr_handle)) {
4622                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4623                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4624                                                          HNS3_RING_TYPE_RX,
4625                                                          q_id);
4626                         if (vec < base + intr_handle->nb_efd - 1)
4627                                 vec++;
4628                 }
4629         }
4630         /* Clean datapath event and queue/vec mapping */
4631         rte_intr_efd_disable(intr_handle);
4632         if (intr_handle->intr_vec) {
4633                 rte_free(intr_handle->intr_vec);
4634                 intr_handle->intr_vec = NULL;
4635         }
4636 }
4637
4638 static void
4639 hns3_dev_stop(struct rte_eth_dev *dev)
4640 {
4641         struct hns3_adapter *hns = dev->data->dev_private;
4642         struct hns3_hw *hw = &hns->hw;
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         hw->adapter_state = HNS3_NIC_STOPPING;
4647         hns3_set_rxtx_function(dev);
4648         rte_wmb();
4649         /* Disable datapath on secondary process. */
4650         hns3_mp_req_stop_rxtx(dev);
4651         /* Prevent crashes when queues are still in use. */
4652         rte_delay_ms(hw->tqps_num);
4653
4654         rte_spinlock_lock(&hw->lock);
4655         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4656                 hns3_do_stop(hns);
4657                 hns3_unmap_rx_interrupt(dev);
4658                 hns3_dev_release_mbufs(hns);
4659                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4660         }
4661         rte_eal_alarm_cancel(hns3_service_handler, dev);
4662         rte_spinlock_unlock(&hw->lock);
4663 }
4664
4665 static void
4666 hns3_dev_close(struct rte_eth_dev *eth_dev)
4667 {
4668         struct hns3_adapter *hns = eth_dev->data->dev_private;
4669         struct hns3_hw *hw = &hns->hw;
4670
4671         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4672                 rte_free(eth_dev->process_private);
4673                 eth_dev->process_private = NULL;
4674                 return;
4675         }
4676
4677         if (hw->adapter_state == HNS3_NIC_STARTED)
4678                 hns3_dev_stop(eth_dev);
4679
4680         hw->adapter_state = HNS3_NIC_CLOSING;
4681         hns3_reset_abort(hns);
4682         hw->adapter_state = HNS3_NIC_CLOSED;
4683
4684         hns3_configure_all_mc_mac_addr(hns, true);
4685         hns3_remove_all_vlan_table(hns);
4686         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4687         hns3_uninit_pf(eth_dev);
4688         hns3_free_all_queues(eth_dev);
4689         rte_free(hw->reset.wait_data);
4690         rte_free(eth_dev->process_private);
4691         eth_dev->process_private = NULL;
4692         hns3_mp_uninit_primary();
4693         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4694 }
4695
4696 static int
4697 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4698 {
4699         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4701
4702         fc_conf->pause_time = pf->pause_time;
4703
4704         /* return fc current mode */
4705         switch (hw->current_mode) {
4706         case HNS3_FC_FULL:
4707                 fc_conf->mode = RTE_FC_FULL;
4708                 break;
4709         case HNS3_FC_TX_PAUSE:
4710                 fc_conf->mode = RTE_FC_TX_PAUSE;
4711                 break;
4712         case HNS3_FC_RX_PAUSE:
4713                 fc_conf->mode = RTE_FC_RX_PAUSE;
4714                 break;
4715         case HNS3_FC_NONE:
4716         default:
4717                 fc_conf->mode = RTE_FC_NONE;
4718                 break;
4719         }
4720
4721         return 0;
4722 }
4723
4724 static void
4725 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4726 {
4727         switch (mode) {
4728         case RTE_FC_NONE:
4729                 hw->requested_mode = HNS3_FC_NONE;
4730                 break;
4731         case RTE_FC_RX_PAUSE:
4732                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4733                 break;
4734         case RTE_FC_TX_PAUSE:
4735                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4736                 break;
4737         case RTE_FC_FULL:
4738                 hw->requested_mode = HNS3_FC_FULL;
4739                 break;
4740         default:
4741                 hw->requested_mode = HNS3_FC_NONE;
4742                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4743                           "configured to RTE_FC_NONE", mode);
4744                 break;
4745         }
4746 }
4747
4748 static int
4749 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4750 {
4751         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4752         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4753         int ret;
4754
4755         if (fc_conf->high_water || fc_conf->low_water ||
4756             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4757                 hns3_err(hw, "Unsupported flow control settings specified, "
4758                          "high_water(%u), low_water(%u), send_xon(%u) and "
4759                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4760                          fc_conf->high_water, fc_conf->low_water,
4761                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4762                 return -EINVAL;
4763         }
4764         if (fc_conf->autoneg) {
4765                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4766                 return -EINVAL;
4767         }
4768         if (!fc_conf->pause_time) {
4769                 hns3_err(hw, "Invalid pause time %d setting.",
4770                          fc_conf->pause_time);
4771                 return -EINVAL;
4772         }
4773
4774         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4775             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4776                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4777                          "current_fc_status = %d", hw->current_fc_status);
4778                 return -EOPNOTSUPP;
4779         }
4780
4781         hns3_get_fc_mode(hw, fc_conf->mode);
4782         if (hw->requested_mode == hw->current_mode &&
4783             pf->pause_time == fc_conf->pause_time)
4784                 return 0;
4785
4786         rte_spinlock_lock(&hw->lock);
4787         ret = hns3_fc_enable(dev, fc_conf);
4788         rte_spinlock_unlock(&hw->lock);
4789
4790         return ret;
4791 }
4792
4793 static int
4794 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4795                             struct rte_eth_pfc_conf *pfc_conf)
4796 {
4797         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4799         uint8_t priority;
4800         int ret;
4801
4802         if (!hns3_dev_dcb_supported(hw)) {
4803                 hns3_err(hw, "This port does not support dcb configurations.");
4804                 return -EOPNOTSUPP;
4805         }
4806
4807         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4808             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4809                 hns3_err(hw, "Unsupported flow control settings specified, "
4810                          "high_water(%u), low_water(%u), send_xon(%u) and "
4811                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4812                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4813                          pfc_conf->fc.send_xon,
4814                          pfc_conf->fc.mac_ctrl_frame_fwd);
4815                 return -EINVAL;
4816         }
4817         if (pfc_conf->fc.autoneg) {
4818                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4819                 return -EINVAL;
4820         }
4821         if (pfc_conf->fc.pause_time == 0) {
4822                 hns3_err(hw, "Invalid pause time %d setting.",
4823                          pfc_conf->fc.pause_time);
4824                 return -EINVAL;
4825         }
4826
4827         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4828             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4829                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4830                              "current_fc_status = %d", hw->current_fc_status);
4831                 return -EOPNOTSUPP;
4832         }
4833
4834         priority = pfc_conf->priority;
4835         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4836         if (hw->dcb_info.pfc_en & BIT(priority) &&
4837             hw->requested_mode == hw->current_mode &&
4838             pfc_conf->fc.pause_time == pf->pause_time)
4839                 return 0;
4840
4841         rte_spinlock_lock(&hw->lock);
4842         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4843         rte_spinlock_unlock(&hw->lock);
4844
4845         return ret;
4846 }
4847
4848 static int
4849 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4850 {
4851         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4853         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4854         int i;
4855
4856         rte_spinlock_lock(&hw->lock);
4857         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4858                 dcb_info->nb_tcs = pf->local_max_tc;
4859         else
4860                 dcb_info->nb_tcs = 1;
4861
4862         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4863                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4864         for (i = 0; i < dcb_info->nb_tcs; i++)
4865                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4866
4867         for (i = 0; i < hw->num_tc; i++) {
4868                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4869                 dcb_info->tc_queue.tc_txq[0][i].base =
4870                                                 hw->tc_queue[i].tqp_offset;
4871                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4872                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4873                                                 hw->tc_queue[i].tqp_count;
4874         }
4875         rte_spinlock_unlock(&hw->lock);
4876
4877         return 0;
4878 }
4879
4880 static int
4881 hns3_reinit_dev(struct hns3_adapter *hns)
4882 {
4883         struct hns3_hw *hw = &hns->hw;
4884         int ret;
4885
4886         ret = hns3_cmd_init(hw);
4887         if (ret) {
4888                 hns3_err(hw, "Failed to init cmd: %d", ret);
4889                 return ret;
4890         }
4891
4892         ret = hns3_reset_all_queues(hns);
4893         if (ret) {
4894                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4895                 return ret;
4896         }
4897
4898         ret = hns3_init_hardware(hns);
4899         if (ret) {
4900                 hns3_err(hw, "Failed to init hardware: %d", ret);
4901                 return ret;
4902         }
4903
4904         ret = hns3_enable_hw_error_intr(hns, true);
4905         if (ret) {
4906                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4907                              ret);
4908                 return ret;
4909         }
4910         hns3_info(hw, "Reset done, driver initialization finished.");
4911
4912         return 0;
4913 }
4914
4915 static bool
4916 is_pf_reset_done(struct hns3_hw *hw)
4917 {
4918         uint32_t val, reg, reg_bit;
4919
4920         switch (hw->reset.level) {
4921         case HNS3_IMP_RESET:
4922                 reg = HNS3_GLOBAL_RESET_REG;
4923                 reg_bit = HNS3_IMP_RESET_BIT;
4924                 break;
4925         case HNS3_GLOBAL_RESET:
4926                 reg = HNS3_GLOBAL_RESET_REG;
4927                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4928                 break;
4929         case HNS3_FUNC_RESET:
4930                 reg = HNS3_FUN_RST_ING;
4931                 reg_bit = HNS3_FUN_RST_ING_B;
4932                 break;
4933         case HNS3_FLR_RESET:
4934         default:
4935                 hns3_err(hw, "Wait for unsupported reset level: %d",
4936                          hw->reset.level);
4937                 return true;
4938         }
4939         val = hns3_read_dev(hw, reg);
4940         if (hns3_get_bit(val, reg_bit))
4941                 return false;
4942         else
4943                 return true;
4944 }
4945
4946 bool
4947 hns3_is_reset_pending(struct hns3_adapter *hns)
4948 {
4949         struct hns3_hw *hw = &hns->hw;
4950         enum hns3_reset_level reset;
4951
4952         hns3_check_event_cause(hns, NULL);
4953         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4954         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4955                 hns3_warn(hw, "High level reset %d is pending", reset);
4956                 return true;
4957         }
4958         reset = hns3_get_reset_level(hns, &hw->reset.request);
4959         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4960                 hns3_warn(hw, "High level reset %d is request", reset);
4961                 return true;
4962         }
4963         return false;
4964 }
4965
4966 static int
4967 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4968 {
4969         struct hns3_hw *hw = &hns->hw;
4970         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4971         struct timeval tv;
4972
4973         if (wait_data->result == HNS3_WAIT_SUCCESS)
4974                 return 0;
4975         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4976                 gettimeofday(&tv, NULL);
4977                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4978                           tv.tv_sec, tv.tv_usec);
4979                 return -ETIME;
4980         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4981                 return -EAGAIN;
4982
4983         wait_data->hns = hns;
4984         wait_data->check_completion = is_pf_reset_done;
4985         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4986                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4987         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4988         wait_data->count = HNS3_RESET_WAIT_CNT;
4989         wait_data->result = HNS3_WAIT_REQUEST;
4990         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4991         return -EAGAIN;
4992 }
4993
4994 static int
4995 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4996 {
4997         struct hns3_cmd_desc desc;
4998         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4999
5000         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5001         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5002         req->fun_reset_vfid = func_id;
5003
5004         return hns3_cmd_send(hw, &desc, 1);
5005 }
5006
5007 static int
5008 hns3_imp_reset_cmd(struct hns3_hw *hw)
5009 {
5010         struct hns3_cmd_desc desc;
5011
5012         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5013         desc.data[0] = 0xeedd;
5014
5015         return hns3_cmd_send(hw, &desc, 1);
5016 }
5017
5018 static void
5019 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5020 {
5021         struct hns3_hw *hw = &hns->hw;
5022         struct timeval tv;
5023         uint32_t val;
5024
5025         gettimeofday(&tv, NULL);
5026         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5027             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5028                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5029                           tv.tv_sec, tv.tv_usec);
5030                 return;
5031         }
5032
5033         switch (reset_level) {
5034         case HNS3_IMP_RESET:
5035                 hns3_imp_reset_cmd(hw);
5036                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5037                           tv.tv_sec, tv.tv_usec);
5038                 break;
5039         case HNS3_GLOBAL_RESET:
5040                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5041                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5042                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5043                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5044                           tv.tv_sec, tv.tv_usec);
5045                 break;
5046         case HNS3_FUNC_RESET:
5047                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5048                           tv.tv_sec, tv.tv_usec);
5049                 /* schedule again to check later */
5050                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5051                 hns3_schedule_reset(hns);
5052                 break;
5053         default:
5054                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5055                 return;
5056         }
5057         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5058 }
5059
5060 static enum hns3_reset_level
5061 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5062 {
5063         struct hns3_hw *hw = &hns->hw;
5064         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5065
5066         /* Return the highest priority reset level amongst all */
5067         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5068                 reset_level = HNS3_IMP_RESET;
5069         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5070                 reset_level = HNS3_GLOBAL_RESET;
5071         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5072                 reset_level = HNS3_FUNC_RESET;
5073         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5074                 reset_level = HNS3_FLR_RESET;
5075
5076         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5077                 return HNS3_NONE_RESET;
5078
5079         return reset_level;
5080 }
5081
5082 static int
5083 hns3_prepare_reset(struct hns3_adapter *hns)
5084 {
5085         struct hns3_hw *hw = &hns->hw;
5086         uint32_t reg_val;
5087         int ret;
5088
5089         switch (hw->reset.level) {
5090         case HNS3_FUNC_RESET:
5091                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5092                 if (ret)
5093                         return ret;
5094
5095                 /*
5096                  * After performaning pf reset, it is not necessary to do the
5097                  * mailbox handling or send any command to firmware, because
5098                  * any mailbox handling or command to firmware is only valid
5099                  * after hns3_cmd_init is called.
5100                  */
5101                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5102                 hw->reset.stats.request_cnt++;
5103                 break;
5104         case HNS3_IMP_RESET:
5105                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5106                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5107                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5108                 break;
5109         default:
5110                 break;
5111         }
5112         return 0;
5113 }
5114
5115 static int
5116 hns3_set_rst_done(struct hns3_hw *hw)
5117 {
5118         struct hns3_pf_rst_done_cmd *req;
5119         struct hns3_cmd_desc desc;
5120
5121         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5122         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5123         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5124         return hns3_cmd_send(hw, &desc, 1);
5125 }
5126
5127 static int
5128 hns3_stop_service(struct hns3_adapter *hns)
5129 {
5130         struct hns3_hw *hw = &hns->hw;
5131         struct rte_eth_dev *eth_dev;
5132
5133         eth_dev = &rte_eth_devices[hw->data->port_id];
5134         if (hw->adapter_state == HNS3_NIC_STARTED)
5135                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5136         hw->mac.link_status = ETH_LINK_DOWN;
5137
5138         hns3_set_rxtx_function(eth_dev);
5139         rte_wmb();
5140         /* Disable datapath on secondary process. */
5141         hns3_mp_req_stop_rxtx(eth_dev);
5142         rte_delay_ms(hw->tqps_num);
5143
5144         rte_spinlock_lock(&hw->lock);
5145         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5146             hw->adapter_state == HNS3_NIC_STOPPING) {
5147                 hns3_do_stop(hns);
5148                 hw->reset.mbuf_deferred_free = true;
5149         } else
5150                 hw->reset.mbuf_deferred_free = false;
5151
5152         /*
5153          * It is cumbersome for hardware to pick-and-choose entries for deletion
5154          * from table space. Hence, for function reset software intervention is
5155          * required to delete the entries
5156          */
5157         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5158                 hns3_configure_all_mc_mac_addr(hns, true);
5159         rte_spinlock_unlock(&hw->lock);
5160
5161         return 0;
5162 }
5163
5164 static int
5165 hns3_start_service(struct hns3_adapter *hns)
5166 {
5167         struct hns3_hw *hw = &hns->hw;
5168         struct rte_eth_dev *eth_dev;
5169
5170         if (hw->reset.level == HNS3_IMP_RESET ||
5171             hw->reset.level == HNS3_GLOBAL_RESET)
5172                 hns3_set_rst_done(hw);
5173         eth_dev = &rte_eth_devices[hw->data->port_id];
5174         hns3_set_rxtx_function(eth_dev);
5175         hns3_mp_req_start_rxtx(eth_dev);
5176         if (hw->adapter_state == HNS3_NIC_STARTED) {
5177                 hns3_service_handler(eth_dev);
5178
5179                 /* Enable interrupt of all rx queues before enabling queues */
5180                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5181                 /*
5182                  * When finished the initialization, enable queues to receive
5183                  * and transmit packets.
5184                  */
5185                 hns3_enable_all_queues(hw, true);
5186         }
5187
5188         return 0;
5189 }
5190
5191 static int
5192 hns3_restore_conf(struct hns3_adapter *hns)
5193 {
5194         struct hns3_hw *hw = &hns->hw;
5195         int ret;
5196
5197         ret = hns3_configure_all_mac_addr(hns, false);
5198         if (ret)
5199                 return ret;
5200
5201         ret = hns3_configure_all_mc_mac_addr(hns, false);
5202         if (ret)
5203                 goto err_mc_mac;
5204
5205         ret = hns3_dev_promisc_restore(hns);
5206         if (ret)
5207                 goto err_promisc;
5208
5209         ret = hns3_restore_vlan_table(hns);
5210         if (ret)
5211                 goto err_promisc;
5212
5213         ret = hns3_restore_vlan_conf(hns);
5214         if (ret)
5215                 goto err_promisc;
5216
5217         ret = hns3_restore_all_fdir_filter(hns);
5218         if (ret)
5219                 goto err_promisc;
5220
5221         ret = hns3_restore_rx_interrupt(hw);
5222         if (ret)
5223                 goto err_promisc;
5224
5225         ret = hns3_restore_gro_conf(hw);
5226         if (ret)
5227                 goto err_promisc;
5228
5229         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5230                 ret = hns3_do_start(hns, false);
5231                 if (ret)
5232                         goto err_promisc;
5233                 hns3_info(hw, "hns3 dev restart successful!");
5234         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5235                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5236         return 0;
5237
5238 err_promisc:
5239         hns3_configure_all_mc_mac_addr(hns, true);
5240 err_mc_mac:
5241         hns3_configure_all_mac_addr(hns, true);
5242         return ret;
5243 }
5244
5245 static void
5246 hns3_reset_service(void *param)
5247 {
5248         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5249         struct hns3_hw *hw = &hns->hw;
5250         enum hns3_reset_level reset_level;
5251         struct timeval tv_delta;
5252         struct timeval tv_start;
5253         struct timeval tv;
5254         uint64_t msec;
5255         int ret;
5256
5257         /*
5258          * The interrupt is not triggered within the delay time.
5259          * The interrupt may have been lost. It is necessary to handle
5260          * the interrupt to recover from the error.
5261          */
5262         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5263                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5264                 hns3_err(hw, "Handling interrupts in delayed tasks");
5265                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5266                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5267                 if (reset_level == HNS3_NONE_RESET) {
5268                         hns3_err(hw, "No reset level is set, try IMP reset");
5269                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5270                 }
5271         }
5272         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5273
5274         /*
5275          * Check if there is any ongoing reset in the hardware. This status can
5276          * be checked from reset_pending. If there is then, we need to wait for
5277          * hardware to complete reset.
5278          *    a. If we are able to figure out in reasonable time that hardware
5279          *       has fully resetted then, we can proceed with driver, client
5280          *       reset.
5281          *    b. else, we can come back later to check this status so re-sched
5282          *       now.
5283          */
5284         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5285         if (reset_level != HNS3_NONE_RESET) {
5286                 gettimeofday(&tv_start, NULL);
5287                 ret = hns3_reset_process(hns, reset_level);
5288                 gettimeofday(&tv, NULL);
5289                 timersub(&tv, &tv_start, &tv_delta);
5290                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5291                        tv_delta.tv_usec / USEC_PER_MSEC;
5292                 if (msec > HNS3_RESET_PROCESS_MS)
5293                         hns3_err(hw, "%d handle long time delta %" PRIx64
5294                                      " ms time=%ld.%.6ld",
5295                                  hw->reset.level, msec,
5296                                  tv.tv_sec, tv.tv_usec);
5297                 if (ret == -EAGAIN)
5298                         return;
5299         }
5300
5301         /* Check if we got any *new* reset requests to be honored */
5302         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5303         if (reset_level != HNS3_NONE_RESET)
5304                 hns3_msix_process(hns, reset_level);
5305 }
5306
5307 static const struct eth_dev_ops hns3_eth_dev_ops = {
5308         .dev_start          = hns3_dev_start,
5309         .dev_stop           = hns3_dev_stop,
5310         .dev_close          = hns3_dev_close,
5311         .promiscuous_enable = hns3_dev_promiscuous_enable,
5312         .promiscuous_disable = hns3_dev_promiscuous_disable,
5313         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5314         .allmulticast_disable = hns3_dev_allmulticast_disable,
5315         .mtu_set            = hns3_dev_mtu_set,
5316         .stats_get          = hns3_stats_get,
5317         .stats_reset        = hns3_stats_reset,
5318         .xstats_get         = hns3_dev_xstats_get,
5319         .xstats_get_names   = hns3_dev_xstats_get_names,
5320         .xstats_reset       = hns3_dev_xstats_reset,
5321         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5322         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5323         .dev_infos_get          = hns3_dev_infos_get,
5324         .fw_version_get         = hns3_fw_version_get,
5325         .rx_queue_setup         = hns3_rx_queue_setup,
5326         .tx_queue_setup         = hns3_tx_queue_setup,
5327         .rx_queue_release       = hns3_dev_rx_queue_release,
5328         .tx_queue_release       = hns3_dev_tx_queue_release,
5329         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5330         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5331         .dev_configure          = hns3_dev_configure,
5332         .flow_ctrl_get          = hns3_flow_ctrl_get,
5333         .flow_ctrl_set          = hns3_flow_ctrl_set,
5334         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5335         .mac_addr_add           = hns3_add_mac_addr,
5336         .mac_addr_remove        = hns3_remove_mac_addr,
5337         .mac_addr_set           = hns3_set_default_mac_addr,
5338         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5339         .link_update            = hns3_dev_link_update,
5340         .rss_hash_update        = hns3_dev_rss_hash_update,
5341         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5342         .reta_update            = hns3_dev_rss_reta_update,
5343         .reta_query             = hns3_dev_rss_reta_query,
5344         .filter_ctrl            = hns3_dev_filter_ctrl,
5345         .vlan_filter_set        = hns3_vlan_filter_set,
5346         .vlan_tpid_set          = hns3_vlan_tpid_set,
5347         .vlan_offload_set       = hns3_vlan_offload_set,
5348         .vlan_pvid_set          = hns3_vlan_pvid_set,
5349         .get_reg                = hns3_get_regs,
5350         .get_dcb_info           = hns3_get_dcb_info,
5351         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5352 };
5353
5354 static const struct hns3_reset_ops hns3_reset_ops = {
5355         .reset_service       = hns3_reset_service,
5356         .stop_service        = hns3_stop_service,
5357         .prepare_reset       = hns3_prepare_reset,
5358         .wait_hardware_ready = hns3_wait_hardware_ready,
5359         .reinit_dev          = hns3_reinit_dev,
5360         .restore_conf        = hns3_restore_conf,
5361         .start_service       = hns3_start_service,
5362 };
5363
5364 static int
5365 hns3_dev_init(struct rte_eth_dev *eth_dev)
5366 {
5367         struct rte_device *dev = eth_dev->device;
5368         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5369         struct hns3_adapter *hns = eth_dev->data->dev_private;
5370         struct hns3_hw *hw = &hns->hw;
5371         uint16_t device_id = pci_dev->id.device_id;
5372         uint8_t revision;
5373         int ret;
5374
5375         PMD_INIT_FUNC_TRACE();
5376
5377         /* Get PCI revision id */
5378         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5379                                   HNS3_PCI_REVISION_ID);
5380         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5381                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5382                              ret);
5383                 return -EIO;
5384         }
5385         hw->revision = revision;
5386
5387         eth_dev->process_private = (struct hns3_process_private *)
5388             rte_zmalloc_socket("hns3_filter_list",
5389                                sizeof(struct hns3_process_private),
5390                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5391         if (eth_dev->process_private == NULL) {
5392                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5393                 return -ENOMEM;
5394         }
5395         /* initialize flow filter lists */
5396         hns3_filterlist_init(eth_dev);
5397
5398         hns3_set_rxtx_function(eth_dev);
5399         eth_dev->dev_ops = &hns3_eth_dev_ops;
5400         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5401                 hns3_mp_init_secondary();
5402                 hw->secondary_cnt++;
5403                 return 0;
5404         }
5405
5406         hns3_mp_init_primary();
5407         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5408
5409         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5410             device_id == HNS3_DEV_ID_50GE_RDMA ||
5411             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5412                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5413
5414         hns->is_vf = false;
5415         hw->data = eth_dev->data;
5416
5417         /*
5418          * Set default max packet size according to the mtu
5419          * default vale in DPDK frame.
5420          */
5421         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5422
5423         ret = hns3_reset_init(hw);
5424         if (ret)
5425                 goto err_init_reset;
5426         hw->reset.ops = &hns3_reset_ops;
5427
5428         ret = hns3_init_pf(eth_dev);
5429         if (ret) {
5430                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5431                 goto err_init_pf;
5432         }
5433
5434         /* Allocate memory for storing MAC addresses */
5435         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5436                                                sizeof(struct rte_ether_addr) *
5437                                                HNS3_UC_MACADDR_NUM, 0);
5438         if (eth_dev->data->mac_addrs == NULL) {
5439                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5440                              "to store MAC addresses",
5441                              sizeof(struct rte_ether_addr) *
5442                              HNS3_UC_MACADDR_NUM);
5443                 ret = -ENOMEM;
5444                 goto err_rte_zmalloc;
5445         }
5446
5447         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5448                             &eth_dev->data->mac_addrs[0]);
5449
5450         hw->adapter_state = HNS3_NIC_INITIALIZED;
5451         /*
5452          * Pass the information to the rte_eth_dev_close() that it should also
5453          * release the private port resources.
5454          */
5455         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5456
5457         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5458                 hns3_err(hw, "Reschedule reset service after dev_init");
5459                 hns3_schedule_reset(hns);
5460         } else {
5461                 /* IMP will wait ready flag before reset */
5462                 hns3_notify_reset_ready(hw, false);
5463         }
5464
5465         hns3_info(hw, "hns3 dev initialization successful!");
5466         return 0;
5467
5468 err_rte_zmalloc:
5469         hns3_uninit_pf(eth_dev);
5470
5471 err_init_pf:
5472         rte_free(hw->reset.wait_data);
5473 err_init_reset:
5474         eth_dev->dev_ops = NULL;
5475         eth_dev->rx_pkt_burst = NULL;
5476         eth_dev->tx_pkt_burst = NULL;
5477         eth_dev->tx_pkt_prepare = NULL;
5478         rte_free(eth_dev->process_private);
5479         eth_dev->process_private = NULL;
5480         return ret;
5481 }
5482
5483 static int
5484 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5485 {
5486         struct hns3_adapter *hns = eth_dev->data->dev_private;
5487         struct hns3_hw *hw = &hns->hw;
5488
5489         PMD_INIT_FUNC_TRACE();
5490
5491         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5492                 return -EPERM;
5493
5494         eth_dev->dev_ops = NULL;
5495         eth_dev->rx_pkt_burst = NULL;
5496         eth_dev->tx_pkt_burst = NULL;
5497         eth_dev->tx_pkt_prepare = NULL;
5498         if (hw->adapter_state < HNS3_NIC_CLOSING)
5499                 hns3_dev_close(eth_dev);
5500
5501         hw->adapter_state = HNS3_NIC_REMOVED;
5502         return 0;
5503 }
5504
5505 static int
5506 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5507                    struct rte_pci_device *pci_dev)
5508 {
5509         return rte_eth_dev_pci_generic_probe(pci_dev,
5510                                              sizeof(struct hns3_adapter),
5511                                              hns3_dev_init);
5512 }
5513
5514 static int
5515 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5516 {
5517         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5518 }
5519
5520 static const struct rte_pci_id pci_id_hns3_map[] = {
5521         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5522         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5523         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5524         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5525         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5526         { .vendor_id = 0, /* sentinel */ },
5527 };
5528
5529 static struct rte_pci_driver rte_hns3_pmd = {
5530         .id_table = pci_id_hns3_map,
5531         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5532         .probe = eth_hns3_pci_probe,
5533         .remove = eth_hns3_pci_remove,
5534 };
5535
5536 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5537 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5538 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5539 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5540 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);