drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105
 106 void hns3_ether_format_addr(char *buf, uint16_t size,
 107                             const struct rte_ether_addr *ether_addr)
 108 {
 109         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 110                 ether_addr->addr_bytes[0],
 111                 ether_addr->addr_bytes[4],
 112                 ether_addr->addr_bytes[5]);
 113 }
 114
 115 static void
 116 hns3_pf_disable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 119 }
 120
 121 static void
 122 hns3_pf_enable_irq0(struct hns3_hw *hw)
 123 {
 124         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 125 }
 126
 127 static enum hns3_evt_cause
 128 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 129                           uint32_t *vec_val)
 130 {
 131         struct hns3_hw *hw = &hns->hw;
 132
 133         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 134         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 135         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 136         if (!is_delay) {
 137                 hw->reset.stats.imp_cnt++;
 138                 hns3_warn(hw, "IMP reset detected, clear reset status");
 139         } else {
 140                 hns3_schedule_delayed_reset(hns);
 141                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 142         }
 143
 144         return HNS3_VECTOR0_EVENT_RST;
 145 }
 146
 147 static enum hns3_evt_cause
 148 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 149                              uint32_t *vec_val)
 150 {
 151         struct hns3_hw *hw = &hns->hw;
 152
 153         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 154         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 155         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 156         if (!is_delay) {
 157                 hw->reset.stats.global_cnt++;
 158                 hns3_warn(hw, "Global reset detected, clear reset status");
 159         } else {
 160                 hns3_schedule_delayed_reset(hns);
 161                 hns3_warn(hw,
 162                           "Global reset detected, don't clear reset status");
 163         }
 164
 165         return HNS3_VECTOR0_EVENT_RST;
 166 }
 167
 168 static enum hns3_evt_cause
 169 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 170 {
 171         struct hns3_hw *hw = &hns->hw;
 172         uint32_t vector0_int_stats;
 173         uint32_t cmdq_src_val;
 174         uint32_t hw_err_src_reg;
 175         uint32_t val;
 176         enum hns3_evt_cause ret;
 177         bool is_delay;
 178
 179         /* fetch the events from their corresponding regs */
 180         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 181         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 182         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 183
 184         is_delay = clearval == NULL ? true : false;
 185         /*
 186          * Assumption: If by any chance reset and mailbox events are reported
 187          * together then we will only process reset event and defer the
 188          * processing of the mailbox events. Since, we would have not cleared
 189          * RX CMDQ event this time we would receive again another interrupt
 190          * from H/W just for the mailbox.
 191          */
 192         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 193                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Global reset */
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 199                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 200                 goto out;
 201         }
 202
 203         /* check for vector0 msix event source */
 204         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 205             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 206                 val = vector0_int_stats | hw_err_src_reg;
 207                 ret = HNS3_VECTOR0_EVENT_ERR;
 208                 goto out;
 209         }
 210
 211         /* check for vector0 mailbox(=CMDQ RX) event source */
 212         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 213                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 214                 val = cmdq_src_val;
 215                 ret = HNS3_VECTOR0_EVENT_MBX;
 216                 goto out;
 217         }
 218
 219         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 220                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 221                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 222         val = vector0_int_stats;
 223         ret = HNS3_VECTOR0_EVENT_OTHER;
 224 out:
 225
 226         if (clearval)
 227                 *clearval = val;
 228         return ret;
 229 }
 230
 231 static void
 232 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 233 {
 234         if (event_type == HNS3_VECTOR0_EVENT_RST)
 235                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 236         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 237                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 238 }
 239
 240 static void
 241 hns3_clear_all_event_cause(struct hns3_hw *hw)
 242 {
 243         uint32_t vector0_int_stats;
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245
 246         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 247                 hns3_warn(hw, "Probe during IMP reset interrupt");
 248
 249         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 250                 hns3_warn(hw, "Probe during Global reset interrupt");
 251
 252         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 253                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 255                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 257 }
 258
 259 static void
 260 hns3_interrupt_handler(void *param)
 261 {
 262         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 263         struct hns3_adapter *hns = dev->data->dev_private;
 264         struct hns3_hw *hw = &hns->hw;
 265         enum hns3_evt_cause event_cause;
 266         uint32_t clearval = 0;
 267
 268         /* Disable interrupt */
 269         hns3_pf_disable_irq0(hw);
 270
 271         event_cause = hns3_check_event_cause(hns, &clearval);
 272         /* vector 0 interrupt is shared with reset and mailbox source events. */
 273         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 274                 hns3_warn(hw, "Received err interrupt");
 275                 hns3_handle_msix_error(hns, &hw->reset.request);
 276                 hns3_handle_ras_error(hns, &hw->reset.request);
 277                 hns3_schedule_reset(hns);
 278         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 279                 hns3_warn(hw, "Received reset interrupt");
 280                 hns3_schedule_reset(hns);
 281         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 282                 hns3_dev_handle_mbx_msg(hw);
 283         else
 284                 hns3_err(hw, "Received unknown event");
 285
 286         hns3_clear_event_cause(hw, event_cause, clearval);
 287         /* Enable interrupt if it is not cause by reset */
 288         hns3_pf_enable_irq0(hw);
 289 }
 290
 291 static int
 292 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 293 {
 294 #define HNS3_VLAN_ID_OFFSET_STEP        160
 295 #define HNS3_VLAN_BYTE_SIZE             8
 296         struct hns3_vlan_filter_pf_cfg_cmd *req;
 297         struct hns3_hw *hw = &hns->hw;
 298         uint8_t vlan_offset_byte_val;
 299         struct hns3_cmd_desc desc;
 300         uint8_t vlan_offset_byte;
 301         uint8_t vlan_offset_base;
 302         int ret;
 303
 304         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 305
 306         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 307         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 308                            HNS3_VLAN_BYTE_SIZE;
 309         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 310
 311         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 312         req->vlan_offset = vlan_offset_base;
 313         req->vlan_cfg = on ? 0 : 1;
 314         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 315
 316         ret = hns3_cmd_send(hw, &desc, 1);
 317         if (ret)
 318                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 319                          vlan_id, ret);
 320
 321         return ret;
 322 }
 323
 324 static void
 325 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 326 {
 327         struct hns3_user_vlan_table *vlan_entry;
 328         struct hns3_pf *pf = &hns->pf;
 329
 330         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 331                 if (vlan_entry->vlan_id == vlan_id) {
 332                         if (vlan_entry->hd_tbl_status)
 333                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 334                         LIST_REMOVE(vlan_entry, next);
 335                         rte_free(vlan_entry);
 336                         break;
 337                 }
 338         }
 339 }
 340
 341 static void
 342 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 343                         bool writen_to_tbl)
 344 {
 345         struct hns3_user_vlan_table *vlan_entry;
 346         struct hns3_hw *hw = &hns->hw;
 347         struct hns3_pf *pf = &hns->pf;
 348
 349         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 350                 if (vlan_entry->vlan_id == vlan_id)
 351                         return;
 352         }
 353
 354         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 355         if (vlan_entry == NULL) {
 356                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 357                 return;
 358         }
 359
 360         vlan_entry->hd_tbl_status = writen_to_tbl;
 361         vlan_entry->vlan_id = vlan_id;
 362
 363         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 364 }
 365
 366 static int
 367 hns3_restore_vlan_table(struct hns3_adapter *hns)
 368 {
 369         struct hns3_user_vlan_table *vlan_entry;
 370         struct hns3_hw *hw = &hns->hw;
 371         struct hns3_pf *pf = &hns->pf;
 372         uint16_t vlan_id;
 373         int ret = 0;
 374
 375         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 376                 return hns3_vlan_pvid_configure(hns,
 377                                                 hw->port_base_vlan_cfg.pvid, 1);
 378
 379         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 380                 if (vlan_entry->hd_tbl_status) {
 381                         vlan_id = vlan_entry->vlan_id;
 382                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 383                         if (ret)
 384                                 break;
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int
 392 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 393 {
 394         struct hns3_hw *hw = &hns->hw;
 395         bool writen_to_tbl = false;
 396         int ret = 0;
 397
 398         /*
 399          * When vlan filter is enabled, hardware regards packets without vlan
 400          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 401          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 402          */
 403         if (on == 0 && vlan_id == 0)
 404                 return 0;
 405
 406         /*
 407          * When port base vlan enabled, we use port base vlan as the vlan
 408          * filter condition. In this case, we don't update vlan filter table
 409          * when user add new vlan or remove exist vlan, just update the
 410          * vlan list. The vlan id in vlan list will be writen in vlan filter
 411          * table until port base vlan disabled
 412          */
 413         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 414                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 415                 writen_to_tbl = true;
 416         }
 417
 418         if (ret == 0) {
 419                 if (on)
 420                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 421                 else
 422                         hns3_rm_dev_vlan_table(hns, vlan_id);
 423         }
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 429 {
 430         struct hns3_adapter *hns = dev->data->dev_private;
 431         struct hns3_hw *hw = &hns->hw;
 432         int ret;
 433
 434         rte_spinlock_lock(&hw->lock);
 435         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 436         rte_spinlock_unlock(&hw->lock);
 437         return ret;
 438 }
 439
 440 static int
 441 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 442                          uint16_t tpid)
 443 {
 444         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 445         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 446         struct hns3_hw *hw = &hns->hw;
 447         struct hns3_cmd_desc desc;
 448         int ret;
 449
 450         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 451              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 452                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 453                 return -EINVAL;
 454         }
 455
 456         if (tpid != RTE_ETHER_TYPE_VLAN) {
 457                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 458                 return -EINVAL;
 459         }
 460
 461         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 462         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 463
 464         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 465                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 466                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 467         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 468                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 471                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 472         }
 473
 474         ret = hns3_cmd_send(hw, &desc, 1);
 475         if (ret) {
 476                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 477                          ret);
 478                 return ret;
 479         }
 480
 481         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 482
 483         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 484         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 485         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 486
 487         ret = hns3_cmd_send(hw, &desc, 1);
 488         if (ret)
 489                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 490                          ret);
 491         return ret;
 492 }
 493
 494 static int
 495 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 496                    uint16_t tpid)
 497 {
 498         struct hns3_adapter *hns = dev->data->dev_private;
 499         struct hns3_hw *hw = &hns->hw;
 500         int ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 504         rte_spinlock_unlock(&hw->lock);
 505         return ret;
 506 }
 507
 508 static int
 509 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 510                              struct hns3_rx_vtag_cfg *vcfg)
 511 {
 512         struct hns3_vport_vtag_rx_cfg_cmd *req;
 513         struct hns3_hw *hw = &hns->hw;
 514         struct hns3_cmd_desc desc;
 515         uint16_t vport_id;
 516         uint8_t bitmap;
 517         int ret;
 518
 519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 520
 521         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 523                      vcfg->strip_tag1_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 525                      vcfg->strip_tag2_en ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 527                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 528         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 529                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 530
 531         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 533                      vcfg->strip_tag1_discard_en ? 1 : 0);
 534         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 535                      vcfg->strip_tag2_discard_en ? 1 : 0);
 536         /*
 537          * In current version VF is not supported when PF is driven by DPDK
 538          * driver, just need to configure parameters for PF vport.
 539          */
 540         vport_id = HNS3_PF_FUNC_ID;
 541         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 542         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 543         req->vf_bitmap[req->vf_offset] = bitmap;
 544
 545         ret = hns3_cmd_send(hw, &desc, 1);
 546         if (ret)
 547                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 548         return ret;
 549 }
 550
 551 static void
 552 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 553                            struct hns3_rx_vtag_cfg *vcfg)
 554 {
 555         struct hns3_pf *pf = &hns->pf;
 556         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 557 }
 558
 559 static void
 560 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 561                            struct hns3_tx_vtag_cfg *vcfg)
 562 {
 563         struct hns3_pf *pf = &hns->pf;
 564         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 565 }
 566
 567 static int
 568 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 569 {
 570         struct hns3_rx_vtag_cfg rxvlan_cfg;
 571         struct hns3_hw *hw = &hns->hw;
 572         int ret;
 573
 574         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 575                 rxvlan_cfg.strip_tag1_en = false;
 576                 rxvlan_cfg.strip_tag2_en = enable;
 577                 rxvlan_cfg.strip_tag2_discard_en = false;
 578         } else {
 579                 rxvlan_cfg.strip_tag1_en = enable;
 580                 rxvlan_cfg.strip_tag2_en = true;
 581                 rxvlan_cfg.strip_tag2_discard_en = true;
 582         }
 583
 584         rxvlan_cfg.strip_tag1_discard_en = false;
 585         rxvlan_cfg.vlan1_vlan_prionly = false;
 586         rxvlan_cfg.vlan2_vlan_prionly = false;
 587         rxvlan_cfg.rx_vlan_offload_en = enable;
 588
 589         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 590         if (ret) {
 591                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 592                 return ret;
 593         }
 594
 595         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 602                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 603 {
 604         struct hns3_vlan_filter_ctrl_cmd *req;
 605         struct hns3_cmd_desc desc;
 606         int ret;
 607
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 609
 610         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 611         req->vlan_type = vlan_type;
 612         req->vlan_fe = filter_en ? fe_type : 0;
 613         req->vf_id = vf_id;
 614
 615         ret = hns3_cmd_send(hw, &desc, 1);
 616         if (ret)
 617                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3_vlan_filter_init(struct hns3_adapter *hns)
 624 {
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 629                                         HNS3_FILTER_FE_EGRESS, false,
 630                                         HNS3_PF_FUNC_ID);
 631         if (ret) {
 632                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 633                 return ret;
 634         }
 635
 636         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 637                                         HNS3_FILTER_FE_INGRESS, false,
 638                                         HNS3_PF_FUNC_ID);
 639         if (ret)
 640                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 647 {
 648         struct hns3_hw *hw = &hns->hw;
 649         int ret;
 650
 651         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 652                                         HNS3_FILTER_FE_INGRESS, enable,
 653                                         HNS3_PF_FUNC_ID);
 654         if (ret)
 655                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 656                          enable ? "enable" : "disable", ret);
 657
 658         return ret;
 659 }
 660
 661 static int
 662 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 663 {
 664         struct hns3_adapter *hns = dev->data->dev_private;
 665         struct hns3_hw *hw = &hns->hw;
 666         struct rte_eth_rxmode *rxmode;
 667         unsigned int tmp_mask;
 668         bool enable;
 669         int ret = 0;
 670
 671         rte_spinlock_lock(&hw->lock);
 672         rxmode = &dev->data->dev_conf.rxmode;
 673         tmp_mask = (unsigned int)mask;
 674         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 675                 /* ignore vlan filter configuration during promiscuous mode */
 676                 if (!dev->data->promiscuous) {
 677                         /* Enable or disable VLAN filter */
 678                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 679                                  true : false;
 680
 681                         ret = hns3_enable_vlan_filter(hns, enable);
 682                         if (ret) {
 683                                 rte_spinlock_unlock(&hw->lock);
 684                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 685                                          enable ? "enable" : "disable", ret);
 686                                 return ret;
 687                         }
 688                 }
 689         }
 690
 691         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 692                 /* Enable or disable VLAN stripping */
 693                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 694                     true : false;
 695
 696                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 697                 if (ret) {
 698                         rte_spinlock_unlock(&hw->lock);
 699                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 700                                  enable ? "enable" : "disable", ret);
 701                         return ret;
 702                 }
 703         }
 704
 705         rte_spinlock_unlock(&hw->lock);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 712                              struct hns3_tx_vtag_cfg *vcfg)
 713 {
 714         struct hns3_vport_vtag_tx_cfg_cmd *req;
 715         struct hns3_cmd_desc desc;
 716         struct hns3_hw *hw = &hns->hw;
 717         uint16_t vport_id;
 718         uint8_t bitmap;
 719         int ret;
 720
 721         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 722
 723         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 724         req->def_vlan_tag1 = vcfg->default_tag1;
 725         req->def_vlan_tag2 = vcfg->default_tag2;
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 727                      vcfg->accept_tag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 729                      vcfg->accept_untag1 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 731                      vcfg->accept_tag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 733                      vcfg->accept_untag2 ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 735                      vcfg->insert_tag1_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 737                      vcfg->insert_tag2_en ? 1 : 0);
 738         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 739
 740         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 741         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 742                      vcfg->tag_shift_mode_en ? 1 : 0);
 743
 744         /*
 745          * In current version VF is not supported when PF is driven by DPDK
 746          * driver, just need to configure parameters for PF vport.
 747          */
 748         vport_id = HNS3_PF_FUNC_ID;
 749         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 750         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 751         req->vf_bitmap[req->vf_offset] = bitmap;
 752
 753         ret = hns3_cmd_send(hw, &desc, 1);
 754         if (ret)
 755                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 756
 757         return ret;
 758 }
 759
 760 static int
 761 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 762                      uint16_t pvid)
 763 {
 764         struct hns3_hw *hw = &hns->hw;
 765         struct hns3_tx_vtag_cfg txvlan_cfg;
 766         int ret;
 767
 768         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 769                 txvlan_cfg.accept_tag1 = true;
 770                 txvlan_cfg.insert_tag1_en = false;
 771                 txvlan_cfg.default_tag1 = 0;
 772         } else {
 773                 txvlan_cfg.accept_tag1 =
 774                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 775                 txvlan_cfg.insert_tag1_en = true;
 776                 txvlan_cfg.default_tag1 = pvid;
 777         }
 778
 779         txvlan_cfg.accept_untag1 = true;
 780         txvlan_cfg.accept_tag2 = true;
 781         txvlan_cfg.accept_untag2 = true;
 782         txvlan_cfg.insert_tag2_en = false;
 783         txvlan_cfg.default_tag2 = 0;
 784         txvlan_cfg.tag_shift_mode_en = true;
 785
 786         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 787         if (ret) {
 788                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 789                          ret);
 790                 return ret;
 791         }
 792
 793         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 794         return ret;
 795 }
 796
 797
 798 static void
 799 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 800 {
 801         struct hns3_user_vlan_table *vlan_entry;
 802         struct hns3_pf *pf = &hns->pf;
 803
 804         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 805                 if (vlan_entry->hd_tbl_status) {
 806                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 807                         vlan_entry->hd_tbl_status = false;
 808                 }
 809         }
 810
 811         if (is_del_list) {
 812                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 813                 while (vlan_entry) {
 814                         LIST_REMOVE(vlan_entry, next);
 815                         rte_free(vlan_entry);
 816                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 817                 }
 818         }
 819 }
 820
 821 static void
 822 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 823 {
 824         struct hns3_user_vlan_table *vlan_entry;
 825         struct hns3_pf *pf = &hns->pf;
 826
 827         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 828                 if (!vlan_entry->hd_tbl_status) {
 829                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 830                         vlan_entry->hd_tbl_status = true;
 831                 }
 832         }
 833 }
 834
 835 static void
 836 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 837 {
 838         struct hns3_hw *hw = &hns->hw;
 839         int ret;
 840
 841         hns3_rm_all_vlan_table(hns, true);
 842         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 843                 ret = hns3_set_port_vlan_filter(hns,
 844                                                 hw->port_base_vlan_cfg.pvid, 0);
 845                 if (ret) {
 846                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 847                                  ret);
 848                         return;
 849                 }
 850         }
 851 }
 852
 853 static int
 854 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 855                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 856 {
 857         struct hns3_hw *hw = &hns->hw;
 858         uint16_t old_pvid;
 859         int ret;
 860
 861         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 862                 old_pvid = hw->port_base_vlan_cfg.pvid;
 863                 if (old_pvid != HNS3_INVALID_PVID) {
 864                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 865                         if (ret) {
 866                                 hns3_err(hw, "failed to remove old pvid %u, "
 867                                                 "ret = %d", old_pvid, ret);
 868                                 return ret;
 869                         }
 870                 }
 871
 872                 hns3_rm_all_vlan_table(hns, false);
 873                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 874                 if (ret) {
 875                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 876                                         new_pvid, ret);
 877                         return ret;
 878                 }
 879         } else {
 880                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 881                 if (ret) {
 882                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 883                                         new_pvid, ret);
 884                         return ret;
 885                 }
 886
 887                 hns3_add_all_vlan_table(hns);
 888         }
 889         return 0;
 890 }
 891
 892 static int
 893 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 894 {
 895         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 896         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 897         bool rx_strip_en;
 898         int ret;
 899
 900         rx_strip_en = old_cfg->rx_vlan_offload_en;
 901         if (on) {
 902                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 903                 rx_vlan_cfg.strip_tag2_en = true;
 904                 rx_vlan_cfg.strip_tag2_discard_en = true;
 905         } else {
 906                 rx_vlan_cfg.strip_tag1_en = false;
 907                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 908                 rx_vlan_cfg.strip_tag2_discard_en = false;
 909         }
 910         rx_vlan_cfg.strip_tag1_discard_en = false;
 911         rx_vlan_cfg.vlan1_vlan_prionly = false;
 912         rx_vlan_cfg.vlan2_vlan_prionly = false;
 913         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 914
 915         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 916         if (ret)
 917                 return ret;
 918
 919         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 920         return ret;
 921 }
 922
 923 static int
 924 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 925 {
 926         struct hns3_hw *hw = &hns->hw;
 927         uint16_t port_base_vlan_state;
 928         int ret;
 929
 930         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 931                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 932                         hns3_warn(hw, "Invalid operation! As current pvid set "
 933                                   "is %u, disable pvid %u is invalid",
 934                                   hw->port_base_vlan_cfg.pvid, pvid);
 935                 return 0;
 936         }
 937
 938         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 939                                     HNS3_PORT_BASE_VLAN_DISABLE;
 940         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 941         if (ret) {
 942                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 943                          ret);
 944                 return ret;
 945         }
 946
 947         ret = hns3_en_pvid_strip(hns, on);
 948         if (ret) {
 949                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 950                          "ret = %d", ret);
 951                 return ret;
 952         }
 953
 954         if (pvid == HNS3_INVALID_PVID)
 955                 goto out;
 956         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 957         if (ret) {
 958                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 959                          ret);
 960                 return ret;
 961         }
 962
 963 out:
 964         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 965         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 966         return ret;
 967 }
 968
 969 static int
 970 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 971 {
 972         struct hns3_adapter *hns = dev->data->dev_private;
 973         struct hns3_hw *hw = &hns->hw;
 974         bool pvid_en_state_change;
 975         uint16_t pvid_state;
 976         int ret;
 977
 978         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 979                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 980                          RTE_ETHER_MAX_VLAN_ID);
 981                 return -EINVAL;
 982         }
 983
 984         /*
 985          * If PVID configuration state change, should refresh the PVID
 986          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 987          */
 988         pvid_state = hw->port_base_vlan_cfg.state;
 989         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 990             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 991                 pvid_en_state_change = false;
 992         else
 993                 pvid_en_state_change = true;
 994
 995         rte_spinlock_lock(&hw->lock);
 996         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 997         rte_spinlock_unlock(&hw->lock);
 998         if (ret)
 999                 return ret;
1000         /*
1001          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1002          * need be processed by PMD driver.
1003          */
1004         if (pvid_en_state_change &&
1005             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1006                 hns3_update_all_queues_pvid_proc_en(hw);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 hns3_default_vlan_config(struct hns3_adapter *hns)
1013 {
1014         struct hns3_hw *hw = &hns->hw;
1015         int ret;
1016
1017         /*
1018          * When vlan filter is enabled, hardware regards packets without vlan
1019          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1020          * table, packets without vlan won't be received. So, add vlan 0 as
1021          * the default vlan.
1022          */
1023         ret = hns3_vlan_filter_configure(hns, 0, 1);
1024         if (ret)
1025                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1026         return ret;
1027 }
1028
1029 static int
1030 hns3_init_vlan_config(struct hns3_adapter *hns)
1031 {
1032         struct hns3_hw *hw = &hns->hw;
1033         int ret;
1034
1035         /*
1036          * This function can be called in the initialization and reset process,
1037          * when in reset process, it means that hardware had been reseted
1038          * successfully and we need to restore the hardware configuration to
1039          * ensure that the hardware configuration remains unchanged before and
1040          * after reset.
1041          */
1042         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1043                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1044                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1045         }
1046
1047         ret = hns3_vlan_filter_init(hns);
1048         if (ret) {
1049                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1050                 return ret;
1051         }
1052
1053         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1054                                        RTE_ETHER_TYPE_VLAN);
1055         if (ret) {
1056                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1057                 return ret;
1058         }
1059
1060         /*
1061          * When in the reinit dev stage of the reset process, the following
1062          * vlan-related configurations may differ from those at initialization,
1063          * we will restore configurations to hardware in hns3_restore_vlan_table
1064          * and hns3_restore_vlan_conf later.
1065          */
1066         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1067                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1068                 if (ret) {
1069                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1070                         return ret;
1071                 }
1072
1073                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1074                 if (ret) {
1075                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1076                                  ret);
1077                         return ret;
1078                 }
1079         }
1080
1081         return hns3_default_vlan_config(hns);
1082 }
1083
1084 static int
1085 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1086 {
1087         struct hns3_pf *pf = &hns->pf;
1088         struct hns3_hw *hw = &hns->hw;
1089         uint64_t offloads;
1090         bool enable;
1091         int ret;
1092
1093         if (!hw->data->promiscuous) {
1094                 /* restore vlan filter states */
1095                 offloads = hw->data->dev_conf.rxmode.offloads;
1096                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1097                 ret = hns3_enable_vlan_filter(hns, enable);
1098                 if (ret) {
1099                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1100                                  "ret = %d", ret);
1101                         return ret;
1102                 }
1103         }
1104
1105         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1106         if (ret) {
1107                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1108                 return ret;
1109         }
1110
1111         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1112         if (ret)
1113                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1114
1115         return ret;
1116 }
1117
1118 static int
1119 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1120 {
1121         struct hns3_adapter *hns = dev->data->dev_private;
1122         struct rte_eth_dev_data *data = dev->data;
1123         struct rte_eth_txmode *txmode;
1124         struct hns3_hw *hw = &hns->hw;
1125         int mask;
1126         int ret;
1127
1128         txmode = &data->dev_conf.txmode;
1129         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1130                 hns3_warn(hw,
1131                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1132                           "configuration is not supported! Ignore these two "
1133                           "parameters: hw_vlan_reject_tagged(%u), "
1134                           "hw_vlan_reject_untagged(%u)",
1135                           txmode->hw_vlan_reject_tagged,
1136                           txmode->hw_vlan_reject_untagged);
1137
1138         /* Apply vlan offload setting */
1139         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1140         ret = hns3_vlan_offload_set(dev, mask);
1141         if (ret) {
1142                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1143                          ret);
1144                 return ret;
1145         }
1146
1147         /*
1148          * If pvid config is not set in rte_eth_conf, driver needn't to set
1149          * VLAN pvid related configuration to hardware.
1150          */
1151         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1152                 return 0;
1153
1154         /* Apply pvid setting */
1155         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1156                                  txmode->hw_vlan_insert_pvid);
1157         if (ret)
1158                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1159                          txmode->pvid, ret);
1160
1161         return ret;
1162 }
1163
1164 static int
1165 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1166                 unsigned int tso_mss_max)
1167 {
1168         struct hns3_cfg_tso_status_cmd *req;
1169         struct hns3_cmd_desc desc;
1170         uint16_t tso_mss;
1171
1172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1173
1174         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1175
1176         tso_mss = 0;
1177         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1178                        tso_mss_min);
1179         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1180
1181         tso_mss = 0;
1182         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1183                        tso_mss_max);
1184         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1185
1186         return hns3_cmd_send(hw, &desc, 1);
1187 }
1188
1189 static int
1190 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1191                    uint16_t *allocated_size, bool is_alloc)
1192 {
1193         struct hns3_umv_spc_alc_cmd *req;
1194         struct hns3_cmd_desc desc;
1195         int ret;
1196
1197         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1198         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1199         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1200         req->space_size = rte_cpu_to_le_32(space_size);
1201
1202         ret = hns3_cmd_send(hw, &desc, 1);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1205                              is_alloc ? "allocate" : "free", ret);
1206                 return ret;
1207         }
1208
1209         if (is_alloc && allocated_size)
1210                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1211
1212         return 0;
1213 }
1214
1215 static int
1216 hns3_init_umv_space(struct hns3_hw *hw)
1217 {
1218         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219         struct hns3_pf *pf = &hns->pf;
1220         uint16_t allocated_size = 0;
1221         int ret;
1222
1223         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1224                                  true);
1225         if (ret)
1226                 return ret;
1227
1228         if (allocated_size < pf->wanted_umv_size)
1229                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1230                              pf->wanted_umv_size, allocated_size);
1231
1232         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1233                                                 pf->wanted_umv_size;
1234         pf->used_umv_size = 0;
1235         return 0;
1236 }
1237
1238 static int
1239 hns3_uninit_umv_space(struct hns3_hw *hw)
1240 {
1241         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242         struct hns3_pf *pf = &hns->pf;
1243         int ret;
1244
1245         if (pf->max_umv_size == 0)
1246                 return 0;
1247
1248         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1249         if (ret)
1250                 return ret;
1251
1252         pf->max_umv_size = 0;
1253
1254         return 0;
1255 }
1256
1257 static bool
1258 hns3_is_umv_space_full(struct hns3_hw *hw)
1259 {
1260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1261         struct hns3_pf *pf = &hns->pf;
1262         bool is_full;
1263
1264         is_full = (pf->used_umv_size >= pf->max_umv_size);
1265
1266         return is_full;
1267 }
1268
1269 static void
1270 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1271 {
1272         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1273         struct hns3_pf *pf = &hns->pf;
1274
1275         if (is_free) {
1276                 if (pf->used_umv_size > 0)
1277                         pf->used_umv_size--;
1278         } else
1279                 pf->used_umv_size++;
1280 }
1281
1282 static void
1283 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1284                       const uint8_t *addr, bool is_mc)
1285 {
1286         const unsigned char *mac_addr = addr;
1287         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1288                             ((uint32_t)mac_addr[2] << 16) |
1289                             ((uint32_t)mac_addr[1] << 8) |
1290                             (uint32_t)mac_addr[0];
1291         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1292
1293         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1294         if (is_mc) {
1295                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1296                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1297                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1298         }
1299
1300         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1301         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1302 }
1303
1304 static int
1305 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1306                              uint8_t resp_code,
1307                              enum hns3_mac_vlan_tbl_opcode op)
1308 {
1309         if (cmdq_resp) {
1310                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1311                          cmdq_resp);
1312                 return -EIO;
1313         }
1314
1315         if (op == HNS3_MAC_VLAN_ADD) {
1316                 if (resp_code == 0 || resp_code == 1) {
1317                         return 0;
1318                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1319                         hns3_err(hw, "add mac addr failed for uc_overflow");
1320                         return -ENOSPC;
1321                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1322                         hns3_err(hw, "add mac addr failed for mc_overflow");
1323                         return -ENOSPC;
1324                 }
1325
1326                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1327                          resp_code);
1328                 return -EIO;
1329         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1330                 if (resp_code == 0) {
1331                         return 0;
1332                 } else if (resp_code == 1) {
1333                         hns3_dbg(hw, "remove mac addr failed for miss");
1334                         return -ENOENT;
1335                 }
1336
1337                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1338                          resp_code);
1339                 return -EIO;
1340         } else if (op == HNS3_MAC_VLAN_LKUP) {
1341                 if (resp_code == 0) {
1342                         return 0;
1343                 } else if (resp_code == 1) {
1344                         hns3_dbg(hw, "lookup mac addr failed for miss");
1345                         return -ENOENT;
1346                 }
1347
1348                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1349                          resp_code);
1350                 return -EIO;
1351         }
1352
1353         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1354                  op);
1355
1356         return -EINVAL;
1357 }
1358
1359 static int
1360 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1361                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1362                          struct hns3_cmd_desc *desc, bool is_mc)
1363 {
1364         uint8_t resp_code;
1365         uint16_t retval;
1366         int ret;
1367
1368         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1369         if (is_mc) {
1370                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 memcpy(desc[0].data, req,
1372                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1373                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1374                                           true);
1375                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1376                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1377                                           true);
1378                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379         } else {
1380                 memcpy(desc[0].data, req,
1381                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1382                 ret = hns3_cmd_send(hw, desc, 1);
1383         }
1384         if (ret) {
1385                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1386                          ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc[0].retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_LKUP);
1394 }
1395
1396 static int
1397 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1398                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1399                       struct hns3_cmd_desc *mc_desc)
1400 {
1401         uint8_t resp_code;
1402         uint16_t retval;
1403         int cfg_status;
1404         int ret;
1405
1406         if (mc_desc == NULL) {
1407                 struct hns3_cmd_desc desc;
1408
1409                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1410                 memcpy(desc.data, req,
1411                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 ret = hns3_cmd_send(hw, &desc, 1);
1413                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1414                 retval = rte_le_to_cpu_16(desc.retval);
1415
1416                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1417                                                           HNS3_MAC_VLAN_ADD);
1418         } else {
1419                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1420                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1422                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1423                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1424                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1425                 memcpy(mc_desc[0].data, req,
1426                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1427                 mc_desc[0].retval = 0;
1428                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1429                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1430                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1431
1432                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1433                                                           HNS3_MAC_VLAN_ADD);
1434         }
1435
1436         if (ret) {
1437                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1438                 return ret;
1439         }
1440
1441         return cfg_status;
1442 }
1443
1444 static int
1445 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1446                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1447 {
1448         struct hns3_cmd_desc desc;
1449         uint8_t resp_code;
1450         uint16_t retval;
1451         int ret;
1452
1453         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1454
1455         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1456
1457         ret = hns3_cmd_send(hw, &desc, 1);
1458         if (ret) {
1459                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1460                 return ret;
1461         }
1462         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1463         retval = rte_le_to_cpu_16(desc.retval);
1464
1465         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1466                                             HNS3_MAC_VLAN_REMOVE);
1467 }
1468
1469 static int
1470 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1471 {
1472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1473         struct hns3_mac_vlan_tbl_entry_cmd req;
1474         struct hns3_pf *pf = &hns->pf;
1475         struct hns3_cmd_desc desc[3];
1476         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1477         uint16_t egress_port = 0;
1478         uint8_t vf_id;
1479         int ret;
1480
1481         /* check if mac addr is valid */
1482         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1483                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1484                                       mac_addr);
1485                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1486                          mac_str);
1487                 return -EINVAL;
1488         }
1489
1490         memset(&req, 0, sizeof(req));
1491
1492         /*
1493          * In current version VF is not supported when PF is driven by DPDK
1494          * driver, just need to configure parameters for PF vport.
1495          */
1496         vf_id = HNS3_PF_FUNC_ID;
1497         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1498                        HNS3_MAC_EPORT_VFID_S, vf_id);
1499
1500         req.egress_port = rte_cpu_to_le_16(egress_port);
1501
1502         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1503
1504         /*
1505          * Lookup the mac address in the mac_vlan table, and add
1506          * it if the entry is inexistent. Repeated unicast entry
1507          * is not allowed in the mac vlan table.
1508          */
1509         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1510         if (ret == -ENOENT) {
1511                 if (!hns3_is_umv_space_full(hw)) {
1512                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1513                         if (!ret)
1514                                 hns3_update_umv_space(hw, false);
1515                         return ret;
1516                 }
1517
1518                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1519
1520                 return -ENOSPC;
1521         }
1522
1523         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1524
1525         /* check if we just hit the duplicate */
1526         if (ret == 0) {
1527                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1528                 return 0;
1529         }
1530
1531         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1532                  mac_str);
1533
1534         return ret;
1535 }
1536
1537 static int
1538 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541         struct rte_ether_addr *addr;
1542         int ret;
1543         int i;
1544
1545         for (i = 0; i < hw->mc_addrs_num; i++) {
1546                 addr = &hw->mc_addrs[i];
1547                 /* Check if there are duplicate addresses */
1548                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1549                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                               addr);
1551                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1552                                  "(%s) is added by the set_mc_mac_addr_list "
1553                                  "API", mac_str);
1554                         return -EINVAL;
1555                 }
1556         }
1557
1558         ret = hns3_add_mc_addr(hw, mac_addr);
1559         if (ret) {
1560                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1563                          mac_str, ret);
1564         }
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         int ret;
1573
1574         ret = hns3_remove_mc_addr(hw, mac_addr);
1575         if (ret) {
1576                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1577                                       mac_addr);
1578                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1579                          mac_str, ret);
1580         }
1581         return ret;
1582 }
1583
1584 static int
1585 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1586                   uint32_t idx, __rte_unused uint32_t pool)
1587 {
1588         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590         int ret;
1591
1592         rte_spinlock_lock(&hw->lock);
1593
1594         /*
1595          * In hns3 network engine adding UC and MC mac address with different
1596          * commands with firmware. We need to determine whether the input
1597          * address is a UC or a MC address to call different commands.
1598          * By the way, it is recommended calling the API function named
1599          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1600          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1601          * may affect the specifications of UC mac addresses.
1602          */
1603         if (rte_is_multicast_ether_addr(mac_addr))
1604                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1605         else
1606                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1607
1608         if (ret) {
1609                 rte_spinlock_unlock(&hw->lock);
1610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                       mac_addr);
1612                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1613                          ret);
1614                 return ret;
1615         }
1616
1617         if (idx == 0)
1618                 hw->mac.default_addr_setted = true;
1619         rte_spinlock_unlock(&hw->lock);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         struct hns3_mac_vlan_tbl_entry_cmd req;
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         int ret;
1630
1631         /* check if mac addr is valid */
1632         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1633                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634                                       mac_addr);
1635                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1636                          mac_str);
1637                 return -EINVAL;
1638         }
1639
1640         memset(&req, 0, sizeof(req));
1641         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1643         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1644         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1645                 return 0;
1646         else if (ret == 0)
1647                 hns3_update_umv_space(hw, true);
1648
1649         return ret;
1650 }
1651
1652 static void
1653 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1654 {
1655         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         /* index will be checked by upper level rte interface */
1657         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         if (rte_is_multicast_ether_addr(mac_addr))
1664                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1665         else
1666                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1667         rte_spinlock_unlock(&hw->lock);
1668         if (ret) {
1669                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670                                       mac_addr);
1671                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1672                          ret);
1673         }
1674 }
1675
1676 static int
1677 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1678                           struct rte_ether_addr *mac_addr)
1679 {
1680         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_ether_addr *oaddr;
1682         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683         bool default_addr_setted;
1684         bool rm_succes = false;
1685         int ret, ret_val;
1686
1687         /*
1688          * It has been guaranteed that input parameter named mac_addr is valid
1689          * address in the rte layer of DPDK framework.
1690          */
1691         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1692         default_addr_setted = hw->mac.default_addr_setted;
1693         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1694                 return 0;
1695
1696         rte_spinlock_lock(&hw->lock);
1697         if (default_addr_setted) {
1698                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1699                 if (ret) {
1700                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701                                               oaddr);
1702                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1703                                   mac_str, ret);
1704                         rm_succes = false;
1705                 } else
1706                         rm_succes = true;
1707         }
1708
1709         ret = hns3_add_uc_addr_common(hw, mac_addr);
1710         if (ret) {
1711                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1714                 goto err_add_uc_addr;
1715         }
1716
1717         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1718         if (ret) {
1719                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1720                 goto err_pause_addr_cfg;
1721         }
1722
1723         rte_ether_addr_copy(mac_addr,
1724                             (struct rte_ether_addr *)hw->mac.mac_addr);
1725         hw->mac.default_addr_setted = true;
1726         rte_spinlock_unlock(&hw->lock);
1727
1728         return 0;
1729
1730 err_pause_addr_cfg:
1731         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1732         if (ret_val) {
1733                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734                                       mac_addr);
1735                 hns3_warn(hw,
1736                           "Failed to roll back to del setted mac addr(%s): %d",
1737                           mac_str, ret_val);
1738         }
1739
1740 err_add_uc_addr:
1741         if (rm_succes) {
1742                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1743                 if (ret_val) {
1744                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745                                               oaddr);
1746                         hns3_warn(hw,
1747                                   "Failed to restore old uc mac addr(%s): %d",
1748                                   mac_str, ret_val);
1749                         hw->mac.default_addr_setted = false;
1750                 }
1751         }
1752         rte_spinlock_unlock(&hw->lock);
1753
1754         return ret;
1755 }
1756
1757 static int
1758 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1759 {
1760         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1761         struct hns3_hw *hw = &hns->hw;
1762         struct rte_ether_addr *addr;
1763         int err = 0;
1764         int ret;
1765         int i;
1766
1767         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1768                 addr = &hw->data->mac_addrs[i];
1769                 if (rte_is_zero_ether_addr(addr))
1770                         continue;
1771                 if (rte_is_multicast_ether_addr(addr))
1772                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1773                               hns3_add_mc_addr(hw, addr);
1774                 else
1775                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1776                               hns3_add_uc_addr_common(hw, addr);
1777
1778                 if (ret) {
1779                         err = ret;
1780                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                               addr);
1782                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1783                                  "ret = %d.", del ? "remove" : "restore",
1784                                  mac_str, i, ret);
1785                 }
1786         }
1787         return err;
1788 }
1789
1790 static void
1791 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1792 {
1793 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1794         uint8_t word_num;
1795         uint8_t bit_num;
1796
1797         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1798                 word_num = vfid / 32;
1799                 bit_num = vfid % 32;
1800                 if (clr)
1801                         desc[1].data[word_num] &=
1802                             rte_cpu_to_le_32(~(1UL << bit_num));
1803                 else
1804                         desc[1].data[word_num] |=
1805                             rte_cpu_to_le_32(1UL << bit_num);
1806         } else {
1807                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1808                 bit_num = vfid % 32;
1809                 if (clr)
1810                         desc[2].data[word_num] &=
1811                             rte_cpu_to_le_32(~(1UL << bit_num));
1812                 else
1813                         desc[2].data[word_num] |=
1814                             rte_cpu_to_le_32(1UL << bit_num);
1815         }
1816 }
1817
1818 static int
1819 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1820 {
1821         struct hns3_mac_vlan_tbl_entry_cmd req;
1822         struct hns3_cmd_desc desc[3];
1823         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824         uint8_t vf_id;
1825         int ret;
1826
1827         /* Check if mac addr is valid */
1828         if (!rte_is_multicast_ether_addr(mac_addr)) {
1829                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                       mac_addr);
1831                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1832                          mac_str);
1833                 return -EINVAL;
1834         }
1835
1836         memset(&req, 0, sizeof(req));
1837         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1838         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1839         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1840         if (ret) {
1841                 /* This mac addr do not exist, add new entry for it */
1842                 memset(desc[0].data, 0, sizeof(desc[0].data));
1843                 memset(desc[1].data, 0, sizeof(desc[0].data));
1844                 memset(desc[2].data, 0, sizeof(desc[0].data));
1845         }
1846
1847         /*
1848          * In current version VF is not supported when PF is driven by DPDK
1849          * driver, just need to configure parameters for PF vport.
1850          */
1851         vf_id = HNS3_PF_FUNC_ID;
1852         hns3_update_desc_vfid(desc, vf_id, false);
1853         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1854         if (ret) {
1855                 if (ret == -ENOSPC)
1856                         hns3_err(hw, "mc mac vlan table is full");
1857                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1858                                       mac_addr);
1859                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1860         }
1861
1862         return ret;
1863 }
1864
1865 static int
1866 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1867 {
1868         struct hns3_mac_vlan_tbl_entry_cmd req;
1869         struct hns3_cmd_desc desc[3];
1870         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1871         uint8_t vf_id;
1872         int ret;
1873
1874         /* Check if mac addr is valid */
1875         if (!rte_is_multicast_ether_addr(mac_addr)) {
1876                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1877                                       mac_addr);
1878                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1879                          mac_str);
1880                 return -EINVAL;
1881         }
1882
1883         memset(&req, 0, sizeof(req));
1884         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1885         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1886         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1887         if (ret == 0) {
1888                 /*
1889                  * This mac addr exist, remove this handle's VFID for it.
1890                  * In current version VF is not supported when PF is driven by
1891                  * DPDK driver, just need to configure parameters for PF vport.
1892                  */
1893                 vf_id = HNS3_PF_FUNC_ID;
1894                 hns3_update_desc_vfid(desc, vf_id, true);
1895
1896                 /* All the vfid is zero, so need to delete this entry */
1897                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1898         } else if (ret == -ENOENT) {
1899                 /* This mac addr doesn't exist. */
1900                 return 0;
1901         }
1902
1903         if (ret) {
1904                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1905                                       mac_addr);
1906                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1907         }
1908
1909         return ret;
1910 }
1911
1912 static int
1913 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1914                            struct rte_ether_addr *mc_addr_set,
1915                            uint32_t nb_mc_addr)
1916 {
1917         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1918         struct rte_ether_addr *addr;
1919         uint32_t i;
1920         uint32_t j;
1921
1922         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1923                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1924                          "invalid. valid range: 0~%d",
1925                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1926                 return -EINVAL;
1927         }
1928
1929         /* Check if input mac addresses are valid */
1930         for (i = 0; i < nb_mc_addr; i++) {
1931                 addr = &mc_addr_set[i];
1932                 if (!rte_is_multicast_ether_addr(addr)) {
1933                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934                                               addr);
1935                         hns3_err(hw,
1936                                  "failed to set mc mac addr, addr(%s) invalid.",
1937                                  mac_str);
1938                         return -EINVAL;
1939                 }
1940
1941                 /* Check if there are duplicate addresses */
1942                 for (j = i + 1; j < nb_mc_addr; j++) {
1943                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944                                 hns3_ether_format_addr(mac_str,
1945                                                       RTE_ETHER_ADDR_FMT_SIZE,
1946                                                       addr);
1947                                 hns3_err(hw, "failed to set mc mac addr, "
1948                                          "addrs invalid. two same addrs(%s).",
1949                                          mac_str);
1950                                 return -EINVAL;
1951                         }
1952                 }
1953
1954                 /*
1955                  * Check if there are duplicate addresses between mac_addrs
1956                  * and mc_addr_set
1957                  */
1958                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1959                         if (rte_is_same_ether_addr(addr,
1960                                                    &hw->data->mac_addrs[j])) {
1961                                 hns3_ether_format_addr(mac_str,
1962                                                       RTE_ETHER_ADDR_FMT_SIZE,
1963                                                       addr);
1964                                 hns3_err(hw, "failed to set mc mac addr, "
1965                                          "addrs invalid. addrs(%s) has already "
1966                                          "configured in mac_addr add API",
1967                                          mac_str);
1968                                 return -EINVAL;
1969                         }
1970                 }
1971         }
1972
1973         return 0;
1974 }
1975
1976 static void
1977 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1978                            struct rte_ether_addr *mc_addr_set,
1979                            int mc_addr_num,
1980                            struct rte_ether_addr *reserved_addr_list,
1981                            int *reserved_addr_num,
1982                            struct rte_ether_addr *add_addr_list,
1983                            int *add_addr_num,
1984                            struct rte_ether_addr *rm_addr_list,
1985                            int *rm_addr_num)
1986 {
1987         struct rte_ether_addr *addr;
1988         int current_addr_num;
1989         int reserved_num = 0;
1990         int add_num = 0;
1991         int rm_num = 0;
1992         int num;
1993         int i;
1994         int j;
1995         bool same_addr;
1996
1997         /* Calculate the mc mac address list that should be removed */
1998         current_addr_num = hw->mc_addrs_num;
1999         for (i = 0; i < current_addr_num; i++) {
2000                 addr = &hw->mc_addrs[i];
2001                 same_addr = false;
2002                 for (j = 0; j < mc_addr_num; j++) {
2003                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2004                                 same_addr = true;
2005                                 break;
2006                         }
2007                 }
2008
2009                 if (!same_addr) {
2010                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2011                         rm_num++;
2012                 } else {
2013                         rte_ether_addr_copy(addr,
2014                                             &reserved_addr_list[reserved_num]);
2015                         reserved_num++;
2016                 }
2017         }
2018
2019         /* Calculate the mc mac address list that should be added */
2020         for (i = 0; i < mc_addr_num; i++) {
2021                 addr = &mc_addr_set[i];
2022                 same_addr = false;
2023                 for (j = 0; j < current_addr_num; j++) {
2024                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2025                                 same_addr = true;
2026                                 break;
2027                         }
2028                 }
2029
2030                 if (!same_addr) {
2031                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2032                         add_num++;
2033                 }
2034         }
2035
2036         /* Reorder the mc mac address list maintained by driver */
2037         for (i = 0; i < reserved_num; i++)
2038                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2039
2040         for (i = 0; i < rm_num; i++) {
2041                 num = reserved_num + i;
2042                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2043         }
2044
2045         *reserved_addr_num = reserved_num;
2046         *add_addr_num = add_num;
2047         *rm_addr_num = rm_num;
2048 }
2049
2050 static int
2051 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2052                           struct rte_ether_addr *mc_addr_set,
2053                           uint32_t nb_mc_addr)
2054 {
2055         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2058         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2059         struct rte_ether_addr *addr;
2060         int reserved_addr_num;
2061         int add_addr_num;
2062         int rm_addr_num;
2063         int mc_addr_num;
2064         int num;
2065         int ret;
2066         int i;
2067
2068         /* Check if input parameters are valid */
2069         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2070         if (ret)
2071                 return ret;
2072
2073         rte_spinlock_lock(&hw->lock);
2074
2075         /*
2076          * Calculate the mc mac address lists those should be removed and be
2077          * added, Reorder the mc mac address list maintained by driver.
2078          */
2079         mc_addr_num = (int)nb_mc_addr;
2080         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2081                                    reserved_addr_list, &reserved_addr_num,
2082                                    add_addr_list, &add_addr_num,
2083                                    rm_addr_list, &rm_addr_num);
2084
2085         /* Remove mc mac addresses */
2086         for (i = 0; i < rm_addr_num; i++) {
2087                 num = rm_addr_num - i - 1;
2088                 addr = &rm_addr_list[num];
2089                 ret = hns3_remove_mc_addr(hw, addr);
2090                 if (ret) {
2091                         rte_spinlock_unlock(&hw->lock);
2092                         return ret;
2093                 }
2094                 hw->mc_addrs_num--;
2095         }
2096
2097         /* Add mc mac addresses */
2098         for (i = 0; i < add_addr_num; i++) {
2099                 addr = &add_addr_list[i];
2100                 ret = hns3_add_mc_addr(hw, addr);
2101                 if (ret) {
2102                         rte_spinlock_unlock(&hw->lock);
2103                         return ret;
2104                 }
2105
2106                 num = reserved_addr_num + i;
2107                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2108                 hw->mc_addrs_num++;
2109         }
2110         rte_spinlock_unlock(&hw->lock);
2111
2112         return 0;
2113 }
2114
2115 static int
2116 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2117 {
2118         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2119         struct hns3_hw *hw = &hns->hw;
2120         struct rte_ether_addr *addr;
2121         int err = 0;
2122         int ret;
2123         int i;
2124
2125         for (i = 0; i < hw->mc_addrs_num; i++) {
2126                 addr = &hw->mc_addrs[i];
2127                 if (!rte_is_multicast_ether_addr(addr))
2128                         continue;
2129                 if (del)
2130                         ret = hns3_remove_mc_addr(hw, addr);
2131                 else
2132                         ret = hns3_add_mc_addr(hw, addr);
2133                 if (ret) {
2134                         err = ret;
2135                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2136                                               addr);
2137                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2138                                  del ? "Remove" : "Restore", mac_str, ret);
2139                 }
2140         }
2141         return err;
2142 }
2143
2144 static int
2145 hns3_check_mq_mode(struct rte_eth_dev *dev)
2146 {
2147         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2148         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2152         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2153         uint8_t num_tc;
2154         int max_tc = 0;
2155         int i;
2156
2157         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2158         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2159
2160         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2161                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2162                          "rx_mq_mode = %d", rx_mq_mode);
2163                 return -EINVAL;
2164         }
2165
2166         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2167             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2168                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2169                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2170                          rx_mq_mode, tx_mq_mode);
2171                 return -EINVAL;
2172         }
2173
2174         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2175                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2176                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2177                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2178                         return -EINVAL;
2179                 }
2180
2181                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2182                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2183                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2184                                  "nb_tcs(%d) != %d or %d in rx direction.",
2185                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2186                         return -EINVAL;
2187                 }
2188
2189                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2190                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2191                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2192                         return -EINVAL;
2193                 }
2194
2195                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2196                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2197                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2198                                          "is not equal to one in tx direction.",
2199                                          i, dcb_rx_conf->dcb_tc[i]);
2200                                 return -EINVAL;
2201                         }
2202                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2203                                 max_tc = dcb_rx_conf->dcb_tc[i];
2204                 }
2205
2206                 num_tc = max_tc + 1;
2207                 if (num_tc > dcb_rx_conf->nb_tcs) {
2208                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2209                                  num_tc, dcb_rx_conf->nb_tcs);
2210                         return -EINVAL;
2211                 }
2212         }
2213
2214         return 0;
2215 }
2216
2217 static int
2218 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2219 {
2220         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221
2222         if (!hns3_dev_dcb_supported(hw)) {
2223                 hns3_err(hw, "this port does not support dcb configurations.");
2224                 return -EOPNOTSUPP;
2225         }
2226
2227         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2228                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2229                 return -EOPNOTSUPP;
2230         }
2231
2232         /* Check multiple queue mode */
2233         return hns3_check_mq_mode(dev);
2234 }
2235
2236 static int
2237 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2238                            enum hns3_ring_type queue_type, uint16_t queue_id)
2239 {
2240         struct hns3_cmd_desc desc;
2241         struct hns3_ctrl_vector_chain_cmd *req =
2242                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2243         enum hns3_cmd_status status;
2244         enum hns3_opcode_type op;
2245         uint16_t tqp_type_and_id = 0;
2246         uint16_t type;
2247         uint16_t gl;
2248
2249         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2250         hns3_cmd_setup_basic_desc(&desc, op, false);
2251         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2252                                               HNS3_TQP_INT_ID_L_S);
2253         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2254                                               HNS3_TQP_INT_ID_H_S);
2255
2256         if (queue_type == HNS3_RING_TYPE_RX)
2257                 gl = HNS3_RING_GL_RX;
2258         else
2259                 gl = HNS3_RING_GL_TX;
2260
2261         type = queue_type;
2262
2263         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2264                        type);
2265         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2266         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2267                        gl);
2268         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2269         req->int_cause_num = 1;
2270         status = hns3_cmd_send(hw, &desc, 1);
2271         if (status) {
2272                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2273                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2274                 return status;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3_init_ring_with_vector(struct hns3_hw *hw)
2282 {
2283         uint16_t vec;
2284         int ret;
2285         int i;
2286
2287         /*
2288          * In hns3 network engine, vector 0 is always the misc interrupt of this
2289          * function, vector 1~N can be used respectively for the queues of the
2290          * function. Tx and Rx queues with the same number share the interrupt
2291          * vector. In the initialization clearing the all hardware mapping
2292          * relationship configurations between queues and interrupt vectors is
2293          * needed, so some error caused by the residual configurations, such as
2294          * the unexpected Tx interrupt, can be avoid.
2295          */
2296         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2297         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2298                 vec = vec - 1; /* the last interrupt is reserved */
2299         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2300         for (i = 0; i < hw->intr_tqps_num; i++) {
2301                 /*
2302                  * Set gap limiter/rate limiter/quanity limiter algorithm
2303                  * configuration for interrupt coalesce of queue's interrupt.
2304                  */
2305                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2306                                        HNS3_TQP_INTR_GL_DEFAULT);
2307                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2308                                        HNS3_TQP_INTR_GL_DEFAULT);
2309                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2310                 /*
2311                  * QL(quantity limiter) is not used currently, just set 0 to
2312                  * close it.
2313                  */
2314                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2315
2316                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2317                                                  HNS3_RING_TYPE_TX, i);
2318                 if (ret) {
2319                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2320                                           "vector: %u, ret=%d", i, vec, ret);
2321                         return ret;
2322                 }
2323
2324                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2325                                                  HNS3_RING_TYPE_RX, i);
2326                 if (ret) {
2327                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2328                                           "vector: %u, ret=%d", i, vec, ret);
2329                         return ret;
2330                 }
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 hns3_dev_configure(struct rte_eth_dev *dev)
2338 {
2339         struct hns3_adapter *hns = dev->data->dev_private;
2340         struct rte_eth_conf *conf = &dev->data->dev_conf;
2341         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2342         struct hns3_hw *hw = &hns->hw;
2343         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2344         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2345         struct rte_eth_rss_conf rss_conf;
2346         uint16_t mtu;
2347         bool gro_en;
2348         int ret;
2349
2350         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2351
2352         /*
2353          * Some versions of hardware network engine does not support
2354          * individually enable/disable/reset the Tx or Rx queue. These devices
2355          * must enable/disable/reset Tx and Rx queues at the same time. When the
2356          * numbers of Tx queues allocated by upper applications are not equal to
2357          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2358          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2359          * work as usual. But these fake queues are imperceptible, and can not
2360          * be used by upper applications.
2361          */
2362         if (!hns3_dev_indep_txrx_supported(hw)) {
2363                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2364                 if (ret) {
2365                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2366                                  ret);
2367                         return ret;
2368                 }
2369         }
2370
2371         hw->adapter_state = HNS3_NIC_CONFIGURING;
2372         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2373                 hns3_err(hw, "setting link speed/duplex not supported");
2374                 ret = -EINVAL;
2375                 goto cfg_err;
2376         }
2377
2378         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2379                 ret = hns3_check_dcb_cfg(dev);
2380                 if (ret)
2381                         goto cfg_err;
2382         }
2383
2384         /* When RSS is not configured, redirect the packet queue 0 */
2385         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2386                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2387                 rss_conf = conf->rx_adv_conf.rss_conf;
2388                 hw->rss_dis_flag = false;
2389                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2390                 if (ret)
2391                         goto cfg_err;
2392         }
2393
2394         /*
2395          * If jumbo frames are enabled, MTU needs to be refreshed
2396          * according to the maximum RX packet length.
2397          */
2398         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2399                 /*
2400                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2401                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2402                  * can safely assign to "uint16_t" type variable.
2403                  */
2404                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2405                 ret = hns3_dev_mtu_set(dev, mtu);
2406                 if (ret)
2407                         goto cfg_err;
2408                 dev->data->mtu = mtu;
2409         }
2410
2411         ret = hns3_dev_configure_vlan(dev);
2412         if (ret)
2413                 goto cfg_err;
2414
2415         /* config hardware GRO */
2416         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2417         ret = hns3_config_gro(hw, gro_en);
2418         if (ret)
2419                 goto cfg_err;
2420
2421         hns->rx_simple_allowed = true;
2422         hns->rx_vec_allowed = true;
2423         hns->tx_simple_allowed = true;
2424         hns->tx_vec_allowed = true;
2425
2426         hns3_init_rx_ptype_tble(dev);
2427         hw->adapter_state = HNS3_NIC_CONFIGURED;
2428
2429         return 0;
2430
2431 cfg_err:
2432         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2433         hw->adapter_state = HNS3_NIC_INITIALIZED;
2434
2435         return ret;
2436 }
2437
2438 static int
2439 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2440 {
2441         struct hns3_config_max_frm_size_cmd *req;
2442         struct hns3_cmd_desc desc;
2443
2444         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2445
2446         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2447         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2448         req->min_frm_size = RTE_ETHER_MIN_LEN;
2449
2450         return hns3_cmd_send(hw, &desc, 1);
2451 }
2452
2453 static int
2454 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2455 {
2456         int ret;
2457
2458         ret = hns3_set_mac_mtu(hw, mps);
2459         if (ret) {
2460                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2461                 return ret;
2462         }
2463
2464         ret = hns3_buffer_alloc(hw);
2465         if (ret)
2466                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2467
2468         return ret;
2469 }
2470
2471 static int
2472 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2473 {
2474         struct hns3_adapter *hns = dev->data->dev_private;
2475         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2476         struct hns3_hw *hw = &hns->hw;
2477         bool is_jumbo_frame;
2478         int ret;
2479
2480         if (dev->data->dev_started) {
2481                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2482                          "before configuration", dev->data->port_id);
2483                 return -EBUSY;
2484         }
2485
2486         rte_spinlock_lock(&hw->lock);
2487         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2488         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2489
2490         /*
2491          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2492          * assign to "uint16_t" type variable.
2493          */
2494         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2495         if (ret) {
2496                 rte_spinlock_unlock(&hw->lock);
2497                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2498                          dev->data->port_id, mtu, ret);
2499                 return ret;
2500         }
2501         hns->pf.mps = (uint16_t)frame_size;
2502         if (is_jumbo_frame)
2503                 dev->data->dev_conf.rxmode.offloads |=
2504                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2505         else
2506                 dev->data->dev_conf.rxmode.offloads &=
2507                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2508         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2509         rte_spinlock_unlock(&hw->lock);
2510
2511         return 0;
2512 }
2513
2514 int
2515 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2516 {
2517         struct hns3_adapter *hns = eth_dev->data->dev_private;
2518         struct hns3_hw *hw = &hns->hw;
2519         uint16_t queue_num = hw->tqps_num;
2520
2521         /*
2522          * In interrupt mode, 'max_rx_queues' is set based on the number of
2523          * MSI-X interrupt resources of the hardware.
2524          */
2525         if (hw->data->dev_conf.intr_conf.rxq == 1)
2526                 queue_num = hw->intr_tqps_num;
2527
2528         info->max_rx_queues = queue_num;
2529         info->max_tx_queues = hw->tqps_num;
2530         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2531         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2532         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2533         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2534         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2535         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2536                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2537                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2538                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2539                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2540                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2541                                  DEV_RX_OFFLOAD_KEEP_CRC |
2542                                  DEV_RX_OFFLOAD_SCATTER |
2543                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2544                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2545                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2546                                  DEV_RX_OFFLOAD_RSS_HASH |
2547                                  DEV_RX_OFFLOAD_TCP_LRO);
2548         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2549                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2550                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2551                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2552                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2553                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2554                                  DEV_TX_OFFLOAD_TCP_TSO |
2555                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2556                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2557                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2558                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2559                                  hns3_txvlan_cap_get(hw));
2560
2561         if (hns3_dev_indep_txrx_supported(hw))
2562                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2563                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2564
2565         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2566                 .nb_max = HNS3_MAX_RING_DESC,
2567                 .nb_min = HNS3_MIN_RING_DESC,
2568                 .nb_align = HNS3_ALIGN_RING_DESC,
2569         };
2570
2571         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2572                 .nb_max = HNS3_MAX_RING_DESC,
2573                 .nb_min = HNS3_MIN_RING_DESC,
2574                 .nb_align = HNS3_ALIGN_RING_DESC,
2575                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2576                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2577         };
2578
2579         info->default_rxconf = (struct rte_eth_rxconf) {
2580                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2581                 /*
2582                  * If there are no available Rx buffer descriptors, incoming
2583                  * packets are always dropped by hardware based on hns3 network
2584                  * engine.
2585                  */
2586                 .rx_drop_en = 1,
2587                 .offloads = 0,
2588         };
2589         info->default_txconf = (struct rte_eth_txconf) {
2590                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2591                 .offloads = 0,
2592         };
2593
2594         info->vmdq_queue_num = 0;
2595
2596         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2597         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2598         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2599
2600         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2601         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2602         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2603         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2604         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2605         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2606
2607         return 0;
2608 }
2609
2610 static int
2611 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2612                     size_t fw_size)
2613 {
2614         struct hns3_adapter *hns = eth_dev->data->dev_private;
2615         struct hns3_hw *hw = &hns->hw;
2616         uint32_t version = hw->fw_version;
2617         int ret;
2618
2619         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2620                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2621                                       HNS3_FW_VERSION_BYTE3_S),
2622                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2623                                       HNS3_FW_VERSION_BYTE2_S),
2624                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2625                                       HNS3_FW_VERSION_BYTE1_S),
2626                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2627                                       HNS3_FW_VERSION_BYTE0_S));
2628         ret += 1; /* add the size of '\0' */
2629         if (fw_size < (uint32_t)ret)
2630                 return ret;
2631         else
2632                 return 0;
2633 }
2634
2635 static int
2636 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2637                      __rte_unused int wait_to_complete)
2638 {
2639         struct hns3_adapter *hns = eth_dev->data->dev_private;
2640         struct hns3_hw *hw = &hns->hw;
2641         struct hns3_mac *mac = &hw->mac;
2642         struct rte_eth_link new_link;
2643
2644         if (!hns3_is_reset_pending(hns)) {
2645                 hns3_update_link_status(hw);
2646                 hns3_update_link_info(eth_dev);
2647         }
2648
2649         memset(&new_link, 0, sizeof(new_link));
2650         switch (mac->link_speed) {
2651         case ETH_SPEED_NUM_10M:
2652         case ETH_SPEED_NUM_100M:
2653         case ETH_SPEED_NUM_1G:
2654         case ETH_SPEED_NUM_10G:
2655         case ETH_SPEED_NUM_25G:
2656         case ETH_SPEED_NUM_40G:
2657         case ETH_SPEED_NUM_50G:
2658         case ETH_SPEED_NUM_100G:
2659         case ETH_SPEED_NUM_200G:
2660                 new_link.link_speed = mac->link_speed;
2661                 break;
2662         default:
2663                 new_link.link_speed = ETH_SPEED_NUM_100M;
2664                 break;
2665         }
2666
2667         new_link.link_duplex = mac->link_duplex;
2668         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2669         new_link.link_autoneg =
2670             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2671
2672         return rte_eth_linkstatus_set(eth_dev, &new_link);
2673 }
2674
2675 static int
2676 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2677 {
2678         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2679         struct hns3_pf *pf = &hns->pf;
2680
2681         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2682                 return -EINVAL;
2683
2684         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2685
2686         return 0;
2687 }
2688
2689 static int
2690 hns3_query_function_status(struct hns3_hw *hw)
2691 {
2692 #define HNS3_QUERY_MAX_CNT              10
2693 #define HNS3_QUERY_SLEEP_MSCOEND        1
2694         struct hns3_func_status_cmd *req;
2695         struct hns3_cmd_desc desc;
2696         int timeout = 0;
2697         int ret;
2698
2699         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2700         req = (struct hns3_func_status_cmd *)desc.data;
2701
2702         do {
2703                 ret = hns3_cmd_send(hw, &desc, 1);
2704                 if (ret) {
2705                         PMD_INIT_LOG(ERR, "query function status failed %d",
2706                                      ret);
2707                         return ret;
2708                 }
2709
2710                 /* Check pf reset is done */
2711                 if (req->pf_state)
2712                         break;
2713
2714                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2715         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2716
2717         return hns3_parse_func_status(hw, req);
2718 }
2719
2720 static int
2721 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2722 {
2723         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2724         struct hns3_pf *pf = &hns->pf;
2725
2726         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2727                 /*
2728                  * The total_tqps_num obtained from firmware is maximum tqp
2729                  * numbers of this port, which should be used for PF and VFs.
2730                  * There is no need for pf to have so many tqp numbers in
2731                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2732                  * coming from config file, is assigned to maximum queue number
2733                  * for the PF of this port by user. So users can modify the
2734                  * maximum queue number of PF according to their own application
2735                  * scenarios, which is more flexible to use. In addition, many
2736                  * memories can be saved due to allocating queue statistics
2737                  * room according to the actual number of queues required. The
2738                  * maximum queue number of PF for network engine with
2739                  * revision_id greater than 0x30 is assigned by config file.
2740                  */
2741                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2742                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2743                                  "must be greater than 0.",
2744                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2745                         return -EINVAL;
2746                 }
2747
2748                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2749                                        hw->total_tqps_num);
2750         } else {
2751                 /*
2752                  * Due to the limitation on the number of PF interrupts
2753                  * available, the maximum queue number assigned to PF on
2754                  * the network engine with revision_id 0x21 is 64.
2755                  */
2756                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2757                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2758         }
2759
2760         return 0;
2761 }
2762
2763 static int
2764 hns3_query_pf_resource(struct hns3_hw *hw)
2765 {
2766         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2767         struct hns3_pf *pf = &hns->pf;
2768         struct hns3_pf_res_cmd *req;
2769         struct hns3_cmd_desc desc;
2770         int ret;
2771
2772         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2773         ret = hns3_cmd_send(hw, &desc, 1);
2774         if (ret) {
2775                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2776                 return ret;
2777         }
2778
2779         req = (struct hns3_pf_res_cmd *)desc.data;
2780         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2781                              rte_le_to_cpu_16(req->ext_tqp_num);
2782         ret = hns3_get_pf_max_tqp_num(hw);
2783         if (ret)
2784                 return ret;
2785
2786         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2787         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2788
2789         if (req->tx_buf_size)
2790                 pf->tx_buf_size =
2791                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2792         else
2793                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2794
2795         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2796
2797         if (req->dv_buf_size)
2798                 pf->dv_buf_size =
2799                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2800         else
2801                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2802
2803         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2804
2805         hw->num_msi =
2806                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2807                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2808
2809         return 0;
2810 }
2811
2812 static void
2813 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2814 {
2815         struct hns3_cfg_param_cmd *req;
2816         uint64_t mac_addr_tmp_high;
2817         uint8_t ext_rss_size_max;
2818         uint64_t mac_addr_tmp;
2819         uint32_t i;
2820
2821         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2822
2823         /* get the configuration */
2824         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2825                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2826         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2827                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2828         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2829                                            HNS3_CFG_TQP_DESC_N_M,
2830                                            HNS3_CFG_TQP_DESC_N_S);
2831
2832         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2833                                        HNS3_CFG_PHY_ADDR_M,
2834                                        HNS3_CFG_PHY_ADDR_S);
2835         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2836                                          HNS3_CFG_MEDIA_TP_M,
2837                                          HNS3_CFG_MEDIA_TP_S);
2838         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2839                                          HNS3_CFG_RX_BUF_LEN_M,
2840                                          HNS3_CFG_RX_BUF_LEN_S);
2841         /* get mac address */
2842         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2843         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2844                                            HNS3_CFG_MAC_ADDR_H_M,
2845                                            HNS3_CFG_MAC_ADDR_H_S);
2846
2847         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2848
2849         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2850                                             HNS3_CFG_DEFAULT_SPEED_M,
2851                                             HNS3_CFG_DEFAULT_SPEED_S);
2852         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2853                                            HNS3_CFG_RSS_SIZE_M,
2854                                            HNS3_CFG_RSS_SIZE_S);
2855
2856         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2857                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2858
2859         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2860         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2861
2862         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2863                                             HNS3_CFG_SPEED_ABILITY_M,
2864                                             HNS3_CFG_SPEED_ABILITY_S);
2865         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2866                                         HNS3_CFG_UMV_TBL_SPACE_M,
2867                                         HNS3_CFG_UMV_TBL_SPACE_S);
2868         if (!cfg->umv_space)
2869                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2870
2871         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2872                                                HNS3_CFG_EXT_RSS_SIZE_M,
2873                                                HNS3_CFG_EXT_RSS_SIZE_S);
2874
2875         /*
2876          * Field ext_rss_size_max obtained from firmware will be more flexible
2877          * for future changes and expansions, which is an exponent of 2, instead
2878          * of reading out directly. If this field is not zero, hns3 PF PMD
2879          * driver uses it as rss_size_max under one TC. Device, whose revision
2880          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2881          * maximum number of queues supported under a TC through this field.
2882          */
2883         if (ext_rss_size_max)
2884                 cfg->rss_size_max = 1U << ext_rss_size_max;
2885 }
2886
2887 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2888  * @hw: pointer to struct hns3_hw
2889  * @hcfg: the config structure to be getted
2890  */
2891 static int
2892 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2893 {
2894         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2895         struct hns3_cfg_param_cmd *req;
2896         uint32_t offset;
2897         uint32_t i;
2898         int ret;
2899
2900         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2901                 offset = 0;
2902                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2903                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2904                                           true);
2905                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2906                                i * HNS3_CFG_RD_LEN_BYTES);
2907                 /* Len should be divided by 4 when send to hardware */
2908                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2909                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2910                 req->offset = rte_cpu_to_le_32(offset);
2911         }
2912
2913         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2914         if (ret) {
2915                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2916                 return ret;
2917         }
2918
2919         hns3_parse_cfg(hcfg, desc);
2920
2921         return 0;
2922 }
2923
2924 static int
2925 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2926 {
2927         switch (speed_cmd) {
2928         case HNS3_CFG_SPEED_10M:
2929                 *speed = ETH_SPEED_NUM_10M;
2930                 break;
2931         case HNS3_CFG_SPEED_100M:
2932                 *speed = ETH_SPEED_NUM_100M;
2933                 break;
2934         case HNS3_CFG_SPEED_1G:
2935                 *speed = ETH_SPEED_NUM_1G;
2936                 break;
2937         case HNS3_CFG_SPEED_10G:
2938                 *speed = ETH_SPEED_NUM_10G;
2939                 break;
2940         case HNS3_CFG_SPEED_25G:
2941                 *speed = ETH_SPEED_NUM_25G;
2942                 break;
2943         case HNS3_CFG_SPEED_40G:
2944                 *speed = ETH_SPEED_NUM_40G;
2945                 break;
2946         case HNS3_CFG_SPEED_50G:
2947                 *speed = ETH_SPEED_NUM_50G;
2948                 break;
2949         case HNS3_CFG_SPEED_100G:
2950                 *speed = ETH_SPEED_NUM_100G;
2951                 break;
2952         case HNS3_CFG_SPEED_200G:
2953                 *speed = ETH_SPEED_NUM_200G;
2954                 break;
2955         default:
2956                 return -EINVAL;
2957         }
2958
2959         return 0;
2960 }
2961
2962 static void
2963 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2964 {
2965         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2966         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2967         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2968         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2969         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2970 }
2971
2972 static void
2973 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2974 {
2975         struct hns3_dev_specs_0_cmd *req0;
2976
2977         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2978
2979         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2980         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2981         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2982         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2983         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2984 }
2985
2986 static int
2987 hns3_query_dev_specifications(struct hns3_hw *hw)
2988 {
2989         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2990         int ret;
2991         int i;
2992
2993         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2994                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2995                                           true);
2996                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2997         }
2998         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2999
3000         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3001         if (ret)
3002                 return ret;
3003
3004         hns3_parse_dev_specifications(hw, desc);
3005
3006         return 0;
3007 }
3008
3009 static int
3010 hns3_get_capability(struct hns3_hw *hw)
3011 {
3012         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3013         struct rte_pci_device *pci_dev;
3014         struct hns3_pf *pf = &hns->pf;
3015         struct rte_eth_dev *eth_dev;
3016         uint16_t device_id;
3017         uint8_t revision;
3018         int ret;
3019
3020         eth_dev = &rte_eth_devices[hw->data->port_id];
3021         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3022         device_id = pci_dev->id.device_id;
3023
3024         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3025             device_id == HNS3_DEV_ID_50GE_RDMA ||
3026             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3027             device_id == HNS3_DEV_ID_200G_RDMA)
3028                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3029
3030         /* Get PCI revision id */
3031         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3032                                   HNS3_PCI_REVISION_ID);
3033         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3034                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3035                              ret);
3036                 return -EIO;
3037         }
3038         hw->revision = revision;
3039
3040         if (revision < PCI_REVISION_ID_HIP09_A) {
3041                 hns3_set_default_dev_specifications(hw);
3042                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3043                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3044                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3045                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3046                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3047                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3048                 hw->rss_info.ipv6_sctp_offload_supported = false;
3049                 return 0;
3050         }
3051
3052         ret = hns3_query_dev_specifications(hw);
3053         if (ret) {
3054                 PMD_INIT_LOG(ERR,
3055                              "failed to query dev specifications, ret = %d",
3056                              ret);
3057                 return ret;
3058         }
3059
3060         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3061         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3062         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3063         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3064         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3065         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3066         hw->rss_info.ipv6_sctp_offload_supported = true;
3067
3068         return 0;
3069 }
3070
3071 static int
3072 hns3_get_board_configuration(struct hns3_hw *hw)
3073 {
3074         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3075         struct hns3_pf *pf = &hns->pf;
3076         struct hns3_cfg cfg;
3077         int ret;
3078
3079         ret = hns3_get_board_cfg(hw, &cfg);
3080         if (ret) {
3081                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3082                 return ret;
3083         }
3084
3085         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3086             !hns3_dev_copper_supported(hw)) {
3087                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3088                 return -EOPNOTSUPP;
3089         }
3090
3091         hw->mac.media_type = cfg.media_type;
3092         hw->rss_size_max = cfg.rss_size_max;
3093         hw->rss_dis_flag = false;
3094         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3095         hw->mac.phy_addr = cfg.phy_addr;
3096         hw->mac.default_addr_setted = false;
3097         hw->num_tx_desc = cfg.tqp_desc_num;
3098         hw->num_rx_desc = cfg.tqp_desc_num;
3099         hw->dcb_info.num_pg = 1;
3100         hw->dcb_info.hw_pfc_map = 0;
3101
3102         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3103         if (ret) {
3104                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3105                              cfg.default_speed, ret);
3106                 return ret;
3107         }
3108
3109         pf->tc_max = cfg.tc_num;
3110         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3111                 PMD_INIT_LOG(WARNING,
3112                              "Get TC num(%u) from flash, set TC num to 1",
3113                              pf->tc_max);
3114                 pf->tc_max = 1;
3115         }
3116
3117         /* Dev does not support DCB */
3118         if (!hns3_dev_dcb_supported(hw)) {
3119                 pf->tc_max = 1;
3120                 pf->pfc_max = 0;
3121         } else
3122                 pf->pfc_max = pf->tc_max;
3123
3124         hw->dcb_info.num_tc = 1;
3125         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3126                                      hw->tqps_num / hw->dcb_info.num_tc);
3127         hns3_set_bit(hw->hw_tc_map, 0, 1);
3128         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3129
3130         pf->wanted_umv_size = cfg.umv_space;
3131
3132         return ret;
3133 }
3134
3135 static int
3136 hns3_get_configuration(struct hns3_hw *hw)
3137 {
3138         int ret;
3139
3140         ret = hns3_query_function_status(hw);
3141         if (ret) {
3142                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3143                 return ret;
3144         }
3145
3146         /* Get device capability */
3147         ret = hns3_get_capability(hw);
3148         if (ret) {
3149                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3150                 return ret;
3151         }
3152
3153         /* Get pf resource */
3154         ret = hns3_query_pf_resource(hw);
3155         if (ret) {
3156                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3157                 return ret;
3158         }
3159
3160         ret = hns3_get_board_configuration(hw);
3161         if (ret) {
3162                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3163                 return ret;
3164         }
3165
3166         ret = hns3_query_dev_fec_info(hw);
3167         if (ret)
3168                 PMD_INIT_LOG(ERR,
3169                              "failed to query FEC information, ret = %d", ret);
3170
3171         return ret;
3172 }
3173
3174 static int
3175 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3176                       uint16_t tqp_vid, bool is_pf)
3177 {
3178         struct hns3_tqp_map_cmd *req;
3179         struct hns3_cmd_desc desc;
3180         int ret;
3181
3182         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3183
3184         req = (struct hns3_tqp_map_cmd *)desc.data;
3185         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3186         req->tqp_vf = func_id;
3187         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3188         if (!is_pf)
3189                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3190         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3191
3192         ret = hns3_cmd_send(hw, &desc, 1);
3193         if (ret)
3194                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3195
3196         return ret;
3197 }
3198
3199 static int
3200 hns3_map_tqp(struct hns3_hw *hw)
3201 {
3202         int ret;
3203         int i;
3204
3205         /*
3206          * In current version, VF is not supported when PF is driven by DPDK
3207          * driver, so we assign total tqps_num tqps allocated to this port
3208          * to PF.
3209          */
3210         for (i = 0; i < hw->total_tqps_num; i++) {
3211                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3212                 if (ret)
3213                         return ret;
3214         }
3215
3216         return 0;
3217 }
3218
3219 static int
3220 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3221 {
3222         struct hns3_config_mac_speed_dup_cmd *req;
3223         struct hns3_cmd_desc desc;
3224         int ret;
3225
3226         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3227
3228         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3229
3230         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3231
3232         switch (speed) {
3233         case ETH_SPEED_NUM_10M:
3234                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3235                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3236                 break;
3237         case ETH_SPEED_NUM_100M:
3238                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3239                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3240                 break;
3241         case ETH_SPEED_NUM_1G:
3242                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3243                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3244                 break;
3245         case ETH_SPEED_NUM_10G:
3246                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3247                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3248                 break;
3249         case ETH_SPEED_NUM_25G:
3250                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3251                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3252                 break;
3253         case ETH_SPEED_NUM_40G:
3254                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3255                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3256                 break;
3257         case ETH_SPEED_NUM_50G:
3258                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3259                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3260                 break;
3261         case ETH_SPEED_NUM_100G:
3262                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3263                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3264                 break;
3265         case ETH_SPEED_NUM_200G:
3266                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3267                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3268                 break;
3269         default:
3270                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3271                 return -EINVAL;
3272         }
3273
3274         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3275
3276         ret = hns3_cmd_send(hw, &desc, 1);
3277         if (ret)
3278                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3279
3280         return ret;
3281 }
3282
3283 static int
3284 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3285 {
3286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3287         struct hns3_pf *pf = &hns->pf;
3288         struct hns3_priv_buf *priv;
3289         uint32_t i, total_size;
3290
3291         total_size = pf->pkt_buf_size;
3292
3293         /* alloc tx buffer for all enabled tc */
3294         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3295                 priv = &buf_alloc->priv_buf[i];
3296
3297                 if (hw->hw_tc_map & BIT(i)) {
3298                         if (total_size < pf->tx_buf_size)
3299                                 return -ENOMEM;
3300
3301                         priv->tx_buf_size = pf->tx_buf_size;
3302                 } else
3303                         priv->tx_buf_size = 0;
3304
3305                 total_size -= priv->tx_buf_size;
3306         }
3307
3308         return 0;
3309 }
3310
3311 static int
3312 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3313 {
3314 /* TX buffer size is unit by 128 byte */
3315 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3316 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3317         struct hns3_tx_buff_alloc_cmd *req;
3318         struct hns3_cmd_desc desc;
3319         uint32_t buf_size;
3320         uint32_t i;
3321         int ret;
3322
3323         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3324
3325         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3326         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3327                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3328
3329                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3330                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3331                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3332         }
3333
3334         ret = hns3_cmd_send(hw, &desc, 1);
3335         if (ret)
3336                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3337
3338         return ret;
3339 }
3340
3341 static int
3342 hns3_get_tc_num(struct hns3_hw *hw)
3343 {
3344         int cnt = 0;
3345         uint8_t i;
3346
3347         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3348                 if (hw->hw_tc_map & BIT(i))
3349                         cnt++;
3350         return cnt;
3351 }
3352
3353 static uint32_t
3354 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3355 {
3356         struct hns3_priv_buf *priv;
3357         uint32_t rx_priv = 0;
3358         int i;
3359
3360         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3361                 priv = &buf_alloc->priv_buf[i];
3362                 if (priv->enable)
3363                         rx_priv += priv->buf_size;
3364         }
3365         return rx_priv;
3366 }
3367
3368 static uint32_t
3369 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3370 {
3371         uint32_t total_tx_size = 0;
3372         uint32_t i;
3373
3374         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3375                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3376
3377         return total_tx_size;
3378 }
3379
3380 /* Get the number of pfc enabled TCs, which have private buffer */
3381 static int
3382 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3383 {
3384         struct hns3_priv_buf *priv;
3385         int cnt = 0;
3386         uint8_t i;
3387
3388         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3389                 priv = &buf_alloc->priv_buf[i];
3390                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3391                         cnt++;
3392         }
3393
3394         return cnt;
3395 }
3396
3397 /* Get the number of pfc disabled TCs, which have private buffer */
3398 static int
3399 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3400                          struct hns3_pkt_buf_alloc *buf_alloc)
3401 {
3402         struct hns3_priv_buf *priv;
3403         int cnt = 0;
3404         uint8_t i;
3405
3406         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3407                 priv = &buf_alloc->priv_buf[i];
3408                 if (hw->hw_tc_map & BIT(i) &&
3409                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3410                         cnt++;
3411         }
3412
3413         return cnt;
3414 }
3415
3416 static bool
3417 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3418                   uint32_t rx_all)
3419 {
3420         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3421         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3422         struct hns3_pf *pf = &hns->pf;
3423         uint32_t shared_buf, aligned_mps;
3424         uint32_t rx_priv;
3425         uint8_t tc_num;
3426         uint8_t i;
3427
3428         tc_num = hns3_get_tc_num(hw);
3429         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3430
3431         if (hns3_dev_dcb_supported(hw))
3432                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3433                                         pf->dv_buf_size;
3434         else
3435                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3436                                         + pf->dv_buf_size;
3437
3438         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3439         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3440                              HNS3_BUF_SIZE_UNIT);
3441
3442         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3443         if (rx_all < rx_priv + shared_std)
3444                 return false;
3445
3446         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3447         buf_alloc->s_buf.buf_size = shared_buf;
3448         if (hns3_dev_dcb_supported(hw)) {
3449                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3450                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3451                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3452                                   HNS3_BUF_SIZE_UNIT);
3453         } else {
3454                 buf_alloc->s_buf.self.high =
3455                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3456                 buf_alloc->s_buf.self.low = aligned_mps;
3457         }
3458
3459         if (hns3_dev_dcb_supported(hw)) {
3460                 hi_thrd = shared_buf - pf->dv_buf_size;
3461
3462                 if (tc_num <= NEED_RESERVE_TC_NUM)
3463                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3464                                   BUF_MAX_PERCENT;
3465
3466                 if (tc_num)
3467                         hi_thrd = hi_thrd / tc_num;
3468
3469                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3470                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3471                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3472         } else {
3473                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3474                 lo_thrd = aligned_mps;
3475         }
3476
3477         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3478                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3479                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3480         }
3481
3482         return true;
3483 }
3484
3485 static bool
3486 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3487                      struct hns3_pkt_buf_alloc *buf_alloc)
3488 {
3489         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3490         struct hns3_pf *pf = &hns->pf;
3491         struct hns3_priv_buf *priv;
3492         uint32_t aligned_mps;
3493         uint32_t rx_all;
3494         uint8_t i;
3495
3496         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3497         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3498
3499         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3500                 priv = &buf_alloc->priv_buf[i];
3501
3502                 priv->enable = 0;
3503                 priv->wl.low = 0;
3504                 priv->wl.high = 0;
3505                 priv->buf_size = 0;
3506
3507                 if (!(hw->hw_tc_map & BIT(i)))
3508                         continue;
3509
3510                 priv->enable = 1;
3511                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3512                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3513                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3514                                                 HNS3_BUF_SIZE_UNIT);
3515                 } else {
3516                         priv->wl.low = 0;
3517                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3518                                         aligned_mps;
3519                 }
3520
3521                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3522         }
3523
3524         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3525 }
3526
3527 static bool
3528 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3529                              struct hns3_pkt_buf_alloc *buf_alloc)
3530 {
3531         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3532         struct hns3_pf *pf = &hns->pf;
3533         struct hns3_priv_buf *priv;
3534         int no_pfc_priv_num;
3535         uint32_t rx_all;
3536         uint8_t mask;
3537         int i;
3538
3539         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3540         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3541
3542         /* let the last to be cleared first */
3543         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3544                 priv = &buf_alloc->priv_buf[i];
3545                 mask = BIT((uint8_t)i);
3546
3547                 if (hw->hw_tc_map & mask &&
3548                     !(hw->dcb_info.hw_pfc_map & mask)) {
3549                         /* Clear the no pfc TC private buffer */
3550                         priv->wl.low = 0;
3551                         priv->wl.high = 0;
3552                         priv->buf_size = 0;
3553                         priv->enable = 0;
3554                         no_pfc_priv_num--;
3555                 }
3556
3557                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3558                     no_pfc_priv_num == 0)
3559                         break;
3560         }
3561
3562         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3563 }
3564
3565 static bool
3566 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3567                            struct hns3_pkt_buf_alloc *buf_alloc)
3568 {
3569         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3570         struct hns3_pf *pf = &hns->pf;
3571         struct hns3_priv_buf *priv;
3572         uint32_t rx_all;
3573         int pfc_priv_num;
3574         uint8_t mask;
3575         int i;
3576
3577         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3578         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3579
3580         /* let the last to be cleared first */
3581         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3582                 priv = &buf_alloc->priv_buf[i];
3583                 mask = BIT((uint8_t)i);
3584                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3585                         /* Reduce the number of pfc TC with private buffer */
3586                         priv->wl.low = 0;
3587                         priv->enable = 0;
3588                         priv->wl.high = 0;
3589                         priv->buf_size = 0;
3590                         pfc_priv_num--;
3591                 }
3592                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3593                     pfc_priv_num == 0)
3594                         break;
3595         }
3596
3597         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3598 }
3599
3600 static bool
3601 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3602                           struct hns3_pkt_buf_alloc *buf_alloc)
3603 {
3604 #define COMPENSATE_BUFFER       0x3C00
3605 #define COMPENSATE_HALF_MPS_NUM 5
3606 #define PRIV_WL_GAP             0x1800
3607         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3608         struct hns3_pf *pf = &hns->pf;
3609         uint32_t tc_num = hns3_get_tc_num(hw);
3610         uint32_t half_mps = pf->mps >> 1;
3611         struct hns3_priv_buf *priv;
3612         uint32_t min_rx_priv;
3613         uint32_t rx_priv;
3614         uint8_t i;
3615
3616         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3617         if (tc_num)
3618                 rx_priv = rx_priv / tc_num;
3619
3620         if (tc_num <= NEED_RESERVE_TC_NUM)
3621                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3622
3623         /*
3624          * Minimum value of private buffer in rx direction (min_rx_priv) is
3625          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3626          * buffer if rx_priv is greater than min_rx_priv.
3627          */
3628         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3629                         COMPENSATE_HALF_MPS_NUM * half_mps;
3630         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3631         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3632
3633         if (rx_priv < min_rx_priv)
3634                 return false;
3635
3636         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3637                 priv = &buf_alloc->priv_buf[i];
3638                 priv->enable = 0;
3639                 priv->wl.low = 0;
3640                 priv->wl.high = 0;
3641                 priv->buf_size = 0;
3642
3643                 if (!(hw->hw_tc_map & BIT(i)))
3644                         continue;
3645
3646                 priv->enable = 1;
3647                 priv->buf_size = rx_priv;
3648                 priv->wl.high = rx_priv - pf->dv_buf_size;
3649                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3650         }
3651
3652         buf_alloc->s_buf.buf_size = 0;
3653
3654         return true;
3655 }
3656
3657 /*
3658  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3659  * @hw: pointer to struct hns3_hw
3660  * @buf_alloc: pointer to buffer calculation data
3661  * @return: 0: calculate sucessful, negative: fail
3662  */
3663 static int
3664 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3665 {
3666         /* When DCB is not supported, rx private buffer is not allocated. */
3667         if (!hns3_dev_dcb_supported(hw)) {
3668                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3669                 struct hns3_pf *pf = &hns->pf;
3670                 uint32_t rx_all = pf->pkt_buf_size;
3671
3672                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3673                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3674                         return -ENOMEM;
3675
3676                 return 0;
3677         }
3678
3679         /*
3680          * Try to allocate privated packet buffer for all TCs without share
3681          * buffer.
3682          */
3683         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3684                 return 0;
3685
3686         /*
3687          * Try to allocate privated packet buffer for all TCs with share
3688          * buffer.
3689          */
3690         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3691                 return 0;
3692
3693         /*
3694          * For different application scenes, the enabled port number, TC number
3695          * and no_drop TC number are different. In order to obtain the better
3696          * performance, software could allocate the buffer size and configure
3697          * the waterline by tring to decrease the private buffer size according
3698          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3699          * enabled tc.
3700          */
3701         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3702                 return 0;
3703
3704         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3705                 return 0;
3706
3707         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3708                 return 0;
3709
3710         return -ENOMEM;
3711 }
3712
3713 static int
3714 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3715 {
3716         struct hns3_rx_priv_buff_cmd *req;
3717         struct hns3_cmd_desc desc;
3718         uint32_t buf_size;
3719         int ret;
3720         int i;
3721
3722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3723         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3724
3725         /* Alloc private buffer TCs */
3726         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3727                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3728
3729                 req->buf_num[i] =
3730                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3731                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3732         }
3733
3734         buf_size = buf_alloc->s_buf.buf_size;
3735         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3736                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3737
3738         ret = hns3_cmd_send(hw, &desc, 1);
3739         if (ret)
3740                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3741
3742         return ret;
3743 }
3744
3745 static int
3746 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3747 {
3748 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3749         struct hns3_rx_priv_wl_buf *req;
3750         struct hns3_priv_buf *priv;
3751         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3752         int i, j;
3753         int ret;
3754
3755         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3756                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3757                                           false);
3758                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3759
3760                 /* The first descriptor set the NEXT bit to 1 */
3761                 if (i == 0)
3762                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3763                 else
3764                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3765
3766                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3767                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3768
3769                         priv = &buf_alloc->priv_buf[idx];
3770                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3771                                                         HNS3_BUF_UNIT_S);
3772                         req->tc_wl[j].high |=
3773                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3774                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3775                                                         HNS3_BUF_UNIT_S);
3776                         req->tc_wl[j].low |=
3777                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3778                 }
3779         }
3780
3781         /* Send 2 descriptor at one time */
3782         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3783         if (ret)
3784                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3785                              ret);
3786         return ret;
3787 }
3788
3789 static int
3790 hns3_common_thrd_config(struct hns3_hw *hw,
3791                         struct hns3_pkt_buf_alloc *buf_alloc)
3792 {
3793 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3794         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3795         struct hns3_rx_com_thrd *req;
3796         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3797         struct hns3_tc_thrd *tc;
3798         int tc_idx;
3799         int i, j;
3800         int ret;
3801
3802         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3803                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3804                                           false);
3805                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3806
3807                 /* The first descriptor set the NEXT bit to 1 */
3808                 if (i == 0)
3809                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3810                 else
3811                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3812
3813                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3814                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3815                         tc = &s_buf->tc_thrd[tc_idx];
3816
3817                         req->com_thrd[j].high =
3818                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3819                         req->com_thrd[j].high |=
3820                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3821                         req->com_thrd[j].low =
3822                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3823                         req->com_thrd[j].low |=
3824                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3825                 }
3826         }
3827
3828         /* Send 2 descriptors at one time */
3829         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3830         if (ret)
3831                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3832
3833         return ret;
3834 }
3835
3836 static int
3837 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3838 {
3839         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3840         struct hns3_rx_com_wl *req;
3841         struct hns3_cmd_desc desc;
3842         int ret;
3843
3844         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3845
3846         req = (struct hns3_rx_com_wl *)desc.data;
3847         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3848         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3849
3850         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3851         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3852
3853         ret = hns3_cmd_send(hw, &desc, 1);
3854         if (ret)
3855                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3856
3857         return ret;
3858 }
3859
3860 int
3861 hns3_buffer_alloc(struct hns3_hw *hw)
3862 {
3863         struct hns3_pkt_buf_alloc pkt_buf;
3864         int ret;
3865
3866         memset(&pkt_buf, 0, sizeof(pkt_buf));
3867         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3868         if (ret) {
3869                 PMD_INIT_LOG(ERR,
3870                              "could not calc tx buffer size for all TCs %d",
3871                              ret);
3872                 return ret;
3873         }
3874
3875         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3876         if (ret) {
3877                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3878                 return ret;
3879         }
3880
3881         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3882         if (ret) {
3883                 PMD_INIT_LOG(ERR,
3884                              "could not calc rx priv buffer size for all TCs %d",
3885                              ret);
3886                 return ret;
3887         }
3888
3889         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3890         if (ret) {
3891                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3892                 return ret;
3893         }
3894
3895         if (hns3_dev_dcb_supported(hw)) {
3896                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3897                 if (ret) {
3898                         PMD_INIT_LOG(ERR,
3899                                      "could not configure rx private waterline %d",
3900                                      ret);
3901                         return ret;
3902                 }
3903
3904                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3905                 if (ret) {
3906                         PMD_INIT_LOG(ERR,
3907                                      "could not configure common threshold %d",
3908                                      ret);
3909                         return ret;
3910                 }
3911         }
3912
3913         ret = hns3_common_wl_config(hw, &pkt_buf);
3914         if (ret)
3915                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3916                              ret);
3917
3918         return ret;
3919 }
3920
3921 static int
3922 hns3_mac_init(struct hns3_hw *hw)
3923 {
3924         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3925         struct hns3_mac *mac = &hw->mac;
3926         struct hns3_pf *pf = &hns->pf;
3927         int ret;
3928
3929         pf->support_sfp_query = true;
3930         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3931         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3932         if (ret) {
3933                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3934                 return ret;
3935         }
3936
3937         mac->link_status = ETH_LINK_DOWN;
3938
3939         return hns3_config_mtu(hw, pf->mps);
3940 }
3941
3942 static int
3943 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3944 {
3945 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3946 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3947 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3948 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3949         int return_status;
3950
3951         if (cmdq_resp) {
3952                 PMD_INIT_LOG(ERR,
3953                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3954                              cmdq_resp);
3955                 return -EIO;
3956         }
3957
3958         switch (resp_code) {
3959         case HNS3_ETHERTYPE_SUCCESS_ADD:
3960         case HNS3_ETHERTYPE_ALREADY_ADD:
3961                 return_status = 0;
3962                 break;
3963         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3964                 PMD_INIT_LOG(ERR,
3965                              "add mac ethertype failed for manager table overflow.");
3966                 return_status = -EIO;
3967                 break;
3968         case HNS3_ETHERTYPE_KEY_CONFLICT:
3969                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3970                 return_status = -EIO;
3971                 break;
3972         default:
3973                 PMD_INIT_LOG(ERR,
3974                              "add mac ethertype failed for undefined, code=%u.",
3975                              resp_code);
3976                 return_status = -EIO;
3977                 break;
3978         }
3979
3980         return return_status;
3981 }
3982
3983 static int
3984 hns3_add_mgr_tbl(struct hns3_hw *hw,
3985                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3986 {
3987         struct hns3_cmd_desc desc;
3988         uint8_t resp_code;
3989         uint16_t retval;
3990         int ret;
3991
3992         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3993         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3994
3995         ret = hns3_cmd_send(hw, &desc, 1);
3996         if (ret) {
3997                 PMD_INIT_LOG(ERR,
3998                              "add mac ethertype failed for cmd_send, ret =%d.",
3999                              ret);
4000                 return ret;
4001         }
4002
4003         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4004         retval = rte_le_to_cpu_16(desc.retval);
4005
4006         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4007 }
4008
4009 static void
4010 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4011                      int *table_item_num)
4012 {
4013         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4014
4015         /*
4016          * In current version, we add one item in management table as below:
4017          * 0x0180C200000E -- LLDP MC address
4018          */
4019         tbl = mgr_table;
4020         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4021         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4022         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4023         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4024         tbl->i_port_bitmap = 0x1;
4025         *table_item_num = 1;
4026 }
4027
4028 static int
4029 hns3_init_mgr_tbl(struct hns3_hw *hw)
4030 {
4031 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4032         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4033         int table_item_num;
4034         int ret;
4035         int i;
4036
4037         memset(mgr_table, 0, sizeof(mgr_table));
4038         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4039         for (i = 0; i < table_item_num; i++) {
4040                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4041                 if (ret) {
4042                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4043                                      ret);
4044                         return ret;
4045                 }
4046         }
4047
4048         return 0;
4049 }
4050
4051 static void
4052 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4053                         bool en_mc, bool en_bc, int vport_id)
4054 {
4055         if (!param)
4056                 return;
4057
4058         memset(param, 0, sizeof(struct hns3_promisc_param));
4059         if (en_uc)
4060                 param->enable = HNS3_PROMISC_EN_UC;
4061         if (en_mc)
4062                 param->enable |= HNS3_PROMISC_EN_MC;
4063         if (en_bc)
4064                 param->enable |= HNS3_PROMISC_EN_BC;
4065         param->vf_id = vport_id;
4066 }
4067
4068 static int
4069 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4070 {
4071         struct hns3_promisc_cfg_cmd *req;
4072         struct hns3_cmd_desc desc;
4073         int ret;
4074
4075         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4076
4077         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4078         req->vf_id = param->vf_id;
4079         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4080             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4081
4082         ret = hns3_cmd_send(hw, &desc, 1);
4083         if (ret)
4084                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4085
4086         return ret;
4087 }
4088
4089 static int
4090 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4091 {
4092         struct hns3_promisc_param param;
4093         bool en_bc_pmc = true;
4094         uint8_t vf_id;
4095
4096         /*
4097          * In current version VF is not supported when PF is driven by DPDK
4098          * driver, just need to configure parameters for PF vport.
4099          */
4100         vf_id = HNS3_PF_FUNC_ID;
4101
4102         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4103         return hns3_cmd_set_promisc_mode(hw, &param);
4104 }
4105
4106 static int
4107 hns3_promisc_init(struct hns3_hw *hw)
4108 {
4109         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4110         struct hns3_pf *pf = &hns->pf;
4111         struct hns3_promisc_param param;
4112         uint16_t func_id;
4113         int ret;
4114
4115         ret = hns3_set_promisc_mode(hw, false, false);
4116         if (ret) {
4117                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4118                 return ret;
4119         }
4120
4121         /*
4122          * In current version VFs are not supported when PF is driven by DPDK
4123          * driver. After PF has been taken over by DPDK, the original VF will
4124          * be invalid. So, there is a possibility of entry residues. It should
4125          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4126          * during init.
4127          */
4128         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4129                 hns3_promisc_param_init(&param, false, false, false, func_id);
4130                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4131                 if (ret) {
4132                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4133                                         " ret = %d", func_id, ret);
4134                         return ret;
4135                 }
4136         }
4137
4138         return 0;
4139 }
4140
4141 static void
4142 hns3_promisc_uninit(struct hns3_hw *hw)
4143 {
4144         struct hns3_promisc_param param;
4145         uint16_t func_id;
4146         int ret;
4147
4148         func_id = HNS3_PF_FUNC_ID;
4149
4150         /*
4151          * In current version VFs are not supported when PF is driven by
4152          * DPDK driver, and VFs' promisc mode status has been cleared during
4153          * init and their status will not change. So just clear PF's promisc
4154          * mode status during uninit.
4155          */
4156         hns3_promisc_param_init(&param, false, false, false, func_id);
4157         ret = hns3_cmd_set_promisc_mode(hw, &param);
4158         if (ret)
4159                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4160                                 " uninit, ret = %d", ret);
4161 }
4162
4163 static int
4164 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4165 {
4166         bool allmulti = dev->data->all_multicast ? true : false;
4167         struct hns3_adapter *hns = dev->data->dev_private;
4168         struct hns3_hw *hw = &hns->hw;
4169         uint64_t offloads;
4170         int err;
4171         int ret;
4172
4173         rte_spinlock_lock(&hw->lock);
4174         ret = hns3_set_promisc_mode(hw, true, true);
4175         if (ret) {
4176                 rte_spinlock_unlock(&hw->lock);
4177                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4178                          ret);
4179                 return ret;
4180         }
4181
4182         /*
4183          * When promiscuous mode was enabled, disable the vlan filter to let
4184          * all packets coming in in the receiving direction.
4185          */
4186         offloads = dev->data->dev_conf.rxmode.offloads;
4187         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4188                 ret = hns3_enable_vlan_filter(hns, false);
4189                 if (ret) {
4190                         hns3_err(hw, "failed to enable promiscuous mode due to "
4191                                      "failure to disable vlan filter, ret = %d",
4192                                  ret);
4193                         err = hns3_set_promisc_mode(hw, false, allmulti);
4194                         if (err)
4195                                 hns3_err(hw, "failed to restore promiscuous "
4196                                          "status after disable vlan filter "
4197                                          "failed during enabling promiscuous "
4198                                          "mode, ret = %d", ret);
4199                 }
4200         }
4201
4202         rte_spinlock_unlock(&hw->lock);
4203
4204         return ret;
4205 }
4206
4207 static int
4208 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4209 {
4210         bool allmulti = dev->data->all_multicast ? true : false;
4211         struct hns3_adapter *hns = dev->data->dev_private;
4212         struct hns3_hw *hw = &hns->hw;
4213         uint64_t offloads;
4214         int err;
4215         int ret;
4216
4217         /* If now in all_multicast mode, must remain in all_multicast mode. */
4218         rte_spinlock_lock(&hw->lock);
4219         ret = hns3_set_promisc_mode(hw, false, allmulti);
4220         if (ret) {
4221                 rte_spinlock_unlock(&hw->lock);
4222                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4223                          ret);
4224                 return ret;
4225         }
4226         /* when promiscuous mode was disabled, restore the vlan filter status */
4227         offloads = dev->data->dev_conf.rxmode.offloads;
4228         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4229                 ret = hns3_enable_vlan_filter(hns, true);
4230                 if (ret) {
4231                         hns3_err(hw, "failed to disable promiscuous mode due to"
4232                                  " failure to restore vlan filter, ret = %d",
4233                                  ret);
4234                         err = hns3_set_promisc_mode(hw, true, true);
4235                         if (err)
4236                                 hns3_err(hw, "failed to restore promiscuous "
4237                                          "status after enabling vlan filter "
4238                                          "failed during disabling promiscuous "
4239                                          "mode, ret = %d", ret);
4240                 }
4241         }
4242         rte_spinlock_unlock(&hw->lock);
4243
4244         return ret;
4245 }
4246
4247 static int
4248 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4249 {
4250         struct hns3_adapter *hns = dev->data->dev_private;
4251         struct hns3_hw *hw = &hns->hw;
4252         int ret;
4253
4254         if (dev->data->promiscuous)
4255                 return 0;
4256
4257         rte_spinlock_lock(&hw->lock);
4258         ret = hns3_set_promisc_mode(hw, false, true);
4259         rte_spinlock_unlock(&hw->lock);
4260         if (ret)
4261                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4262                          ret);
4263
4264         return ret;
4265 }
4266
4267 static int
4268 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4269 {
4270         struct hns3_adapter *hns = dev->data->dev_private;
4271         struct hns3_hw *hw = &hns->hw;
4272         int ret;
4273
4274         /* If now in promiscuous mode, must remain in all_multicast mode. */
4275         if (dev->data->promiscuous)
4276                 return 0;
4277
4278         rte_spinlock_lock(&hw->lock);
4279         ret = hns3_set_promisc_mode(hw, false, false);
4280         rte_spinlock_unlock(&hw->lock);
4281         if (ret)
4282                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4283                          ret);
4284
4285         return ret;
4286 }
4287
4288 static int
4289 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4290 {
4291         struct hns3_hw *hw = &hns->hw;
4292         bool allmulti = hw->data->all_multicast ? true : false;
4293         int ret;
4294
4295         if (hw->data->promiscuous) {
4296                 ret = hns3_set_promisc_mode(hw, true, true);
4297                 if (ret)
4298                         hns3_err(hw, "failed to restore promiscuous mode, "
4299                                  "ret = %d", ret);
4300                 return ret;
4301         }
4302
4303         ret = hns3_set_promisc_mode(hw, false, allmulti);
4304         if (ret)
4305                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4306                          ret);
4307         return ret;
4308 }
4309
4310 static int
4311 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4312 {
4313         struct hns3_sfp_speed_cmd *resp;
4314         struct hns3_cmd_desc desc;
4315         int ret;
4316
4317         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4318         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4319         ret = hns3_cmd_send(hw, &desc, 1);
4320         if (ret == -EOPNOTSUPP) {
4321                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4322                 return ret;
4323         } else if (ret) {
4324                 hns3_err(hw, "get sfp speed failed %d", ret);
4325                 return ret;
4326         }
4327
4328         *speed = resp->sfp_speed;
4329
4330         return 0;
4331 }
4332
4333 static uint8_t
4334 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4335 {
4336         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4337                 duplex = ETH_LINK_FULL_DUPLEX;
4338
4339         return duplex;
4340 }
4341
4342 static int
4343 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4344 {
4345         struct hns3_mac *mac = &hw->mac;
4346         uint32_t cur_speed = mac->link_speed;
4347         int ret;
4348
4349         duplex = hns3_check_speed_dup(duplex, speed);
4350         if (mac->link_speed == speed && mac->link_duplex == duplex)
4351                 return 0;
4352
4353         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4354         if (ret)
4355                 return ret;
4356
4357         mac->link_speed = speed;
4358         ret = hns3_dcb_port_shaper_cfg(hw);
4359         if (ret) {
4360                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4361                 mac->link_speed = cur_speed;
4362                 return ret;
4363         }
4364
4365         mac->link_duplex = duplex;
4366
4367         return 0;
4368 }
4369
4370 static int
4371 hns3_update_fiber_link_info(struct hns3_hw *hw)
4372 {
4373         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4374         uint32_t speed;
4375         int ret;
4376
4377         /* If IMP do not support get SFP/qSFP speed, return directly */
4378         if (!pf->support_sfp_query)
4379                 return 0;
4380
4381         ret = hns3_get_sfp_speed(hw, &speed);
4382         if (ret == -EOPNOTSUPP) {
4383                 pf->support_sfp_query = false;
4384                 return ret;
4385         } else if (ret)
4386                 return ret;
4387
4388         if (speed == ETH_SPEED_NUM_NONE)
4389                 return 0; /* do nothing if no SFP */
4390
4391         /* Config full duplex for SFP */
4392         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4393 }
4394
4395 static int
4396 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4397 {
4398         struct hns3_adapter *hns = eth_dev->data->dev_private;
4399         struct hns3_hw *hw = &hns->hw;
4400         int ret = 0;
4401
4402         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4403                 return 0;
4404         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4405                 ret = hns3_update_fiber_link_info(hw);
4406
4407         return ret;
4408 }
4409
4410 static int
4411 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4412 {
4413         struct hns3_config_mac_mode_cmd *req;
4414         struct hns3_cmd_desc desc;
4415         uint32_t loop_en = 0;
4416         uint8_t val = 0;
4417         int ret;
4418
4419         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4420
4421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4422         if (enable)
4423                 val = 1;
4424         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4425         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4426         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4427         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4428         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4429         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4430         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4431         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4432         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4433         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4434
4435         /*
4436          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4437          * when receiving frames. Otherwise, CRC will be stripped.
4438          */
4439         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4440                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4441         else
4442                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4443         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4444         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4445         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4446         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4447
4448         ret = hns3_cmd_send(hw, &desc, 1);
4449         if (ret)
4450                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4451
4452         return ret;
4453 }
4454
4455 static int
4456 hns3_get_mac_link_status(struct hns3_hw *hw)
4457 {
4458         struct hns3_link_status_cmd *req;
4459         struct hns3_cmd_desc desc;
4460         int link_status;
4461         int ret;
4462
4463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4464         ret = hns3_cmd_send(hw, &desc, 1);
4465         if (ret) {
4466                 hns3_err(hw, "get link status cmd failed %d", ret);
4467                 return ETH_LINK_DOWN;
4468         }
4469
4470         req = (struct hns3_link_status_cmd *)desc.data;
4471         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4472
4473         return !!link_status;
4474 }
4475
4476 static bool
4477 hns3_update_link_status(struct hns3_hw *hw)
4478 {
4479         int state;
4480
4481         state = hns3_get_mac_link_status(hw);
4482         if (state != hw->mac.link_status) {
4483                 hw->mac.link_status = state;
4484                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4485                 return true;
4486         }
4487
4488         return false;
4489 }
4490
4491 /*
4492  * Current, the PF driver get link status by two ways:
4493  * 1) Periodic polling in the intr thread context, driver call
4494  *    hns3_update_link_status to update link status.
4495  * 2) Firmware report async interrupt, driver process the event in the intr
4496  *    thread context, and call hns3_update_link_status to update link status.
4497  *
4498  * If detect link status changed, driver need report LSE. One method is add the
4499  * report LSE logic in hns3_update_link_status.
4500  *
4501  * But the PF driver ops(link_update) also call hns3_update_link_status to
4502  * update link status.
4503  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4504  * bonding application.
4505  *
4506  * So add the one new API which used only in intr thread context.
4507  */
4508 void
4509 hns3_update_link_status_and_event(struct hns3_hw *hw)
4510 {
4511         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4512         bool changed = hns3_update_link_status(hw);
4513         if (changed)
4514                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4515 }
4516
4517 static void
4518 hns3_service_handler(void *param)
4519 {
4520         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4521         struct hns3_adapter *hns = eth_dev->data->dev_private;
4522         struct hns3_hw *hw = &hns->hw;
4523
4524         if (!hns3_is_reset_pending(hns)) {
4525                 hns3_update_link_status_and_event(hw);
4526                 hns3_update_link_info(eth_dev);
4527         } else {
4528                 hns3_warn(hw, "Cancel the query when reset is pending");
4529         }
4530
4531         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4532 }
4533
4534 static int
4535 hns3_init_hardware(struct hns3_adapter *hns)
4536 {
4537         struct hns3_hw *hw = &hns->hw;
4538         int ret;
4539
4540         ret = hns3_map_tqp(hw);
4541         if (ret) {
4542                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4543                 return ret;
4544         }
4545
4546         ret = hns3_init_umv_space(hw);
4547         if (ret) {
4548                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4549                 return ret;
4550         }
4551
4552         ret = hns3_mac_init(hw);
4553         if (ret) {
4554                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4555                 goto err_mac_init;
4556         }
4557
4558         ret = hns3_init_mgr_tbl(hw);
4559         if (ret) {
4560                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4561                 goto err_mac_init;
4562         }
4563
4564         ret = hns3_promisc_init(hw);
4565         if (ret) {
4566                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4567                              ret);
4568                 goto err_mac_init;
4569         }
4570
4571         ret = hns3_init_vlan_config(hns);
4572         if (ret) {
4573                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4574                 goto err_mac_init;
4575         }
4576
4577         ret = hns3_dcb_init(hw);
4578         if (ret) {
4579                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4580                 goto err_mac_init;
4581         }
4582
4583         ret = hns3_init_fd_config(hns);
4584         if (ret) {
4585                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4586                 goto err_mac_init;
4587         }
4588
4589         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4590         if (ret) {
4591                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4592                 goto err_mac_init;
4593         }
4594
4595         ret = hns3_config_gro(hw, false);
4596         if (ret) {
4597                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4598                 goto err_mac_init;
4599         }
4600
4601         /*
4602          * In the initialization clearing the all hardware mapping relationship
4603          * configurations between queues and interrupt vectors is needed, so
4604          * some error caused by the residual configurations, such as the
4605          * unexpected interrupt, can be avoid.
4606          */
4607         ret = hns3_init_ring_with_vector(hw);
4608         if (ret) {
4609                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4610                 goto err_mac_init;
4611         }
4612
4613         return 0;
4614
4615 err_mac_init:
4616         hns3_uninit_umv_space(hw);
4617         return ret;
4618 }
4619
4620 static int
4621 hns3_clear_hw(struct hns3_hw *hw)
4622 {
4623         struct hns3_cmd_desc desc;
4624         int ret;
4625
4626         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4627
4628         ret = hns3_cmd_send(hw, &desc, 1);
4629         if (ret && ret != -EOPNOTSUPP)
4630                 return ret;
4631
4632         return 0;
4633 }
4634
4635 static void
4636 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4637 {
4638         uint32_t val;
4639
4640         /*
4641          * The new firmware support report more hardware error types by
4642          * msix mode. These errors are defined as RAS errors in hardware
4643          * and belong to a different type from the MSI-x errors processed
4644          * by the network driver.
4645          *
4646          * Network driver should open the new error report on initialition
4647          */
4648         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4649         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4650         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4651 }
4652
4653 static int
4654 hns3_init_pf(struct rte_eth_dev *eth_dev)
4655 {
4656         struct rte_device *dev = eth_dev->device;
4657         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4658         struct hns3_adapter *hns = eth_dev->data->dev_private;
4659         struct hns3_hw *hw = &hns->hw;
4660         int ret;
4661
4662         PMD_INIT_FUNC_TRACE();
4663
4664         /* Get hardware io base address from pcie BAR2 IO space */
4665         hw->io_base = pci_dev->mem_resource[2].addr;
4666
4667         /* Firmware command queue initialize */
4668         ret = hns3_cmd_init_queue(hw);
4669         if (ret) {
4670                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4671                 goto err_cmd_init_queue;
4672         }
4673
4674         hns3_clear_all_event_cause(hw);
4675
4676         /* Firmware command initialize */
4677         ret = hns3_cmd_init(hw);
4678         if (ret) {
4679                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4680                 goto err_cmd_init;
4681         }
4682
4683         /*
4684          * To ensure that the hardware environment is clean during
4685          * initialization, the driver actively clear the hardware environment
4686          * during initialization, including PF and corresponding VFs' vlan, mac,
4687          * flow table configurations, etc.
4688          */
4689         ret = hns3_clear_hw(hw);
4690         if (ret) {
4691                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4692                 goto err_cmd_init;
4693         }
4694
4695         hns3_config_all_msix_error(hw, true);
4696
4697         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4698                                          hns3_interrupt_handler,
4699                                          eth_dev);
4700         if (ret) {
4701                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4702                 goto err_intr_callback_register;
4703         }
4704
4705         /* Enable interrupt */
4706         rte_intr_enable(&pci_dev->intr_handle);
4707         hns3_pf_enable_irq0(hw);
4708
4709         /* Get configuration */
4710         ret = hns3_get_configuration(hw);
4711         if (ret) {
4712                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4713                 goto err_get_config;
4714         }
4715
4716         ret = hns3_tqp_stats_init(hw);
4717         if (ret)
4718                 goto err_get_config;
4719
4720         ret = hns3_init_hardware(hns);
4721         if (ret) {
4722                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4723                 goto err_init_hw;
4724         }
4725
4726         /* Initialize flow director filter list & hash */
4727         ret = hns3_fdir_filter_init(hns);
4728         if (ret) {
4729                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4730                 goto err_fdir;
4731         }
4732
4733         hns3_rss_set_default_args(hw);
4734
4735         ret = hns3_enable_hw_error_intr(hns, true);
4736         if (ret) {
4737                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4738                              ret);
4739                 goto err_enable_intr;
4740         }
4741
4742         hns3_tm_conf_init(eth_dev);
4743
4744         return 0;
4745
4746 err_enable_intr:
4747         hns3_fdir_filter_uninit(hns);
4748 err_fdir:
4749         hns3_uninit_umv_space(hw);
4750 err_init_hw:
4751         hns3_tqp_stats_uninit(hw);
4752 err_get_config:
4753         hns3_pf_disable_irq0(hw);
4754         rte_intr_disable(&pci_dev->intr_handle);
4755         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4756                              eth_dev);
4757 err_intr_callback_register:
4758 err_cmd_init:
4759         hns3_cmd_uninit(hw);
4760         hns3_cmd_destroy_queue(hw);
4761 err_cmd_init_queue:
4762         hw->io_base = NULL;
4763
4764         return ret;
4765 }
4766
4767 static void
4768 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4769 {
4770         struct hns3_adapter *hns = eth_dev->data->dev_private;
4771         struct rte_device *dev = eth_dev->device;
4772         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4773         struct hns3_hw *hw = &hns->hw;
4774
4775         PMD_INIT_FUNC_TRACE();
4776
4777         hns3_tm_conf_uninit(eth_dev);
4778         hns3_enable_hw_error_intr(hns, false);
4779         hns3_rss_uninit(hns);
4780         (void)hns3_config_gro(hw, false);
4781         hns3_promisc_uninit(hw);
4782         hns3_fdir_filter_uninit(hns);
4783         hns3_uninit_umv_space(hw);
4784         hns3_tqp_stats_uninit(hw);
4785         hns3_pf_disable_irq0(hw);
4786         rte_intr_disable(&pci_dev->intr_handle);
4787         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4788                              eth_dev);
4789         hns3_config_all_msix_error(hw, false);
4790         hns3_cmd_uninit(hw);
4791         hns3_cmd_destroy_queue(hw);
4792         hw->io_base = NULL;
4793 }
4794
4795 static int
4796 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4797 {
4798         struct hns3_hw *hw = &hns->hw;
4799         int ret;
4800
4801         ret = hns3_dcb_cfg_update(hns);
4802         if (ret)
4803                 return ret;
4804
4805         /*
4806          * The hns3_dcb_cfg_update may configure TM module, so
4807          * hns3_tm_conf_update must called later.
4808          */
4809         ret = hns3_tm_conf_update(hw);
4810         if (ret) {
4811                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4812                 return ret;
4813         }
4814
4815         ret = hns3_init_queues(hns, reset_queue);
4816         if (ret) {
4817                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4818                 return ret;
4819         }
4820
4821         ret = hns3_cfg_mac_mode(hw, true);
4822         if (ret) {
4823                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4824                 goto err_config_mac_mode;
4825         }
4826         return 0;
4827
4828 err_config_mac_mode:
4829         hns3_dev_release_mbufs(hns);
4830         /*
4831          * Here is exception handling, hns3_reset_all_tqps will have the
4832          * corresponding error message if it is handled incorrectly, so it is
4833          * not necessary to check hns3_reset_all_tqps return value, here keep
4834          * ret as the error code causing the exception.
4835          */
4836         (void)hns3_reset_all_tqps(hns);
4837         return ret;
4838 }
4839
4840 static int
4841 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4842 {
4843         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4844         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4845         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
4847         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4848         uint32_t intr_vector;
4849         uint16_t q_id;
4850         int ret;
4851
4852         /*
4853          * hns3 needs a separate interrupt to be used as event interrupt which
4854          * could not be shared with task queue pair, so KERNEL drivers need
4855          * support multiple interrupt vectors.
4856          */
4857         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4858             !rte_intr_cap_multiple(intr_handle))
4859                 return 0;
4860
4861         rte_intr_disable(intr_handle);
4862         intr_vector = hw->used_rx_queues;
4863         /* creates event fd for each intr vector when MSIX is used */
4864         if (rte_intr_efd_enable(intr_handle, intr_vector))
4865                 return -EINVAL;
4866
4867         if (intr_handle->intr_vec == NULL) {
4868                 intr_handle->intr_vec =
4869                         rte_zmalloc("intr_vec",
4870                                     hw->used_rx_queues * sizeof(int), 0);
4871                 if (intr_handle->intr_vec == NULL) {
4872                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4873                                         hw->used_rx_queues);
4874                         ret = -ENOMEM;
4875                         goto alloc_intr_vec_error;
4876                 }
4877         }
4878
4879         if (rte_intr_allow_others(intr_handle)) {
4880                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4881                 base = RTE_INTR_VEC_RXTX_OFFSET;
4882         }
4883
4884         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4885                 ret = hns3_bind_ring_with_vector(hw, vec, true,
4886                                                  HNS3_RING_TYPE_RX, q_id);
4887                 if (ret)
4888                         goto bind_vector_error;
4889                 intr_handle->intr_vec[q_id] = vec;
4890                 /*
4891                  * If there are not enough efds (e.g. not enough interrupt),
4892                  * remaining queues will be bond to the last interrupt.
4893                  */
4894                 if (vec < base + intr_handle->nb_efd - 1)
4895                         vec++;
4896         }
4897         rte_intr_enable(intr_handle);
4898         return 0;
4899
4900 bind_vector_error:
4901         rte_free(intr_handle->intr_vec);
4902         intr_handle->intr_vec = NULL;
4903 alloc_intr_vec_error:
4904         rte_intr_efd_disable(intr_handle);
4905         return ret;
4906 }
4907
4908 static int
4909 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4910 {
4911         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4913         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4914         uint16_t q_id;
4915         int ret;
4916
4917         if (dev->data->dev_conf.intr_conf.rxq == 0)
4918                 return 0;
4919
4920         if (rte_intr_dp_is_en(intr_handle)) {
4921                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4922                         ret = hns3_bind_ring_with_vector(hw,
4923                                         intr_handle->intr_vec[q_id], true,
4924                                         HNS3_RING_TYPE_RX, q_id);
4925                         if (ret)
4926                                 return ret;
4927                 }
4928         }
4929
4930         return 0;
4931 }
4932
4933 static void
4934 hns3_restore_filter(struct rte_eth_dev *dev)
4935 {
4936         hns3_restore_rss_filter(dev);
4937 }
4938
4939 static int
4940 hns3_dev_start(struct rte_eth_dev *dev)
4941 {
4942         struct hns3_adapter *hns = dev->data->dev_private;
4943         struct hns3_hw *hw = &hns->hw;
4944         int ret;
4945
4946         PMD_INIT_FUNC_TRACE();
4947         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4948                 return -EBUSY;
4949
4950         rte_spinlock_lock(&hw->lock);
4951         hw->adapter_state = HNS3_NIC_STARTING;
4952
4953         ret = hns3_do_start(hns, true);
4954         if (ret) {
4955                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4956                 rte_spinlock_unlock(&hw->lock);
4957                 return ret;
4958         }
4959         ret = hns3_map_rx_interrupt(dev);
4960         if (ret) {
4961                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4962                 rte_spinlock_unlock(&hw->lock);
4963                 return ret;
4964         }
4965
4966         /*
4967          * There are three register used to control the status of a TQP
4968          * (contains a pair of Tx queue and Rx queue) in the new version network
4969          * engine. One is used to control the enabling of Tx queue, the other is
4970          * used to control the enabling of Rx queue, and the last is the master
4971          * switch used to control the enabling of the tqp. The Tx register and
4972          * TQP register must be enabled at the same time to enable a Tx queue.
4973          * The same applies to the Rx queue. For the older network engine, this
4974          * function only refresh the enabled flag, and it is used to update the
4975          * status of queue in the dpdk framework.
4976          */
4977         ret = hns3_start_all_txqs(dev);
4978         if (ret) {
4979                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4980                 rte_spinlock_unlock(&hw->lock);
4981                 return ret;
4982         }
4983
4984         ret = hns3_start_all_rxqs(dev);
4985         if (ret) {
4986                 hns3_stop_all_txqs(dev);
4987                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4988                 rte_spinlock_unlock(&hw->lock);
4989                 return ret;
4990         }
4991
4992         hw->adapter_state = HNS3_NIC_STARTED;
4993         rte_spinlock_unlock(&hw->lock);
4994
4995         hns3_rx_scattered_calc(dev);
4996         hns3_set_rxtx_function(dev);
4997         hns3_mp_req_start_rxtx(dev);
4998         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4999
5000         hns3_restore_filter(dev);
5001
5002         /* Enable interrupt of all rx queues before enabling queues */
5003         hns3_dev_all_rx_queue_intr_enable(hw, true);
5004
5005         /*
5006          * After finished the initialization, enable tqps to receive/transmit
5007          * packets and refresh all queue status.
5008          */
5009         hns3_start_tqps(hw);
5010
5011         hns3_tm_dev_start_proc(hw);
5012
5013         hns3_info(hw, "hns3 dev start successful!");
5014         return 0;
5015 }
5016
5017 static int
5018 hns3_do_stop(struct hns3_adapter *hns)
5019 {
5020         struct hns3_hw *hw = &hns->hw;
5021         int ret;
5022
5023         ret = hns3_cfg_mac_mode(hw, false);
5024         if (ret)
5025                 return ret;
5026         hw->mac.link_status = ETH_LINK_DOWN;
5027
5028         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
5029                 hns3_configure_all_mac_addr(hns, true);
5030                 ret = hns3_reset_all_tqps(hns);
5031                 if (ret) {
5032                         hns3_err(hw, "failed to reset all queues ret = %d.",
5033                                  ret);
5034                         return ret;
5035                 }
5036         }
5037         hw->mac.default_addr_setted = false;
5038         return 0;
5039 }
5040
5041 static void
5042 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5043 {
5044         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5045         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5046         struct hns3_adapter *hns = dev->data->dev_private;
5047         struct hns3_hw *hw = &hns->hw;
5048         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5049         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5050         uint16_t q_id;
5051
5052         if (dev->data->dev_conf.intr_conf.rxq == 0)
5053                 return;
5054
5055         /* unmap the ring with vector */
5056         if (rte_intr_allow_others(intr_handle)) {
5057                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5058                 base = RTE_INTR_VEC_RXTX_OFFSET;
5059         }
5060         if (rte_intr_dp_is_en(intr_handle)) {
5061                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5062                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5063                                                          HNS3_RING_TYPE_RX,
5064                                                          q_id);
5065                         if (vec < base + intr_handle->nb_efd - 1)
5066                                 vec++;
5067                 }
5068         }
5069         /* Clean datapath event and queue/vec mapping */
5070         rte_intr_efd_disable(intr_handle);
5071         if (intr_handle->intr_vec) {
5072                 rte_free(intr_handle->intr_vec);
5073                 intr_handle->intr_vec = NULL;
5074         }
5075 }
5076
5077 static int
5078 hns3_dev_stop(struct rte_eth_dev *dev)
5079 {
5080         struct hns3_adapter *hns = dev->data->dev_private;
5081         struct hns3_hw *hw = &hns->hw;
5082
5083         PMD_INIT_FUNC_TRACE();
5084         dev->data->dev_started = 0;
5085
5086         hw->adapter_state = HNS3_NIC_STOPPING;
5087         hns3_set_rxtx_function(dev);
5088         rte_wmb();
5089         /* Disable datapath on secondary process. */
5090         hns3_mp_req_stop_rxtx(dev);
5091         /* Prevent crashes when queues are still in use. */
5092         rte_delay_ms(hw->tqps_num);
5093
5094         rte_spinlock_lock(&hw->lock);
5095         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5096                 hns3_tm_dev_stop_proc(hw);
5097                 hns3_stop_tqps(hw);
5098                 hns3_do_stop(hns);
5099                 hns3_unmap_rx_interrupt(dev);
5100                 hns3_dev_release_mbufs(hns);
5101                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5102         }
5103         hns3_rx_scattered_reset(dev);
5104         rte_eal_alarm_cancel(hns3_service_handler, dev);
5105         rte_spinlock_unlock(&hw->lock);
5106
5107         return 0;
5108 }
5109
5110 static int
5111 hns3_dev_close(struct rte_eth_dev *eth_dev)
5112 {
5113         struct hns3_adapter *hns = eth_dev->data->dev_private;
5114         struct hns3_hw *hw = &hns->hw;
5115         int ret = 0;
5116
5117         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5118                 rte_free(eth_dev->process_private);
5119                 eth_dev->process_private = NULL;
5120                 return 0;
5121         }
5122
5123         if (hw->adapter_state == HNS3_NIC_STARTED)
5124                 ret = hns3_dev_stop(eth_dev);
5125
5126         hw->adapter_state = HNS3_NIC_CLOSING;
5127         hns3_reset_abort(hns);
5128         hw->adapter_state = HNS3_NIC_CLOSED;
5129
5130         hns3_configure_all_mc_mac_addr(hns, true);
5131         hns3_remove_all_vlan_table(hns);
5132         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5133         hns3_uninit_pf(eth_dev);
5134         hns3_free_all_queues(eth_dev);
5135         rte_free(hw->reset.wait_data);
5136         rte_free(eth_dev->process_private);
5137         eth_dev->process_private = NULL;
5138         hns3_mp_uninit_primary();
5139         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5140
5141         return ret;
5142 }
5143
5144 static int
5145 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5146 {
5147         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5149
5150         fc_conf->pause_time = pf->pause_time;
5151
5152         /* return fc current mode */
5153         switch (hw->current_mode) {
5154         case HNS3_FC_FULL:
5155                 fc_conf->mode = RTE_FC_FULL;
5156                 break;
5157         case HNS3_FC_TX_PAUSE:
5158                 fc_conf->mode = RTE_FC_TX_PAUSE;
5159                 break;
5160         case HNS3_FC_RX_PAUSE:
5161                 fc_conf->mode = RTE_FC_RX_PAUSE;
5162                 break;
5163         case HNS3_FC_NONE:
5164         default:
5165                 fc_conf->mode = RTE_FC_NONE;
5166                 break;
5167         }
5168
5169         return 0;
5170 }
5171
5172 static void
5173 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5174 {
5175         switch (mode) {
5176         case RTE_FC_NONE:
5177                 hw->requested_mode = HNS3_FC_NONE;
5178                 break;
5179         case RTE_FC_RX_PAUSE:
5180                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5181                 break;
5182         case RTE_FC_TX_PAUSE:
5183                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5184                 break;
5185         case RTE_FC_FULL:
5186                 hw->requested_mode = HNS3_FC_FULL;
5187                 break;
5188         default:
5189                 hw->requested_mode = HNS3_FC_NONE;
5190                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5191                           "configured to RTE_FC_NONE", mode);
5192                 break;
5193         }
5194 }
5195
5196 static int
5197 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5198 {
5199         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5201         int ret;
5202
5203         if (fc_conf->high_water || fc_conf->low_water ||
5204             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5205                 hns3_err(hw, "Unsupported flow control settings specified, "
5206                          "high_water(%u), low_water(%u), send_xon(%u) and "
5207                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5208                          fc_conf->high_water, fc_conf->low_water,
5209                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5210                 return -EINVAL;
5211         }
5212         if (fc_conf->autoneg) {
5213                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5214                 return -EINVAL;
5215         }
5216         if (!fc_conf->pause_time) {
5217                 hns3_err(hw, "Invalid pause time %u setting.",
5218                          fc_conf->pause_time);
5219                 return -EINVAL;
5220         }
5221
5222         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5223             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5224                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5225                          "current_fc_status = %d", hw->current_fc_status);
5226                 return -EOPNOTSUPP;
5227         }
5228
5229         hns3_get_fc_mode(hw, fc_conf->mode);
5230         if (hw->requested_mode == hw->current_mode &&
5231             pf->pause_time == fc_conf->pause_time)
5232                 return 0;
5233
5234         rte_spinlock_lock(&hw->lock);
5235         ret = hns3_fc_enable(dev, fc_conf);
5236         rte_spinlock_unlock(&hw->lock);
5237
5238         return ret;
5239 }
5240
5241 static int
5242 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5243                             struct rte_eth_pfc_conf *pfc_conf)
5244 {
5245         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5247         uint8_t priority;
5248         int ret;
5249
5250         if (!hns3_dev_dcb_supported(hw)) {
5251                 hns3_err(hw, "This port does not support dcb configurations.");
5252                 return -EOPNOTSUPP;
5253         }
5254
5255         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5256             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5257                 hns3_err(hw, "Unsupported flow control settings specified, "
5258                          "high_water(%u), low_water(%u), send_xon(%u) and "
5259                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5260                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5261                          pfc_conf->fc.send_xon,
5262                          pfc_conf->fc.mac_ctrl_frame_fwd);
5263                 return -EINVAL;
5264         }
5265         if (pfc_conf->fc.autoneg) {
5266                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5267                 return -EINVAL;
5268         }
5269         if (pfc_conf->fc.pause_time == 0) {
5270                 hns3_err(hw, "Invalid pause time %u setting.",
5271                          pfc_conf->fc.pause_time);
5272                 return -EINVAL;
5273         }
5274
5275         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5276             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5277                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5278                              "current_fc_status = %d", hw->current_fc_status);
5279                 return -EOPNOTSUPP;
5280         }
5281
5282         priority = pfc_conf->priority;
5283         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5284         if (hw->dcb_info.pfc_en & BIT(priority) &&
5285             hw->requested_mode == hw->current_mode &&
5286             pfc_conf->fc.pause_time == pf->pause_time)
5287                 return 0;
5288
5289         rte_spinlock_lock(&hw->lock);
5290         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5291         rte_spinlock_unlock(&hw->lock);
5292
5293         return ret;
5294 }
5295
5296 static int
5297 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5298 {
5299         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5300         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5301         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5302         int i;
5303
5304         rte_spinlock_lock(&hw->lock);
5305         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5306                 dcb_info->nb_tcs = pf->local_max_tc;
5307         else
5308                 dcb_info->nb_tcs = 1;
5309
5310         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5311                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5312         for (i = 0; i < dcb_info->nb_tcs; i++)
5313                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5314
5315         for (i = 0; i < hw->num_tc; i++) {
5316                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5317                 dcb_info->tc_queue.tc_txq[0][i].base =
5318                                                 hw->tc_queue[i].tqp_offset;
5319                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5320                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5321                                                 hw->tc_queue[i].tqp_count;
5322         }
5323         rte_spinlock_unlock(&hw->lock);
5324
5325         return 0;
5326 }
5327
5328 static int
5329 hns3_reinit_dev(struct hns3_adapter *hns)
5330 {
5331         struct hns3_hw *hw = &hns->hw;
5332         int ret;
5333
5334         ret = hns3_cmd_init(hw);
5335         if (ret) {
5336                 hns3_err(hw, "Failed to init cmd: %d", ret);
5337                 return ret;
5338         }
5339
5340         ret = hns3_reset_all_tqps(hns);
5341         if (ret) {
5342                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5343                 return ret;
5344         }
5345
5346         ret = hns3_init_hardware(hns);
5347         if (ret) {
5348                 hns3_err(hw, "Failed to init hardware: %d", ret);
5349                 return ret;
5350         }
5351
5352         ret = hns3_enable_hw_error_intr(hns, true);
5353         if (ret) {
5354                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5355                              ret);
5356                 return ret;
5357         }
5358         hns3_info(hw, "Reset done, driver initialization finished.");
5359
5360         return 0;
5361 }
5362
5363 static bool
5364 is_pf_reset_done(struct hns3_hw *hw)
5365 {
5366         uint32_t val, reg, reg_bit;
5367
5368         switch (hw->reset.level) {
5369         case HNS3_IMP_RESET:
5370                 reg = HNS3_GLOBAL_RESET_REG;
5371                 reg_bit = HNS3_IMP_RESET_BIT;
5372                 break;
5373         case HNS3_GLOBAL_RESET:
5374                 reg = HNS3_GLOBAL_RESET_REG;
5375                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5376                 break;
5377         case HNS3_FUNC_RESET:
5378                 reg = HNS3_FUN_RST_ING;
5379                 reg_bit = HNS3_FUN_RST_ING_B;
5380                 break;
5381         case HNS3_FLR_RESET:
5382         default:
5383                 hns3_err(hw, "Wait for unsupported reset level: %d",
5384                          hw->reset.level);
5385                 return true;
5386         }
5387         val = hns3_read_dev(hw, reg);
5388         if (hns3_get_bit(val, reg_bit))
5389                 return false;
5390         else
5391                 return true;
5392 }
5393
5394 bool
5395 hns3_is_reset_pending(struct hns3_adapter *hns)
5396 {
5397         struct hns3_hw *hw = &hns->hw;
5398         enum hns3_reset_level reset;
5399
5400         hns3_check_event_cause(hns, NULL);
5401         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5402         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5403                 hns3_warn(hw, "High level reset %d is pending", reset);
5404                 return true;
5405         }
5406         reset = hns3_get_reset_level(hns, &hw->reset.request);
5407         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5408                 hns3_warn(hw, "High level reset %d is request", reset);
5409                 return true;
5410         }
5411         return false;
5412 }
5413
5414 static int
5415 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5416 {
5417         struct hns3_hw *hw = &hns->hw;
5418         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5419         struct timeval tv;
5420
5421         if (wait_data->result == HNS3_WAIT_SUCCESS)
5422                 return 0;
5423         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5424                 gettimeofday(&tv, NULL);
5425                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5426                           tv.tv_sec, tv.tv_usec);
5427                 return -ETIME;
5428         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5429                 return -EAGAIN;
5430
5431         wait_data->hns = hns;
5432         wait_data->check_completion = is_pf_reset_done;
5433         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5434                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5435         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5436         wait_data->count = HNS3_RESET_WAIT_CNT;
5437         wait_data->result = HNS3_WAIT_REQUEST;
5438         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5439         return -EAGAIN;
5440 }
5441
5442 static int
5443 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5444 {
5445         struct hns3_cmd_desc desc;
5446         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5447
5448         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5449         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5450         req->fun_reset_vfid = func_id;
5451
5452         return hns3_cmd_send(hw, &desc, 1);
5453 }
5454
5455 static int
5456 hns3_imp_reset_cmd(struct hns3_hw *hw)
5457 {
5458         struct hns3_cmd_desc desc;
5459
5460         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5461         desc.data[0] = 0xeedd;
5462
5463         return hns3_cmd_send(hw, &desc, 1);
5464 }
5465
5466 static void
5467 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5468 {
5469         struct hns3_hw *hw = &hns->hw;
5470         struct timeval tv;
5471         uint32_t val;
5472
5473         gettimeofday(&tv, NULL);
5474         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5475             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5476                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5477                           tv.tv_sec, tv.tv_usec);
5478                 return;
5479         }
5480
5481         switch (reset_level) {
5482         case HNS3_IMP_RESET:
5483                 hns3_imp_reset_cmd(hw);
5484                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5485                           tv.tv_sec, tv.tv_usec);
5486                 break;
5487         case HNS3_GLOBAL_RESET:
5488                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5489                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5490                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5491                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5492                           tv.tv_sec, tv.tv_usec);
5493                 break;
5494         case HNS3_FUNC_RESET:
5495                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5496                           tv.tv_sec, tv.tv_usec);
5497                 /* schedule again to check later */
5498                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5499                 hns3_schedule_reset(hns);
5500                 break;
5501         default:
5502                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5503                 return;
5504         }
5505         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5506 }
5507
5508 static enum hns3_reset_level
5509 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5510 {
5511         struct hns3_hw *hw = &hns->hw;
5512         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5513
5514         /* Return the highest priority reset level amongst all */
5515         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5516                 reset_level = HNS3_IMP_RESET;
5517         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5518                 reset_level = HNS3_GLOBAL_RESET;
5519         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5520                 reset_level = HNS3_FUNC_RESET;
5521         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5522                 reset_level = HNS3_FLR_RESET;
5523
5524         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5525                 return HNS3_NONE_RESET;
5526
5527         return reset_level;
5528 }
5529
5530 static void
5531 hns3_record_imp_error(struct hns3_adapter *hns)
5532 {
5533         struct hns3_hw *hw = &hns->hw;
5534         uint32_t reg_val;
5535
5536         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5537         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5538                 hns3_warn(hw, "Detected IMP RD poison!");
5539                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5540                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5541                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5542         }
5543
5544         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5545                 hns3_warn(hw, "Detected IMP CMDQ error!");
5546                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5547                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5548                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5549         }
5550 }
5551
5552 static int
5553 hns3_prepare_reset(struct hns3_adapter *hns)
5554 {
5555         struct hns3_hw *hw = &hns->hw;
5556         uint32_t reg_val;
5557         int ret;
5558
5559         switch (hw->reset.level) {
5560         case HNS3_FUNC_RESET:
5561                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5562                 if (ret)
5563                         return ret;
5564
5565                 /*
5566                  * After performaning pf reset, it is not necessary to do the
5567                  * mailbox handling or send any command to firmware, because
5568                  * any mailbox handling or command to firmware is only valid
5569                  * after hns3_cmd_init is called.
5570                  */
5571                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5572                 hw->reset.stats.request_cnt++;
5573                 break;
5574         case HNS3_IMP_RESET:
5575                 hns3_record_imp_error(hns);
5576                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5577                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5578                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5579                 break;
5580         default:
5581                 break;
5582         }
5583         return 0;
5584 }
5585
5586 static int
5587 hns3_set_rst_done(struct hns3_hw *hw)
5588 {
5589         struct hns3_pf_rst_done_cmd *req;
5590         struct hns3_cmd_desc desc;
5591
5592         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5594         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5595         return hns3_cmd_send(hw, &desc, 1);
5596 }
5597
5598 static int
5599 hns3_stop_service(struct hns3_adapter *hns)
5600 {
5601         struct hns3_hw *hw = &hns->hw;
5602         struct rte_eth_dev *eth_dev;
5603
5604         eth_dev = &rte_eth_devices[hw->data->port_id];
5605         if (hw->adapter_state == HNS3_NIC_STARTED) {
5606                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5607                 hns3_update_link_status_and_event(hw);
5608         }
5609         hw->mac.link_status = ETH_LINK_DOWN;
5610
5611         hns3_set_rxtx_function(eth_dev);
5612         rte_wmb();
5613         /* Disable datapath on secondary process. */
5614         hns3_mp_req_stop_rxtx(eth_dev);
5615         rte_delay_ms(hw->tqps_num);
5616
5617         rte_spinlock_lock(&hw->lock);
5618         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5619             hw->adapter_state == HNS3_NIC_STOPPING) {
5620                 hns3_enable_all_queues(hw, false);
5621                 hns3_do_stop(hns);
5622                 hw->reset.mbuf_deferred_free = true;
5623         } else
5624                 hw->reset.mbuf_deferred_free = false;
5625
5626         /*
5627          * It is cumbersome for hardware to pick-and-choose entries for deletion
5628          * from table space. Hence, for function reset software intervention is
5629          * required to delete the entries
5630          */
5631         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5632                 hns3_configure_all_mc_mac_addr(hns, true);
5633         rte_spinlock_unlock(&hw->lock);
5634
5635         return 0;
5636 }
5637
5638 static int
5639 hns3_start_service(struct hns3_adapter *hns)
5640 {
5641         struct hns3_hw *hw = &hns->hw;
5642         struct rte_eth_dev *eth_dev;
5643
5644         if (hw->reset.level == HNS3_IMP_RESET ||
5645             hw->reset.level == HNS3_GLOBAL_RESET)
5646                 hns3_set_rst_done(hw);
5647         eth_dev = &rte_eth_devices[hw->data->port_id];
5648         hns3_set_rxtx_function(eth_dev);
5649         hns3_mp_req_start_rxtx(eth_dev);
5650         if (hw->adapter_state == HNS3_NIC_STARTED) {
5651                 /*
5652                  * This API parent function already hold the hns3_hw.lock, the
5653                  * hns3_service_handler may report lse, in bonding application
5654                  * it will call driver's ops which may acquire the hns3_hw.lock
5655                  * again, thus lead to deadlock.
5656                  * We defer calls hns3_service_handler to avoid the deadlock.
5657                  */
5658                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5659                                   hns3_service_handler, eth_dev);
5660
5661                 /* Enable interrupt of all rx queues before enabling queues */
5662                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5663                 /*
5664                  * Enable state of each rxq and txq will be recovered after
5665                  * reset, so we need to restore them before enable all tqps;
5666                  */
5667                 hns3_restore_tqp_enable_state(hw);
5668                 /*
5669                  * When finished the initialization, enable queues to receive
5670                  * and transmit packets.
5671                  */
5672                 hns3_enable_all_queues(hw, true);
5673         }
5674
5675         return 0;
5676 }
5677
5678 static int
5679 hns3_restore_conf(struct hns3_adapter *hns)
5680 {
5681         struct hns3_hw *hw = &hns->hw;
5682         int ret;
5683
5684         ret = hns3_configure_all_mac_addr(hns, false);
5685         if (ret)
5686                 return ret;
5687
5688         ret = hns3_configure_all_mc_mac_addr(hns, false);
5689         if (ret)
5690                 goto err_mc_mac;
5691
5692         ret = hns3_dev_promisc_restore(hns);
5693         if (ret)
5694                 goto err_promisc;
5695
5696         ret = hns3_restore_vlan_table(hns);
5697         if (ret)
5698                 goto err_promisc;
5699
5700         ret = hns3_restore_vlan_conf(hns);
5701         if (ret)
5702                 goto err_promisc;
5703
5704         ret = hns3_restore_all_fdir_filter(hns);
5705         if (ret)
5706                 goto err_promisc;
5707
5708         ret = hns3_restore_rx_interrupt(hw);
5709         if (ret)
5710                 goto err_promisc;
5711
5712         ret = hns3_restore_gro_conf(hw);
5713         if (ret)
5714                 goto err_promisc;
5715
5716         ret = hns3_restore_fec(hw);
5717         if (ret)
5718                 goto err_promisc;
5719
5720         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5721                 ret = hns3_do_start(hns, false);
5722                 if (ret)
5723                         goto err_promisc;
5724                 hns3_info(hw, "hns3 dev restart successful!");
5725         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5726                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5727         return 0;
5728
5729 err_promisc:
5730         hns3_configure_all_mc_mac_addr(hns, true);
5731 err_mc_mac:
5732         hns3_configure_all_mac_addr(hns, true);
5733         return ret;
5734 }
5735
5736 static void
5737 hns3_reset_service(void *param)
5738 {
5739         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5740         struct hns3_hw *hw = &hns->hw;
5741         enum hns3_reset_level reset_level;
5742         struct timeval tv_delta;
5743         struct timeval tv_start;
5744         struct timeval tv;
5745         uint64_t msec;
5746         int ret;
5747
5748         /*
5749          * The interrupt is not triggered within the delay time.
5750          * The interrupt may have been lost. It is necessary to handle
5751          * the interrupt to recover from the error.
5752          */
5753         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5754                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5755                 hns3_err(hw, "Handling interrupts in delayed tasks");
5756                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5757                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5758                 if (reset_level == HNS3_NONE_RESET) {
5759                         hns3_err(hw, "No reset level is set, try IMP reset");
5760                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5761                 }
5762         }
5763         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5764
5765         /*
5766          * Check if there is any ongoing reset in the hardware. This status can
5767          * be checked from reset_pending. If there is then, we need to wait for
5768          * hardware to complete reset.
5769          *    a. If we are able to figure out in reasonable time that hardware
5770          *       has fully resetted then, we can proceed with driver, client
5771          *       reset.
5772          *    b. else, we can come back later to check this status so re-sched
5773          *       now.
5774          */
5775         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5776         if (reset_level != HNS3_NONE_RESET) {
5777                 gettimeofday(&tv_start, NULL);
5778                 ret = hns3_reset_process(hns, reset_level);
5779                 gettimeofday(&tv, NULL);
5780                 timersub(&tv, &tv_start, &tv_delta);
5781                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5782                        tv_delta.tv_usec / USEC_PER_MSEC;
5783                 if (msec > HNS3_RESET_PROCESS_MS)
5784                         hns3_err(hw, "%d handle long time delta %" PRIx64
5785                                      " ms time=%ld.%.6ld",
5786                                  hw->reset.level, msec,
5787                                  tv.tv_sec, tv.tv_usec);
5788                 if (ret == -EAGAIN)
5789                         return;
5790         }
5791
5792         /* Check if we got any *new* reset requests to be honored */
5793         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5794         if (reset_level != HNS3_NONE_RESET)
5795                 hns3_msix_process(hns, reset_level);
5796 }
5797
5798 static unsigned int
5799 hns3_get_speed_capa_num(uint16_t device_id)
5800 {
5801         unsigned int num;
5802
5803         switch (device_id) {
5804         case HNS3_DEV_ID_25GE:
5805         case HNS3_DEV_ID_25GE_RDMA:
5806                 num = 2;
5807                 break;
5808         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5809         case HNS3_DEV_ID_200G_RDMA:
5810                 num = 1;
5811                 break;
5812         default:
5813                 num = 0;
5814                 break;
5815         }
5816
5817         return num;
5818 }
5819
5820 static int
5821 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5822                         uint16_t device_id)
5823 {
5824         switch (device_id) {
5825         case HNS3_DEV_ID_25GE:
5826         /* fallthrough */
5827         case HNS3_DEV_ID_25GE_RDMA:
5828                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5829                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5830
5831                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5832                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5833                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5834                 break;
5835         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5836                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5837                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5838                 break;
5839         case HNS3_DEV_ID_200G_RDMA:
5840                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5841                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5842                 break;
5843         default:
5844                 return -ENOTSUP;
5845         }
5846
5847         return 0;
5848 }
5849
5850 static int
5851 hns3_fec_get_capability(struct rte_eth_dev *dev,
5852                         struct rte_eth_fec_capa *speed_fec_capa,
5853                         unsigned int num)
5854 {
5855         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5857         uint16_t device_id = pci_dev->id.device_id;
5858         unsigned int capa_num;
5859         int ret;
5860
5861         capa_num = hns3_get_speed_capa_num(device_id);
5862         if (capa_num == 0) {
5863                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5864                          device_id);
5865                 return -ENOTSUP;
5866         }
5867
5868         if (speed_fec_capa == NULL || num < capa_num)
5869                 return capa_num;
5870
5871         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5872         if (ret)
5873                 return -ENOTSUP;
5874
5875         return capa_num;
5876 }
5877
5878 static int
5879 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5880 {
5881         struct hns3_config_fec_cmd *req;
5882         struct hns3_cmd_desc desc;
5883         int ret;
5884
5885         /*
5886          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5887          * in device of link speed
5888          * below 10 Gbps.
5889          */
5890         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5891                 *state = 0;
5892                 return 0;
5893         }
5894
5895         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5896         req = (struct hns3_config_fec_cmd *)desc.data;
5897         ret = hns3_cmd_send(hw, &desc, 1);
5898         if (ret) {
5899                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5900                          ret);
5901                 return ret;
5902         }
5903
5904         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5905         return 0;
5906 }
5907
5908 static int
5909 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5910 {
5911 #define QUERY_ACTIVE_SPEED      1
5912         struct hns3_sfp_speed_cmd *resp;
5913         uint32_t tmp_fec_capa;
5914         uint8_t auto_state;
5915         struct hns3_cmd_desc desc;
5916         int ret;
5917
5918         /*
5919          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5920          * configured FEC mode is returned.
5921          * If link is up, current FEC mode is returned.
5922          */
5923         if (hw->mac.link_status == ETH_LINK_DOWN) {
5924                 ret = get_current_fec_auto_state(hw, &auto_state);
5925                 if (ret)
5926                         return ret;
5927
5928                 if (auto_state == 0x1) {
5929                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5930                         return 0;
5931                 }
5932         }
5933
5934         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5935         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5936         resp->query_type = QUERY_ACTIVE_SPEED;
5937
5938         ret = hns3_cmd_send(hw, &desc, 1);
5939         if (ret == -EOPNOTSUPP) {
5940                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5941                 return ret;
5942         } else if (ret) {
5943                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5944                 return ret;
5945         }
5946
5947         /*
5948          * FEC mode order defined in hns3 hardware is inconsistend with
5949          * that defined in the ethdev library. So the sequence needs
5950          * to be converted.
5951          */
5952         switch (resp->active_fec) {
5953         case HNS3_HW_FEC_MODE_NOFEC:
5954                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5955                 break;
5956         case HNS3_HW_FEC_MODE_BASER:
5957                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5958                 break;
5959         case HNS3_HW_FEC_MODE_RS:
5960                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5961                 break;
5962         default:
5963                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5964                 break;
5965         }
5966
5967         *fec_capa = tmp_fec_capa;
5968         return 0;
5969 }
5970
5971 static int
5972 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5973 {
5974         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5975
5976         return hns3_fec_get_internal(hw, fec_capa);
5977 }
5978
5979 static int
5980 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5981 {
5982         struct hns3_config_fec_cmd *req;
5983         struct hns3_cmd_desc desc;
5984         int ret;
5985
5986         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5987
5988         req = (struct hns3_config_fec_cmd *)desc.data;
5989         switch (mode) {
5990         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5991                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5992                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5993                 break;
5994         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5995                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5996                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5997                 break;
5998         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5999                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6000                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6001                 break;
6002         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6003                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6004                 break;
6005         default:
6006                 return 0;
6007         }
6008         ret = hns3_cmd_send(hw, &desc, 1);
6009         if (ret)
6010                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6011
6012         return ret;
6013 }
6014
6015 static uint32_t
6016 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6017 {
6018         struct hns3_mac *mac = &hw->mac;
6019         uint32_t cur_capa;
6020
6021         switch (mac->link_speed) {
6022         case ETH_SPEED_NUM_10G:
6023                 cur_capa = fec_capa[1].capa;
6024                 break;
6025         case ETH_SPEED_NUM_25G:
6026         case ETH_SPEED_NUM_100G:
6027         case ETH_SPEED_NUM_200G:
6028                 cur_capa = fec_capa[0].capa;
6029                 break;
6030         default:
6031                 cur_capa = 0;
6032                 break;
6033         }
6034
6035         return cur_capa;
6036 }
6037
6038 static bool
6039 is_fec_mode_one_bit_set(uint32_t mode)
6040 {
6041         int cnt = 0;
6042         uint8_t i;
6043
6044         for (i = 0; i < sizeof(mode); i++)
6045                 if (mode >> i & 0x1)
6046                         cnt++;
6047
6048         return cnt == 1 ? true : false;
6049 }
6050
6051 static int
6052 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6053 {
6054 #define FEC_CAPA_NUM 2
6055         struct hns3_adapter *hns = dev->data->dev_private;
6056         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6057         struct hns3_pf *pf = &hns->pf;
6058
6059         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6060         uint32_t cur_capa;
6061         uint32_t num = FEC_CAPA_NUM;
6062         int ret;
6063
6064         ret = hns3_fec_get_capability(dev, fec_capa, num);
6065         if (ret < 0)
6066                 return ret;
6067
6068         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6069         if (!is_fec_mode_one_bit_set(mode))
6070                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6071                              "FEC mode should be only one bit set", mode);
6072
6073         /*
6074          * Check whether the configured mode is within the FEC capability.
6075          * If not, the configured mode will not be supported.
6076          */
6077         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6078         if (!(cur_capa & mode)) {
6079                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6080                 return -EINVAL;
6081         }
6082
6083         ret = hns3_set_fec_hw(hw, mode);
6084         if (ret)
6085                 return ret;
6086
6087         pf->fec_mode = mode;
6088         return 0;
6089 }
6090
6091 static int
6092 hns3_restore_fec(struct hns3_hw *hw)
6093 {
6094         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6095         struct hns3_pf *pf = &hns->pf;
6096         uint32_t mode = pf->fec_mode;
6097         int ret;
6098
6099         ret = hns3_set_fec_hw(hw, mode);
6100         if (ret)
6101                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6102                          mode, ret);
6103
6104         return ret;
6105 }
6106
6107 static int
6108 hns3_query_dev_fec_info(struct hns3_hw *hw)
6109 {
6110         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6111         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6112         int ret;
6113
6114         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6115         if (ret)
6116                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6117
6118         return ret;
6119 }
6120
6121 static const struct eth_dev_ops hns3_eth_dev_ops = {
6122         .dev_configure      = hns3_dev_configure,
6123         .dev_start          = hns3_dev_start,
6124         .dev_stop           = hns3_dev_stop,
6125         .dev_close          = hns3_dev_close,
6126         .promiscuous_enable = hns3_dev_promiscuous_enable,
6127         .promiscuous_disable = hns3_dev_promiscuous_disable,
6128         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6129         .allmulticast_disable = hns3_dev_allmulticast_disable,
6130         .mtu_set            = hns3_dev_mtu_set,
6131         .stats_get          = hns3_stats_get,
6132         .stats_reset        = hns3_stats_reset,
6133         .xstats_get         = hns3_dev_xstats_get,
6134         .xstats_get_names   = hns3_dev_xstats_get_names,
6135         .xstats_reset       = hns3_dev_xstats_reset,
6136         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6137         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6138         .dev_infos_get          = hns3_dev_infos_get,
6139         .fw_version_get         = hns3_fw_version_get,
6140         .rx_queue_setup         = hns3_rx_queue_setup,
6141         .tx_queue_setup         = hns3_tx_queue_setup,
6142         .rx_queue_release       = hns3_dev_rx_queue_release,
6143         .tx_queue_release       = hns3_dev_tx_queue_release,
6144         .rx_queue_start         = hns3_dev_rx_queue_start,
6145         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6146         .tx_queue_start         = hns3_dev_tx_queue_start,
6147         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6148         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6149         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6150         .rxq_info_get           = hns3_rxq_info_get,
6151         .txq_info_get           = hns3_txq_info_get,
6152         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6153         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6154         .flow_ctrl_get          = hns3_flow_ctrl_get,
6155         .flow_ctrl_set          = hns3_flow_ctrl_set,
6156         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6157         .mac_addr_add           = hns3_add_mac_addr,
6158         .mac_addr_remove        = hns3_remove_mac_addr,
6159         .mac_addr_set           = hns3_set_default_mac_addr,
6160         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6161         .link_update            = hns3_dev_link_update,
6162         .rss_hash_update        = hns3_dev_rss_hash_update,
6163         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6164         .reta_update            = hns3_dev_rss_reta_update,
6165         .reta_query             = hns3_dev_rss_reta_query,
6166         .filter_ctrl            = hns3_dev_filter_ctrl,
6167         .vlan_filter_set        = hns3_vlan_filter_set,
6168         .vlan_tpid_set          = hns3_vlan_tpid_set,
6169         .vlan_offload_set       = hns3_vlan_offload_set,
6170         .vlan_pvid_set          = hns3_vlan_pvid_set,
6171         .get_reg                = hns3_get_regs,
6172         .get_dcb_info           = hns3_get_dcb_info,
6173         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6174         .fec_get_capability     = hns3_fec_get_capability,
6175         .fec_get                = hns3_fec_get,
6176         .fec_set                = hns3_fec_set,
6177         .tm_ops_get             = hns3_tm_ops_get,
6178 };
6179
6180 static const struct hns3_reset_ops hns3_reset_ops = {
6181         .reset_service       = hns3_reset_service,
6182         .stop_service        = hns3_stop_service,
6183         .prepare_reset       = hns3_prepare_reset,
6184         .wait_hardware_ready = hns3_wait_hardware_ready,
6185         .reinit_dev          = hns3_reinit_dev,
6186         .restore_conf        = hns3_restore_conf,
6187         .start_service       = hns3_start_service,
6188 };
6189
6190 static int
6191 hns3_dev_init(struct rte_eth_dev *eth_dev)
6192 {
6193         struct hns3_adapter *hns = eth_dev->data->dev_private;
6194         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6195         struct rte_ether_addr *eth_addr;
6196         struct hns3_hw *hw = &hns->hw;
6197         int ret;
6198
6199         PMD_INIT_FUNC_TRACE();
6200
6201         eth_dev->process_private = (struct hns3_process_private *)
6202             rte_zmalloc_socket("hns3_filter_list",
6203                                sizeof(struct hns3_process_private),
6204                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6205         if (eth_dev->process_private == NULL) {
6206                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6207                 return -ENOMEM;
6208         }
6209         /* initialize flow filter lists */
6210         hns3_filterlist_init(eth_dev);
6211
6212         hns3_set_rxtx_function(eth_dev);
6213         eth_dev->dev_ops = &hns3_eth_dev_ops;
6214         eth_dev->rx_queue_count = hns3_rx_queue_count;
6215         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6216                 ret = hns3_mp_init_secondary();
6217                 if (ret) {
6218                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6219                                      "process, ret = %d", ret);
6220                         goto err_mp_init_secondary;
6221                 }
6222
6223                 hw->secondary_cnt++;
6224                 return 0;
6225         }
6226
6227         ret = hns3_mp_init_primary();
6228         if (ret) {
6229                 PMD_INIT_LOG(ERR,
6230                              "Failed to init for primary process, ret = %d",
6231                              ret);
6232                 goto err_mp_init_primary;
6233         }
6234
6235         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6236         hns->is_vf = false;
6237         hw->data = eth_dev->data;
6238
6239         /*
6240          * Set default max packet size according to the mtu
6241          * default vale in DPDK frame.
6242          */
6243         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6244
6245         ret = hns3_reset_init(hw);
6246         if (ret)
6247                 goto err_init_reset;
6248         hw->reset.ops = &hns3_reset_ops;
6249
6250         ret = hns3_init_pf(eth_dev);
6251         if (ret) {
6252                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6253                 goto err_init_pf;
6254         }
6255
6256         /* Allocate memory for storing MAC addresses */
6257         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6258                                                sizeof(struct rte_ether_addr) *
6259                                                HNS3_UC_MACADDR_NUM, 0);
6260         if (eth_dev->data->mac_addrs == NULL) {
6261                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6262                              "to store MAC addresses",
6263                              sizeof(struct rte_ether_addr) *
6264                              HNS3_UC_MACADDR_NUM);
6265                 ret = -ENOMEM;
6266                 goto err_rte_zmalloc;
6267         }
6268
6269         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6270         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6271                 rte_eth_random_addr(hw->mac.mac_addr);
6272                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6273                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6274                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6275                           "unicast address, using random MAC address %s",
6276                           mac_str);
6277         }
6278         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6279                             &eth_dev->data->mac_addrs[0]);
6280
6281         hw->adapter_state = HNS3_NIC_INITIALIZED;
6282
6283         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6284                 hns3_err(hw, "Reschedule reset service after dev_init");
6285                 hns3_schedule_reset(hns);
6286         } else {
6287                 /* IMP will wait ready flag before reset */
6288                 hns3_notify_reset_ready(hw, false);
6289         }
6290
6291         hns3_info(hw, "hns3 dev initialization successful!");
6292         return 0;
6293
6294 err_rte_zmalloc:
6295         hns3_uninit_pf(eth_dev);
6296
6297 err_init_pf:
6298         rte_free(hw->reset.wait_data);
6299
6300 err_init_reset:
6301         hns3_mp_uninit_primary();
6302
6303 err_mp_init_primary:
6304 err_mp_init_secondary:
6305         eth_dev->dev_ops = NULL;
6306         eth_dev->rx_pkt_burst = NULL;
6307         eth_dev->tx_pkt_burst = NULL;
6308         eth_dev->tx_pkt_prepare = NULL;
6309         rte_free(eth_dev->process_private);
6310         eth_dev->process_private = NULL;
6311         return ret;
6312 }
6313
6314 static int
6315 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6316 {
6317         struct hns3_adapter *hns = eth_dev->data->dev_private;
6318         struct hns3_hw *hw = &hns->hw;
6319
6320         PMD_INIT_FUNC_TRACE();
6321
6322         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6323                 rte_free(eth_dev->process_private);
6324                 eth_dev->process_private = NULL;
6325                 return 0;
6326         }
6327
6328         if (hw->adapter_state < HNS3_NIC_CLOSING)
6329                 hns3_dev_close(eth_dev);
6330
6331         hw->adapter_state = HNS3_NIC_REMOVED;
6332         return 0;
6333 }
6334
6335 static int
6336 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6337                    struct rte_pci_device *pci_dev)
6338 {
6339         return rte_eth_dev_pci_generic_probe(pci_dev,
6340                                              sizeof(struct hns3_adapter),
6341                                              hns3_dev_init);
6342 }
6343
6344 static int
6345 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6346 {
6347         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6348 }
6349
6350 static const struct rte_pci_id pci_id_hns3_map[] = {
6351         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6352         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6353         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6354         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6355         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6356         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6357         { .vendor_id = 0, }, /* sentinel */
6358 };
6359
6360 static struct rte_pci_driver rte_hns3_pmd = {
6361         .id_table = pci_id_hns3_map,
6362         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6363         .probe = eth_hns3_pci_probe,
6364         .remove = eth_hns3_pci_remove,
6365 };
6366
6367 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6368 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6369 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6370 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6371 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);