drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_pf *pf = &hns->pf;
 312         uint16_t vlan_id;
 313         int ret = 0;
 314
 315         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 316                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 317                                                1);
 318                 return ret;
 319         }
 320
 321         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 322                 if (vlan_entry->hd_tbl_status) {
 323                         vlan_id = vlan_entry->vlan_id;
 324                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 325                         if (ret)
 326                                 break;
 327                 }
 328         }
 329
 330         return ret;
 331 }
 332
 333 static int
 334 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 335 {
 336         struct hns3_pf *pf = &hns->pf;
 337         bool writen_to_tbl = false;
 338         int ret = 0;
 339
 340         /*
 341          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 342          * for normal packet, deleting vlan id 0 is not allowed.
 343          */
 344         if (on == 0 && vlan_id == 0)
 345                 return 0;
 346
 347         /*
 348          * When port base vlan enabled, we use port base vlan as the vlan
 349          * filter condition. In this case, we don't update vlan filter table
 350          * when user add new vlan or remove exist vlan, just update the
 351          * vlan list. The vlan id in vlan list will be writen in vlan filter
 352          * table until port base vlan disabled
 353          */
 354         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 355                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 356                 writen_to_tbl = true;
 357         }
 358
 359         if (ret == 0 && vlan_id) {
 360                 if (on)
 361                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 362                 else
 363                         hns3_rm_dev_vlan_table(hns, vlan_id);
 364         }
 365         return ret;
 366 }
 367
 368 static int
 369 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 370 {
 371         struct hns3_adapter *hns = dev->data->dev_private;
 372         struct hns3_hw *hw = &hns->hw;
 373         int ret;
 374
 375         rte_spinlock_lock(&hw->lock);
 376         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 377         rte_spinlock_unlock(&hw->lock);
 378         return ret;
 379 }
 380
 381 static int
 382 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 383                          uint16_t tpid)
 384 {
 385         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 386         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 387         struct hns3_hw *hw = &hns->hw;
 388         struct hns3_cmd_desc desc;
 389         int ret;
 390
 391         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 392              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 393                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 394                 return -EINVAL;
 395         }
 396
 397         if (tpid != RTE_ETHER_TYPE_VLAN) {
 398                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 399                 return -EINVAL;
 400         }
 401
 402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 403         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 404
 405         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 406                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 407                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 408         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 412                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 413         }
 414
 415         ret = hns3_cmd_send(hw, &desc, 1);
 416         if (ret) {
 417                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 418                          ret);
 419                 return ret;
 420         }
 421
 422         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 423
 424         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 425         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 426         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 427
 428         ret = hns3_cmd_send(hw, &desc, 1);
 429         if (ret)
 430                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 431                          ret);
 432         return ret;
 433 }
 434
 435 static int
 436 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 437                    uint16_t tpid)
 438 {
 439         struct hns3_adapter *hns = dev->data->dev_private;
 440         struct hns3_hw *hw = &hns->hw;
 441         int ret;
 442
 443         rte_spinlock_lock(&hw->lock);
 444         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 445         rte_spinlock_unlock(&hw->lock);
 446         return ret;
 447 }
 448
 449 static int
 450 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 451                              struct hns3_rx_vtag_cfg *vcfg)
 452 {
 453         struct hns3_vport_vtag_rx_cfg_cmd *req;
 454         struct hns3_hw *hw = &hns->hw;
 455         struct hns3_cmd_desc desc;
 456         uint16_t vport_id;
 457         uint8_t bitmap;
 458         int ret;
 459
 460         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 461
 462         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 464                      vcfg->strip_tag1_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 466                      vcfg->strip_tag2_en ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 468                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 469         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 470                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 471
 472         /*
 473          * In current version VF is not supported when PF is driven by DPDK
 474          * driver, the PF-related vf_id is 0, just need to configure parameters
 475          * for vport_id 0.
 476          */
 477         vport_id = 0;
 478         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 479         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 480         req->vf_bitmap[req->vf_offset] = bitmap;
 481
 482         ret = hns3_cmd_send(hw, &desc, 1);
 483         if (ret)
 484                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 485         return ret;
 486 }
 487
 488 static void
 489 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 490                            struct hns3_rx_vtag_cfg *vcfg)
 491 {
 492         struct hns3_pf *pf = &hns->pf;
 493         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 494 }
 495
 496 static void
 497 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 498                            struct hns3_tx_vtag_cfg *vcfg)
 499 {
 500         struct hns3_pf *pf = &hns->pf;
 501         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 502 }
 503
 504 static int
 505 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 506 {
 507         struct hns3_rx_vtag_cfg rxvlan_cfg;
 508         struct hns3_pf *pf = &hns->pf;
 509         struct hns3_hw *hw = &hns->hw;
 510         int ret;
 511
 512         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 513                 rxvlan_cfg.strip_tag1_en = false;
 514                 rxvlan_cfg.strip_tag2_en = enable;
 515         } else {
 516                 rxvlan_cfg.strip_tag1_en = enable;
 517                 rxvlan_cfg.strip_tag2_en = true;
 518         }
 519
 520         rxvlan_cfg.vlan1_vlan_prionly = false;
 521         rxvlan_cfg.vlan2_vlan_prionly = false;
 522         rxvlan_cfg.rx_vlan_offload_en = enable;
 523
 524         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 525         if (ret) {
 526                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 527                 return ret;
 528         }
 529
 530         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 531
 532         return ret;
 533 }
 534
 535 static int
 536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 537                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 538 {
 539         struct hns3_vlan_filter_ctrl_cmd *req;
 540         struct hns3_cmd_desc desc;
 541         int ret;
 542
 543         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 544
 545         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 546         req->vlan_type = vlan_type;
 547         req->vlan_fe = filter_en ? fe_type : 0;
 548         req->vf_id = vf_id;
 549
 550         ret = hns3_cmd_send(hw, &desc, 1);
 551         if (ret)
 552                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 553
 554         return ret;
 555 }
 556
 557 static int
 558 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 559 {
 560         struct hns3_hw *hw = &hns->hw;
 561         int ret;
 562
 563         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 564                                         HNS3_FILTER_FE_EGRESS, false, 0);
 565         if (ret) {
 566                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 567                 return ret;
 568         }
 569
 570         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 571                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 572         if (ret)
 573                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 574
 575         return ret;
 576 }
 577
 578 static int
 579 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 580 {
 581         struct hns3_adapter *hns = dev->data->dev_private;
 582         struct hns3_hw *hw = &hns->hw;
 583         struct rte_eth_rxmode *rxmode;
 584         unsigned int tmp_mask;
 585         bool enable;
 586         int ret = 0;
 587
 588         rte_spinlock_lock(&hw->lock);
 589         rxmode = &dev->data->dev_conf.rxmode;
 590         tmp_mask = (unsigned int)mask;
 591         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 592                 /* Enable or disable VLAN stripping */
 593                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 594                     true : false;
 595
 596                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 597                 if (ret) {
 598                         rte_spinlock_unlock(&hw->lock);
 599                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 600                         return ret;
 601                 }
 602         }
 603
 604         rte_spinlock_unlock(&hw->lock);
 605
 606         return ret;
 607 }
 608
 609 static int
 610 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 611                              struct hns3_tx_vtag_cfg *vcfg)
 612 {
 613         struct hns3_vport_vtag_tx_cfg_cmd *req;
 614         struct hns3_cmd_desc desc;
 615         struct hns3_hw *hw = &hns->hw;
 616         uint16_t vport_id;
 617         uint8_t bitmap;
 618         int ret;
 619
 620         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 621
 622         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 623         req->def_vlan_tag1 = vcfg->default_tag1;
 624         req->def_vlan_tag2 = vcfg->default_tag2;
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 626                      vcfg->accept_tag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 628                      vcfg->accept_untag1 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 630                      vcfg->accept_tag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 632                      vcfg->accept_untag2 ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 634                      vcfg->insert_tag1_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 636                      vcfg->insert_tag2_en ? 1 : 0);
 637         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 638
 639         /*
 640          * In current version VF is not supported when PF is driven by DPDK
 641          * driver, the PF-related vf_id is 0, just need to configure parameters
 642          * for vport_id 0.
 643          */
 644         vport_id = 0;
 645         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 646         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 647         req->vf_bitmap[req->vf_offset] = bitmap;
 648
 649         ret = hns3_cmd_send(hw, &desc, 1);
 650         if (ret)
 651                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 658                      uint16_t pvid)
 659 {
 660         struct hns3_hw *hw = &hns->hw;
 661         struct hns3_tx_vtag_cfg txvlan_cfg;
 662         int ret;
 663
 664         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 665                 txvlan_cfg.accept_tag1 = true;
 666                 txvlan_cfg.insert_tag1_en = false;
 667                 txvlan_cfg.default_tag1 = 0;
 668         } else {
 669                 txvlan_cfg.accept_tag1 = false;
 670                 txvlan_cfg.insert_tag1_en = true;
 671                 txvlan_cfg.default_tag1 = pvid;
 672         }
 673
 674         txvlan_cfg.accept_untag1 = true;
 675         txvlan_cfg.accept_tag2 = true;
 676         txvlan_cfg.accept_untag2 = true;
 677         txvlan_cfg.insert_tag2_en = false;
 678         txvlan_cfg.default_tag2 = 0;
 679
 680         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 681         if (ret) {
 682                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 683                          ret);
 684                 return ret;
 685         }
 686
 687         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 688         return ret;
 689 }
 690
 691 static void
 692 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 693 {
 694         struct hns3_pf *pf = &hns->pf;
 695
 696         pf->port_base_vlan_cfg.state = on ?
 697             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 698
 699         pf->port_base_vlan_cfg.pvid = pvid;
 700 }
 701
 702 static void
 703 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 704 {
 705         struct hns3_user_vlan_table *vlan_entry;
 706         struct hns3_pf *pf = &hns->pf;
 707
 708         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 709                 if (vlan_entry->hd_tbl_status)
 710                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 711
 712                 vlan_entry->hd_tbl_status = false;
 713         }
 714
 715         if (is_del_list) {
 716                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 717                 while (vlan_entry) {
 718                         LIST_REMOVE(vlan_entry, next);
 719                         rte_free(vlan_entry);
 720                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 721                 }
 722         }
 723 }
 724
 725 static void
 726 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 727 {
 728         struct hns3_user_vlan_table *vlan_entry;
 729         struct hns3_pf *pf = &hns->pf;
 730
 731         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 732                 if (!vlan_entry->hd_tbl_status)
 733                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 734
 735                 vlan_entry->hd_tbl_status = true;
 736         }
 737 }
 738
 739 static void
 740 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 741 {
 742         struct hns3_hw *hw = &hns->hw;
 743         struct hns3_pf *pf = &hns->pf;
 744         int ret;
 745
 746         hns3_rm_all_vlan_table(hns, true);
 747         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 748                 ret = hns3_set_port_vlan_filter(hns,
 749                                                 pf->port_base_vlan_cfg.pvid, 0);
 750                 if (ret) {
 751                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 752                                  ret);
 753                         return;
 754                 }
 755         }
 756 }
 757
 758 static int
 759 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 760                                 uint16_t port_base_vlan_state,
 761                                 uint16_t new_pvid, uint16_t old_pvid)
 762 {
 763         struct hns3_pf *pf = &hns->pf;
 764         struct hns3_hw *hw = &hns->hw;
 765         int ret = 0;
 766
 767         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 768                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 769                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 770                         if (ret) {
 771                                 hns3_err(hw,
 772                                          "Failed to clear clear old pvid filter, ret =%d",
 773                                          ret);
 774                                 return ret;
 775                         }
 776                 }
 777
 778                 hns3_rm_all_vlan_table(hns, false);
 779                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 780         }
 781
 782         if (new_pvid != 0) {
 783                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 784                 if (ret) {
 785                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 786                                  ret);
 787                         return ret;
 788                 }
 789         }
 790
 791         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 792                 hns3_add_all_vlan_table(hns);
 793
 794         return ret;
 795 }
 796
 797 static int
 798 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 799 {
 800         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 801         struct hns3_hw *hw = &hns->hw;
 802         bool rx_strip_en;
 803         int ret;
 804
 805         rx_strip_en = on ? true : false;
 806         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 807         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 808         rx_vlan_cfg.vlan1_vlan_prionly = false;
 809         rx_vlan_cfg.vlan2_vlan_prionly = false;
 810         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 811
 812         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 813         if (ret) {
 814                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 815                 return ret;
 816         }
 817
 818         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 819         return ret;
 820 }
 821
 822 static int
 823 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 824 {
 825         struct hns3_pf *pf = &hns->pf;
 826         struct hns3_hw *hw = &hns->hw;
 827         uint16_t port_base_vlan_state;
 828         uint16_t old_pvid;
 829         int ret;
 830
 831         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 832                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 833                         hns3_warn(hw, "Invalid operation! As current pvid set "
 834                                   "is %u, disable pvid %u is invalid",
 835                                   pf->port_base_vlan_cfg.pvid, pvid);
 836                 return 0;
 837         }
 838
 839         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 840                                     HNS3_PORT_BASE_VLAN_DISABLE;
 841         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 842         if (ret) {
 843                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 844                 return ret;
 845         }
 846
 847         ret = hns3_en_rx_strip_all(hns, on);
 848         if (ret) {
 849                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 850                 return ret;
 851         }
 852
 853         if (pvid == HNS3_INVLID_PVID)
 854                 goto out;
 855         old_pvid = pf->port_base_vlan_cfg.pvid;
 856         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 857                                               old_pvid);
 858         if (ret) {
 859                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 860                          ret);
 861                 return ret;
 862         }
 863
 864 out:
 865         hns3_store_port_base_vlan_info(hns, pvid, on);
 866         return ret;
 867 }
 868
 869 static int
 870 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 871 {
 872         struct hns3_adapter *hns = dev->data->dev_private;
 873         struct hns3_hw *hw = &hns->hw;
 874         int ret;
 875
 876         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 877                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 878                          RTE_ETHER_MAX_VLAN_ID);
 879                 return -EINVAL;
 880         }
 881
 882         rte_spinlock_lock(&hw->lock);
 883         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 884         rte_spinlock_unlock(&hw->lock);
 885         return ret;
 886 }
 887
 888 static void
 889 init_port_base_vlan_info(struct hns3_hw *hw)
 890 {
 891         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 892         struct hns3_pf *pf = &hns->pf;
 893
 894         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 895         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 896 }
 897
 898 static int
 899 hns3_default_vlan_config(struct hns3_adapter *hns)
 900 {
 901         struct hns3_hw *hw = &hns->hw;
 902         int ret;
 903
 904         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 905         if (ret)
 906                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 907         return ret;
 908 }
 909
 910 static int
 911 hns3_init_vlan_config(struct hns3_adapter *hns)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         int ret;
 915
 916         /*
 917          * This function can be called in the initialization and reset process,
 918          * when in reset process, it means that hardware had been reseted
 919          * successfully and we need to restore the hardware configuration to
 920          * ensure that the hardware configuration remains unchanged before and
 921          * after reset.
 922          */
 923         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 924                 init_port_base_vlan_info(hw);
 925
 926         ret = hns3_enable_vlan_filter(hns, true);
 927         if (ret) {
 928                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 929                 return ret;
 930         }
 931
 932         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 933                                        RTE_ETHER_TYPE_VLAN);
 934         if (ret) {
 935                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 936                 return ret;
 937         }
 938
 939         /*
 940          * When in the reinit dev stage of the reset process, the following
 941          * vlan-related configurations may differ from those at initialization,
 942          * we will restore configurations to hardware in hns3_restore_vlan_table
 943          * and hns3_restore_vlan_conf later.
 944          */
 945         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 946                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 947                 if (ret) {
 948                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 949                         return ret;
 950                 }
 951
 952                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 953                 if (ret) {
 954                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 955                                  ret);
 956                         return ret;
 957                 }
 958         }
 959
 960         return hns3_default_vlan_config(hns);
 961 }
 962
 963 static int
 964 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 965 {
 966         struct hns3_pf *pf = &hns->pf;
 967         struct hns3_hw *hw = &hns->hw;
 968         int ret;
 969
 970         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 971         if (ret) {
 972                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 973                 return ret;
 974         }
 975
 976         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 977         if (ret)
 978                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 979
 980         return ret;
 981 }
 982
 983 static int
 984 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 985 {
 986         struct hns3_adapter *hns = dev->data->dev_private;
 987         struct rte_eth_dev_data *data = dev->data;
 988         struct rte_eth_txmode *txmode;
 989         struct hns3_hw *hw = &hns->hw;
 990         int ret;
 991
 992         txmode = &data->dev_conf.txmode;
 993         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 994                 hns3_warn(hw,
 995                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 996                           "configuration is not supported! Ignore these two "
 997                           "parameters: hw_vlan_reject_tagged(%d), "
 998                           "hw_vlan_reject_untagged(%d)",
 999                           txmode->hw_vlan_reject_tagged,
1000                           txmode->hw_vlan_reject_untagged);
1001
1002         /* Apply vlan offload setting */
1003         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1004         if (ret) {
1005                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1006                 return ret;
1007         }
1008
1009         /* Apply pvid setting */
1010         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1011                                  txmode->hw_vlan_insert_pvid);
1012         if (ret)
1013                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1014                          txmode->pvid, ret);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1021                 unsigned int tso_mss_max)
1022 {
1023         struct hns3_cfg_tso_status_cmd *req;
1024         struct hns3_cmd_desc desc;
1025         uint16_t tso_mss;
1026
1027         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1028
1029         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1030
1031         tso_mss = 0;
1032         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1033                        tso_mss_min);
1034         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1035
1036         tso_mss = 0;
1037         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1038                        tso_mss_max);
1039         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1040
1041         return hns3_cmd_send(hw, &desc, 1);
1042 }
1043
1044 int
1045 hns3_config_gro(struct hns3_hw *hw, bool en)
1046 {
1047         struct hns3_cfg_gro_status_cmd *req;
1048         struct hns3_cmd_desc desc;
1049         int ret;
1050
1051         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1052         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1053
1054         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1055
1056         ret = hns3_cmd_send(hw, &desc, 1);
1057         if (ret)
1058                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1059
1060         return ret;
1061 }
1062
1063 static int
1064 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1065                    uint16_t *allocated_size, bool is_alloc)
1066 {
1067         struct hns3_umv_spc_alc_cmd *req;
1068         struct hns3_cmd_desc desc;
1069         int ret;
1070
1071         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1072         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1073         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1074         req->space_size = rte_cpu_to_le_32(space_size);
1075
1076         ret = hns3_cmd_send(hw, &desc, 1);
1077         if (ret) {
1078                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1079                              is_alloc ? "allocate" : "free", ret);
1080                 return ret;
1081         }
1082
1083         if (is_alloc && allocated_size)
1084                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1085
1086         return 0;
1087 }
1088
1089 static int
1090 hns3_init_umv_space(struct hns3_hw *hw)
1091 {
1092         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1093         struct hns3_pf *pf = &hns->pf;
1094         uint16_t allocated_size = 0;
1095         int ret;
1096
1097         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1098                                  true);
1099         if (ret)
1100                 return ret;
1101
1102         if (allocated_size < pf->wanted_umv_size)
1103                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1104                              pf->wanted_umv_size, allocated_size);
1105
1106         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1107                                                 pf->wanted_umv_size;
1108         pf->used_umv_size = 0;
1109         return 0;
1110 }
1111
1112 static int
1113 hns3_uninit_umv_space(struct hns3_hw *hw)
1114 {
1115         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1116         struct hns3_pf *pf = &hns->pf;
1117         int ret;
1118
1119         if (pf->max_umv_size == 0)
1120                 return 0;
1121
1122         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1123         if (ret)
1124                 return ret;
1125
1126         pf->max_umv_size = 0;
1127
1128         return 0;
1129 }
1130
1131 static bool
1132 hns3_is_umv_space_full(struct hns3_hw *hw)
1133 {
1134         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1135         struct hns3_pf *pf = &hns->pf;
1136         bool is_full;
1137
1138         is_full = (pf->used_umv_size >= pf->max_umv_size);
1139
1140         return is_full;
1141 }
1142
1143 static void
1144 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1145 {
1146         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1147         struct hns3_pf *pf = &hns->pf;
1148
1149         if (is_free) {
1150                 if (pf->used_umv_size > 0)
1151                         pf->used_umv_size--;
1152         } else
1153                 pf->used_umv_size++;
1154 }
1155
1156 static void
1157 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1158                       const uint8_t *addr, bool is_mc)
1159 {
1160         const unsigned char *mac_addr = addr;
1161         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1162                             ((uint32_t)mac_addr[2] << 16) |
1163                             ((uint32_t)mac_addr[1] << 8) |
1164                             (uint32_t)mac_addr[0];
1165         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1166
1167         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1168         if (is_mc) {
1169                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1170                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1171                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1172         }
1173
1174         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1175         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1176 }
1177
1178 static int
1179 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1180                              uint8_t resp_code,
1181                              enum hns3_mac_vlan_tbl_opcode op)
1182 {
1183         if (cmdq_resp) {
1184                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1185                          cmdq_resp);
1186                 return -EIO;
1187         }
1188
1189         if (op == HNS3_MAC_VLAN_ADD) {
1190                 if (resp_code == 0 || resp_code == 1) {
1191                         return 0;
1192                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1193                         hns3_err(hw, "add mac addr failed for uc_overflow");
1194                         return -ENOSPC;
1195                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1196                         hns3_err(hw, "add mac addr failed for mc_overflow");
1197                         return -ENOSPC;
1198                 }
1199
1200                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1201                          resp_code);
1202                 return -EIO;
1203         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1204                 if (resp_code == 0) {
1205                         return 0;
1206                 } else if (resp_code == 1) {
1207                         hns3_dbg(hw, "remove mac addr failed for miss");
1208                         return -ENOENT;
1209                 }
1210
1211                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1212                          resp_code);
1213                 return -EIO;
1214         } else if (op == HNS3_MAC_VLAN_LKUP) {
1215                 if (resp_code == 0) {
1216                         return 0;
1217                 } else if (resp_code == 1) {
1218                         hns3_dbg(hw, "lookup mac addr failed for miss");
1219                         return -ENOENT;
1220                 }
1221
1222                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1223                          resp_code);
1224                 return -EIO;
1225         }
1226
1227         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1228                  op);
1229
1230         return -EINVAL;
1231 }
1232
1233 static int
1234 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1235                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1236                          struct hns3_cmd_desc *desc, bool is_mc)
1237 {
1238         uint8_t resp_code;
1239         uint16_t retval;
1240         int ret;
1241
1242         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1243         if (is_mc) {
1244                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1245                 memcpy(desc[0].data, req,
1246                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1247                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1248                                           true);
1249                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1250                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1251                                           true);
1252                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1253         } else {
1254                 memcpy(desc[0].data, req,
1255                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1256                 ret = hns3_cmd_send(hw, desc, 1);
1257         }
1258         if (ret) {
1259                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1260                          ret);
1261                 return ret;
1262         }
1263         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1264         retval = rte_le_to_cpu_16(desc[0].retval);
1265
1266         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1267                                             HNS3_MAC_VLAN_LKUP);
1268 }
1269
1270 static int
1271 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1272                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1273                       struct hns3_cmd_desc *mc_desc)
1274 {
1275         uint8_t resp_code;
1276         uint16_t retval;
1277         int cfg_status;
1278         int ret;
1279
1280         if (mc_desc == NULL) {
1281                 struct hns3_cmd_desc desc;
1282
1283                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1284                 memcpy(desc.data, req,
1285                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1286                 ret = hns3_cmd_send(hw, &desc, 1);
1287                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1288                 retval = rte_le_to_cpu_16(desc.retval);
1289
1290                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1291                                                           HNS3_MAC_VLAN_ADD);
1292         } else {
1293                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1294                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1295                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1296                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1297                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1298                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1299                 memcpy(mc_desc[0].data, req,
1300                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1301                 mc_desc[0].retval = 0;
1302                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1303                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1304                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1305
1306                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1307                                                           HNS3_MAC_VLAN_ADD);
1308         }
1309
1310         if (ret) {
1311                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1312                 return ret;
1313         }
1314
1315         return cfg_status;
1316 }
1317
1318 static int
1319 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1320                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1321 {
1322         struct hns3_cmd_desc desc;
1323         uint8_t resp_code;
1324         uint16_t retval;
1325         int ret;
1326
1327         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1328
1329         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1330
1331         ret = hns3_cmd_send(hw, &desc, 1);
1332         if (ret) {
1333                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1334                 return ret;
1335         }
1336         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1337         retval = rte_le_to_cpu_16(desc.retval);
1338
1339         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1340                                             HNS3_MAC_VLAN_REMOVE);
1341 }
1342
1343 static int
1344 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1345 {
1346         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1347         struct hns3_mac_vlan_tbl_entry_cmd req;
1348         struct hns3_pf *pf = &hns->pf;
1349         struct hns3_cmd_desc desc;
1350         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1351         uint16_t egress_port = 0;
1352         uint8_t vf_id;
1353         int ret;
1354
1355         /* check if mac addr is valid */
1356         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1357                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1358                                       mac_addr);
1359                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1360                          mac_str);
1361                 return -EINVAL;
1362         }
1363
1364         memset(&req, 0, sizeof(req));
1365
1366         /*
1367          * In current version VF is not supported when PF is driven by DPDK
1368          * driver, the PF-related vf_id is 0, just need to configure parameters
1369          * for vf_id 0.
1370          */
1371         vf_id = 0;
1372         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1373                        HNS3_MAC_EPORT_VFID_S, vf_id);
1374
1375         req.egress_port = rte_cpu_to_le_16(egress_port);
1376
1377         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1378
1379         /*
1380          * Lookup the mac address in the mac_vlan table, and add
1381          * it if the entry is inexistent. Repeated unicast entry
1382          * is not allowed in the mac vlan table.
1383          */
1384         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1385         if (ret == -ENOENT) {
1386                 if (!hns3_is_umv_space_full(hw)) {
1387                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1388                         if (!ret)
1389                                 hns3_update_umv_space(hw, false);
1390                         return ret;
1391                 }
1392
1393                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1394
1395                 return -ENOSPC;
1396         }
1397
1398         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1399
1400         /* check if we just hit the duplicate */
1401         if (ret == 0) {
1402                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1403                 return 0;
1404         }
1405
1406         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1407                  mac_str);
1408
1409         return ret;
1410 }
1411
1412 static int
1413 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1414                   uint32_t idx, __rte_unused uint32_t pool)
1415 {
1416         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1418         int ret;
1419
1420         rte_spinlock_lock(&hw->lock);
1421         ret = hns3_add_uc_addr_common(hw, mac_addr);
1422         if (ret) {
1423                 rte_spinlock_unlock(&hw->lock);
1424                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1425                                       mac_addr);
1426                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1427                 return ret;
1428         }
1429
1430         if (idx == 0)
1431                 hw->mac.default_addr_setted = true;
1432         rte_spinlock_unlock(&hw->lock);
1433
1434         return ret;
1435 }
1436
1437 static int
1438 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1439 {
1440         struct hns3_mac_vlan_tbl_entry_cmd req;
1441         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1442         int ret;
1443
1444         /* check if mac addr is valid */
1445         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1446                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1447                                       mac_addr);
1448                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1449                          mac_str);
1450                 return -EINVAL;
1451         }
1452
1453         memset(&req, 0, sizeof(req));
1454         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1455         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1456         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1457         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1458                 return 0;
1459         else if (ret == 0)
1460                 hns3_update_umv_space(hw, true);
1461
1462         return ret;
1463 }
1464
1465 static void
1466 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1467 {
1468         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1469         /* index will be checked by upper level rte interface */
1470         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1471         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1472         int ret;
1473
1474         rte_spinlock_lock(&hw->lock);
1475         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1476         if (ret) {
1477                 rte_spinlock_unlock(&hw->lock);
1478                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                       mac_addr);
1480                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1481                 return;
1482         }
1483
1484         rte_spinlock_unlock(&hw->lock);
1485 }
1486
1487 static int
1488 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1489                           struct rte_ether_addr *mac_addr)
1490 {
1491         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492         struct rte_ether_addr *oaddr;
1493         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1494         bool default_addr_setted;
1495         bool rm_succes = false;
1496         int ret, ret_val;
1497
1498         /*
1499          * It has been guaranteed that input parameter named mac_addr is valid
1500          * address in the rte layer of DPDK framework.
1501          */
1502         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1503         default_addr_setted = hw->mac.default_addr_setted;
1504         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1505                 return 0;
1506
1507         rte_spinlock_lock(&hw->lock);
1508         if (default_addr_setted) {
1509                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1510                 if (ret) {
1511                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1512                                               oaddr);
1513                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1514                                   mac_str, ret);
1515                         rm_succes = false;
1516                 } else
1517                         rm_succes = true;
1518         }
1519
1520         ret = hns3_add_uc_addr_common(hw, mac_addr);
1521         if (ret) {
1522                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1523                                       mac_addr);
1524                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1525                 goto err_add_uc_addr;
1526         }
1527
1528         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1529         if (ret) {
1530                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1531                 goto err_pause_addr_cfg;
1532         }
1533
1534         rte_ether_addr_copy(mac_addr,
1535                             (struct rte_ether_addr *)hw->mac.mac_addr);
1536         hw->mac.default_addr_setted = true;
1537         rte_spinlock_unlock(&hw->lock);
1538
1539         return 0;
1540
1541 err_pause_addr_cfg:
1542         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1543         if (ret_val) {
1544                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1545                                       mac_addr);
1546                 hns3_warn(hw,
1547                           "Failed to roll back to del setted mac addr(%s): %d",
1548                           mac_str, ret_val);
1549         }
1550
1551 err_add_uc_addr:
1552         if (rm_succes) {
1553                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1554                 if (ret_val) {
1555                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1556                                               oaddr);
1557                         hns3_warn(hw,
1558                                   "Failed to restore old uc mac addr(%s): %d",
1559                                   mac_str, ret_val);
1560                         hw->mac.default_addr_setted = false;
1561                 }
1562         }
1563         rte_spinlock_unlock(&hw->lock);
1564
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         struct hns3_hw *hw = &hns->hw;
1573         struct rte_ether_addr *addr;
1574         int err = 0;
1575         int ret;
1576         int i;
1577
1578         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1579                 addr = &hw->data->mac_addrs[i];
1580                 if (!rte_is_valid_assigned_ether_addr(addr))
1581                         continue;
1582                 if (del)
1583                         ret = hns3_remove_uc_addr_common(hw, addr);
1584                 else
1585                         ret = hns3_add_uc_addr_common(hw, addr);
1586                 if (ret) {
1587                         err = ret;
1588                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1589                                               addr);
1590                         hns3_dbg(hw,
1591                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1592                                  del ? "remove" : "restore", mac_str, ret, i);
1593                 }
1594         }
1595         return err;
1596 }
1597
1598 static void
1599 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1600 {
1601 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1602         uint8_t word_num;
1603         uint8_t bit_num;
1604
1605         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1606                 word_num = vfid / 32;
1607                 bit_num = vfid % 32;
1608                 if (clr)
1609                         desc[1].data[word_num] &=
1610                             rte_cpu_to_le_32(~(1UL << bit_num));
1611                 else
1612                         desc[1].data[word_num] |=
1613                             rte_cpu_to_le_32(1UL << bit_num);
1614         } else {
1615                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1616                 bit_num = vfid % 32;
1617                 if (clr)
1618                         desc[2].data[word_num] &=
1619                             rte_cpu_to_le_32(~(1UL << bit_num));
1620                 else
1621                         desc[2].data[word_num] |=
1622                             rte_cpu_to_le_32(1UL << bit_num);
1623         }
1624 }
1625
1626 static int
1627 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1628 {
1629         struct hns3_mac_vlan_tbl_entry_cmd req;
1630         struct hns3_cmd_desc desc[3];
1631         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1632         uint8_t vf_id;
1633         int ret;
1634
1635         /* Check if mac addr is valid */
1636         if (!rte_is_multicast_ether_addr(mac_addr)) {
1637                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1638                                       mac_addr);
1639                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1640                          mac_str);
1641                 return -EINVAL;
1642         }
1643
1644         memset(&req, 0, sizeof(req));
1645         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1646         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1647         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1648         if (ret) {
1649                 /* This mac addr do not exist, add new entry for it */
1650                 memset(desc[0].data, 0, sizeof(desc[0].data));
1651                 memset(desc[1].data, 0, sizeof(desc[0].data));
1652                 memset(desc[2].data, 0, sizeof(desc[0].data));
1653         }
1654
1655         /*
1656          * In current version VF is not supported when PF is driven by DPDK
1657          * driver, the PF-related vf_id is 0, just need to configure parameters
1658          * for vf_id 0.
1659          */
1660         vf_id = 0;
1661         hns3_update_desc_vfid(desc, vf_id, false);
1662         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1663         if (ret) {
1664                 if (ret == -ENOSPC)
1665                         hns3_err(hw, "mc mac vlan table is full");
1666                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1667                                       mac_addr);
1668                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1669         }
1670
1671         return ret;
1672 }
1673
1674 static int
1675 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1676 {
1677         struct hns3_mac_vlan_tbl_entry_cmd req;
1678         struct hns3_cmd_desc desc[3];
1679         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1680         uint8_t vf_id;
1681         int ret;
1682
1683         /* Check if mac addr is valid */
1684         if (!rte_is_multicast_ether_addr(mac_addr)) {
1685                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686                                       mac_addr);
1687                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1688                          mac_str);
1689                 return -EINVAL;
1690         }
1691
1692         memset(&req, 0, sizeof(req));
1693         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1694         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1695         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1696         if (ret == 0) {
1697                 /*
1698                  * This mac addr exist, remove this handle's VFID for it.
1699                  * In current version VF is not supported when PF is driven by
1700                  * DPDK driver, the PF-related vf_id is 0, just need to
1701                  * configure parameters for vf_id 0.
1702                  */
1703                 vf_id = 0;
1704                 hns3_update_desc_vfid(desc, vf_id, true);
1705
1706                 /* All the vfid is zero, so need to delete this entry */
1707                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1708         } else if (ret == -ENOENT) {
1709                 /* This mac addr doesn't exist. */
1710                 return 0;
1711         }
1712
1713         if (ret) {
1714                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1715                                       mac_addr);
1716                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1717         }
1718
1719         return ret;
1720 }
1721
1722 static int
1723 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1724                            struct rte_ether_addr *mc_addr_set,
1725                            uint32_t nb_mc_addr)
1726 {
1727         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728         struct rte_ether_addr *addr;
1729         uint32_t i;
1730         uint32_t j;
1731
1732         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1733                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1734                          "invalid. valid range: 0~%d",
1735                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1736                 return -EINVAL;
1737         }
1738
1739         /* Check if input mac addresses are valid */
1740         for (i = 0; i < nb_mc_addr; i++) {
1741                 addr = &mc_addr_set[i];
1742                 if (!rte_is_multicast_ether_addr(addr)) {
1743                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1744                                               addr);
1745                         hns3_err(hw,
1746                                  "Failed to set mc mac addr, addr(%s) invalid.",
1747                                  mac_str);
1748                         return -EINVAL;
1749                 }
1750
1751                 /* Check if there are duplicate addresses */
1752                 for (j = i + 1; j < nb_mc_addr; j++) {
1753                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1754                                 rte_ether_format_addr(mac_str,
1755                                                       RTE_ETHER_ADDR_FMT_SIZE,
1756                                                       addr);
1757                                 hns3_err(hw, "Failed to set mc mac addr, "
1758                                          "addrs invalid. two same addrs(%s).",
1759                                          mac_str);
1760                                 return -EINVAL;
1761                         }
1762                 }
1763         }
1764
1765         return 0;
1766 }
1767
1768 static void
1769 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1770                            struct rte_ether_addr *mc_addr_set,
1771                            int mc_addr_num,
1772                            struct rte_ether_addr *reserved_addr_list,
1773                            int *reserved_addr_num,
1774                            struct rte_ether_addr *add_addr_list,
1775                            int *add_addr_num,
1776                            struct rte_ether_addr *rm_addr_list,
1777                            int *rm_addr_num)
1778 {
1779         struct rte_ether_addr *addr;
1780         int current_addr_num;
1781         int reserved_num = 0;
1782         int add_num = 0;
1783         int rm_num = 0;
1784         int num;
1785         int i;
1786         int j;
1787         bool same_addr;
1788
1789         /* Calculate the mc mac address list that should be removed */
1790         current_addr_num = hw->mc_addrs_num;
1791         for (i = 0; i < current_addr_num; i++) {
1792                 addr = &hw->mc_addrs[i];
1793                 same_addr = false;
1794                 for (j = 0; j < mc_addr_num; j++) {
1795                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1796                                 same_addr = true;
1797                                 break;
1798                         }
1799                 }
1800
1801                 if (!same_addr) {
1802                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1803                         rm_num++;
1804                 } else {
1805                         rte_ether_addr_copy(addr,
1806                                             &reserved_addr_list[reserved_num]);
1807                         reserved_num++;
1808                 }
1809         }
1810
1811         /* Calculate the mc mac address list that should be added */
1812         for (i = 0; i < mc_addr_num; i++) {
1813                 addr = &mc_addr_set[i];
1814                 same_addr = false;
1815                 for (j = 0; j < current_addr_num; j++) {
1816                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1817                                 same_addr = true;
1818                                 break;
1819                         }
1820                 }
1821
1822                 if (!same_addr) {
1823                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1824                         add_num++;
1825                 }
1826         }
1827
1828         /* Reorder the mc mac address list maintained by driver */
1829         for (i = 0; i < reserved_num; i++)
1830                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1831
1832         for (i = 0; i < rm_num; i++) {
1833                 num = reserved_num + i;
1834                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1835         }
1836
1837         *reserved_addr_num = reserved_num;
1838         *add_addr_num = add_num;
1839         *rm_addr_num = rm_num;
1840 }
1841
1842 static int
1843 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1844                           struct rte_ether_addr *mc_addr_set,
1845                           uint32_t nb_mc_addr)
1846 {
1847         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1849         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1850         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1851         struct rte_ether_addr *addr;
1852         int reserved_addr_num;
1853         int add_addr_num;
1854         int rm_addr_num;
1855         int mc_addr_num;
1856         int num;
1857         int ret;
1858         int i;
1859
1860         /* Check if input parameters are valid */
1861         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1862         if (ret)
1863                 return ret;
1864
1865         rte_spinlock_lock(&hw->lock);
1866
1867         /*
1868          * Calculate the mc mac address lists those should be removed and be
1869          * added, Reorder the mc mac address list maintained by driver.
1870          */
1871         mc_addr_num = (int)nb_mc_addr;
1872         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1873                                    reserved_addr_list, &reserved_addr_num,
1874                                    add_addr_list, &add_addr_num,
1875                                    rm_addr_list, &rm_addr_num);
1876
1877         /* Remove mc mac addresses */
1878         for (i = 0; i < rm_addr_num; i++) {
1879                 num = rm_addr_num - i - 1;
1880                 addr = &rm_addr_list[num];
1881                 ret = hns3_remove_mc_addr(hw, addr);
1882                 if (ret) {
1883                         rte_spinlock_unlock(&hw->lock);
1884                         return ret;
1885                 }
1886                 hw->mc_addrs_num--;
1887         }
1888
1889         /* Add mc mac addresses */
1890         for (i = 0; i < add_addr_num; i++) {
1891                 addr = &add_addr_list[i];
1892                 ret = hns3_add_mc_addr(hw, addr);
1893                 if (ret) {
1894                         rte_spinlock_unlock(&hw->lock);
1895                         return ret;
1896                 }
1897
1898                 num = reserved_addr_num + i;
1899                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1900                 hw->mc_addrs_num++;
1901         }
1902         rte_spinlock_unlock(&hw->lock);
1903
1904         return 0;
1905 }
1906
1907 static int
1908 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1909 {
1910         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1911         struct hns3_hw *hw = &hns->hw;
1912         struct rte_ether_addr *addr;
1913         int err = 0;
1914         int ret;
1915         int i;
1916
1917         for (i = 0; i < hw->mc_addrs_num; i++) {
1918                 addr = &hw->mc_addrs[i];
1919                 if (!rte_is_multicast_ether_addr(addr))
1920                         continue;
1921                 if (del)
1922                         ret = hns3_remove_mc_addr(hw, addr);
1923                 else
1924                         ret = hns3_add_mc_addr(hw, addr);
1925                 if (ret) {
1926                         err = ret;
1927                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                               addr);
1929                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1930                                  del ? "Remove" : "Restore", mac_str);
1931                 }
1932         }
1933         return err;
1934 }
1935
1936 static int
1937 hns3_check_mq_mode(struct rte_eth_dev *dev)
1938 {
1939         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1940         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1941         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1943         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1944         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1945         uint8_t num_tc;
1946         int max_tc = 0;
1947         int i;
1948
1949         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1950         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1951
1952         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1953                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1954                          "rx_mq_mode = %d", rx_mq_mode);
1955                 return -EINVAL;
1956         }
1957
1958         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1959             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1960                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1961                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1962                          rx_mq_mode, tx_mq_mode);
1963                 return -EINVAL;
1964         }
1965
1966         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1967                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1968                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1969                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1970                         return -EINVAL;
1971                 }
1972
1973                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1974                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1975                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1976                                  "nb_tcs(%d) != %d or %d in rx direction.",
1977                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1978                         return -EINVAL;
1979                 }
1980
1981                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1982                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1983                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1984                         return -EINVAL;
1985                 }
1986
1987                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1988                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1989                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1990                                          "is not equal to one in tx direction.",
1991                                          i, dcb_rx_conf->dcb_tc[i]);
1992                                 return -EINVAL;
1993                         }
1994                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1995                                 max_tc = dcb_rx_conf->dcb_tc[i];
1996                 }
1997
1998                 num_tc = max_tc + 1;
1999                 if (num_tc > dcb_rx_conf->nb_tcs) {
2000                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2001                                  num_tc, dcb_rx_conf->nb_tcs);
2002                         return -EINVAL;
2003                 }
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int
2010 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2011 {
2012         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013
2014         if (!hns3_dev_dcb_supported(hw)) {
2015                 hns3_err(hw, "this port does not support dcb configurations.");
2016                 return -EOPNOTSUPP;
2017         }
2018
2019         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2020                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2021                 return -EOPNOTSUPP;
2022         }
2023
2024         /* Check multiple queue mode */
2025         return hns3_check_mq_mode(dev);
2026 }
2027
2028 static int
2029 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2030                            enum hns3_ring_type queue_type, uint16_t queue_id)
2031 {
2032         struct hns3_cmd_desc desc;
2033         struct hns3_ctrl_vector_chain_cmd *req =
2034                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2035         enum hns3_cmd_status status;
2036         enum hns3_opcode_type op;
2037         uint16_t tqp_type_and_id = 0;
2038         const char *op_str;
2039         uint16_t type;
2040         uint16_t gl;
2041
2042         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2043         hns3_cmd_setup_basic_desc(&desc, op, false);
2044         req->int_vector_id = vector_id;
2045
2046         if (queue_type == HNS3_RING_TYPE_RX)
2047                 gl = HNS3_RING_GL_RX;
2048         else
2049                 gl = HNS3_RING_GL_TX;
2050
2051         type = queue_type;
2052
2053         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2054                        type);
2055         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2056         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2057                        gl);
2058         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2059         req->int_cause_num = 1;
2060         op_str = mmap ? "Map" : "Unmap";
2061         status = hns3_cmd_send(hw, &desc, 1);
2062         if (status) {
2063                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2064                          op_str, queue_id, req->int_vector_id, status);
2065                 return status;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static int
2072 hns3_init_ring_with_vector(struct hns3_hw *hw)
2073 {
2074         uint8_t vec;
2075         int ret;
2076         int i;
2077
2078         /*
2079          * In hns3 network engine, vector 0 is always the misc interrupt of this
2080          * function, vector 1~N can be used respectively for the queues of the
2081          * function. Tx and Rx queues with the same number share the interrupt
2082          * vector. In the initialization clearing the all hardware mapping
2083          * relationship configurations between queues and interrupt vectors is
2084          * needed, so some error caused by the residual configurations, such as
2085          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2086          * constraints in hns3 hardware engine, we have to implement clearing
2087          * the mapping relationship configurations by binding all queues to the
2088          * last interrupt vector and reserving the last interrupt vector. This
2089          * method results in a decrease of the maximum queues when upper
2090          * applications call the rte_eth_dev_configure API function to enable
2091          * Rx interrupt.
2092          */
2093         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2094         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2095         for (i = 0; i < hw->intr_tqps_num; i++) {
2096                 /*
2097                  * Set gap limiter and rate limiter configuration of queue's
2098                  * interrupt.
2099                  */
2100                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2101                                        HNS3_TQP_INTR_GL_DEFAULT);
2102                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2103                                        HNS3_TQP_INTR_GL_DEFAULT);
2104                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2105
2106                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2107                                                  HNS3_RING_TYPE_TX, i);
2108                 if (ret) {
2109                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2110                                           "vector: %d, ret=%d", i, vec, ret);
2111                         return ret;
2112                 }
2113
2114                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2115                                                  HNS3_RING_TYPE_RX, i);
2116                 if (ret) {
2117                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2118                                           "vector: %d, ret=%d", i, vec, ret);
2119                         return ret;
2120                 }
2121         }
2122
2123         return 0;
2124 }
2125
2126 static int
2127 hns3_dev_configure(struct rte_eth_dev *dev)
2128 {
2129         struct hns3_adapter *hns = dev->data->dev_private;
2130         struct rte_eth_conf *conf = &dev->data->dev_conf;
2131         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2132         struct hns3_hw *hw = &hns->hw;
2133         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2136         struct rte_eth_rss_conf rss_conf;
2137         uint16_t mtu;
2138         int ret;
2139
2140         /*
2141          * Hardware does not support individually enable/disable/reset the Tx or
2142          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2143          * and Rx queues at the same time. When the numbers of Tx queues
2144          * allocated by upper applications are not equal to the numbers of Rx
2145          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2146          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2147          * these fake queues are imperceptible, and can not be used by upper
2148          * applications.
2149          */
2150         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2151         if (ret) {
2152                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2153                 return ret;
2154         }
2155
2156         hw->adapter_state = HNS3_NIC_CONFIGURING;
2157         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2158                 hns3_err(hw, "setting link speed/duplex not supported");
2159                 ret = -EINVAL;
2160                 goto cfg_err;
2161         }
2162
2163         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2164                 ret = hns3_check_dcb_cfg(dev);
2165                 if (ret)
2166                         goto cfg_err;
2167         }
2168
2169         /* When RSS is not configured, redirect the packet queue 0 */
2170         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2171                 rss_conf = conf->rx_adv_conf.rss_conf;
2172                 if (rss_conf.rss_key == NULL) {
2173                         rss_conf.rss_key = rss_cfg->key;
2174                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2175                 }
2176
2177                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2178                 if (ret)
2179                         goto cfg_err;
2180         }
2181
2182         /*
2183          * If jumbo frames are enabled, MTU needs to be refreshed
2184          * according to the maximum RX packet length.
2185          */
2186         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2187                 /*
2188                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2189                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2190                  * can safely assign to "uint16_t" type variable.
2191                  */
2192                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2193                 ret = hns3_dev_mtu_set(dev, mtu);
2194                 if (ret)
2195                         goto cfg_err;
2196                 dev->data->mtu = mtu;
2197         }
2198
2199         ret = hns3_dev_configure_vlan(dev);
2200         if (ret)
2201                 goto cfg_err;
2202
2203         hw->adapter_state = HNS3_NIC_CONFIGURED;
2204
2205         return 0;
2206
2207 cfg_err:
2208         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2209         hw->adapter_state = HNS3_NIC_INITIALIZED;
2210
2211         return ret;
2212 }
2213
2214 static int
2215 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2216 {
2217         struct hns3_config_max_frm_size_cmd *req;
2218         struct hns3_cmd_desc desc;
2219
2220         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2221
2222         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2223         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2224         req->min_frm_size = RTE_ETHER_MIN_LEN;
2225
2226         return hns3_cmd_send(hw, &desc, 1);
2227 }
2228
2229 static int
2230 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2231 {
2232         int ret;
2233
2234         ret = hns3_set_mac_mtu(hw, mps);
2235         if (ret) {
2236                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2237                 return ret;
2238         }
2239
2240         ret = hns3_buffer_alloc(hw);
2241         if (ret) {
2242                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2243                 return ret;
2244         }
2245
2246         return 0;
2247 }
2248
2249 static int
2250 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2251 {
2252         struct hns3_adapter *hns = dev->data->dev_private;
2253         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2254         struct hns3_hw *hw = &hns->hw;
2255         bool is_jumbo_frame;
2256         int ret;
2257
2258         if (dev->data->dev_started) {
2259                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2260                          "before configuration", dev->data->port_id);
2261                 return -EBUSY;
2262         }
2263
2264         rte_spinlock_lock(&hw->lock);
2265         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2266         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2267
2268         /*
2269          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2270          * assign to "uint16_t" type variable.
2271          */
2272         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2273         if (ret) {
2274                 rte_spinlock_unlock(&hw->lock);
2275                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2276                          dev->data->port_id, mtu, ret);
2277                 return ret;
2278         }
2279         hns->pf.mps = (uint16_t)frame_size;
2280         if (is_jumbo_frame)
2281                 dev->data->dev_conf.rxmode.offloads |=
2282                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2283         else
2284                 dev->data->dev_conf.rxmode.offloads &=
2285                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2286         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2287         rte_spinlock_unlock(&hw->lock);
2288
2289         return 0;
2290 }
2291
2292 static int
2293 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2294 {
2295         struct hns3_adapter *hns = eth_dev->data->dev_private;
2296         struct hns3_hw *hw = &hns->hw;
2297         uint16_t queue_num = hw->tqps_num;
2298
2299         /*
2300          * In interrupt mode, 'max_rx_queues' is set based on the number of
2301          * MSI-X interrupt resources of the hardware.
2302          */
2303         if (hw->data->dev_conf.intr_conf.rxq == 1)
2304                 queue_num = hw->intr_tqps_num;
2305
2306         info->max_rx_queues = queue_num;
2307         info->max_tx_queues = hw->tqps_num;
2308         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2309         info->min_rx_bufsize = hw->rx_buf_len;
2310         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2311         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2312         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2313                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2314                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2315                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2316                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2317                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2318                                  DEV_RX_OFFLOAD_KEEP_CRC |
2319                                  DEV_RX_OFFLOAD_SCATTER |
2320                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2321                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2322                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2323                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2324                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2325         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2326         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2327                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2328                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2329                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2330                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2331                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2332                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2333                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2334                                  DEV_TX_OFFLOAD_TCP_TSO |
2335                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2336                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2337                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2338                                  info->tx_queue_offload_capa);
2339
2340         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2341                 .nb_max = HNS3_MAX_RING_DESC,
2342                 .nb_min = HNS3_MIN_RING_DESC,
2343                 .nb_align = HNS3_ALIGN_RING_DESC,
2344         };
2345
2346         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2347                 .nb_max = HNS3_MAX_RING_DESC,
2348                 .nb_min = HNS3_MIN_RING_DESC,
2349                 .nb_align = HNS3_ALIGN_RING_DESC,
2350         };
2351
2352         info->vmdq_queue_num = 0;
2353
2354         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2355         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2356         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2357
2358         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2359         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2360         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2361         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2362         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2363         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2364
2365         return 0;
2366 }
2367
2368 static int
2369 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2370                     size_t fw_size)
2371 {
2372         struct hns3_adapter *hns = eth_dev->data->dev_private;
2373         struct hns3_hw *hw = &hns->hw;
2374         int ret;
2375
2376         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2377         ret += 1; /* add the size of '\0' */
2378         if (fw_size < (uint32_t)ret)
2379                 return ret;
2380         else
2381                 return 0;
2382 }
2383
2384 static int
2385 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2386                      __rte_unused int wait_to_complete)
2387 {
2388         struct hns3_adapter *hns = eth_dev->data->dev_private;
2389         struct hns3_hw *hw = &hns->hw;
2390         struct hns3_mac *mac = &hw->mac;
2391         struct rte_eth_link new_link;
2392
2393         if (!hns3_is_reset_pending(hns)) {
2394                 hns3_update_speed_duplex(eth_dev);
2395                 hns3_update_link_status(hw);
2396         }
2397
2398         memset(&new_link, 0, sizeof(new_link));
2399         switch (mac->link_speed) {
2400         case ETH_SPEED_NUM_10M:
2401         case ETH_SPEED_NUM_100M:
2402         case ETH_SPEED_NUM_1G:
2403         case ETH_SPEED_NUM_10G:
2404         case ETH_SPEED_NUM_25G:
2405         case ETH_SPEED_NUM_40G:
2406         case ETH_SPEED_NUM_50G:
2407         case ETH_SPEED_NUM_100G:
2408                 new_link.link_speed = mac->link_speed;
2409                 break;
2410         default:
2411                 new_link.link_speed = ETH_SPEED_NUM_100M;
2412                 break;
2413         }
2414
2415         new_link.link_duplex = mac->link_duplex;
2416         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2417         new_link.link_autoneg =
2418             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2419
2420         return rte_eth_linkstatus_set(eth_dev, &new_link);
2421 }
2422
2423 static int
2424 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2425 {
2426         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2427         struct hns3_pf *pf = &hns->pf;
2428
2429         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2430                 return -EINVAL;
2431
2432         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2433
2434         return 0;
2435 }
2436
2437 static int
2438 hns3_query_function_status(struct hns3_hw *hw)
2439 {
2440 #define HNS3_QUERY_MAX_CNT              10
2441 #define HNS3_QUERY_SLEEP_MSCOEND        1
2442         struct hns3_func_status_cmd *req;
2443         struct hns3_cmd_desc desc;
2444         int timeout = 0;
2445         int ret;
2446
2447         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2448         req = (struct hns3_func_status_cmd *)desc.data;
2449
2450         do {
2451                 ret = hns3_cmd_send(hw, &desc, 1);
2452                 if (ret) {
2453                         PMD_INIT_LOG(ERR, "query function status failed %d",
2454                                      ret);
2455                         return ret;
2456                 }
2457
2458                 /* Check pf reset is done */
2459                 if (req->pf_state)
2460                         break;
2461
2462                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2463         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2464
2465         return hns3_parse_func_status(hw, req);
2466 }
2467
2468 static int
2469 hns3_query_pf_resource(struct hns3_hw *hw)
2470 {
2471         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2472         struct hns3_pf *pf = &hns->pf;
2473         struct hns3_pf_res_cmd *req;
2474         struct hns3_cmd_desc desc;
2475         uint16_t num_msi;
2476         int ret;
2477
2478         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2479         ret = hns3_cmd_send(hw, &desc, 1);
2480         if (ret) {
2481                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2482                 return ret;
2483         }
2484
2485         req = (struct hns3_pf_res_cmd *)desc.data;
2486         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2487         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2488         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2489         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2490
2491         if (req->tx_buf_size)
2492                 pf->tx_buf_size =
2493                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2494         else
2495                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2496
2497         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2498
2499         if (req->dv_buf_size)
2500                 pf->dv_buf_size =
2501                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2502         else
2503                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2504
2505         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2506
2507         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2508                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2509         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2510
2511         return 0;
2512 }
2513
2514 static void
2515 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2516 {
2517         struct hns3_cfg_param_cmd *req;
2518         uint64_t mac_addr_tmp_high;
2519         uint64_t mac_addr_tmp;
2520         uint32_t i;
2521
2522         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2523
2524         /* get the configuration */
2525         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2526                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2527         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2528                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2529         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2530                                            HNS3_CFG_TQP_DESC_N_M,
2531                                            HNS3_CFG_TQP_DESC_N_S);
2532
2533         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534                                        HNS3_CFG_PHY_ADDR_M,
2535                                        HNS3_CFG_PHY_ADDR_S);
2536         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2537                                          HNS3_CFG_MEDIA_TP_M,
2538                                          HNS3_CFG_MEDIA_TP_S);
2539         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2540                                          HNS3_CFG_RX_BUF_LEN_M,
2541                                          HNS3_CFG_RX_BUF_LEN_S);
2542         /* get mac address */
2543         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2544         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2545                                            HNS3_CFG_MAC_ADDR_H_M,
2546                                            HNS3_CFG_MAC_ADDR_H_S);
2547
2548         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2549
2550         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2551                                             HNS3_CFG_DEFAULT_SPEED_M,
2552                                             HNS3_CFG_DEFAULT_SPEED_S);
2553         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2554                                            HNS3_CFG_RSS_SIZE_M,
2555                                            HNS3_CFG_RSS_SIZE_S);
2556
2557         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2558                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2559
2560         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2561         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2562
2563         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2564                                             HNS3_CFG_SPEED_ABILITY_M,
2565                                             HNS3_CFG_SPEED_ABILITY_S);
2566         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2567                                         HNS3_CFG_UMV_TBL_SPACE_M,
2568                                         HNS3_CFG_UMV_TBL_SPACE_S);
2569         if (!cfg->umv_space)
2570                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2571 }
2572
2573 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2574  * @hw: pointer to struct hns3_hw
2575  * @hcfg: the config structure to be getted
2576  */
2577 static int
2578 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2579 {
2580         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2581         struct hns3_cfg_param_cmd *req;
2582         uint32_t offset;
2583         uint32_t i;
2584         int ret;
2585
2586         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2587                 offset = 0;
2588                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2589                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2590                                           true);
2591                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2592                                i * HNS3_CFG_RD_LEN_BYTES);
2593                 /* Len should be divided by 4 when send to hardware */
2594                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2595                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2596                 req->offset = rte_cpu_to_le_32(offset);
2597         }
2598
2599         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2600         if (ret) {
2601                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2602                 return ret;
2603         }
2604
2605         hns3_parse_cfg(hcfg, desc);
2606
2607         return 0;
2608 }
2609
2610 static int
2611 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2612 {
2613         switch (speed_cmd) {
2614         case HNS3_CFG_SPEED_10M:
2615                 *speed = ETH_SPEED_NUM_10M;
2616                 break;
2617         case HNS3_CFG_SPEED_100M:
2618                 *speed = ETH_SPEED_NUM_100M;
2619                 break;
2620         case HNS3_CFG_SPEED_1G:
2621                 *speed = ETH_SPEED_NUM_1G;
2622                 break;
2623         case HNS3_CFG_SPEED_10G:
2624                 *speed = ETH_SPEED_NUM_10G;
2625                 break;
2626         case HNS3_CFG_SPEED_25G:
2627                 *speed = ETH_SPEED_NUM_25G;
2628                 break;
2629         case HNS3_CFG_SPEED_40G:
2630                 *speed = ETH_SPEED_NUM_40G;
2631                 break;
2632         case HNS3_CFG_SPEED_50G:
2633                 *speed = ETH_SPEED_NUM_50G;
2634                 break;
2635         case HNS3_CFG_SPEED_100G:
2636                 *speed = ETH_SPEED_NUM_100G;
2637                 break;
2638         default:
2639                 return -EINVAL;
2640         }
2641
2642         return 0;
2643 }
2644
2645 static int
2646 hns3_get_board_configuration(struct hns3_hw *hw)
2647 {
2648         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2649         struct hns3_pf *pf = &hns->pf;
2650         struct hns3_cfg cfg;
2651         int ret;
2652
2653         ret = hns3_get_board_cfg(hw, &cfg);
2654         if (ret) {
2655                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2656                 return ret;
2657         }
2658
2659         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2660                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2661                 return -EOPNOTSUPP;
2662         }
2663
2664         hw->mac.media_type = cfg.media_type;
2665         hw->rss_size_max = cfg.rss_size_max;
2666         hw->rx_buf_len = cfg.rx_buf_len;
2667         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2668         hw->mac.phy_addr = cfg.phy_addr;
2669         hw->mac.default_addr_setted = false;
2670         hw->num_tx_desc = cfg.tqp_desc_num;
2671         hw->num_rx_desc = cfg.tqp_desc_num;
2672         hw->dcb_info.num_pg = 1;
2673         hw->dcb_info.hw_pfc_map = 0;
2674
2675         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2676         if (ret) {
2677                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2678                              cfg.default_speed, ret);
2679                 return ret;
2680         }
2681
2682         pf->tc_max = cfg.tc_num;
2683         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2684                 PMD_INIT_LOG(WARNING,
2685                              "Get TC num(%u) from flash, set TC num to 1",
2686                              pf->tc_max);
2687                 pf->tc_max = 1;
2688         }
2689
2690         /* Dev does not support DCB */
2691         if (!hns3_dev_dcb_supported(hw)) {
2692                 pf->tc_max = 1;
2693                 pf->pfc_max = 0;
2694         } else
2695                 pf->pfc_max = pf->tc_max;
2696
2697         hw->dcb_info.num_tc = 1;
2698         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2699                                      hw->tqps_num / hw->dcb_info.num_tc);
2700         hns3_set_bit(hw->hw_tc_map, 0, 1);
2701         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2702
2703         pf->wanted_umv_size = cfg.umv_space;
2704
2705         return ret;
2706 }
2707
2708 static int
2709 hns3_get_configuration(struct hns3_hw *hw)
2710 {
2711         int ret;
2712
2713         ret = hns3_query_function_status(hw);
2714         if (ret) {
2715                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2716                 return ret;
2717         }
2718
2719         /* Get pf resource */
2720         ret = hns3_query_pf_resource(hw);
2721         if (ret) {
2722                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2723                 return ret;
2724         }
2725
2726         ret = hns3_get_board_configuration(hw);
2727         if (ret) {
2728                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2729                 return ret;
2730         }
2731
2732         return 0;
2733 }
2734
2735 static int
2736 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2737                       uint16_t tqp_vid, bool is_pf)
2738 {
2739         struct hns3_tqp_map_cmd *req;
2740         struct hns3_cmd_desc desc;
2741         int ret;
2742
2743         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2744
2745         req = (struct hns3_tqp_map_cmd *)desc.data;
2746         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2747         req->tqp_vf = func_id;
2748         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2749         if (!is_pf)
2750                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2751         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2752
2753         ret = hns3_cmd_send(hw, &desc, 1);
2754         if (ret)
2755                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2756
2757         return ret;
2758 }
2759
2760 static int
2761 hns3_map_tqp(struct hns3_hw *hw)
2762 {
2763         uint16_t tqps_num = hw->total_tqps_num;
2764         uint16_t func_id;
2765         uint16_t tqp_id;
2766         bool is_pf;
2767         int num;
2768         int ret;
2769         int i;
2770
2771         /*
2772          * In current version VF is not supported when PF is driven by DPDK
2773          * driver, so we allocate tqps to PF as much as possible.
2774          */
2775         tqp_id = 0;
2776         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2777         for (func_id = 0; func_id < num; func_id++) {
2778                 is_pf = func_id == 0 ? true : false;
2779                 for (i = 0;
2780                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2781                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2782                                                     is_pf);
2783                         if (ret)
2784                                 return ret;
2785                 }
2786         }
2787
2788         return 0;
2789 }
2790
2791 static int
2792 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2793 {
2794         struct hns3_config_mac_speed_dup_cmd *req;
2795         struct hns3_cmd_desc desc;
2796         int ret;
2797
2798         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2799
2800         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2801
2802         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2803
2804         switch (speed) {
2805         case ETH_SPEED_NUM_10M:
2806                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2807                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2808                 break;
2809         case ETH_SPEED_NUM_100M:
2810                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2811                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2812                 break;
2813         case ETH_SPEED_NUM_1G:
2814                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2815                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2816                 break;
2817         case ETH_SPEED_NUM_10G:
2818                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2819                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2820                 break;
2821         case ETH_SPEED_NUM_25G:
2822                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2823                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2824                 break;
2825         case ETH_SPEED_NUM_40G:
2826                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2827                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2828                 break;
2829         case ETH_SPEED_NUM_50G:
2830                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2831                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2832                 break;
2833         case ETH_SPEED_NUM_100G:
2834                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2835                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2836                 break;
2837         default:
2838                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2839                 return -EINVAL;
2840         }
2841
2842         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2843
2844         ret = hns3_cmd_send(hw, &desc, 1);
2845         if (ret)
2846                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2847
2848         return ret;
2849 }
2850
2851 static int
2852 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2853 {
2854         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2855         struct hns3_pf *pf = &hns->pf;
2856         struct hns3_priv_buf *priv;
2857         uint32_t i, total_size;
2858
2859         total_size = pf->pkt_buf_size;
2860
2861         /* alloc tx buffer for all enabled tc */
2862         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2863                 priv = &buf_alloc->priv_buf[i];
2864
2865                 if (hw->hw_tc_map & BIT(i)) {
2866                         if (total_size < pf->tx_buf_size)
2867                                 return -ENOMEM;
2868
2869                         priv->tx_buf_size = pf->tx_buf_size;
2870                 } else
2871                         priv->tx_buf_size = 0;
2872
2873                 total_size -= priv->tx_buf_size;
2874         }
2875
2876         return 0;
2877 }
2878
2879 static int
2880 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2881 {
2882 /* TX buffer size is unit by 128 byte */
2883 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2884 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2885         struct hns3_tx_buff_alloc_cmd *req;
2886         struct hns3_cmd_desc desc;
2887         uint32_t buf_size;
2888         uint32_t i;
2889         int ret;
2890
2891         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2892
2893         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2894         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2895                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2896
2897                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2898                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2899                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2900         }
2901
2902         ret = hns3_cmd_send(hw, &desc, 1);
2903         if (ret)
2904                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2905
2906         return ret;
2907 }
2908
2909 static int
2910 hns3_get_tc_num(struct hns3_hw *hw)
2911 {
2912         int cnt = 0;
2913         uint8_t i;
2914
2915         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2916                 if (hw->hw_tc_map & BIT(i))
2917                         cnt++;
2918         return cnt;
2919 }
2920
2921 static uint32_t
2922 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2923 {
2924         struct hns3_priv_buf *priv;
2925         uint32_t rx_priv = 0;
2926         int i;
2927
2928         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2929                 priv = &buf_alloc->priv_buf[i];
2930                 if (priv->enable)
2931                         rx_priv += priv->buf_size;
2932         }
2933         return rx_priv;
2934 }
2935
2936 static uint32_t
2937 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2938 {
2939         uint32_t total_tx_size = 0;
2940         uint32_t i;
2941
2942         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2943                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2944
2945         return total_tx_size;
2946 }
2947
2948 /* Get the number of pfc enabled TCs, which have private buffer */
2949 static int
2950 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2951 {
2952         struct hns3_priv_buf *priv;
2953         int cnt = 0;
2954         uint8_t i;
2955
2956         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2957                 priv = &buf_alloc->priv_buf[i];
2958                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2959                         cnt++;
2960         }
2961
2962         return cnt;
2963 }
2964
2965 /* Get the number of pfc disabled TCs, which have private buffer */
2966 static int
2967 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2968                          struct hns3_pkt_buf_alloc *buf_alloc)
2969 {
2970         struct hns3_priv_buf *priv;
2971         int cnt = 0;
2972         uint8_t i;
2973
2974         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2975                 priv = &buf_alloc->priv_buf[i];
2976                 if (hw->hw_tc_map & BIT(i) &&
2977                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2978                         cnt++;
2979         }
2980
2981         return cnt;
2982 }
2983
2984 static bool
2985 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2986                   uint32_t rx_all)
2987 {
2988         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2989         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2990         struct hns3_pf *pf = &hns->pf;
2991         uint32_t shared_buf, aligned_mps;
2992         uint32_t rx_priv;
2993         uint8_t tc_num;
2994         uint8_t i;
2995
2996         tc_num = hns3_get_tc_num(hw);
2997         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2998
2999         if (hns3_dev_dcb_supported(hw))
3000                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3001                                         pf->dv_buf_size;
3002         else
3003                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3004                                         + pf->dv_buf_size;
3005
3006         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3007         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3008                              HNS3_BUF_SIZE_UNIT);
3009
3010         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3011         if (rx_all < rx_priv + shared_std)
3012                 return false;
3013
3014         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3015         buf_alloc->s_buf.buf_size = shared_buf;
3016         if (hns3_dev_dcb_supported(hw)) {
3017                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3018                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3019                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3020                                   HNS3_BUF_SIZE_UNIT);
3021         } else {
3022                 buf_alloc->s_buf.self.high =
3023                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3024                 buf_alloc->s_buf.self.low = aligned_mps;
3025         }
3026
3027         if (hns3_dev_dcb_supported(hw)) {
3028                 hi_thrd = shared_buf - pf->dv_buf_size;
3029
3030                 if (tc_num <= NEED_RESERVE_TC_NUM)
3031                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3032                                         / BUF_MAX_PERCENT;
3033
3034                 if (tc_num)
3035                         hi_thrd = hi_thrd / tc_num;
3036
3037                 hi_thrd = max_t(uint32_t, hi_thrd,
3038                                 HNS3_BUF_MUL_BY * aligned_mps);
3039                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3040                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3041         } else {
3042                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3043                 lo_thrd = aligned_mps;
3044         }
3045
3046         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3047                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3048                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3049         }
3050
3051         return true;
3052 }
3053
3054 static bool
3055 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3056                      struct hns3_pkt_buf_alloc *buf_alloc)
3057 {
3058         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3059         struct hns3_pf *pf = &hns->pf;
3060         struct hns3_priv_buf *priv;
3061         uint32_t aligned_mps;
3062         uint32_t rx_all;
3063         uint8_t i;
3064
3065         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3066         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3067
3068         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3069                 priv = &buf_alloc->priv_buf[i];
3070
3071                 priv->enable = 0;
3072                 priv->wl.low = 0;
3073                 priv->wl.high = 0;
3074                 priv->buf_size = 0;
3075
3076                 if (!(hw->hw_tc_map & BIT(i)))
3077                         continue;
3078
3079                 priv->enable = 1;
3080                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3081                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3082                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3083                                                 HNS3_BUF_SIZE_UNIT);
3084                 } else {
3085                         priv->wl.low = 0;
3086                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3087                                         aligned_mps;
3088                 }
3089
3090                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3091         }
3092
3093         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3094 }
3095
3096 static bool
3097 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3098                              struct hns3_pkt_buf_alloc *buf_alloc)
3099 {
3100         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3101         struct hns3_pf *pf = &hns->pf;
3102         struct hns3_priv_buf *priv;
3103         int no_pfc_priv_num;
3104         uint32_t rx_all;
3105         uint8_t mask;
3106         int i;
3107
3108         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3109         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3110
3111         /* let the last to be cleared first */
3112         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3113                 priv = &buf_alloc->priv_buf[i];
3114                 mask = BIT((uint8_t)i);
3115
3116                 if (hw->hw_tc_map & mask &&
3117                     !(hw->dcb_info.hw_pfc_map & mask)) {
3118                         /* Clear the no pfc TC private buffer */
3119                         priv->wl.low = 0;
3120                         priv->wl.high = 0;
3121                         priv->buf_size = 0;
3122                         priv->enable = 0;
3123                         no_pfc_priv_num--;
3124                 }
3125
3126                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3127                     no_pfc_priv_num == 0)
3128                         break;
3129         }
3130
3131         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3132 }
3133
3134 static bool
3135 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3136                            struct hns3_pkt_buf_alloc *buf_alloc)
3137 {
3138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3139         struct hns3_pf *pf = &hns->pf;
3140         struct hns3_priv_buf *priv;
3141         uint32_t rx_all;
3142         int pfc_priv_num;
3143         uint8_t mask;
3144         int i;
3145
3146         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3147         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3148
3149         /* let the last to be cleared first */
3150         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3151                 priv = &buf_alloc->priv_buf[i];
3152                 mask = BIT((uint8_t)i);
3153
3154                 if (hw->hw_tc_map & mask &&
3155                     hw->dcb_info.hw_pfc_map & mask) {
3156                         /* Reduce the number of pfc TC with private buffer */
3157                         priv->wl.low = 0;
3158                         priv->enable = 0;
3159                         priv->wl.high = 0;
3160                         priv->buf_size = 0;
3161                         pfc_priv_num--;
3162                 }
3163                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3164                     pfc_priv_num == 0)
3165                         break;
3166         }
3167
3168         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3169 }
3170
3171 static bool
3172 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3173                           struct hns3_pkt_buf_alloc *buf_alloc)
3174 {
3175 #define COMPENSATE_BUFFER       0x3C00
3176 #define COMPENSATE_HALF_MPS_NUM 5
3177 #define PRIV_WL_GAP             0x1800
3178         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3179         struct hns3_pf *pf = &hns->pf;
3180         uint32_t tc_num = hns3_get_tc_num(hw);
3181         uint32_t half_mps = pf->mps >> 1;
3182         struct hns3_priv_buf *priv;
3183         uint32_t min_rx_priv;
3184         uint32_t rx_priv;
3185         uint8_t i;
3186
3187         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3188         if (tc_num)
3189                 rx_priv = rx_priv / tc_num;
3190
3191         if (tc_num <= NEED_RESERVE_TC_NUM)
3192                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3193
3194         /*
3195          * Minimum value of private buffer in rx direction (min_rx_priv) is
3196          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3197          * buffer if rx_priv is greater than min_rx_priv.
3198          */
3199         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3200                         COMPENSATE_HALF_MPS_NUM * half_mps;
3201         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3202         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3203
3204         if (rx_priv < min_rx_priv)
3205                 return false;
3206
3207         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3208                 priv = &buf_alloc->priv_buf[i];
3209
3210                 priv->enable = 0;
3211                 priv->wl.low = 0;
3212                 priv->wl.high = 0;
3213                 priv->buf_size = 0;
3214
3215                 if (!(hw->hw_tc_map & BIT(i)))
3216                         continue;
3217
3218                 priv->enable = 1;
3219                 priv->buf_size = rx_priv;
3220                 priv->wl.high = rx_priv - pf->dv_buf_size;
3221                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3222         }
3223
3224         buf_alloc->s_buf.buf_size = 0;
3225
3226         return true;
3227 }
3228
3229 /*
3230  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3231  * @hw: pointer to struct hns3_hw
3232  * @buf_alloc: pointer to buffer calculation data
3233  * @return: 0: calculate sucessful, negative: fail
3234  */
3235 static int
3236 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3237 {
3238         /* When DCB is not supported, rx private buffer is not allocated. */
3239         if (!hns3_dev_dcb_supported(hw)) {
3240                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3241                 struct hns3_pf *pf = &hns->pf;
3242                 uint32_t rx_all = pf->pkt_buf_size;
3243
3244                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3245                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3246                         return -ENOMEM;
3247
3248                 return 0;
3249         }
3250
3251         /*
3252          * Try to allocate privated packet buffer for all TCs without share
3253          * buffer.
3254          */
3255         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3256                 return 0;
3257
3258         /*
3259          * Try to allocate privated packet buffer for all TCs with share
3260          * buffer.
3261          */
3262         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3263                 return 0;
3264
3265         /*
3266          * For different application scenes, the enabled port number, TC number
3267          * and no_drop TC number are different. In order to obtain the better
3268          * performance, software could allocate the buffer size and configure
3269          * the waterline by tring to decrease the private buffer size according
3270          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3271          * enabled tc.
3272          */
3273         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3274                 return 0;
3275
3276         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3277                 return 0;
3278
3279         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3280                 return 0;
3281
3282         return -ENOMEM;
3283 }
3284
3285 static int
3286 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3287 {
3288         struct hns3_rx_priv_buff_cmd *req;
3289         struct hns3_cmd_desc desc;
3290         uint32_t buf_size;
3291         int ret;
3292         int i;
3293
3294         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3295         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3296
3297         /* Alloc private buffer TCs */
3298         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3299                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3300
3301                 req->buf_num[i] =
3302                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3303                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3304         }
3305
3306         buf_size = buf_alloc->s_buf.buf_size;
3307         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3308                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3309
3310         ret = hns3_cmd_send(hw, &desc, 1);
3311         if (ret)
3312                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3313
3314         return ret;
3315 }
3316
3317 static int
3318 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3319 {
3320 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3321         struct hns3_rx_priv_wl_buf *req;
3322         struct hns3_priv_buf *priv;
3323         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3324         int i, j;
3325         int ret;
3326
3327         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3328                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3329                                           false);
3330                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3331
3332                 /* The first descriptor set the NEXT bit to 1 */
3333                 if (i == 0)
3334                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3335                 else
3336                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3337
3338                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3339                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3340
3341                         priv = &buf_alloc->priv_buf[idx];
3342                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3343                                                         HNS3_BUF_UNIT_S);
3344                         req->tc_wl[j].high |=
3345                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3346                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3347                                                         HNS3_BUF_UNIT_S);
3348                         req->tc_wl[j].low |=
3349                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3350                 }
3351         }
3352
3353         /* Send 2 descriptor at one time */
3354         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3355         if (ret)
3356                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3357                              ret);
3358         return ret;
3359 }
3360
3361 static int
3362 hns3_common_thrd_config(struct hns3_hw *hw,
3363                         struct hns3_pkt_buf_alloc *buf_alloc)
3364 {
3365 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3366         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3367         struct hns3_rx_com_thrd *req;
3368         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3369         struct hns3_tc_thrd *tc;
3370         int tc_idx;
3371         int i, j;
3372         int ret;
3373
3374         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3375                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3376                                           false);
3377                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3378
3379                 /* The first descriptor set the NEXT bit to 1 */
3380                 if (i == 0)
3381                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3382                 else
3383                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3384
3385                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3386                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3387                         tc = &s_buf->tc_thrd[tc_idx];
3388
3389                         req->com_thrd[j].high =
3390                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3391                         req->com_thrd[j].high |=
3392                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3393                         req->com_thrd[j].low =
3394                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3395                         req->com_thrd[j].low |=
3396                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3397                 }
3398         }
3399
3400         /* Send 2 descriptors at one time */
3401         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3402         if (ret)
3403                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3404
3405         return ret;
3406 }
3407
3408 static int
3409 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3410 {
3411         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3412         struct hns3_rx_com_wl *req;
3413         struct hns3_cmd_desc desc;
3414         int ret;
3415
3416         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3417
3418         req = (struct hns3_rx_com_wl *)desc.data;
3419         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3420         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3421
3422         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3423         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3424
3425         ret = hns3_cmd_send(hw, &desc, 1);
3426         if (ret)
3427                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3428
3429         return ret;
3430 }
3431
3432 int
3433 hns3_buffer_alloc(struct hns3_hw *hw)
3434 {
3435         struct hns3_pkt_buf_alloc pkt_buf;
3436         int ret;
3437
3438         memset(&pkt_buf, 0, sizeof(pkt_buf));
3439         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3440         if (ret) {
3441                 PMD_INIT_LOG(ERR,
3442                              "could not calc tx buffer size for all TCs %d",
3443                              ret);
3444                 return ret;
3445         }
3446
3447         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3448         if (ret) {
3449                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3450                 return ret;
3451         }
3452
3453         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3454         if (ret) {
3455                 PMD_INIT_LOG(ERR,
3456                              "could not calc rx priv buffer size for all TCs %d",
3457                              ret);
3458                 return ret;
3459         }
3460
3461         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3462         if (ret) {
3463                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3464                 return ret;
3465         }
3466
3467         if (hns3_dev_dcb_supported(hw)) {
3468                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3469                 if (ret) {
3470                         PMD_INIT_LOG(ERR,
3471                                      "could not configure rx private waterline %d",
3472                                      ret);
3473                         return ret;
3474                 }
3475
3476                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3477                 if (ret) {
3478                         PMD_INIT_LOG(ERR,
3479                                      "could not configure common threshold %d",
3480                                      ret);
3481                         return ret;
3482                 }
3483         }
3484
3485         ret = hns3_common_wl_config(hw, &pkt_buf);
3486         if (ret)
3487                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3488                              ret);
3489
3490         return ret;
3491 }
3492
3493 static int
3494 hns3_mac_init(struct hns3_hw *hw)
3495 {
3496         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3497         struct hns3_mac *mac = &hw->mac;
3498         struct hns3_pf *pf = &hns->pf;
3499         int ret;
3500
3501         pf->support_sfp_query = true;
3502         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3503         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3504         if (ret) {
3505                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3506                 return ret;
3507         }
3508
3509         mac->link_status = ETH_LINK_DOWN;
3510
3511         return hns3_config_mtu(hw, pf->mps);
3512 }
3513
3514 static int
3515 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3516 {
3517 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3518 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3519 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3520 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3521         int return_status;
3522
3523         if (cmdq_resp) {
3524                 PMD_INIT_LOG(ERR,
3525                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3526                              cmdq_resp);
3527                 return -EIO;
3528         }
3529
3530         switch (resp_code) {
3531         case HNS3_ETHERTYPE_SUCCESS_ADD:
3532         case HNS3_ETHERTYPE_ALREADY_ADD:
3533                 return_status = 0;
3534                 break;
3535         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3536                 PMD_INIT_LOG(ERR,
3537                              "add mac ethertype failed for manager table overflow.");
3538                 return_status = -EIO;
3539                 break;
3540         case HNS3_ETHERTYPE_KEY_CONFLICT:
3541                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3542                 return_status = -EIO;
3543                 break;
3544         default:
3545                 PMD_INIT_LOG(ERR,
3546                              "add mac ethertype failed for undefined, code=%d.",
3547                              resp_code);
3548                 return_status = -EIO;
3549         }
3550
3551         return return_status;
3552 }
3553
3554 static int
3555 hns3_add_mgr_tbl(struct hns3_hw *hw,
3556                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3557 {
3558         struct hns3_cmd_desc desc;
3559         uint8_t resp_code;
3560         uint16_t retval;
3561         int ret;
3562
3563         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3564         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3565
3566         ret = hns3_cmd_send(hw, &desc, 1);
3567         if (ret) {
3568                 PMD_INIT_LOG(ERR,
3569                              "add mac ethertype failed for cmd_send, ret =%d.",
3570                              ret);
3571                 return ret;
3572         }
3573
3574         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3575         retval = rte_le_to_cpu_16(desc.retval);
3576
3577         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3578 }
3579
3580 static void
3581 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3582                      int *table_item_num)
3583 {
3584         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3585
3586         /*
3587          * In current version, we add one item in management table as below:
3588          * 0x0180C200000E -- LLDP MC address
3589          */
3590         tbl = mgr_table;
3591         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3592         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3593         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3594         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3595         tbl->i_port_bitmap = 0x1;
3596         *table_item_num = 1;
3597 }
3598
3599 static int
3600 hns3_init_mgr_tbl(struct hns3_hw *hw)
3601 {
3602 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3603         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3604         int table_item_num;
3605         int ret;
3606         int i;
3607
3608         memset(mgr_table, 0, sizeof(mgr_table));
3609         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3610         for (i = 0; i < table_item_num; i++) {
3611                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3612                 if (ret) {
3613                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3614                                      ret);
3615                         return ret;
3616                 }
3617         }
3618
3619         return 0;
3620 }
3621
3622 static void
3623 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3624                         bool en_mc, bool en_bc, int vport_id)
3625 {
3626         if (!param)
3627                 return;
3628
3629         memset(param, 0, sizeof(struct hns3_promisc_param));
3630         if (en_uc)
3631                 param->enable = HNS3_PROMISC_EN_UC;
3632         if (en_mc)
3633                 param->enable |= HNS3_PROMISC_EN_MC;
3634         if (en_bc)
3635                 param->enable |= HNS3_PROMISC_EN_BC;
3636         param->vf_id = vport_id;
3637 }
3638
3639 static int
3640 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3641 {
3642         struct hns3_promisc_cfg_cmd *req;
3643         struct hns3_cmd_desc desc;
3644         int ret;
3645
3646         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3647
3648         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3649         req->vf_id = param->vf_id;
3650         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3651             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3652
3653         ret = hns3_cmd_send(hw, &desc, 1);
3654         if (ret)
3655                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3656
3657         return ret;
3658 }
3659
3660 static int
3661 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3662 {
3663         struct hns3_promisc_param param;
3664         bool en_bc_pmc = true;
3665         uint8_t vf_id;
3666         int ret;
3667
3668         /*
3669          * In current version VF is not supported when PF is driven by DPDK
3670          * driver, the PF-related vf_id is 0, just need to configure parameters
3671          * for vf_id 0.
3672          */
3673         vf_id = 0;
3674
3675         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3676         ret = hns3_cmd_set_promisc_mode(hw, &param);
3677         if (ret)
3678                 return ret;
3679
3680         return 0;
3681 }
3682
3683 static int
3684 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3685 {
3686         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3687         struct hns3_pf *pf = &hns->pf;
3688         struct hns3_promisc_param param;
3689         uint16_t func_id;
3690         int ret;
3691
3692         /* func_id 0 is denoted PF, the VFs start from 1 */
3693         for (func_id = 1; func_id < pf->func_num; func_id++) {
3694                 hns3_promisc_param_init(&param, false, false, false, func_id);
3695                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3696                 if (ret)
3697                         return ret;
3698         }
3699
3700         return 0;
3701 }
3702
3703 static int
3704 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3705 {
3706         struct hns3_adapter *hns = dev->data->dev_private;
3707         struct hns3_hw *hw = &hns->hw;
3708         int ret;
3709
3710         rte_spinlock_lock(&hw->lock);
3711         ret = hns3_set_promisc_mode(hw, true, true);
3712         rte_spinlock_unlock(&hw->lock);
3713         if (ret)
3714                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3715                          ret);
3716
3717         return ret;
3718 }
3719
3720 static int
3721 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3722 {
3723         bool allmulti = dev->data->all_multicast ? true : false;
3724         struct hns3_adapter *hns = dev->data->dev_private;
3725         struct hns3_hw *hw = &hns->hw;
3726         int ret;
3727
3728         /* If now in all_multicast mode, must remain in all_multicast mode. */
3729         rte_spinlock_lock(&hw->lock);
3730         ret = hns3_set_promisc_mode(hw, false, allmulti);
3731         rte_spinlock_unlock(&hw->lock);
3732         if (ret)
3733                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3734                          ret);
3735
3736         return ret;
3737 }
3738
3739 static int
3740 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3741 {
3742         struct hns3_adapter *hns = dev->data->dev_private;
3743         struct hns3_hw *hw = &hns->hw;
3744         int ret;
3745
3746         if (dev->data->promiscuous)
3747                 return 0;
3748
3749         rte_spinlock_lock(&hw->lock);
3750         ret = hns3_set_promisc_mode(hw, false, true);
3751         rte_spinlock_unlock(&hw->lock);
3752         if (ret)
3753                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3754                          ret);
3755
3756         return ret;
3757 }
3758
3759 static int
3760 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3761 {
3762         struct hns3_adapter *hns = dev->data->dev_private;
3763         struct hns3_hw *hw = &hns->hw;
3764         int ret;
3765
3766         /* If now in promiscuous mode, must remain in all_multicast mode. */
3767         if (dev->data->promiscuous)
3768                 return 0;
3769
3770         rte_spinlock_lock(&hw->lock);
3771         ret = hns3_set_promisc_mode(hw, false, false);
3772         rte_spinlock_unlock(&hw->lock);
3773         if (ret)
3774                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3775                          ret);
3776
3777         return ret;
3778 }
3779
3780 static int
3781 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3782 {
3783         struct hns3_hw *hw = &hns->hw;
3784         bool allmulti = hw->data->all_multicast ? true : false;
3785
3786         if (hw->data->promiscuous)
3787                 return hns3_set_promisc_mode(hw, true, true);
3788
3789         return hns3_set_promisc_mode(hw, false, allmulti);
3790 }
3791
3792 static int
3793 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3794 {
3795         struct hns3_sfp_speed_cmd *resp;
3796         struct hns3_cmd_desc desc;
3797         int ret;
3798
3799         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3800         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3801         ret = hns3_cmd_send(hw, &desc, 1);
3802         if (ret == -EOPNOTSUPP) {
3803                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3804                 return ret;
3805         } else if (ret) {
3806                 hns3_err(hw, "get sfp speed failed %d", ret);
3807                 return ret;
3808         }
3809
3810         *speed = resp->sfp_speed;
3811
3812         return 0;
3813 }
3814
3815 static uint8_t
3816 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3817 {
3818         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3819                 duplex = ETH_LINK_FULL_DUPLEX;
3820
3821         return duplex;
3822 }
3823
3824 static int
3825 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3826 {
3827         struct hns3_mac *mac = &hw->mac;
3828         int ret;
3829
3830         duplex = hns3_check_speed_dup(duplex, speed);
3831         if (mac->link_speed == speed && mac->link_duplex == duplex)
3832                 return 0;
3833
3834         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3835         if (ret)
3836                 return ret;
3837
3838         mac->link_speed = speed;
3839         mac->link_duplex = duplex;
3840
3841         return 0;
3842 }
3843
3844 static int
3845 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3846 {
3847         struct hns3_adapter *hns = eth_dev->data->dev_private;
3848         struct hns3_hw *hw = &hns->hw;
3849         struct hns3_pf *pf = &hns->pf;
3850         uint32_t speed;
3851         int ret;
3852
3853         /* If IMP do not support get SFP/qSFP speed, return directly */
3854         if (!pf->support_sfp_query)
3855                 return 0;
3856
3857         ret = hns3_get_sfp_speed(hw, &speed);
3858         if (ret == -EOPNOTSUPP) {
3859                 pf->support_sfp_query = false;
3860                 return ret;
3861         } else if (ret)
3862                 return ret;
3863
3864         if (speed == ETH_SPEED_NUM_NONE)
3865                 return 0; /* do nothing if no SFP */
3866
3867         /* Config full duplex for SFP */
3868         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3869 }
3870
3871 static int
3872 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3873 {
3874         struct hns3_config_mac_mode_cmd *req;
3875         struct hns3_cmd_desc desc;
3876         uint32_t loop_en = 0;
3877         uint8_t val = 0;
3878         int ret;
3879
3880         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3881
3882         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3883         if (enable)
3884                 val = 1;
3885         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3886         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3887         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3888         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3889         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3890         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3891         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3892         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3893         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3894         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3895         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3896         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3897         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3898         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3899         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3900
3901         ret = hns3_cmd_send(hw, &desc, 1);
3902         if (ret)
3903                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3904
3905         return ret;
3906 }
3907
3908 static int
3909 hns3_get_mac_link_status(struct hns3_hw *hw)
3910 {
3911         struct hns3_link_status_cmd *req;
3912         struct hns3_cmd_desc desc;
3913         int link_status;
3914         int ret;
3915
3916         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3917         ret = hns3_cmd_send(hw, &desc, 1);
3918         if (ret) {
3919                 hns3_err(hw, "get link status cmd failed %d", ret);
3920                 return ETH_LINK_DOWN;
3921         }
3922
3923         req = (struct hns3_link_status_cmd *)desc.data;
3924         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3925
3926         return !!link_status;
3927 }
3928
3929 void
3930 hns3_update_link_status(struct hns3_hw *hw)
3931 {
3932         int state;
3933
3934         state = hns3_get_mac_link_status(hw);
3935         if (state != hw->mac.link_status) {
3936                 hw->mac.link_status = state;
3937                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3938         }
3939 }
3940
3941 static void
3942 hns3_service_handler(void *param)
3943 {
3944         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3945         struct hns3_adapter *hns = eth_dev->data->dev_private;
3946         struct hns3_hw *hw = &hns->hw;
3947
3948         if (!hns3_is_reset_pending(hns)) {
3949                 hns3_update_speed_duplex(eth_dev);
3950                 hns3_update_link_status(hw);
3951         } else
3952                 hns3_warn(hw, "Cancel the query when reset is pending");
3953
3954         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3955 }
3956
3957 static int
3958 hns3_init_hardware(struct hns3_adapter *hns)
3959 {
3960         struct hns3_hw *hw = &hns->hw;
3961         int ret;
3962
3963         ret = hns3_map_tqp(hw);
3964         if (ret) {
3965                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3966                 return ret;
3967         }
3968
3969         ret = hns3_init_umv_space(hw);
3970         if (ret) {
3971                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3972                 return ret;
3973         }
3974
3975         ret = hns3_mac_init(hw);
3976         if (ret) {
3977                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3978                 goto err_mac_init;
3979         }
3980
3981         ret = hns3_init_mgr_tbl(hw);
3982         if (ret) {
3983                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3984                 goto err_mac_init;
3985         }
3986
3987         ret = hns3_set_promisc_mode(hw, false, false);
3988         if (ret) {
3989                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3990                 goto err_mac_init;
3991         }
3992
3993         ret = hns3_clear_all_vfs_promisc_mode(hw);
3994         if (ret) {
3995                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3996                              ret);
3997                 goto err_mac_init;
3998         }
3999
4000         ret = hns3_init_vlan_config(hns);
4001         if (ret) {
4002                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4003                 goto err_mac_init;
4004         }
4005
4006         ret = hns3_dcb_init(hw);
4007         if (ret) {
4008                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4009                 goto err_mac_init;
4010         }
4011
4012         ret = hns3_init_fd_config(hns);
4013         if (ret) {
4014                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4015                 goto err_mac_init;
4016         }
4017
4018         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4019         if (ret) {
4020                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4021                 goto err_mac_init;
4022         }
4023
4024         ret = hns3_config_gro(hw, false);
4025         if (ret) {
4026                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4027                 goto err_mac_init;
4028         }
4029         return 0;
4030
4031 err_mac_init:
4032         hns3_uninit_umv_space(hw);
4033         return ret;
4034 }
4035
4036 static int
4037 hns3_init_pf(struct rte_eth_dev *eth_dev)
4038 {
4039         struct rte_device *dev = eth_dev->device;
4040         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4041         struct hns3_adapter *hns = eth_dev->data->dev_private;
4042         struct hns3_hw *hw = &hns->hw;
4043         int ret;
4044
4045         PMD_INIT_FUNC_TRACE();
4046
4047         /* Get hardware io base address from pcie BAR2 IO space */
4048         hw->io_base = pci_dev->mem_resource[2].addr;
4049
4050         /* Firmware command queue initialize */
4051         ret = hns3_cmd_init_queue(hw);
4052         if (ret) {
4053                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4054                 goto err_cmd_init_queue;
4055         }
4056
4057         hns3_clear_all_event_cause(hw);
4058
4059         /* Firmware command initialize */
4060         ret = hns3_cmd_init(hw);
4061         if (ret) {
4062                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4063                 goto err_cmd_init;
4064         }
4065
4066         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4067                                          hns3_interrupt_handler,
4068                                          eth_dev);
4069         if (ret) {
4070                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4071                 goto err_intr_callback_register;
4072         }
4073
4074         /* Enable interrupt */
4075         rte_intr_enable(&pci_dev->intr_handle);
4076         hns3_pf_enable_irq0(hw);
4077
4078         /* Get configuration */
4079         ret = hns3_get_configuration(hw);
4080         if (ret) {
4081                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4082                 goto err_get_config;
4083         }
4084
4085         ret = hns3_init_hardware(hns);
4086         if (ret) {
4087                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4088                 goto err_get_config;
4089         }
4090
4091         /* Initialize flow director filter list & hash */
4092         ret = hns3_fdir_filter_init(hns);
4093         if (ret) {
4094                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4095                 goto err_hw_init;
4096         }
4097
4098         hns3_set_default_rss_args(hw);
4099
4100         ret = hns3_enable_hw_error_intr(hns, true);
4101         if (ret) {
4102                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4103                              ret);
4104                 goto err_fdir;
4105         }
4106
4107         /*
4108          * In the initialization clearing the all hardware mapping relationship
4109          * configurations between queues and interrupt vectors is needed, so
4110          * some error caused by the residual configurations, such as the
4111          * unexpected interrupt, can be avoid.
4112          */
4113         ret = hns3_init_ring_with_vector(hw);
4114         if (ret)
4115                 goto err_fdir;
4116
4117         return 0;
4118
4119 err_fdir:
4120         hns3_fdir_filter_uninit(hns);
4121 err_hw_init:
4122         hns3_uninit_umv_space(hw);
4123
4124 err_get_config:
4125         hns3_pf_disable_irq0(hw);
4126         rte_intr_disable(&pci_dev->intr_handle);
4127         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4128                              eth_dev);
4129
4130 err_intr_callback_register:
4131         hns3_cmd_uninit(hw);
4132
4133 err_cmd_init:
4134         hns3_cmd_destroy_queue(hw);
4135
4136 err_cmd_init_queue:
4137         hw->io_base = NULL;
4138
4139         return ret;
4140 }
4141
4142 static void
4143 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4144 {
4145         struct hns3_adapter *hns = eth_dev->data->dev_private;
4146         struct rte_device *dev = eth_dev->device;
4147         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4148         struct hns3_hw *hw = &hns->hw;
4149
4150         PMD_INIT_FUNC_TRACE();
4151
4152         hns3_enable_hw_error_intr(hns, false);
4153         hns3_rss_uninit(hns);
4154         hns3_fdir_filter_uninit(hns);
4155         hns3_uninit_umv_space(hw);
4156         hns3_pf_disable_irq0(hw);
4157         rte_intr_disable(&pci_dev->intr_handle);
4158         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4159                              eth_dev);
4160         hns3_cmd_uninit(hw);
4161         hns3_cmd_destroy_queue(hw);
4162         hw->io_base = NULL;
4163 }
4164
4165 static int
4166 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4167 {
4168         struct hns3_hw *hw = &hns->hw;
4169         int ret;
4170
4171         ret = hns3_dcb_cfg_update(hns);
4172         if (ret)
4173                 return ret;
4174
4175         /* Enable queues */
4176         ret = hns3_start_queues(hns, reset_queue);
4177         if (ret) {
4178                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4179                 return ret;
4180         }
4181
4182         /* Enable MAC */
4183         ret = hns3_cfg_mac_mode(hw, true);
4184         if (ret) {
4185                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4186                 goto err_config_mac_mode;
4187         }
4188         return 0;
4189
4190 err_config_mac_mode:
4191         hns3_stop_queues(hns, true);
4192         return ret;
4193 }
4194
4195 static int
4196 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4197 {
4198         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4199         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4200         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         uint32_t intr_vector;
4202         uint8_t base = 0;
4203         uint8_t vec = 0;
4204         uint16_t q_id;
4205         int ret;
4206
4207         if (dev->data->dev_conf.intr_conf.rxq == 0)
4208                 return 0;
4209
4210         /* disable uio/vfio intr/eventfd mapping */
4211         rte_intr_disable(intr_handle);
4212
4213         /* check and configure queue intr-vector mapping */
4214         if (rte_intr_cap_multiple(intr_handle) ||
4215             !RTE_ETH_DEV_SRIOV(dev).active) {
4216                 intr_vector = hw->used_rx_queues;
4217                 /* creates event fd for each intr vector when MSIX is used */
4218                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4219                         return -EINVAL;
4220         }
4221         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4222                 intr_handle->intr_vec =
4223                         rte_zmalloc("intr_vec",
4224                                     hw->used_rx_queues * sizeof(int), 0);
4225                 if (intr_handle->intr_vec == NULL) {
4226                         hns3_err(hw, "Failed to allocate %d rx_queues"
4227                                      " intr_vec", hw->used_rx_queues);
4228                         ret = -ENOMEM;
4229                         goto alloc_intr_vec_error;
4230                 }
4231         }
4232
4233         if (rte_intr_allow_others(intr_handle)) {
4234                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4235                 base = RTE_INTR_VEC_RXTX_OFFSET;
4236         }
4237         if (rte_intr_dp_is_en(intr_handle)) {
4238                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4239                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4240                                                          HNS3_RING_TYPE_RX,
4241                                                          q_id);
4242                         if (ret)
4243                                 goto bind_vector_error;
4244                         intr_handle->intr_vec[q_id] = vec;
4245                         if (vec < base + intr_handle->nb_efd - 1)
4246                                 vec++;
4247                 }
4248         }
4249         rte_intr_enable(intr_handle);
4250         return 0;
4251
4252 bind_vector_error:
4253         rte_intr_efd_disable(intr_handle);
4254         if (intr_handle->intr_vec) {
4255                 free(intr_handle->intr_vec);
4256                 intr_handle->intr_vec = NULL;
4257         }
4258         return ret;
4259 alloc_intr_vec_error:
4260         rte_intr_efd_disable(intr_handle);
4261         return ret;
4262 }
4263
4264 static int
4265 hns3_dev_start(struct rte_eth_dev *dev)
4266 {
4267         struct hns3_adapter *hns = dev->data->dev_private;
4268         struct hns3_hw *hw = &hns->hw;
4269         int ret;
4270
4271         PMD_INIT_FUNC_TRACE();
4272         if (rte_atomic16_read(&hw->reset.resetting))
4273                 return -EBUSY;
4274
4275         rte_spinlock_lock(&hw->lock);
4276         hw->adapter_state = HNS3_NIC_STARTING;
4277
4278         ret = hns3_do_start(hns, true);
4279         if (ret) {
4280                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4281                 rte_spinlock_unlock(&hw->lock);
4282                 return ret;
4283         }
4284
4285         hw->adapter_state = HNS3_NIC_STARTED;
4286         rte_spinlock_unlock(&hw->lock);
4287
4288         ret = hns3_map_rx_interrupt(dev);
4289         if (ret)
4290                 return ret;
4291         hns3_set_rxtx_function(dev);
4292         hns3_mp_req_start_rxtx(dev);
4293         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4294
4295         hns3_info(hw, "hns3 dev start successful!");
4296         return 0;
4297 }
4298
4299 static int
4300 hns3_do_stop(struct hns3_adapter *hns)
4301 {
4302         struct hns3_hw *hw = &hns->hw;
4303         bool reset_queue;
4304         int ret;
4305
4306         ret = hns3_cfg_mac_mode(hw, false);
4307         if (ret)
4308                 return ret;
4309         hw->mac.link_status = ETH_LINK_DOWN;
4310
4311         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4312                 hns3_configure_all_mac_addr(hns, true);
4313                 reset_queue = true;
4314         } else
4315                 reset_queue = false;
4316         hw->mac.default_addr_setted = false;
4317         return hns3_stop_queues(hns, reset_queue);
4318 }
4319
4320 static void
4321 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4322 {
4323         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4324         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4325         struct hns3_adapter *hns = dev->data->dev_private;
4326         struct hns3_hw *hw = &hns->hw;
4327         uint8_t base = 0;
4328         uint8_t vec = 0;
4329         uint16_t q_id;
4330
4331         if (dev->data->dev_conf.intr_conf.rxq == 0)
4332                 return;
4333
4334         /* unmap the ring with vector */
4335         if (rte_intr_allow_others(intr_handle)) {
4336                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4337                 base = RTE_INTR_VEC_RXTX_OFFSET;
4338         }
4339         if (rte_intr_dp_is_en(intr_handle)) {
4340                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4341                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4342                                                          HNS3_RING_TYPE_RX,
4343                                                          q_id);
4344                         if (vec < base + intr_handle->nb_efd - 1)
4345                                 vec++;
4346                 }
4347         }
4348         /* Clean datapath event and queue/vec mapping */
4349         rte_intr_efd_disable(intr_handle);
4350         if (intr_handle->intr_vec) {
4351                 rte_free(intr_handle->intr_vec);
4352                 intr_handle->intr_vec = NULL;
4353         }
4354 }
4355
4356 static void
4357 hns3_dev_stop(struct rte_eth_dev *dev)
4358 {
4359         struct hns3_adapter *hns = dev->data->dev_private;
4360         struct hns3_hw *hw = &hns->hw;
4361
4362         PMD_INIT_FUNC_TRACE();
4363
4364         hw->adapter_state = HNS3_NIC_STOPPING;
4365         hns3_set_rxtx_function(dev);
4366         rte_wmb();
4367         /* Disable datapath on secondary process. */
4368         hns3_mp_req_stop_rxtx(dev);
4369         /* Prevent crashes when queues are still in use. */
4370         rte_delay_ms(hw->tqps_num);
4371
4372         rte_spinlock_lock(&hw->lock);
4373         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4374                 hns3_do_stop(hns);
4375                 hns3_dev_release_mbufs(hns);
4376                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4377         }
4378         rte_eal_alarm_cancel(hns3_service_handler, dev);
4379         rte_spinlock_unlock(&hw->lock);
4380         hns3_unmap_rx_interrupt(dev);
4381 }
4382
4383 static void
4384 hns3_dev_close(struct rte_eth_dev *eth_dev)
4385 {
4386         struct hns3_adapter *hns = eth_dev->data->dev_private;
4387         struct hns3_hw *hw = &hns->hw;
4388
4389         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4390                 rte_free(eth_dev->process_private);
4391                 eth_dev->process_private = NULL;
4392                 return;
4393         }
4394
4395         if (hw->adapter_state == HNS3_NIC_STARTED)
4396                 hns3_dev_stop(eth_dev);
4397
4398         hw->adapter_state = HNS3_NIC_CLOSING;
4399         hns3_reset_abort(hns);
4400         hw->adapter_state = HNS3_NIC_CLOSED;
4401
4402         hns3_configure_all_mc_mac_addr(hns, true);
4403         hns3_remove_all_vlan_table(hns);
4404         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4405         hns3_uninit_pf(eth_dev);
4406         hns3_free_all_queues(eth_dev);
4407         rte_free(hw->reset.wait_data);
4408         rte_free(eth_dev->process_private);
4409         eth_dev->process_private = NULL;
4410         hns3_mp_uninit_primary();
4411         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4412 }
4413
4414 static int
4415 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4416 {
4417         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4419
4420         fc_conf->pause_time = pf->pause_time;
4421
4422         /* return fc current mode */
4423         switch (hw->current_mode) {
4424         case HNS3_FC_FULL:
4425                 fc_conf->mode = RTE_FC_FULL;
4426                 break;
4427         case HNS3_FC_TX_PAUSE:
4428                 fc_conf->mode = RTE_FC_TX_PAUSE;
4429                 break;
4430         case HNS3_FC_RX_PAUSE:
4431                 fc_conf->mode = RTE_FC_RX_PAUSE;
4432                 break;
4433         case HNS3_FC_NONE:
4434         default:
4435                 fc_conf->mode = RTE_FC_NONE;
4436                 break;
4437         }
4438
4439         return 0;
4440 }
4441
4442 static void
4443 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4444 {
4445         switch (mode) {
4446         case RTE_FC_NONE:
4447                 hw->requested_mode = HNS3_FC_NONE;
4448                 break;
4449         case RTE_FC_RX_PAUSE:
4450                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4451                 break;
4452         case RTE_FC_TX_PAUSE:
4453                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4454                 break;
4455         case RTE_FC_FULL:
4456                 hw->requested_mode = HNS3_FC_FULL;
4457                 break;
4458         default:
4459                 hw->requested_mode = HNS3_FC_NONE;
4460                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4461                           "configured to RTE_FC_NONE", mode);
4462                 break;
4463         }
4464 }
4465
4466 static int
4467 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4468 {
4469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4471         int ret;
4472
4473         if (fc_conf->high_water || fc_conf->low_water ||
4474             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4475                 hns3_err(hw, "Unsupported flow control settings specified, "
4476                          "high_water(%u), low_water(%u), send_xon(%u) and "
4477                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4478                          fc_conf->high_water, fc_conf->low_water,
4479                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4480                 return -EINVAL;
4481         }
4482         if (fc_conf->autoneg) {
4483                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4484                 return -EINVAL;
4485         }
4486         if (!fc_conf->pause_time) {
4487                 hns3_err(hw, "Invalid pause time %d setting.",
4488                          fc_conf->pause_time);
4489                 return -EINVAL;
4490         }
4491
4492         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4493             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4494                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4495                          "current_fc_status = %d", hw->current_fc_status);
4496                 return -EOPNOTSUPP;
4497         }
4498
4499         hns3_get_fc_mode(hw, fc_conf->mode);
4500         if (hw->requested_mode == hw->current_mode &&
4501             pf->pause_time == fc_conf->pause_time)
4502                 return 0;
4503
4504         rte_spinlock_lock(&hw->lock);
4505         ret = hns3_fc_enable(dev, fc_conf);
4506         rte_spinlock_unlock(&hw->lock);
4507
4508         return ret;
4509 }
4510
4511 static int
4512 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4513                             struct rte_eth_pfc_conf *pfc_conf)
4514 {
4515         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517         uint8_t priority;
4518         int ret;
4519
4520         if (!hns3_dev_dcb_supported(hw)) {
4521                 hns3_err(hw, "This port does not support dcb configurations.");
4522                 return -EOPNOTSUPP;
4523         }
4524
4525         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4526             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4527                 hns3_err(hw, "Unsupported flow control settings specified, "
4528                          "high_water(%u), low_water(%u), send_xon(%u) and "
4529                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4530                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4531                          pfc_conf->fc.send_xon,
4532                          pfc_conf->fc.mac_ctrl_frame_fwd);
4533                 return -EINVAL;
4534         }
4535         if (pfc_conf->fc.autoneg) {
4536                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4537                 return -EINVAL;
4538         }
4539         if (pfc_conf->fc.pause_time == 0) {
4540                 hns3_err(hw, "Invalid pause time %d setting.",
4541                          pfc_conf->fc.pause_time);
4542                 return -EINVAL;
4543         }
4544
4545         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4546             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4547                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4548                              "current_fc_status = %d", hw->current_fc_status);
4549                 return -EOPNOTSUPP;
4550         }
4551
4552         priority = pfc_conf->priority;
4553         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4554         if (hw->dcb_info.pfc_en & BIT(priority) &&
4555             hw->requested_mode == hw->current_mode &&
4556             pfc_conf->fc.pause_time == pf->pause_time)
4557                 return 0;
4558
4559         rte_spinlock_lock(&hw->lock);
4560         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4561         rte_spinlock_unlock(&hw->lock);
4562
4563         return ret;
4564 }
4565
4566 static int
4567 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4568 {
4569         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4571         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4572         int i;
4573
4574         rte_spinlock_lock(&hw->lock);
4575         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4576                 dcb_info->nb_tcs = pf->local_max_tc;
4577         else
4578                 dcb_info->nb_tcs = 1;
4579
4580         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4581                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4582         for (i = 0; i < dcb_info->nb_tcs; i++)
4583                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4584
4585         for (i = 0; i < hw->num_tc; i++) {
4586                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4587                 dcb_info->tc_queue.tc_txq[0][i].base =
4588                                                 hw->tc_queue[i].tqp_offset;
4589                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4590                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4591                                                 hw->tc_queue[i].tqp_count;
4592         }
4593         rte_spinlock_unlock(&hw->lock);
4594
4595         return 0;
4596 }
4597
4598 static int
4599 hns3_reinit_dev(struct hns3_adapter *hns)
4600 {
4601         struct hns3_hw *hw = &hns->hw;
4602         int ret;
4603
4604         ret = hns3_cmd_init(hw);
4605         if (ret) {
4606                 hns3_err(hw, "Failed to init cmd: %d", ret);
4607                 return ret;
4608         }
4609
4610         ret = hns3_reset_all_queues(hns);
4611         if (ret) {
4612                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4613                 goto err_init;
4614         }
4615
4616         ret = hns3_init_hardware(hns);
4617         if (ret) {
4618                 hns3_err(hw, "Failed to init hardware: %d", ret);
4619                 goto err_init;
4620         }
4621
4622         ret = hns3_enable_hw_error_intr(hns, true);
4623         if (ret) {
4624                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4625                              ret);
4626                 goto err_mac_init;
4627         }
4628         hns3_info(hw, "Reset done, driver initialization finished.");
4629
4630         return 0;
4631
4632 err_mac_init:
4633         hns3_uninit_umv_space(hw);
4634 err_init:
4635         hns3_cmd_uninit(hw);
4636
4637         return ret;
4638 }
4639
4640 static bool
4641 is_pf_reset_done(struct hns3_hw *hw)
4642 {
4643         uint32_t val, reg, reg_bit;
4644
4645         switch (hw->reset.level) {
4646         case HNS3_IMP_RESET:
4647                 reg = HNS3_GLOBAL_RESET_REG;
4648                 reg_bit = HNS3_IMP_RESET_BIT;
4649                 break;
4650         case HNS3_GLOBAL_RESET:
4651                 reg = HNS3_GLOBAL_RESET_REG;
4652                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4653                 break;
4654         case HNS3_FUNC_RESET:
4655                 reg = HNS3_FUN_RST_ING;
4656                 reg_bit = HNS3_FUN_RST_ING_B;
4657                 break;
4658         case HNS3_FLR_RESET:
4659         default:
4660                 hns3_err(hw, "Wait for unsupported reset level: %d",
4661                          hw->reset.level);
4662                 return true;
4663         }
4664         val = hns3_read_dev(hw, reg);
4665         if (hns3_get_bit(val, reg_bit))
4666                 return false;
4667         else
4668                 return true;
4669 }
4670
4671 bool
4672 hns3_is_reset_pending(struct hns3_adapter *hns)
4673 {
4674         struct hns3_hw *hw = &hns->hw;
4675         enum hns3_reset_level reset;
4676
4677         hns3_check_event_cause(hns, NULL);
4678         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4679         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4680                 hns3_warn(hw, "High level reset %d is pending", reset);
4681                 return true;
4682         }
4683         reset = hns3_get_reset_level(hns, &hw->reset.request);
4684         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4685                 hns3_warn(hw, "High level reset %d is request", reset);
4686                 return true;
4687         }
4688         return false;
4689 }
4690
4691 static int
4692 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4693 {
4694         struct hns3_hw *hw = &hns->hw;
4695         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4696         struct timeval tv;
4697
4698         if (wait_data->result == HNS3_WAIT_SUCCESS)
4699                 return 0;
4700         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4701                 gettimeofday(&tv, NULL);
4702                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4703                           tv.tv_sec, tv.tv_usec);
4704                 return -ETIME;
4705         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4706                 return -EAGAIN;
4707
4708         wait_data->hns = hns;
4709         wait_data->check_completion = is_pf_reset_done;
4710         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4711                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4712         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4713         wait_data->count = HNS3_RESET_WAIT_CNT;
4714         wait_data->result = HNS3_WAIT_REQUEST;
4715         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4716         return -EAGAIN;
4717 }
4718
4719 static int
4720 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4721 {
4722         struct hns3_cmd_desc desc;
4723         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4724
4725         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4726         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4727         req->fun_reset_vfid = func_id;
4728
4729         return hns3_cmd_send(hw, &desc, 1);
4730 }
4731
4732 static int
4733 hns3_imp_reset_cmd(struct hns3_hw *hw)
4734 {
4735         struct hns3_cmd_desc desc;
4736
4737         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4738         desc.data[0] = 0xeedd;
4739
4740         return hns3_cmd_send(hw, &desc, 1);
4741 }
4742
4743 static void
4744 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4745 {
4746         struct hns3_hw *hw = &hns->hw;
4747         struct timeval tv;
4748         uint32_t val;
4749
4750         gettimeofday(&tv, NULL);
4751         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4752             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4753                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4754                           tv.tv_sec, tv.tv_usec);
4755                 return;
4756         }
4757
4758         switch (reset_level) {
4759         case HNS3_IMP_RESET:
4760                 hns3_imp_reset_cmd(hw);
4761                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4762                           tv.tv_sec, tv.tv_usec);
4763                 break;
4764         case HNS3_GLOBAL_RESET:
4765                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4766                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4767                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4768                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4769                           tv.tv_sec, tv.tv_usec);
4770                 break;
4771         case HNS3_FUNC_RESET:
4772                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4773                           tv.tv_sec, tv.tv_usec);
4774                 /* schedule again to check later */
4775                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4776                 hns3_schedule_reset(hns);
4777                 break;
4778         default:
4779                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4780                 return;
4781         }
4782         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4783 }
4784
4785 static enum hns3_reset_level
4786 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4787 {
4788         struct hns3_hw *hw = &hns->hw;
4789         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4790
4791         /* Return the highest priority reset level amongst all */
4792         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4793                 reset_level = HNS3_IMP_RESET;
4794         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4795                 reset_level = HNS3_GLOBAL_RESET;
4796         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4797                 reset_level = HNS3_FUNC_RESET;
4798         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4799                 reset_level = HNS3_FLR_RESET;
4800
4801         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4802                 return HNS3_NONE_RESET;
4803
4804         return reset_level;
4805 }
4806
4807 static int
4808 hns3_prepare_reset(struct hns3_adapter *hns)
4809 {
4810         struct hns3_hw *hw = &hns->hw;
4811         uint32_t reg_val;
4812         int ret;
4813
4814         switch (hw->reset.level) {
4815         case HNS3_FUNC_RESET:
4816                 ret = hns3_func_reset_cmd(hw, 0);
4817                 if (ret)
4818                         return ret;
4819
4820                 /*
4821                  * After performaning pf reset, it is not necessary to do the
4822                  * mailbox handling or send any command to firmware, because
4823                  * any mailbox handling or command to firmware is only valid
4824                  * after hns3_cmd_init is called.
4825                  */
4826                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4827                 hw->reset.stats.request_cnt++;
4828                 break;
4829         case HNS3_IMP_RESET:
4830                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4831                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4832                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4833                 break;
4834         default:
4835                 break;
4836         }
4837         return 0;
4838 }
4839
4840 static int
4841 hns3_set_rst_done(struct hns3_hw *hw)
4842 {
4843         struct hns3_pf_rst_done_cmd *req;
4844         struct hns3_cmd_desc desc;
4845
4846         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4847         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4848         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4849         return hns3_cmd_send(hw, &desc, 1);
4850 }
4851
4852 static int
4853 hns3_stop_service(struct hns3_adapter *hns)
4854 {
4855         struct hns3_hw *hw = &hns->hw;
4856         struct rte_eth_dev *eth_dev;
4857
4858         eth_dev = &rte_eth_devices[hw->data->port_id];
4859         if (hw->adapter_state == HNS3_NIC_STARTED)
4860                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4861         hw->mac.link_status = ETH_LINK_DOWN;
4862
4863         hns3_set_rxtx_function(eth_dev);
4864         rte_wmb();
4865         /* Disable datapath on secondary process. */
4866         hns3_mp_req_stop_rxtx(eth_dev);
4867         rte_delay_ms(hw->tqps_num);
4868
4869         rte_spinlock_lock(&hw->lock);
4870         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4871             hw->adapter_state == HNS3_NIC_STOPPING) {
4872                 hns3_do_stop(hns);
4873                 hw->reset.mbuf_deferred_free = true;
4874         } else
4875                 hw->reset.mbuf_deferred_free = false;
4876
4877         /*
4878          * It is cumbersome for hardware to pick-and-choose entries for deletion
4879          * from table space. Hence, for function reset software intervention is
4880          * required to delete the entries
4881          */
4882         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4883                 hns3_configure_all_mc_mac_addr(hns, true);
4884         rte_spinlock_unlock(&hw->lock);
4885
4886         return 0;
4887 }
4888
4889 static int
4890 hns3_start_service(struct hns3_adapter *hns)
4891 {
4892         struct hns3_hw *hw = &hns->hw;
4893         struct rte_eth_dev *eth_dev;
4894
4895         if (hw->reset.level == HNS3_IMP_RESET ||
4896             hw->reset.level == HNS3_GLOBAL_RESET)
4897                 hns3_set_rst_done(hw);
4898         eth_dev = &rte_eth_devices[hw->data->port_id];
4899         hns3_set_rxtx_function(eth_dev);
4900         hns3_mp_req_start_rxtx(eth_dev);
4901         if (hw->adapter_state == HNS3_NIC_STARTED)
4902                 hns3_service_handler(eth_dev);
4903
4904         return 0;
4905 }
4906
4907 static int
4908 hns3_restore_conf(struct hns3_adapter *hns)
4909 {
4910         struct hns3_hw *hw = &hns->hw;
4911         int ret;
4912
4913         ret = hns3_configure_all_mac_addr(hns, false);
4914         if (ret)
4915                 return ret;
4916
4917         ret = hns3_configure_all_mc_mac_addr(hns, false);
4918         if (ret)
4919                 goto err_mc_mac;
4920
4921         ret = hns3_dev_promisc_restore(hns);
4922         if (ret)
4923                 goto err_promisc;
4924
4925         ret = hns3_restore_vlan_table(hns);
4926         if (ret)
4927                 goto err_promisc;
4928
4929         ret = hns3_restore_vlan_conf(hns);
4930         if (ret)
4931                 goto err_promisc;
4932
4933         ret = hns3_restore_all_fdir_filter(hns);
4934         if (ret)
4935                 goto err_promisc;
4936
4937         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4938                 ret = hns3_do_start(hns, false);
4939                 if (ret)
4940                         goto err_promisc;
4941                 hns3_info(hw, "hns3 dev restart successful!");
4942         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4943                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4944         return 0;
4945
4946 err_promisc:
4947         hns3_configure_all_mc_mac_addr(hns, true);
4948 err_mc_mac:
4949         hns3_configure_all_mac_addr(hns, true);
4950         return ret;
4951 }
4952
4953 static void
4954 hns3_reset_service(void *param)
4955 {
4956         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4957         struct hns3_hw *hw = &hns->hw;
4958         enum hns3_reset_level reset_level;
4959         struct timeval tv_delta;
4960         struct timeval tv_start;
4961         struct timeval tv;
4962         uint64_t msec;
4963         int ret;
4964
4965         /*
4966          * The interrupt is not triggered within the delay time.
4967          * The interrupt may have been lost. It is necessary to handle
4968          * the interrupt to recover from the error.
4969          */
4970         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4971                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4972                 hns3_err(hw, "Handling interrupts in delayed tasks");
4973                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4974                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4975                 if (reset_level == HNS3_NONE_RESET) {
4976                         hns3_err(hw, "No reset level is set, try IMP reset");
4977                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4978                 }
4979         }
4980         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4981
4982         /*
4983          * Check if there is any ongoing reset in the hardware. This status can
4984          * be checked from reset_pending. If there is then, we need to wait for
4985          * hardware to complete reset.
4986          *    a. If we are able to figure out in reasonable time that hardware
4987          *       has fully resetted then, we can proceed with driver, client
4988          *       reset.
4989          *    b. else, we can come back later to check this status so re-sched
4990          *       now.
4991          */
4992         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4993         if (reset_level != HNS3_NONE_RESET) {
4994                 gettimeofday(&tv_start, NULL);
4995                 ret = hns3_reset_process(hns, reset_level);
4996                 gettimeofday(&tv, NULL);
4997                 timersub(&tv, &tv_start, &tv_delta);
4998                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4999                        tv_delta.tv_usec / USEC_PER_MSEC;
5000                 if (msec > HNS3_RESET_PROCESS_MS)
5001                         hns3_err(hw, "%d handle long time delta %" PRIx64
5002                                      " ms time=%ld.%.6ld",
5003                                  hw->reset.level, msec,
5004                                  tv.tv_sec, tv.tv_usec);
5005                 if (ret == -EAGAIN)
5006                         return;
5007         }
5008
5009         /* Check if we got any *new* reset requests to be honored */
5010         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5011         if (reset_level != HNS3_NONE_RESET)
5012                 hns3_msix_process(hns, reset_level);
5013 }
5014
5015 static const struct eth_dev_ops hns3_eth_dev_ops = {
5016         .dev_start          = hns3_dev_start,
5017         .dev_stop           = hns3_dev_stop,
5018         .dev_close          = hns3_dev_close,
5019         .promiscuous_enable = hns3_dev_promiscuous_enable,
5020         .promiscuous_disable = hns3_dev_promiscuous_disable,
5021         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5022         .allmulticast_disable = hns3_dev_allmulticast_disable,
5023         .mtu_set            = hns3_dev_mtu_set,
5024         .stats_get          = hns3_stats_get,
5025         .stats_reset        = hns3_stats_reset,
5026         .xstats_get         = hns3_dev_xstats_get,
5027         .xstats_get_names   = hns3_dev_xstats_get_names,
5028         .xstats_reset       = hns3_dev_xstats_reset,
5029         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5030         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5031         .dev_infos_get          = hns3_dev_infos_get,
5032         .fw_version_get         = hns3_fw_version_get,
5033         .rx_queue_setup         = hns3_rx_queue_setup,
5034         .tx_queue_setup         = hns3_tx_queue_setup,
5035         .rx_queue_release       = hns3_dev_rx_queue_release,
5036         .tx_queue_release       = hns3_dev_tx_queue_release,
5037         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5038         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5039         .dev_configure          = hns3_dev_configure,
5040         .flow_ctrl_get          = hns3_flow_ctrl_get,
5041         .flow_ctrl_set          = hns3_flow_ctrl_set,
5042         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5043         .mac_addr_add           = hns3_add_mac_addr,
5044         .mac_addr_remove        = hns3_remove_mac_addr,
5045         .mac_addr_set           = hns3_set_default_mac_addr,
5046         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5047         .link_update            = hns3_dev_link_update,
5048         .rss_hash_update        = hns3_dev_rss_hash_update,
5049         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5050         .reta_update            = hns3_dev_rss_reta_update,
5051         .reta_query             = hns3_dev_rss_reta_query,
5052         .filter_ctrl            = hns3_dev_filter_ctrl,
5053         .vlan_filter_set        = hns3_vlan_filter_set,
5054         .vlan_tpid_set          = hns3_vlan_tpid_set,
5055         .vlan_offload_set       = hns3_vlan_offload_set,
5056         .vlan_pvid_set          = hns3_vlan_pvid_set,
5057         .get_reg                = hns3_get_regs,
5058         .get_dcb_info           = hns3_get_dcb_info,
5059         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5060 };
5061
5062 static const struct hns3_reset_ops hns3_reset_ops = {
5063         .reset_service       = hns3_reset_service,
5064         .stop_service        = hns3_stop_service,
5065         .prepare_reset       = hns3_prepare_reset,
5066         .wait_hardware_ready = hns3_wait_hardware_ready,
5067         .reinit_dev          = hns3_reinit_dev,
5068         .restore_conf        = hns3_restore_conf,
5069         .start_service       = hns3_start_service,
5070 };
5071
5072 static int
5073 hns3_dev_init(struct rte_eth_dev *eth_dev)
5074 {
5075         struct rte_device *dev = eth_dev->device;
5076         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5077         struct hns3_adapter *hns = eth_dev->data->dev_private;
5078         struct hns3_hw *hw = &hns->hw;
5079         uint16_t device_id = pci_dev->id.device_id;
5080         int ret;
5081
5082         PMD_INIT_FUNC_TRACE();
5083         eth_dev->process_private = (struct hns3_process_private *)
5084             rte_zmalloc_socket("hns3_filter_list",
5085                                sizeof(struct hns3_process_private),
5086                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5087         if (eth_dev->process_private == NULL) {
5088                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5089                 return -ENOMEM;
5090         }
5091         /* initialize flow filter lists */
5092         hns3_filterlist_init(eth_dev);
5093
5094         hns3_set_rxtx_function(eth_dev);
5095         eth_dev->dev_ops = &hns3_eth_dev_ops;
5096         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5097                 hns3_mp_init_secondary();
5098                 hw->secondary_cnt++;
5099                 return 0;
5100         }
5101
5102         hns3_mp_init_primary();
5103         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5104
5105         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5106             device_id == HNS3_DEV_ID_50GE_RDMA ||
5107             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5108                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5109
5110         hns->is_vf = false;
5111         hw->data = eth_dev->data;
5112
5113         /*
5114          * Set default max packet size according to the mtu
5115          * default vale in DPDK frame.
5116          */
5117         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5118
5119         ret = hns3_reset_init(hw);
5120         if (ret)
5121                 goto err_init_reset;
5122         hw->reset.ops = &hns3_reset_ops;
5123
5124         ret = hns3_init_pf(eth_dev);
5125         if (ret) {
5126                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5127                 goto err_init_pf;
5128         }
5129
5130         /* Allocate memory for storing MAC addresses */
5131         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5132                                                sizeof(struct rte_ether_addr) *
5133                                                HNS3_UC_MACADDR_NUM, 0);
5134         if (eth_dev->data->mac_addrs == NULL) {
5135                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5136                              "to store MAC addresses",
5137                              sizeof(struct rte_ether_addr) *
5138                              HNS3_UC_MACADDR_NUM);
5139                 ret = -ENOMEM;
5140                 goto err_rte_zmalloc;
5141         }
5142
5143         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5144                             &eth_dev->data->mac_addrs[0]);
5145
5146         hw->adapter_state = HNS3_NIC_INITIALIZED;
5147         /*
5148          * Pass the information to the rte_eth_dev_close() that it should also
5149          * release the private port resources.
5150          */
5151         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5152
5153         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5154                 hns3_err(hw, "Reschedule reset service after dev_init");
5155                 hns3_schedule_reset(hns);
5156         } else {
5157                 /* IMP will wait ready flag before reset */
5158                 hns3_notify_reset_ready(hw, false);
5159         }
5160
5161         hns3_info(hw, "hns3 dev initialization successful!");
5162         return 0;
5163
5164 err_rte_zmalloc:
5165         hns3_uninit_pf(eth_dev);
5166
5167 err_init_pf:
5168         rte_free(hw->reset.wait_data);
5169 err_init_reset:
5170         eth_dev->dev_ops = NULL;
5171         eth_dev->rx_pkt_burst = NULL;
5172         eth_dev->tx_pkt_burst = NULL;
5173         eth_dev->tx_pkt_prepare = NULL;
5174         rte_free(eth_dev->process_private);
5175         eth_dev->process_private = NULL;
5176         return ret;
5177 }
5178
5179 static int
5180 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5181 {
5182         struct hns3_adapter *hns = eth_dev->data->dev_private;
5183         struct hns3_hw *hw = &hns->hw;
5184
5185         PMD_INIT_FUNC_TRACE();
5186
5187         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5188                 return -EPERM;
5189
5190         eth_dev->dev_ops = NULL;
5191         eth_dev->rx_pkt_burst = NULL;
5192         eth_dev->tx_pkt_burst = NULL;
5193         eth_dev->tx_pkt_prepare = NULL;
5194         if (hw->adapter_state < HNS3_NIC_CLOSING)
5195                 hns3_dev_close(eth_dev);
5196
5197         hw->adapter_state = HNS3_NIC_REMOVED;
5198         return 0;
5199 }
5200
5201 static int
5202 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5203                    struct rte_pci_device *pci_dev)
5204 {
5205         return rte_eth_dev_pci_generic_probe(pci_dev,
5206                                              sizeof(struct hns3_adapter),
5207                                              hns3_dev_init);
5208 }
5209
5210 static int
5211 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5212 {
5213         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5214 }
5215
5216 static const struct rte_pci_id pci_id_hns3_map[] = {
5217         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5218         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5219         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5220         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5221         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5222         { .vendor_id = 0, /* sentinel */ },
5223 };
5224
5225 static struct rte_pci_driver rte_hns3_pmd = {
5226         .id_table = pci_id_hns3_map,
5227         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5228         .probe = eth_hns3_pci_probe,
5229         .remove = eth_hns3_pci_remove,
5230 };
5231
5232 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5233 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5234 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5235
5236 RTE_INIT(hns3_init_log)
5237 {
5238         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5239         if (hns3_logtype_init >= 0)
5240                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5241         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5242         if (hns3_logtype_driver >= 0)
5243                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5244 }