drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105
 106 void hns3_ether_format_addr(char *buf, uint16_t size,
 107                             const struct rte_ether_addr *ether_addr)
 108 {
 109         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 110                 ether_addr->addr_bytes[0],
 111                 ether_addr->addr_bytes[4],
 112                 ether_addr->addr_bytes[5]);
 113 }
 114
 115 static void
 116 hns3_pf_disable_irq0(struct hns3_hw *hw)
 117 {
 118         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 119 }
 120
 121 static void
 122 hns3_pf_enable_irq0(struct hns3_hw *hw)
 123 {
 124         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 125 }
 126
 127 static enum hns3_evt_cause
 128 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 129                           uint32_t *vec_val)
 130 {
 131         struct hns3_hw *hw = &hns->hw;
 132
 133         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 134         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 135         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 136         if (!is_delay) {
 137                 hw->reset.stats.imp_cnt++;
 138                 hns3_warn(hw, "IMP reset detected, clear reset status");
 139         } else {
 140                 hns3_schedule_delayed_reset(hns);
 141                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 142         }
 143
 144         return HNS3_VECTOR0_EVENT_RST;
 145 }
 146
 147 static enum hns3_evt_cause
 148 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 149                              uint32_t *vec_val)
 150 {
 151         struct hns3_hw *hw = &hns->hw;
 152
 153         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 154         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 155         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 156         if (!is_delay) {
 157                 hw->reset.stats.global_cnt++;
 158                 hns3_warn(hw, "Global reset detected, clear reset status");
 159         } else {
 160                 hns3_schedule_delayed_reset(hns);
 161                 hns3_warn(hw,
 162                           "Global reset detected, don't clear reset status");
 163         }
 164
 165         return HNS3_VECTOR0_EVENT_RST;
 166 }
 167
 168 static enum hns3_evt_cause
 169 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 170 {
 171         struct hns3_hw *hw = &hns->hw;
 172         uint32_t vector0_int_stats;
 173         uint32_t cmdq_src_val;
 174         uint32_t hw_err_src_reg;
 175         uint32_t val;
 176         enum hns3_evt_cause ret;
 177         bool is_delay;
 178
 179         /* fetch the events from their corresponding regs */
 180         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 181         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 182         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 183
 184         is_delay = clearval == NULL ? true : false;
 185         /*
 186          * Assumption: If by any chance reset and mailbox events are reported
 187          * together then we will only process reset event and defer the
 188          * processing of the mailbox events. Since, we would have not cleared
 189          * RX CMDQ event this time we would receive again another interrupt
 190          * from H/W just for the mailbox.
 191          */
 192         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 193                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 194                 goto out;
 195         }
 196
 197         /* Global reset */
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 199                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 200                 goto out;
 201         }
 202
 203         /* check for vector0 msix event source */
 204         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 205             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 206                 val = vector0_int_stats | hw_err_src_reg;
 207                 ret = HNS3_VECTOR0_EVENT_ERR;
 208                 goto out;
 209         }
 210
 211         /* check for vector0 mailbox(=CMDQ RX) event source */
 212         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 213                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 214                 val = cmdq_src_val;
 215                 ret = HNS3_VECTOR0_EVENT_MBX;
 216                 goto out;
 217         }
 218
 219         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 220                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 221                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 222         val = vector0_int_stats;
 223         ret = HNS3_VECTOR0_EVENT_OTHER;
 224 out:
 225
 226         if (clearval)
 227                 *clearval = val;
 228         return ret;
 229 }
 230
 231 static void
 232 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 233 {
 234         if (event_type == HNS3_VECTOR0_EVENT_RST)
 235                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 236         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 237                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 238 }
 239
 240 static void
 241 hns3_clear_all_event_cause(struct hns3_hw *hw)
 242 {
 243         uint32_t vector0_int_stats;
 244         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 245
 246         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 247                 hns3_warn(hw, "Probe during IMP reset interrupt");
 248
 249         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 250                 hns3_warn(hw, "Probe during Global reset interrupt");
 251
 252         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 253                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 255                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 256         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 257 }
 258
 259 static void
 260 hns3_interrupt_handler(void *param)
 261 {
 262         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 263         struct hns3_adapter *hns = dev->data->dev_private;
 264         struct hns3_hw *hw = &hns->hw;
 265         enum hns3_evt_cause event_cause;
 266         uint32_t clearval = 0;
 267
 268         /* Disable interrupt */
 269         hns3_pf_disable_irq0(hw);
 270
 271         event_cause = hns3_check_event_cause(hns, &clearval);
 272         /* vector 0 interrupt is shared with reset and mailbox source events. */
 273         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 274                 hns3_warn(hw, "Received err interrupt");
 275                 hns3_handle_msix_error(hns, &hw->reset.request);
 276                 hns3_handle_ras_error(hns, &hw->reset.request);
 277                 hns3_schedule_reset(hns);
 278         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 279                 hns3_warn(hw, "Received reset interrupt");
 280                 hns3_schedule_reset(hns);
 281         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 282                 hns3_dev_handle_mbx_msg(hw);
 283         else
 284                 hns3_err(hw, "Received unknown event");
 285
 286         hns3_clear_event_cause(hw, event_cause, clearval);
 287         /* Enable interrupt if it is not cause by reset */
 288         hns3_pf_enable_irq0(hw);
 289 }
 290
 291 static int
 292 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 293 {
 294 #define HNS3_VLAN_ID_OFFSET_STEP        160
 295 #define HNS3_VLAN_BYTE_SIZE             8
 296         struct hns3_vlan_filter_pf_cfg_cmd *req;
 297         struct hns3_hw *hw = &hns->hw;
 298         uint8_t vlan_offset_byte_val;
 299         struct hns3_cmd_desc desc;
 300         uint8_t vlan_offset_byte;
 301         uint8_t vlan_offset_base;
 302         int ret;
 303
 304         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 305
 306         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 307         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 308                            HNS3_VLAN_BYTE_SIZE;
 309         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 310
 311         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 312         req->vlan_offset = vlan_offset_base;
 313         req->vlan_cfg = on ? 0 : 1;
 314         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 315
 316         ret = hns3_cmd_send(hw, &desc, 1);
 317         if (ret)
 318                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 319                          vlan_id, ret);
 320
 321         return ret;
 322 }
 323
 324 static void
 325 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 326 {
 327         struct hns3_user_vlan_table *vlan_entry;
 328         struct hns3_pf *pf = &hns->pf;
 329
 330         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 331                 if (vlan_entry->vlan_id == vlan_id) {
 332                         if (vlan_entry->hd_tbl_status)
 333                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 334                         LIST_REMOVE(vlan_entry, next);
 335                         rte_free(vlan_entry);
 336                         break;
 337                 }
 338         }
 339 }
 340
 341 static void
 342 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 343                         bool writen_to_tbl)
 344 {
 345         struct hns3_user_vlan_table *vlan_entry;
 346         struct hns3_hw *hw = &hns->hw;
 347         struct hns3_pf *pf = &hns->pf;
 348
 349         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 350                 if (vlan_entry->vlan_id == vlan_id)
 351                         return;
 352         }
 353
 354         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 355         if (vlan_entry == NULL) {
 356                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 357                 return;
 358         }
 359
 360         vlan_entry->hd_tbl_status = writen_to_tbl;
 361         vlan_entry->vlan_id = vlan_id;
 362
 363         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 364 }
 365
 366 static int
 367 hns3_restore_vlan_table(struct hns3_adapter *hns)
 368 {
 369         struct hns3_user_vlan_table *vlan_entry;
 370         struct hns3_hw *hw = &hns->hw;
 371         struct hns3_pf *pf = &hns->pf;
 372         uint16_t vlan_id;
 373         int ret = 0;
 374
 375         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 376                 return hns3_vlan_pvid_configure(hns,
 377                                                 hw->port_base_vlan_cfg.pvid, 1);
 378
 379         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 380                 if (vlan_entry->hd_tbl_status) {
 381                         vlan_id = vlan_entry->vlan_id;
 382                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 383                         if (ret)
 384                                 break;
 385                 }
 386         }
 387
 388         return ret;
 389 }
 390
 391 static int
 392 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 393 {
 394         struct hns3_hw *hw = &hns->hw;
 395         bool writen_to_tbl = false;
 396         int ret = 0;
 397
 398         /*
 399          * When vlan filter is enabled, hardware regards packets without vlan
 400          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 401          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 402          */
 403         if (on == 0 && vlan_id == 0)
 404                 return 0;
 405
 406         /*
 407          * When port base vlan enabled, we use port base vlan as the vlan
 408          * filter condition. In this case, we don't update vlan filter table
 409          * when user add new vlan or remove exist vlan, just update the
 410          * vlan list. The vlan id in vlan list will be writen in vlan filter
 411          * table until port base vlan disabled
 412          */
 413         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 414                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 415                 writen_to_tbl = true;
 416         }
 417
 418         if (ret == 0) {
 419                 if (on)
 420                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 421                 else
 422                         hns3_rm_dev_vlan_table(hns, vlan_id);
 423         }
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 429 {
 430         struct hns3_adapter *hns = dev->data->dev_private;
 431         struct hns3_hw *hw = &hns->hw;
 432         int ret;
 433
 434         rte_spinlock_lock(&hw->lock);
 435         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 436         rte_spinlock_unlock(&hw->lock);
 437         return ret;
 438 }
 439
 440 static int
 441 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 442                          uint16_t tpid)
 443 {
 444         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 445         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 446         struct hns3_hw *hw = &hns->hw;
 447         struct hns3_cmd_desc desc;
 448         int ret;
 449
 450         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 451              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 452                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 453                 return -EINVAL;
 454         }
 455
 456         if (tpid != RTE_ETHER_TYPE_VLAN) {
 457                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 458                 return -EINVAL;
 459         }
 460
 461         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 462         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 463
 464         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 465                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 466                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 467         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 468                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 471                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 472         }
 473
 474         ret = hns3_cmd_send(hw, &desc, 1);
 475         if (ret) {
 476                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 477                          ret);
 478                 return ret;
 479         }
 480
 481         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 482
 483         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 484         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 485         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 486
 487         ret = hns3_cmd_send(hw, &desc, 1);
 488         if (ret)
 489                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 490                          ret);
 491         return ret;
 492 }
 493
 494 static int
 495 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 496                    uint16_t tpid)
 497 {
 498         struct hns3_adapter *hns = dev->data->dev_private;
 499         struct hns3_hw *hw = &hns->hw;
 500         int ret;
 501
 502         rte_spinlock_lock(&hw->lock);
 503         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 504         rte_spinlock_unlock(&hw->lock);
 505         return ret;
 506 }
 507
 508 static int
 509 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 510                              struct hns3_rx_vtag_cfg *vcfg)
 511 {
 512         struct hns3_vport_vtag_rx_cfg_cmd *req;
 513         struct hns3_hw *hw = &hns->hw;
 514         struct hns3_cmd_desc desc;
 515         uint16_t vport_id;
 516         uint8_t bitmap;
 517         int ret;
 518
 519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 520
 521         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 523                      vcfg->strip_tag1_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 525                      vcfg->strip_tag2_en ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 527                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 528         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 529                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 530
 531         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 533                      vcfg->strip_tag1_discard_en ? 1 : 0);
 534         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 535                      vcfg->strip_tag2_discard_en ? 1 : 0);
 536         /*
 537          * In current version VF is not supported when PF is driven by DPDK
 538          * driver, just need to configure parameters for PF vport.
 539          */
 540         vport_id = HNS3_PF_FUNC_ID;
 541         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 542         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 543         req->vf_bitmap[req->vf_offset] = bitmap;
 544
 545         ret = hns3_cmd_send(hw, &desc, 1);
 546         if (ret)
 547                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 548         return ret;
 549 }
 550
 551 static void
 552 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 553                            struct hns3_rx_vtag_cfg *vcfg)
 554 {
 555         struct hns3_pf *pf = &hns->pf;
 556         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 557 }
 558
 559 static void
 560 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 561                            struct hns3_tx_vtag_cfg *vcfg)
 562 {
 563         struct hns3_pf *pf = &hns->pf;
 564         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 565 }
 566
 567 static int
 568 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 569 {
 570         struct hns3_rx_vtag_cfg rxvlan_cfg;
 571         struct hns3_hw *hw = &hns->hw;
 572         int ret;
 573
 574         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 575                 rxvlan_cfg.strip_tag1_en = false;
 576                 rxvlan_cfg.strip_tag2_en = enable;
 577                 rxvlan_cfg.strip_tag2_discard_en = false;
 578         } else {
 579                 rxvlan_cfg.strip_tag1_en = enable;
 580                 rxvlan_cfg.strip_tag2_en = true;
 581                 rxvlan_cfg.strip_tag2_discard_en = true;
 582         }
 583
 584         rxvlan_cfg.strip_tag1_discard_en = false;
 585         rxvlan_cfg.vlan1_vlan_prionly = false;
 586         rxvlan_cfg.vlan2_vlan_prionly = false;
 587         rxvlan_cfg.rx_vlan_offload_en = enable;
 588
 589         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 590         if (ret) {
 591                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 592                 return ret;
 593         }
 594
 595         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 602                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 603 {
 604         struct hns3_vlan_filter_ctrl_cmd *req;
 605         struct hns3_cmd_desc desc;
 606         int ret;
 607
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 609
 610         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 611         req->vlan_type = vlan_type;
 612         req->vlan_fe = filter_en ? fe_type : 0;
 613         req->vf_id = vf_id;
 614
 615         ret = hns3_cmd_send(hw, &desc, 1);
 616         if (ret)
 617                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 618
 619         return ret;
 620 }
 621
 622 static int
 623 hns3_vlan_filter_init(struct hns3_adapter *hns)
 624 {
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 629                                         HNS3_FILTER_FE_EGRESS, false,
 630                                         HNS3_PF_FUNC_ID);
 631         if (ret) {
 632                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 633                 return ret;
 634         }
 635
 636         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 637                                         HNS3_FILTER_FE_INGRESS, false,
 638                                         HNS3_PF_FUNC_ID);
 639         if (ret)
 640                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 647 {
 648         struct hns3_hw *hw = &hns->hw;
 649         int ret;
 650
 651         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 652                                         HNS3_FILTER_FE_INGRESS, enable,
 653                                         HNS3_PF_FUNC_ID);
 654         if (ret)
 655                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 656                          enable ? "enable" : "disable", ret);
 657
 658         return ret;
 659 }
 660
 661 static int
 662 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 663 {
 664         struct hns3_adapter *hns = dev->data->dev_private;
 665         struct hns3_hw *hw = &hns->hw;
 666         struct rte_eth_rxmode *rxmode;
 667         unsigned int tmp_mask;
 668         bool enable;
 669         int ret = 0;
 670
 671         rte_spinlock_lock(&hw->lock);
 672         rxmode = &dev->data->dev_conf.rxmode;
 673         tmp_mask = (unsigned int)mask;
 674         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 675                 /* ignore vlan filter configuration during promiscuous mode */
 676                 if (!dev->data->promiscuous) {
 677                         /* Enable or disable VLAN filter */
 678                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 679                                  true : false;
 680
 681                         ret = hns3_enable_vlan_filter(hns, enable);
 682                         if (ret) {
 683                                 rte_spinlock_unlock(&hw->lock);
 684                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 685                                          enable ? "enable" : "disable", ret);
 686                                 return ret;
 687                         }
 688                 }
 689         }
 690
 691         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 692                 /* Enable or disable VLAN stripping */
 693                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 694                     true : false;
 695
 696                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 697                 if (ret) {
 698                         rte_spinlock_unlock(&hw->lock);
 699                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 700                                  enable ? "enable" : "disable", ret);
 701                         return ret;
 702                 }
 703         }
 704
 705         rte_spinlock_unlock(&hw->lock);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 712                              struct hns3_tx_vtag_cfg *vcfg)
 713 {
 714         struct hns3_vport_vtag_tx_cfg_cmd *req;
 715         struct hns3_cmd_desc desc;
 716         struct hns3_hw *hw = &hns->hw;
 717         uint16_t vport_id;
 718         uint8_t bitmap;
 719         int ret;
 720
 721         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 722
 723         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 724         req->def_vlan_tag1 = vcfg->default_tag1;
 725         req->def_vlan_tag2 = vcfg->default_tag2;
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 727                      vcfg->accept_tag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 729                      vcfg->accept_untag1 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 731                      vcfg->accept_tag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 733                      vcfg->accept_untag2 ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 735                      vcfg->insert_tag1_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 737                      vcfg->insert_tag2_en ? 1 : 0);
 738         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 739
 740         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 741         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 742                      vcfg->tag_shift_mode_en ? 1 : 0);
 743
 744         /*
 745          * In current version VF is not supported when PF is driven by DPDK
 746          * driver, just need to configure parameters for PF vport.
 747          */
 748         vport_id = HNS3_PF_FUNC_ID;
 749         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 750         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 751         req->vf_bitmap[req->vf_offset] = bitmap;
 752
 753         ret = hns3_cmd_send(hw, &desc, 1);
 754         if (ret)
 755                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 756
 757         return ret;
 758 }
 759
 760 static int
 761 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 762                      uint16_t pvid)
 763 {
 764         struct hns3_hw *hw = &hns->hw;
 765         struct hns3_tx_vtag_cfg txvlan_cfg;
 766         int ret;
 767
 768         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 769                 txvlan_cfg.accept_tag1 = true;
 770                 txvlan_cfg.insert_tag1_en = false;
 771                 txvlan_cfg.default_tag1 = 0;
 772         } else {
 773                 txvlan_cfg.accept_tag1 =
 774                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 775                 txvlan_cfg.insert_tag1_en = true;
 776                 txvlan_cfg.default_tag1 = pvid;
 777         }
 778
 779         txvlan_cfg.accept_untag1 = true;
 780         txvlan_cfg.accept_tag2 = true;
 781         txvlan_cfg.accept_untag2 = true;
 782         txvlan_cfg.insert_tag2_en = false;
 783         txvlan_cfg.default_tag2 = 0;
 784         txvlan_cfg.tag_shift_mode_en = true;
 785
 786         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 787         if (ret) {
 788                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 789                          ret);
 790                 return ret;
 791         }
 792
 793         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 794         return ret;
 795 }
 796
 797
 798 static void
 799 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 800 {
 801         struct hns3_user_vlan_table *vlan_entry;
 802         struct hns3_pf *pf = &hns->pf;
 803
 804         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 805                 if (vlan_entry->hd_tbl_status) {
 806                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 807                         vlan_entry->hd_tbl_status = false;
 808                 }
 809         }
 810
 811         if (is_del_list) {
 812                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 813                 while (vlan_entry) {
 814                         LIST_REMOVE(vlan_entry, next);
 815                         rte_free(vlan_entry);
 816                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 817                 }
 818         }
 819 }
 820
 821 static void
 822 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 823 {
 824         struct hns3_user_vlan_table *vlan_entry;
 825         struct hns3_pf *pf = &hns->pf;
 826
 827         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 828                 if (!vlan_entry->hd_tbl_status) {
 829                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 830                         vlan_entry->hd_tbl_status = true;
 831                 }
 832         }
 833 }
 834
 835 static void
 836 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 837 {
 838         struct hns3_hw *hw = &hns->hw;
 839         int ret;
 840
 841         hns3_rm_all_vlan_table(hns, true);
 842         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 843                 ret = hns3_set_port_vlan_filter(hns,
 844                                                 hw->port_base_vlan_cfg.pvid, 0);
 845                 if (ret) {
 846                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 847                                  ret);
 848                         return;
 849                 }
 850         }
 851 }
 852
 853 static int
 854 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 855                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 856 {
 857         struct hns3_hw *hw = &hns->hw;
 858         uint16_t old_pvid;
 859         int ret;
 860
 861         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 862                 old_pvid = hw->port_base_vlan_cfg.pvid;
 863                 if (old_pvid != HNS3_INVALID_PVID) {
 864                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 865                         if (ret) {
 866                                 hns3_err(hw, "failed to remove old pvid %u, "
 867                                                 "ret = %d", old_pvid, ret);
 868                                 return ret;
 869                         }
 870                 }
 871
 872                 hns3_rm_all_vlan_table(hns, false);
 873                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 874                 if (ret) {
 875                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 876                                         new_pvid, ret);
 877                         return ret;
 878                 }
 879         } else {
 880                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 881                 if (ret) {
 882                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 883                                         new_pvid, ret);
 884                         return ret;
 885                 }
 886
 887                 hns3_add_all_vlan_table(hns);
 888         }
 889         return 0;
 890 }
 891
 892 static int
 893 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 894 {
 895         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 896         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 897         bool rx_strip_en;
 898         int ret;
 899
 900         rx_strip_en = old_cfg->rx_vlan_offload_en;
 901         if (on) {
 902                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 903                 rx_vlan_cfg.strip_tag2_en = true;
 904                 rx_vlan_cfg.strip_tag2_discard_en = true;
 905         } else {
 906                 rx_vlan_cfg.strip_tag1_en = false;
 907                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 908                 rx_vlan_cfg.strip_tag2_discard_en = false;
 909         }
 910         rx_vlan_cfg.strip_tag1_discard_en = false;
 911         rx_vlan_cfg.vlan1_vlan_prionly = false;
 912         rx_vlan_cfg.vlan2_vlan_prionly = false;
 913         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 914
 915         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 916         if (ret)
 917                 return ret;
 918
 919         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 920         return ret;
 921 }
 922
 923 static int
 924 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 925 {
 926         struct hns3_hw *hw = &hns->hw;
 927         uint16_t port_base_vlan_state;
 928         int ret;
 929
 930         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 931                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 932                         hns3_warn(hw, "Invalid operation! As current pvid set "
 933                                   "is %u, disable pvid %u is invalid",
 934                                   hw->port_base_vlan_cfg.pvid, pvid);
 935                 return 0;
 936         }
 937
 938         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 939                                     HNS3_PORT_BASE_VLAN_DISABLE;
 940         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 941         if (ret) {
 942                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 943                          ret);
 944                 return ret;
 945         }
 946
 947         ret = hns3_en_pvid_strip(hns, on);
 948         if (ret) {
 949                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 950                          "ret = %d", ret);
 951                 return ret;
 952         }
 953
 954         if (pvid == HNS3_INVALID_PVID)
 955                 goto out;
 956         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 957         if (ret) {
 958                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 959                          ret);
 960                 return ret;
 961         }
 962
 963 out:
 964         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 965         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 966         return ret;
 967 }
 968
 969 static int
 970 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 971 {
 972         struct hns3_adapter *hns = dev->data->dev_private;
 973         struct hns3_hw *hw = &hns->hw;
 974         bool pvid_en_state_change;
 975         uint16_t pvid_state;
 976         int ret;
 977
 978         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 979                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 980                          RTE_ETHER_MAX_VLAN_ID);
 981                 return -EINVAL;
 982         }
 983
 984         /*
 985          * If PVID configuration state change, should refresh the PVID
 986          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 987          */
 988         pvid_state = hw->port_base_vlan_cfg.state;
 989         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 990             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 991                 pvid_en_state_change = false;
 992         else
 993                 pvid_en_state_change = true;
 994
 995         rte_spinlock_lock(&hw->lock);
 996         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 997         rte_spinlock_unlock(&hw->lock);
 998         if (ret)
 999                 return ret;
1000         /*
1001          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1002          * need be processed by PMD driver.
1003          */
1004         if (pvid_en_state_change &&
1005             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1006                 hns3_update_all_queues_pvid_proc_en(hw);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 hns3_default_vlan_config(struct hns3_adapter *hns)
1013 {
1014         struct hns3_hw *hw = &hns->hw;
1015         int ret;
1016
1017         /*
1018          * When vlan filter is enabled, hardware regards packets without vlan
1019          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1020          * table, packets without vlan won't be received. So, add vlan 0 as
1021          * the default vlan.
1022          */
1023         ret = hns3_vlan_filter_configure(hns, 0, 1);
1024         if (ret)
1025                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1026         return ret;
1027 }
1028
1029 static int
1030 hns3_init_vlan_config(struct hns3_adapter *hns)
1031 {
1032         struct hns3_hw *hw = &hns->hw;
1033         int ret;
1034
1035         /*
1036          * This function can be called in the initialization and reset process,
1037          * when in reset process, it means that hardware had been reseted
1038          * successfully and we need to restore the hardware configuration to
1039          * ensure that the hardware configuration remains unchanged before and
1040          * after reset.
1041          */
1042         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1043                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1044                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1045         }
1046
1047         ret = hns3_vlan_filter_init(hns);
1048         if (ret) {
1049                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1050                 return ret;
1051         }
1052
1053         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1054                                        RTE_ETHER_TYPE_VLAN);
1055         if (ret) {
1056                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1057                 return ret;
1058         }
1059
1060         /*
1061          * When in the reinit dev stage of the reset process, the following
1062          * vlan-related configurations may differ from those at initialization,
1063          * we will restore configurations to hardware in hns3_restore_vlan_table
1064          * and hns3_restore_vlan_conf later.
1065          */
1066         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1067                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1068                 if (ret) {
1069                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1070                         return ret;
1071                 }
1072
1073                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1074                 if (ret) {
1075                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1076                                  ret);
1077                         return ret;
1078                 }
1079         }
1080
1081         return hns3_default_vlan_config(hns);
1082 }
1083
1084 static int
1085 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1086 {
1087         struct hns3_pf *pf = &hns->pf;
1088         struct hns3_hw *hw = &hns->hw;
1089         uint64_t offloads;
1090         bool enable;
1091         int ret;
1092
1093         if (!hw->data->promiscuous) {
1094                 /* restore vlan filter states */
1095                 offloads = hw->data->dev_conf.rxmode.offloads;
1096                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1097                 ret = hns3_enable_vlan_filter(hns, enable);
1098                 if (ret) {
1099                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1100                                  "ret = %d", ret);
1101                         return ret;
1102                 }
1103         }
1104
1105         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1106         if (ret) {
1107                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1108                 return ret;
1109         }
1110
1111         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1112         if (ret)
1113                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1114
1115         return ret;
1116 }
1117
1118 static int
1119 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1120 {
1121         struct hns3_adapter *hns = dev->data->dev_private;
1122         struct rte_eth_dev_data *data = dev->data;
1123         struct rte_eth_txmode *txmode;
1124         struct hns3_hw *hw = &hns->hw;
1125         int mask;
1126         int ret;
1127
1128         txmode = &data->dev_conf.txmode;
1129         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1130                 hns3_warn(hw,
1131                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1132                           "configuration is not supported! Ignore these two "
1133                           "parameters: hw_vlan_reject_tagged(%u), "
1134                           "hw_vlan_reject_untagged(%u)",
1135                           txmode->hw_vlan_reject_tagged,
1136                           txmode->hw_vlan_reject_untagged);
1137
1138         /* Apply vlan offload setting */
1139         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1140         ret = hns3_vlan_offload_set(dev, mask);
1141         if (ret) {
1142                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1143                          ret);
1144                 return ret;
1145         }
1146
1147         /*
1148          * If pvid config is not set in rte_eth_conf, driver needn't to set
1149          * VLAN pvid related configuration to hardware.
1150          */
1151         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1152                 return 0;
1153
1154         /* Apply pvid setting */
1155         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1156                                  txmode->hw_vlan_insert_pvid);
1157         if (ret)
1158                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1159                          txmode->pvid, ret);
1160
1161         return ret;
1162 }
1163
1164 static int
1165 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1166                 unsigned int tso_mss_max)
1167 {
1168         struct hns3_cfg_tso_status_cmd *req;
1169         struct hns3_cmd_desc desc;
1170         uint16_t tso_mss;
1171
1172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1173
1174         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1175
1176         tso_mss = 0;
1177         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1178                        tso_mss_min);
1179         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1180
1181         tso_mss = 0;
1182         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1183                        tso_mss_max);
1184         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1185
1186         return hns3_cmd_send(hw, &desc, 1);
1187 }
1188
1189 static int
1190 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1191                    uint16_t *allocated_size, bool is_alloc)
1192 {
1193         struct hns3_umv_spc_alc_cmd *req;
1194         struct hns3_cmd_desc desc;
1195         int ret;
1196
1197         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1198         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1199         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1200         req->space_size = rte_cpu_to_le_32(space_size);
1201
1202         ret = hns3_cmd_send(hw, &desc, 1);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1205                              is_alloc ? "allocate" : "free", ret);
1206                 return ret;
1207         }
1208
1209         if (is_alloc && allocated_size)
1210                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1211
1212         return 0;
1213 }
1214
1215 static int
1216 hns3_init_umv_space(struct hns3_hw *hw)
1217 {
1218         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1219         struct hns3_pf *pf = &hns->pf;
1220         uint16_t allocated_size = 0;
1221         int ret;
1222
1223         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1224                                  true);
1225         if (ret)
1226                 return ret;
1227
1228         if (allocated_size < pf->wanted_umv_size)
1229                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1230                              pf->wanted_umv_size, allocated_size);
1231
1232         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1233                                                 pf->wanted_umv_size;
1234         pf->used_umv_size = 0;
1235         return 0;
1236 }
1237
1238 static int
1239 hns3_uninit_umv_space(struct hns3_hw *hw)
1240 {
1241         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1242         struct hns3_pf *pf = &hns->pf;
1243         int ret;
1244
1245         if (pf->max_umv_size == 0)
1246                 return 0;
1247
1248         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1249         if (ret)
1250                 return ret;
1251
1252         pf->max_umv_size = 0;
1253
1254         return 0;
1255 }
1256
1257 static bool
1258 hns3_is_umv_space_full(struct hns3_hw *hw)
1259 {
1260         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1261         struct hns3_pf *pf = &hns->pf;
1262         bool is_full;
1263
1264         is_full = (pf->used_umv_size >= pf->max_umv_size);
1265
1266         return is_full;
1267 }
1268
1269 static void
1270 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1271 {
1272         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1273         struct hns3_pf *pf = &hns->pf;
1274
1275         if (is_free) {
1276                 if (pf->used_umv_size > 0)
1277                         pf->used_umv_size--;
1278         } else
1279                 pf->used_umv_size++;
1280 }
1281
1282 static void
1283 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1284                       const uint8_t *addr, bool is_mc)
1285 {
1286         const unsigned char *mac_addr = addr;
1287         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1288                             ((uint32_t)mac_addr[2] << 16) |
1289                             ((uint32_t)mac_addr[1] << 8) |
1290                             (uint32_t)mac_addr[0];
1291         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1292
1293         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1294         if (is_mc) {
1295                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1296                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1297                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1298         }
1299
1300         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1301         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1302 }
1303
1304 static int
1305 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1306                              uint8_t resp_code,
1307                              enum hns3_mac_vlan_tbl_opcode op)
1308 {
1309         if (cmdq_resp) {
1310                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1311                          cmdq_resp);
1312                 return -EIO;
1313         }
1314
1315         if (op == HNS3_MAC_VLAN_ADD) {
1316                 if (resp_code == 0 || resp_code == 1) {
1317                         return 0;
1318                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1319                         hns3_err(hw, "add mac addr failed for uc_overflow");
1320                         return -ENOSPC;
1321                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1322                         hns3_err(hw, "add mac addr failed for mc_overflow");
1323                         return -ENOSPC;
1324                 }
1325
1326                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1327                          resp_code);
1328                 return -EIO;
1329         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1330                 if (resp_code == 0) {
1331                         return 0;
1332                 } else if (resp_code == 1) {
1333                         hns3_dbg(hw, "remove mac addr failed for miss");
1334                         return -ENOENT;
1335                 }
1336
1337                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1338                          resp_code);
1339                 return -EIO;
1340         } else if (op == HNS3_MAC_VLAN_LKUP) {
1341                 if (resp_code == 0) {
1342                         return 0;
1343                 } else if (resp_code == 1) {
1344                         hns3_dbg(hw, "lookup mac addr failed for miss");
1345                         return -ENOENT;
1346                 }
1347
1348                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1349                          resp_code);
1350                 return -EIO;
1351         }
1352
1353         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1354                  op);
1355
1356         return -EINVAL;
1357 }
1358
1359 static int
1360 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1361                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1362                          struct hns3_cmd_desc *desc, bool is_mc)
1363 {
1364         uint8_t resp_code;
1365         uint16_t retval;
1366         int ret;
1367
1368         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1369         if (is_mc) {
1370                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 memcpy(desc[0].data, req,
1372                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1373                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1374                                           true);
1375                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1376                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1377                                           true);
1378                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379         } else {
1380                 memcpy(desc[0].data, req,
1381                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1382                 ret = hns3_cmd_send(hw, desc, 1);
1383         }
1384         if (ret) {
1385                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1386                          ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc[0].retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_LKUP);
1394 }
1395
1396 static int
1397 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1398                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1399                       struct hns3_cmd_desc *mc_desc)
1400 {
1401         uint8_t resp_code;
1402         uint16_t retval;
1403         int cfg_status;
1404         int ret;
1405
1406         if (mc_desc == NULL) {
1407                 struct hns3_cmd_desc desc;
1408
1409                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1410                 memcpy(desc.data, req,
1411                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 ret = hns3_cmd_send(hw, &desc, 1);
1413                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1414                 retval = rte_le_to_cpu_16(desc.retval);
1415
1416                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1417                                                           HNS3_MAC_VLAN_ADD);
1418         } else {
1419                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1420                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1422                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1423                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1424                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1425                 memcpy(mc_desc[0].data, req,
1426                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1427                 mc_desc[0].retval = 0;
1428                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1429                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1430                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1431
1432                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1433                                                           HNS3_MAC_VLAN_ADD);
1434         }
1435
1436         if (ret) {
1437                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1438                 return ret;
1439         }
1440
1441         return cfg_status;
1442 }
1443
1444 static int
1445 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1446                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1447 {
1448         struct hns3_cmd_desc desc;
1449         uint8_t resp_code;
1450         uint16_t retval;
1451         int ret;
1452
1453         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1454
1455         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1456
1457         ret = hns3_cmd_send(hw, &desc, 1);
1458         if (ret) {
1459                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1460                 return ret;
1461         }
1462         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1463         retval = rte_le_to_cpu_16(desc.retval);
1464
1465         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1466                                             HNS3_MAC_VLAN_REMOVE);
1467 }
1468
1469 static int
1470 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1471 {
1472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1473         struct hns3_mac_vlan_tbl_entry_cmd req;
1474         struct hns3_pf *pf = &hns->pf;
1475         struct hns3_cmd_desc desc[3];
1476         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1477         uint16_t egress_port = 0;
1478         uint8_t vf_id;
1479         int ret;
1480
1481         /* check if mac addr is valid */
1482         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1483                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1484                                       mac_addr);
1485                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1486                          mac_str);
1487                 return -EINVAL;
1488         }
1489
1490         memset(&req, 0, sizeof(req));
1491
1492         /*
1493          * In current version VF is not supported when PF is driven by DPDK
1494          * driver, just need to configure parameters for PF vport.
1495          */
1496         vf_id = HNS3_PF_FUNC_ID;
1497         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1498                        HNS3_MAC_EPORT_VFID_S, vf_id);
1499
1500         req.egress_port = rte_cpu_to_le_16(egress_port);
1501
1502         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1503
1504         /*
1505          * Lookup the mac address in the mac_vlan table, and add
1506          * it if the entry is inexistent. Repeated unicast entry
1507          * is not allowed in the mac vlan table.
1508          */
1509         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1510         if (ret == -ENOENT) {
1511                 if (!hns3_is_umv_space_full(hw)) {
1512                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1513                         if (!ret)
1514                                 hns3_update_umv_space(hw, false);
1515                         return ret;
1516                 }
1517
1518                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1519
1520                 return -ENOSPC;
1521         }
1522
1523         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1524
1525         /* check if we just hit the duplicate */
1526         if (ret == 0) {
1527                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1528                 return 0;
1529         }
1530
1531         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1532                  mac_str);
1533
1534         return ret;
1535 }
1536
1537 static int
1538 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1541         struct rte_ether_addr *addr;
1542         int ret;
1543         int i;
1544
1545         for (i = 0; i < hw->mc_addrs_num; i++) {
1546                 addr = &hw->mc_addrs[i];
1547                 /* Check if there are duplicate addresses */
1548                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1549                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                               addr);
1551                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1552                                  "(%s) is added by the set_mc_mac_addr_list "
1553                                  "API", mac_str);
1554                         return -EINVAL;
1555                 }
1556         }
1557
1558         ret = hns3_add_mc_addr(hw, mac_addr);
1559         if (ret) {
1560                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1563                          mac_str, ret);
1564         }
1565         return ret;
1566 }
1567
1568 static int
1569 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1570 {
1571         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1572         int ret;
1573
1574         ret = hns3_remove_mc_addr(hw, mac_addr);
1575         if (ret) {
1576                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1577                                       mac_addr);
1578                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1579                          mac_str, ret);
1580         }
1581         return ret;
1582 }
1583
1584 static int
1585 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1586                   uint32_t idx, __rte_unused uint32_t pool)
1587 {
1588         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590         int ret;
1591
1592         rte_spinlock_lock(&hw->lock);
1593
1594         /*
1595          * In hns3 network engine adding UC and MC mac address with different
1596          * commands with firmware. We need to determine whether the input
1597          * address is a UC or a MC address to call different commands.
1598          * By the way, it is recommended calling the API function named
1599          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1600          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1601          * may affect the specifications of UC mac addresses.
1602          */
1603         if (rte_is_multicast_ether_addr(mac_addr))
1604                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1605         else
1606                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1607
1608         if (ret) {
1609                 rte_spinlock_unlock(&hw->lock);
1610                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                       mac_addr);
1612                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1613                          ret);
1614                 return ret;
1615         }
1616
1617         if (idx == 0)
1618                 hw->mac.default_addr_setted = true;
1619         rte_spinlock_unlock(&hw->lock);
1620
1621         return ret;
1622 }
1623
1624 static int
1625 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         struct hns3_mac_vlan_tbl_entry_cmd req;
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         int ret;
1630
1631         /* check if mac addr is valid */
1632         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1633                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634                                       mac_addr);
1635                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1636                          mac_str);
1637                 return -EINVAL;
1638         }
1639
1640         memset(&req, 0, sizeof(req));
1641         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1643         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1644         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1645                 return 0;
1646         else if (ret == 0)
1647                 hns3_update_umv_space(hw, true);
1648
1649         return ret;
1650 }
1651
1652 static void
1653 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1654 {
1655         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1656         /* index will be checked by upper level rte interface */
1657         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         if (rte_is_multicast_ether_addr(mac_addr))
1664                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1665         else
1666                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1667         rte_spinlock_unlock(&hw->lock);
1668         if (ret) {
1669                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1670                                       mac_addr);
1671                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1672                          ret);
1673         }
1674 }
1675
1676 static int
1677 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1678                           struct rte_ether_addr *mac_addr)
1679 {
1680         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_ether_addr *oaddr;
1682         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1683         bool default_addr_setted;
1684         bool rm_succes = false;
1685         int ret, ret_val;
1686
1687         /*
1688          * It has been guaranteed that input parameter named mac_addr is valid
1689          * address in the rte layer of DPDK framework.
1690          */
1691         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1692         default_addr_setted = hw->mac.default_addr_setted;
1693         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1694                 return 0;
1695
1696         rte_spinlock_lock(&hw->lock);
1697         if (default_addr_setted) {
1698                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1699                 if (ret) {
1700                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1701                                               oaddr);
1702                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1703                                   mac_str, ret);
1704                         rm_succes = false;
1705                 } else
1706                         rm_succes = true;
1707         }
1708
1709         ret = hns3_add_uc_addr_common(hw, mac_addr);
1710         if (ret) {
1711                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1714                 goto err_add_uc_addr;
1715         }
1716
1717         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1718         if (ret) {
1719                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1720                 goto err_pause_addr_cfg;
1721         }
1722
1723         rte_ether_addr_copy(mac_addr,
1724                             (struct rte_ether_addr *)hw->mac.mac_addr);
1725         hw->mac.default_addr_setted = true;
1726         rte_spinlock_unlock(&hw->lock);
1727
1728         return 0;
1729
1730 err_pause_addr_cfg:
1731         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1732         if (ret_val) {
1733                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734                                       mac_addr);
1735                 hns3_warn(hw,
1736                           "Failed to roll back to del setted mac addr(%s): %d",
1737                           mac_str, ret_val);
1738         }
1739
1740 err_add_uc_addr:
1741         if (rm_succes) {
1742                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1743                 if (ret_val) {
1744                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1745                                               oaddr);
1746                         hns3_warn(hw,
1747                                   "Failed to restore old uc mac addr(%s): %d",
1748                                   mac_str, ret_val);
1749                         hw->mac.default_addr_setted = false;
1750                 }
1751         }
1752         rte_spinlock_unlock(&hw->lock);
1753
1754         return ret;
1755 }
1756
1757 static int
1758 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1759 {
1760         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1761         struct hns3_hw *hw = &hns->hw;
1762         struct rte_ether_addr *addr;
1763         int err = 0;
1764         int ret;
1765         int i;
1766
1767         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1768                 addr = &hw->data->mac_addrs[i];
1769                 if (rte_is_zero_ether_addr(addr))
1770                         continue;
1771                 if (rte_is_multicast_ether_addr(addr))
1772                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1773                               hns3_add_mc_addr(hw, addr);
1774                 else
1775                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1776                               hns3_add_uc_addr_common(hw, addr);
1777
1778                 if (ret) {
1779                         err = ret;
1780                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                               addr);
1782                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1783                                  "ret = %d.", del ? "remove" : "restore",
1784                                  mac_str, i, ret);
1785                 }
1786         }
1787         return err;
1788 }
1789
1790 static void
1791 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1792 {
1793 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1794         uint8_t word_num;
1795         uint8_t bit_num;
1796
1797         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1798                 word_num = vfid / 32;
1799                 bit_num = vfid % 32;
1800                 if (clr)
1801                         desc[1].data[word_num] &=
1802                             rte_cpu_to_le_32(~(1UL << bit_num));
1803                 else
1804                         desc[1].data[word_num] |=
1805                             rte_cpu_to_le_32(1UL << bit_num);
1806         } else {
1807                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1808                 bit_num = vfid % 32;
1809                 if (clr)
1810                         desc[2].data[word_num] &=
1811                             rte_cpu_to_le_32(~(1UL << bit_num));
1812                 else
1813                         desc[2].data[word_num] |=
1814                             rte_cpu_to_le_32(1UL << bit_num);
1815         }
1816 }
1817
1818 static int
1819 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1820 {
1821         struct hns3_mac_vlan_tbl_entry_cmd req;
1822         struct hns3_cmd_desc desc[3];
1823         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1824         uint8_t vf_id;
1825         int ret;
1826
1827         /* Check if mac addr is valid */
1828         if (!rte_is_multicast_ether_addr(mac_addr)) {
1829                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                       mac_addr);
1831                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1832                          mac_str);
1833                 return -EINVAL;
1834         }
1835
1836         memset(&req, 0, sizeof(req));
1837         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1838         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1839         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1840         if (ret) {
1841                 /* This mac addr do not exist, add new entry for it */
1842                 memset(desc[0].data, 0, sizeof(desc[0].data));
1843                 memset(desc[1].data, 0, sizeof(desc[0].data));
1844                 memset(desc[2].data, 0, sizeof(desc[0].data));
1845         }
1846
1847         /*
1848          * In current version VF is not supported when PF is driven by DPDK
1849          * driver, just need to configure parameters for PF vport.
1850          */
1851         vf_id = HNS3_PF_FUNC_ID;
1852         hns3_update_desc_vfid(desc, vf_id, false);
1853         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1854         if (ret) {
1855                 if (ret == -ENOSPC)
1856                         hns3_err(hw, "mc mac vlan table is full");
1857                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1858                                       mac_addr);
1859                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1860         }
1861
1862         return ret;
1863 }
1864
1865 static int
1866 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1867 {
1868         struct hns3_mac_vlan_tbl_entry_cmd req;
1869         struct hns3_cmd_desc desc[3];
1870         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1871         uint8_t vf_id;
1872         int ret;
1873
1874         /* Check if mac addr is valid */
1875         if (!rte_is_multicast_ether_addr(mac_addr)) {
1876                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1877                                       mac_addr);
1878                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1879                          mac_str);
1880                 return -EINVAL;
1881         }
1882
1883         memset(&req, 0, sizeof(req));
1884         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1885         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1886         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1887         if (ret == 0) {
1888                 /*
1889                  * This mac addr exist, remove this handle's VFID for it.
1890                  * In current version VF is not supported when PF is driven by
1891                  * DPDK driver, just need to configure parameters for PF vport.
1892                  */
1893                 vf_id = HNS3_PF_FUNC_ID;
1894                 hns3_update_desc_vfid(desc, vf_id, true);
1895
1896                 /* All the vfid is zero, so need to delete this entry */
1897                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1898         } else if (ret == -ENOENT) {
1899                 /* This mac addr doesn't exist. */
1900                 return 0;
1901         }
1902
1903         if (ret) {
1904                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1905                                       mac_addr);
1906                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1907         }
1908
1909         return ret;
1910 }
1911
1912 static int
1913 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1914                            struct rte_ether_addr *mc_addr_set,
1915                            uint32_t nb_mc_addr)
1916 {
1917         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1918         struct rte_ether_addr *addr;
1919         uint32_t i;
1920         uint32_t j;
1921
1922         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1923                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1924                          "invalid. valid range: 0~%d",
1925                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1926                 return -EINVAL;
1927         }
1928
1929         /* Check if input mac addresses are valid */
1930         for (i = 0; i < nb_mc_addr; i++) {
1931                 addr = &mc_addr_set[i];
1932                 if (!rte_is_multicast_ether_addr(addr)) {
1933                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934                                               addr);
1935                         hns3_err(hw,
1936                                  "failed to set mc mac addr, addr(%s) invalid.",
1937                                  mac_str);
1938                         return -EINVAL;
1939                 }
1940
1941                 /* Check if there are duplicate addresses */
1942                 for (j = i + 1; j < nb_mc_addr; j++) {
1943                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1944                                 hns3_ether_format_addr(mac_str,
1945                                                       RTE_ETHER_ADDR_FMT_SIZE,
1946                                                       addr);
1947                                 hns3_err(hw, "failed to set mc mac addr, "
1948                                          "addrs invalid. two same addrs(%s).",
1949                                          mac_str);
1950                                 return -EINVAL;
1951                         }
1952                 }
1953
1954                 /*
1955                  * Check if there are duplicate addresses between mac_addrs
1956                  * and mc_addr_set
1957                  */
1958                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1959                         if (rte_is_same_ether_addr(addr,
1960                                                    &hw->data->mac_addrs[j])) {
1961                                 hns3_ether_format_addr(mac_str,
1962                                                       RTE_ETHER_ADDR_FMT_SIZE,
1963                                                       addr);
1964                                 hns3_err(hw, "failed to set mc mac addr, "
1965                                          "addrs invalid. addrs(%s) has already "
1966                                          "configured in mac_addr add API",
1967                                          mac_str);
1968                                 return -EINVAL;
1969                         }
1970                 }
1971         }
1972
1973         return 0;
1974 }
1975
1976 static void
1977 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1978                            struct rte_ether_addr *mc_addr_set,
1979                            int mc_addr_num,
1980                            struct rte_ether_addr *reserved_addr_list,
1981                            int *reserved_addr_num,
1982                            struct rte_ether_addr *add_addr_list,
1983                            int *add_addr_num,
1984                            struct rte_ether_addr *rm_addr_list,
1985                            int *rm_addr_num)
1986 {
1987         struct rte_ether_addr *addr;
1988         int current_addr_num;
1989         int reserved_num = 0;
1990         int add_num = 0;
1991         int rm_num = 0;
1992         int num;
1993         int i;
1994         int j;
1995         bool same_addr;
1996
1997         /* Calculate the mc mac address list that should be removed */
1998         current_addr_num = hw->mc_addrs_num;
1999         for (i = 0; i < current_addr_num; i++) {
2000                 addr = &hw->mc_addrs[i];
2001                 same_addr = false;
2002                 for (j = 0; j < mc_addr_num; j++) {
2003                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2004                                 same_addr = true;
2005                                 break;
2006                         }
2007                 }
2008
2009                 if (!same_addr) {
2010                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2011                         rm_num++;
2012                 } else {
2013                         rte_ether_addr_copy(addr,
2014                                             &reserved_addr_list[reserved_num]);
2015                         reserved_num++;
2016                 }
2017         }
2018
2019         /* Calculate the mc mac address list that should be added */
2020         for (i = 0; i < mc_addr_num; i++) {
2021                 addr = &mc_addr_set[i];
2022                 same_addr = false;
2023                 for (j = 0; j < current_addr_num; j++) {
2024                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2025                                 same_addr = true;
2026                                 break;
2027                         }
2028                 }
2029
2030                 if (!same_addr) {
2031                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2032                         add_num++;
2033                 }
2034         }
2035
2036         /* Reorder the mc mac address list maintained by driver */
2037         for (i = 0; i < reserved_num; i++)
2038                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2039
2040         for (i = 0; i < rm_num; i++) {
2041                 num = reserved_num + i;
2042                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2043         }
2044
2045         *reserved_addr_num = reserved_num;
2046         *add_addr_num = add_num;
2047         *rm_addr_num = rm_num;
2048 }
2049
2050 static int
2051 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2052                           struct rte_ether_addr *mc_addr_set,
2053                           uint32_t nb_mc_addr)
2054 {
2055         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2058         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2059         struct rte_ether_addr *addr;
2060         int reserved_addr_num;
2061         int add_addr_num;
2062         int rm_addr_num;
2063         int mc_addr_num;
2064         int num;
2065         int ret;
2066         int i;
2067
2068         /* Check if input parameters are valid */
2069         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2070         if (ret)
2071                 return ret;
2072
2073         rte_spinlock_lock(&hw->lock);
2074
2075         /*
2076          * Calculate the mc mac address lists those should be removed and be
2077          * added, Reorder the mc mac address list maintained by driver.
2078          */
2079         mc_addr_num = (int)nb_mc_addr;
2080         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2081                                    reserved_addr_list, &reserved_addr_num,
2082                                    add_addr_list, &add_addr_num,
2083                                    rm_addr_list, &rm_addr_num);
2084
2085         /* Remove mc mac addresses */
2086         for (i = 0; i < rm_addr_num; i++) {
2087                 num = rm_addr_num - i - 1;
2088                 addr = &rm_addr_list[num];
2089                 ret = hns3_remove_mc_addr(hw, addr);
2090                 if (ret) {
2091                         rte_spinlock_unlock(&hw->lock);
2092                         return ret;
2093                 }
2094                 hw->mc_addrs_num--;
2095         }
2096
2097         /* Add mc mac addresses */
2098         for (i = 0; i < add_addr_num; i++) {
2099                 addr = &add_addr_list[i];
2100                 ret = hns3_add_mc_addr(hw, addr);
2101                 if (ret) {
2102                         rte_spinlock_unlock(&hw->lock);
2103                         return ret;
2104                 }
2105
2106                 num = reserved_addr_num + i;
2107                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2108                 hw->mc_addrs_num++;
2109         }
2110         rte_spinlock_unlock(&hw->lock);
2111
2112         return 0;
2113 }
2114
2115 static int
2116 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2117 {
2118         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2119         struct hns3_hw *hw = &hns->hw;
2120         struct rte_ether_addr *addr;
2121         int err = 0;
2122         int ret;
2123         int i;
2124
2125         for (i = 0; i < hw->mc_addrs_num; i++) {
2126                 addr = &hw->mc_addrs[i];
2127                 if (!rte_is_multicast_ether_addr(addr))
2128                         continue;
2129                 if (del)
2130                         ret = hns3_remove_mc_addr(hw, addr);
2131                 else
2132                         ret = hns3_add_mc_addr(hw, addr);
2133                 if (ret) {
2134                         err = ret;
2135                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2136                                               addr);
2137                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2138                                  del ? "Remove" : "Restore", mac_str, ret);
2139                 }
2140         }
2141         return err;
2142 }
2143
2144 static int
2145 hns3_check_mq_mode(struct rte_eth_dev *dev)
2146 {
2147         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2148         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2152         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2153         uint8_t num_tc;
2154         int max_tc = 0;
2155         int i;
2156
2157         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2158         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2159
2160         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2161                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2162                          "rx_mq_mode = %d", rx_mq_mode);
2163                 return -EINVAL;
2164         }
2165
2166         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2167             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2168                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2169                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2170                          rx_mq_mode, tx_mq_mode);
2171                 return -EINVAL;
2172         }
2173
2174         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2175                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2176                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2177                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2178                         return -EINVAL;
2179                 }
2180
2181                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2182                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2183                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2184                                  "nb_tcs(%d) != %d or %d in rx direction.",
2185                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2186                         return -EINVAL;
2187                 }
2188
2189                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2190                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2191                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2192                         return -EINVAL;
2193                 }
2194
2195                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2196                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2197                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2198                                          "is not equal to one in tx direction.",
2199                                          i, dcb_rx_conf->dcb_tc[i]);
2200                                 return -EINVAL;
2201                         }
2202                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2203                                 max_tc = dcb_rx_conf->dcb_tc[i];
2204                 }
2205
2206                 num_tc = max_tc + 1;
2207                 if (num_tc > dcb_rx_conf->nb_tcs) {
2208                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2209                                  num_tc, dcb_rx_conf->nb_tcs);
2210                         return -EINVAL;
2211                 }
2212         }
2213
2214         return 0;
2215 }
2216
2217 static int
2218 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2219 {
2220         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221
2222         if (!hns3_dev_dcb_supported(hw)) {
2223                 hns3_err(hw, "this port does not support dcb configurations.");
2224                 return -EOPNOTSUPP;
2225         }
2226
2227         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2228                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2229                 return -EOPNOTSUPP;
2230         }
2231
2232         /* Check multiple queue mode */
2233         return hns3_check_mq_mode(dev);
2234 }
2235
2236 static int
2237 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2238                            enum hns3_ring_type queue_type, uint16_t queue_id)
2239 {
2240         struct hns3_cmd_desc desc;
2241         struct hns3_ctrl_vector_chain_cmd *req =
2242                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2243         enum hns3_cmd_status status;
2244         enum hns3_opcode_type op;
2245         uint16_t tqp_type_and_id = 0;
2246         uint16_t type;
2247         uint16_t gl;
2248
2249         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2250         hns3_cmd_setup_basic_desc(&desc, op, false);
2251         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2252                                               HNS3_TQP_INT_ID_L_S);
2253         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2254                                               HNS3_TQP_INT_ID_H_S);
2255
2256         if (queue_type == HNS3_RING_TYPE_RX)
2257                 gl = HNS3_RING_GL_RX;
2258         else
2259                 gl = HNS3_RING_GL_TX;
2260
2261         type = queue_type;
2262
2263         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2264                        type);
2265         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2266         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2267                        gl);
2268         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2269         req->int_cause_num = 1;
2270         status = hns3_cmd_send(hw, &desc, 1);
2271         if (status) {
2272                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2273                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2274                 return status;
2275         }
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3_init_ring_with_vector(struct hns3_hw *hw)
2282 {
2283         uint16_t vec;
2284         int ret;
2285         int i;
2286
2287         /*
2288          * In hns3 network engine, vector 0 is always the misc interrupt of this
2289          * function, vector 1~N can be used respectively for the queues of the
2290          * function. Tx and Rx queues with the same number share the interrupt
2291          * vector. In the initialization clearing the all hardware mapping
2292          * relationship configurations between queues and interrupt vectors is
2293          * needed, so some error caused by the residual configurations, such as
2294          * the unexpected Tx interrupt, can be avoid.
2295          */
2296         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2297         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2298                 vec = vec - 1; /* the last interrupt is reserved */
2299         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2300         for (i = 0; i < hw->intr_tqps_num; i++) {
2301                 /*
2302                  * Set gap limiter/rate limiter/quanity limiter algorithm
2303                  * configuration for interrupt coalesce of queue's interrupt.
2304                  */
2305                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2306                                        HNS3_TQP_INTR_GL_DEFAULT);
2307                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2308                                        HNS3_TQP_INTR_GL_DEFAULT);
2309                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2310                 /*
2311                  * QL(quantity limiter) is not used currently, just set 0 to
2312                  * close it.
2313                  */
2314                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2315
2316                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2317                                                  HNS3_RING_TYPE_TX, i);
2318                 if (ret) {
2319                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2320                                           "vector: %u, ret=%d", i, vec, ret);
2321                         return ret;
2322                 }
2323
2324                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2325                                                  HNS3_RING_TYPE_RX, i);
2326                 if (ret) {
2327                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2328                                           "vector: %u, ret=%d", i, vec, ret);
2329                         return ret;
2330                 }
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 hns3_dev_configure(struct rte_eth_dev *dev)
2338 {
2339         struct hns3_adapter *hns = dev->data->dev_private;
2340         struct rte_eth_conf *conf = &dev->data->dev_conf;
2341         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2342         struct hns3_hw *hw = &hns->hw;
2343         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2344         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2345         struct rte_eth_rss_conf rss_conf;
2346         uint32_t max_rx_pkt_len;
2347         uint16_t mtu;
2348         bool gro_en;
2349         int ret;
2350
2351         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2352
2353         /*
2354          * Some versions of hardware network engine does not support
2355          * individually enable/disable/reset the Tx or Rx queue. These devices
2356          * must enable/disable/reset Tx and Rx queues at the same time. When the
2357          * numbers of Tx queues allocated by upper applications are not equal to
2358          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2359          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2360          * work as usual. But these fake queues are imperceptible, and can not
2361          * be used by upper applications.
2362          */
2363         if (!hns3_dev_indep_txrx_supported(hw)) {
2364                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2365                 if (ret) {
2366                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2367                                  ret);
2368                         return ret;
2369                 }
2370         }
2371
2372         hw->adapter_state = HNS3_NIC_CONFIGURING;
2373         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2374                 hns3_err(hw, "setting link speed/duplex not supported");
2375                 ret = -EINVAL;
2376                 goto cfg_err;
2377         }
2378
2379         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2380                 ret = hns3_check_dcb_cfg(dev);
2381                 if (ret)
2382                         goto cfg_err;
2383         }
2384
2385         /* When RSS is not configured, redirect the packet queue 0 */
2386         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2387                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2388                 rss_conf = conf->rx_adv_conf.rss_conf;
2389                 hw->rss_dis_flag = false;
2390                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2391                 if (ret)
2392                         goto cfg_err;
2393         }
2394
2395         /*
2396          * If jumbo frames are enabled, MTU needs to be refreshed
2397          * according to the maximum RX packet length.
2398          */
2399         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2400                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2401                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2402                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2403                         hns3_err(hw, "maximum Rx packet length must be greater "
2404                                  "than %u and less than %u when jumbo frame enabled.",
2405                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2406                                  (uint16_t)HNS3_MAX_FRAME_LEN);
2407                         ret = -EINVAL;
2408                         goto cfg_err;
2409                 }
2410
2411                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2412                 ret = hns3_dev_mtu_set(dev, mtu);
2413                 if (ret)
2414                         goto cfg_err;
2415                 dev->data->mtu = mtu;
2416         }
2417
2418         ret = hns3_dev_configure_vlan(dev);
2419         if (ret)
2420                 goto cfg_err;
2421
2422         /* config hardware GRO */
2423         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2424         ret = hns3_config_gro(hw, gro_en);
2425         if (ret)
2426                 goto cfg_err;
2427
2428         hns->rx_simple_allowed = true;
2429         hns->rx_vec_allowed = true;
2430         hns->tx_simple_allowed = true;
2431         hns->tx_vec_allowed = true;
2432
2433         hns3_init_rx_ptype_tble(dev);
2434         hw->adapter_state = HNS3_NIC_CONFIGURED;
2435
2436         return 0;
2437
2438 cfg_err:
2439         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2440         hw->adapter_state = HNS3_NIC_INITIALIZED;
2441
2442         return ret;
2443 }
2444
2445 static int
2446 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2447 {
2448         struct hns3_config_max_frm_size_cmd *req;
2449         struct hns3_cmd_desc desc;
2450
2451         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2452
2453         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2454         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2455         req->min_frm_size = RTE_ETHER_MIN_LEN;
2456
2457         return hns3_cmd_send(hw, &desc, 1);
2458 }
2459
2460 static int
2461 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2462 {
2463         int ret;
2464
2465         ret = hns3_set_mac_mtu(hw, mps);
2466         if (ret) {
2467                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2468                 return ret;
2469         }
2470
2471         ret = hns3_buffer_alloc(hw);
2472         if (ret)
2473                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2474
2475         return ret;
2476 }
2477
2478 static int
2479 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2480 {
2481         struct hns3_adapter *hns = dev->data->dev_private;
2482         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2483         struct hns3_hw *hw = &hns->hw;
2484         bool is_jumbo_frame;
2485         int ret;
2486
2487         if (dev->data->dev_started) {
2488                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2489                          "before configuration", dev->data->port_id);
2490                 return -EBUSY;
2491         }
2492
2493         rte_spinlock_lock(&hw->lock);
2494         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2495         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2496
2497         /*
2498          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2499          * assign to "uint16_t" type variable.
2500          */
2501         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2502         if (ret) {
2503                 rte_spinlock_unlock(&hw->lock);
2504                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2505                          dev->data->port_id, mtu, ret);
2506                 return ret;
2507         }
2508         hns->pf.mps = (uint16_t)frame_size;
2509         if (is_jumbo_frame)
2510                 dev->data->dev_conf.rxmode.offloads |=
2511                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2512         else
2513                 dev->data->dev_conf.rxmode.offloads &=
2514                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2515         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2516         rte_spinlock_unlock(&hw->lock);
2517
2518         return 0;
2519 }
2520
2521 int
2522 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2523 {
2524         struct hns3_adapter *hns = eth_dev->data->dev_private;
2525         struct hns3_hw *hw = &hns->hw;
2526         uint16_t queue_num = hw->tqps_num;
2527
2528         /*
2529          * In interrupt mode, 'max_rx_queues' is set based on the number of
2530          * MSI-X interrupt resources of the hardware.
2531          */
2532         if (hw->data->dev_conf.intr_conf.rxq == 1)
2533                 queue_num = hw->intr_tqps_num;
2534
2535         info->max_rx_queues = queue_num;
2536         info->max_tx_queues = hw->tqps_num;
2537         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2538         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2539         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2540         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2541         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2542         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2543                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2544                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2545                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2546                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2547                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2548                                  DEV_RX_OFFLOAD_KEEP_CRC |
2549                                  DEV_RX_OFFLOAD_SCATTER |
2550                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2551                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2552                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2553                                  DEV_RX_OFFLOAD_RSS_HASH |
2554                                  DEV_RX_OFFLOAD_TCP_LRO);
2555         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2556                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2557                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2558                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2559                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2560                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2561                                  DEV_TX_OFFLOAD_TCP_TSO |
2562                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2563                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2564                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2565                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2566                                  hns3_txvlan_cap_get(hw));
2567
2568         if (hns3_dev_indep_txrx_supported(hw))
2569                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2570                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2571
2572         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2573                 .nb_max = HNS3_MAX_RING_DESC,
2574                 .nb_min = HNS3_MIN_RING_DESC,
2575                 .nb_align = HNS3_ALIGN_RING_DESC,
2576         };
2577
2578         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2579                 .nb_max = HNS3_MAX_RING_DESC,
2580                 .nb_min = HNS3_MIN_RING_DESC,
2581                 .nb_align = HNS3_ALIGN_RING_DESC,
2582                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2583                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2584         };
2585
2586         info->default_rxconf = (struct rte_eth_rxconf) {
2587                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2588                 /*
2589                  * If there are no available Rx buffer descriptors, incoming
2590                  * packets are always dropped by hardware based on hns3 network
2591                  * engine.
2592                  */
2593                 .rx_drop_en = 1,
2594                 .offloads = 0,
2595         };
2596         info->default_txconf = (struct rte_eth_txconf) {
2597                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2598                 .offloads = 0,
2599         };
2600
2601         info->vmdq_queue_num = 0;
2602
2603         info->reta_size = hw->rss_ind_tbl_size;
2604         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2605         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2606
2607         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2608         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2609         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2610         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2611         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2612         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2613
2614         return 0;
2615 }
2616
2617 static int
2618 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2619                     size_t fw_size)
2620 {
2621         struct hns3_adapter *hns = eth_dev->data->dev_private;
2622         struct hns3_hw *hw = &hns->hw;
2623         uint32_t version = hw->fw_version;
2624         int ret;
2625
2626         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2627                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2628                                       HNS3_FW_VERSION_BYTE3_S),
2629                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2630                                       HNS3_FW_VERSION_BYTE2_S),
2631                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2632                                       HNS3_FW_VERSION_BYTE1_S),
2633                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2634                                       HNS3_FW_VERSION_BYTE0_S));
2635         ret += 1; /* add the size of '\0' */
2636         if (fw_size < (uint32_t)ret)
2637                 return ret;
2638         else
2639                 return 0;
2640 }
2641
2642 static int
2643 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2644                      __rte_unused int wait_to_complete)
2645 {
2646         struct hns3_adapter *hns = eth_dev->data->dev_private;
2647         struct hns3_hw *hw = &hns->hw;
2648         struct hns3_mac *mac = &hw->mac;
2649         struct rte_eth_link new_link;
2650
2651         if (!hns3_is_reset_pending(hns)) {
2652                 hns3_update_link_status(hw);
2653                 hns3_update_link_info(eth_dev);
2654         }
2655
2656         memset(&new_link, 0, sizeof(new_link));
2657         switch (mac->link_speed) {
2658         case ETH_SPEED_NUM_10M:
2659         case ETH_SPEED_NUM_100M:
2660         case ETH_SPEED_NUM_1G:
2661         case ETH_SPEED_NUM_10G:
2662         case ETH_SPEED_NUM_25G:
2663         case ETH_SPEED_NUM_40G:
2664         case ETH_SPEED_NUM_50G:
2665         case ETH_SPEED_NUM_100G:
2666         case ETH_SPEED_NUM_200G:
2667                 new_link.link_speed = mac->link_speed;
2668                 break;
2669         default:
2670                 new_link.link_speed = ETH_SPEED_NUM_100M;
2671                 break;
2672         }
2673
2674         new_link.link_duplex = mac->link_duplex;
2675         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2676         new_link.link_autoneg =
2677             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2678
2679         return rte_eth_linkstatus_set(eth_dev, &new_link);
2680 }
2681
2682 static int
2683 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2684 {
2685         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2686         struct hns3_pf *pf = &hns->pf;
2687
2688         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2689                 return -EINVAL;
2690
2691         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2692
2693         return 0;
2694 }
2695
2696 static int
2697 hns3_query_function_status(struct hns3_hw *hw)
2698 {
2699 #define HNS3_QUERY_MAX_CNT              10
2700 #define HNS3_QUERY_SLEEP_MSCOEND        1
2701         struct hns3_func_status_cmd *req;
2702         struct hns3_cmd_desc desc;
2703         int timeout = 0;
2704         int ret;
2705
2706         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2707         req = (struct hns3_func_status_cmd *)desc.data;
2708
2709         do {
2710                 ret = hns3_cmd_send(hw, &desc, 1);
2711                 if (ret) {
2712                         PMD_INIT_LOG(ERR, "query function status failed %d",
2713                                      ret);
2714                         return ret;
2715                 }
2716
2717                 /* Check pf reset is done */
2718                 if (req->pf_state)
2719                         break;
2720
2721                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2722         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2723
2724         return hns3_parse_func_status(hw, req);
2725 }
2726
2727 static int
2728 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2729 {
2730         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2731         struct hns3_pf *pf = &hns->pf;
2732
2733         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2734                 /*
2735                  * The total_tqps_num obtained from firmware is maximum tqp
2736                  * numbers of this port, which should be used for PF and VFs.
2737                  * There is no need for pf to have so many tqp numbers in
2738                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2739                  * coming from config file, is assigned to maximum queue number
2740                  * for the PF of this port by user. So users can modify the
2741                  * maximum queue number of PF according to their own application
2742                  * scenarios, which is more flexible to use. In addition, many
2743                  * memories can be saved due to allocating queue statistics
2744                  * room according to the actual number of queues required. The
2745                  * maximum queue number of PF for network engine with
2746                  * revision_id greater than 0x30 is assigned by config file.
2747                  */
2748                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2749                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2750                                  "must be greater than 0.",
2751                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2752                         return -EINVAL;
2753                 }
2754
2755                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2756                                        hw->total_tqps_num);
2757         } else {
2758                 /*
2759                  * Due to the limitation on the number of PF interrupts
2760                  * available, the maximum queue number assigned to PF on
2761                  * the network engine with revision_id 0x21 is 64.
2762                  */
2763                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2764                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2765         }
2766
2767         return 0;
2768 }
2769
2770 static int
2771 hns3_query_pf_resource(struct hns3_hw *hw)
2772 {
2773         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2774         struct hns3_pf *pf = &hns->pf;
2775         struct hns3_pf_res_cmd *req;
2776         struct hns3_cmd_desc desc;
2777         int ret;
2778
2779         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2780         ret = hns3_cmd_send(hw, &desc, 1);
2781         if (ret) {
2782                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2783                 return ret;
2784         }
2785
2786         req = (struct hns3_pf_res_cmd *)desc.data;
2787         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2788                              rte_le_to_cpu_16(req->ext_tqp_num);
2789         ret = hns3_get_pf_max_tqp_num(hw);
2790         if (ret)
2791                 return ret;
2792
2793         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2794         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2795
2796         if (req->tx_buf_size)
2797                 pf->tx_buf_size =
2798                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2799         else
2800                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2801
2802         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2803
2804         if (req->dv_buf_size)
2805                 pf->dv_buf_size =
2806                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2807         else
2808                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2809
2810         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2811
2812         hw->num_msi =
2813                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2814                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2815
2816         return 0;
2817 }
2818
2819 static void
2820 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2821 {
2822         struct hns3_cfg_param_cmd *req;
2823         uint64_t mac_addr_tmp_high;
2824         uint8_t ext_rss_size_max;
2825         uint64_t mac_addr_tmp;
2826         uint32_t i;
2827
2828         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2829
2830         /* get the configuration */
2831         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2832                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2833         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2834                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2835         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2836                                            HNS3_CFG_TQP_DESC_N_M,
2837                                            HNS3_CFG_TQP_DESC_N_S);
2838
2839         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2840                                        HNS3_CFG_PHY_ADDR_M,
2841                                        HNS3_CFG_PHY_ADDR_S);
2842         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2843                                          HNS3_CFG_MEDIA_TP_M,
2844                                          HNS3_CFG_MEDIA_TP_S);
2845         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2846                                          HNS3_CFG_RX_BUF_LEN_M,
2847                                          HNS3_CFG_RX_BUF_LEN_S);
2848         /* get mac address */
2849         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2850         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2851                                            HNS3_CFG_MAC_ADDR_H_M,
2852                                            HNS3_CFG_MAC_ADDR_H_S);
2853
2854         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2855
2856         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2857                                             HNS3_CFG_DEFAULT_SPEED_M,
2858                                             HNS3_CFG_DEFAULT_SPEED_S);
2859         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2860                                            HNS3_CFG_RSS_SIZE_M,
2861                                            HNS3_CFG_RSS_SIZE_S);
2862
2863         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2864                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2865
2866         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2867         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2868
2869         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2870                                             HNS3_CFG_SPEED_ABILITY_M,
2871                                             HNS3_CFG_SPEED_ABILITY_S);
2872         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2873                                         HNS3_CFG_UMV_TBL_SPACE_M,
2874                                         HNS3_CFG_UMV_TBL_SPACE_S);
2875         if (!cfg->umv_space)
2876                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2877
2878         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2879                                                HNS3_CFG_EXT_RSS_SIZE_M,
2880                                                HNS3_CFG_EXT_RSS_SIZE_S);
2881
2882         /*
2883          * Field ext_rss_size_max obtained from firmware will be more flexible
2884          * for future changes and expansions, which is an exponent of 2, instead
2885          * of reading out directly. If this field is not zero, hns3 PF PMD
2886          * driver uses it as rss_size_max under one TC. Device, whose revision
2887          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2888          * maximum number of queues supported under a TC through this field.
2889          */
2890         if (ext_rss_size_max)
2891                 cfg->rss_size_max = 1U << ext_rss_size_max;
2892 }
2893
2894 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2895  * @hw: pointer to struct hns3_hw
2896  * @hcfg: the config structure to be getted
2897  */
2898 static int
2899 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2900 {
2901         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2902         struct hns3_cfg_param_cmd *req;
2903         uint32_t offset;
2904         uint32_t i;
2905         int ret;
2906
2907         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2908                 offset = 0;
2909                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2910                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2911                                           true);
2912                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2913                                i * HNS3_CFG_RD_LEN_BYTES);
2914                 /* Len should be divided by 4 when send to hardware */
2915                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2916                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2917                 req->offset = rte_cpu_to_le_32(offset);
2918         }
2919
2920         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2921         if (ret) {
2922                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2923                 return ret;
2924         }
2925
2926         hns3_parse_cfg(hcfg, desc);
2927
2928         return 0;
2929 }
2930
2931 static int
2932 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2933 {
2934         switch (speed_cmd) {
2935         case HNS3_CFG_SPEED_10M:
2936                 *speed = ETH_SPEED_NUM_10M;
2937                 break;
2938         case HNS3_CFG_SPEED_100M:
2939                 *speed = ETH_SPEED_NUM_100M;
2940                 break;
2941         case HNS3_CFG_SPEED_1G:
2942                 *speed = ETH_SPEED_NUM_1G;
2943                 break;
2944         case HNS3_CFG_SPEED_10G:
2945                 *speed = ETH_SPEED_NUM_10G;
2946                 break;
2947         case HNS3_CFG_SPEED_25G:
2948                 *speed = ETH_SPEED_NUM_25G;
2949                 break;
2950         case HNS3_CFG_SPEED_40G:
2951                 *speed = ETH_SPEED_NUM_40G;
2952                 break;
2953         case HNS3_CFG_SPEED_50G:
2954                 *speed = ETH_SPEED_NUM_50G;
2955                 break;
2956         case HNS3_CFG_SPEED_100G:
2957                 *speed = ETH_SPEED_NUM_100G;
2958                 break;
2959         case HNS3_CFG_SPEED_200G:
2960                 *speed = ETH_SPEED_NUM_200G;
2961                 break;
2962         default:
2963                 return -EINVAL;
2964         }
2965
2966         return 0;
2967 }
2968
2969 static void
2970 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2971 {
2972         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2973         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2974         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2975         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2976         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2977 }
2978
2979 static void
2980 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2981 {
2982         struct hns3_dev_specs_0_cmd *req0;
2983
2984         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2985
2986         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2987         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2988         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2989         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2990         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2991 }
2992
2993 static int
2994 hns3_check_dev_specifications(struct hns3_hw *hw)
2995 {
2996         if (hw->rss_ind_tbl_size == 0 ||
2997             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2998                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2999                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3000                               HNS3_RSS_IND_TBL_SIZE_MAX);
3001                 return -EINVAL;
3002         }
3003
3004         return 0;
3005 }
3006
3007 static int
3008 hns3_query_dev_specifications(struct hns3_hw *hw)
3009 {
3010         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3011         int ret;
3012         int i;
3013
3014         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3015                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3016                                           true);
3017                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3018         }
3019         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3020
3021         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3022         if (ret)
3023                 return ret;
3024
3025         hns3_parse_dev_specifications(hw, desc);
3026
3027         return hns3_check_dev_specifications(hw);
3028 }
3029
3030 static int
3031 hns3_get_capability(struct hns3_hw *hw)
3032 {
3033         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3034         struct rte_pci_device *pci_dev;
3035         struct hns3_pf *pf = &hns->pf;
3036         struct rte_eth_dev *eth_dev;
3037         uint16_t device_id;
3038         uint8_t revision;
3039         int ret;
3040
3041         eth_dev = &rte_eth_devices[hw->data->port_id];
3042         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3043         device_id = pci_dev->id.device_id;
3044
3045         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3046             device_id == HNS3_DEV_ID_50GE_RDMA ||
3047             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3048             device_id == HNS3_DEV_ID_200G_RDMA)
3049                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3050
3051         /* Get PCI revision id */
3052         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3053                                   HNS3_PCI_REVISION_ID);
3054         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3055                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3056                              ret);
3057                 return -EIO;
3058         }
3059         hw->revision = revision;
3060
3061         if (revision < PCI_REVISION_ID_HIP09_A) {
3062                 hns3_set_default_dev_specifications(hw);
3063                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3064                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3065                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3066                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3067                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3068                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3069                 hw->rss_info.ipv6_sctp_offload_supported = false;
3070                 return 0;
3071         }
3072
3073         ret = hns3_query_dev_specifications(hw);
3074         if (ret) {
3075                 PMD_INIT_LOG(ERR,
3076                              "failed to query dev specifications, ret = %d",
3077                              ret);
3078                 return ret;
3079         }
3080
3081         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3082         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3083         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3084         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3085         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3086         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3087         hw->rss_info.ipv6_sctp_offload_supported = true;
3088
3089         return 0;
3090 }
3091
3092 static int
3093 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3094 {
3095         int ret;
3096
3097         switch (media_type) {
3098         case HNS3_MEDIA_TYPE_COPPER:
3099                 if (!hns3_dev_copper_supported(hw)) {
3100                         PMD_INIT_LOG(ERR,
3101                                      "Media type is copper, not supported.");
3102                         ret = -EOPNOTSUPP;
3103                 } else {
3104                         ret = 0;
3105                 }
3106                 break;
3107         case HNS3_MEDIA_TYPE_FIBER:
3108                 ret = 0;
3109                 break;
3110         case HNS3_MEDIA_TYPE_BACKPLANE:
3111                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3112                 ret = -EOPNOTSUPP;
3113                 break;
3114         default:
3115                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3116                 ret = -EINVAL;
3117                 break;
3118         }
3119
3120         return ret;
3121 }
3122
3123 static int
3124 hns3_get_board_configuration(struct hns3_hw *hw)
3125 {
3126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3127         struct hns3_pf *pf = &hns->pf;
3128         struct hns3_cfg cfg;
3129         int ret;
3130
3131         ret = hns3_get_board_cfg(hw, &cfg);
3132         if (ret) {
3133                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3134                 return ret;
3135         }
3136
3137         ret = hns3_check_media_type(hw, cfg.media_type);
3138         if (ret)
3139                 return ret;
3140
3141         hw->mac.media_type = cfg.media_type;
3142         hw->rss_size_max = cfg.rss_size_max;
3143         hw->rss_dis_flag = false;
3144         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3145         hw->mac.phy_addr = cfg.phy_addr;
3146         hw->mac.default_addr_setted = false;
3147         hw->num_tx_desc = cfg.tqp_desc_num;
3148         hw->num_rx_desc = cfg.tqp_desc_num;
3149         hw->dcb_info.num_pg = 1;
3150         hw->dcb_info.hw_pfc_map = 0;
3151
3152         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3153         if (ret) {
3154                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3155                              cfg.default_speed, ret);
3156                 return ret;
3157         }
3158
3159         pf->tc_max = cfg.tc_num;
3160         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3161                 PMD_INIT_LOG(WARNING,
3162                              "Get TC num(%u) from flash, set TC num to 1",
3163                              pf->tc_max);
3164                 pf->tc_max = 1;
3165         }
3166
3167         /* Dev does not support DCB */
3168         if (!hns3_dev_dcb_supported(hw)) {
3169                 pf->tc_max = 1;
3170                 pf->pfc_max = 0;
3171         } else
3172                 pf->pfc_max = pf->tc_max;
3173
3174         hw->dcb_info.num_tc = 1;
3175         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3176                                      hw->tqps_num / hw->dcb_info.num_tc);
3177         hns3_set_bit(hw->hw_tc_map, 0, 1);
3178         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3179
3180         pf->wanted_umv_size = cfg.umv_space;
3181
3182         return ret;
3183 }
3184
3185 static int
3186 hns3_get_configuration(struct hns3_hw *hw)
3187 {
3188         int ret;
3189
3190         ret = hns3_query_function_status(hw);
3191         if (ret) {
3192                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3193                 return ret;
3194         }
3195
3196         /* Get device capability */
3197         ret = hns3_get_capability(hw);
3198         if (ret) {
3199                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3200                 return ret;
3201         }
3202
3203         /* Get pf resource */
3204         ret = hns3_query_pf_resource(hw);
3205         if (ret) {
3206                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3207                 return ret;
3208         }
3209
3210         ret = hns3_get_board_configuration(hw);
3211         if (ret) {
3212                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3213                 return ret;
3214         }
3215
3216         ret = hns3_query_dev_fec_info(hw);
3217         if (ret)
3218                 PMD_INIT_LOG(ERR,
3219                              "failed to query FEC information, ret = %d", ret);
3220
3221         return ret;
3222 }
3223
3224 static int
3225 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3226                       uint16_t tqp_vid, bool is_pf)
3227 {
3228         struct hns3_tqp_map_cmd *req;
3229         struct hns3_cmd_desc desc;
3230         int ret;
3231
3232         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3233
3234         req = (struct hns3_tqp_map_cmd *)desc.data;
3235         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3236         req->tqp_vf = func_id;
3237         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3238         if (!is_pf)
3239                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3240         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3241
3242         ret = hns3_cmd_send(hw, &desc, 1);
3243         if (ret)
3244                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3245
3246         return ret;
3247 }
3248
3249 static int
3250 hns3_map_tqp(struct hns3_hw *hw)
3251 {
3252         int ret;
3253         int i;
3254
3255         /*
3256          * In current version, VF is not supported when PF is driven by DPDK
3257          * driver, so we assign total tqps_num tqps allocated to this port
3258          * to PF.
3259          */
3260         for (i = 0; i < hw->total_tqps_num; i++) {
3261                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3262                 if (ret)
3263                         return ret;
3264         }
3265
3266         return 0;
3267 }
3268
3269 static int
3270 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3271 {
3272         struct hns3_config_mac_speed_dup_cmd *req;
3273         struct hns3_cmd_desc desc;
3274         int ret;
3275
3276         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3277
3278         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3279
3280         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3281
3282         switch (speed) {
3283         case ETH_SPEED_NUM_10M:
3284                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3285                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3286                 break;
3287         case ETH_SPEED_NUM_100M:
3288                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3289                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3290                 break;
3291         case ETH_SPEED_NUM_1G:
3292                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3293                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3294                 break;
3295         case ETH_SPEED_NUM_10G:
3296                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3297                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3298                 break;
3299         case ETH_SPEED_NUM_25G:
3300                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3301                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3302                 break;
3303         case ETH_SPEED_NUM_40G:
3304                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3305                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3306                 break;
3307         case ETH_SPEED_NUM_50G:
3308                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3309                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3310                 break;
3311         case ETH_SPEED_NUM_100G:
3312                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3313                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3314                 break;
3315         case ETH_SPEED_NUM_200G:
3316                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3317                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3318                 break;
3319         default:
3320                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3321                 return -EINVAL;
3322         }
3323
3324         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3325
3326         ret = hns3_cmd_send(hw, &desc, 1);
3327         if (ret)
3328                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3329
3330         return ret;
3331 }
3332
3333 static int
3334 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3335 {
3336         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3337         struct hns3_pf *pf = &hns->pf;
3338         struct hns3_priv_buf *priv;
3339         uint32_t i, total_size;
3340
3341         total_size = pf->pkt_buf_size;
3342
3343         /* alloc tx buffer for all enabled tc */
3344         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3345                 priv = &buf_alloc->priv_buf[i];
3346
3347                 if (hw->hw_tc_map & BIT(i)) {
3348                         if (total_size < pf->tx_buf_size)
3349                                 return -ENOMEM;
3350
3351                         priv->tx_buf_size = pf->tx_buf_size;
3352                 } else
3353                         priv->tx_buf_size = 0;
3354
3355                 total_size -= priv->tx_buf_size;
3356         }
3357
3358         return 0;
3359 }
3360
3361 static int
3362 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3363 {
3364 /* TX buffer size is unit by 128 byte */
3365 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3366 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3367         struct hns3_tx_buff_alloc_cmd *req;
3368         struct hns3_cmd_desc desc;
3369         uint32_t buf_size;
3370         uint32_t i;
3371         int ret;
3372
3373         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3374
3375         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3376         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3377                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3378
3379                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3380                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3381                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3382         }
3383
3384         ret = hns3_cmd_send(hw, &desc, 1);
3385         if (ret)
3386                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3387
3388         return ret;
3389 }
3390
3391 static int
3392 hns3_get_tc_num(struct hns3_hw *hw)
3393 {
3394         int cnt = 0;
3395         uint8_t i;
3396
3397         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3398                 if (hw->hw_tc_map & BIT(i))
3399                         cnt++;
3400         return cnt;
3401 }
3402
3403 static uint32_t
3404 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3405 {
3406         struct hns3_priv_buf *priv;
3407         uint32_t rx_priv = 0;
3408         int i;
3409
3410         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3411                 priv = &buf_alloc->priv_buf[i];
3412                 if (priv->enable)
3413                         rx_priv += priv->buf_size;
3414         }
3415         return rx_priv;
3416 }
3417
3418 static uint32_t
3419 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3420 {
3421         uint32_t total_tx_size = 0;
3422         uint32_t i;
3423
3424         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3425                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3426
3427         return total_tx_size;
3428 }
3429
3430 /* Get the number of pfc enabled TCs, which have private buffer */
3431 static int
3432 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3433 {
3434         struct hns3_priv_buf *priv;
3435         int cnt = 0;
3436         uint8_t i;
3437
3438         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3439                 priv = &buf_alloc->priv_buf[i];
3440                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3441                         cnt++;
3442         }
3443
3444         return cnt;
3445 }
3446
3447 /* Get the number of pfc disabled TCs, which have private buffer */
3448 static int
3449 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3450                          struct hns3_pkt_buf_alloc *buf_alloc)
3451 {
3452         struct hns3_priv_buf *priv;
3453         int cnt = 0;
3454         uint8_t i;
3455
3456         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3457                 priv = &buf_alloc->priv_buf[i];
3458                 if (hw->hw_tc_map & BIT(i) &&
3459                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3460                         cnt++;
3461         }
3462
3463         return cnt;
3464 }
3465
3466 static bool
3467 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3468                   uint32_t rx_all)
3469 {
3470         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3471         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3472         struct hns3_pf *pf = &hns->pf;
3473         uint32_t shared_buf, aligned_mps;
3474         uint32_t rx_priv;
3475         uint8_t tc_num;
3476         uint8_t i;
3477
3478         tc_num = hns3_get_tc_num(hw);
3479         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3480
3481         if (hns3_dev_dcb_supported(hw))
3482                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3483                                         pf->dv_buf_size;
3484         else
3485                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3486                                         + pf->dv_buf_size;
3487
3488         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3489         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3490                              HNS3_BUF_SIZE_UNIT);
3491
3492         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3493         if (rx_all < rx_priv + shared_std)
3494                 return false;
3495
3496         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3497         buf_alloc->s_buf.buf_size = shared_buf;
3498         if (hns3_dev_dcb_supported(hw)) {
3499                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3500                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3501                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3502                                   HNS3_BUF_SIZE_UNIT);
3503         } else {
3504                 buf_alloc->s_buf.self.high =
3505                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3506                 buf_alloc->s_buf.self.low = aligned_mps;
3507         }
3508
3509         if (hns3_dev_dcb_supported(hw)) {
3510                 hi_thrd = shared_buf - pf->dv_buf_size;
3511
3512                 if (tc_num <= NEED_RESERVE_TC_NUM)
3513                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3514                                   BUF_MAX_PERCENT;
3515
3516                 if (tc_num)
3517                         hi_thrd = hi_thrd / tc_num;
3518
3519                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3520                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3521                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3522         } else {
3523                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3524                 lo_thrd = aligned_mps;
3525         }
3526
3527         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3528                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3529                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3530         }
3531
3532         return true;
3533 }
3534
3535 static bool
3536 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3537                      struct hns3_pkt_buf_alloc *buf_alloc)
3538 {
3539         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3540         struct hns3_pf *pf = &hns->pf;
3541         struct hns3_priv_buf *priv;
3542         uint32_t aligned_mps;
3543         uint32_t rx_all;
3544         uint8_t i;
3545
3546         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3547         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3548
3549         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3550                 priv = &buf_alloc->priv_buf[i];
3551
3552                 priv->enable = 0;
3553                 priv->wl.low = 0;
3554                 priv->wl.high = 0;
3555                 priv->buf_size = 0;
3556
3557                 if (!(hw->hw_tc_map & BIT(i)))
3558                         continue;
3559
3560                 priv->enable = 1;
3561                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3562                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3563                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3564                                                 HNS3_BUF_SIZE_UNIT);
3565                 } else {
3566                         priv->wl.low = 0;
3567                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3568                                         aligned_mps;
3569                 }
3570
3571                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3572         }
3573
3574         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3575 }
3576
3577 static bool
3578 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3579                              struct hns3_pkt_buf_alloc *buf_alloc)
3580 {
3581         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3582         struct hns3_pf *pf = &hns->pf;
3583         struct hns3_priv_buf *priv;
3584         int no_pfc_priv_num;
3585         uint32_t rx_all;
3586         uint8_t mask;
3587         int i;
3588
3589         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3590         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3591
3592         /* let the last to be cleared first */
3593         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3594                 priv = &buf_alloc->priv_buf[i];
3595                 mask = BIT((uint8_t)i);
3596
3597                 if (hw->hw_tc_map & mask &&
3598                     !(hw->dcb_info.hw_pfc_map & mask)) {
3599                         /* Clear the no pfc TC private buffer */
3600                         priv->wl.low = 0;
3601                         priv->wl.high = 0;
3602                         priv->buf_size = 0;
3603                         priv->enable = 0;
3604                         no_pfc_priv_num--;
3605                 }
3606
3607                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3608                     no_pfc_priv_num == 0)
3609                         break;
3610         }
3611
3612         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3613 }
3614
3615 static bool
3616 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3617                            struct hns3_pkt_buf_alloc *buf_alloc)
3618 {
3619         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3620         struct hns3_pf *pf = &hns->pf;
3621         struct hns3_priv_buf *priv;
3622         uint32_t rx_all;
3623         int pfc_priv_num;
3624         uint8_t mask;
3625         int i;
3626
3627         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3628         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3629
3630         /* let the last to be cleared first */
3631         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3632                 priv = &buf_alloc->priv_buf[i];
3633                 mask = BIT((uint8_t)i);
3634                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3635                         /* Reduce the number of pfc TC with private buffer */
3636                         priv->wl.low = 0;
3637                         priv->enable = 0;
3638                         priv->wl.high = 0;
3639                         priv->buf_size = 0;
3640                         pfc_priv_num--;
3641                 }
3642                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3643                     pfc_priv_num == 0)
3644                         break;
3645         }
3646
3647         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3648 }
3649
3650 static bool
3651 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3652                           struct hns3_pkt_buf_alloc *buf_alloc)
3653 {
3654 #define COMPENSATE_BUFFER       0x3C00
3655 #define COMPENSATE_HALF_MPS_NUM 5
3656 #define PRIV_WL_GAP             0x1800
3657         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3658         struct hns3_pf *pf = &hns->pf;
3659         uint32_t tc_num = hns3_get_tc_num(hw);
3660         uint32_t half_mps = pf->mps >> 1;
3661         struct hns3_priv_buf *priv;
3662         uint32_t min_rx_priv;
3663         uint32_t rx_priv;
3664         uint8_t i;
3665
3666         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3667         if (tc_num)
3668                 rx_priv = rx_priv / tc_num;
3669
3670         if (tc_num <= NEED_RESERVE_TC_NUM)
3671                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3672
3673         /*
3674          * Minimum value of private buffer in rx direction (min_rx_priv) is
3675          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3676          * buffer if rx_priv is greater than min_rx_priv.
3677          */
3678         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3679                         COMPENSATE_HALF_MPS_NUM * half_mps;
3680         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3681         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3682
3683         if (rx_priv < min_rx_priv)
3684                 return false;
3685
3686         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3687                 priv = &buf_alloc->priv_buf[i];
3688                 priv->enable = 0;
3689                 priv->wl.low = 0;
3690                 priv->wl.high = 0;
3691                 priv->buf_size = 0;
3692
3693                 if (!(hw->hw_tc_map & BIT(i)))
3694                         continue;
3695
3696                 priv->enable = 1;
3697                 priv->buf_size = rx_priv;
3698                 priv->wl.high = rx_priv - pf->dv_buf_size;
3699                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3700         }
3701
3702         buf_alloc->s_buf.buf_size = 0;
3703
3704         return true;
3705 }
3706
3707 /*
3708  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3709  * @hw: pointer to struct hns3_hw
3710  * @buf_alloc: pointer to buffer calculation data
3711  * @return: 0: calculate sucessful, negative: fail
3712  */
3713 static int
3714 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3715 {
3716         /* When DCB is not supported, rx private buffer is not allocated. */
3717         if (!hns3_dev_dcb_supported(hw)) {
3718                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3719                 struct hns3_pf *pf = &hns->pf;
3720                 uint32_t rx_all = pf->pkt_buf_size;
3721
3722                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3723                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3724                         return -ENOMEM;
3725
3726                 return 0;
3727         }
3728
3729         /*
3730          * Try to allocate privated packet buffer for all TCs without share
3731          * buffer.
3732          */
3733         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3734                 return 0;
3735
3736         /*
3737          * Try to allocate privated packet buffer for all TCs with share
3738          * buffer.
3739          */
3740         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3741                 return 0;
3742
3743         /*
3744          * For different application scenes, the enabled port number, TC number
3745          * and no_drop TC number are different. In order to obtain the better
3746          * performance, software could allocate the buffer size and configure
3747          * the waterline by tring to decrease the private buffer size according
3748          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3749          * enabled tc.
3750          */
3751         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3752                 return 0;
3753
3754         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3755                 return 0;
3756
3757         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3758                 return 0;
3759
3760         return -ENOMEM;
3761 }
3762
3763 static int
3764 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3765 {
3766         struct hns3_rx_priv_buff_cmd *req;
3767         struct hns3_cmd_desc desc;
3768         uint32_t buf_size;
3769         int ret;
3770         int i;
3771
3772         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3773         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3774
3775         /* Alloc private buffer TCs */
3776         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3777                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3778
3779                 req->buf_num[i] =
3780                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3781                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3782         }
3783
3784         buf_size = buf_alloc->s_buf.buf_size;
3785         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3786                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3787
3788         ret = hns3_cmd_send(hw, &desc, 1);
3789         if (ret)
3790                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3791
3792         return ret;
3793 }
3794
3795 static int
3796 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3797 {
3798 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3799         struct hns3_rx_priv_wl_buf *req;
3800         struct hns3_priv_buf *priv;
3801         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3802         int i, j;
3803         int ret;
3804
3805         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3806                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3807                                           false);
3808                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3809
3810                 /* The first descriptor set the NEXT bit to 1 */
3811                 if (i == 0)
3812                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3813                 else
3814                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3815
3816                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3817                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3818
3819                         priv = &buf_alloc->priv_buf[idx];
3820                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3821                                                         HNS3_BUF_UNIT_S);
3822                         req->tc_wl[j].high |=
3823                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3824                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3825                                                         HNS3_BUF_UNIT_S);
3826                         req->tc_wl[j].low |=
3827                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3828                 }
3829         }
3830
3831         /* Send 2 descriptor at one time */
3832         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3833         if (ret)
3834                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3835                              ret);
3836         return ret;
3837 }
3838
3839 static int
3840 hns3_common_thrd_config(struct hns3_hw *hw,
3841                         struct hns3_pkt_buf_alloc *buf_alloc)
3842 {
3843 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3844         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3845         struct hns3_rx_com_thrd *req;
3846         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3847         struct hns3_tc_thrd *tc;
3848         int tc_idx;
3849         int i, j;
3850         int ret;
3851
3852         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3853                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3854                                           false);
3855                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3856
3857                 /* The first descriptor set the NEXT bit to 1 */
3858                 if (i == 0)
3859                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3860                 else
3861                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3862
3863                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3864                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3865                         tc = &s_buf->tc_thrd[tc_idx];
3866
3867                         req->com_thrd[j].high =
3868                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3869                         req->com_thrd[j].high |=
3870                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3871                         req->com_thrd[j].low =
3872                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3873                         req->com_thrd[j].low |=
3874                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3875                 }
3876         }
3877
3878         /* Send 2 descriptors at one time */
3879         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3880         if (ret)
3881                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3882
3883         return ret;
3884 }
3885
3886 static int
3887 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3888 {
3889         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3890         struct hns3_rx_com_wl *req;
3891         struct hns3_cmd_desc desc;
3892         int ret;
3893
3894         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3895
3896         req = (struct hns3_rx_com_wl *)desc.data;
3897         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3898         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3899
3900         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3901         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3902
3903         ret = hns3_cmd_send(hw, &desc, 1);
3904         if (ret)
3905                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3906
3907         return ret;
3908 }
3909
3910 int
3911 hns3_buffer_alloc(struct hns3_hw *hw)
3912 {
3913         struct hns3_pkt_buf_alloc pkt_buf;
3914         int ret;
3915
3916         memset(&pkt_buf, 0, sizeof(pkt_buf));
3917         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3918         if (ret) {
3919                 PMD_INIT_LOG(ERR,
3920                              "could not calc tx buffer size for all TCs %d",
3921                              ret);
3922                 return ret;
3923         }
3924
3925         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3926         if (ret) {
3927                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3928                 return ret;
3929         }
3930
3931         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3932         if (ret) {
3933                 PMD_INIT_LOG(ERR,
3934                              "could not calc rx priv buffer size for all TCs %d",
3935                              ret);
3936                 return ret;
3937         }
3938
3939         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3940         if (ret) {
3941                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3942                 return ret;
3943         }
3944
3945         if (hns3_dev_dcb_supported(hw)) {
3946                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3947                 if (ret) {
3948                         PMD_INIT_LOG(ERR,
3949                                      "could not configure rx private waterline %d",
3950                                      ret);
3951                         return ret;
3952                 }
3953
3954                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3955                 if (ret) {
3956                         PMD_INIT_LOG(ERR,
3957                                      "could not configure common threshold %d",
3958                                      ret);
3959                         return ret;
3960                 }
3961         }
3962
3963         ret = hns3_common_wl_config(hw, &pkt_buf);
3964         if (ret)
3965                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3966                              ret);
3967
3968         return ret;
3969 }
3970
3971 static int
3972 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
3973 {
3974         struct hns3_firmware_compat_cmd *req;
3975         struct hns3_cmd_desc desc;
3976         uint32_t compat = 0;
3977
3978         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
3979         req = (struct hns3_firmware_compat_cmd *)desc.data;
3980
3981         if (is_init) {
3982                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
3983                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
3984                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
3985                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
3986         }
3987
3988         req->compat = rte_cpu_to_le_32(compat);
3989
3990         return hns3_cmd_send(hw, &desc, 1);
3991 }
3992
3993 static int
3994 hns3_mac_init(struct hns3_hw *hw)
3995 {
3996         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3997         struct hns3_mac *mac = &hw->mac;
3998         struct hns3_pf *pf = &hns->pf;
3999         int ret;
4000
4001         pf->support_sfp_query = true;
4002         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4003         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4004         if (ret) {
4005                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4006                 return ret;
4007         }
4008
4009         mac->link_status = ETH_LINK_DOWN;
4010
4011         return hns3_config_mtu(hw, pf->mps);
4012 }
4013
4014 static int
4015 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4016 {
4017 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4018 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4019 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4020 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4021         int return_status;
4022
4023         if (cmdq_resp) {
4024                 PMD_INIT_LOG(ERR,
4025                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4026                              cmdq_resp);
4027                 return -EIO;
4028         }
4029
4030         switch (resp_code) {
4031         case HNS3_ETHERTYPE_SUCCESS_ADD:
4032         case HNS3_ETHERTYPE_ALREADY_ADD:
4033                 return_status = 0;
4034                 break;
4035         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4036                 PMD_INIT_LOG(ERR,
4037                              "add mac ethertype failed for manager table overflow.");
4038                 return_status = -EIO;
4039                 break;
4040         case HNS3_ETHERTYPE_KEY_CONFLICT:
4041                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4042                 return_status = -EIO;
4043                 break;
4044         default:
4045                 PMD_INIT_LOG(ERR,
4046                              "add mac ethertype failed for undefined, code=%u.",
4047                              resp_code);
4048                 return_status = -EIO;
4049                 break;
4050         }
4051
4052         return return_status;
4053 }
4054
4055 static int
4056 hns3_add_mgr_tbl(struct hns3_hw *hw,
4057                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4058 {
4059         struct hns3_cmd_desc desc;
4060         uint8_t resp_code;
4061         uint16_t retval;
4062         int ret;
4063
4064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4065         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4066
4067         ret = hns3_cmd_send(hw, &desc, 1);
4068         if (ret) {
4069                 PMD_INIT_LOG(ERR,
4070                              "add mac ethertype failed for cmd_send, ret =%d.",
4071                              ret);
4072                 return ret;
4073         }
4074
4075         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4076         retval = rte_le_to_cpu_16(desc.retval);
4077
4078         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4079 }
4080
4081 static void
4082 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4083                      int *table_item_num)
4084 {
4085         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4086
4087         /*
4088          * In current version, we add one item in management table as below:
4089          * 0x0180C200000E -- LLDP MC address
4090          */
4091         tbl = mgr_table;
4092         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4093         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4094         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4095         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4096         tbl->i_port_bitmap = 0x1;
4097         *table_item_num = 1;
4098 }
4099
4100 static int
4101 hns3_init_mgr_tbl(struct hns3_hw *hw)
4102 {
4103 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4104         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4105         int table_item_num;
4106         int ret;
4107         int i;
4108
4109         memset(mgr_table, 0, sizeof(mgr_table));
4110         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4111         for (i = 0; i < table_item_num; i++) {
4112                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4113                 if (ret) {
4114                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4115                                      ret);
4116                         return ret;
4117                 }
4118         }
4119
4120         return 0;
4121 }
4122
4123 static void
4124 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4125                         bool en_mc, bool en_bc, int vport_id)
4126 {
4127         if (!param)
4128                 return;
4129
4130         memset(param, 0, sizeof(struct hns3_promisc_param));
4131         if (en_uc)
4132                 param->enable = HNS3_PROMISC_EN_UC;
4133         if (en_mc)
4134                 param->enable |= HNS3_PROMISC_EN_MC;
4135         if (en_bc)
4136                 param->enable |= HNS3_PROMISC_EN_BC;
4137         param->vf_id = vport_id;
4138 }
4139
4140 static int
4141 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4142 {
4143         struct hns3_promisc_cfg_cmd *req;
4144         struct hns3_cmd_desc desc;
4145         int ret;
4146
4147         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4148
4149         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4150         req->vf_id = param->vf_id;
4151         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4152             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4153
4154         ret = hns3_cmd_send(hw, &desc, 1);
4155         if (ret)
4156                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4157
4158         return ret;
4159 }
4160
4161 static int
4162 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4163 {
4164         struct hns3_promisc_param param;
4165         bool en_bc_pmc = true;
4166         uint8_t vf_id;
4167
4168         /*
4169          * In current version VF is not supported when PF is driven by DPDK
4170          * driver, just need to configure parameters for PF vport.
4171          */
4172         vf_id = HNS3_PF_FUNC_ID;
4173
4174         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4175         return hns3_cmd_set_promisc_mode(hw, &param);
4176 }
4177
4178 static int
4179 hns3_promisc_init(struct hns3_hw *hw)
4180 {
4181         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4182         struct hns3_pf *pf = &hns->pf;
4183         struct hns3_promisc_param param;
4184         uint16_t func_id;
4185         int ret;
4186
4187         ret = hns3_set_promisc_mode(hw, false, false);
4188         if (ret) {
4189                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4190                 return ret;
4191         }
4192
4193         /*
4194          * In current version VFs are not supported when PF is driven by DPDK
4195          * driver. After PF has been taken over by DPDK, the original VF will
4196          * be invalid. So, there is a possibility of entry residues. It should
4197          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4198          * during init.
4199          */
4200         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4201                 hns3_promisc_param_init(&param, false, false, false, func_id);
4202                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4203                 if (ret) {
4204                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4205                                         " ret = %d", func_id, ret);
4206                         return ret;
4207                 }
4208         }
4209
4210         return 0;
4211 }
4212
4213 static void
4214 hns3_promisc_uninit(struct hns3_hw *hw)
4215 {
4216         struct hns3_promisc_param param;
4217         uint16_t func_id;
4218         int ret;
4219
4220         func_id = HNS3_PF_FUNC_ID;
4221
4222         /*
4223          * In current version VFs are not supported when PF is driven by
4224          * DPDK driver, and VFs' promisc mode status has been cleared during
4225          * init and their status will not change. So just clear PF's promisc
4226          * mode status during uninit.
4227          */
4228         hns3_promisc_param_init(&param, false, false, false, func_id);
4229         ret = hns3_cmd_set_promisc_mode(hw, &param);
4230         if (ret)
4231                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4232                                 " uninit, ret = %d", ret);
4233 }
4234
4235 static int
4236 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4237 {
4238         bool allmulti = dev->data->all_multicast ? true : false;
4239         struct hns3_adapter *hns = dev->data->dev_private;
4240         struct hns3_hw *hw = &hns->hw;
4241         uint64_t offloads;
4242         int err;
4243         int ret;
4244
4245         rte_spinlock_lock(&hw->lock);
4246         ret = hns3_set_promisc_mode(hw, true, true);
4247         if (ret) {
4248                 rte_spinlock_unlock(&hw->lock);
4249                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4250                          ret);
4251                 return ret;
4252         }
4253
4254         /*
4255          * When promiscuous mode was enabled, disable the vlan filter to let
4256          * all packets coming in in the receiving direction.
4257          */
4258         offloads = dev->data->dev_conf.rxmode.offloads;
4259         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4260                 ret = hns3_enable_vlan_filter(hns, false);
4261                 if (ret) {
4262                         hns3_err(hw, "failed to enable promiscuous mode due to "
4263                                      "failure to disable vlan filter, ret = %d",
4264                                  ret);
4265                         err = hns3_set_promisc_mode(hw, false, allmulti);
4266                         if (err)
4267                                 hns3_err(hw, "failed to restore promiscuous "
4268                                          "status after disable vlan filter "
4269                                          "failed during enabling promiscuous "
4270                                          "mode, ret = %d", ret);
4271                 }
4272         }
4273
4274         rte_spinlock_unlock(&hw->lock);
4275
4276         return ret;
4277 }
4278
4279 static int
4280 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4281 {
4282         bool allmulti = dev->data->all_multicast ? true : false;
4283         struct hns3_adapter *hns = dev->data->dev_private;
4284         struct hns3_hw *hw = &hns->hw;
4285         uint64_t offloads;
4286         int err;
4287         int ret;
4288
4289         /* If now in all_multicast mode, must remain in all_multicast mode. */
4290         rte_spinlock_lock(&hw->lock);
4291         ret = hns3_set_promisc_mode(hw, false, allmulti);
4292         if (ret) {
4293                 rte_spinlock_unlock(&hw->lock);
4294                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4295                          ret);
4296                 return ret;
4297         }
4298         /* when promiscuous mode was disabled, restore the vlan filter status */
4299         offloads = dev->data->dev_conf.rxmode.offloads;
4300         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4301                 ret = hns3_enable_vlan_filter(hns, true);
4302                 if (ret) {
4303                         hns3_err(hw, "failed to disable promiscuous mode due to"
4304                                  " failure to restore vlan filter, ret = %d",
4305                                  ret);
4306                         err = hns3_set_promisc_mode(hw, true, true);
4307                         if (err)
4308                                 hns3_err(hw, "failed to restore promiscuous "
4309                                          "status after enabling vlan filter "
4310                                          "failed during disabling promiscuous "
4311                                          "mode, ret = %d", ret);
4312                 }
4313         }
4314         rte_spinlock_unlock(&hw->lock);
4315
4316         return ret;
4317 }
4318
4319 static int
4320 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4321 {
4322         struct hns3_adapter *hns = dev->data->dev_private;
4323         struct hns3_hw *hw = &hns->hw;
4324         int ret;
4325
4326         if (dev->data->promiscuous)
4327                 return 0;
4328
4329         rte_spinlock_lock(&hw->lock);
4330         ret = hns3_set_promisc_mode(hw, false, true);
4331         rte_spinlock_unlock(&hw->lock);
4332         if (ret)
4333                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4334                          ret);
4335
4336         return ret;
4337 }
4338
4339 static int
4340 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4341 {
4342         struct hns3_adapter *hns = dev->data->dev_private;
4343         struct hns3_hw *hw = &hns->hw;
4344         int ret;
4345
4346         /* If now in promiscuous mode, must remain in all_multicast mode. */
4347         if (dev->data->promiscuous)
4348                 return 0;
4349
4350         rte_spinlock_lock(&hw->lock);
4351         ret = hns3_set_promisc_mode(hw, false, false);
4352         rte_spinlock_unlock(&hw->lock);
4353         if (ret)
4354                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4355                          ret);
4356
4357         return ret;
4358 }
4359
4360 static int
4361 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4362 {
4363         struct hns3_hw *hw = &hns->hw;
4364         bool allmulti = hw->data->all_multicast ? true : false;
4365         int ret;
4366
4367         if (hw->data->promiscuous) {
4368                 ret = hns3_set_promisc_mode(hw, true, true);
4369                 if (ret)
4370                         hns3_err(hw, "failed to restore promiscuous mode, "
4371                                  "ret = %d", ret);
4372                 return ret;
4373         }
4374
4375         ret = hns3_set_promisc_mode(hw, false, allmulti);
4376         if (ret)
4377                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4378                          ret);
4379         return ret;
4380 }
4381
4382 static int
4383 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4384 {
4385         struct hns3_sfp_speed_cmd *resp;
4386         struct hns3_cmd_desc desc;
4387         int ret;
4388
4389         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4390         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4391         ret = hns3_cmd_send(hw, &desc, 1);
4392         if (ret == -EOPNOTSUPP) {
4393                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4394                 return ret;
4395         } else if (ret) {
4396                 hns3_err(hw, "get sfp speed failed %d", ret);
4397                 return ret;
4398         }
4399
4400         *speed = resp->sfp_speed;
4401
4402         return 0;
4403 }
4404
4405 static uint8_t
4406 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4407 {
4408         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4409                 duplex = ETH_LINK_FULL_DUPLEX;
4410
4411         return duplex;
4412 }
4413
4414 static int
4415 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4416 {
4417         struct hns3_mac *mac = &hw->mac;
4418         int ret;
4419
4420         duplex = hns3_check_speed_dup(duplex, speed);
4421         if (mac->link_speed == speed && mac->link_duplex == duplex)
4422                 return 0;
4423
4424         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4425         if (ret)
4426                 return ret;
4427
4428         ret = hns3_port_shaper_update(hw, speed);
4429         if (ret)
4430                 return ret;
4431
4432         mac->link_speed = speed;
4433         mac->link_duplex = duplex;
4434
4435         return 0;
4436 }
4437
4438 static int
4439 hns3_update_fiber_link_info(struct hns3_hw *hw)
4440 {
4441         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4442         uint32_t speed;
4443         int ret;
4444
4445         /* If IMP do not support get SFP/qSFP speed, return directly */
4446         if (!pf->support_sfp_query)
4447                 return 0;
4448
4449         ret = hns3_get_sfp_speed(hw, &speed);
4450         if (ret == -EOPNOTSUPP) {
4451                 pf->support_sfp_query = false;
4452                 return ret;
4453         } else if (ret)
4454                 return ret;
4455
4456         if (speed == ETH_SPEED_NUM_NONE)
4457                 return 0; /* do nothing if no SFP */
4458
4459         /* Config full duplex for SFP */
4460         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4461 }
4462
4463 static void
4464 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4465 {
4466         struct hns3_phy_params_bd0_cmd *req;
4467
4468         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4469         mac->link_speed = rte_le_to_cpu_32(req->speed);
4470         mac->link_duplex = hns3_get_bit(req->duplex,
4471                                            HNS3_PHY_DUPLEX_CFG_B);
4472         mac->link_autoneg = hns3_get_bit(req->autoneg,
4473                                            HNS3_PHY_AUTONEG_CFG_B);
4474         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4475         mac->advertising = rte_le_to_cpu_32(req->advertising);
4476         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4477         mac->support_autoneg = !!(mac->supported_capa &
4478                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4479 }
4480
4481 static int
4482 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4483 {
4484         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4485         uint16_t i;
4486         int ret;
4487
4488         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4489                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4490                                           true);
4491                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4492         }
4493         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4494
4495         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4496         if (ret) {
4497                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4498                 return ret;
4499         }
4500
4501         hns3_parse_phy_params(desc, mac);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 hns3_update_phy_link_info(struct hns3_hw *hw)
4508 {
4509         struct hns3_mac *mac = &hw->mac;
4510         struct hns3_mac mac_info;
4511         int ret;
4512
4513         memset(&mac_info, 0, sizeof(struct hns3_mac));
4514         ret = hns3_get_phy_params(hw, &mac_info);
4515         if (ret)
4516                 return ret;
4517
4518         if (mac_info.link_speed != mac->link_speed) {
4519                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4520                 if (ret)
4521                         return ret;
4522         }
4523
4524         mac->link_speed = mac_info.link_speed;
4525         mac->link_duplex = mac_info.link_duplex;
4526         mac->link_autoneg = mac_info.link_autoneg;
4527         mac->supported_capa = mac_info.supported_capa;
4528         mac->advertising = mac_info.advertising;
4529         mac->lp_advertising = mac_info.lp_advertising;
4530         mac->support_autoneg = mac_info.support_autoneg;
4531
4532         return 0;
4533 }
4534
4535 static int
4536 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4537 {
4538         struct hns3_adapter *hns = eth_dev->data->dev_private;
4539         struct hns3_hw *hw = &hns->hw;
4540         int ret = 0;
4541
4542         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4543                 ret = hns3_update_phy_link_info(hw);
4544         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4545                 ret = hns3_update_fiber_link_info(hw);
4546
4547         return ret;
4548 }
4549
4550 static int
4551 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4552 {
4553         struct hns3_config_mac_mode_cmd *req;
4554         struct hns3_cmd_desc desc;
4555         uint32_t loop_en = 0;
4556         uint8_t val = 0;
4557         int ret;
4558
4559         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4560
4561         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4562         if (enable)
4563                 val = 1;
4564         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4565         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4566         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4567         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4568         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4569         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4570         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4571         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4572         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4573         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4574
4575         /*
4576          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4577          * when receiving frames. Otherwise, CRC will be stripped.
4578          */
4579         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4580                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4581         else
4582                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4583         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4584         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4585         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4586         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4587
4588         ret = hns3_cmd_send(hw, &desc, 1);
4589         if (ret)
4590                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4591
4592         return ret;
4593 }
4594
4595 static int
4596 hns3_get_mac_link_status(struct hns3_hw *hw)
4597 {
4598         struct hns3_link_status_cmd *req;
4599         struct hns3_cmd_desc desc;
4600         int link_status;
4601         int ret;
4602
4603         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4604         ret = hns3_cmd_send(hw, &desc, 1);
4605         if (ret) {
4606                 hns3_err(hw, "get link status cmd failed %d", ret);
4607                 return ETH_LINK_DOWN;
4608         }
4609
4610         req = (struct hns3_link_status_cmd *)desc.data;
4611         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4612
4613         return !!link_status;
4614 }
4615
4616 static bool
4617 hns3_update_link_status(struct hns3_hw *hw)
4618 {
4619         int state;
4620
4621         state = hns3_get_mac_link_status(hw);
4622         if (state != hw->mac.link_status) {
4623                 hw->mac.link_status = state;
4624                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4625                 return true;
4626         }
4627
4628         return false;
4629 }
4630
4631 /*
4632  * Current, the PF driver get link status by two ways:
4633  * 1) Periodic polling in the intr thread context, driver call
4634  *    hns3_update_link_status to update link status.
4635  * 2) Firmware report async interrupt, driver process the event in the intr
4636  *    thread context, and call hns3_update_link_status to update link status.
4637  *
4638  * If detect link status changed, driver need report LSE. One method is add the
4639  * report LSE logic in hns3_update_link_status.
4640  *
4641  * But the PF driver ops(link_update) also call hns3_update_link_status to
4642  * update link status.
4643  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4644  * bonding application.
4645  *
4646  * So add the one new API which used only in intr thread context.
4647  */
4648 void
4649 hns3_update_link_status_and_event(struct hns3_hw *hw)
4650 {
4651         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4652         bool changed = hns3_update_link_status(hw);
4653         if (changed)
4654                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4655 }
4656
4657 static void
4658 hns3_service_handler(void *param)
4659 {
4660         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4661         struct hns3_adapter *hns = eth_dev->data->dev_private;
4662         struct hns3_hw *hw = &hns->hw;
4663
4664         if (!hns3_is_reset_pending(hns)) {
4665                 hns3_update_link_status_and_event(hw);
4666                 hns3_update_link_info(eth_dev);
4667         } else {
4668                 hns3_warn(hw, "Cancel the query when reset is pending");
4669         }
4670
4671         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4672 }
4673
4674 static int
4675 hns3_init_hardware(struct hns3_adapter *hns)
4676 {
4677         struct hns3_hw *hw = &hns->hw;
4678         int ret;
4679
4680         ret = hns3_map_tqp(hw);
4681         if (ret) {
4682                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4683                 return ret;
4684         }
4685
4686         ret = hns3_init_umv_space(hw);
4687         if (ret) {
4688                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4689                 return ret;
4690         }
4691
4692         ret = hns3_mac_init(hw);
4693         if (ret) {
4694                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4695                 goto err_mac_init;
4696         }
4697
4698         ret = hns3_init_mgr_tbl(hw);
4699         if (ret) {
4700                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4701                 goto err_mac_init;
4702         }
4703
4704         ret = hns3_promisc_init(hw);
4705         if (ret) {
4706                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4707                              ret);
4708                 goto err_mac_init;
4709         }
4710
4711         ret = hns3_init_vlan_config(hns);
4712         if (ret) {
4713                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4714                 goto err_mac_init;
4715         }
4716
4717         ret = hns3_dcb_init(hw);
4718         if (ret) {
4719                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4720                 goto err_mac_init;
4721         }
4722
4723         ret = hns3_init_fd_config(hns);
4724         if (ret) {
4725                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4726                 goto err_mac_init;
4727         }
4728
4729         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4730         if (ret) {
4731                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4732                 goto err_mac_init;
4733         }
4734
4735         ret = hns3_config_gro(hw, false);
4736         if (ret) {
4737                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4738                 goto err_mac_init;
4739         }
4740
4741         /*
4742          * In the initialization clearing the all hardware mapping relationship
4743          * configurations between queues and interrupt vectors is needed, so
4744          * some error caused by the residual configurations, such as the
4745          * unexpected interrupt, can be avoid.
4746          */
4747         ret = hns3_init_ring_with_vector(hw);
4748         if (ret) {
4749                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4750                 goto err_mac_init;
4751         }
4752
4753         /*
4754          * Requiring firmware to enable some features, driver can
4755          * still work without it.
4756          */
4757         ret = hns3_firmware_compat_config(hw, true);
4758         if (ret)
4759                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4760                              "supported, ret = %d.", ret);
4761
4762         return 0;
4763
4764 err_mac_init:
4765         hns3_uninit_umv_space(hw);
4766         return ret;
4767 }
4768
4769 static int
4770 hns3_clear_hw(struct hns3_hw *hw)
4771 {
4772         struct hns3_cmd_desc desc;
4773         int ret;
4774
4775         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4776
4777         ret = hns3_cmd_send(hw, &desc, 1);
4778         if (ret && ret != -EOPNOTSUPP)
4779                 return ret;
4780
4781         return 0;
4782 }
4783
4784 static void
4785 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4786 {
4787         uint32_t val;
4788
4789         /*
4790          * The new firmware support report more hardware error types by
4791          * msix mode. These errors are defined as RAS errors in hardware
4792          * and belong to a different type from the MSI-x errors processed
4793          * by the network driver.
4794          *
4795          * Network driver should open the new error report on initialition
4796          */
4797         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4798         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4799         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4800 }
4801
4802 static int
4803 hns3_init_pf(struct rte_eth_dev *eth_dev)
4804 {
4805         struct rte_device *dev = eth_dev->device;
4806         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4807         struct hns3_adapter *hns = eth_dev->data->dev_private;
4808         struct hns3_hw *hw = &hns->hw;
4809         int ret;
4810
4811         PMD_INIT_FUNC_TRACE();
4812
4813         /* Get hardware io base address from pcie BAR2 IO space */
4814         hw->io_base = pci_dev->mem_resource[2].addr;
4815
4816         /* Firmware command queue initialize */
4817         ret = hns3_cmd_init_queue(hw);
4818         if (ret) {
4819                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4820                 goto err_cmd_init_queue;
4821         }
4822
4823         hns3_clear_all_event_cause(hw);
4824
4825         /* Firmware command initialize */
4826         ret = hns3_cmd_init(hw);
4827         if (ret) {
4828                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4829                 goto err_cmd_init;
4830         }
4831
4832         /*
4833          * To ensure that the hardware environment is clean during
4834          * initialization, the driver actively clear the hardware environment
4835          * during initialization, including PF and corresponding VFs' vlan, mac,
4836          * flow table configurations, etc.
4837          */
4838         ret = hns3_clear_hw(hw);
4839         if (ret) {
4840                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4841                 goto err_cmd_init;
4842         }
4843
4844         /* Hardware statistics of imissed registers cleared. */
4845         ret = hns3_update_imissed_stats(hw, true);
4846         if (ret) {
4847                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4848                 return ret;
4849         }
4850
4851         hns3_config_all_msix_error(hw, true);
4852
4853         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4854                                          hns3_interrupt_handler,
4855                                          eth_dev);
4856         if (ret) {
4857                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4858                 goto err_intr_callback_register;
4859         }
4860
4861         /* Enable interrupt */
4862         rte_intr_enable(&pci_dev->intr_handle);
4863         hns3_pf_enable_irq0(hw);
4864
4865         /* Get configuration */
4866         ret = hns3_get_configuration(hw);
4867         if (ret) {
4868                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4869                 goto err_get_config;
4870         }
4871
4872         ret = hns3_tqp_stats_init(hw);
4873         if (ret)
4874                 goto err_get_config;
4875
4876         ret = hns3_init_hardware(hns);
4877         if (ret) {
4878                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4879                 goto err_init_hw;
4880         }
4881
4882         /* Initialize flow director filter list & hash */
4883         ret = hns3_fdir_filter_init(hns);
4884         if (ret) {
4885                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4886                 goto err_fdir;
4887         }
4888
4889         hns3_rss_set_default_args(hw);
4890
4891         ret = hns3_enable_hw_error_intr(hns, true);
4892         if (ret) {
4893                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4894                              ret);
4895                 goto err_enable_intr;
4896         }
4897
4898         hns3_tm_conf_init(eth_dev);
4899
4900         return 0;
4901
4902 err_enable_intr:
4903         hns3_fdir_filter_uninit(hns);
4904 err_fdir:
4905         (void)hns3_firmware_compat_config(hw, false);
4906         hns3_uninit_umv_space(hw);
4907 err_init_hw:
4908         hns3_tqp_stats_uninit(hw);
4909 err_get_config:
4910         hns3_pf_disable_irq0(hw);
4911         rte_intr_disable(&pci_dev->intr_handle);
4912         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4913                              eth_dev);
4914 err_intr_callback_register:
4915 err_cmd_init:
4916         hns3_cmd_uninit(hw);
4917         hns3_cmd_destroy_queue(hw);
4918 err_cmd_init_queue:
4919         hw->io_base = NULL;
4920
4921         return ret;
4922 }
4923
4924 static void
4925 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4926 {
4927         struct hns3_adapter *hns = eth_dev->data->dev_private;
4928         struct rte_device *dev = eth_dev->device;
4929         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4930         struct hns3_hw *hw = &hns->hw;
4931
4932         PMD_INIT_FUNC_TRACE();
4933
4934         hns3_tm_conf_uninit(eth_dev);
4935         hns3_enable_hw_error_intr(hns, false);
4936         hns3_rss_uninit(hns);
4937         (void)hns3_config_gro(hw, false);
4938         hns3_promisc_uninit(hw);
4939         hns3_fdir_filter_uninit(hns);
4940         (void)hns3_firmware_compat_config(hw, false);
4941         hns3_uninit_umv_space(hw);
4942         hns3_tqp_stats_uninit(hw);
4943         hns3_pf_disable_irq0(hw);
4944         rte_intr_disable(&pci_dev->intr_handle);
4945         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4946                              eth_dev);
4947         hns3_config_all_msix_error(hw, false);
4948         hns3_cmd_uninit(hw);
4949         hns3_cmd_destroy_queue(hw);
4950         hw->io_base = NULL;
4951 }
4952
4953 static int
4954 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4955 {
4956         struct hns3_hw *hw = &hns->hw;
4957         int ret;
4958
4959         ret = hns3_dcb_cfg_update(hns);
4960         if (ret)
4961                 return ret;
4962
4963         /*
4964          * The hns3_dcb_cfg_update may configure TM module, so
4965          * hns3_tm_conf_update must called later.
4966          */
4967         ret = hns3_tm_conf_update(hw);
4968         if (ret) {
4969                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4970                 return ret;
4971         }
4972
4973         ret = hns3_init_queues(hns, reset_queue);
4974         if (ret) {
4975                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4976                 return ret;
4977         }
4978
4979         ret = hns3_cfg_mac_mode(hw, true);
4980         if (ret) {
4981                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4982                 goto err_config_mac_mode;
4983         }
4984         return 0;
4985
4986 err_config_mac_mode:
4987         hns3_dev_release_mbufs(hns);
4988         /*
4989          * Here is exception handling, hns3_reset_all_tqps will have the
4990          * corresponding error message if it is handled incorrectly, so it is
4991          * not necessary to check hns3_reset_all_tqps return value, here keep
4992          * ret as the error code causing the exception.
4993          */
4994         (void)hns3_reset_all_tqps(hns);
4995         return ret;
4996 }
4997
4998 static int
4999 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5000 {
5001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5003         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5005         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5006         uint32_t intr_vector;
5007         uint16_t q_id;
5008         int ret;
5009
5010         /*
5011          * hns3 needs a separate interrupt to be used as event interrupt which
5012          * could not be shared with task queue pair, so KERNEL drivers need
5013          * support multiple interrupt vectors.
5014          */
5015         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5016             !rte_intr_cap_multiple(intr_handle))
5017                 return 0;
5018
5019         rte_intr_disable(intr_handle);
5020         intr_vector = hw->used_rx_queues;
5021         /* creates event fd for each intr vector when MSIX is used */
5022         if (rte_intr_efd_enable(intr_handle, intr_vector))
5023                 return -EINVAL;
5024
5025         if (intr_handle->intr_vec == NULL) {
5026                 intr_handle->intr_vec =
5027                         rte_zmalloc("intr_vec",
5028                                     hw->used_rx_queues * sizeof(int), 0);
5029                 if (intr_handle->intr_vec == NULL) {
5030                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5031                                         hw->used_rx_queues);
5032                         ret = -ENOMEM;
5033                         goto alloc_intr_vec_error;
5034                 }
5035         }
5036
5037         if (rte_intr_allow_others(intr_handle)) {
5038                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5039                 base = RTE_INTR_VEC_RXTX_OFFSET;
5040         }
5041
5042         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5043                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5044                                                  HNS3_RING_TYPE_RX, q_id);
5045                 if (ret)
5046                         goto bind_vector_error;
5047                 intr_handle->intr_vec[q_id] = vec;
5048                 /*
5049                  * If there are not enough efds (e.g. not enough interrupt),
5050                  * remaining queues will be bond to the last interrupt.
5051                  */
5052                 if (vec < base + intr_handle->nb_efd - 1)
5053                         vec++;
5054         }
5055         rte_intr_enable(intr_handle);
5056         return 0;
5057
5058 bind_vector_error:
5059         rte_free(intr_handle->intr_vec);
5060         intr_handle->intr_vec = NULL;
5061 alloc_intr_vec_error:
5062         rte_intr_efd_disable(intr_handle);
5063         return ret;
5064 }
5065
5066 static int
5067 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5068 {
5069         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5070         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5071         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5072         uint16_t q_id;
5073         int ret;
5074
5075         if (dev->data->dev_conf.intr_conf.rxq == 0)
5076                 return 0;
5077
5078         if (rte_intr_dp_is_en(intr_handle)) {
5079                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5080                         ret = hns3_bind_ring_with_vector(hw,
5081                                         intr_handle->intr_vec[q_id], true,
5082                                         HNS3_RING_TYPE_RX, q_id);
5083                         if (ret)
5084                                 return ret;
5085                 }
5086         }
5087
5088         return 0;
5089 }
5090
5091 static void
5092 hns3_restore_filter(struct rte_eth_dev *dev)
5093 {
5094         hns3_restore_rss_filter(dev);
5095 }
5096
5097 static int
5098 hns3_dev_start(struct rte_eth_dev *dev)
5099 {
5100         struct hns3_adapter *hns = dev->data->dev_private;
5101         struct hns3_hw *hw = &hns->hw;
5102         int ret;
5103
5104         PMD_INIT_FUNC_TRACE();
5105         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5106                 return -EBUSY;
5107
5108         rte_spinlock_lock(&hw->lock);
5109         hw->adapter_state = HNS3_NIC_STARTING;
5110
5111         ret = hns3_do_start(hns, true);
5112         if (ret) {
5113                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5114                 rte_spinlock_unlock(&hw->lock);
5115                 return ret;
5116         }
5117         ret = hns3_map_rx_interrupt(dev);
5118         if (ret) {
5119                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5120                 rte_spinlock_unlock(&hw->lock);
5121                 return ret;
5122         }
5123
5124         /*
5125          * There are three register used to control the status of a TQP
5126          * (contains a pair of Tx queue and Rx queue) in the new version network
5127          * engine. One is used to control the enabling of Tx queue, the other is
5128          * used to control the enabling of Rx queue, and the last is the master
5129          * switch used to control the enabling of the tqp. The Tx register and
5130          * TQP register must be enabled at the same time to enable a Tx queue.
5131          * The same applies to the Rx queue. For the older network engine, this
5132          * function only refresh the enabled flag, and it is used to update the
5133          * status of queue in the dpdk framework.
5134          */
5135         ret = hns3_start_all_txqs(dev);
5136         if (ret) {
5137                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5138                 rte_spinlock_unlock(&hw->lock);
5139                 return ret;
5140         }
5141
5142         ret = hns3_start_all_rxqs(dev);
5143         if (ret) {
5144                 hns3_stop_all_txqs(dev);
5145                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5146                 rte_spinlock_unlock(&hw->lock);
5147                 return ret;
5148         }
5149
5150         hw->adapter_state = HNS3_NIC_STARTED;
5151         rte_spinlock_unlock(&hw->lock);
5152
5153         hns3_rx_scattered_calc(dev);
5154         hns3_set_rxtx_function(dev);
5155         hns3_mp_req_start_rxtx(dev);
5156         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5157
5158         hns3_restore_filter(dev);
5159
5160         /* Enable interrupt of all rx queues before enabling queues */
5161         hns3_dev_all_rx_queue_intr_enable(hw, true);
5162
5163         /*
5164          * After finished the initialization, enable tqps to receive/transmit
5165          * packets and refresh all queue status.
5166          */
5167         hns3_start_tqps(hw);
5168
5169         hns3_tm_dev_start_proc(hw);
5170
5171         hns3_info(hw, "hns3 dev start successful!");
5172         return 0;
5173 }
5174
5175 static int
5176 hns3_do_stop(struct hns3_adapter *hns)
5177 {
5178         struct hns3_hw *hw = &hns->hw;
5179         int ret;
5180
5181         ret = hns3_cfg_mac_mode(hw, false);
5182         if (ret)
5183                 return ret;
5184         hw->mac.link_status = ETH_LINK_DOWN;
5185
5186         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5187                 hns3_configure_all_mac_addr(hns, true);
5188                 ret = hns3_reset_all_tqps(hns);
5189                 if (ret) {
5190                         hns3_err(hw, "failed to reset all queues ret = %d.",
5191                                  ret);
5192                         return ret;
5193                 }
5194         }
5195         hw->mac.default_addr_setted = false;
5196         return 0;
5197 }
5198
5199 static void
5200 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5201 {
5202         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5203         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5204         struct hns3_adapter *hns = dev->data->dev_private;
5205         struct hns3_hw *hw = &hns->hw;
5206         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5207         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5208         uint16_t q_id;
5209
5210         if (dev->data->dev_conf.intr_conf.rxq == 0)
5211                 return;
5212
5213         /* unmap the ring with vector */
5214         if (rte_intr_allow_others(intr_handle)) {
5215                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5216                 base = RTE_INTR_VEC_RXTX_OFFSET;
5217         }
5218         if (rte_intr_dp_is_en(intr_handle)) {
5219                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5220                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5221                                                          HNS3_RING_TYPE_RX,
5222                                                          q_id);
5223                         if (vec < base + intr_handle->nb_efd - 1)
5224                                 vec++;
5225                 }
5226         }
5227         /* Clean datapath event and queue/vec mapping */
5228         rte_intr_efd_disable(intr_handle);
5229         if (intr_handle->intr_vec) {
5230                 rte_free(intr_handle->intr_vec);
5231                 intr_handle->intr_vec = NULL;
5232         }
5233 }
5234
5235 static int
5236 hns3_dev_stop(struct rte_eth_dev *dev)
5237 {
5238         struct hns3_adapter *hns = dev->data->dev_private;
5239         struct hns3_hw *hw = &hns->hw;
5240
5241         PMD_INIT_FUNC_TRACE();
5242         dev->data->dev_started = 0;
5243
5244         hw->adapter_state = HNS3_NIC_STOPPING;
5245         hns3_set_rxtx_function(dev);
5246         rte_wmb();
5247         /* Disable datapath on secondary process. */
5248         hns3_mp_req_stop_rxtx(dev);
5249         /* Prevent crashes when queues are still in use. */
5250         rte_delay_ms(hw->tqps_num);
5251
5252         rte_spinlock_lock(&hw->lock);
5253         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5254                 hns3_tm_dev_stop_proc(hw);
5255                 hns3_stop_tqps(hw);
5256                 hns3_do_stop(hns);
5257                 hns3_unmap_rx_interrupt(dev);
5258                 hns3_dev_release_mbufs(hns);
5259                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5260         }
5261         hns3_rx_scattered_reset(dev);
5262         rte_eal_alarm_cancel(hns3_service_handler, dev);
5263         rte_spinlock_unlock(&hw->lock);
5264
5265         return 0;
5266 }
5267
5268 static int
5269 hns3_dev_close(struct rte_eth_dev *eth_dev)
5270 {
5271         struct hns3_adapter *hns = eth_dev->data->dev_private;
5272         struct hns3_hw *hw = &hns->hw;
5273         int ret = 0;
5274
5275         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5276                 rte_free(eth_dev->process_private);
5277                 eth_dev->process_private = NULL;
5278                 return 0;
5279         }
5280
5281         if (hw->adapter_state == HNS3_NIC_STARTED)
5282                 ret = hns3_dev_stop(eth_dev);
5283
5284         hw->adapter_state = HNS3_NIC_CLOSING;
5285         hns3_reset_abort(hns);
5286         hw->adapter_state = HNS3_NIC_CLOSED;
5287
5288         hns3_configure_all_mc_mac_addr(hns, true);
5289         hns3_remove_all_vlan_table(hns);
5290         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5291         hns3_uninit_pf(eth_dev);
5292         hns3_free_all_queues(eth_dev);
5293         rte_free(hw->reset.wait_data);
5294         rte_free(eth_dev->process_private);
5295         eth_dev->process_private = NULL;
5296         hns3_mp_uninit_primary();
5297         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5298
5299         return ret;
5300 }
5301
5302 static int
5303 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5304 {
5305         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5306         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5307
5308         fc_conf->pause_time = pf->pause_time;
5309
5310         /* return fc current mode */
5311         switch (hw->current_mode) {
5312         case HNS3_FC_FULL:
5313                 fc_conf->mode = RTE_FC_FULL;
5314                 break;
5315         case HNS3_FC_TX_PAUSE:
5316                 fc_conf->mode = RTE_FC_TX_PAUSE;
5317                 break;
5318         case HNS3_FC_RX_PAUSE:
5319                 fc_conf->mode = RTE_FC_RX_PAUSE;
5320                 break;
5321         case HNS3_FC_NONE:
5322         default:
5323                 fc_conf->mode = RTE_FC_NONE;
5324                 break;
5325         }
5326
5327         return 0;
5328 }
5329
5330 static void
5331 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5332 {
5333         switch (mode) {
5334         case RTE_FC_NONE:
5335                 hw->requested_mode = HNS3_FC_NONE;
5336                 break;
5337         case RTE_FC_RX_PAUSE:
5338                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5339                 break;
5340         case RTE_FC_TX_PAUSE:
5341                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5342                 break;
5343         case RTE_FC_FULL:
5344                 hw->requested_mode = HNS3_FC_FULL;
5345                 break;
5346         default:
5347                 hw->requested_mode = HNS3_FC_NONE;
5348                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5349                           "configured to RTE_FC_NONE", mode);
5350                 break;
5351         }
5352 }
5353
5354 static int
5355 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5356 {
5357         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5358         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5359         int ret;
5360
5361         if (fc_conf->high_water || fc_conf->low_water ||
5362             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5363                 hns3_err(hw, "Unsupported flow control settings specified, "
5364                          "high_water(%u), low_water(%u), send_xon(%u) and "
5365                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5366                          fc_conf->high_water, fc_conf->low_water,
5367                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5368                 return -EINVAL;
5369         }
5370         if (fc_conf->autoneg) {
5371                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5372                 return -EINVAL;
5373         }
5374         if (!fc_conf->pause_time) {
5375                 hns3_err(hw, "Invalid pause time %u setting.",
5376                          fc_conf->pause_time);
5377                 return -EINVAL;
5378         }
5379
5380         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5381             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5382                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5383                          "current_fc_status = %d", hw->current_fc_status);
5384                 return -EOPNOTSUPP;
5385         }
5386
5387         hns3_get_fc_mode(hw, fc_conf->mode);
5388         if (hw->requested_mode == hw->current_mode &&
5389             pf->pause_time == fc_conf->pause_time)
5390                 return 0;
5391
5392         rte_spinlock_lock(&hw->lock);
5393         ret = hns3_fc_enable(dev, fc_conf);
5394         rte_spinlock_unlock(&hw->lock);
5395
5396         return ret;
5397 }
5398
5399 static int
5400 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5401                             struct rte_eth_pfc_conf *pfc_conf)
5402 {
5403         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5405         uint8_t priority;
5406         int ret;
5407
5408         if (!hns3_dev_dcb_supported(hw)) {
5409                 hns3_err(hw, "This port does not support dcb configurations.");
5410                 return -EOPNOTSUPP;
5411         }
5412
5413         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5414             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5415                 hns3_err(hw, "Unsupported flow control settings specified, "
5416                          "high_water(%u), low_water(%u), send_xon(%u) and "
5417                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5418                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5419                          pfc_conf->fc.send_xon,
5420                          pfc_conf->fc.mac_ctrl_frame_fwd);
5421                 return -EINVAL;
5422         }
5423         if (pfc_conf->fc.autoneg) {
5424                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5425                 return -EINVAL;
5426         }
5427         if (pfc_conf->fc.pause_time == 0) {
5428                 hns3_err(hw, "Invalid pause time %u setting.",
5429                          pfc_conf->fc.pause_time);
5430                 return -EINVAL;
5431         }
5432
5433         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5434             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5435                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5436                              "current_fc_status = %d", hw->current_fc_status);
5437                 return -EOPNOTSUPP;
5438         }
5439
5440         priority = pfc_conf->priority;
5441         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5442         if (hw->dcb_info.pfc_en & BIT(priority) &&
5443             hw->requested_mode == hw->current_mode &&
5444             pfc_conf->fc.pause_time == pf->pause_time)
5445                 return 0;
5446
5447         rte_spinlock_lock(&hw->lock);
5448         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5449         rte_spinlock_unlock(&hw->lock);
5450
5451         return ret;
5452 }
5453
5454 static int
5455 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5456 {
5457         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5459         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5460         int i;
5461
5462         rte_spinlock_lock(&hw->lock);
5463         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5464                 dcb_info->nb_tcs = pf->local_max_tc;
5465         else
5466                 dcb_info->nb_tcs = 1;
5467
5468         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5469                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5470         for (i = 0; i < dcb_info->nb_tcs; i++)
5471                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5472
5473         for (i = 0; i < hw->num_tc; i++) {
5474                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5475                 dcb_info->tc_queue.tc_txq[0][i].base =
5476                                                 hw->tc_queue[i].tqp_offset;
5477                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5478                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5479                                                 hw->tc_queue[i].tqp_count;
5480         }
5481         rte_spinlock_unlock(&hw->lock);
5482
5483         return 0;
5484 }
5485
5486 static int
5487 hns3_reinit_dev(struct hns3_adapter *hns)
5488 {
5489         struct hns3_hw *hw = &hns->hw;
5490         int ret;
5491
5492         ret = hns3_cmd_init(hw);
5493         if (ret) {
5494                 hns3_err(hw, "Failed to init cmd: %d", ret);
5495                 return ret;
5496         }
5497
5498         ret = hns3_reset_all_tqps(hns);
5499         if (ret) {
5500                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5501                 return ret;
5502         }
5503
5504         ret = hns3_init_hardware(hns);
5505         if (ret) {
5506                 hns3_err(hw, "Failed to init hardware: %d", ret);
5507                 return ret;
5508         }
5509
5510         ret = hns3_enable_hw_error_intr(hns, true);
5511         if (ret) {
5512                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5513                              ret);
5514                 return ret;
5515         }
5516         hns3_info(hw, "Reset done, driver initialization finished.");
5517
5518         return 0;
5519 }
5520
5521 static bool
5522 is_pf_reset_done(struct hns3_hw *hw)
5523 {
5524         uint32_t val, reg, reg_bit;
5525
5526         switch (hw->reset.level) {
5527         case HNS3_IMP_RESET:
5528                 reg = HNS3_GLOBAL_RESET_REG;
5529                 reg_bit = HNS3_IMP_RESET_BIT;
5530                 break;
5531         case HNS3_GLOBAL_RESET:
5532                 reg = HNS3_GLOBAL_RESET_REG;
5533                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5534                 break;
5535         case HNS3_FUNC_RESET:
5536                 reg = HNS3_FUN_RST_ING;
5537                 reg_bit = HNS3_FUN_RST_ING_B;
5538                 break;
5539         case HNS3_FLR_RESET:
5540         default:
5541                 hns3_err(hw, "Wait for unsupported reset level: %d",
5542                          hw->reset.level);
5543                 return true;
5544         }
5545         val = hns3_read_dev(hw, reg);
5546         if (hns3_get_bit(val, reg_bit))
5547                 return false;
5548         else
5549                 return true;
5550 }
5551
5552 bool
5553 hns3_is_reset_pending(struct hns3_adapter *hns)
5554 {
5555         struct hns3_hw *hw = &hns->hw;
5556         enum hns3_reset_level reset;
5557
5558         hns3_check_event_cause(hns, NULL);
5559         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5560         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5561                 hns3_warn(hw, "High level reset %d is pending", reset);
5562                 return true;
5563         }
5564         reset = hns3_get_reset_level(hns, &hw->reset.request);
5565         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5566                 hns3_warn(hw, "High level reset %d is request", reset);
5567                 return true;
5568         }
5569         return false;
5570 }
5571
5572 static int
5573 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5574 {
5575         struct hns3_hw *hw = &hns->hw;
5576         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5577         struct timeval tv;
5578
5579         if (wait_data->result == HNS3_WAIT_SUCCESS)
5580                 return 0;
5581         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5582                 gettimeofday(&tv, NULL);
5583                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5584                           tv.tv_sec, tv.tv_usec);
5585                 return -ETIME;
5586         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5587                 return -EAGAIN;
5588
5589         wait_data->hns = hns;
5590         wait_data->check_completion = is_pf_reset_done;
5591         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5592                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5593         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5594         wait_data->count = HNS3_RESET_WAIT_CNT;
5595         wait_data->result = HNS3_WAIT_REQUEST;
5596         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5597         return -EAGAIN;
5598 }
5599
5600 static int
5601 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5602 {
5603         struct hns3_cmd_desc desc;
5604         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5605
5606         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5607         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5608         req->fun_reset_vfid = func_id;
5609
5610         return hns3_cmd_send(hw, &desc, 1);
5611 }
5612
5613 static int
5614 hns3_imp_reset_cmd(struct hns3_hw *hw)
5615 {
5616         struct hns3_cmd_desc desc;
5617
5618         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5619         desc.data[0] = 0xeedd;
5620
5621         return hns3_cmd_send(hw, &desc, 1);
5622 }
5623
5624 static void
5625 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5626 {
5627         struct hns3_hw *hw = &hns->hw;
5628         struct timeval tv;
5629         uint32_t val;
5630
5631         gettimeofday(&tv, NULL);
5632         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5633             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5634                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5635                           tv.tv_sec, tv.tv_usec);
5636                 return;
5637         }
5638
5639         switch (reset_level) {
5640         case HNS3_IMP_RESET:
5641                 hns3_imp_reset_cmd(hw);
5642                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5643                           tv.tv_sec, tv.tv_usec);
5644                 break;
5645         case HNS3_GLOBAL_RESET:
5646                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5647                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5648                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5649                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5650                           tv.tv_sec, tv.tv_usec);
5651                 break;
5652         case HNS3_FUNC_RESET:
5653                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5654                           tv.tv_sec, tv.tv_usec);
5655                 /* schedule again to check later */
5656                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5657                 hns3_schedule_reset(hns);
5658                 break;
5659         default:
5660                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5661                 return;
5662         }
5663         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5664 }
5665
5666 static enum hns3_reset_level
5667 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5668 {
5669         struct hns3_hw *hw = &hns->hw;
5670         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5671
5672         /* Return the highest priority reset level amongst all */
5673         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5674                 reset_level = HNS3_IMP_RESET;
5675         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5676                 reset_level = HNS3_GLOBAL_RESET;
5677         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5678                 reset_level = HNS3_FUNC_RESET;
5679         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5680                 reset_level = HNS3_FLR_RESET;
5681
5682         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5683                 return HNS3_NONE_RESET;
5684
5685         return reset_level;
5686 }
5687
5688 static void
5689 hns3_record_imp_error(struct hns3_adapter *hns)
5690 {
5691         struct hns3_hw *hw = &hns->hw;
5692         uint32_t reg_val;
5693
5694         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5695         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5696                 hns3_warn(hw, "Detected IMP RD poison!");
5697                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5698                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5699                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5700         }
5701
5702         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5703                 hns3_warn(hw, "Detected IMP CMDQ error!");
5704                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5705                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5706                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5707         }
5708 }
5709
5710 static int
5711 hns3_prepare_reset(struct hns3_adapter *hns)
5712 {
5713         struct hns3_hw *hw = &hns->hw;
5714         uint32_t reg_val;
5715         int ret;
5716
5717         switch (hw->reset.level) {
5718         case HNS3_FUNC_RESET:
5719                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5720                 if (ret)
5721                         return ret;
5722
5723                 /*
5724                  * After performaning pf reset, it is not necessary to do the
5725                  * mailbox handling or send any command to firmware, because
5726                  * any mailbox handling or command to firmware is only valid
5727                  * after hns3_cmd_init is called.
5728                  */
5729                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5730                 hw->reset.stats.request_cnt++;
5731                 break;
5732         case HNS3_IMP_RESET:
5733                 hns3_record_imp_error(hns);
5734                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5735                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5736                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5737                 break;
5738         default:
5739                 break;
5740         }
5741         return 0;
5742 }
5743
5744 static int
5745 hns3_set_rst_done(struct hns3_hw *hw)
5746 {
5747         struct hns3_pf_rst_done_cmd *req;
5748         struct hns3_cmd_desc desc;
5749
5750         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5751         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5752         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5753         return hns3_cmd_send(hw, &desc, 1);
5754 }
5755
5756 static int
5757 hns3_stop_service(struct hns3_adapter *hns)
5758 {
5759         struct hns3_hw *hw = &hns->hw;
5760         struct rte_eth_dev *eth_dev;
5761
5762         eth_dev = &rte_eth_devices[hw->data->port_id];
5763         if (hw->adapter_state == HNS3_NIC_STARTED) {
5764                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5765                 hns3_update_link_status_and_event(hw);
5766         }
5767         hw->mac.link_status = ETH_LINK_DOWN;
5768
5769         hns3_set_rxtx_function(eth_dev);
5770         rte_wmb();
5771         /* Disable datapath on secondary process. */
5772         hns3_mp_req_stop_rxtx(eth_dev);
5773         rte_delay_ms(hw->tqps_num);
5774
5775         rte_spinlock_lock(&hw->lock);
5776         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5777             hw->adapter_state == HNS3_NIC_STOPPING) {
5778                 hns3_enable_all_queues(hw, false);
5779                 hns3_do_stop(hns);
5780                 hw->reset.mbuf_deferred_free = true;
5781         } else
5782                 hw->reset.mbuf_deferred_free = false;
5783
5784         /*
5785          * It is cumbersome for hardware to pick-and-choose entries for deletion
5786          * from table space. Hence, for function reset software intervention is
5787          * required to delete the entries
5788          */
5789         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5790                 hns3_configure_all_mc_mac_addr(hns, true);
5791         rte_spinlock_unlock(&hw->lock);
5792
5793         return 0;
5794 }
5795
5796 static int
5797 hns3_start_service(struct hns3_adapter *hns)
5798 {
5799         struct hns3_hw *hw = &hns->hw;
5800         struct rte_eth_dev *eth_dev;
5801
5802         if (hw->reset.level == HNS3_IMP_RESET ||
5803             hw->reset.level == HNS3_GLOBAL_RESET)
5804                 hns3_set_rst_done(hw);
5805         eth_dev = &rte_eth_devices[hw->data->port_id];
5806         hns3_set_rxtx_function(eth_dev);
5807         hns3_mp_req_start_rxtx(eth_dev);
5808         if (hw->adapter_state == HNS3_NIC_STARTED) {
5809                 /*
5810                  * This API parent function already hold the hns3_hw.lock, the
5811                  * hns3_service_handler may report lse, in bonding application
5812                  * it will call driver's ops which may acquire the hns3_hw.lock
5813                  * again, thus lead to deadlock.
5814                  * We defer calls hns3_service_handler to avoid the deadlock.
5815                  */
5816                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5817                                   hns3_service_handler, eth_dev);
5818
5819                 /* Enable interrupt of all rx queues before enabling queues */
5820                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5821                 /*
5822                  * Enable state of each rxq and txq will be recovered after
5823                  * reset, so we need to restore them before enable all tqps;
5824                  */
5825                 hns3_restore_tqp_enable_state(hw);
5826                 /*
5827                  * When finished the initialization, enable queues to receive
5828                  * and transmit packets.
5829                  */
5830                 hns3_enable_all_queues(hw, true);
5831         }
5832
5833         return 0;
5834 }
5835
5836 static int
5837 hns3_restore_conf(struct hns3_adapter *hns)
5838 {
5839         struct hns3_hw *hw = &hns->hw;
5840         int ret;
5841
5842         ret = hns3_configure_all_mac_addr(hns, false);
5843         if (ret)
5844                 return ret;
5845
5846         ret = hns3_configure_all_mc_mac_addr(hns, false);
5847         if (ret)
5848                 goto err_mc_mac;
5849
5850         ret = hns3_dev_promisc_restore(hns);
5851         if (ret)
5852                 goto err_promisc;
5853
5854         ret = hns3_restore_vlan_table(hns);
5855         if (ret)
5856                 goto err_promisc;
5857
5858         ret = hns3_restore_vlan_conf(hns);
5859         if (ret)
5860                 goto err_promisc;
5861
5862         ret = hns3_restore_all_fdir_filter(hns);
5863         if (ret)
5864                 goto err_promisc;
5865
5866         ret = hns3_restore_rx_interrupt(hw);
5867         if (ret)
5868                 goto err_promisc;
5869
5870         ret = hns3_restore_gro_conf(hw);
5871         if (ret)
5872                 goto err_promisc;
5873
5874         ret = hns3_restore_fec(hw);
5875         if (ret)
5876                 goto err_promisc;
5877
5878         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5879                 ret = hns3_do_start(hns, false);
5880                 if (ret)
5881                         goto err_promisc;
5882                 hns3_info(hw, "hns3 dev restart successful!");
5883         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5884                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5885         return 0;
5886
5887 err_promisc:
5888         hns3_configure_all_mc_mac_addr(hns, true);
5889 err_mc_mac:
5890         hns3_configure_all_mac_addr(hns, true);
5891         return ret;
5892 }
5893
5894 static void
5895 hns3_reset_service(void *param)
5896 {
5897         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5898         struct hns3_hw *hw = &hns->hw;
5899         enum hns3_reset_level reset_level;
5900         struct timeval tv_delta;
5901         struct timeval tv_start;
5902         struct timeval tv;
5903         uint64_t msec;
5904         int ret;
5905
5906         /*
5907          * The interrupt is not triggered within the delay time.
5908          * The interrupt may have been lost. It is necessary to handle
5909          * the interrupt to recover from the error.
5910          */
5911         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5912                             SCHEDULE_DEFERRED) {
5913                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5914                                   __ATOMIC_RELAXED);
5915                 hns3_err(hw, "Handling interrupts in delayed tasks");
5916                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5917                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5918                 if (reset_level == HNS3_NONE_RESET) {
5919                         hns3_err(hw, "No reset level is set, try IMP reset");
5920                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5921                 }
5922         }
5923         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5924
5925         /*
5926          * Check if there is any ongoing reset in the hardware. This status can
5927          * be checked from reset_pending. If there is then, we need to wait for
5928          * hardware to complete reset.
5929          *    a. If we are able to figure out in reasonable time that hardware
5930          *       has fully resetted then, we can proceed with driver, client
5931          *       reset.
5932          *    b. else, we can come back later to check this status so re-sched
5933          *       now.
5934          */
5935         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5936         if (reset_level != HNS3_NONE_RESET) {
5937                 gettimeofday(&tv_start, NULL);
5938                 ret = hns3_reset_process(hns, reset_level);
5939                 gettimeofday(&tv, NULL);
5940                 timersub(&tv, &tv_start, &tv_delta);
5941                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5942                        tv_delta.tv_usec / USEC_PER_MSEC;
5943                 if (msec > HNS3_RESET_PROCESS_MS)
5944                         hns3_err(hw, "%d handle long time delta %" PRIx64
5945                                      " ms time=%ld.%.6ld",
5946                                  hw->reset.level, msec,
5947                                  tv.tv_sec, tv.tv_usec);
5948                 if (ret == -EAGAIN)
5949                         return;
5950         }
5951
5952         /* Check if we got any *new* reset requests to be honored */
5953         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5954         if (reset_level != HNS3_NONE_RESET)
5955                 hns3_msix_process(hns, reset_level);
5956 }
5957
5958 static unsigned int
5959 hns3_get_speed_capa_num(uint16_t device_id)
5960 {
5961         unsigned int num;
5962
5963         switch (device_id) {
5964         case HNS3_DEV_ID_25GE:
5965         case HNS3_DEV_ID_25GE_RDMA:
5966                 num = 2;
5967                 break;
5968         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5969         case HNS3_DEV_ID_200G_RDMA:
5970                 num = 1;
5971                 break;
5972         default:
5973                 num = 0;
5974                 break;
5975         }
5976
5977         return num;
5978 }
5979
5980 static int
5981 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5982                         uint16_t device_id)
5983 {
5984         switch (device_id) {
5985         case HNS3_DEV_ID_25GE:
5986         /* fallthrough */
5987         case HNS3_DEV_ID_25GE_RDMA:
5988                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5989                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5990
5991                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5992                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5993                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5994                 break;
5995         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5996                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5997                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5998                 break;
5999         case HNS3_DEV_ID_200G_RDMA:
6000                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6001                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6002                 break;
6003         default:
6004                 return -ENOTSUP;
6005         }
6006
6007         return 0;
6008 }
6009
6010 static int
6011 hns3_fec_get_capability(struct rte_eth_dev *dev,
6012                         struct rte_eth_fec_capa *speed_fec_capa,
6013                         unsigned int num)
6014 {
6015         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6017         uint16_t device_id = pci_dev->id.device_id;
6018         unsigned int capa_num;
6019         int ret;
6020
6021         capa_num = hns3_get_speed_capa_num(device_id);
6022         if (capa_num == 0) {
6023                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6024                          device_id);
6025                 return -ENOTSUP;
6026         }
6027
6028         if (speed_fec_capa == NULL || num < capa_num)
6029                 return capa_num;
6030
6031         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6032         if (ret)
6033                 return -ENOTSUP;
6034
6035         return capa_num;
6036 }
6037
6038 static int
6039 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6040 {
6041         struct hns3_config_fec_cmd *req;
6042         struct hns3_cmd_desc desc;
6043         int ret;
6044
6045         /*
6046          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6047          * in device of link speed
6048          * below 10 Gbps.
6049          */
6050         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6051                 *state = 0;
6052                 return 0;
6053         }
6054
6055         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6056         req = (struct hns3_config_fec_cmd *)desc.data;
6057         ret = hns3_cmd_send(hw, &desc, 1);
6058         if (ret) {
6059                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6060                          ret);
6061                 return ret;
6062         }
6063
6064         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6065         return 0;
6066 }
6067
6068 static int
6069 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6070 {
6071 #define QUERY_ACTIVE_SPEED      1
6072         struct hns3_sfp_speed_cmd *resp;
6073         uint32_t tmp_fec_capa;
6074         uint8_t auto_state;
6075         struct hns3_cmd_desc desc;
6076         int ret;
6077
6078         /*
6079          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6080          * configured FEC mode is returned.
6081          * If link is up, current FEC mode is returned.
6082          */
6083         if (hw->mac.link_status == ETH_LINK_DOWN) {
6084                 ret = get_current_fec_auto_state(hw, &auto_state);
6085                 if (ret)
6086                         return ret;
6087
6088                 if (auto_state == 0x1) {
6089                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6090                         return 0;
6091                 }
6092         }
6093
6094         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6095         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6096         resp->query_type = QUERY_ACTIVE_SPEED;
6097
6098         ret = hns3_cmd_send(hw, &desc, 1);
6099         if (ret == -EOPNOTSUPP) {
6100                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6101                 return ret;
6102         } else if (ret) {
6103                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6104                 return ret;
6105         }
6106
6107         /*
6108          * FEC mode order defined in hns3 hardware is inconsistend with
6109          * that defined in the ethdev library. So the sequence needs
6110          * to be converted.
6111          */
6112         switch (resp->active_fec) {
6113         case HNS3_HW_FEC_MODE_NOFEC:
6114                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6115                 break;
6116         case HNS3_HW_FEC_MODE_BASER:
6117                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6118                 break;
6119         case HNS3_HW_FEC_MODE_RS:
6120                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6121                 break;
6122         default:
6123                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6124                 break;
6125         }
6126
6127         *fec_capa = tmp_fec_capa;
6128         return 0;
6129 }
6130
6131 static int
6132 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6133 {
6134         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6135
6136         return hns3_fec_get_internal(hw, fec_capa);
6137 }
6138
6139 static int
6140 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6141 {
6142         struct hns3_config_fec_cmd *req;
6143         struct hns3_cmd_desc desc;
6144         int ret;
6145
6146         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6147
6148         req = (struct hns3_config_fec_cmd *)desc.data;
6149         switch (mode) {
6150         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6151                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6152                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6153                 break;
6154         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6155                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6156                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6157                 break;
6158         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6159                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6160                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6161                 break;
6162         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6163                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6164                 break;
6165         default:
6166                 return 0;
6167         }
6168         ret = hns3_cmd_send(hw, &desc, 1);
6169         if (ret)
6170                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6171
6172         return ret;
6173 }
6174
6175 static uint32_t
6176 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6177 {
6178         struct hns3_mac *mac = &hw->mac;
6179         uint32_t cur_capa;
6180
6181         switch (mac->link_speed) {
6182         case ETH_SPEED_NUM_10G:
6183                 cur_capa = fec_capa[1].capa;
6184                 break;
6185         case ETH_SPEED_NUM_25G:
6186         case ETH_SPEED_NUM_100G:
6187         case ETH_SPEED_NUM_200G:
6188                 cur_capa = fec_capa[0].capa;
6189                 break;
6190         default:
6191                 cur_capa = 0;
6192                 break;
6193         }
6194
6195         return cur_capa;
6196 }
6197
6198 static bool
6199 is_fec_mode_one_bit_set(uint32_t mode)
6200 {
6201         int cnt = 0;
6202         uint8_t i;
6203
6204         for (i = 0; i < sizeof(mode); i++)
6205                 if (mode >> i & 0x1)
6206                         cnt++;
6207
6208         return cnt == 1 ? true : false;
6209 }
6210
6211 static int
6212 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6213 {
6214 #define FEC_CAPA_NUM 2
6215         struct hns3_adapter *hns = dev->data->dev_private;
6216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6217         struct hns3_pf *pf = &hns->pf;
6218
6219         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6220         uint32_t cur_capa;
6221         uint32_t num = FEC_CAPA_NUM;
6222         int ret;
6223
6224         ret = hns3_fec_get_capability(dev, fec_capa, num);
6225         if (ret < 0)
6226                 return ret;
6227
6228         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6229         if (!is_fec_mode_one_bit_set(mode))
6230                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6231                              "FEC mode should be only one bit set", mode);
6232
6233         /*
6234          * Check whether the configured mode is within the FEC capability.
6235          * If not, the configured mode will not be supported.
6236          */
6237         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6238         if (!(cur_capa & mode)) {
6239                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6240                 return -EINVAL;
6241         }
6242
6243         ret = hns3_set_fec_hw(hw, mode);
6244         if (ret)
6245                 return ret;
6246
6247         pf->fec_mode = mode;
6248         return 0;
6249 }
6250
6251 static int
6252 hns3_restore_fec(struct hns3_hw *hw)
6253 {
6254         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6255         struct hns3_pf *pf = &hns->pf;
6256         uint32_t mode = pf->fec_mode;
6257         int ret;
6258
6259         ret = hns3_set_fec_hw(hw, mode);
6260         if (ret)
6261                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6262                          mode, ret);
6263
6264         return ret;
6265 }
6266
6267 static int
6268 hns3_query_dev_fec_info(struct hns3_hw *hw)
6269 {
6270         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6271         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6272         int ret;
6273
6274         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6275         if (ret)
6276                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6277
6278         return ret;
6279 }
6280
6281 static bool
6282 hns3_optical_module_existed(struct hns3_hw *hw)
6283 {
6284         struct hns3_cmd_desc desc;
6285         bool existed;
6286         int ret;
6287
6288         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6289         ret = hns3_cmd_send(hw, &desc, 1);
6290         if (ret) {
6291                 hns3_err(hw,
6292                          "fail to get optical module exist state, ret = %d.\n",
6293                          ret);
6294                 return false;
6295         }
6296         existed = !!desc.data[0];
6297
6298         return existed;
6299 }
6300
6301 static int
6302 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6303                                 uint32_t len, uint8_t *data)
6304 {
6305 #define HNS3_SFP_INFO_CMD_NUM 6
6306 #define HNS3_SFP_INFO_MAX_LEN \
6307         (HNS3_SFP_INFO_BD0_LEN + \
6308         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6309         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6310         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6311         uint16_t read_len;
6312         uint16_t copy_len;
6313         int ret;
6314         int i;
6315
6316         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6317                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6318                                           true);
6319                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6320                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6321         }
6322
6323         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6324         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6325         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6326         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6327
6328         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6329         if (ret) {
6330                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6331                                 ret);
6332                 return ret;
6333         }
6334
6335         /* The data format in BD0 is different with the others. */
6336         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6337         memcpy(data, sfp_info_bd0->data, copy_len);
6338         read_len = copy_len;
6339
6340         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6341                 if (read_len >= len)
6342                         break;
6343
6344                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6345                 memcpy(data + read_len, desc[i].data, copy_len);
6346                 read_len += copy_len;
6347         }
6348
6349         return (int)read_len;
6350 }
6351
6352 static int
6353 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6354                        struct rte_dev_eeprom_info *info)
6355 {
6356         struct hns3_adapter *hns = dev->data->dev_private;
6357         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6358         uint32_t offset = info->offset;
6359         uint32_t len = info->length;
6360         uint8_t *data = info->data;
6361         uint32_t read_len = 0;
6362
6363         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6364                 return -ENOTSUP;
6365
6366         if (!hns3_optical_module_existed(hw)) {
6367                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6368                 return -EIO;
6369         }
6370
6371         while (read_len < len) {
6372                 int ret;
6373                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6374                                                   len - read_len,
6375                                                   data + read_len);
6376                 if (ret < 0)
6377                         return -EIO;
6378                 read_len += ret;
6379         }
6380
6381         return 0;
6382 }
6383
6384 static int
6385 hns3_get_module_info(struct rte_eth_dev *dev,
6386                      struct rte_eth_dev_module_info *modinfo)
6387 {
6388 #define HNS3_SFF8024_ID_SFP             0x03
6389 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6390 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6391 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6392 #define HNS3_SFF_8636_V1_3              0x03
6393         struct hns3_adapter *hns = dev->data->dev_private;
6394         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6395         struct rte_dev_eeprom_info info;
6396         struct hns3_sfp_type sfp_type;
6397         int ret;
6398
6399         memset(&sfp_type, 0, sizeof(sfp_type));
6400         memset(&info, 0, sizeof(info));
6401         info.data = (uint8_t *)&sfp_type;
6402         info.length = sizeof(sfp_type);
6403         ret = hns3_get_module_eeprom(dev, &info);
6404         if (ret)
6405                 return ret;
6406
6407         switch (sfp_type.type) {
6408         case HNS3_SFF8024_ID_SFP:
6409                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6410                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6411                 break;
6412         case HNS3_SFF8024_ID_QSFP_8438:
6413                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6414                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6415                 break;
6416         case HNS3_SFF8024_ID_QSFP_8436_8636:
6417                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6418                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6419                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6420                 } else {
6421                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6422                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6423                 }
6424                 break;
6425         case HNS3_SFF8024_ID_QSFP28_8636:
6426                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6427                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6428                 break;
6429         default:
6430                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6431                          sfp_type.type, sfp_type.ext_type);
6432                 return -EINVAL;
6433         }
6434
6435         return 0;
6436 }
6437
6438 static const struct eth_dev_ops hns3_eth_dev_ops = {
6439         .dev_configure      = hns3_dev_configure,
6440         .dev_start          = hns3_dev_start,
6441         .dev_stop           = hns3_dev_stop,
6442         .dev_close          = hns3_dev_close,
6443         .promiscuous_enable = hns3_dev_promiscuous_enable,
6444         .promiscuous_disable = hns3_dev_promiscuous_disable,
6445         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6446         .allmulticast_disable = hns3_dev_allmulticast_disable,
6447         .mtu_set            = hns3_dev_mtu_set,
6448         .stats_get          = hns3_stats_get,
6449         .stats_reset        = hns3_stats_reset,
6450         .xstats_get         = hns3_dev_xstats_get,
6451         .xstats_get_names   = hns3_dev_xstats_get_names,
6452         .xstats_reset       = hns3_dev_xstats_reset,
6453         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6454         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6455         .dev_infos_get          = hns3_dev_infos_get,
6456         .fw_version_get         = hns3_fw_version_get,
6457         .rx_queue_setup         = hns3_rx_queue_setup,
6458         .tx_queue_setup         = hns3_tx_queue_setup,
6459         .rx_queue_release       = hns3_dev_rx_queue_release,
6460         .tx_queue_release       = hns3_dev_tx_queue_release,
6461         .rx_queue_start         = hns3_dev_rx_queue_start,
6462         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6463         .tx_queue_start         = hns3_dev_tx_queue_start,
6464         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6465         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6466         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6467         .rxq_info_get           = hns3_rxq_info_get,
6468         .txq_info_get           = hns3_txq_info_get,
6469         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6470         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6471         .flow_ctrl_get          = hns3_flow_ctrl_get,
6472         .flow_ctrl_set          = hns3_flow_ctrl_set,
6473         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6474         .mac_addr_add           = hns3_add_mac_addr,
6475         .mac_addr_remove        = hns3_remove_mac_addr,
6476         .mac_addr_set           = hns3_set_default_mac_addr,
6477         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6478         .link_update            = hns3_dev_link_update,
6479         .rss_hash_update        = hns3_dev_rss_hash_update,
6480         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6481         .reta_update            = hns3_dev_rss_reta_update,
6482         .reta_query             = hns3_dev_rss_reta_query,
6483         .filter_ctrl            = hns3_dev_filter_ctrl,
6484         .vlan_filter_set        = hns3_vlan_filter_set,
6485         .vlan_tpid_set          = hns3_vlan_tpid_set,
6486         .vlan_offload_set       = hns3_vlan_offload_set,
6487         .vlan_pvid_set          = hns3_vlan_pvid_set,
6488         .get_reg                = hns3_get_regs,
6489         .get_module_info        = hns3_get_module_info,
6490         .get_module_eeprom      = hns3_get_module_eeprom,
6491         .get_dcb_info           = hns3_get_dcb_info,
6492         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6493         .fec_get_capability     = hns3_fec_get_capability,
6494         .fec_get                = hns3_fec_get,
6495         .fec_set                = hns3_fec_set,
6496         .tm_ops_get             = hns3_tm_ops_get,
6497         .tx_done_cleanup        = hns3_tx_done_cleanup,
6498 };
6499
6500 static const struct hns3_reset_ops hns3_reset_ops = {
6501         .reset_service       = hns3_reset_service,
6502         .stop_service        = hns3_stop_service,
6503         .prepare_reset       = hns3_prepare_reset,
6504         .wait_hardware_ready = hns3_wait_hardware_ready,
6505         .reinit_dev          = hns3_reinit_dev,
6506         .restore_conf        = hns3_restore_conf,
6507         .start_service       = hns3_start_service,
6508 };
6509
6510 static int
6511 hns3_dev_init(struct rte_eth_dev *eth_dev)
6512 {
6513         struct hns3_adapter *hns = eth_dev->data->dev_private;
6514         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6515         struct rte_ether_addr *eth_addr;
6516         struct hns3_hw *hw = &hns->hw;
6517         int ret;
6518
6519         PMD_INIT_FUNC_TRACE();
6520
6521         eth_dev->process_private = (struct hns3_process_private *)
6522             rte_zmalloc_socket("hns3_filter_list",
6523                                sizeof(struct hns3_process_private),
6524                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6525         if (eth_dev->process_private == NULL) {
6526                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6527                 return -ENOMEM;
6528         }
6529         /* initialize flow filter lists */
6530         hns3_filterlist_init(eth_dev);
6531
6532         hns3_set_rxtx_function(eth_dev);
6533         eth_dev->dev_ops = &hns3_eth_dev_ops;
6534         eth_dev->rx_queue_count = hns3_rx_queue_count;
6535         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6536                 ret = hns3_mp_init_secondary();
6537                 if (ret) {
6538                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6539                                      "process, ret = %d", ret);
6540                         goto err_mp_init_secondary;
6541                 }
6542
6543                 hw->secondary_cnt++;
6544                 return 0;
6545         }
6546
6547         ret = hns3_mp_init_primary();
6548         if (ret) {
6549                 PMD_INIT_LOG(ERR,
6550                              "Failed to init for primary process, ret = %d",
6551                              ret);
6552                 goto err_mp_init_primary;
6553         }
6554
6555         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6556         hns->is_vf = false;
6557         hw->data = eth_dev->data;
6558
6559         /*
6560          * Set default max packet size according to the mtu
6561          * default vale in DPDK frame.
6562          */
6563         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6564
6565         ret = hns3_reset_init(hw);
6566         if (ret)
6567                 goto err_init_reset;
6568         hw->reset.ops = &hns3_reset_ops;
6569
6570         ret = hns3_init_pf(eth_dev);
6571         if (ret) {
6572                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6573                 goto err_init_pf;
6574         }
6575
6576         /* Allocate memory for storing MAC addresses */
6577         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6578                                                sizeof(struct rte_ether_addr) *
6579                                                HNS3_UC_MACADDR_NUM, 0);
6580         if (eth_dev->data->mac_addrs == NULL) {
6581                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6582                              "to store MAC addresses",
6583                              sizeof(struct rte_ether_addr) *
6584                              HNS3_UC_MACADDR_NUM);
6585                 ret = -ENOMEM;
6586                 goto err_rte_zmalloc;
6587         }
6588
6589         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6590         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6591                 rte_eth_random_addr(hw->mac.mac_addr);
6592                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6593                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6594                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6595                           "unicast address, using random MAC address %s",
6596                           mac_str);
6597         }
6598         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6599                             &eth_dev->data->mac_addrs[0]);
6600
6601         hw->adapter_state = HNS3_NIC_INITIALIZED;
6602
6603         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6604                             SCHEDULE_PENDING) {
6605                 hns3_err(hw, "Reschedule reset service after dev_init");
6606                 hns3_schedule_reset(hns);
6607         } else {
6608                 /* IMP will wait ready flag before reset */
6609                 hns3_notify_reset_ready(hw, false);
6610         }
6611
6612         hns3_info(hw, "hns3 dev initialization successful!");
6613         return 0;
6614
6615 err_rte_zmalloc:
6616         hns3_uninit_pf(eth_dev);
6617
6618 err_init_pf:
6619         rte_free(hw->reset.wait_data);
6620
6621 err_init_reset:
6622         hns3_mp_uninit_primary();
6623
6624 err_mp_init_primary:
6625 err_mp_init_secondary:
6626         eth_dev->dev_ops = NULL;
6627         eth_dev->rx_pkt_burst = NULL;
6628         eth_dev->tx_pkt_burst = NULL;
6629         eth_dev->tx_pkt_prepare = NULL;
6630         rte_free(eth_dev->process_private);
6631         eth_dev->process_private = NULL;
6632         return ret;
6633 }
6634
6635 static int
6636 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6637 {
6638         struct hns3_adapter *hns = eth_dev->data->dev_private;
6639         struct hns3_hw *hw = &hns->hw;
6640
6641         PMD_INIT_FUNC_TRACE();
6642
6643         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6644                 rte_free(eth_dev->process_private);
6645                 eth_dev->process_private = NULL;
6646                 return 0;
6647         }
6648
6649         if (hw->adapter_state < HNS3_NIC_CLOSING)
6650                 hns3_dev_close(eth_dev);
6651
6652         hw->adapter_state = HNS3_NIC_REMOVED;
6653         return 0;
6654 }
6655
6656 static int
6657 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6658                    struct rte_pci_device *pci_dev)
6659 {
6660         return rte_eth_dev_pci_generic_probe(pci_dev,
6661                                              sizeof(struct hns3_adapter),
6662                                              hns3_dev_init);
6663 }
6664
6665 static int
6666 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6667 {
6668         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6669 }
6670
6671 static const struct rte_pci_id pci_id_hns3_map[] = {
6672         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6673         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6674         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6675         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6676         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6677         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6678         { .vendor_id = 0, }, /* sentinel */
6679 };
6680
6681 static struct rte_pci_driver rte_hns3_pmd = {
6682         .id_table = pci_id_hns3_map,
6683         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6684         .probe = eth_hns3_pci_probe,
6685         .remove = eth_hns3_pci_remove,
6686 };
6687
6688 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6689 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6690 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6691 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6692 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);