drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_OFFSET_160            160
 236         struct hns3_vlan_filter_pf_cfg_cmd *req;
 237         struct hns3_hw *hw = &hns->hw;
 238         uint8_t vlan_offset_byte_val;
 239         struct hns3_cmd_desc desc;
 240         uint8_t vlan_offset_byte;
 241         uint8_t vlan_offset_160;
 242         int ret;
 243
 244         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 245
 246         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 247         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 248         vlan_offset_byte_val = 1 << (vlan_id % 8);
 249
 250         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 251         req->vlan_offset = vlan_offset_160;
 252         req->vlan_cfg = on ? 0 : 1;
 253         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 254
 255         ret = hns3_cmd_send(hw, &desc, 1);
 256         if (ret)
 257                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 258                          vlan_id, ret);
 259
 260         return ret;
 261 }
 262
 263 static void
 264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 265 {
 266         struct hns3_user_vlan_table *vlan_entry;
 267         struct hns3_pf *pf = &hns->pf;
 268
 269         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 270                 if (vlan_entry->vlan_id == vlan_id) {
 271                         if (vlan_entry->hd_tbl_status)
 272                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 273                         LIST_REMOVE(vlan_entry, next);
 274                         rte_free(vlan_entry);
 275                         break;
 276                 }
 277         }
 278 }
 279
 280 static void
 281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 282                         bool writen_to_tbl)
 283 {
 284         struct hns3_user_vlan_table *vlan_entry;
 285         struct hns3_hw *hw = &hns->hw;
 286         struct hns3_pf *pf = &hns->pf;
 287
 288         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 289                 if (vlan_entry->vlan_id == vlan_id)
 290                         return;
 291         }
 292
 293         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 294         if (vlan_entry == NULL) {
 295                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 296                 return;
 297         }
 298
 299         vlan_entry->hd_tbl_status = writen_to_tbl;
 300         vlan_entry->vlan_id = vlan_id;
 301
 302         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 303 }
 304
 305 static int
 306 hns3_restore_vlan_table(struct hns3_adapter *hns)
 307 {
 308         struct hns3_user_vlan_table *vlan_entry;
 309         struct hns3_pf *pf = &hns->pf;
 310         uint16_t vlan_id;
 311         int ret = 0;
 312
 313         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 314                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 315                                                1);
 316                 return ret;
 317         }
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 876         rte_spinlock_unlock(&hw->lock);
 877         return ret;
 878 }
 879
 880 static void
 881 init_port_base_vlan_info(struct hns3_hw *hw)
 882 {
 883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 884         struct hns3_pf *pf = &hns->pf;
 885
 886         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 887         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 888 }
 889
 890 static int
 891 hns3_default_vlan_config(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 897         if (ret)
 898                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_init_vlan_config(struct hns3_adapter *hns)
 904 {
 905         struct hns3_hw *hw = &hns->hw;
 906         int ret;
 907
 908         /*
 909          * This function can be called in the initialization and reset process,
 910          * when in reset process, it means that hardware had been reseted
 911          * successfully and we need to restore the hardware configuration to
 912          * ensure that the hardware configuration remains unchanged before and
 913          * after reset.
 914          */
 915         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 916                 init_port_base_vlan_info(hw);
 917
 918         ret = hns3_enable_vlan_filter(hns, true);
 919         if (ret) {
 920                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 925                                        RTE_ETHER_TYPE_VLAN);
 926         if (ret) {
 927                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * When in the reinit dev stage of the reset process, the following
 933          * vlan-related configurations may differ from those at initialization,
 934          * we will restore configurations to hardware in hns3_restore_vlan_table
 935          * and hns3_restore_vlan_conf later.
 936          */
 937         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 938                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 939                 if (ret) {
 940                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 941                         return ret;
 942                 }
 943
 944                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 945                 if (ret) {
 946                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 947                                  ret);
 948                         return ret;
 949                 }
 950         }
 951
 952         return hns3_default_vlan_config(hns);
 953 }
 954
 955 static int
 956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 957 {
 958         struct hns3_pf *pf = &hns->pf;
 959         struct hns3_hw *hw = &hns->hw;
 960         int ret;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 963         if (ret) {
 964                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 969         if (ret)
 970                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 977 {
 978         struct hns3_adapter *hns = dev->data->dev_private;
 979         struct rte_eth_dev_data *data = dev->data;
 980         struct rte_eth_txmode *txmode;
 981         struct hns3_hw *hw = &hns->hw;
 982         int ret;
 983
 984         txmode = &data->dev_conf.txmode;
 985         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 986                 hns3_warn(hw,
 987                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 988                           "configuration is not supported! Ignore these two "
 989                           "parameters: hw_vlan_reject_tagged(%d), "
 990                           "hw_vlan_reject_untagged(%d)",
 991                           txmode->hw_vlan_reject_tagged,
 992                           txmode->hw_vlan_reject_untagged);
 993
 994         /* Apply vlan offload setting */
 995         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 996         if (ret) {
 997                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 998                 return ret;
 999         }
1000
1001         /* Apply pvid setting */
1002         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003                                  txmode->hw_vlan_insert_pvid);
1004         if (ret)
1005                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1006                          txmode->pvid, ret);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013                 unsigned int tso_mss_max)
1014 {
1015         struct hns3_cfg_tso_status_cmd *req;
1016         struct hns3_cmd_desc desc;
1017         uint16_t tso_mss;
1018
1019         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1020
1021         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1022
1023         tso_mss = 0;
1024         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1025                        tso_mss_min);
1026         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1027
1028         tso_mss = 0;
1029         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1030                        tso_mss_max);
1031         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1032
1033         return hns3_cmd_send(hw, &desc, 1);
1034 }
1035
1036 int
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1038 {
1039         struct hns3_cfg_gro_status_cmd *req;
1040         struct hns3_cmd_desc desc;
1041         int ret;
1042
1043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1045
1046         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1047
1048         ret = hns3_cmd_send(hw, &desc, 1);
1049         if (ret)
1050                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057                    uint16_t *allocated_size, bool is_alloc)
1058 {
1059         struct hns3_umv_spc_alc_cmd *req;
1060         struct hns3_cmd_desc desc;
1061         int ret;
1062
1063         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066         req->space_size = rte_cpu_to_le_32(space_size);
1067
1068         ret = hns3_cmd_send(hw, &desc, 1);
1069         if (ret) {
1070                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071                              is_alloc ? "allocate" : "free", ret);
1072                 return ret;
1073         }
1074
1075         if (is_alloc && allocated_size)
1076                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_init_umv_space(struct hns3_hw *hw)
1083 {
1084         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085         struct hns3_pf *pf = &hns->pf;
1086         uint16_t allocated_size = 0;
1087         int ret;
1088
1089         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1090                                  true);
1091         if (ret)
1092                 return ret;
1093
1094         if (allocated_size < pf->wanted_umv_size)
1095                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096                              pf->wanted_umv_size, allocated_size);
1097
1098         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099                                                 pf->wanted_umv_size;
1100         pf->used_umv_size = 0;
1101         return 0;
1102 }
1103
1104 static int
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1106 {
1107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108         struct hns3_pf *pf = &hns->pf;
1109         int ret;
1110
1111         if (pf->max_umv_size == 0)
1112                 return 0;
1113
1114         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1115         if (ret)
1116                 return ret;
1117
1118         pf->max_umv_size = 0;
1119
1120         return 0;
1121 }
1122
1123 static bool
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1125 {
1126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127         struct hns3_pf *pf = &hns->pf;
1128         bool is_full;
1129
1130         is_full = (pf->used_umv_size >= pf->max_umv_size);
1131
1132         return is_full;
1133 }
1134
1135 static void
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1137 {
1138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139         struct hns3_pf *pf = &hns->pf;
1140
1141         if (is_free) {
1142                 if (pf->used_umv_size > 0)
1143                         pf->used_umv_size--;
1144         } else
1145                 pf->used_umv_size++;
1146 }
1147
1148 static void
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150                       const uint8_t *addr, bool is_mc)
1151 {
1152         const unsigned char *mac_addr = addr;
1153         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154                             ((uint32_t)mac_addr[2] << 16) |
1155                             ((uint32_t)mac_addr[1] << 8) |
1156                             (uint32_t)mac_addr[0];
1157         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1158
1159         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1160         if (is_mc) {
1161                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1164         }
1165
1166         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1168 }
1169
1170 static int
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1172                              uint8_t resp_code,
1173                              enum hns3_mac_vlan_tbl_opcode op)
1174 {
1175         if (cmdq_resp) {
1176                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1177                          cmdq_resp);
1178                 return -EIO;
1179         }
1180
1181         if (op == HNS3_MAC_VLAN_ADD) {
1182                 if (resp_code == 0 || resp_code == 1) {
1183                         return 0;
1184                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for uc_overflow");
1186                         return -ENOSPC;
1187                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188                         hns3_err(hw, "add mac addr failed for mc_overflow");
1189                         return -ENOSPC;
1190                 }
1191
1192                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1193                          resp_code);
1194                 return -EIO;
1195         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196                 if (resp_code == 0) {
1197                         return 0;
1198                 } else if (resp_code == 1) {
1199                         hns3_dbg(hw, "remove mac addr failed for miss");
1200                         return -ENOENT;
1201                 }
1202
1203                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_LKUP) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "lookup mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         }
1218
1219         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1220                  op);
1221
1222         return -EINVAL;
1223 }
1224
1225 static int
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1228                          struct hns3_cmd_desc *desc, bool is_mc)
1229 {
1230         uint8_t resp_code;
1231         uint16_t retval;
1232         int ret;
1233
1234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1235         if (is_mc) {
1236                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237                 memcpy(desc[0].data, req,
1238                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1243                                           true);
1244                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1245         } else {
1246                 memcpy(desc[0].data, req,
1247                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248                 ret = hns3_cmd_send(hw, desc, 1);
1249         }
1250         if (ret) {
1251                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1252                          ret);
1253                 return ret;
1254         }
1255         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256         retval = rte_le_to_cpu_16(desc[0].retval);
1257
1258         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259                                             HNS3_MAC_VLAN_LKUP);
1260 }
1261
1262 static int
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1265                       struct hns3_cmd_desc *mc_desc)
1266 {
1267         uint8_t resp_code;
1268         uint16_t retval;
1269         int cfg_status;
1270         int ret;
1271
1272         if (mc_desc == NULL) {
1273                 struct hns3_cmd_desc desc;
1274
1275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276                 memcpy(desc.data, req,
1277                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278                 ret = hns3_cmd_send(hw, &desc, 1);
1279                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280                 retval = rte_le_to_cpu_16(desc.retval);
1281
1282                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1283                                                           HNS3_MAC_VLAN_ADD);
1284         } else {
1285                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291                 memcpy(mc_desc[0].data, req,
1292                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293                 mc_desc[0].retval = 0;
1294                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1297
1298                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1299                                                           HNS3_MAC_VLAN_ADD);
1300         }
1301
1302         if (ret) {
1303                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1304                 return ret;
1305         }
1306
1307         return cfg_status;
1308 }
1309
1310 static int
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1313 {
1314         struct hns3_cmd_desc desc;
1315         uint8_t resp_code;
1316         uint16_t retval;
1317         int ret;
1318
1319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1320
1321         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322
1323         ret = hns3_cmd_send(hw, &desc, 1);
1324         if (ret) {
1325                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1326                 return ret;
1327         }
1328         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329         retval = rte_le_to_cpu_16(desc.retval);
1330
1331         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332                                             HNS3_MAC_VLAN_REMOVE);
1333 }
1334
1335 static int
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1337 {
1338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339         struct hns3_mac_vlan_tbl_entry_cmd req;
1340         struct hns3_pf *pf = &hns->pf;
1341         struct hns3_cmd_desc desc;
1342         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343         uint16_t egress_port = 0;
1344         uint8_t vf_id;
1345         int ret;
1346
1347         /* check if mac addr is valid */
1348         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1350                                       mac_addr);
1351                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1352                          mac_str);
1353                 return -EINVAL;
1354         }
1355
1356         memset(&req, 0, sizeof(req));
1357
1358         /*
1359          * In current version VF is not supported when PF is driven by DPDK
1360          * driver, the PF-related vf_id is 0, just need to configure parameters
1361          * for vf_id 0.
1362          */
1363         vf_id = 0;
1364         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365                        HNS3_MAC_EPORT_VFID_S, vf_id);
1366
1367         req.egress_port = rte_cpu_to_le_16(egress_port);
1368
1369         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1370
1371         /*
1372          * Lookup the mac address in the mac_vlan table, and add
1373          * it if the entry is inexistent. Repeated unicast entry
1374          * is not allowed in the mac vlan table.
1375          */
1376         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377         if (ret == -ENOENT) {
1378                 if (!hns3_is_umv_space_full(hw)) {
1379                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1380                         if (!ret)
1381                                 hns3_update_umv_space(hw, false);
1382                         return ret;
1383                 }
1384
1385                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1386
1387                 return -ENOSPC;
1388         }
1389
1390         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1391
1392         /* check if we just hit the duplicate */
1393         if (ret == 0) {
1394                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1395                 return 0;
1396         }
1397
1398         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1399                  mac_str);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1407 {
1408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1410         int ret;
1411
1412         rte_spinlock_lock(&hw->lock);
1413         ret = hns3_add_uc_addr_common(hw, mac_addr);
1414         if (ret) {
1415                 rte_spinlock_unlock(&hw->lock);
1416                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417                                       mac_addr);
1418                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1419                 return ret;
1420         }
1421
1422         if (idx == 0)
1423                 hw->mac.default_addr_setted = true;
1424         rte_spinlock_unlock(&hw->lock);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1431 {
1432         struct hns3_mac_vlan_tbl_entry_cmd req;
1433         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1434         int ret;
1435
1436         /* check if mac addr is valid */
1437         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1441                          mac_str);
1442                 return -EINVAL;
1443         }
1444
1445         memset(&req, 0, sizeof(req));
1446         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1450                 return 0;
1451         else if (ret == 0)
1452                 hns3_update_umv_space(hw, true);
1453
1454         return ret;
1455 }
1456
1457 static void
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1459 {
1460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         /* index will be checked by upper level rte interface */
1462         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         int ret;
1465
1466         rte_spinlock_lock(&hw->lock);
1467         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1468         if (ret) {
1469                 rte_spinlock_unlock(&hw->lock);
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1473                 return;
1474         }
1475
1476         if (idx == 0)
1477                 hw->mac.default_addr_setted = false;
1478         rte_spinlock_unlock(&hw->lock);
1479 }
1480
1481 static int
1482 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1483                           struct rte_ether_addr *mac_addr)
1484 {
1485         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486         struct rte_ether_addr *oaddr;
1487         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1488         bool default_addr_setted;
1489         bool rm_succes = false;
1490         int ret, ret_val;
1491
1492         /* check if mac addr is valid */
1493         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1494                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1495                                       mac_addr);
1496                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1497                          mac_str);
1498                 return -EINVAL;
1499         }
1500
1501         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1502         default_addr_setted = hw->mac.default_addr_setted;
1503         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1504                 return 0;
1505
1506         rte_spinlock_lock(&hw->lock);
1507         if (default_addr_setted) {
1508                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1509                 if (ret) {
1510                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1511                                               oaddr);
1512                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1513                                   mac_str, ret);
1514                         rm_succes = false;
1515                 } else
1516                         rm_succes = true;
1517         }
1518
1519         ret = hns3_add_uc_addr_common(hw, mac_addr);
1520         if (ret) {
1521                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1522                                       mac_addr);
1523                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1524                 goto err_add_uc_addr;
1525         }
1526
1527         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1528         if (ret) {
1529                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1530                 goto err_pause_addr_cfg;
1531         }
1532
1533         rte_ether_addr_copy(mac_addr,
1534                             (struct rte_ether_addr *)hw->mac.mac_addr);
1535         hw->mac.default_addr_setted = true;
1536         rte_spinlock_unlock(&hw->lock);
1537
1538         return 0;
1539
1540 err_pause_addr_cfg:
1541         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1542         if (ret_val) {
1543                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1544                                       mac_addr);
1545                 hns3_warn(hw,
1546                           "Failed to roll back to del setted mac addr(%s): %d",
1547                           mac_str, ret_val);
1548         }
1549
1550 err_add_uc_addr:
1551         if (rm_succes) {
1552                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1553                 if (ret_val) {
1554                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1555                                               oaddr);
1556                         hns3_warn(hw,
1557                                   "Failed to restore old uc mac addr(%s): %d",
1558                                   mac_str, ret_val);
1559                         hw->mac.default_addr_setted = false;
1560                 }
1561         }
1562         rte_spinlock_unlock(&hw->lock);
1563
1564         return ret;
1565 }
1566
1567 static int
1568 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1569 {
1570         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1571         struct hns3_hw *hw = &hns->hw;
1572         struct rte_ether_addr *addr;
1573         int err = 0;
1574         int ret;
1575         int i;
1576
1577         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1578                 addr = &hw->data->mac_addrs[i];
1579                 if (!rte_is_valid_assigned_ether_addr(addr))
1580                         continue;
1581                 if (del)
1582                         ret = hns3_remove_uc_addr_common(hw, addr);
1583                 else
1584                         ret = hns3_add_uc_addr_common(hw, addr);
1585                 if (ret) {
1586                         err = ret;
1587                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1588                                               addr);
1589                         hns3_dbg(hw,
1590                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1591                                  del ? "remove" : "restore", mac_str, ret, i);
1592                 }
1593         }
1594         return err;
1595 }
1596
1597 static void
1598 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1599 {
1600 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1601         uint8_t word_num;
1602         uint8_t bit_num;
1603
1604         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1605                 word_num = vfid / 32;
1606                 bit_num = vfid % 32;
1607                 if (clr)
1608                         desc[1].data[word_num] &=
1609                             rte_cpu_to_le_32(~(1UL << bit_num));
1610                 else
1611                         desc[1].data[word_num] |=
1612                             rte_cpu_to_le_32(1UL << bit_num);
1613         } else {
1614                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1615                 bit_num = vfid % 32;
1616                 if (clr)
1617                         desc[2].data[word_num] &=
1618                             rte_cpu_to_le_32(~(1UL << bit_num));
1619                 else
1620                         desc[2].data[word_num] |=
1621                             rte_cpu_to_le_32(1UL << bit_num);
1622         }
1623 }
1624
1625 static int
1626 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1627 {
1628         struct hns3_mac_vlan_tbl_entry_cmd req;
1629         struct hns3_cmd_desc desc[3];
1630         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1631         uint8_t vf_id;
1632         int ret;
1633
1634         /* Check if mac addr is valid */
1635         if (!rte_is_multicast_ether_addr(mac_addr)) {
1636                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1637                                       mac_addr);
1638                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1639                          mac_str);
1640                 return -EINVAL;
1641         }
1642
1643         memset(&req, 0, sizeof(req));
1644         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1645         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1646         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1647         if (ret) {
1648                 /* This mac addr do not exist, add new entry for it */
1649                 memset(desc[0].data, 0, sizeof(desc[0].data));
1650                 memset(desc[1].data, 0, sizeof(desc[0].data));
1651                 memset(desc[2].data, 0, sizeof(desc[0].data));
1652         }
1653
1654         /*
1655          * In current version VF is not supported when PF is driven by DPDK
1656          * driver, the PF-related vf_id is 0, just need to configure parameters
1657          * for vf_id 0.
1658          */
1659         vf_id = 0;
1660         hns3_update_desc_vfid(desc, vf_id, false);
1661         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1662         if (ret) {
1663                 if (ret == -ENOSPC)
1664                         hns3_err(hw, "mc mac vlan table is full");
1665                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1666                                       mac_addr);
1667                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1668         }
1669
1670         return ret;
1671 }
1672
1673 static int
1674 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1675 {
1676         struct hns3_mac_vlan_tbl_entry_cmd req;
1677         struct hns3_cmd_desc desc[3];
1678         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1679         uint8_t vf_id;
1680         int ret;
1681
1682         /* Check if mac addr is valid */
1683         if (!rte_is_multicast_ether_addr(mac_addr)) {
1684                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1685                                       mac_addr);
1686                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1687                          mac_str);
1688                 return -EINVAL;
1689         }
1690
1691         memset(&req, 0, sizeof(req));
1692         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1693         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1694         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1695         if (ret == 0) {
1696                 /*
1697                  * This mac addr exist, remove this handle's VFID for it.
1698                  * In current version VF is not supported when PF is driven by
1699                  * DPDK driver, the PF-related vf_id is 0, just need to
1700                  * configure parameters for vf_id 0.
1701                  */
1702                 vf_id = 0;
1703                 hns3_update_desc_vfid(desc, vf_id, true);
1704
1705                 /* All the vfid is zero, so need to delete this entry */
1706                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1707         } else if (ret == -ENOENT) {
1708                 /* This mac addr doesn't exist. */
1709                 return 0;
1710         }
1711
1712         if (ret) {
1713                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1714                                       mac_addr);
1715                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1716         }
1717
1718         return ret;
1719 }
1720
1721 static int
1722 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1723                            struct rte_ether_addr *mc_addr_set,
1724                            uint32_t nb_mc_addr)
1725 {
1726         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1727         struct rte_ether_addr *addr;
1728         uint32_t i;
1729         uint32_t j;
1730
1731         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1732                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1733                          "invalid. valid range: 0~%d",
1734                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1735                 return -EINVAL;
1736         }
1737
1738         /* Check if input mac addresses are valid */
1739         for (i = 0; i < nb_mc_addr; i++) {
1740                 addr = &mc_addr_set[i];
1741                 if (!rte_is_multicast_ether_addr(addr)) {
1742                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1743                                               addr);
1744                         hns3_err(hw,
1745                                  "Failed to set mc mac addr, addr(%s) invalid.",
1746                                  mac_str);
1747                         return -EINVAL;
1748                 }
1749
1750                 /* Check if there are duplicate addresses */
1751                 for (j = i + 1; j < nb_mc_addr; j++) {
1752                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1753                                 rte_ether_format_addr(mac_str,
1754                                                       RTE_ETHER_ADDR_FMT_SIZE,
1755                                                       addr);
1756                                 hns3_err(hw, "Failed to set mc mac addr, "
1757                                          "addrs invalid. two same addrs(%s).",
1758                                          mac_str);
1759                                 return -EINVAL;
1760                         }
1761                 }
1762         }
1763
1764         return 0;
1765 }
1766
1767 static void
1768 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1769                            struct rte_ether_addr *mc_addr_set,
1770                            int mc_addr_num,
1771                            struct rte_ether_addr *reserved_addr_list,
1772                            int *reserved_addr_num,
1773                            struct rte_ether_addr *add_addr_list,
1774                            int *add_addr_num,
1775                            struct rte_ether_addr *rm_addr_list,
1776                            int *rm_addr_num)
1777 {
1778         struct rte_ether_addr *addr;
1779         int current_addr_num;
1780         int reserved_num = 0;
1781         int add_num = 0;
1782         int rm_num = 0;
1783         int num;
1784         int i;
1785         int j;
1786         bool same_addr;
1787
1788         /* Calculate the mc mac address list that should be removed */
1789         current_addr_num = hw->mc_addrs_num;
1790         for (i = 0; i < current_addr_num; i++) {
1791                 addr = &hw->mc_addrs[i];
1792                 same_addr = false;
1793                 for (j = 0; j < mc_addr_num; j++) {
1794                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1795                                 same_addr = true;
1796                                 break;
1797                         }
1798                 }
1799
1800                 if (!same_addr) {
1801                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1802                         rm_num++;
1803                 } else {
1804                         rte_ether_addr_copy(addr,
1805                                             &reserved_addr_list[reserved_num]);
1806                         reserved_num++;
1807                 }
1808         }
1809
1810         /* Calculate the mc mac address list that should be added */
1811         for (i = 0; i < mc_addr_num; i++) {
1812                 addr = &mc_addr_set[i];
1813                 same_addr = false;
1814                 for (j = 0; j < current_addr_num; j++) {
1815                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1816                                 same_addr = true;
1817                                 break;
1818                         }
1819                 }
1820
1821                 if (!same_addr) {
1822                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1823                         add_num++;
1824                 }
1825         }
1826
1827         /* Reorder the mc mac address list maintained by driver */
1828         for (i = 0; i < reserved_num; i++)
1829                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1830
1831         for (i = 0; i < rm_num; i++) {
1832                 num = reserved_num + i;
1833                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1834         }
1835
1836         *reserved_addr_num = reserved_num;
1837         *add_addr_num = add_num;
1838         *rm_addr_num = rm_num;
1839 }
1840
1841 static int
1842 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1843                           struct rte_ether_addr *mc_addr_set,
1844                           uint32_t nb_mc_addr)
1845 {
1846         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1848         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1849         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1850         struct rte_ether_addr *addr;
1851         int reserved_addr_num;
1852         int add_addr_num;
1853         int rm_addr_num;
1854         int mc_addr_num;
1855         int num;
1856         int ret;
1857         int i;
1858
1859         /* Check if input parameters are valid */
1860         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1861         if (ret)
1862                 return ret;
1863
1864         rte_spinlock_lock(&hw->lock);
1865
1866         /*
1867          * Calculate the mc mac address lists those should be removed and be
1868          * added, Reorder the mc mac address list maintained by driver.
1869          */
1870         mc_addr_num = (int)nb_mc_addr;
1871         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1872                                    reserved_addr_list, &reserved_addr_num,
1873                                    add_addr_list, &add_addr_num,
1874                                    rm_addr_list, &rm_addr_num);
1875
1876         /* Remove mc mac addresses */
1877         for (i = 0; i < rm_addr_num; i++) {
1878                 num = rm_addr_num - i - 1;
1879                 addr = &rm_addr_list[num];
1880                 ret = hns3_remove_mc_addr(hw, addr);
1881                 if (ret) {
1882                         rte_spinlock_unlock(&hw->lock);
1883                         return ret;
1884                 }
1885                 hw->mc_addrs_num--;
1886         }
1887
1888         /* Add mc mac addresses */
1889         for (i = 0; i < add_addr_num; i++) {
1890                 addr = &add_addr_list[i];
1891                 ret = hns3_add_mc_addr(hw, addr);
1892                 if (ret) {
1893                         rte_spinlock_unlock(&hw->lock);
1894                         return ret;
1895                 }
1896
1897                 num = reserved_addr_num + i;
1898                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1899                 hw->mc_addrs_num++;
1900         }
1901         rte_spinlock_unlock(&hw->lock);
1902
1903         return 0;
1904 }
1905
1906 static int
1907 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1908 {
1909         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1910         struct hns3_hw *hw = &hns->hw;
1911         struct rte_ether_addr *addr;
1912         int err = 0;
1913         int ret;
1914         int i;
1915
1916         for (i = 0; i < hw->mc_addrs_num; i++) {
1917                 addr = &hw->mc_addrs[i];
1918                 if (!rte_is_multicast_ether_addr(addr))
1919                         continue;
1920                 if (del)
1921                         ret = hns3_remove_mc_addr(hw, addr);
1922                 else
1923                         ret = hns3_add_mc_addr(hw, addr);
1924                 if (ret) {
1925                         err = ret;
1926                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1927                                               addr);
1928                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1929                                  del ? "Remove" : "Restore", mac_str);
1930                 }
1931         }
1932         return err;
1933 }
1934
1935 static int
1936 hns3_check_mq_mode(struct rte_eth_dev *dev)
1937 {
1938         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1939         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1940         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1942         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1943         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1944         uint8_t num_tc;
1945         int max_tc = 0;
1946         int i;
1947
1948         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1949         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1950
1951         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1952                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1953                          "rx_mq_mode = %d", rx_mq_mode);
1954                 return -EINVAL;
1955         }
1956
1957         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1958             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1959                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1960                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1961                          rx_mq_mode, tx_mq_mode);
1962                 return -EINVAL;
1963         }
1964
1965         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1966                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1967                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1968                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1969                         return -EINVAL;
1970                 }
1971
1972                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1973                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1974                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1975                                  "nb_tcs(%d) != %d or %d in rx direction.",
1976                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1977                         return -EINVAL;
1978                 }
1979
1980                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1981                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1982                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1983                         return -EINVAL;
1984                 }
1985
1986                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1987                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1988                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1989                                          "is not equal to one in tx direction.",
1990                                          i, dcb_rx_conf->dcb_tc[i]);
1991                                 return -EINVAL;
1992                         }
1993                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1994                                 max_tc = dcb_rx_conf->dcb_tc[i];
1995                 }
1996
1997                 num_tc = max_tc + 1;
1998                 if (num_tc > dcb_rx_conf->nb_tcs) {
1999                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2000                                  num_tc, dcb_rx_conf->nb_tcs);
2001                         return -EINVAL;
2002                 }
2003         }
2004
2005         return 0;
2006 }
2007
2008 static int
2009 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2010 {
2011         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012
2013         if (!hns3_dev_dcb_supported(hw)) {
2014                 hns3_err(hw, "this port does not support dcb configurations.");
2015                 return -EOPNOTSUPP;
2016         }
2017
2018         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2019                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2020                 return -EOPNOTSUPP;
2021         }
2022
2023         /* Check multiple queue mode */
2024         return hns3_check_mq_mode(dev);
2025 }
2026
2027 static int
2028 hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
2029                            bool mmap, uint16_t queue_id)
2030 {
2031         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032         struct hns3_cmd_desc desc;
2033         struct hns3_ctrl_vector_chain_cmd *req =
2034                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2035         enum hns3_cmd_status status;
2036         enum hns3_opcode_type op;
2037         uint16_t tqp_type_and_id = 0;
2038
2039         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2040         hns3_cmd_setup_basic_desc(&desc, op, false);
2041         req->int_vector_id = vector_id;
2042
2043         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2044                        HNS3_RING_TYPE_RX);
2045         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2046         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2047                        HNS3_RING_GL_RX);
2048         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2049
2050         req->int_cause_num = 1;
2051         status = hns3_cmd_send(hw, &desc, 1);
2052         if (status) {
2053                 hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
2054                          queue_id, vector_id, status);
2055                 return -EIO;
2056         }
2057
2058         return 0;
2059 }
2060
2061 static int
2062 hns3_dev_configure(struct rte_eth_dev *dev)
2063 {
2064         struct hns3_adapter *hns = dev->data->dev_private;
2065         struct rte_eth_conf *conf = &dev->data->dev_conf;
2066         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2067         struct hns3_hw *hw = &hns->hw;
2068         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2069         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2070         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2071         struct rte_eth_rss_conf rss_conf;
2072         uint16_t mtu;
2073         int ret;
2074
2075         /*
2076          * Hardware does not support individually enable/disable/reset the Tx or
2077          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2078          * and Rx queues at the same time. When the numbers of Tx queues
2079          * allocated by upper applications are not equal to the numbers of Rx
2080          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2081          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2082          * these fake queues are imperceptible, and can not be used by upper
2083          * applications.
2084          */
2085         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2086         if (ret) {
2087                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2088                 return ret;
2089         }
2090
2091         hw->adapter_state = HNS3_NIC_CONFIGURING;
2092         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2093                 hns3_err(hw, "setting link speed/duplex not supported");
2094                 ret = -EINVAL;
2095                 goto cfg_err;
2096         }
2097
2098         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2099                 ret = hns3_check_dcb_cfg(dev);
2100                 if (ret)
2101                         goto cfg_err;
2102         }
2103
2104         /* When RSS is not configured, redirect the packet queue 0 */
2105         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2106                 rss_conf = conf->rx_adv_conf.rss_conf;
2107                 if (rss_conf.rss_key == NULL) {
2108                         rss_conf.rss_key = rss_cfg->key;
2109                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2110                 }
2111
2112                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2113                 if (ret)
2114                         goto cfg_err;
2115         }
2116
2117         /*
2118          * If jumbo frames are enabled, MTU needs to be refreshed
2119          * according to the maximum RX packet length.
2120          */
2121         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2122                 /*
2123                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2124                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2125                  * can safely assign to "uint16_t" type variable.
2126                  */
2127                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2128                 ret = hns3_dev_mtu_set(dev, mtu);
2129                 if (ret)
2130                         goto cfg_err;
2131                 dev->data->mtu = mtu;
2132         }
2133
2134         ret = hns3_dev_configure_vlan(dev);
2135         if (ret)
2136                 goto cfg_err;
2137
2138         hw->adapter_state = HNS3_NIC_CONFIGURED;
2139
2140         return 0;
2141
2142 cfg_err:
2143         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2144         hw->adapter_state = HNS3_NIC_INITIALIZED;
2145
2146         return ret;
2147 }
2148
2149 static int
2150 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2151 {
2152         struct hns3_config_max_frm_size_cmd *req;
2153         struct hns3_cmd_desc desc;
2154
2155         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2156
2157         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2158         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2159         req->min_frm_size = RTE_ETHER_MIN_LEN;
2160
2161         return hns3_cmd_send(hw, &desc, 1);
2162 }
2163
2164 static int
2165 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2166 {
2167         int ret;
2168
2169         ret = hns3_set_mac_mtu(hw, mps);
2170         if (ret) {
2171                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2172                 return ret;
2173         }
2174
2175         ret = hns3_buffer_alloc(hw);
2176         if (ret) {
2177                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2178                 return ret;
2179         }
2180
2181         return 0;
2182 }
2183
2184 static int
2185 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2186 {
2187         struct hns3_adapter *hns = dev->data->dev_private;
2188         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2189         struct hns3_hw *hw = &hns->hw;
2190         bool is_jumbo_frame;
2191         int ret;
2192
2193         if (dev->data->dev_started) {
2194                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2195                          "before configuration", dev->data->port_id);
2196                 return -EBUSY;
2197         }
2198
2199         rte_spinlock_lock(&hw->lock);
2200         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2201         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2202
2203         /*
2204          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2205          * assign to "uint16_t" type variable.
2206          */
2207         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2208         if (ret) {
2209                 rte_spinlock_unlock(&hw->lock);
2210                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2211                          dev->data->port_id, mtu, ret);
2212                 return ret;
2213         }
2214         hns->pf.mps = (uint16_t)frame_size;
2215         if (is_jumbo_frame)
2216                 dev->data->dev_conf.rxmode.offloads |=
2217                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2218         else
2219                 dev->data->dev_conf.rxmode.offloads &=
2220                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2221         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2222         rte_spinlock_unlock(&hw->lock);
2223
2224         return 0;
2225 }
2226
2227 static int
2228 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2229 {
2230         struct hns3_adapter *hns = eth_dev->data->dev_private;
2231         struct hns3_hw *hw = &hns->hw;
2232
2233         info->max_rx_queues = hw->tqps_num;
2234         info->max_tx_queues = hw->tqps_num;
2235         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2236         info->min_rx_bufsize = hw->rx_buf_len;
2237         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2238         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2239         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2240                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2241                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2242                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2243                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2244                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2245                                  DEV_RX_OFFLOAD_KEEP_CRC |
2246                                  DEV_RX_OFFLOAD_SCATTER |
2247                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2248                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2249                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2250                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2251                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2252         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2253         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2254                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2255                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2256                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2257                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2258                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2259                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2260                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2261                                  info->tx_queue_offload_capa);
2262
2263         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2264                 .nb_max = HNS3_MAX_RING_DESC,
2265                 .nb_min = HNS3_MIN_RING_DESC,
2266                 .nb_align = HNS3_ALIGN_RING_DESC,
2267         };
2268
2269         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2270                 .nb_max = HNS3_MAX_RING_DESC,
2271                 .nb_min = HNS3_MIN_RING_DESC,
2272                 .nb_align = HNS3_ALIGN_RING_DESC,
2273         };
2274
2275         info->vmdq_queue_num = 0;
2276
2277         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2278         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2279         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2280
2281         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2282         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2283         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2284         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2285         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2286         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2287
2288         return 0;
2289 }
2290
2291 static int
2292 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2293                     size_t fw_size)
2294 {
2295         struct hns3_adapter *hns = eth_dev->data->dev_private;
2296         struct hns3_hw *hw = &hns->hw;
2297         int ret;
2298
2299         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2300         ret += 1; /* add the size of '\0' */
2301         if (fw_size < (uint32_t)ret)
2302                 return ret;
2303         else
2304                 return 0;
2305 }
2306
2307 static int
2308 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2309                      __rte_unused int wait_to_complete)
2310 {
2311         struct hns3_adapter *hns = eth_dev->data->dev_private;
2312         struct hns3_hw *hw = &hns->hw;
2313         struct hns3_mac *mac = &hw->mac;
2314         struct rte_eth_link new_link;
2315
2316         if (!hns3_is_reset_pending(hns)) {
2317                 hns3_update_speed_duplex(eth_dev);
2318                 hns3_update_link_status(hw);
2319         }
2320
2321         memset(&new_link, 0, sizeof(new_link));
2322         switch (mac->link_speed) {
2323         case ETH_SPEED_NUM_10M:
2324         case ETH_SPEED_NUM_100M:
2325         case ETH_SPEED_NUM_1G:
2326         case ETH_SPEED_NUM_10G:
2327         case ETH_SPEED_NUM_25G:
2328         case ETH_SPEED_NUM_40G:
2329         case ETH_SPEED_NUM_50G:
2330         case ETH_SPEED_NUM_100G:
2331                 new_link.link_speed = mac->link_speed;
2332                 break;
2333         default:
2334                 new_link.link_speed = ETH_SPEED_NUM_100M;
2335                 break;
2336         }
2337
2338         new_link.link_duplex = mac->link_duplex;
2339         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2340         new_link.link_autoneg =
2341             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2342
2343         return rte_eth_linkstatus_set(eth_dev, &new_link);
2344 }
2345
2346 static int
2347 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2348 {
2349         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2350         struct hns3_pf *pf = &hns->pf;
2351
2352         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2353                 return -EINVAL;
2354
2355         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2356
2357         return 0;
2358 }
2359
2360 static int
2361 hns3_query_function_status(struct hns3_hw *hw)
2362 {
2363 #define HNS3_QUERY_MAX_CNT              10
2364 #define HNS3_QUERY_SLEEP_MSCOEND        1
2365         struct hns3_func_status_cmd *req;
2366         struct hns3_cmd_desc desc;
2367         int timeout = 0;
2368         int ret;
2369
2370         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2371         req = (struct hns3_func_status_cmd *)desc.data;
2372
2373         do {
2374                 ret = hns3_cmd_send(hw, &desc, 1);
2375                 if (ret) {
2376                         PMD_INIT_LOG(ERR, "query function status failed %d",
2377                                      ret);
2378                         return ret;
2379                 }
2380
2381                 /* Check pf reset is done */
2382                 if (req->pf_state)
2383                         break;
2384
2385                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2386         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2387
2388         return hns3_parse_func_status(hw, req);
2389 }
2390
2391 static int
2392 hns3_query_pf_resource(struct hns3_hw *hw)
2393 {
2394         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2395         struct hns3_pf *pf = &hns->pf;
2396         struct hns3_pf_res_cmd *req;
2397         struct hns3_cmd_desc desc;
2398         int ret;
2399
2400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2401         ret = hns3_cmd_send(hw, &desc, 1);
2402         if (ret) {
2403                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2404                 return ret;
2405         }
2406
2407         req = (struct hns3_pf_res_cmd *)desc.data;
2408         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2409         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2410         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2411         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2412
2413         if (req->tx_buf_size)
2414                 pf->tx_buf_size =
2415                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2416         else
2417                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2418
2419         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2420
2421         if (req->dv_buf_size)
2422                 pf->dv_buf_size =
2423                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2424         else
2425                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2426
2427         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2428
2429         hw->num_msi =
2430             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2431                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2432
2433         return 0;
2434 }
2435
2436 static void
2437 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2438 {
2439         struct hns3_cfg_param_cmd *req;
2440         uint64_t mac_addr_tmp_high;
2441         uint64_t mac_addr_tmp;
2442         uint32_t i;
2443
2444         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2445
2446         /* get the configuration */
2447         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2448                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2449         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2450                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2451         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2452                                            HNS3_CFG_TQP_DESC_N_M,
2453                                            HNS3_CFG_TQP_DESC_N_S);
2454
2455         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2456                                        HNS3_CFG_PHY_ADDR_M,
2457                                        HNS3_CFG_PHY_ADDR_S);
2458         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2459                                          HNS3_CFG_MEDIA_TP_M,
2460                                          HNS3_CFG_MEDIA_TP_S);
2461         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2462                                          HNS3_CFG_RX_BUF_LEN_M,
2463                                          HNS3_CFG_RX_BUF_LEN_S);
2464         /* get mac address */
2465         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2466         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2467                                            HNS3_CFG_MAC_ADDR_H_M,
2468                                            HNS3_CFG_MAC_ADDR_H_S);
2469
2470         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2471
2472         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2473                                             HNS3_CFG_DEFAULT_SPEED_M,
2474                                             HNS3_CFG_DEFAULT_SPEED_S);
2475         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2476                                            HNS3_CFG_RSS_SIZE_M,
2477                                            HNS3_CFG_RSS_SIZE_S);
2478
2479         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2480                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2481
2482         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2483         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2484
2485         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2486                                             HNS3_CFG_SPEED_ABILITY_M,
2487                                             HNS3_CFG_SPEED_ABILITY_S);
2488         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2489                                         HNS3_CFG_UMV_TBL_SPACE_M,
2490                                         HNS3_CFG_UMV_TBL_SPACE_S);
2491         if (!cfg->umv_space)
2492                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2493 }
2494
2495 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2496  * @hw: pointer to struct hns3_hw
2497  * @hcfg: the config structure to be getted
2498  */
2499 static int
2500 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2501 {
2502         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2503         struct hns3_cfg_param_cmd *req;
2504         uint32_t offset;
2505         uint32_t i;
2506         int ret;
2507
2508         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2509                 offset = 0;
2510                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2511                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2512                                           true);
2513                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2514                                i * HNS3_CFG_RD_LEN_BYTES);
2515                 /* Len should be divided by 4 when send to hardware */
2516                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2517                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2518                 req->offset = rte_cpu_to_le_32(offset);
2519         }
2520
2521         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2522         if (ret) {
2523                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2524                 return ret;
2525         }
2526
2527         hns3_parse_cfg(hcfg, desc);
2528
2529         return 0;
2530 }
2531
2532 static int
2533 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2534 {
2535         switch (speed_cmd) {
2536         case HNS3_CFG_SPEED_10M:
2537                 *speed = ETH_SPEED_NUM_10M;
2538                 break;
2539         case HNS3_CFG_SPEED_100M:
2540                 *speed = ETH_SPEED_NUM_100M;
2541                 break;
2542         case HNS3_CFG_SPEED_1G:
2543                 *speed = ETH_SPEED_NUM_1G;
2544                 break;
2545         case HNS3_CFG_SPEED_10G:
2546                 *speed = ETH_SPEED_NUM_10G;
2547                 break;
2548         case HNS3_CFG_SPEED_25G:
2549                 *speed = ETH_SPEED_NUM_25G;
2550                 break;
2551         case HNS3_CFG_SPEED_40G:
2552                 *speed = ETH_SPEED_NUM_40G;
2553                 break;
2554         case HNS3_CFG_SPEED_50G:
2555                 *speed = ETH_SPEED_NUM_50G;
2556                 break;
2557         case HNS3_CFG_SPEED_100G:
2558                 *speed = ETH_SPEED_NUM_100G;
2559                 break;
2560         default:
2561                 return -EINVAL;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static int
2568 hns3_get_board_configuration(struct hns3_hw *hw)
2569 {
2570         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2571         struct hns3_pf *pf = &hns->pf;
2572         struct hns3_cfg cfg;
2573         int ret;
2574
2575         ret = hns3_get_board_cfg(hw, &cfg);
2576         if (ret) {
2577                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2578                 return ret;
2579         }
2580
2581         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2582                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2583                 return -EOPNOTSUPP;
2584         }
2585
2586         hw->mac.media_type = cfg.media_type;
2587         hw->rss_size_max = cfg.rss_size_max;
2588         hw->rx_buf_len = cfg.rx_buf_len;
2589         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2590         hw->mac.phy_addr = cfg.phy_addr;
2591         hw->mac.default_addr_setted = false;
2592         hw->num_tx_desc = cfg.tqp_desc_num;
2593         hw->num_rx_desc = cfg.tqp_desc_num;
2594         hw->dcb_info.num_pg = 1;
2595         hw->dcb_info.hw_pfc_map = 0;
2596
2597         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2598         if (ret) {
2599                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2600                              cfg.default_speed, ret);
2601                 return ret;
2602         }
2603
2604         pf->tc_max = cfg.tc_num;
2605         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2606                 PMD_INIT_LOG(WARNING,
2607                              "Get TC num(%u) from flash, set TC num to 1",
2608                              pf->tc_max);
2609                 pf->tc_max = 1;
2610         }
2611
2612         /* Dev does not support DCB */
2613         if (!hns3_dev_dcb_supported(hw)) {
2614                 pf->tc_max = 1;
2615                 pf->pfc_max = 0;
2616         } else
2617                 pf->pfc_max = pf->tc_max;
2618
2619         hw->dcb_info.num_tc = 1;
2620         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2621                                      hw->tqps_num / hw->dcb_info.num_tc);
2622         hns3_set_bit(hw->hw_tc_map, 0, 1);
2623         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2624
2625         pf->wanted_umv_size = cfg.umv_space;
2626
2627         return ret;
2628 }
2629
2630 static int
2631 hns3_get_configuration(struct hns3_hw *hw)
2632 {
2633         int ret;
2634
2635         ret = hns3_query_function_status(hw);
2636         if (ret) {
2637                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2638                 return ret;
2639         }
2640
2641         /* Get pf resource */
2642         ret = hns3_query_pf_resource(hw);
2643         if (ret) {
2644                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2645                 return ret;
2646         }
2647
2648         ret = hns3_get_board_configuration(hw);
2649         if (ret) {
2650                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2651                 return ret;
2652         }
2653
2654         return 0;
2655 }
2656
2657 static int
2658 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2659                       uint16_t tqp_vid, bool is_pf)
2660 {
2661         struct hns3_tqp_map_cmd *req;
2662         struct hns3_cmd_desc desc;
2663         int ret;
2664
2665         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2666
2667         req = (struct hns3_tqp_map_cmd *)desc.data;
2668         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2669         req->tqp_vf = func_id;
2670         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2671         if (!is_pf)
2672                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2673         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2674
2675         ret = hns3_cmd_send(hw, &desc, 1);
2676         if (ret)
2677                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2678
2679         return ret;
2680 }
2681
2682 static int
2683 hns3_map_tqp(struct hns3_hw *hw)
2684 {
2685         uint16_t tqps_num = hw->total_tqps_num;
2686         uint16_t func_id;
2687         uint16_t tqp_id;
2688         bool is_pf;
2689         int num;
2690         int ret;
2691         int i;
2692
2693         /*
2694          * In current version VF is not supported when PF is driven by DPDK
2695          * driver, so we allocate tqps to PF as much as possible.
2696          */
2697         tqp_id = 0;
2698         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2699         for (func_id = 0; func_id < num; func_id++) {
2700                 is_pf = func_id == 0 ? true : false;
2701                 for (i = 0;
2702                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2703                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2704                                                     is_pf);
2705                         if (ret)
2706                                 return ret;
2707                 }
2708         }
2709
2710         return 0;
2711 }
2712
2713 static int
2714 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2715 {
2716         struct hns3_config_mac_speed_dup_cmd *req;
2717         struct hns3_cmd_desc desc;
2718         int ret;
2719
2720         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2721
2722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2723
2724         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2725
2726         switch (speed) {
2727         case ETH_SPEED_NUM_10M:
2728                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2729                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2730                 break;
2731         case ETH_SPEED_NUM_100M:
2732                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2733                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2734                 break;
2735         case ETH_SPEED_NUM_1G:
2736                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2737                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2738                 break;
2739         case ETH_SPEED_NUM_10G:
2740                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2741                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2742                 break;
2743         case ETH_SPEED_NUM_25G:
2744                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2745                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2746                 break;
2747         case ETH_SPEED_NUM_40G:
2748                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2749                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2750                 break;
2751         case ETH_SPEED_NUM_50G:
2752                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2753                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2754                 break;
2755         case ETH_SPEED_NUM_100G:
2756                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2757                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2758                 break;
2759         default:
2760                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2761                 return -EINVAL;
2762         }
2763
2764         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2765
2766         ret = hns3_cmd_send(hw, &desc, 1);
2767         if (ret)
2768                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2769
2770         return ret;
2771 }
2772
2773 static int
2774 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2775 {
2776         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2777         struct hns3_pf *pf = &hns->pf;
2778         struct hns3_priv_buf *priv;
2779         uint32_t i, total_size;
2780
2781         total_size = pf->pkt_buf_size;
2782
2783         /* alloc tx buffer for all enabled tc */
2784         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2785                 priv = &buf_alloc->priv_buf[i];
2786
2787                 if (hw->hw_tc_map & BIT(i)) {
2788                         if (total_size < pf->tx_buf_size)
2789                                 return -ENOMEM;
2790
2791                         priv->tx_buf_size = pf->tx_buf_size;
2792                 } else
2793                         priv->tx_buf_size = 0;
2794
2795                 total_size -= priv->tx_buf_size;
2796         }
2797
2798         return 0;
2799 }
2800
2801 static int
2802 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2803 {
2804 /* TX buffer size is unit by 128 byte */
2805 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2806 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2807         struct hns3_tx_buff_alloc_cmd *req;
2808         struct hns3_cmd_desc desc;
2809         uint32_t buf_size;
2810         uint32_t i;
2811         int ret;
2812
2813         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2814
2815         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2816         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2817                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2818
2819                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2820                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2821                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2822         }
2823
2824         ret = hns3_cmd_send(hw, &desc, 1);
2825         if (ret)
2826                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2827
2828         return ret;
2829 }
2830
2831 static int
2832 hns3_get_tc_num(struct hns3_hw *hw)
2833 {
2834         int cnt = 0;
2835         uint8_t i;
2836
2837         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2838                 if (hw->hw_tc_map & BIT(i))
2839                         cnt++;
2840         return cnt;
2841 }
2842
2843 static uint32_t
2844 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2845 {
2846         struct hns3_priv_buf *priv;
2847         uint32_t rx_priv = 0;
2848         int i;
2849
2850         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2851                 priv = &buf_alloc->priv_buf[i];
2852                 if (priv->enable)
2853                         rx_priv += priv->buf_size;
2854         }
2855         return rx_priv;
2856 }
2857
2858 static uint32_t
2859 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2860 {
2861         uint32_t total_tx_size = 0;
2862         uint32_t i;
2863
2864         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2865                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2866
2867         return total_tx_size;
2868 }
2869
2870 /* Get the number of pfc enabled TCs, which have private buffer */
2871 static int
2872 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2873 {
2874         struct hns3_priv_buf *priv;
2875         int cnt = 0;
2876         uint8_t i;
2877
2878         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2879                 priv = &buf_alloc->priv_buf[i];
2880                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2881                         cnt++;
2882         }
2883
2884         return cnt;
2885 }
2886
2887 /* Get the number of pfc disabled TCs, which have private buffer */
2888 static int
2889 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2890                          struct hns3_pkt_buf_alloc *buf_alloc)
2891 {
2892         struct hns3_priv_buf *priv;
2893         int cnt = 0;
2894         uint8_t i;
2895
2896         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2897                 priv = &buf_alloc->priv_buf[i];
2898                 if (hw->hw_tc_map & BIT(i) &&
2899                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2900                         cnt++;
2901         }
2902
2903         return cnt;
2904 }
2905
2906 static bool
2907 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2908                   uint32_t rx_all)
2909 {
2910         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2911         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2912         struct hns3_pf *pf = &hns->pf;
2913         uint32_t shared_buf, aligned_mps;
2914         uint32_t rx_priv;
2915         uint8_t tc_num;
2916         uint8_t i;
2917
2918         tc_num = hns3_get_tc_num(hw);
2919         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2920
2921         if (hns3_dev_dcb_supported(hw))
2922                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2923                                         pf->dv_buf_size;
2924         else
2925                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2926                                         + pf->dv_buf_size;
2927
2928         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2929         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2930                              HNS3_BUF_SIZE_UNIT);
2931
2932         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2933         if (rx_all < rx_priv + shared_std)
2934                 return false;
2935
2936         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2937         buf_alloc->s_buf.buf_size = shared_buf;
2938         if (hns3_dev_dcb_supported(hw)) {
2939                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2940                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2941                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2942                                   HNS3_BUF_SIZE_UNIT);
2943         } else {
2944                 buf_alloc->s_buf.self.high =
2945                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2946                 buf_alloc->s_buf.self.low = aligned_mps;
2947         }
2948
2949         if (hns3_dev_dcb_supported(hw)) {
2950                 hi_thrd = shared_buf - pf->dv_buf_size;
2951
2952                 if (tc_num <= NEED_RESERVE_TC_NUM)
2953                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2954                                         / BUF_MAX_PERCENT;
2955
2956                 if (tc_num)
2957                         hi_thrd = hi_thrd / tc_num;
2958
2959                 hi_thrd = max_t(uint32_t, hi_thrd,
2960                                 HNS3_BUF_MUL_BY * aligned_mps);
2961                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2962                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2963         } else {
2964                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2965                 lo_thrd = aligned_mps;
2966         }
2967
2968         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2969                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2970                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2971         }
2972
2973         return true;
2974 }
2975
2976 static bool
2977 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2978                      struct hns3_pkt_buf_alloc *buf_alloc)
2979 {
2980         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2981         struct hns3_pf *pf = &hns->pf;
2982         struct hns3_priv_buf *priv;
2983         uint32_t aligned_mps;
2984         uint32_t rx_all;
2985         uint8_t i;
2986
2987         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2988         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2989
2990         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2991                 priv = &buf_alloc->priv_buf[i];
2992
2993                 priv->enable = 0;
2994                 priv->wl.low = 0;
2995                 priv->wl.high = 0;
2996                 priv->buf_size = 0;
2997
2998                 if (!(hw->hw_tc_map & BIT(i)))
2999                         continue;
3000
3001                 priv->enable = 1;
3002                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3003                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3004                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3005                                                 HNS3_BUF_SIZE_UNIT);
3006                 } else {
3007                         priv->wl.low = 0;
3008                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3009                                         aligned_mps;
3010                 }
3011
3012                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3013         }
3014
3015         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3016 }
3017
3018 static bool
3019 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3020                              struct hns3_pkt_buf_alloc *buf_alloc)
3021 {
3022         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3023         struct hns3_pf *pf = &hns->pf;
3024         struct hns3_priv_buf *priv;
3025         int no_pfc_priv_num;
3026         uint32_t rx_all;
3027         uint8_t mask;
3028         int i;
3029
3030         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3031         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3032
3033         /* let the last to be cleared first */
3034         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3035                 priv = &buf_alloc->priv_buf[i];
3036                 mask = BIT((uint8_t)i);
3037
3038                 if (hw->hw_tc_map & mask &&
3039                     !(hw->dcb_info.hw_pfc_map & mask)) {
3040                         /* Clear the no pfc TC private buffer */
3041                         priv->wl.low = 0;
3042                         priv->wl.high = 0;
3043                         priv->buf_size = 0;
3044                         priv->enable = 0;
3045                         no_pfc_priv_num--;
3046                 }
3047
3048                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3049                     no_pfc_priv_num == 0)
3050                         break;
3051         }
3052
3053         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3054 }
3055
3056 static bool
3057 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3058                            struct hns3_pkt_buf_alloc *buf_alloc)
3059 {
3060         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3061         struct hns3_pf *pf = &hns->pf;
3062         struct hns3_priv_buf *priv;
3063         uint32_t rx_all;
3064         int pfc_priv_num;
3065         uint8_t mask;
3066         int i;
3067
3068         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3069         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3070
3071         /* let the last to be cleared first */
3072         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3073                 priv = &buf_alloc->priv_buf[i];
3074                 mask = BIT((uint8_t)i);
3075
3076                 if (hw->hw_tc_map & mask &&
3077                     hw->dcb_info.hw_pfc_map & mask) {
3078                         /* Reduce the number of pfc TC with private buffer */
3079                         priv->wl.low = 0;
3080                         priv->enable = 0;
3081                         priv->wl.high = 0;
3082                         priv->buf_size = 0;
3083                         pfc_priv_num--;
3084                 }
3085                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3086                     pfc_priv_num == 0)
3087                         break;
3088         }
3089
3090         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3091 }
3092
3093 static bool
3094 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3095                           struct hns3_pkt_buf_alloc *buf_alloc)
3096 {
3097 #define COMPENSATE_BUFFER       0x3C00
3098 #define COMPENSATE_HALF_MPS_NUM 5
3099 #define PRIV_WL_GAP             0x1800
3100         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3101         struct hns3_pf *pf = &hns->pf;
3102         uint32_t tc_num = hns3_get_tc_num(hw);
3103         uint32_t half_mps = pf->mps >> 1;
3104         struct hns3_priv_buf *priv;
3105         uint32_t min_rx_priv;
3106         uint32_t rx_priv;
3107         uint8_t i;
3108
3109         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3110         if (tc_num)
3111                 rx_priv = rx_priv / tc_num;
3112
3113         if (tc_num <= NEED_RESERVE_TC_NUM)
3114                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3115
3116         /*
3117          * Minimum value of private buffer in rx direction (min_rx_priv) is
3118          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3119          * buffer if rx_priv is greater than min_rx_priv.
3120          */
3121         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3122                         COMPENSATE_HALF_MPS_NUM * half_mps;
3123         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3124         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3125
3126         if (rx_priv < min_rx_priv)
3127                 return false;
3128
3129         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3130                 priv = &buf_alloc->priv_buf[i];
3131
3132                 priv->enable = 0;
3133                 priv->wl.low = 0;
3134                 priv->wl.high = 0;
3135                 priv->buf_size = 0;
3136
3137                 if (!(hw->hw_tc_map & BIT(i)))
3138                         continue;
3139
3140                 priv->enable = 1;
3141                 priv->buf_size = rx_priv;
3142                 priv->wl.high = rx_priv - pf->dv_buf_size;
3143                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3144         }
3145
3146         buf_alloc->s_buf.buf_size = 0;
3147
3148         return true;
3149 }
3150
3151 /*
3152  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3153  * @hw: pointer to struct hns3_hw
3154  * @buf_alloc: pointer to buffer calculation data
3155  * @return: 0: calculate sucessful, negative: fail
3156  */
3157 static int
3158 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3159 {
3160         /* When DCB is not supported, rx private buffer is not allocated. */
3161         if (!hns3_dev_dcb_supported(hw)) {
3162                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3163                 struct hns3_pf *pf = &hns->pf;
3164                 uint32_t rx_all = pf->pkt_buf_size;
3165
3166                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3167                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3168                         return -ENOMEM;
3169
3170                 return 0;
3171         }
3172
3173         /*
3174          * Try to allocate privated packet buffer for all TCs without share
3175          * buffer.
3176          */
3177         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3178                 return 0;
3179
3180         /*
3181          * Try to allocate privated packet buffer for all TCs with share
3182          * buffer.
3183          */
3184         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3185                 return 0;
3186
3187         /*
3188          * For different application scenes, the enabled port number, TC number
3189          * and no_drop TC number are different. In order to obtain the better
3190          * performance, software could allocate the buffer size and configure
3191          * the waterline by tring to decrease the private buffer size according
3192          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3193          * enabled tc.
3194          */
3195         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3196                 return 0;
3197
3198         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3199                 return 0;
3200
3201         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3202                 return 0;
3203
3204         return -ENOMEM;
3205 }
3206
3207 static int
3208 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3209 {
3210         struct hns3_rx_priv_buff_cmd *req;
3211         struct hns3_cmd_desc desc;
3212         uint32_t buf_size;
3213         int ret;
3214         int i;
3215
3216         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3217         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3218
3219         /* Alloc private buffer TCs */
3220         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3221                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3222
3223                 req->buf_num[i] =
3224                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3225                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3226         }
3227
3228         buf_size = buf_alloc->s_buf.buf_size;
3229         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3230                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3231
3232         ret = hns3_cmd_send(hw, &desc, 1);
3233         if (ret)
3234                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3235
3236         return ret;
3237 }
3238
3239 static int
3240 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3241 {
3242 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3243         struct hns3_rx_priv_wl_buf *req;
3244         struct hns3_priv_buf *priv;
3245         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3246         int i, j;
3247         int ret;
3248
3249         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3250                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3251                                           false);
3252                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3253
3254                 /* The first descriptor set the NEXT bit to 1 */
3255                 if (i == 0)
3256                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3257                 else
3258                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3259
3260                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3261                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3262
3263                         priv = &buf_alloc->priv_buf[idx];
3264                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3265                                                         HNS3_BUF_UNIT_S);
3266                         req->tc_wl[j].high |=
3267                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3268                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3269                                                         HNS3_BUF_UNIT_S);
3270                         req->tc_wl[j].low |=
3271                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3272                 }
3273         }
3274
3275         /* Send 2 descriptor at one time */
3276         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3277         if (ret)
3278                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3279                              ret);
3280         return ret;
3281 }
3282
3283 static int
3284 hns3_common_thrd_config(struct hns3_hw *hw,
3285                         struct hns3_pkt_buf_alloc *buf_alloc)
3286 {
3287 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3288         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3289         struct hns3_rx_com_thrd *req;
3290         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3291         struct hns3_tc_thrd *tc;
3292         int tc_idx;
3293         int i, j;
3294         int ret;
3295
3296         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3297                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3298                                           false);
3299                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3300
3301                 /* The first descriptor set the NEXT bit to 1 */
3302                 if (i == 0)
3303                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3304                 else
3305                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3306
3307                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3308                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3309                         tc = &s_buf->tc_thrd[tc_idx];
3310
3311                         req->com_thrd[j].high =
3312                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3313                         req->com_thrd[j].high |=
3314                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3315                         req->com_thrd[j].low =
3316                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3317                         req->com_thrd[j].low |=
3318                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3319                 }
3320         }
3321
3322         /* Send 2 descriptors at one time */
3323         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3324         if (ret)
3325                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3326
3327         return ret;
3328 }
3329
3330 static int
3331 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3332 {
3333         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3334         struct hns3_rx_com_wl *req;
3335         struct hns3_cmd_desc desc;
3336         int ret;
3337
3338         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3339
3340         req = (struct hns3_rx_com_wl *)desc.data;
3341         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3342         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3343
3344         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3345         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3346
3347         ret = hns3_cmd_send(hw, &desc, 1);
3348         if (ret)
3349                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3350
3351         return ret;
3352 }
3353
3354 int
3355 hns3_buffer_alloc(struct hns3_hw *hw)
3356 {
3357         struct hns3_pkt_buf_alloc pkt_buf;
3358         int ret;
3359
3360         memset(&pkt_buf, 0, sizeof(pkt_buf));
3361         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3362         if (ret) {
3363                 PMD_INIT_LOG(ERR,
3364                              "could not calc tx buffer size for all TCs %d",
3365                              ret);
3366                 return ret;
3367         }
3368
3369         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3370         if (ret) {
3371                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3372                 return ret;
3373         }
3374
3375         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3376         if (ret) {
3377                 PMD_INIT_LOG(ERR,
3378                              "could not calc rx priv buffer size for all TCs %d",
3379                              ret);
3380                 return ret;
3381         }
3382
3383         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3384         if (ret) {
3385                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3386                 return ret;
3387         }
3388
3389         if (hns3_dev_dcb_supported(hw)) {
3390                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3391                 if (ret) {
3392                         PMD_INIT_LOG(ERR,
3393                                      "could not configure rx private waterline %d",
3394                                      ret);
3395                         return ret;
3396                 }
3397
3398                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3399                 if (ret) {
3400                         PMD_INIT_LOG(ERR,
3401                                      "could not configure common threshold %d",
3402                                      ret);
3403                         return ret;
3404                 }
3405         }
3406
3407         ret = hns3_common_wl_config(hw, &pkt_buf);
3408         if (ret)
3409                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3410                              ret);
3411
3412         return ret;
3413 }
3414
3415 static int
3416 hns3_mac_init(struct hns3_hw *hw)
3417 {
3418         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3419         struct hns3_mac *mac = &hw->mac;
3420         struct hns3_pf *pf = &hns->pf;
3421         int ret;
3422
3423         pf->support_sfp_query = true;
3424         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3425         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3426         if (ret) {
3427                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3428                 return ret;
3429         }
3430
3431         mac->link_status = ETH_LINK_DOWN;
3432
3433         return hns3_config_mtu(hw, pf->mps);
3434 }
3435
3436 static int
3437 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3438 {
3439 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3440 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3441 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3442 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3443         int return_status;
3444
3445         if (cmdq_resp) {
3446                 PMD_INIT_LOG(ERR,
3447                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3448                              cmdq_resp);
3449                 return -EIO;
3450         }
3451
3452         switch (resp_code) {
3453         case HNS3_ETHERTYPE_SUCCESS_ADD:
3454         case HNS3_ETHERTYPE_ALREADY_ADD:
3455                 return_status = 0;
3456                 break;
3457         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3458                 PMD_INIT_LOG(ERR,
3459                              "add mac ethertype failed for manager table overflow.");
3460                 return_status = -EIO;
3461                 break;
3462         case HNS3_ETHERTYPE_KEY_CONFLICT:
3463                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3464                 return_status = -EIO;
3465                 break;
3466         default:
3467                 PMD_INIT_LOG(ERR,
3468                              "add mac ethertype failed for undefined, code=%d.",
3469                              resp_code);
3470                 return_status = -EIO;
3471         }
3472
3473         return return_status;
3474 }
3475
3476 static int
3477 hns3_add_mgr_tbl(struct hns3_hw *hw,
3478                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3479 {
3480         struct hns3_cmd_desc desc;
3481         uint8_t resp_code;
3482         uint16_t retval;
3483         int ret;
3484
3485         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3486         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3487
3488         ret = hns3_cmd_send(hw, &desc, 1);
3489         if (ret) {
3490                 PMD_INIT_LOG(ERR,
3491                              "add mac ethertype failed for cmd_send, ret =%d.",
3492                              ret);
3493                 return ret;
3494         }
3495
3496         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3497         retval = rte_le_to_cpu_16(desc.retval);
3498
3499         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3500 }
3501
3502 static void
3503 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3504                      int *table_item_num)
3505 {
3506         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3507
3508         /*
3509          * In current version, we add one item in management table as below:
3510          * 0x0180C200000E -- LLDP MC address
3511          */
3512         tbl = mgr_table;
3513         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3514         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3515         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3516         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3517         tbl->i_port_bitmap = 0x1;
3518         *table_item_num = 1;
3519 }
3520
3521 static int
3522 hns3_init_mgr_tbl(struct hns3_hw *hw)
3523 {
3524 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3525         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3526         int table_item_num;
3527         int ret;
3528         int i;
3529
3530         memset(mgr_table, 0, sizeof(mgr_table));
3531         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3532         for (i = 0; i < table_item_num; i++) {
3533                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3534                 if (ret) {
3535                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3536                                      ret);
3537                         return ret;
3538                 }
3539         }
3540
3541         return 0;
3542 }
3543
3544 static void
3545 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3546                         bool en_mc, bool en_bc, int vport_id)
3547 {
3548         if (!param)
3549                 return;
3550
3551         memset(param, 0, sizeof(struct hns3_promisc_param));
3552         if (en_uc)
3553                 param->enable = HNS3_PROMISC_EN_UC;
3554         if (en_mc)
3555                 param->enable |= HNS3_PROMISC_EN_MC;
3556         if (en_bc)
3557                 param->enable |= HNS3_PROMISC_EN_BC;
3558         param->vf_id = vport_id;
3559 }
3560
3561 static int
3562 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3563 {
3564         struct hns3_promisc_cfg_cmd *req;
3565         struct hns3_cmd_desc desc;
3566         int ret;
3567
3568         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3569
3570         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3571         req->vf_id = param->vf_id;
3572         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3573             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3574
3575         ret = hns3_cmd_send(hw, &desc, 1);
3576         if (ret)
3577                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3578
3579         return ret;
3580 }
3581
3582 static int
3583 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3584 {
3585         struct hns3_promisc_param param;
3586         bool en_bc_pmc = true;
3587         uint8_t vf_id;
3588         int ret;
3589
3590         /*
3591          * In current version VF is not supported when PF is driven by DPDK
3592          * driver, the PF-related vf_id is 0, just need to configure parameters
3593          * for vf_id 0.
3594          */
3595         vf_id = 0;
3596
3597         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3598         ret = hns3_cmd_set_promisc_mode(hw, &param);
3599         if (ret)
3600                 return ret;
3601
3602         return 0;
3603 }
3604
3605 static int
3606 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3607 {
3608         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3609         struct hns3_pf *pf = &hns->pf;
3610         struct hns3_promisc_param param;
3611         uint16_t func_id;
3612         int ret;
3613
3614         /* func_id 0 is denoted PF, the VFs start from 1 */
3615         for (func_id = 1; func_id < pf->func_num; func_id++) {
3616                 hns3_promisc_param_init(&param, false, false, false, func_id);
3617                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3618                 if (ret)
3619                         return ret;
3620         }
3621
3622         return 0;
3623 }
3624
3625 static int
3626 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3627 {
3628         struct hns3_adapter *hns = dev->data->dev_private;
3629         struct hns3_hw *hw = &hns->hw;
3630         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3631         int ret;
3632
3633         rte_spinlock_lock(&hw->lock);
3634         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3635         rte_spinlock_unlock(&hw->lock);
3636         if (ret)
3637                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3638
3639         return ret;
3640 }
3641
3642 static int
3643 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3644 {
3645         struct hns3_adapter *hns = dev->data->dev_private;
3646         struct hns3_hw *hw = &hns->hw;
3647         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3648         int ret;
3649
3650         /* If now in all_multicast mode, must remain in all_multicast mode. */
3651         rte_spinlock_lock(&hw->lock);
3652         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3653         rte_spinlock_unlock(&hw->lock);
3654         if (ret)
3655                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3656
3657         return ret;
3658 }
3659
3660 static int
3661 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3662 {
3663         struct hns3_adapter *hns = dev->data->dev_private;
3664         struct hns3_hw *hw = &hns->hw;
3665         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3666         int ret;
3667
3668         rte_spinlock_lock(&hw->lock);
3669         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3670         rte_spinlock_unlock(&hw->lock);
3671         if (ret)
3672                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3673
3674         return ret;
3675 }
3676
3677 static int
3678 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3679 {
3680         struct hns3_adapter *hns = dev->data->dev_private;
3681         struct hns3_hw *hw = &hns->hw;
3682         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3683         int ret;
3684
3685         /* If now in promiscuous mode, must remain in all_multicast mode. */
3686         if (dev->data->promiscuous == 1)
3687                 return 0;
3688
3689         rte_spinlock_lock(&hw->lock);
3690         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3691         rte_spinlock_unlock(&hw->lock);
3692         if (ret)
3693                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3694
3695         return ret;
3696 }
3697
3698 static int
3699 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3700 {
3701         struct hns3_hw *hw = &hns->hw;
3702         bool en_mc_pmc;
3703         bool en_uc_pmc;
3704
3705         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3706         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3707
3708         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3709 }
3710
3711 static int
3712 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3713 {
3714         struct hns3_sfp_speed_cmd *resp;
3715         struct hns3_cmd_desc desc;
3716         int ret;
3717
3718         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3719         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3720         ret = hns3_cmd_send(hw, &desc, 1);
3721         if (ret == -EOPNOTSUPP) {
3722                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3723                 return ret;
3724         } else if (ret) {
3725                 hns3_err(hw, "get sfp speed failed %d", ret);
3726                 return ret;
3727         }
3728
3729         *speed = resp->sfp_speed;
3730
3731         return 0;
3732 }
3733
3734 static uint8_t
3735 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3736 {
3737         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3738                 duplex = ETH_LINK_FULL_DUPLEX;
3739
3740         return duplex;
3741 }
3742
3743 static int
3744 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3745 {
3746         struct hns3_mac *mac = &hw->mac;
3747         int ret;
3748
3749         duplex = hns3_check_speed_dup(duplex, speed);
3750         if (mac->link_speed == speed && mac->link_duplex == duplex)
3751                 return 0;
3752
3753         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3754         if (ret)
3755                 return ret;
3756
3757         mac->link_speed = speed;
3758         mac->link_duplex = duplex;
3759
3760         return 0;
3761 }
3762
3763 static int
3764 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3765 {
3766         struct hns3_adapter *hns = eth_dev->data->dev_private;
3767         struct hns3_hw *hw = &hns->hw;
3768         struct hns3_pf *pf = &hns->pf;
3769         uint32_t speed;
3770         int ret;
3771
3772         /* If IMP do not support get SFP/qSFP speed, return directly */
3773         if (!pf->support_sfp_query)
3774                 return 0;
3775
3776         ret = hns3_get_sfp_speed(hw, &speed);
3777         if (ret == -EOPNOTSUPP) {
3778                 pf->support_sfp_query = false;
3779                 return ret;
3780         } else if (ret)
3781                 return ret;
3782
3783         if (speed == ETH_SPEED_NUM_NONE)
3784                 return 0; /* do nothing if no SFP */
3785
3786         /* Config full duplex for SFP */
3787         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3788 }
3789
3790 static int
3791 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3792 {
3793         struct hns3_config_mac_mode_cmd *req;
3794         struct hns3_cmd_desc desc;
3795         uint32_t loop_en = 0;
3796         uint8_t val = 0;
3797         int ret;
3798
3799         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3800
3801         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3802         if (enable)
3803                 val = 1;
3804         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3805         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3806         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3807         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3808         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3809         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3810         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3811         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3812         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3813         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3814         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3815         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3816         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3817         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3818         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3819
3820         ret = hns3_cmd_send(hw, &desc, 1);
3821         if (ret)
3822                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3823
3824         return ret;
3825 }
3826
3827 static int
3828 hns3_get_mac_link_status(struct hns3_hw *hw)
3829 {
3830         struct hns3_link_status_cmd *req;
3831         struct hns3_cmd_desc desc;
3832         int link_status;
3833         int ret;
3834
3835         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3836         ret = hns3_cmd_send(hw, &desc, 1);
3837         if (ret) {
3838                 hns3_err(hw, "get link status cmd failed %d", ret);
3839                 return ret;
3840         }
3841
3842         req = (struct hns3_link_status_cmd *)desc.data;
3843         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3844
3845         return !!link_status;
3846 }
3847
3848 void
3849 hns3_update_link_status(struct hns3_hw *hw)
3850 {
3851         int state;
3852
3853         state = hns3_get_mac_link_status(hw);
3854         if (state != hw->mac.link_status) {
3855                 hw->mac.link_status = state;
3856                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3857         }
3858 }
3859
3860 static void
3861 hns3_service_handler(void *param)
3862 {
3863         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3864         struct hns3_adapter *hns = eth_dev->data->dev_private;
3865         struct hns3_hw *hw = &hns->hw;
3866
3867         if (!hns3_is_reset_pending(hns)) {
3868                 hns3_update_speed_duplex(eth_dev);
3869                 hns3_update_link_status(hw);
3870         } else
3871                 hns3_warn(hw, "Cancel the query when reset is pending");
3872
3873         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3874 }
3875
3876 static int
3877 hns3_init_hardware(struct hns3_adapter *hns)
3878 {
3879         struct hns3_hw *hw = &hns->hw;
3880         int ret;
3881
3882         ret = hns3_map_tqp(hw);
3883         if (ret) {
3884                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3885                 return ret;
3886         }
3887
3888         ret = hns3_init_umv_space(hw);
3889         if (ret) {
3890                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3891                 return ret;
3892         }
3893
3894         ret = hns3_mac_init(hw);
3895         if (ret) {
3896                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3897                 goto err_mac_init;
3898         }
3899
3900         ret = hns3_init_mgr_tbl(hw);
3901         if (ret) {
3902                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3903                 goto err_mac_init;
3904         }
3905
3906         ret = hns3_set_promisc_mode(hw, false, false);
3907         if (ret) {
3908                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3909                 goto err_mac_init;
3910         }
3911
3912         ret = hns3_clear_all_vfs_promisc_mode(hw);
3913         if (ret) {
3914                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3915                              ret);
3916                 goto err_mac_init;
3917         }
3918
3919         ret = hns3_init_vlan_config(hns);
3920         if (ret) {
3921                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3922                 goto err_mac_init;
3923         }
3924
3925         ret = hns3_dcb_init(hw);
3926         if (ret) {
3927                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3928                 goto err_mac_init;
3929         }
3930
3931         ret = hns3_init_fd_config(hns);
3932         if (ret) {
3933                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3934                 goto err_mac_init;
3935         }
3936
3937         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3938         if (ret) {
3939                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3940                 goto err_mac_init;
3941         }
3942
3943         ret = hns3_config_gro(hw, false);
3944         if (ret) {
3945                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3946                 goto err_mac_init;
3947         }
3948         return 0;
3949
3950 err_mac_init:
3951         hns3_uninit_umv_space(hw);
3952         return ret;
3953 }
3954
3955 static int
3956 hns3_init_pf(struct rte_eth_dev *eth_dev)
3957 {
3958         struct rte_device *dev = eth_dev->device;
3959         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3960         struct hns3_adapter *hns = eth_dev->data->dev_private;
3961         struct hns3_hw *hw = &hns->hw;
3962         int ret;
3963
3964         PMD_INIT_FUNC_TRACE();
3965
3966         /* Get hardware io base address from pcie BAR2 IO space */
3967         hw->io_base = pci_dev->mem_resource[2].addr;
3968
3969         /* Firmware command queue initialize */
3970         ret = hns3_cmd_init_queue(hw);
3971         if (ret) {
3972                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3973                 goto err_cmd_init_queue;
3974         }
3975
3976         hns3_clear_all_event_cause(hw);
3977
3978         /* Firmware command initialize */
3979         ret = hns3_cmd_init(hw);
3980         if (ret) {
3981                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3982                 goto err_cmd_init;
3983         }
3984
3985         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3986                                          hns3_interrupt_handler,
3987                                          eth_dev);
3988         if (ret) {
3989                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3990                 goto err_intr_callback_register;
3991         }
3992
3993         /* Enable interrupt */
3994         rte_intr_enable(&pci_dev->intr_handle);
3995         hns3_pf_enable_irq0(hw);
3996
3997         /* Get configuration */
3998         ret = hns3_get_configuration(hw);
3999         if (ret) {
4000                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4001                 goto err_get_config;
4002         }
4003
4004         ret = hns3_init_hardware(hns);
4005         if (ret) {
4006                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4007                 goto err_get_config;
4008         }
4009
4010         /* Initialize flow director filter list & hash */
4011         ret = hns3_fdir_filter_init(hns);
4012         if (ret) {
4013                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4014                 goto err_hw_init;
4015         }
4016
4017         hns3_set_default_rss_args(hw);
4018
4019         ret = hns3_enable_hw_error_intr(hns, true);
4020         if (ret) {
4021                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4022                              ret);
4023                 goto err_fdir;
4024         }
4025
4026         return 0;
4027
4028 err_fdir:
4029         hns3_fdir_filter_uninit(hns);
4030 err_hw_init:
4031         hns3_uninit_umv_space(hw);
4032
4033 err_get_config:
4034         hns3_pf_disable_irq0(hw);
4035         rte_intr_disable(&pci_dev->intr_handle);
4036         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4037                              eth_dev);
4038
4039 err_intr_callback_register:
4040         hns3_cmd_uninit(hw);
4041
4042 err_cmd_init:
4043         hns3_cmd_destroy_queue(hw);
4044
4045 err_cmd_init_queue:
4046         hw->io_base = NULL;
4047
4048         return ret;
4049 }
4050
4051 static void
4052 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4053 {
4054         struct hns3_adapter *hns = eth_dev->data->dev_private;
4055         struct rte_device *dev = eth_dev->device;
4056         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4057         struct hns3_hw *hw = &hns->hw;
4058
4059         PMD_INIT_FUNC_TRACE();
4060
4061         hns3_enable_hw_error_intr(hns, false);
4062         hns3_rss_uninit(hns);
4063         hns3_fdir_filter_uninit(hns);
4064         hns3_uninit_umv_space(hw);
4065         hns3_pf_disable_irq0(hw);
4066         rte_intr_disable(&pci_dev->intr_handle);
4067         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4068                              eth_dev);
4069         hns3_cmd_uninit(hw);
4070         hns3_cmd_destroy_queue(hw);
4071         hw->io_base = NULL;
4072 }
4073
4074 static int
4075 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4076 {
4077         struct hns3_hw *hw = &hns->hw;
4078         int ret;
4079
4080         ret = hns3_dcb_cfg_update(hns);
4081         if (ret)
4082                 return ret;
4083
4084         /* Enable queues */
4085         ret = hns3_start_queues(hns, reset_queue);
4086         if (ret) {
4087                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4088                 return ret;
4089         }
4090
4091         /* Enable MAC */
4092         ret = hns3_cfg_mac_mode(hw, true);
4093         if (ret) {
4094                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4095                 goto err_config_mac_mode;
4096         }
4097         return 0;
4098
4099 err_config_mac_mode:
4100         hns3_stop_queues(hns, true);
4101         return ret;
4102 }
4103
4104 static int
4105 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4106 {
4107         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4109         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110         uint32_t intr_vector;
4111         uint8_t base = 0;
4112         uint8_t vec = 0;
4113         uint16_t q_id;
4114         int ret;
4115
4116         if (dev->data->dev_conf.intr_conf.rxq == 0)
4117                 return 0;
4118
4119         /* disable uio/vfio intr/eventfd mapping */
4120         rte_intr_disable(intr_handle);
4121
4122         /* check and configure queue intr-vector mapping */
4123         if (rte_intr_cap_multiple(intr_handle) ||
4124             !RTE_ETH_DEV_SRIOV(dev).active) {
4125                 intr_vector = hw->used_rx_queues;
4126                 /* creates event fd for each intr vector when MSIX is used */
4127                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4128                         return -EINVAL;
4129         }
4130         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4131                 intr_handle->intr_vec =
4132                         rte_zmalloc("intr_vec",
4133                                     hw->used_rx_queues * sizeof(int), 0);
4134                 if (intr_handle->intr_vec == NULL) {
4135                         hns3_err(hw, "Failed to allocate %d rx_queues"
4136                                      " intr_vec", hw->used_rx_queues);
4137                         ret = -ENOMEM;
4138                         goto alloc_intr_vec_error;
4139                 }
4140         }
4141
4142         if (rte_intr_allow_others(intr_handle)) {
4143                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4144                 base = RTE_INTR_VEC_RXTX_OFFSET;
4145         }
4146         if (rte_intr_dp_is_en(intr_handle)) {
4147                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4148                         ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
4149                         if (ret)
4150                                 goto bind_vector_error;
4151                         intr_handle->intr_vec[q_id] = vec;
4152                         if (vec < base + intr_handle->nb_efd - 1)
4153                                 vec++;
4154                 }
4155         }
4156         rte_intr_enable(intr_handle);
4157         return 0;
4158
4159 bind_vector_error:
4160         rte_intr_efd_disable(intr_handle);
4161         if (intr_handle->intr_vec) {
4162                 free(intr_handle->intr_vec);
4163                 intr_handle->intr_vec = NULL;
4164         }
4165         return ret;
4166 alloc_intr_vec_error:
4167         rte_intr_efd_disable(intr_handle);
4168         return ret;
4169 }
4170
4171 static int
4172 hns3_dev_start(struct rte_eth_dev *dev)
4173 {
4174         struct hns3_adapter *hns = dev->data->dev_private;
4175         struct hns3_hw *hw = &hns->hw;
4176         int ret;
4177
4178         PMD_INIT_FUNC_TRACE();
4179         if (rte_atomic16_read(&hw->reset.resetting))
4180                 return -EBUSY;
4181
4182         rte_spinlock_lock(&hw->lock);
4183         hw->adapter_state = HNS3_NIC_STARTING;
4184
4185         ret = hns3_do_start(hns, true);
4186         if (ret) {
4187                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4188                 rte_spinlock_unlock(&hw->lock);
4189                 return ret;
4190         }
4191
4192         hw->adapter_state = HNS3_NIC_STARTED;
4193         rte_spinlock_unlock(&hw->lock);
4194
4195         ret = hns3_map_rx_interrupt(dev);
4196         if (ret)
4197                 return ret;
4198         hns3_set_rxtx_function(dev);
4199         hns3_mp_req_start_rxtx(dev);
4200         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4201
4202         hns3_info(hw, "hns3 dev start successful!");
4203         return 0;
4204 }
4205
4206 static int
4207 hns3_do_stop(struct hns3_adapter *hns)
4208 {
4209         struct hns3_hw *hw = &hns->hw;
4210         bool reset_queue;
4211         int ret;
4212
4213         ret = hns3_cfg_mac_mode(hw, false);
4214         if (ret)
4215                 return ret;
4216         hw->mac.link_status = ETH_LINK_DOWN;
4217
4218         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4219                 hns3_configure_all_mac_addr(hns, true);
4220                 reset_queue = true;
4221         } else
4222                 reset_queue = false;
4223         hw->mac.default_addr_setted = false;
4224         return hns3_stop_queues(hns, reset_queue);
4225 }
4226
4227 static void
4228 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4229 {
4230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4231         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4232         struct hns3_adapter *hns = dev->data->dev_private;
4233         struct hns3_hw *hw = &hns->hw;
4234         uint8_t base = 0;
4235         uint8_t vec = 0;
4236         uint16_t q_id;
4237
4238         if (dev->data->dev_conf.intr_conf.rxq == 0)
4239                 return;
4240
4241         /* unmap the ring with vector */
4242         if (rte_intr_allow_others(intr_handle)) {
4243                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4244                 base = RTE_INTR_VEC_RXTX_OFFSET;
4245         }
4246         if (rte_intr_dp_is_en(intr_handle)) {
4247                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4248                         (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
4249                         if (vec < base + intr_handle->nb_efd - 1)
4250                                 vec++;
4251                 }
4252         }
4253         /* Clean datapath event and queue/vec mapping */
4254         rte_intr_efd_disable(intr_handle);
4255         if (intr_handle->intr_vec) {
4256                 rte_free(intr_handle->intr_vec);
4257                 intr_handle->intr_vec = NULL;
4258         }
4259 }
4260
4261 static void
4262 hns3_dev_stop(struct rte_eth_dev *dev)
4263 {
4264         struct hns3_adapter *hns = dev->data->dev_private;
4265         struct hns3_hw *hw = &hns->hw;
4266
4267         PMD_INIT_FUNC_TRACE();
4268
4269         hw->adapter_state = HNS3_NIC_STOPPING;
4270         hns3_set_rxtx_function(dev);
4271         rte_wmb();
4272         /* Disable datapath on secondary process. */
4273         hns3_mp_req_stop_rxtx(dev);
4274         /* Prevent crashes when queues are still in use. */
4275         rte_delay_ms(hw->tqps_num);
4276
4277         rte_spinlock_lock(&hw->lock);
4278         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4279                 hns3_do_stop(hns);
4280                 hns3_dev_release_mbufs(hns);
4281                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4282         }
4283         rte_eal_alarm_cancel(hns3_service_handler, dev);
4284         rte_spinlock_unlock(&hw->lock);
4285         hns3_unmap_rx_interrupt(dev);
4286 }
4287
4288 static void
4289 hns3_dev_close(struct rte_eth_dev *eth_dev)
4290 {
4291         struct hns3_adapter *hns = eth_dev->data->dev_private;
4292         struct hns3_hw *hw = &hns->hw;
4293
4294         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4295                 rte_free(eth_dev->process_private);
4296                 eth_dev->process_private = NULL;
4297                 return;
4298         }
4299
4300         if (hw->adapter_state == HNS3_NIC_STARTED)
4301                 hns3_dev_stop(eth_dev);
4302
4303         hw->adapter_state = HNS3_NIC_CLOSING;
4304         hns3_reset_abort(hns);
4305         hw->adapter_state = HNS3_NIC_CLOSED;
4306
4307         hns3_configure_all_mc_mac_addr(hns, true);
4308         hns3_remove_all_vlan_table(hns);
4309         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4310         hns3_uninit_pf(eth_dev);
4311         hns3_free_all_queues(eth_dev);
4312         rte_free(hw->reset.wait_data);
4313         rte_free(eth_dev->process_private);
4314         eth_dev->process_private = NULL;
4315         hns3_mp_uninit_primary();
4316         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4317 }
4318
4319 static int
4320 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4321 {
4322         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4323         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4324
4325         fc_conf->pause_time = pf->pause_time;
4326
4327         /* return fc current mode */
4328         switch (hw->current_mode) {
4329         case HNS3_FC_FULL:
4330                 fc_conf->mode = RTE_FC_FULL;
4331                 break;
4332         case HNS3_FC_TX_PAUSE:
4333                 fc_conf->mode = RTE_FC_TX_PAUSE;
4334                 break;
4335         case HNS3_FC_RX_PAUSE:
4336                 fc_conf->mode = RTE_FC_RX_PAUSE;
4337                 break;
4338         case HNS3_FC_NONE:
4339         default:
4340                 fc_conf->mode = RTE_FC_NONE;
4341                 break;
4342         }
4343
4344         return 0;
4345 }
4346
4347 static void
4348 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4349 {
4350         switch (mode) {
4351         case RTE_FC_NONE:
4352                 hw->requested_mode = HNS3_FC_NONE;
4353                 break;
4354         case RTE_FC_RX_PAUSE:
4355                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4356                 break;
4357         case RTE_FC_TX_PAUSE:
4358                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4359                 break;
4360         case RTE_FC_FULL:
4361                 hw->requested_mode = HNS3_FC_FULL;
4362                 break;
4363         default:
4364                 hw->requested_mode = HNS3_FC_NONE;
4365                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4366                           "configured to RTE_FC_NONE", mode);
4367                 break;
4368         }
4369 }
4370
4371 static int
4372 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4373 {
4374         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4375         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4376         int ret;
4377
4378         if (fc_conf->high_water || fc_conf->low_water ||
4379             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4380                 hns3_err(hw, "Unsupported flow control settings specified, "
4381                          "high_water(%u), low_water(%u), send_xon(%u) and "
4382                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4383                          fc_conf->high_water, fc_conf->low_water,
4384                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4385                 return -EINVAL;
4386         }
4387         if (fc_conf->autoneg) {
4388                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4389                 return -EINVAL;
4390         }
4391         if (!fc_conf->pause_time) {
4392                 hns3_err(hw, "Invalid pause time %d setting.",
4393                          fc_conf->pause_time);
4394                 return -EINVAL;
4395         }
4396
4397         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4398             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4399                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4400                          "current_fc_status = %d", hw->current_fc_status);
4401                 return -EOPNOTSUPP;
4402         }
4403
4404         hns3_get_fc_mode(hw, fc_conf->mode);
4405         if (hw->requested_mode == hw->current_mode &&
4406             pf->pause_time == fc_conf->pause_time)
4407                 return 0;
4408
4409         rte_spinlock_lock(&hw->lock);
4410         ret = hns3_fc_enable(dev, fc_conf);
4411         rte_spinlock_unlock(&hw->lock);
4412
4413         return ret;
4414 }
4415
4416 static int
4417 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4418                             struct rte_eth_pfc_conf *pfc_conf)
4419 {
4420         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4421         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4422         uint8_t priority;
4423         int ret;
4424
4425         if (!hns3_dev_dcb_supported(hw)) {
4426                 hns3_err(hw, "This port does not support dcb configurations.");
4427                 return -EOPNOTSUPP;
4428         }
4429
4430         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4431             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4432                 hns3_err(hw, "Unsupported flow control settings specified, "
4433                          "high_water(%u), low_water(%u), send_xon(%u) and "
4434                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4435                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4436                          pfc_conf->fc.send_xon,
4437                          pfc_conf->fc.mac_ctrl_frame_fwd);
4438                 return -EINVAL;
4439         }
4440         if (pfc_conf->fc.autoneg) {
4441                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4442                 return -EINVAL;
4443         }
4444         if (pfc_conf->fc.pause_time == 0) {
4445                 hns3_err(hw, "Invalid pause time %d setting.",
4446                          pfc_conf->fc.pause_time);
4447                 return -EINVAL;
4448         }
4449
4450         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4451             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4452                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4453                              "current_fc_status = %d", hw->current_fc_status);
4454                 return -EOPNOTSUPP;
4455         }
4456
4457         priority = pfc_conf->priority;
4458         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4459         if (hw->dcb_info.pfc_en & BIT(priority) &&
4460             hw->requested_mode == hw->current_mode &&
4461             pfc_conf->fc.pause_time == pf->pause_time)
4462                 return 0;
4463
4464         rte_spinlock_lock(&hw->lock);
4465         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4466         rte_spinlock_unlock(&hw->lock);
4467
4468         return ret;
4469 }
4470
4471 static int
4472 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4473 {
4474         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4476         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4477         int i;
4478
4479         rte_spinlock_lock(&hw->lock);
4480         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4481                 dcb_info->nb_tcs = pf->local_max_tc;
4482         else
4483                 dcb_info->nb_tcs = 1;
4484
4485         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4486                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4487         for (i = 0; i < dcb_info->nb_tcs; i++)
4488                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4489
4490         for (i = 0; i < hw->num_tc; i++) {
4491                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4492                 dcb_info->tc_queue.tc_txq[0][i].base =
4493                                                 hw->tc_queue[i].tqp_offset;
4494                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4495                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4496                                                 hw->tc_queue[i].tqp_count;
4497         }
4498         rte_spinlock_unlock(&hw->lock);
4499
4500         return 0;
4501 }
4502
4503 static int
4504 hns3_reinit_dev(struct hns3_adapter *hns)
4505 {
4506         struct hns3_hw *hw = &hns->hw;
4507         int ret;
4508
4509         ret = hns3_cmd_init(hw);
4510         if (ret) {
4511                 hns3_err(hw, "Failed to init cmd: %d", ret);
4512                 return ret;
4513         }
4514
4515         ret = hns3_reset_all_queues(hns);
4516         if (ret) {
4517                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4518                 goto err_init;
4519         }
4520
4521         ret = hns3_init_hardware(hns);
4522         if (ret) {
4523                 hns3_err(hw, "Failed to init hardware: %d", ret);
4524                 goto err_init;
4525         }
4526
4527         ret = hns3_enable_hw_error_intr(hns, true);
4528         if (ret) {
4529                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4530                              ret);
4531                 goto err_mac_init;
4532         }
4533         hns3_info(hw, "Reset done, driver initialization finished.");
4534
4535         return 0;
4536
4537 err_mac_init:
4538         hns3_uninit_umv_space(hw);
4539 err_init:
4540         hns3_cmd_uninit(hw);
4541
4542         return ret;
4543 }
4544
4545 static bool
4546 is_pf_reset_done(struct hns3_hw *hw)
4547 {
4548         uint32_t val, reg, reg_bit;
4549
4550         switch (hw->reset.level) {
4551         case HNS3_IMP_RESET:
4552                 reg = HNS3_GLOBAL_RESET_REG;
4553                 reg_bit = HNS3_IMP_RESET_BIT;
4554                 break;
4555         case HNS3_GLOBAL_RESET:
4556                 reg = HNS3_GLOBAL_RESET_REG;
4557                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4558                 break;
4559         case HNS3_FUNC_RESET:
4560                 reg = HNS3_FUN_RST_ING;
4561                 reg_bit = HNS3_FUN_RST_ING_B;
4562                 break;
4563         case HNS3_FLR_RESET:
4564         default:
4565                 hns3_err(hw, "Wait for unsupported reset level: %d",
4566                          hw->reset.level);
4567                 return true;
4568         }
4569         val = hns3_read_dev(hw, reg);
4570         if (hns3_get_bit(val, reg_bit))
4571                 return false;
4572         else
4573                 return true;
4574 }
4575
4576 bool
4577 hns3_is_reset_pending(struct hns3_adapter *hns)
4578 {
4579         struct hns3_hw *hw = &hns->hw;
4580         enum hns3_reset_level reset;
4581
4582         hns3_check_event_cause(hns, NULL);
4583         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4584         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4585                 hns3_warn(hw, "High level reset %d is pending", reset);
4586                 return true;
4587         }
4588         reset = hns3_get_reset_level(hns, &hw->reset.request);
4589         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4590                 hns3_warn(hw, "High level reset %d is request", reset);
4591                 return true;
4592         }
4593         return false;
4594 }
4595
4596 static int
4597 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4598 {
4599         struct hns3_hw *hw = &hns->hw;
4600         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4601         struct timeval tv;
4602
4603         if (wait_data->result == HNS3_WAIT_SUCCESS)
4604                 return 0;
4605         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4606                 gettimeofday(&tv, NULL);
4607                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4608                           tv.tv_sec, tv.tv_usec);
4609                 return -ETIME;
4610         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4611                 return -EAGAIN;
4612
4613         wait_data->hns = hns;
4614         wait_data->check_completion = is_pf_reset_done;
4615         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4616                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4617         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4618         wait_data->count = HNS3_RESET_WAIT_CNT;
4619         wait_data->result = HNS3_WAIT_REQUEST;
4620         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4621         return -EAGAIN;
4622 }
4623
4624 static int
4625 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4626 {
4627         struct hns3_cmd_desc desc;
4628         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4629
4630         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4631         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4632         req->fun_reset_vfid = func_id;
4633
4634         return hns3_cmd_send(hw, &desc, 1);
4635 }
4636
4637 static int
4638 hns3_imp_reset_cmd(struct hns3_hw *hw)
4639 {
4640         struct hns3_cmd_desc desc;
4641
4642         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4643         desc.data[0] = 0xeedd;
4644
4645         return hns3_cmd_send(hw, &desc, 1);
4646 }
4647
4648 static void
4649 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4650 {
4651         struct hns3_hw *hw = &hns->hw;
4652         struct timeval tv;
4653         uint32_t val;
4654
4655         gettimeofday(&tv, NULL);
4656         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4657             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4658                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4659                           tv.tv_sec, tv.tv_usec);
4660                 return;
4661         }
4662
4663         switch (reset_level) {
4664         case HNS3_IMP_RESET:
4665                 hns3_imp_reset_cmd(hw);
4666                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4667                           tv.tv_sec, tv.tv_usec);
4668                 break;
4669         case HNS3_GLOBAL_RESET:
4670                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4671                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4672                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4673                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4674                           tv.tv_sec, tv.tv_usec);
4675                 break;
4676         case HNS3_FUNC_RESET:
4677                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4678                           tv.tv_sec, tv.tv_usec);
4679                 /* schedule again to check later */
4680                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4681                 hns3_schedule_reset(hns);
4682                 break;
4683         default:
4684                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4685                 return;
4686         }
4687         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4688 }
4689
4690 static enum hns3_reset_level
4691 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4692 {
4693         struct hns3_hw *hw = &hns->hw;
4694         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4695
4696         /* Return the highest priority reset level amongst all */
4697         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4698                 reset_level = HNS3_IMP_RESET;
4699         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4700                 reset_level = HNS3_GLOBAL_RESET;
4701         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4702                 reset_level = HNS3_FUNC_RESET;
4703         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4704                 reset_level = HNS3_FLR_RESET;
4705
4706         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4707                 return HNS3_NONE_RESET;
4708
4709         return reset_level;
4710 }
4711
4712 static int
4713 hns3_prepare_reset(struct hns3_adapter *hns)
4714 {
4715         struct hns3_hw *hw = &hns->hw;
4716         uint32_t reg_val;
4717         int ret;
4718
4719         switch (hw->reset.level) {
4720         case HNS3_FUNC_RESET:
4721                 ret = hns3_func_reset_cmd(hw, 0);
4722                 if (ret)
4723                         return ret;
4724
4725                 /*
4726                  * After performaning pf reset, it is not necessary to do the
4727                  * mailbox handling or send any command to firmware, because
4728                  * any mailbox handling or command to firmware is only valid
4729                  * after hns3_cmd_init is called.
4730                  */
4731                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4732                 hw->reset.stats.request_cnt++;
4733                 break;
4734         case HNS3_IMP_RESET:
4735                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4736                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4737                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4738                 break;
4739         default:
4740                 break;
4741         }
4742         return 0;
4743 }
4744
4745 static int
4746 hns3_set_rst_done(struct hns3_hw *hw)
4747 {
4748         struct hns3_pf_rst_done_cmd *req;
4749         struct hns3_cmd_desc desc;
4750
4751         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4752         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4753         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4754         return hns3_cmd_send(hw, &desc, 1);
4755 }
4756
4757 static int
4758 hns3_stop_service(struct hns3_adapter *hns)
4759 {
4760         struct hns3_hw *hw = &hns->hw;
4761         struct rte_eth_dev *eth_dev;
4762
4763         eth_dev = &rte_eth_devices[hw->data->port_id];
4764         if (hw->adapter_state == HNS3_NIC_STARTED)
4765                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4766         hw->mac.link_status = ETH_LINK_DOWN;
4767
4768         hns3_set_rxtx_function(eth_dev);
4769         rte_wmb();
4770         /* Disable datapath on secondary process. */
4771         hns3_mp_req_stop_rxtx(eth_dev);
4772         rte_delay_ms(hw->tqps_num);
4773
4774         rte_spinlock_lock(&hw->lock);
4775         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4776             hw->adapter_state == HNS3_NIC_STOPPING) {
4777                 hns3_do_stop(hns);
4778                 hw->reset.mbuf_deferred_free = true;
4779         } else
4780                 hw->reset.mbuf_deferred_free = false;
4781
4782         /*
4783          * It is cumbersome for hardware to pick-and-choose entries for deletion
4784          * from table space. Hence, for function reset software intervention is
4785          * required to delete the entries
4786          */
4787         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4788                 hns3_configure_all_mc_mac_addr(hns, true);
4789         rte_spinlock_unlock(&hw->lock);
4790
4791         return 0;
4792 }
4793
4794 static int
4795 hns3_start_service(struct hns3_adapter *hns)
4796 {
4797         struct hns3_hw *hw = &hns->hw;
4798         struct rte_eth_dev *eth_dev;
4799
4800         if (hw->reset.level == HNS3_IMP_RESET ||
4801             hw->reset.level == HNS3_GLOBAL_RESET)
4802                 hns3_set_rst_done(hw);
4803         eth_dev = &rte_eth_devices[hw->data->port_id];
4804         hns3_set_rxtx_function(eth_dev);
4805         hns3_mp_req_start_rxtx(eth_dev);
4806         if (hw->adapter_state == HNS3_NIC_STARTED)
4807                 hns3_service_handler(eth_dev);
4808
4809         return 0;
4810 }
4811
4812 static int
4813 hns3_restore_conf(struct hns3_adapter *hns)
4814 {
4815         struct hns3_hw *hw = &hns->hw;
4816         int ret;
4817
4818         ret = hns3_configure_all_mac_addr(hns, false);
4819         if (ret)
4820                 return ret;
4821
4822         ret = hns3_configure_all_mc_mac_addr(hns, false);
4823         if (ret)
4824                 goto err_mc_mac;
4825
4826         ret = hns3_dev_promisc_restore(hns);
4827         if (ret)
4828                 goto err_promisc;
4829
4830         ret = hns3_restore_vlan_table(hns);
4831         if (ret)
4832                 goto err_promisc;
4833
4834         ret = hns3_restore_vlan_conf(hns);
4835         if (ret)
4836                 goto err_promisc;
4837
4838         ret = hns3_restore_all_fdir_filter(hns);
4839         if (ret)
4840                 goto err_promisc;
4841
4842         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4843                 ret = hns3_do_start(hns, false);
4844                 if (ret)
4845                         goto err_promisc;
4846                 hns3_info(hw, "hns3 dev restart successful!");
4847         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4848                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4849         return 0;
4850
4851 err_promisc:
4852         hns3_configure_all_mc_mac_addr(hns, true);
4853 err_mc_mac:
4854         hns3_configure_all_mac_addr(hns, true);
4855         return ret;
4856 }
4857
4858 static void
4859 hns3_reset_service(void *param)
4860 {
4861         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4862         struct hns3_hw *hw = &hns->hw;
4863         enum hns3_reset_level reset_level;
4864         struct timeval tv_delta;
4865         struct timeval tv_start;
4866         struct timeval tv;
4867         uint64_t msec;
4868         int ret;
4869
4870         /*
4871          * The interrupt is not triggered within the delay time.
4872          * The interrupt may have been lost. It is necessary to handle
4873          * the interrupt to recover from the error.
4874          */
4875         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4876                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4877                 hns3_err(hw, "Handling interrupts in delayed tasks");
4878                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4879                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4880                 if (reset_level == HNS3_NONE_RESET) {
4881                         hns3_err(hw, "No reset level is set, try IMP reset");
4882                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4883                 }
4884         }
4885         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4886
4887         /*
4888          * Check if there is any ongoing reset in the hardware. This status can
4889          * be checked from reset_pending. If there is then, we need to wait for
4890          * hardware to complete reset.
4891          *    a. If we are able to figure out in reasonable time that hardware
4892          *       has fully resetted then, we can proceed with driver, client
4893          *       reset.
4894          *    b. else, we can come back later to check this status so re-sched
4895          *       now.
4896          */
4897         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4898         if (reset_level != HNS3_NONE_RESET) {
4899                 gettimeofday(&tv_start, NULL);
4900                 ret = hns3_reset_process(hns, reset_level);
4901                 gettimeofday(&tv, NULL);
4902                 timersub(&tv, &tv_start, &tv_delta);
4903                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4904                        tv_delta.tv_usec / USEC_PER_MSEC;
4905                 if (msec > HNS3_RESET_PROCESS_MS)
4906                         hns3_err(hw, "%d handle long time delta %" PRIx64
4907                                      " ms time=%ld.%.6ld",
4908                                  hw->reset.level, msec,
4909                                  tv.tv_sec, tv.tv_usec);
4910                 if (ret == -EAGAIN)
4911                         return;
4912         }
4913
4914         /* Check if we got any *new* reset requests to be honored */
4915         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4916         if (reset_level != HNS3_NONE_RESET)
4917                 hns3_msix_process(hns, reset_level);
4918 }
4919
4920 static const struct eth_dev_ops hns3_eth_dev_ops = {
4921         .dev_start          = hns3_dev_start,
4922         .dev_stop           = hns3_dev_stop,
4923         .dev_close          = hns3_dev_close,
4924         .promiscuous_enable = hns3_dev_promiscuous_enable,
4925         .promiscuous_disable = hns3_dev_promiscuous_disable,
4926         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4927         .allmulticast_disable = hns3_dev_allmulticast_disable,
4928         .mtu_set            = hns3_dev_mtu_set,
4929         .stats_get          = hns3_stats_get,
4930         .stats_reset        = hns3_stats_reset,
4931         .xstats_get         = hns3_dev_xstats_get,
4932         .xstats_get_names   = hns3_dev_xstats_get_names,
4933         .xstats_reset       = hns3_dev_xstats_reset,
4934         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4935         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4936         .dev_infos_get          = hns3_dev_infos_get,
4937         .fw_version_get         = hns3_fw_version_get,
4938         .rx_queue_setup         = hns3_rx_queue_setup,
4939         .tx_queue_setup         = hns3_tx_queue_setup,
4940         .rx_queue_release       = hns3_dev_rx_queue_release,
4941         .tx_queue_release       = hns3_dev_tx_queue_release,
4942         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
4943         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
4944         .dev_configure          = hns3_dev_configure,
4945         .flow_ctrl_get          = hns3_flow_ctrl_get,
4946         .flow_ctrl_set          = hns3_flow_ctrl_set,
4947         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4948         .mac_addr_add           = hns3_add_mac_addr,
4949         .mac_addr_remove        = hns3_remove_mac_addr,
4950         .mac_addr_set           = hns3_set_default_mac_addr,
4951         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4952         .link_update            = hns3_dev_link_update,
4953         .rss_hash_update        = hns3_dev_rss_hash_update,
4954         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4955         .reta_update            = hns3_dev_rss_reta_update,
4956         .reta_query             = hns3_dev_rss_reta_query,
4957         .filter_ctrl            = hns3_dev_filter_ctrl,
4958         .vlan_filter_set        = hns3_vlan_filter_set,
4959         .vlan_tpid_set          = hns3_vlan_tpid_set,
4960         .vlan_offload_set       = hns3_vlan_offload_set,
4961         .vlan_pvid_set          = hns3_vlan_pvid_set,
4962         .get_reg                = hns3_get_regs,
4963         .get_dcb_info           = hns3_get_dcb_info,
4964         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4965 };
4966
4967 static const struct hns3_reset_ops hns3_reset_ops = {
4968         .reset_service       = hns3_reset_service,
4969         .stop_service        = hns3_stop_service,
4970         .prepare_reset       = hns3_prepare_reset,
4971         .wait_hardware_ready = hns3_wait_hardware_ready,
4972         .reinit_dev          = hns3_reinit_dev,
4973         .restore_conf        = hns3_restore_conf,
4974         .start_service       = hns3_start_service,
4975 };
4976
4977 static int
4978 hns3_dev_init(struct rte_eth_dev *eth_dev)
4979 {
4980         struct rte_device *dev = eth_dev->device;
4981         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4982         struct hns3_adapter *hns = eth_dev->data->dev_private;
4983         struct hns3_hw *hw = &hns->hw;
4984         uint16_t device_id = pci_dev->id.device_id;
4985         int ret;
4986
4987         PMD_INIT_FUNC_TRACE();
4988         eth_dev->process_private = (struct hns3_process_private *)
4989             rte_zmalloc_socket("hns3_filter_list",
4990                                sizeof(struct hns3_process_private),
4991                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4992         if (eth_dev->process_private == NULL) {
4993                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4994                 return -ENOMEM;
4995         }
4996         /* initialize flow filter lists */
4997         hns3_filterlist_init(eth_dev);
4998
4999         hns3_set_rxtx_function(eth_dev);
5000         eth_dev->dev_ops = &hns3_eth_dev_ops;
5001         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5002                 hns3_mp_init_secondary();
5003                 hw->secondary_cnt++;
5004                 return 0;
5005         }
5006
5007         hns3_mp_init_primary();
5008         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5009
5010         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5011             device_id == HNS3_DEV_ID_50GE_RDMA ||
5012             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5013                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5014
5015         hns->is_vf = false;
5016         hw->data = eth_dev->data;
5017
5018         /*
5019          * Set default max packet size according to the mtu
5020          * default vale in DPDK frame.
5021          */
5022         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5023
5024         ret = hns3_reset_init(hw);
5025         if (ret)
5026                 goto err_init_reset;
5027         hw->reset.ops = &hns3_reset_ops;
5028
5029         ret = hns3_init_pf(eth_dev);
5030         if (ret) {
5031                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5032                 goto err_init_pf;
5033         }
5034
5035         /* Allocate memory for storing MAC addresses */
5036         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5037                                                sizeof(struct rte_ether_addr) *
5038                                                HNS3_UC_MACADDR_NUM, 0);
5039         if (eth_dev->data->mac_addrs == NULL) {
5040                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5041                              "to store MAC addresses",
5042                              sizeof(struct rte_ether_addr) *
5043                              HNS3_UC_MACADDR_NUM);
5044                 ret = -ENOMEM;
5045                 goto err_rte_zmalloc;
5046         }
5047
5048         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5049                             &eth_dev->data->mac_addrs[0]);
5050
5051         hw->adapter_state = HNS3_NIC_INITIALIZED;
5052         /*
5053          * Pass the information to the rte_eth_dev_close() that it should also
5054          * release the private port resources.
5055          */
5056         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5057
5058         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5059                 hns3_err(hw, "Reschedule reset service after dev_init");
5060                 hns3_schedule_reset(hns);
5061         } else {
5062                 /* IMP will wait ready flag before reset */
5063                 hns3_notify_reset_ready(hw, false);
5064         }
5065
5066         hns3_info(hw, "hns3 dev initialization successful!");
5067         return 0;
5068
5069 err_rte_zmalloc:
5070         hns3_uninit_pf(eth_dev);
5071
5072 err_init_pf:
5073         rte_free(hw->reset.wait_data);
5074 err_init_reset:
5075         eth_dev->dev_ops = NULL;
5076         eth_dev->rx_pkt_burst = NULL;
5077         eth_dev->tx_pkt_burst = NULL;
5078         eth_dev->tx_pkt_prepare = NULL;
5079         rte_free(eth_dev->process_private);
5080         eth_dev->process_private = NULL;
5081         return ret;
5082 }
5083
5084 static int
5085 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5086 {
5087         struct hns3_adapter *hns = eth_dev->data->dev_private;
5088         struct hns3_hw *hw = &hns->hw;
5089
5090         PMD_INIT_FUNC_TRACE();
5091
5092         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5093                 return -EPERM;
5094
5095         eth_dev->dev_ops = NULL;
5096         eth_dev->rx_pkt_burst = NULL;
5097         eth_dev->tx_pkt_burst = NULL;
5098         eth_dev->tx_pkt_prepare = NULL;
5099         if (hw->adapter_state < HNS3_NIC_CLOSING)
5100                 hns3_dev_close(eth_dev);
5101
5102         hw->adapter_state = HNS3_NIC_REMOVED;
5103         return 0;
5104 }
5105
5106 static int
5107 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5108                    struct rte_pci_device *pci_dev)
5109 {
5110         return rte_eth_dev_pci_generic_probe(pci_dev,
5111                                              sizeof(struct hns3_adapter),
5112                                              hns3_dev_init);
5113 }
5114
5115 static int
5116 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5117 {
5118         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5119 }
5120
5121 static const struct rte_pci_id pci_id_hns3_map[] = {
5122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5127         { .vendor_id = 0, /* sentinel */ },
5128 };
5129
5130 static struct rte_pci_driver rte_hns3_pmd = {
5131         .id_table = pci_id_hns3_map,
5132         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5133         .probe = eth_hns3_pci_probe,
5134         .remove = eth_hns3_pci_remove,
5135 };
5136
5137 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5138 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5139 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5140
5141 RTE_INIT(hns3_init_log)
5142 {
5143         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5144         if (hns3_logtype_init >= 0)
5145                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5146         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5147         if (hns3_logtype_driver >= 0)
5148                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5149 }