drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, the PF-related vf_id is 0, just need to configure parameters
 478          * for vport_id 0.
 479          */
 480         vport_id = 0;
 481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 483         req->vf_bitmap[req->vf_offset] = bitmap;
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 488         return ret;
 489 }
 490
 491 static void
 492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_rx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 497 }
 498
 499 static void
 500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 501                            struct hns3_tx_vtag_cfg *vcfg)
 502 {
 503         struct hns3_pf *pf = &hns->pf;
 504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 505 }
 506
 507 static int
 508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 509 {
 510         struct hns3_rx_vtag_cfg rxvlan_cfg;
 511         struct hns3_pf *pf = &hns->pf;
 512         struct hns3_hw *hw = &hns->hw;
 513         int ret;
 514
 515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 516                 rxvlan_cfg.strip_tag1_en = false;
 517                 rxvlan_cfg.strip_tag2_en = enable;
 518         } else {
 519                 rxvlan_cfg.strip_tag1_en = enable;
 520                 rxvlan_cfg.strip_tag2_en = true;
 521         }
 522
 523         rxvlan_cfg.vlan1_vlan_prionly = false;
 524         rxvlan_cfg.vlan2_vlan_prionly = false;
 525         rxvlan_cfg.rx_vlan_offload_en = enable;
 526
 527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 528         if (ret) {
 529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 530                 return ret;
 531         }
 532
 533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 541 {
 542         struct hns3_vlan_filter_ctrl_cmd *req;
 543         struct hns3_cmd_desc desc;
 544         int ret;
 545
 546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 547
 548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 549         req->vlan_type = vlan_type;
 550         req->vlan_fe = filter_en ? fe_type : 0;
 551         req->vf_id = vf_id;
 552
 553         ret = hns3_cmd_send(hw, &desc, 1);
 554         if (ret)
 555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 556
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_vlan_filter_init(struct hns3_adapter *hns)
 562 {
 563         struct hns3_hw *hw = &hns->hw;
 564         int ret;
 565
 566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 567                                         HNS3_FILTER_FE_EGRESS, false, 0);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false, 0);
 575         if (ret)
 576                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 577
 578         return ret;
 579 }
 580
 581 static int
 582 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 583 {
 584         struct hns3_hw *hw = &hns->hw;
 585         int ret;
 586
 587         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 588                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 589         if (ret)
 590                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 591                          enable ? "enable" : "disable", ret);
 592
 593         return ret;
 594 }
 595
 596 static int
 597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 598 {
 599         struct hns3_adapter *hns = dev->data->dev_private;
 600         struct hns3_hw *hw = &hns->hw;
 601         struct rte_eth_rxmode *rxmode;
 602         unsigned int tmp_mask;
 603         bool enable;
 604         int ret = 0;
 605
 606         rte_spinlock_lock(&hw->lock);
 607         rxmode = &dev->data->dev_conf.rxmode;
 608         tmp_mask = (unsigned int)mask;
 609         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 610                 /* Enable or disable VLAN filter */
 611                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 612                     true : false;
 613
 614                 ret = hns3_enable_vlan_filter(hns, enable);
 615                 if (ret) {
 616                         rte_spinlock_unlock(&hw->lock);
 617                         hns3_err(hw, "failed to %s rx filter, ret = %d",
 618                                  enable ? "enable" : "disable", ret);
 619                         return ret;
 620                 }
 621         }
 622
 623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 624                 /* Enable or disable VLAN stripping */
 625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 626                     true : false;
 627
 628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 629                 if (ret) {
 630                         rte_spinlock_unlock(&hw->lock);
 631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 632                                  enable ? "enable" : "disable", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         rte_spinlock_unlock(&hw->lock);
 638
 639         return ret;
 640 }
 641
 642 static int
 643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 644                              struct hns3_tx_vtag_cfg *vcfg)
 645 {
 646         struct hns3_vport_vtag_tx_cfg_cmd *req;
 647         struct hns3_cmd_desc desc;
 648         struct hns3_hw *hw = &hns->hw;
 649         uint16_t vport_id;
 650         uint8_t bitmap;
 651         int ret;
 652
 653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 654
 655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 656         req->def_vlan_tag1 = vcfg->default_tag1;
 657         req->def_vlan_tag2 = vcfg->default_tag2;
 658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 659                      vcfg->accept_tag1 ? 1 : 0);
 660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 661                      vcfg->accept_untag1 ? 1 : 0);
 662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 663                      vcfg->accept_tag2 ? 1 : 0);
 664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 665                      vcfg->accept_untag2 ? 1 : 0);
 666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 667                      vcfg->insert_tag1_en ? 1 : 0);
 668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 669                      vcfg->insert_tag2_en ? 1 : 0);
 670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 671
 672         /*
 673          * In current version VF is not supported when PF is driven by DPDK
 674          * driver, the PF-related vf_id is 0, just need to configure parameters
 675          * for vport_id 0.
 676          */
 677         vport_id = 0;
 678         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 679         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 680         req->vf_bitmap[req->vf_offset] = bitmap;
 681
 682         ret = hns3_cmd_send(hw, &desc, 1);
 683         if (ret)
 684                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 685
 686         return ret;
 687 }
 688
 689 static int
 690 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 691                      uint16_t pvid)
 692 {
 693         struct hns3_hw *hw = &hns->hw;
 694         struct hns3_tx_vtag_cfg txvlan_cfg;
 695         int ret;
 696
 697         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 698                 txvlan_cfg.accept_tag1 = true;
 699                 txvlan_cfg.insert_tag1_en = false;
 700                 txvlan_cfg.default_tag1 = 0;
 701         } else {
 702                 txvlan_cfg.accept_tag1 = false;
 703                 txvlan_cfg.insert_tag1_en = true;
 704                 txvlan_cfg.default_tag1 = pvid;
 705         }
 706
 707         txvlan_cfg.accept_untag1 = true;
 708         txvlan_cfg.accept_tag2 = true;
 709         txvlan_cfg.accept_untag2 = true;
 710         txvlan_cfg.insert_tag2_en = false;
 711         txvlan_cfg.default_tag2 = 0;
 712
 713         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 714         if (ret) {
 715                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 716                          ret);
 717                 return ret;
 718         }
 719
 720         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 721         return ret;
 722 }
 723
 724 static void
 725 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 726 {
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         pf->port_base_vlan_cfg.state = on ?
 730             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 731
 732         pf->port_base_vlan_cfg.pvid = pvid;
 733 }
 734
 735 static void
 736 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 737 {
 738         struct hns3_user_vlan_table *vlan_entry;
 739         struct hns3_pf *pf = &hns->pf;
 740
 741         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 742                 if (vlan_entry->hd_tbl_status)
 743                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 744
 745                 vlan_entry->hd_tbl_status = false;
 746         }
 747
 748         if (is_del_list) {
 749                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 750                 while (vlan_entry) {
 751                         LIST_REMOVE(vlan_entry, next);
 752                         rte_free(vlan_entry);
 753                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 754                 }
 755         }
 756 }
 757
 758 static void
 759 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 760 {
 761         struct hns3_user_vlan_table *vlan_entry;
 762         struct hns3_pf *pf = &hns->pf;
 763
 764         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 765                 if (!vlan_entry->hd_tbl_status)
 766                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 767
 768                 vlan_entry->hd_tbl_status = true;
 769         }
 770 }
 771
 772 static void
 773 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 774 {
 775         struct hns3_hw *hw = &hns->hw;
 776         struct hns3_pf *pf = &hns->pf;
 777         int ret;
 778
 779         hns3_rm_all_vlan_table(hns, true);
 780         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 781                 ret = hns3_set_port_vlan_filter(hns,
 782                                                 pf->port_base_vlan_cfg.pvid, 0);
 783                 if (ret) {
 784                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 785                                  ret);
 786                         return;
 787                 }
 788         }
 789 }
 790
 791 static int
 792 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 793                                 uint16_t port_base_vlan_state,
 794                                 uint16_t new_pvid, uint16_t old_pvid)
 795 {
 796         struct hns3_pf *pf = &hns->pf;
 797         struct hns3_hw *hw = &hns->hw;
 798         int ret = 0;
 799
 800         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 801                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 802                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 803                         if (ret) {
 804                                 hns3_err(hw,
 805                                          "Failed to clear clear old pvid filter, ret =%d",
 806                                          ret);
 807                                 return ret;
 808                         }
 809                 }
 810
 811                 hns3_rm_all_vlan_table(hns, false);
 812                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 813         }
 814
 815         if (new_pvid != 0) {
 816                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 817                 if (ret) {
 818                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 819                                  ret);
 820                         return ret;
 821                 }
 822         }
 823
 824         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 825                 hns3_add_all_vlan_table(hns);
 826
 827         return ret;
 828 }
 829
 830 static int
 831 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 832 {
 833         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 834         struct hns3_hw *hw = &hns->hw;
 835         bool rx_strip_en;
 836         int ret;
 837
 838         rx_strip_en = on ? true : false;
 839         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 840         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 841         rx_vlan_cfg.vlan1_vlan_prionly = false;
 842         rx_vlan_cfg.vlan2_vlan_prionly = false;
 843         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 844
 845         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 846         if (ret) {
 847                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 852         return ret;
 853 }
 854
 855 static int
 856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 857 {
 858         struct hns3_pf *pf = &hns->pf;
 859         struct hns3_hw *hw = &hns->hw;
 860         uint16_t port_base_vlan_state;
 861         uint16_t old_pvid;
 862         int ret;
 863
 864         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 865                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 866                         hns3_warn(hw, "Invalid operation! As current pvid set "
 867                                   "is %u, disable pvid %u is invalid",
 868                                   pf->port_base_vlan_cfg.pvid, pvid);
 869                 return 0;
 870         }
 871
 872         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 873                                     HNS3_PORT_BASE_VLAN_DISABLE;
 874         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 875         if (ret) {
 876                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 877                 return ret;
 878         }
 879
 880         ret = hns3_en_rx_strip_all(hns, on);
 881         if (ret) {
 882                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 883                 return ret;
 884         }
 885
 886         if (pvid == HNS3_INVLID_PVID)
 887                 goto out;
 888         old_pvid = pf->port_base_vlan_cfg.pvid;
 889         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 890                                               old_pvid);
 891         if (ret) {
 892                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 893                          ret);
 894                 return ret;
 895         }
 896
 897 out:
 898         hns3_store_port_base_vlan_info(hns, pvid, on);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 904 {
 905         struct hns3_adapter *hns = dev->data->dev_private;
 906         struct hns3_hw *hw = &hns->hw;
 907         int ret;
 908
 909         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 910                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 911                          RTE_ETHER_MAX_VLAN_ID);
 912                 return -EINVAL;
 913         }
 914
 915         rte_spinlock_lock(&hw->lock);
 916         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 917         rte_spinlock_unlock(&hw->lock);
 918         return ret;
 919 }
 920
 921 static void
 922 init_port_base_vlan_info(struct hns3_hw *hw)
 923 {
 924         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 925         struct hns3_pf *pf = &hns->pf;
 926
 927         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 928         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 929 }
 930
 931 static int
 932 hns3_default_vlan_config(struct hns3_adapter *hns)
 933 {
 934         struct hns3_hw *hw = &hns->hw;
 935         int ret;
 936
 937         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 938         if (ret)
 939                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 940         return ret;
 941 }
 942
 943 static int
 944 hns3_init_vlan_config(struct hns3_adapter *hns)
 945 {
 946         struct hns3_hw *hw = &hns->hw;
 947         int ret;
 948
 949         /*
 950          * This function can be called in the initialization and reset process,
 951          * when in reset process, it means that hardware had been reseted
 952          * successfully and we need to restore the hardware configuration to
 953          * ensure that the hardware configuration remains unchanged before and
 954          * after reset.
 955          */
 956         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 957                 init_port_base_vlan_info(hw);
 958
 959         ret = hns3_vlan_filter_init(hns);
 960         if (ret) {
 961                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 962                 return ret;
 963         }
 964
 965         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 966                                        RTE_ETHER_TYPE_VLAN);
 967         if (ret) {
 968                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 969                 return ret;
 970         }
 971
 972         /*
 973          * When in the reinit dev stage of the reset process, the following
 974          * vlan-related configurations may differ from those at initialization,
 975          * we will restore configurations to hardware in hns3_restore_vlan_table
 976          * and hns3_restore_vlan_conf later.
 977          */
 978         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 979                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 980                 if (ret) {
 981                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 982                         return ret;
 983                 }
 984
 985                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 986                 if (ret) {
 987                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 988                                  ret);
 989                         return ret;
 990                 }
 991         }
 992
 993         return hns3_default_vlan_config(hns);
 994 }
 995
 996 static int
 997 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 998 {
 999         struct hns3_pf *pf = &hns->pf;
1000         struct hns3_hw *hw = &hns->hw;
1001         uint64_t offloads;
1002         bool enable;
1003         int ret;
1004
1005         /* restore vlan filter states */
1006         offloads = hw->data->dev_conf.rxmode.offloads;
1007         enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1008         ret = hns3_enable_vlan_filter(hns, enable);
1009         if (ret) {
1010                 hns3_err(hw, "failed to restore vlan rx filter conf, ret = %d",
1011                          ret);
1012                 return ret;
1013         }
1014
1015         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1016         if (ret) {
1017                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1018                 return ret;
1019         }
1020
1021         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1022         if (ret)
1023                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1024
1025         return ret;
1026 }
1027
1028 static int
1029 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1030 {
1031         struct hns3_adapter *hns = dev->data->dev_private;
1032         struct rte_eth_dev_data *data = dev->data;
1033         struct rte_eth_txmode *txmode;
1034         struct hns3_hw *hw = &hns->hw;
1035         int mask;
1036         int ret;
1037
1038         txmode = &data->dev_conf.txmode;
1039         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1040                 hns3_warn(hw,
1041                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1042                           "configuration is not supported! Ignore these two "
1043                           "parameters: hw_vlan_reject_tagged(%d), "
1044                           "hw_vlan_reject_untagged(%d)",
1045                           txmode->hw_vlan_reject_tagged,
1046                           txmode->hw_vlan_reject_untagged);
1047
1048         /* Apply vlan offload setting */
1049         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1050         ret = hns3_vlan_offload_set(dev, mask);
1051         if (ret) {
1052                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1053                          ret);
1054                 return ret;
1055         }
1056
1057         /* Apply pvid setting */
1058         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1059                                  txmode->hw_vlan_insert_pvid);
1060         if (ret)
1061                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1062                          txmode->pvid, ret);
1063
1064         return ret;
1065 }
1066
1067 static int
1068 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1069                 unsigned int tso_mss_max)
1070 {
1071         struct hns3_cfg_tso_status_cmd *req;
1072         struct hns3_cmd_desc desc;
1073         uint16_t tso_mss;
1074
1075         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1076
1077         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1078
1079         tso_mss = 0;
1080         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1081                        tso_mss_min);
1082         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1083
1084         tso_mss = 0;
1085         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1086                        tso_mss_max);
1087         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1088
1089         return hns3_cmd_send(hw, &desc, 1);
1090 }
1091
1092 int
1093 hns3_config_gro(struct hns3_hw *hw, bool en)
1094 {
1095         struct hns3_cfg_gro_status_cmd *req;
1096         struct hns3_cmd_desc desc;
1097         int ret;
1098
1099         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1100         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1101
1102         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1103
1104         ret = hns3_cmd_send(hw, &desc, 1);
1105         if (ret)
1106                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1107
1108         return ret;
1109 }
1110
1111 static int
1112 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1113                    uint16_t *allocated_size, bool is_alloc)
1114 {
1115         struct hns3_umv_spc_alc_cmd *req;
1116         struct hns3_cmd_desc desc;
1117         int ret;
1118
1119         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1120         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1121         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1122         req->space_size = rte_cpu_to_le_32(space_size);
1123
1124         ret = hns3_cmd_send(hw, &desc, 1);
1125         if (ret) {
1126                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1127                              is_alloc ? "allocate" : "free", ret);
1128                 return ret;
1129         }
1130
1131         if (is_alloc && allocated_size)
1132                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1133
1134         return 0;
1135 }
1136
1137 static int
1138 hns3_init_umv_space(struct hns3_hw *hw)
1139 {
1140         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1141         struct hns3_pf *pf = &hns->pf;
1142         uint16_t allocated_size = 0;
1143         int ret;
1144
1145         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1146                                  true);
1147         if (ret)
1148                 return ret;
1149
1150         if (allocated_size < pf->wanted_umv_size)
1151                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1152                              pf->wanted_umv_size, allocated_size);
1153
1154         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1155                                                 pf->wanted_umv_size;
1156         pf->used_umv_size = 0;
1157         return 0;
1158 }
1159
1160 static int
1161 hns3_uninit_umv_space(struct hns3_hw *hw)
1162 {
1163         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1164         struct hns3_pf *pf = &hns->pf;
1165         int ret;
1166
1167         if (pf->max_umv_size == 0)
1168                 return 0;
1169
1170         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1171         if (ret)
1172                 return ret;
1173
1174         pf->max_umv_size = 0;
1175
1176         return 0;
1177 }
1178
1179 static bool
1180 hns3_is_umv_space_full(struct hns3_hw *hw)
1181 {
1182         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1183         struct hns3_pf *pf = &hns->pf;
1184         bool is_full;
1185
1186         is_full = (pf->used_umv_size >= pf->max_umv_size);
1187
1188         return is_full;
1189 }
1190
1191 static void
1192 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1193 {
1194         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1195         struct hns3_pf *pf = &hns->pf;
1196
1197         if (is_free) {
1198                 if (pf->used_umv_size > 0)
1199                         pf->used_umv_size--;
1200         } else
1201                 pf->used_umv_size++;
1202 }
1203
1204 static void
1205 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1206                       const uint8_t *addr, bool is_mc)
1207 {
1208         const unsigned char *mac_addr = addr;
1209         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1210                             ((uint32_t)mac_addr[2] << 16) |
1211                             ((uint32_t)mac_addr[1] << 8) |
1212                             (uint32_t)mac_addr[0];
1213         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1214
1215         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1216         if (is_mc) {
1217                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1218                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1219                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1220         }
1221
1222         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1223         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1224 }
1225
1226 static int
1227 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1228                              uint8_t resp_code,
1229                              enum hns3_mac_vlan_tbl_opcode op)
1230 {
1231         if (cmdq_resp) {
1232                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1233                          cmdq_resp);
1234                 return -EIO;
1235         }
1236
1237         if (op == HNS3_MAC_VLAN_ADD) {
1238                 if (resp_code == 0 || resp_code == 1) {
1239                         return 0;
1240                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1241                         hns3_err(hw, "add mac addr failed for uc_overflow");
1242                         return -ENOSPC;
1243                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1244                         hns3_err(hw, "add mac addr failed for mc_overflow");
1245                         return -ENOSPC;
1246                 }
1247
1248                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1249                          resp_code);
1250                 return -EIO;
1251         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1252                 if (resp_code == 0) {
1253                         return 0;
1254                 } else if (resp_code == 1) {
1255                         hns3_dbg(hw, "remove mac addr failed for miss");
1256                         return -ENOENT;
1257                 }
1258
1259                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1260                          resp_code);
1261                 return -EIO;
1262         } else if (op == HNS3_MAC_VLAN_LKUP) {
1263                 if (resp_code == 0) {
1264                         return 0;
1265                 } else if (resp_code == 1) {
1266                         hns3_dbg(hw, "lookup mac addr failed for miss");
1267                         return -ENOENT;
1268                 }
1269
1270                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1271                          resp_code);
1272                 return -EIO;
1273         }
1274
1275         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1276                  op);
1277
1278         return -EINVAL;
1279 }
1280
1281 static int
1282 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1283                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1284                          struct hns3_cmd_desc *desc, bool is_mc)
1285 {
1286         uint8_t resp_code;
1287         uint16_t retval;
1288         int ret;
1289
1290         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1291         if (is_mc) {
1292                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1293                 memcpy(desc[0].data, req,
1294                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1295                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1296                                           true);
1297                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1299                                           true);
1300                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1301         } else {
1302                 memcpy(desc[0].data, req,
1303                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1304                 ret = hns3_cmd_send(hw, desc, 1);
1305         }
1306         if (ret) {
1307                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1308                          ret);
1309                 return ret;
1310         }
1311         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1312         retval = rte_le_to_cpu_16(desc[0].retval);
1313
1314         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1315                                             HNS3_MAC_VLAN_LKUP);
1316 }
1317
1318 static int
1319 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1320                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1321                       struct hns3_cmd_desc *mc_desc)
1322 {
1323         uint8_t resp_code;
1324         uint16_t retval;
1325         int cfg_status;
1326         int ret;
1327
1328         if (mc_desc == NULL) {
1329                 struct hns3_cmd_desc desc;
1330
1331                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1332                 memcpy(desc.data, req,
1333                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1334                 ret = hns3_cmd_send(hw, &desc, 1);
1335                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1336                 retval = rte_le_to_cpu_16(desc.retval);
1337
1338                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1339                                                           HNS3_MAC_VLAN_ADD);
1340         } else {
1341                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1342                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1343                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1344                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1345                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1346                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1347                 memcpy(mc_desc[0].data, req,
1348                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1349                 mc_desc[0].retval = 0;
1350                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1351                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1352                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1353
1354                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1355                                                           HNS3_MAC_VLAN_ADD);
1356         }
1357
1358         if (ret) {
1359                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1360                 return ret;
1361         }
1362
1363         return cfg_status;
1364 }
1365
1366 static int
1367 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1368                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1369 {
1370         struct hns3_cmd_desc desc;
1371         uint8_t resp_code;
1372         uint16_t retval;
1373         int ret;
1374
1375         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1376
1377         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1378
1379         ret = hns3_cmd_send(hw, &desc, 1);
1380         if (ret) {
1381                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1382                 return ret;
1383         }
1384         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1385         retval = rte_le_to_cpu_16(desc.retval);
1386
1387         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1388                                             HNS3_MAC_VLAN_REMOVE);
1389 }
1390
1391 static int
1392 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1393 {
1394         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1395         struct hns3_mac_vlan_tbl_entry_cmd req;
1396         struct hns3_pf *pf = &hns->pf;
1397         struct hns3_cmd_desc desc;
1398         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1399         uint16_t egress_port = 0;
1400         uint8_t vf_id;
1401         int ret;
1402
1403         /* check if mac addr is valid */
1404         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1405                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1406                                       mac_addr);
1407                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1408                          mac_str);
1409                 return -EINVAL;
1410         }
1411
1412         memset(&req, 0, sizeof(req));
1413
1414         /*
1415          * In current version VF is not supported when PF is driven by DPDK
1416          * driver, the PF-related vf_id is 0, just need to configure parameters
1417          * for vf_id 0.
1418          */
1419         vf_id = 0;
1420         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1421                        HNS3_MAC_EPORT_VFID_S, vf_id);
1422
1423         req.egress_port = rte_cpu_to_le_16(egress_port);
1424
1425         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1426
1427         /*
1428          * Lookup the mac address in the mac_vlan table, and add
1429          * it if the entry is inexistent. Repeated unicast entry
1430          * is not allowed in the mac vlan table.
1431          */
1432         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1433         if (ret == -ENOENT) {
1434                 if (!hns3_is_umv_space_full(hw)) {
1435                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1436                         if (!ret)
1437                                 hns3_update_umv_space(hw, false);
1438                         return ret;
1439                 }
1440
1441                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1442
1443                 return -ENOSPC;
1444         }
1445
1446         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1447
1448         /* check if we just hit the duplicate */
1449         if (ret == 0) {
1450                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1451                 return 0;
1452         }
1453
1454         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1455                  mac_str);
1456
1457         return ret;
1458 }
1459
1460 static int
1461 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1462 {
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         struct rte_ether_addr *addr;
1465         int ret;
1466         int i;
1467
1468         for (i = 0; i < hw->mc_addrs_num; i++) {
1469                 addr = &hw->mc_addrs[i];
1470                 /* Check if there are duplicate addresses */
1471                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1472                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1473                                               addr);
1474                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1475                                  "(%s) is added by the set_mc_mac_addr_list "
1476                                  "API", mac_str);
1477                         return -EINVAL;
1478                 }
1479         }
1480
1481         ret = hns3_add_mc_addr(hw, mac_addr);
1482         if (ret) {
1483                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1484                                       mac_addr);
1485                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1486                          mac_str, ret);
1487         }
1488         return ret;
1489 }
1490
1491 static int
1492 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1493 {
1494         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1495         int ret;
1496
1497         ret = hns3_remove_mc_addr(hw, mac_addr);
1498         if (ret) {
1499                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1500                                       mac_addr);
1501                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1502                          mac_str, ret);
1503         }
1504         return ret;
1505 }
1506
1507 static int
1508 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1509                   uint32_t idx, __rte_unused uint32_t pool)
1510 {
1511         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1513         int ret;
1514
1515         rte_spinlock_lock(&hw->lock);
1516
1517         /*
1518          * In hns3 network engine adding UC and MC mac address with different
1519          * commands with firmware. We need to determine whether the input
1520          * address is a UC or a MC address to call different commands.
1521          * By the way, it is recommended calling the API function named
1522          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1523          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1524          * may affect the specifications of UC mac addresses.
1525          */
1526         if (rte_is_multicast_ether_addr(mac_addr))
1527                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1528         else
1529                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1530
1531         if (ret) {
1532                 rte_spinlock_unlock(&hw->lock);
1533                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1534                                       mac_addr);
1535                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1536                          ret);
1537                 return ret;
1538         }
1539
1540         if (idx == 0)
1541                 hw->mac.default_addr_setted = true;
1542         rte_spinlock_unlock(&hw->lock);
1543
1544         return ret;
1545 }
1546
1547 static int
1548 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1549 {
1550         struct hns3_mac_vlan_tbl_entry_cmd req;
1551         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1552         int ret;
1553
1554         /* check if mac addr is valid */
1555         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1557                                       mac_addr);
1558                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1559                          mac_str);
1560                 return -EINVAL;
1561         }
1562
1563         memset(&req, 0, sizeof(req));
1564         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1565         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1566         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1567         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1568                 return 0;
1569         else if (ret == 0)
1570                 hns3_update_umv_space(hw, true);
1571
1572         return ret;
1573 }
1574
1575 static void
1576 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1577 {
1578         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579         /* index will be checked by upper level rte interface */
1580         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1581         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1582         int ret;
1583
1584         rte_spinlock_lock(&hw->lock);
1585
1586         if (rte_is_multicast_ether_addr(mac_addr))
1587                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1588         else
1589                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1590         rte_spinlock_unlock(&hw->lock);
1591         if (ret) {
1592                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1593                                       mac_addr);
1594                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1595                          ret);
1596         }
1597 }
1598
1599 static int
1600 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1601                           struct rte_ether_addr *mac_addr)
1602 {
1603         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         struct rte_ether_addr *oaddr;
1605         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1606         bool default_addr_setted;
1607         bool rm_succes = false;
1608         int ret, ret_val;
1609
1610         /*
1611          * It has been guaranteed that input parameter named mac_addr is valid
1612          * address in the rte layer of DPDK framework.
1613          */
1614         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1615         default_addr_setted = hw->mac.default_addr_setted;
1616         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1617                 return 0;
1618
1619         rte_spinlock_lock(&hw->lock);
1620         if (default_addr_setted) {
1621                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1622                 if (ret) {
1623                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1624                                               oaddr);
1625                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1626                                   mac_str, ret);
1627                         rm_succes = false;
1628                 } else
1629                         rm_succes = true;
1630         }
1631
1632         ret = hns3_add_uc_addr_common(hw, mac_addr);
1633         if (ret) {
1634                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635                                       mac_addr);
1636                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1637                 goto err_add_uc_addr;
1638         }
1639
1640         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1641         if (ret) {
1642                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1643                 goto err_pause_addr_cfg;
1644         }
1645
1646         rte_ether_addr_copy(mac_addr,
1647                             (struct rte_ether_addr *)hw->mac.mac_addr);
1648         hw->mac.default_addr_setted = true;
1649         rte_spinlock_unlock(&hw->lock);
1650
1651         return 0;
1652
1653 err_pause_addr_cfg:
1654         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1655         if (ret_val) {
1656                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1657                                       mac_addr);
1658                 hns3_warn(hw,
1659                           "Failed to roll back to del setted mac addr(%s): %d",
1660                           mac_str, ret_val);
1661         }
1662
1663 err_add_uc_addr:
1664         if (rm_succes) {
1665                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1666                 if (ret_val) {
1667                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668                                               oaddr);
1669                         hns3_warn(hw,
1670                                   "Failed to restore old uc mac addr(%s): %d",
1671                                   mac_str, ret_val);
1672                         hw->mac.default_addr_setted = false;
1673                 }
1674         }
1675         rte_spinlock_unlock(&hw->lock);
1676
1677         return ret;
1678 }
1679
1680 static int
1681 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1682 {
1683         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1684         struct hns3_hw *hw = &hns->hw;
1685         struct rte_ether_addr *addr;
1686         int err = 0;
1687         int ret;
1688         int i;
1689
1690         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1691                 addr = &hw->data->mac_addrs[i];
1692                 if (rte_is_zero_ether_addr(addr))
1693                         continue;
1694                 if (rte_is_multicast_ether_addr(addr))
1695                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1696                               hns3_add_mc_addr(hw, addr);
1697                 else
1698                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1699                               hns3_add_uc_addr_common(hw, addr);
1700
1701                 if (ret) {
1702                         err = ret;
1703                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704                                               addr);
1705                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1706                                  "ret = %d.", del ? "remove" : "restore",
1707                                  mac_str, i, ret);
1708                 }
1709         }
1710         return err;
1711 }
1712
1713 static void
1714 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1715 {
1716 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1717         uint8_t word_num;
1718         uint8_t bit_num;
1719
1720         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1721                 word_num = vfid / 32;
1722                 bit_num = vfid % 32;
1723                 if (clr)
1724                         desc[1].data[word_num] &=
1725                             rte_cpu_to_le_32(~(1UL << bit_num));
1726                 else
1727                         desc[1].data[word_num] |=
1728                             rte_cpu_to_le_32(1UL << bit_num);
1729         } else {
1730                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1731                 bit_num = vfid % 32;
1732                 if (clr)
1733                         desc[2].data[word_num] &=
1734                             rte_cpu_to_le_32(~(1UL << bit_num));
1735                 else
1736                         desc[2].data[word_num] |=
1737                             rte_cpu_to_le_32(1UL << bit_num);
1738         }
1739 }
1740
1741 static int
1742 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1743 {
1744         struct hns3_mac_vlan_tbl_entry_cmd req;
1745         struct hns3_cmd_desc desc[3];
1746         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1747         uint8_t vf_id;
1748         int ret;
1749
1750         /* Check if mac addr is valid */
1751         if (!rte_is_multicast_ether_addr(mac_addr)) {
1752                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1753                                       mac_addr);
1754                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1755                          mac_str);
1756                 return -EINVAL;
1757         }
1758
1759         memset(&req, 0, sizeof(req));
1760         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1761         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1762         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1763         if (ret) {
1764                 /* This mac addr do not exist, add new entry for it */
1765                 memset(desc[0].data, 0, sizeof(desc[0].data));
1766                 memset(desc[1].data, 0, sizeof(desc[0].data));
1767                 memset(desc[2].data, 0, sizeof(desc[0].data));
1768         }
1769
1770         /*
1771          * In current version VF is not supported when PF is driven by DPDK
1772          * driver, the PF-related vf_id is 0, just need to configure parameters
1773          * for vf_id 0.
1774          */
1775         vf_id = 0;
1776         hns3_update_desc_vfid(desc, vf_id, false);
1777         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1778         if (ret) {
1779                 if (ret == -ENOSPC)
1780                         hns3_err(hw, "mc mac vlan table is full");
1781                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                       mac_addr);
1783                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1784         }
1785
1786         return ret;
1787 }
1788
1789 static int
1790 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1791 {
1792         struct hns3_mac_vlan_tbl_entry_cmd req;
1793         struct hns3_cmd_desc desc[3];
1794         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1795         uint8_t vf_id;
1796         int ret;
1797
1798         /* Check if mac addr is valid */
1799         if (!rte_is_multicast_ether_addr(mac_addr)) {
1800                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1801                                       mac_addr);
1802                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1803                          mac_str);
1804                 return -EINVAL;
1805         }
1806
1807         memset(&req, 0, sizeof(req));
1808         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1809         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1810         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1811         if (ret == 0) {
1812                 /*
1813                  * This mac addr exist, remove this handle's VFID for it.
1814                  * In current version VF is not supported when PF is driven by
1815                  * DPDK driver, the PF-related vf_id is 0, just need to
1816                  * configure parameters for vf_id 0.
1817                  */
1818                 vf_id = 0;
1819                 hns3_update_desc_vfid(desc, vf_id, true);
1820
1821                 /* All the vfid is zero, so need to delete this entry */
1822                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1823         } else if (ret == -ENOENT) {
1824                 /* This mac addr doesn't exist. */
1825                 return 0;
1826         }
1827
1828         if (ret) {
1829                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1830                                       mac_addr);
1831                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1832         }
1833
1834         return ret;
1835 }
1836
1837 static int
1838 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1839                            struct rte_ether_addr *mc_addr_set,
1840                            uint32_t nb_mc_addr)
1841 {
1842         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1843         struct rte_ether_addr *addr;
1844         uint32_t i;
1845         uint32_t j;
1846
1847         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1848                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1849                          "invalid. valid range: 0~%d",
1850                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1851                 return -EINVAL;
1852         }
1853
1854         /* Check if input mac addresses are valid */
1855         for (i = 0; i < nb_mc_addr; i++) {
1856                 addr = &mc_addr_set[i];
1857                 if (!rte_is_multicast_ether_addr(addr)) {
1858                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1859                                               addr);
1860                         hns3_err(hw,
1861                                  "failed to set mc mac addr, addr(%s) invalid.",
1862                                  mac_str);
1863                         return -EINVAL;
1864                 }
1865
1866                 /* Check if there are duplicate addresses */
1867                 for (j = i + 1; j < nb_mc_addr; j++) {
1868                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1869                                 rte_ether_format_addr(mac_str,
1870                                                       RTE_ETHER_ADDR_FMT_SIZE,
1871                                                       addr);
1872                                 hns3_err(hw, "failed to set mc mac addr, "
1873                                          "addrs invalid. two same addrs(%s).",
1874                                          mac_str);
1875                                 return -EINVAL;
1876                         }
1877                 }
1878
1879                 /*
1880                  * Check if there are duplicate addresses between mac_addrs
1881                  * and mc_addr_set
1882                  */
1883                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1884                         if (rte_is_same_ether_addr(addr,
1885                                                    &hw->data->mac_addrs[j])) {
1886                                 rte_ether_format_addr(mac_str,
1887                                                       RTE_ETHER_ADDR_FMT_SIZE,
1888                                                       addr);
1889                                 hns3_err(hw, "failed to set mc mac addr, "
1890                                          "addrs invalid. addrs(%s) has already "
1891                                          "configured in mac_addr add API",
1892                                          mac_str);
1893                                 return -EINVAL;
1894                         }
1895                 }
1896         }
1897
1898         return 0;
1899 }
1900
1901 static void
1902 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1903                            struct rte_ether_addr *mc_addr_set,
1904                            int mc_addr_num,
1905                            struct rte_ether_addr *reserved_addr_list,
1906                            int *reserved_addr_num,
1907                            struct rte_ether_addr *add_addr_list,
1908                            int *add_addr_num,
1909                            struct rte_ether_addr *rm_addr_list,
1910                            int *rm_addr_num)
1911 {
1912         struct rte_ether_addr *addr;
1913         int current_addr_num;
1914         int reserved_num = 0;
1915         int add_num = 0;
1916         int rm_num = 0;
1917         int num;
1918         int i;
1919         int j;
1920         bool same_addr;
1921
1922         /* Calculate the mc mac address list that should be removed */
1923         current_addr_num = hw->mc_addrs_num;
1924         for (i = 0; i < current_addr_num; i++) {
1925                 addr = &hw->mc_addrs[i];
1926                 same_addr = false;
1927                 for (j = 0; j < mc_addr_num; j++) {
1928                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1929                                 same_addr = true;
1930                                 break;
1931                         }
1932                 }
1933
1934                 if (!same_addr) {
1935                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1936                         rm_num++;
1937                 } else {
1938                         rte_ether_addr_copy(addr,
1939                                             &reserved_addr_list[reserved_num]);
1940                         reserved_num++;
1941                 }
1942         }
1943
1944         /* Calculate the mc mac address list that should be added */
1945         for (i = 0; i < mc_addr_num; i++) {
1946                 addr = &mc_addr_set[i];
1947                 same_addr = false;
1948                 for (j = 0; j < current_addr_num; j++) {
1949                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1950                                 same_addr = true;
1951                                 break;
1952                         }
1953                 }
1954
1955                 if (!same_addr) {
1956                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1957                         add_num++;
1958                 }
1959         }
1960
1961         /* Reorder the mc mac address list maintained by driver */
1962         for (i = 0; i < reserved_num; i++)
1963                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1964
1965         for (i = 0; i < rm_num; i++) {
1966                 num = reserved_num + i;
1967                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1968         }
1969
1970         *reserved_addr_num = reserved_num;
1971         *add_addr_num = add_num;
1972         *rm_addr_num = rm_num;
1973 }
1974
1975 static int
1976 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1977                           struct rte_ether_addr *mc_addr_set,
1978                           uint32_t nb_mc_addr)
1979 {
1980         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1982         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1983         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1984         struct rte_ether_addr *addr;
1985         int reserved_addr_num;
1986         int add_addr_num;
1987         int rm_addr_num;
1988         int mc_addr_num;
1989         int num;
1990         int ret;
1991         int i;
1992
1993         /* Check if input parameters are valid */
1994         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1995         if (ret)
1996                 return ret;
1997
1998         rte_spinlock_lock(&hw->lock);
1999
2000         /*
2001          * Calculate the mc mac address lists those should be removed and be
2002          * added, Reorder the mc mac address list maintained by driver.
2003          */
2004         mc_addr_num = (int)nb_mc_addr;
2005         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2006                                    reserved_addr_list, &reserved_addr_num,
2007                                    add_addr_list, &add_addr_num,
2008                                    rm_addr_list, &rm_addr_num);
2009
2010         /* Remove mc mac addresses */
2011         for (i = 0; i < rm_addr_num; i++) {
2012                 num = rm_addr_num - i - 1;
2013                 addr = &rm_addr_list[num];
2014                 ret = hns3_remove_mc_addr(hw, addr);
2015                 if (ret) {
2016                         rte_spinlock_unlock(&hw->lock);
2017                         return ret;
2018                 }
2019                 hw->mc_addrs_num--;
2020         }
2021
2022         /* Add mc mac addresses */
2023         for (i = 0; i < add_addr_num; i++) {
2024                 addr = &add_addr_list[i];
2025                 ret = hns3_add_mc_addr(hw, addr);
2026                 if (ret) {
2027                         rte_spinlock_unlock(&hw->lock);
2028                         return ret;
2029                 }
2030
2031                 num = reserved_addr_num + i;
2032                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2033                 hw->mc_addrs_num++;
2034         }
2035         rte_spinlock_unlock(&hw->lock);
2036
2037         return 0;
2038 }
2039
2040 static int
2041 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2042 {
2043         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2044         struct hns3_hw *hw = &hns->hw;
2045         struct rte_ether_addr *addr;
2046         int err = 0;
2047         int ret;
2048         int i;
2049
2050         for (i = 0; i < hw->mc_addrs_num; i++) {
2051                 addr = &hw->mc_addrs[i];
2052                 if (!rte_is_multicast_ether_addr(addr))
2053                         continue;
2054                 if (del)
2055                         ret = hns3_remove_mc_addr(hw, addr);
2056                 else
2057                         ret = hns3_add_mc_addr(hw, addr);
2058                 if (ret) {
2059                         err = ret;
2060                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2061                                               addr);
2062                         hns3_dbg(hw, "%s mc mac addr: %s failed",
2063                                  del ? "Remove" : "Restore", mac_str);
2064                 }
2065         }
2066         return err;
2067 }
2068
2069 static int
2070 hns3_check_mq_mode(struct rte_eth_dev *dev)
2071 {
2072         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2073         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2074         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2076         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2077         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2078         uint8_t num_tc;
2079         int max_tc = 0;
2080         int i;
2081
2082         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2083         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2084
2085         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2086                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2087                          "rx_mq_mode = %d", rx_mq_mode);
2088                 return -EINVAL;
2089         }
2090
2091         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2092             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2093                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2094                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2095                          rx_mq_mode, tx_mq_mode);
2096                 return -EINVAL;
2097         }
2098
2099         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2100                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2101                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2102                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2103                         return -EINVAL;
2104                 }
2105
2106                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2107                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2108                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2109                                  "nb_tcs(%d) != %d or %d in rx direction.",
2110                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2111                         return -EINVAL;
2112                 }
2113
2114                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2115                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2116                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2117                         return -EINVAL;
2118                 }
2119
2120                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2121                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2122                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2123                                          "is not equal to one in tx direction.",
2124                                          i, dcb_rx_conf->dcb_tc[i]);
2125                                 return -EINVAL;
2126                         }
2127                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2128                                 max_tc = dcb_rx_conf->dcb_tc[i];
2129                 }
2130
2131                 num_tc = max_tc + 1;
2132                 if (num_tc > dcb_rx_conf->nb_tcs) {
2133                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2134                                  num_tc, dcb_rx_conf->nb_tcs);
2135                         return -EINVAL;
2136                 }
2137         }
2138
2139         return 0;
2140 }
2141
2142 static int
2143 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2144 {
2145         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146
2147         if (!hns3_dev_dcb_supported(hw)) {
2148                 hns3_err(hw, "this port does not support dcb configurations.");
2149                 return -EOPNOTSUPP;
2150         }
2151
2152         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2153                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2154                 return -EOPNOTSUPP;
2155         }
2156
2157         /* Check multiple queue mode */
2158         return hns3_check_mq_mode(dev);
2159 }
2160
2161 static int
2162 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2163                            enum hns3_ring_type queue_type, uint16_t queue_id)
2164 {
2165         struct hns3_cmd_desc desc;
2166         struct hns3_ctrl_vector_chain_cmd *req =
2167                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2168         enum hns3_cmd_status status;
2169         enum hns3_opcode_type op;
2170         uint16_t tqp_type_and_id = 0;
2171         const char *op_str;
2172         uint16_t type;
2173         uint16_t gl;
2174
2175         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2176         hns3_cmd_setup_basic_desc(&desc, op, false);
2177         req->int_vector_id = vector_id;
2178
2179         if (queue_type == HNS3_RING_TYPE_RX)
2180                 gl = HNS3_RING_GL_RX;
2181         else
2182                 gl = HNS3_RING_GL_TX;
2183
2184         type = queue_type;
2185
2186         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2187                        type);
2188         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2189         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2190                        gl);
2191         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2192         req->int_cause_num = 1;
2193         op_str = mmap ? "Map" : "Unmap";
2194         status = hns3_cmd_send(hw, &desc, 1);
2195         if (status) {
2196                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2197                          op_str, queue_id, req->int_vector_id, status);
2198                 return status;
2199         }
2200
2201         return 0;
2202 }
2203
2204 static int
2205 hns3_init_ring_with_vector(struct hns3_hw *hw)
2206 {
2207         uint8_t vec;
2208         int ret;
2209         int i;
2210
2211         /*
2212          * In hns3 network engine, vector 0 is always the misc interrupt of this
2213          * function, vector 1~N can be used respectively for the queues of the
2214          * function. Tx and Rx queues with the same number share the interrupt
2215          * vector. In the initialization clearing the all hardware mapping
2216          * relationship configurations between queues and interrupt vectors is
2217          * needed, so some error caused by the residual configurations, such as
2218          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2219          * constraints in hns3 hardware engine, we have to implement clearing
2220          * the mapping relationship configurations by binding all queues to the
2221          * last interrupt vector and reserving the last interrupt vector. This
2222          * method results in a decrease of the maximum queues when upper
2223          * applications call the rte_eth_dev_configure API function to enable
2224          * Rx interrupt.
2225          */
2226         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2227         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2228         for (i = 0; i < hw->intr_tqps_num; i++) {
2229                 /*
2230                  * Set gap limiter and rate limiter configuration of queue's
2231                  * interrupt.
2232                  */
2233                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2234                                        HNS3_TQP_INTR_GL_DEFAULT);
2235                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2236                                        HNS3_TQP_INTR_GL_DEFAULT);
2237                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2238
2239                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2240                                                  HNS3_RING_TYPE_TX, i);
2241                 if (ret) {
2242                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2243                                           "vector: %d, ret=%d", i, vec, ret);
2244                         return ret;
2245                 }
2246
2247                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2248                                                  HNS3_RING_TYPE_RX, i);
2249                 if (ret) {
2250                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2251                                           "vector: %d, ret=%d", i, vec, ret);
2252                         return ret;
2253                 }
2254         }
2255
2256         return 0;
2257 }
2258
2259 static int
2260 hns3_dev_configure(struct rte_eth_dev *dev)
2261 {
2262         struct hns3_adapter *hns = dev->data->dev_private;
2263         struct rte_eth_conf *conf = &dev->data->dev_conf;
2264         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2265         struct hns3_hw *hw = &hns->hw;
2266         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2267         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2268         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2269         struct rte_eth_rss_conf rss_conf;
2270         uint16_t mtu;
2271         int ret;
2272
2273         /*
2274          * Hardware does not support individually enable/disable/reset the Tx or
2275          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2276          * and Rx queues at the same time. When the numbers of Tx queues
2277          * allocated by upper applications are not equal to the numbers of Rx
2278          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2279          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2280          * these fake queues are imperceptible, and can not be used by upper
2281          * applications.
2282          */
2283         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2284         if (ret) {
2285                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2286                 return ret;
2287         }
2288
2289         hw->adapter_state = HNS3_NIC_CONFIGURING;
2290         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2291                 hns3_err(hw, "setting link speed/duplex not supported");
2292                 ret = -EINVAL;
2293                 goto cfg_err;
2294         }
2295
2296         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2297                 ret = hns3_check_dcb_cfg(dev);
2298                 if (ret)
2299                         goto cfg_err;
2300         }
2301
2302         /* When RSS is not configured, redirect the packet queue 0 */
2303         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2304                 rss_conf = conf->rx_adv_conf.rss_conf;
2305                 if (rss_conf.rss_key == NULL) {
2306                         rss_conf.rss_key = rss_cfg->key;
2307                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2308                 }
2309
2310                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2311                 if (ret)
2312                         goto cfg_err;
2313         }
2314
2315         /*
2316          * If jumbo frames are enabled, MTU needs to be refreshed
2317          * according to the maximum RX packet length.
2318          */
2319         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2320                 /*
2321                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2322                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2323                  * can safely assign to "uint16_t" type variable.
2324                  */
2325                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2326                 ret = hns3_dev_mtu_set(dev, mtu);
2327                 if (ret)
2328                         goto cfg_err;
2329                 dev->data->mtu = mtu;
2330         }
2331
2332         ret = hns3_dev_configure_vlan(dev);
2333         if (ret)
2334                 goto cfg_err;
2335
2336         hw->adapter_state = HNS3_NIC_CONFIGURED;
2337
2338         return 0;
2339
2340 cfg_err:
2341         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2342         hw->adapter_state = HNS3_NIC_INITIALIZED;
2343
2344         return ret;
2345 }
2346
2347 static int
2348 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2349 {
2350         struct hns3_config_max_frm_size_cmd *req;
2351         struct hns3_cmd_desc desc;
2352
2353         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2354
2355         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2356         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2357         req->min_frm_size = RTE_ETHER_MIN_LEN;
2358
2359         return hns3_cmd_send(hw, &desc, 1);
2360 }
2361
2362 static int
2363 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2364 {
2365         int ret;
2366
2367         ret = hns3_set_mac_mtu(hw, mps);
2368         if (ret) {
2369                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2370                 return ret;
2371         }
2372
2373         ret = hns3_buffer_alloc(hw);
2374         if (ret)
2375                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2376
2377         return ret;
2378 }
2379
2380 static int
2381 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2382 {
2383         struct hns3_adapter *hns = dev->data->dev_private;
2384         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2385         struct hns3_hw *hw = &hns->hw;
2386         bool is_jumbo_frame;
2387         int ret;
2388
2389         if (dev->data->dev_started) {
2390                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2391                          "before configuration", dev->data->port_id);
2392                 return -EBUSY;
2393         }
2394
2395         rte_spinlock_lock(&hw->lock);
2396         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2397         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2398
2399         /*
2400          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2401          * assign to "uint16_t" type variable.
2402          */
2403         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2404         if (ret) {
2405                 rte_spinlock_unlock(&hw->lock);
2406                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2407                          dev->data->port_id, mtu, ret);
2408                 return ret;
2409         }
2410         hns->pf.mps = (uint16_t)frame_size;
2411         if (is_jumbo_frame)
2412                 dev->data->dev_conf.rxmode.offloads |=
2413                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2414         else
2415                 dev->data->dev_conf.rxmode.offloads &=
2416                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2417         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2418         rte_spinlock_unlock(&hw->lock);
2419
2420         return 0;
2421 }
2422
2423 static int
2424 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2425 {
2426         struct hns3_adapter *hns = eth_dev->data->dev_private;
2427         struct hns3_hw *hw = &hns->hw;
2428         uint16_t queue_num = hw->tqps_num;
2429
2430         /*
2431          * In interrupt mode, 'max_rx_queues' is set based on the number of
2432          * MSI-X interrupt resources of the hardware.
2433          */
2434         if (hw->data->dev_conf.intr_conf.rxq == 1)
2435                 queue_num = hw->intr_tqps_num;
2436
2437         info->max_rx_queues = queue_num;
2438         info->max_tx_queues = hw->tqps_num;
2439         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2440         info->min_rx_bufsize = hw->rx_buf_len;
2441         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2442         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2443         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2444                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2445                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2446                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2447                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2448                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2449                                  DEV_RX_OFFLOAD_KEEP_CRC |
2450                                  DEV_RX_OFFLOAD_SCATTER |
2451                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2452                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2453                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2454                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2455                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2456                                  DEV_RX_OFFLOAD_RSS_HASH);
2457         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2458         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2459                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2460                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2461                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2462                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2463                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2464                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2465                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2466                                  DEV_TX_OFFLOAD_TCP_TSO |
2467                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2468                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2469                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2470                                  info->tx_queue_offload_capa);
2471
2472         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2473                 .nb_max = HNS3_MAX_RING_DESC,
2474                 .nb_min = HNS3_MIN_RING_DESC,
2475                 .nb_align = HNS3_ALIGN_RING_DESC,
2476         };
2477
2478         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2479                 .nb_max = HNS3_MAX_RING_DESC,
2480                 .nb_min = HNS3_MIN_RING_DESC,
2481                 .nb_align = HNS3_ALIGN_RING_DESC,
2482         };
2483
2484         info->vmdq_queue_num = 0;
2485
2486         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2487         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2488         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2489
2490         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2491         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2492         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2493         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2494         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2495         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2496
2497         return 0;
2498 }
2499
2500 static int
2501 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2502                     size_t fw_size)
2503 {
2504         struct hns3_adapter *hns = eth_dev->data->dev_private;
2505         struct hns3_hw *hw = &hns->hw;
2506         int ret;
2507
2508         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2509         ret += 1; /* add the size of '\0' */
2510         if (fw_size < (uint32_t)ret)
2511                 return ret;
2512         else
2513                 return 0;
2514 }
2515
2516 static int
2517 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2518                      __rte_unused int wait_to_complete)
2519 {
2520         struct hns3_adapter *hns = eth_dev->data->dev_private;
2521         struct hns3_hw *hw = &hns->hw;
2522         struct hns3_mac *mac = &hw->mac;
2523         struct rte_eth_link new_link;
2524
2525         if (!hns3_is_reset_pending(hns)) {
2526                 hns3_update_speed_duplex(eth_dev);
2527                 hns3_update_link_status(hw);
2528         }
2529
2530         memset(&new_link, 0, sizeof(new_link));
2531         switch (mac->link_speed) {
2532         case ETH_SPEED_NUM_10M:
2533         case ETH_SPEED_NUM_100M:
2534         case ETH_SPEED_NUM_1G:
2535         case ETH_SPEED_NUM_10G:
2536         case ETH_SPEED_NUM_25G:
2537         case ETH_SPEED_NUM_40G:
2538         case ETH_SPEED_NUM_50G:
2539         case ETH_SPEED_NUM_100G:
2540                 new_link.link_speed = mac->link_speed;
2541                 break;
2542         default:
2543                 new_link.link_speed = ETH_SPEED_NUM_100M;
2544                 break;
2545         }
2546
2547         new_link.link_duplex = mac->link_duplex;
2548         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2549         new_link.link_autoneg =
2550             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2551
2552         return rte_eth_linkstatus_set(eth_dev, &new_link);
2553 }
2554
2555 static int
2556 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2557 {
2558         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2559         struct hns3_pf *pf = &hns->pf;
2560
2561         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2562                 return -EINVAL;
2563
2564         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2565
2566         return 0;
2567 }
2568
2569 static int
2570 hns3_query_function_status(struct hns3_hw *hw)
2571 {
2572 #define HNS3_QUERY_MAX_CNT              10
2573 #define HNS3_QUERY_SLEEP_MSCOEND        1
2574         struct hns3_func_status_cmd *req;
2575         struct hns3_cmd_desc desc;
2576         int timeout = 0;
2577         int ret;
2578
2579         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2580         req = (struct hns3_func_status_cmd *)desc.data;
2581
2582         do {
2583                 ret = hns3_cmd_send(hw, &desc, 1);
2584                 if (ret) {
2585                         PMD_INIT_LOG(ERR, "query function status failed %d",
2586                                      ret);
2587                         return ret;
2588                 }
2589
2590                 /* Check pf reset is done */
2591                 if (req->pf_state)
2592                         break;
2593
2594                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2595         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2596
2597         return hns3_parse_func_status(hw, req);
2598 }
2599
2600 static int
2601 hns3_query_pf_resource(struct hns3_hw *hw)
2602 {
2603         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2604         struct hns3_pf *pf = &hns->pf;
2605         struct hns3_pf_res_cmd *req;
2606         struct hns3_cmd_desc desc;
2607         uint16_t num_msi;
2608         int ret;
2609
2610         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2611         ret = hns3_cmd_send(hw, &desc, 1);
2612         if (ret) {
2613                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2614                 return ret;
2615         }
2616
2617         req = (struct hns3_pf_res_cmd *)desc.data;
2618         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2619         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2620         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2621         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2622
2623         if (req->tx_buf_size)
2624                 pf->tx_buf_size =
2625                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2626         else
2627                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2628
2629         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2630
2631         if (req->dv_buf_size)
2632                 pf->dv_buf_size =
2633                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2634         else
2635                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2636
2637         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2638
2639         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2640                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2641         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2642
2643         return 0;
2644 }
2645
2646 static void
2647 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2648 {
2649         struct hns3_cfg_param_cmd *req;
2650         uint64_t mac_addr_tmp_high;
2651         uint64_t mac_addr_tmp;
2652         uint32_t i;
2653
2654         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2655
2656         /* get the configuration */
2657         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2658                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2659         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2660                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2661         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2662                                            HNS3_CFG_TQP_DESC_N_M,
2663                                            HNS3_CFG_TQP_DESC_N_S);
2664
2665         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2666                                        HNS3_CFG_PHY_ADDR_M,
2667                                        HNS3_CFG_PHY_ADDR_S);
2668         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2669                                          HNS3_CFG_MEDIA_TP_M,
2670                                          HNS3_CFG_MEDIA_TP_S);
2671         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2672                                          HNS3_CFG_RX_BUF_LEN_M,
2673                                          HNS3_CFG_RX_BUF_LEN_S);
2674         /* get mac address */
2675         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2676         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2677                                            HNS3_CFG_MAC_ADDR_H_M,
2678                                            HNS3_CFG_MAC_ADDR_H_S);
2679
2680         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2681
2682         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2683                                             HNS3_CFG_DEFAULT_SPEED_M,
2684                                             HNS3_CFG_DEFAULT_SPEED_S);
2685         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2686                                            HNS3_CFG_RSS_SIZE_M,
2687                                            HNS3_CFG_RSS_SIZE_S);
2688
2689         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2690                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2691
2692         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2693         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2694
2695         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2696                                             HNS3_CFG_SPEED_ABILITY_M,
2697                                             HNS3_CFG_SPEED_ABILITY_S);
2698         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2699                                         HNS3_CFG_UMV_TBL_SPACE_M,
2700                                         HNS3_CFG_UMV_TBL_SPACE_S);
2701         if (!cfg->umv_space)
2702                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2703 }
2704
2705 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2706  * @hw: pointer to struct hns3_hw
2707  * @hcfg: the config structure to be getted
2708  */
2709 static int
2710 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2711 {
2712         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2713         struct hns3_cfg_param_cmd *req;
2714         uint32_t offset;
2715         uint32_t i;
2716         int ret;
2717
2718         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2719                 offset = 0;
2720                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2721                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2722                                           true);
2723                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2724                                i * HNS3_CFG_RD_LEN_BYTES);
2725                 /* Len should be divided by 4 when send to hardware */
2726                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2727                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2728                 req->offset = rte_cpu_to_le_32(offset);
2729         }
2730
2731         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2732         if (ret) {
2733                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2734                 return ret;
2735         }
2736
2737         hns3_parse_cfg(hcfg, desc);
2738
2739         return 0;
2740 }
2741
2742 static int
2743 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2744 {
2745         switch (speed_cmd) {
2746         case HNS3_CFG_SPEED_10M:
2747                 *speed = ETH_SPEED_NUM_10M;
2748                 break;
2749         case HNS3_CFG_SPEED_100M:
2750                 *speed = ETH_SPEED_NUM_100M;
2751                 break;
2752         case HNS3_CFG_SPEED_1G:
2753                 *speed = ETH_SPEED_NUM_1G;
2754                 break;
2755         case HNS3_CFG_SPEED_10G:
2756                 *speed = ETH_SPEED_NUM_10G;
2757                 break;
2758         case HNS3_CFG_SPEED_25G:
2759                 *speed = ETH_SPEED_NUM_25G;
2760                 break;
2761         case HNS3_CFG_SPEED_40G:
2762                 *speed = ETH_SPEED_NUM_40G;
2763                 break;
2764         case HNS3_CFG_SPEED_50G:
2765                 *speed = ETH_SPEED_NUM_50G;
2766                 break;
2767         case HNS3_CFG_SPEED_100G:
2768                 *speed = ETH_SPEED_NUM_100G;
2769                 break;
2770         default:
2771                 return -EINVAL;
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int
2778 hns3_get_board_configuration(struct hns3_hw *hw)
2779 {
2780         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2781         struct hns3_pf *pf = &hns->pf;
2782         struct hns3_cfg cfg;
2783         int ret;
2784
2785         ret = hns3_get_board_cfg(hw, &cfg);
2786         if (ret) {
2787                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2788                 return ret;
2789         }
2790
2791         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2792                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2793                 return -EOPNOTSUPP;
2794         }
2795
2796         hw->mac.media_type = cfg.media_type;
2797         hw->rss_size_max = cfg.rss_size_max;
2798         hw->rss_dis_flag = false;
2799         hw->rx_buf_len = cfg.rx_buf_len;
2800         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2801         hw->mac.phy_addr = cfg.phy_addr;
2802         hw->mac.default_addr_setted = false;
2803         hw->num_tx_desc = cfg.tqp_desc_num;
2804         hw->num_rx_desc = cfg.tqp_desc_num;
2805         hw->dcb_info.num_pg = 1;
2806         hw->dcb_info.hw_pfc_map = 0;
2807
2808         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2809         if (ret) {
2810                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2811                              cfg.default_speed, ret);
2812                 return ret;
2813         }
2814
2815         pf->tc_max = cfg.tc_num;
2816         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2817                 PMD_INIT_LOG(WARNING,
2818                              "Get TC num(%u) from flash, set TC num to 1",
2819                              pf->tc_max);
2820                 pf->tc_max = 1;
2821         }
2822
2823         /* Dev does not support DCB */
2824         if (!hns3_dev_dcb_supported(hw)) {
2825                 pf->tc_max = 1;
2826                 pf->pfc_max = 0;
2827         } else
2828                 pf->pfc_max = pf->tc_max;
2829
2830         hw->dcb_info.num_tc = 1;
2831         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2832                                      hw->tqps_num / hw->dcb_info.num_tc);
2833         hns3_set_bit(hw->hw_tc_map, 0, 1);
2834         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2835
2836         pf->wanted_umv_size = cfg.umv_space;
2837
2838         return ret;
2839 }
2840
2841 static int
2842 hns3_get_configuration(struct hns3_hw *hw)
2843 {
2844         int ret;
2845
2846         ret = hns3_query_function_status(hw);
2847         if (ret) {
2848                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2849                 return ret;
2850         }
2851
2852         /* Get pf resource */
2853         ret = hns3_query_pf_resource(hw);
2854         if (ret) {
2855                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2856                 return ret;
2857         }
2858
2859         ret = hns3_get_board_configuration(hw);
2860         if (ret)
2861                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2862
2863         return ret;
2864 }
2865
2866 static int
2867 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2868                       uint16_t tqp_vid, bool is_pf)
2869 {
2870         struct hns3_tqp_map_cmd *req;
2871         struct hns3_cmd_desc desc;
2872         int ret;
2873
2874         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2875
2876         req = (struct hns3_tqp_map_cmd *)desc.data;
2877         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2878         req->tqp_vf = func_id;
2879         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2880         if (!is_pf)
2881                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2882         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2883
2884         ret = hns3_cmd_send(hw, &desc, 1);
2885         if (ret)
2886                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2887
2888         return ret;
2889 }
2890
2891 static int
2892 hns3_map_tqp(struct hns3_hw *hw)
2893 {
2894         uint16_t tqps_num = hw->total_tqps_num;
2895         uint16_t func_id;
2896         uint16_t tqp_id;
2897         bool is_pf;
2898         int num;
2899         int ret;
2900         int i;
2901
2902         /*
2903          * In current version VF is not supported when PF is driven by DPDK
2904          * driver, so we allocate tqps to PF as much as possible.
2905          */
2906         tqp_id = 0;
2907         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2908         for (func_id = 0; func_id < num; func_id++) {
2909                 is_pf = func_id == 0 ? true : false;
2910                 for (i = 0;
2911                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2912                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2913                                                     is_pf);
2914                         if (ret)
2915                                 return ret;
2916                 }
2917         }
2918
2919         return 0;
2920 }
2921
2922 static int
2923 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2924 {
2925         struct hns3_config_mac_speed_dup_cmd *req;
2926         struct hns3_cmd_desc desc;
2927         int ret;
2928
2929         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2930
2931         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2932
2933         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2934
2935         switch (speed) {
2936         case ETH_SPEED_NUM_10M:
2937                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2938                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2939                 break;
2940         case ETH_SPEED_NUM_100M:
2941                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2942                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2943                 break;
2944         case ETH_SPEED_NUM_1G:
2945                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2946                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2947                 break;
2948         case ETH_SPEED_NUM_10G:
2949                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2950                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2951                 break;
2952         case ETH_SPEED_NUM_25G:
2953                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2954                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2955                 break;
2956         case ETH_SPEED_NUM_40G:
2957                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2958                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2959                 break;
2960         case ETH_SPEED_NUM_50G:
2961                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2962                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2963                 break;
2964         case ETH_SPEED_NUM_100G:
2965                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2966                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2967                 break;
2968         default:
2969                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2970                 return -EINVAL;
2971         }
2972
2973         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2974
2975         ret = hns3_cmd_send(hw, &desc, 1);
2976         if (ret)
2977                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2978
2979         return ret;
2980 }
2981
2982 static int
2983 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2984 {
2985         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2986         struct hns3_pf *pf = &hns->pf;
2987         struct hns3_priv_buf *priv;
2988         uint32_t i, total_size;
2989
2990         total_size = pf->pkt_buf_size;
2991
2992         /* alloc tx buffer for all enabled tc */
2993         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2994                 priv = &buf_alloc->priv_buf[i];
2995
2996                 if (hw->hw_tc_map & BIT(i)) {
2997                         if (total_size < pf->tx_buf_size)
2998                                 return -ENOMEM;
2999
3000                         priv->tx_buf_size = pf->tx_buf_size;
3001                 } else
3002                         priv->tx_buf_size = 0;
3003
3004                 total_size -= priv->tx_buf_size;
3005         }
3006
3007         return 0;
3008 }
3009
3010 static int
3011 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3012 {
3013 /* TX buffer size is unit by 128 byte */
3014 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3015 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3016         struct hns3_tx_buff_alloc_cmd *req;
3017         struct hns3_cmd_desc desc;
3018         uint32_t buf_size;
3019         uint32_t i;
3020         int ret;
3021
3022         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3023
3024         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3025         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3026                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3027
3028                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3029                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3030                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3031         }
3032
3033         ret = hns3_cmd_send(hw, &desc, 1);
3034         if (ret)
3035                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3036
3037         return ret;
3038 }
3039
3040 static int
3041 hns3_get_tc_num(struct hns3_hw *hw)
3042 {
3043         int cnt = 0;
3044         uint8_t i;
3045
3046         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3047                 if (hw->hw_tc_map & BIT(i))
3048                         cnt++;
3049         return cnt;
3050 }
3051
3052 static uint32_t
3053 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3054 {
3055         struct hns3_priv_buf *priv;
3056         uint32_t rx_priv = 0;
3057         int i;
3058
3059         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3060                 priv = &buf_alloc->priv_buf[i];
3061                 if (priv->enable)
3062                         rx_priv += priv->buf_size;
3063         }
3064         return rx_priv;
3065 }
3066
3067 static uint32_t
3068 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3069 {
3070         uint32_t total_tx_size = 0;
3071         uint32_t i;
3072
3073         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3074                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3075
3076         return total_tx_size;
3077 }
3078
3079 /* Get the number of pfc enabled TCs, which have private buffer */
3080 static int
3081 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3082 {
3083         struct hns3_priv_buf *priv;
3084         int cnt = 0;
3085         uint8_t i;
3086
3087         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3088                 priv = &buf_alloc->priv_buf[i];
3089                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3090                         cnt++;
3091         }
3092
3093         return cnt;
3094 }
3095
3096 /* Get the number of pfc disabled TCs, which have private buffer */
3097 static int
3098 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3099                          struct hns3_pkt_buf_alloc *buf_alloc)
3100 {
3101         struct hns3_priv_buf *priv;
3102         int cnt = 0;
3103         uint8_t i;
3104
3105         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3106                 priv = &buf_alloc->priv_buf[i];
3107                 if (hw->hw_tc_map & BIT(i) &&
3108                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3109                         cnt++;
3110         }
3111
3112         return cnt;
3113 }
3114
3115 static bool
3116 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3117                   uint32_t rx_all)
3118 {
3119         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3120         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3121         struct hns3_pf *pf = &hns->pf;
3122         uint32_t shared_buf, aligned_mps;
3123         uint32_t rx_priv;
3124         uint8_t tc_num;
3125         uint8_t i;
3126
3127         tc_num = hns3_get_tc_num(hw);
3128         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3129
3130         if (hns3_dev_dcb_supported(hw))
3131                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3132                                         pf->dv_buf_size;
3133         else
3134                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3135                                         + pf->dv_buf_size;
3136
3137         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3138         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3139                              HNS3_BUF_SIZE_UNIT);
3140
3141         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3142         if (rx_all < rx_priv + shared_std)
3143                 return false;
3144
3145         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3146         buf_alloc->s_buf.buf_size = shared_buf;
3147         if (hns3_dev_dcb_supported(hw)) {
3148                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3149                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3150                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3151                                   HNS3_BUF_SIZE_UNIT);
3152         } else {
3153                 buf_alloc->s_buf.self.high =
3154                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3155                 buf_alloc->s_buf.self.low = aligned_mps;
3156         }
3157
3158         if (hns3_dev_dcb_supported(hw)) {
3159                 hi_thrd = shared_buf - pf->dv_buf_size;
3160
3161                 if (tc_num <= NEED_RESERVE_TC_NUM)
3162                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3163                                         / BUF_MAX_PERCENT;
3164
3165                 if (tc_num)
3166                         hi_thrd = hi_thrd / tc_num;
3167
3168                 hi_thrd = max_t(uint32_t, hi_thrd,
3169                                 HNS3_BUF_MUL_BY * aligned_mps);
3170                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3171                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3172         } else {
3173                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3174                 lo_thrd = aligned_mps;
3175         }
3176
3177         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3178                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3179                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3180         }
3181
3182         return true;
3183 }
3184
3185 static bool
3186 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3187                      struct hns3_pkt_buf_alloc *buf_alloc)
3188 {
3189         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3190         struct hns3_pf *pf = &hns->pf;
3191         struct hns3_priv_buf *priv;
3192         uint32_t aligned_mps;
3193         uint32_t rx_all;
3194         uint8_t i;
3195
3196         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3197         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3198
3199         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3200                 priv = &buf_alloc->priv_buf[i];
3201
3202                 priv->enable = 0;
3203                 priv->wl.low = 0;
3204                 priv->wl.high = 0;
3205                 priv->buf_size = 0;
3206
3207                 if (!(hw->hw_tc_map & BIT(i)))
3208                         continue;
3209
3210                 priv->enable = 1;
3211                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3212                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3213                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3214                                                 HNS3_BUF_SIZE_UNIT);
3215                 } else {
3216                         priv->wl.low = 0;
3217                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3218                                         aligned_mps;
3219                 }
3220
3221                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3222         }
3223
3224         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3225 }
3226
3227 static bool
3228 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3229                              struct hns3_pkt_buf_alloc *buf_alloc)
3230 {
3231         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3232         struct hns3_pf *pf = &hns->pf;
3233         struct hns3_priv_buf *priv;
3234         int no_pfc_priv_num;
3235         uint32_t rx_all;
3236         uint8_t mask;
3237         int i;
3238
3239         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3240         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3241
3242         /* let the last to be cleared first */
3243         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3244                 priv = &buf_alloc->priv_buf[i];
3245                 mask = BIT((uint8_t)i);
3246
3247                 if (hw->hw_tc_map & mask &&
3248                     !(hw->dcb_info.hw_pfc_map & mask)) {
3249                         /* Clear the no pfc TC private buffer */
3250                         priv->wl.low = 0;
3251                         priv->wl.high = 0;
3252                         priv->buf_size = 0;
3253                         priv->enable = 0;
3254                         no_pfc_priv_num--;
3255                 }
3256
3257                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3258                     no_pfc_priv_num == 0)
3259                         break;
3260         }
3261
3262         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3263 }
3264
3265 static bool
3266 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3267                            struct hns3_pkt_buf_alloc *buf_alloc)
3268 {
3269         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3270         struct hns3_pf *pf = &hns->pf;
3271         struct hns3_priv_buf *priv;
3272         uint32_t rx_all;
3273         int pfc_priv_num;
3274         uint8_t mask;
3275         int i;
3276
3277         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3278         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3279
3280         /* let the last to be cleared first */
3281         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3282                 priv = &buf_alloc->priv_buf[i];
3283                 mask = BIT((uint8_t)i);
3284
3285                 if (hw->hw_tc_map & mask &&
3286                     hw->dcb_info.hw_pfc_map & mask) {
3287                         /* Reduce the number of pfc TC with private buffer */
3288                         priv->wl.low = 0;
3289                         priv->enable = 0;
3290                         priv->wl.high = 0;
3291                         priv->buf_size = 0;
3292                         pfc_priv_num--;
3293                 }
3294                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3295                     pfc_priv_num == 0)
3296                         break;
3297         }
3298
3299         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3300 }
3301
3302 static bool
3303 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3304                           struct hns3_pkt_buf_alloc *buf_alloc)
3305 {
3306 #define COMPENSATE_BUFFER       0x3C00
3307 #define COMPENSATE_HALF_MPS_NUM 5
3308 #define PRIV_WL_GAP             0x1800
3309         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3310         struct hns3_pf *pf = &hns->pf;
3311         uint32_t tc_num = hns3_get_tc_num(hw);
3312         uint32_t half_mps = pf->mps >> 1;
3313         struct hns3_priv_buf *priv;
3314         uint32_t min_rx_priv;
3315         uint32_t rx_priv;
3316         uint8_t i;
3317
3318         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3319         if (tc_num)
3320                 rx_priv = rx_priv / tc_num;
3321
3322         if (tc_num <= NEED_RESERVE_TC_NUM)
3323                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3324
3325         /*
3326          * Minimum value of private buffer in rx direction (min_rx_priv) is
3327          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3328          * buffer if rx_priv is greater than min_rx_priv.
3329          */
3330         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3331                         COMPENSATE_HALF_MPS_NUM * half_mps;
3332         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3333         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3334
3335         if (rx_priv < min_rx_priv)
3336                 return false;
3337
3338         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3339                 priv = &buf_alloc->priv_buf[i];
3340
3341                 priv->enable = 0;
3342                 priv->wl.low = 0;
3343                 priv->wl.high = 0;
3344                 priv->buf_size = 0;
3345
3346                 if (!(hw->hw_tc_map & BIT(i)))
3347                         continue;
3348
3349                 priv->enable = 1;
3350                 priv->buf_size = rx_priv;
3351                 priv->wl.high = rx_priv - pf->dv_buf_size;
3352                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3353         }
3354
3355         buf_alloc->s_buf.buf_size = 0;
3356
3357         return true;
3358 }
3359
3360 /*
3361  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3362  * @hw: pointer to struct hns3_hw
3363  * @buf_alloc: pointer to buffer calculation data
3364  * @return: 0: calculate sucessful, negative: fail
3365  */
3366 static int
3367 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3368 {
3369         /* When DCB is not supported, rx private buffer is not allocated. */
3370         if (!hns3_dev_dcb_supported(hw)) {
3371                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3372                 struct hns3_pf *pf = &hns->pf;
3373                 uint32_t rx_all = pf->pkt_buf_size;
3374
3375                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3376                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3377                         return -ENOMEM;
3378
3379                 return 0;
3380         }
3381
3382         /*
3383          * Try to allocate privated packet buffer for all TCs without share
3384          * buffer.
3385          */
3386         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3387                 return 0;
3388
3389         /*
3390          * Try to allocate privated packet buffer for all TCs with share
3391          * buffer.
3392          */
3393         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3394                 return 0;
3395
3396         /*
3397          * For different application scenes, the enabled port number, TC number
3398          * and no_drop TC number are different. In order to obtain the better
3399          * performance, software could allocate the buffer size and configure
3400          * the waterline by tring to decrease the private buffer size according
3401          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3402          * enabled tc.
3403          */
3404         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3405                 return 0;
3406
3407         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3408                 return 0;
3409
3410         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3411                 return 0;
3412
3413         return -ENOMEM;
3414 }
3415
3416 static int
3417 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3418 {
3419         struct hns3_rx_priv_buff_cmd *req;
3420         struct hns3_cmd_desc desc;
3421         uint32_t buf_size;
3422         int ret;
3423         int i;
3424
3425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3426         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3427
3428         /* Alloc private buffer TCs */
3429         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3430                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3431
3432                 req->buf_num[i] =
3433                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3434                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3435         }
3436
3437         buf_size = buf_alloc->s_buf.buf_size;
3438         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3439                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3440
3441         ret = hns3_cmd_send(hw, &desc, 1);
3442         if (ret)
3443                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3444
3445         return ret;
3446 }
3447
3448 static int
3449 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3450 {
3451 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3452         struct hns3_rx_priv_wl_buf *req;
3453         struct hns3_priv_buf *priv;
3454         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3455         int i, j;
3456         int ret;
3457
3458         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3459                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3460                                           false);
3461                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3462
3463                 /* The first descriptor set the NEXT bit to 1 */
3464                 if (i == 0)
3465                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3466                 else
3467                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3468
3469                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3470                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3471
3472                         priv = &buf_alloc->priv_buf[idx];
3473                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3474                                                         HNS3_BUF_UNIT_S);
3475                         req->tc_wl[j].high |=
3476                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3477                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3478                                                         HNS3_BUF_UNIT_S);
3479                         req->tc_wl[j].low |=
3480                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3481                 }
3482         }
3483
3484         /* Send 2 descriptor at one time */
3485         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3486         if (ret)
3487                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3488                              ret);
3489         return ret;
3490 }
3491
3492 static int
3493 hns3_common_thrd_config(struct hns3_hw *hw,
3494                         struct hns3_pkt_buf_alloc *buf_alloc)
3495 {
3496 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3497         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3498         struct hns3_rx_com_thrd *req;
3499         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3500         struct hns3_tc_thrd *tc;
3501         int tc_idx;
3502         int i, j;
3503         int ret;
3504
3505         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3506                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3507                                           false);
3508                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3509
3510                 /* The first descriptor set the NEXT bit to 1 */
3511                 if (i == 0)
3512                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3513                 else
3514                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3515
3516                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3517                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3518                         tc = &s_buf->tc_thrd[tc_idx];
3519
3520                         req->com_thrd[j].high =
3521                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3522                         req->com_thrd[j].high |=
3523                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3524                         req->com_thrd[j].low =
3525                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3526                         req->com_thrd[j].low |=
3527                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3528                 }
3529         }
3530
3531         /* Send 2 descriptors at one time */
3532         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3533         if (ret)
3534                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3535
3536         return ret;
3537 }
3538
3539 static int
3540 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3541 {
3542         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3543         struct hns3_rx_com_wl *req;
3544         struct hns3_cmd_desc desc;
3545         int ret;
3546
3547         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3548
3549         req = (struct hns3_rx_com_wl *)desc.data;
3550         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3551         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3552
3553         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3554         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3555
3556         ret = hns3_cmd_send(hw, &desc, 1);
3557         if (ret)
3558                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3559
3560         return ret;
3561 }
3562
3563 int
3564 hns3_buffer_alloc(struct hns3_hw *hw)
3565 {
3566         struct hns3_pkt_buf_alloc pkt_buf;
3567         int ret;
3568
3569         memset(&pkt_buf, 0, sizeof(pkt_buf));
3570         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3571         if (ret) {
3572                 PMD_INIT_LOG(ERR,
3573                              "could not calc tx buffer size for all TCs %d",
3574                              ret);
3575                 return ret;
3576         }
3577
3578         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3579         if (ret) {
3580                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3581                 return ret;
3582         }
3583
3584         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3585         if (ret) {
3586                 PMD_INIT_LOG(ERR,
3587                              "could not calc rx priv buffer size for all TCs %d",
3588                              ret);
3589                 return ret;
3590         }
3591
3592         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3593         if (ret) {
3594                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3595                 return ret;
3596         }
3597
3598         if (hns3_dev_dcb_supported(hw)) {
3599                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3600                 if (ret) {
3601                         PMD_INIT_LOG(ERR,
3602                                      "could not configure rx private waterline %d",
3603                                      ret);
3604                         return ret;
3605                 }
3606
3607                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3608                 if (ret) {
3609                         PMD_INIT_LOG(ERR,
3610                                      "could not configure common threshold %d",
3611                                      ret);
3612                         return ret;
3613                 }
3614         }
3615
3616         ret = hns3_common_wl_config(hw, &pkt_buf);
3617         if (ret)
3618                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3619                              ret);
3620
3621         return ret;
3622 }
3623
3624 static int
3625 hns3_mac_init(struct hns3_hw *hw)
3626 {
3627         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3628         struct hns3_mac *mac = &hw->mac;
3629         struct hns3_pf *pf = &hns->pf;
3630         int ret;
3631
3632         pf->support_sfp_query = true;
3633         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3634         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3635         if (ret) {
3636                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3637                 return ret;
3638         }
3639
3640         mac->link_status = ETH_LINK_DOWN;
3641
3642         return hns3_config_mtu(hw, pf->mps);
3643 }
3644
3645 static int
3646 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3647 {
3648 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3649 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3650 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3651 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3652         int return_status;
3653
3654         if (cmdq_resp) {
3655                 PMD_INIT_LOG(ERR,
3656                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3657                              cmdq_resp);
3658                 return -EIO;
3659         }
3660
3661         switch (resp_code) {
3662         case HNS3_ETHERTYPE_SUCCESS_ADD:
3663         case HNS3_ETHERTYPE_ALREADY_ADD:
3664                 return_status = 0;
3665                 break;
3666         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3667                 PMD_INIT_LOG(ERR,
3668                              "add mac ethertype failed for manager table overflow.");
3669                 return_status = -EIO;
3670                 break;
3671         case HNS3_ETHERTYPE_KEY_CONFLICT:
3672                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3673                 return_status = -EIO;
3674                 break;
3675         default:
3676                 PMD_INIT_LOG(ERR,
3677                              "add mac ethertype failed for undefined, code=%d.",
3678                              resp_code);
3679                 return_status = -EIO;
3680                 break;
3681         }
3682
3683         return return_status;
3684 }
3685
3686 static int
3687 hns3_add_mgr_tbl(struct hns3_hw *hw,
3688                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3689 {
3690         struct hns3_cmd_desc desc;
3691         uint8_t resp_code;
3692         uint16_t retval;
3693         int ret;
3694
3695         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3696         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3697
3698         ret = hns3_cmd_send(hw, &desc, 1);
3699         if (ret) {
3700                 PMD_INIT_LOG(ERR,
3701                              "add mac ethertype failed for cmd_send, ret =%d.",
3702                              ret);
3703                 return ret;
3704         }
3705
3706         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3707         retval = rte_le_to_cpu_16(desc.retval);
3708
3709         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3710 }
3711
3712 static void
3713 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3714                      int *table_item_num)
3715 {
3716         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3717
3718         /*
3719          * In current version, we add one item in management table as below:
3720          * 0x0180C200000E -- LLDP MC address
3721          */
3722         tbl = mgr_table;
3723         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3724         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3725         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3726         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3727         tbl->i_port_bitmap = 0x1;
3728         *table_item_num = 1;
3729 }
3730
3731 static int
3732 hns3_init_mgr_tbl(struct hns3_hw *hw)
3733 {
3734 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3735         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3736         int table_item_num;
3737         int ret;
3738         int i;
3739
3740         memset(mgr_table, 0, sizeof(mgr_table));
3741         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3742         for (i = 0; i < table_item_num; i++) {
3743                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3744                 if (ret) {
3745                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3746                                      ret);
3747                         return ret;
3748                 }
3749         }
3750
3751         return 0;
3752 }
3753
3754 static void
3755 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3756                         bool en_mc, bool en_bc, int vport_id)
3757 {
3758         if (!param)
3759                 return;
3760
3761         memset(param, 0, sizeof(struct hns3_promisc_param));
3762         if (en_uc)
3763                 param->enable = HNS3_PROMISC_EN_UC;
3764         if (en_mc)
3765                 param->enable |= HNS3_PROMISC_EN_MC;
3766         if (en_bc)
3767                 param->enable |= HNS3_PROMISC_EN_BC;
3768         param->vf_id = vport_id;
3769 }
3770
3771 static int
3772 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3773 {
3774         struct hns3_promisc_cfg_cmd *req;
3775         struct hns3_cmd_desc desc;
3776         int ret;
3777
3778         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3779
3780         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3781         req->vf_id = param->vf_id;
3782         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3783             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3784
3785         ret = hns3_cmd_send(hw, &desc, 1);
3786         if (ret)
3787                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3788
3789         return ret;
3790 }
3791
3792 static int
3793 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3794 {
3795         struct hns3_promisc_param param;
3796         bool en_bc_pmc = true;
3797         uint8_t vf_id;
3798
3799         /*
3800          * In current version VF is not supported when PF is driven by DPDK
3801          * driver, the PF-related vf_id is 0, just need to configure parameters
3802          * for vf_id 0.
3803          */
3804         vf_id = 0;
3805
3806         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3807         return hns3_cmd_set_promisc_mode(hw, &param);
3808 }
3809
3810 static int
3811 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3812 {
3813         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3814         struct hns3_pf *pf = &hns->pf;
3815         struct hns3_promisc_param param;
3816         uint16_t func_id;
3817         int ret;
3818
3819         /* func_id 0 is denoted PF, the VFs start from 1 */
3820         for (func_id = 1; func_id < pf->func_num; func_id++) {
3821                 hns3_promisc_param_init(&param, false, false, false, func_id);
3822                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3823                 if (ret)
3824                         return ret;
3825         }
3826
3827         return 0;
3828 }
3829
3830 static int
3831 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3832 {
3833         struct hns3_adapter *hns = dev->data->dev_private;
3834         struct hns3_hw *hw = &hns->hw;
3835         int ret;
3836
3837         rte_spinlock_lock(&hw->lock);
3838         ret = hns3_set_promisc_mode(hw, true, true);
3839         rte_spinlock_unlock(&hw->lock);
3840         if (ret)
3841                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3842                          ret);
3843
3844         return ret;
3845 }
3846
3847 static int
3848 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3849 {
3850         bool allmulti = dev->data->all_multicast ? true : false;
3851         struct hns3_adapter *hns = dev->data->dev_private;
3852         struct hns3_hw *hw = &hns->hw;
3853         int ret;
3854
3855         /* If now in all_multicast mode, must remain in all_multicast mode. */
3856         rte_spinlock_lock(&hw->lock);
3857         ret = hns3_set_promisc_mode(hw, false, allmulti);
3858         rte_spinlock_unlock(&hw->lock);
3859         if (ret)
3860                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3861                          ret);
3862
3863         return ret;
3864 }
3865
3866 static int
3867 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3868 {
3869         struct hns3_adapter *hns = dev->data->dev_private;
3870         struct hns3_hw *hw = &hns->hw;
3871         int ret;
3872
3873         if (dev->data->promiscuous)
3874                 return 0;
3875
3876         rte_spinlock_lock(&hw->lock);
3877         ret = hns3_set_promisc_mode(hw, false, true);
3878         rte_spinlock_unlock(&hw->lock);
3879         if (ret)
3880                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3881                          ret);
3882
3883         return ret;
3884 }
3885
3886 static int
3887 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3888 {
3889         struct hns3_adapter *hns = dev->data->dev_private;
3890         struct hns3_hw *hw = &hns->hw;
3891         int ret;
3892
3893         /* If now in promiscuous mode, must remain in all_multicast mode. */
3894         if (dev->data->promiscuous)
3895                 return 0;
3896
3897         rte_spinlock_lock(&hw->lock);
3898         ret = hns3_set_promisc_mode(hw, false, false);
3899         rte_spinlock_unlock(&hw->lock);
3900         if (ret)
3901                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3902                          ret);
3903
3904         return ret;
3905 }
3906
3907 static int
3908 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3909 {
3910         struct hns3_hw *hw = &hns->hw;
3911         bool allmulti = hw->data->all_multicast ? true : false;
3912
3913         if (hw->data->promiscuous)
3914                 return hns3_set_promisc_mode(hw, true, true);
3915
3916         return hns3_set_promisc_mode(hw, false, allmulti);
3917 }
3918
3919 static int
3920 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3921 {
3922         struct hns3_sfp_speed_cmd *resp;
3923         struct hns3_cmd_desc desc;
3924         int ret;
3925
3926         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3927         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3928         ret = hns3_cmd_send(hw, &desc, 1);
3929         if (ret == -EOPNOTSUPP) {
3930                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3931                 return ret;
3932         } else if (ret) {
3933                 hns3_err(hw, "get sfp speed failed %d", ret);
3934                 return ret;
3935         }
3936
3937         *speed = resp->sfp_speed;
3938
3939         return 0;
3940 }
3941
3942 static uint8_t
3943 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3944 {
3945         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3946                 duplex = ETH_LINK_FULL_DUPLEX;
3947
3948         return duplex;
3949 }
3950
3951 static int
3952 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3953 {
3954         struct hns3_mac *mac = &hw->mac;
3955         int ret;
3956
3957         duplex = hns3_check_speed_dup(duplex, speed);
3958         if (mac->link_speed == speed && mac->link_duplex == duplex)
3959                 return 0;
3960
3961         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3962         if (ret)
3963                 return ret;
3964
3965         mac->link_speed = speed;
3966         mac->link_duplex = duplex;
3967
3968         return 0;
3969 }
3970
3971 static int
3972 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3973 {
3974         struct hns3_adapter *hns = eth_dev->data->dev_private;
3975         struct hns3_hw *hw = &hns->hw;
3976         struct hns3_pf *pf = &hns->pf;
3977         uint32_t speed;
3978         int ret;
3979
3980         /* If IMP do not support get SFP/qSFP speed, return directly */
3981         if (!pf->support_sfp_query)
3982                 return 0;
3983
3984         ret = hns3_get_sfp_speed(hw, &speed);
3985         if (ret == -EOPNOTSUPP) {
3986                 pf->support_sfp_query = false;
3987                 return ret;
3988         } else if (ret)
3989                 return ret;
3990
3991         if (speed == ETH_SPEED_NUM_NONE)
3992                 return 0; /* do nothing if no SFP */
3993
3994         /* Config full duplex for SFP */
3995         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3996 }
3997
3998 static int
3999 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4000 {
4001         struct hns3_config_mac_mode_cmd *req;
4002         struct hns3_cmd_desc desc;
4003         uint32_t loop_en = 0;
4004         uint8_t val = 0;
4005         int ret;
4006
4007         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4008
4009         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4010         if (enable)
4011                 val = 1;
4012         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4013         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4014         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4015         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4016         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4017         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4018         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4019         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4020         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4021         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4022         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4023         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4024         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4025         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4026         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4027
4028         ret = hns3_cmd_send(hw, &desc, 1);
4029         if (ret)
4030                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4031
4032         return ret;
4033 }
4034
4035 static int
4036 hns3_get_mac_link_status(struct hns3_hw *hw)
4037 {
4038         struct hns3_link_status_cmd *req;
4039         struct hns3_cmd_desc desc;
4040         int link_status;
4041         int ret;
4042
4043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4044         ret = hns3_cmd_send(hw, &desc, 1);
4045         if (ret) {
4046                 hns3_err(hw, "get link status cmd failed %d", ret);
4047                 return ETH_LINK_DOWN;
4048         }
4049
4050         req = (struct hns3_link_status_cmd *)desc.data;
4051         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4052
4053         return !!link_status;
4054 }
4055
4056 void
4057 hns3_update_link_status(struct hns3_hw *hw)
4058 {
4059         int state;
4060
4061         state = hns3_get_mac_link_status(hw);
4062         if (state != hw->mac.link_status) {
4063                 hw->mac.link_status = state;
4064                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4065         }
4066 }
4067
4068 static void
4069 hns3_service_handler(void *param)
4070 {
4071         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4072         struct hns3_adapter *hns = eth_dev->data->dev_private;
4073         struct hns3_hw *hw = &hns->hw;
4074
4075         if (!hns3_is_reset_pending(hns)) {
4076                 hns3_update_speed_duplex(eth_dev);
4077                 hns3_update_link_status(hw);
4078         } else
4079                 hns3_warn(hw, "Cancel the query when reset is pending");
4080
4081         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4082 }
4083
4084 static int
4085 hns3_init_hardware(struct hns3_adapter *hns)
4086 {
4087         struct hns3_hw *hw = &hns->hw;
4088         int ret;
4089
4090         ret = hns3_map_tqp(hw);
4091         if (ret) {
4092                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4093                 return ret;
4094         }
4095
4096         ret = hns3_init_umv_space(hw);
4097         if (ret) {
4098                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4099                 return ret;
4100         }
4101
4102         ret = hns3_mac_init(hw);
4103         if (ret) {
4104                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4105                 goto err_mac_init;
4106         }
4107
4108         ret = hns3_init_mgr_tbl(hw);
4109         if (ret) {
4110                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4111                 goto err_mac_init;
4112         }
4113
4114         ret = hns3_set_promisc_mode(hw, false, false);
4115         if (ret) {
4116                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4117                 goto err_mac_init;
4118         }
4119
4120         ret = hns3_clear_all_vfs_promisc_mode(hw);
4121         if (ret) {
4122                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4123                              ret);
4124                 goto err_mac_init;
4125         }
4126
4127         ret = hns3_init_vlan_config(hns);
4128         if (ret) {
4129                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4130                 goto err_mac_init;
4131         }
4132
4133         ret = hns3_dcb_init(hw);
4134         if (ret) {
4135                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4136                 goto err_mac_init;
4137         }
4138
4139         ret = hns3_init_fd_config(hns);
4140         if (ret) {
4141                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4142                 goto err_mac_init;
4143         }
4144
4145         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4146         if (ret) {
4147                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4148                 goto err_mac_init;
4149         }
4150
4151         ret = hns3_config_gro(hw, false);
4152         if (ret) {
4153                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4154                 goto err_mac_init;
4155         }
4156
4157         /*
4158          * In the initialization clearing the all hardware mapping relationship
4159          * configurations between queues and interrupt vectors is needed, so
4160          * some error caused by the residual configurations, such as the
4161          * unexpected interrupt, can be avoid.
4162          */
4163         ret = hns3_init_ring_with_vector(hw);
4164         if (ret) {
4165                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4166                 goto err_mac_init;
4167         }
4168
4169         return 0;
4170
4171 err_mac_init:
4172         hns3_uninit_umv_space(hw);
4173         return ret;
4174 }
4175
4176 static int
4177 hns3_init_pf(struct rte_eth_dev *eth_dev)
4178 {
4179         struct rte_device *dev = eth_dev->device;
4180         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4181         struct hns3_adapter *hns = eth_dev->data->dev_private;
4182         struct hns3_hw *hw = &hns->hw;
4183         int ret;
4184
4185         PMD_INIT_FUNC_TRACE();
4186
4187         /* Get hardware io base address from pcie BAR2 IO space */
4188         hw->io_base = pci_dev->mem_resource[2].addr;
4189
4190         /* Firmware command queue initialize */
4191         ret = hns3_cmd_init_queue(hw);
4192         if (ret) {
4193                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4194                 goto err_cmd_init_queue;
4195         }
4196
4197         hns3_clear_all_event_cause(hw);
4198
4199         /* Firmware command initialize */
4200         ret = hns3_cmd_init(hw);
4201         if (ret) {
4202                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4203                 goto err_cmd_init;
4204         }
4205
4206         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4207                                          hns3_interrupt_handler,
4208                                          eth_dev);
4209         if (ret) {
4210                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4211                 goto err_intr_callback_register;
4212         }
4213
4214         /* Enable interrupt */
4215         rte_intr_enable(&pci_dev->intr_handle);
4216         hns3_pf_enable_irq0(hw);
4217
4218         /* Get configuration */
4219         ret = hns3_get_configuration(hw);
4220         if (ret) {
4221                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4222                 goto err_get_config;
4223         }
4224
4225         ret = hns3_init_hardware(hns);
4226         if (ret) {
4227                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4228                 goto err_get_config;
4229         }
4230
4231         /* Initialize flow director filter list & hash */
4232         ret = hns3_fdir_filter_init(hns);
4233         if (ret) {
4234                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4235                 goto err_hw_init;
4236         }
4237
4238         hns3_set_default_rss_args(hw);
4239
4240         ret = hns3_enable_hw_error_intr(hns, true);
4241         if (ret) {
4242                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4243                              ret);
4244                 goto err_fdir;
4245         }
4246
4247         return 0;
4248
4249 err_fdir:
4250         hns3_fdir_filter_uninit(hns);
4251 err_hw_init:
4252         hns3_uninit_umv_space(hw);
4253
4254 err_get_config:
4255         hns3_pf_disable_irq0(hw);
4256         rte_intr_disable(&pci_dev->intr_handle);
4257         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4258                              eth_dev);
4259 err_intr_callback_register:
4260 err_cmd_init:
4261         hns3_cmd_uninit(hw);
4262         hns3_cmd_destroy_queue(hw);
4263 err_cmd_init_queue:
4264         hw->io_base = NULL;
4265
4266         return ret;
4267 }
4268
4269 static void
4270 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4271 {
4272         struct hns3_adapter *hns = eth_dev->data->dev_private;
4273         struct rte_device *dev = eth_dev->device;
4274         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4275         struct hns3_hw *hw = &hns->hw;
4276
4277         PMD_INIT_FUNC_TRACE();
4278
4279         hns3_enable_hw_error_intr(hns, false);
4280         hns3_rss_uninit(hns);
4281         hns3_fdir_filter_uninit(hns);
4282         hns3_uninit_umv_space(hw);
4283         hns3_pf_disable_irq0(hw);
4284         rte_intr_disable(&pci_dev->intr_handle);
4285         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4286                              eth_dev);
4287         hns3_cmd_uninit(hw);
4288         hns3_cmd_destroy_queue(hw);
4289         hw->io_base = NULL;
4290 }
4291
4292 static int
4293 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4294 {
4295         struct hns3_hw *hw = &hns->hw;
4296         int ret;
4297
4298         ret = hns3_dcb_cfg_update(hns);
4299         if (ret)
4300                 return ret;
4301
4302         /* Enable queues */
4303         ret = hns3_start_queues(hns, reset_queue);
4304         if (ret) {
4305                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4306                 return ret;
4307         }
4308
4309         /* Enable MAC */
4310         ret = hns3_cfg_mac_mode(hw, true);
4311         if (ret) {
4312                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4313                 goto err_config_mac_mode;
4314         }
4315         return 0;
4316
4317 err_config_mac_mode:
4318         hns3_stop_queues(hns, true);
4319         return ret;
4320 }
4321
4322 static int
4323 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4324 {
4325         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4326         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4327         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4329         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4330         uint32_t intr_vector;
4331         uint16_t q_id;
4332         int ret;
4333
4334         if (dev->data->dev_conf.intr_conf.rxq == 0)
4335                 return 0;
4336
4337         /* disable uio/vfio intr/eventfd mapping */
4338         rte_intr_disable(intr_handle);
4339
4340         /* check and configure queue intr-vector mapping */
4341         if (rte_intr_cap_multiple(intr_handle) ||
4342             !RTE_ETH_DEV_SRIOV(dev).active) {
4343                 intr_vector = hw->used_rx_queues;
4344                 /* creates event fd for each intr vector when MSIX is used */
4345                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4346                         return -EINVAL;
4347         }
4348         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4349                 intr_handle->intr_vec =
4350                         rte_zmalloc("intr_vec",
4351                                     hw->used_rx_queues * sizeof(int), 0);
4352                 if (intr_handle->intr_vec == NULL) {
4353                         hns3_err(hw, "Failed to allocate %d rx_queues"
4354                                      " intr_vec", hw->used_rx_queues);
4355                         ret = -ENOMEM;
4356                         goto alloc_intr_vec_error;
4357                 }
4358         }
4359
4360         if (rte_intr_allow_others(intr_handle)) {
4361                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4362                 base = RTE_INTR_VEC_RXTX_OFFSET;
4363         }
4364         if (rte_intr_dp_is_en(intr_handle)) {
4365                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4366                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4367                                                          HNS3_RING_TYPE_RX,
4368                                                          q_id);
4369                         if (ret)
4370                                 goto bind_vector_error;
4371                         intr_handle->intr_vec[q_id] = vec;
4372                         if (vec < base + intr_handle->nb_efd - 1)
4373                                 vec++;
4374                 }
4375         }
4376         rte_intr_enable(intr_handle);
4377         return 0;
4378
4379 bind_vector_error:
4380         rte_intr_efd_disable(intr_handle);
4381         if (intr_handle->intr_vec) {
4382                 free(intr_handle->intr_vec);
4383                 intr_handle->intr_vec = NULL;
4384         }
4385         return ret;
4386 alloc_intr_vec_error:
4387         rte_intr_efd_disable(intr_handle);
4388         return ret;
4389 }
4390
4391 static int
4392 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4393 {
4394         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4395         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4397         uint16_t q_id;
4398         int ret;
4399
4400         if (dev->data->dev_conf.intr_conf.rxq == 0)
4401                 return 0;
4402
4403         if (rte_intr_dp_is_en(intr_handle)) {
4404                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4405                         ret = hns3_bind_ring_with_vector(hw,
4406                                         intr_handle->intr_vec[q_id], true,
4407                                         HNS3_RING_TYPE_RX, q_id);
4408                         if (ret)
4409                                 return ret;
4410                 }
4411         }
4412
4413         return 0;
4414 }
4415
4416 static void
4417 hns3_restore_filter(struct rte_eth_dev *dev)
4418 {
4419         hns3_restore_rss_filter(dev);
4420 }
4421
4422 static int
4423 hns3_dev_start(struct rte_eth_dev *dev)
4424 {
4425         struct hns3_adapter *hns = dev->data->dev_private;
4426         struct hns3_hw *hw = &hns->hw;
4427         int ret;
4428
4429         PMD_INIT_FUNC_TRACE();
4430         if (rte_atomic16_read(&hw->reset.resetting))
4431                 return -EBUSY;
4432
4433         rte_spinlock_lock(&hw->lock);
4434         hw->adapter_state = HNS3_NIC_STARTING;
4435
4436         ret = hns3_do_start(hns, true);
4437         if (ret) {
4438                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4439                 rte_spinlock_unlock(&hw->lock);
4440                 return ret;
4441         }
4442         ret = hns3_map_rx_interrupt(dev);
4443         if (ret) {
4444                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4445                 rte_spinlock_unlock(&hw->lock);
4446                 return ret;
4447         }
4448
4449         hw->adapter_state = HNS3_NIC_STARTED;
4450         rte_spinlock_unlock(&hw->lock);
4451
4452         hns3_set_rxtx_function(dev);
4453         hns3_mp_req_start_rxtx(dev);
4454         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4455
4456         hns3_restore_filter(dev);
4457
4458         /* Enable interrupt of all rx queues before enabling queues */
4459         hns3_dev_all_rx_queue_intr_enable(hw, true);
4460         /*
4461          * When finished the initialization, enable queues to receive/transmit
4462          * packets.
4463          */
4464         hns3_enable_all_queues(hw, true);
4465
4466         hns3_info(hw, "hns3 dev start successful!");
4467         return 0;
4468 }
4469
4470 static int
4471 hns3_do_stop(struct hns3_adapter *hns)
4472 {
4473         struct hns3_hw *hw = &hns->hw;
4474         bool reset_queue;
4475         int ret;
4476
4477         ret = hns3_cfg_mac_mode(hw, false);
4478         if (ret)
4479                 return ret;
4480         hw->mac.link_status = ETH_LINK_DOWN;
4481
4482         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4483                 hns3_configure_all_mac_addr(hns, true);
4484                 reset_queue = true;
4485         } else
4486                 reset_queue = false;
4487         hw->mac.default_addr_setted = false;
4488         return hns3_stop_queues(hns, reset_queue);
4489 }
4490
4491 static void
4492 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4493 {
4494         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4495         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4496         struct hns3_adapter *hns = dev->data->dev_private;
4497         struct hns3_hw *hw = &hns->hw;
4498         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4499         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4500         uint16_t q_id;
4501
4502         if (dev->data->dev_conf.intr_conf.rxq == 0)
4503                 return;
4504
4505         /* unmap the ring with vector */
4506         if (rte_intr_allow_others(intr_handle)) {
4507                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4508                 base = RTE_INTR_VEC_RXTX_OFFSET;
4509         }
4510         if (rte_intr_dp_is_en(intr_handle)) {
4511                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4512                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4513                                                          HNS3_RING_TYPE_RX,
4514                                                          q_id);
4515                         if (vec < base + intr_handle->nb_efd - 1)
4516                                 vec++;
4517                 }
4518         }
4519         /* Clean datapath event and queue/vec mapping */
4520         rte_intr_efd_disable(intr_handle);
4521         if (intr_handle->intr_vec) {
4522                 rte_free(intr_handle->intr_vec);
4523                 intr_handle->intr_vec = NULL;
4524         }
4525 }
4526
4527 static void
4528 hns3_dev_stop(struct rte_eth_dev *dev)
4529 {
4530         struct hns3_adapter *hns = dev->data->dev_private;
4531         struct hns3_hw *hw = &hns->hw;
4532
4533         PMD_INIT_FUNC_TRACE();
4534
4535         hw->adapter_state = HNS3_NIC_STOPPING;
4536         hns3_set_rxtx_function(dev);
4537         rte_wmb();
4538         /* Disable datapath on secondary process. */
4539         hns3_mp_req_stop_rxtx(dev);
4540         /* Prevent crashes when queues are still in use. */
4541         rte_delay_ms(hw->tqps_num);
4542
4543         rte_spinlock_lock(&hw->lock);
4544         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4545                 hns3_do_stop(hns);
4546                 hns3_unmap_rx_interrupt(dev);
4547                 hns3_dev_release_mbufs(hns);
4548                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4549         }
4550         rte_eal_alarm_cancel(hns3_service_handler, dev);
4551         rte_spinlock_unlock(&hw->lock);
4552 }
4553
4554 static void
4555 hns3_dev_close(struct rte_eth_dev *eth_dev)
4556 {
4557         struct hns3_adapter *hns = eth_dev->data->dev_private;
4558         struct hns3_hw *hw = &hns->hw;
4559
4560         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4561                 rte_free(eth_dev->process_private);
4562                 eth_dev->process_private = NULL;
4563                 return;
4564         }
4565
4566         if (hw->adapter_state == HNS3_NIC_STARTED)
4567                 hns3_dev_stop(eth_dev);
4568
4569         hw->adapter_state = HNS3_NIC_CLOSING;
4570         hns3_reset_abort(hns);
4571         hw->adapter_state = HNS3_NIC_CLOSED;
4572
4573         hns3_configure_all_mc_mac_addr(hns, true);
4574         hns3_remove_all_vlan_table(hns);
4575         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4576         hns3_uninit_pf(eth_dev);
4577         hns3_free_all_queues(eth_dev);
4578         rte_free(hw->reset.wait_data);
4579         rte_free(eth_dev->process_private);
4580         eth_dev->process_private = NULL;
4581         hns3_mp_uninit_primary();
4582         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4583 }
4584
4585 static int
4586 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4587 {
4588         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4590
4591         fc_conf->pause_time = pf->pause_time;
4592
4593         /* return fc current mode */
4594         switch (hw->current_mode) {
4595         case HNS3_FC_FULL:
4596                 fc_conf->mode = RTE_FC_FULL;
4597                 break;
4598         case HNS3_FC_TX_PAUSE:
4599                 fc_conf->mode = RTE_FC_TX_PAUSE;
4600                 break;
4601         case HNS3_FC_RX_PAUSE:
4602                 fc_conf->mode = RTE_FC_RX_PAUSE;
4603                 break;
4604         case HNS3_FC_NONE:
4605         default:
4606                 fc_conf->mode = RTE_FC_NONE;
4607                 break;
4608         }
4609
4610         return 0;
4611 }
4612
4613 static void
4614 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4615 {
4616         switch (mode) {
4617         case RTE_FC_NONE:
4618                 hw->requested_mode = HNS3_FC_NONE;
4619                 break;
4620         case RTE_FC_RX_PAUSE:
4621                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4622                 break;
4623         case RTE_FC_TX_PAUSE:
4624                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4625                 break;
4626         case RTE_FC_FULL:
4627                 hw->requested_mode = HNS3_FC_FULL;
4628                 break;
4629         default:
4630                 hw->requested_mode = HNS3_FC_NONE;
4631                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4632                           "configured to RTE_FC_NONE", mode);
4633                 break;
4634         }
4635 }
4636
4637 static int
4638 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4639 {
4640         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4642         int ret;
4643
4644         if (fc_conf->high_water || fc_conf->low_water ||
4645             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4646                 hns3_err(hw, "Unsupported flow control settings specified, "
4647                          "high_water(%u), low_water(%u), send_xon(%u) and "
4648                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4649                          fc_conf->high_water, fc_conf->low_water,
4650                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4651                 return -EINVAL;
4652         }
4653         if (fc_conf->autoneg) {
4654                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4655                 return -EINVAL;
4656         }
4657         if (!fc_conf->pause_time) {
4658                 hns3_err(hw, "Invalid pause time %d setting.",
4659                          fc_conf->pause_time);
4660                 return -EINVAL;
4661         }
4662
4663         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4664             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4665                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4666                          "current_fc_status = %d", hw->current_fc_status);
4667                 return -EOPNOTSUPP;
4668         }
4669
4670         hns3_get_fc_mode(hw, fc_conf->mode);
4671         if (hw->requested_mode == hw->current_mode &&
4672             pf->pause_time == fc_conf->pause_time)
4673                 return 0;
4674
4675         rte_spinlock_lock(&hw->lock);
4676         ret = hns3_fc_enable(dev, fc_conf);
4677         rte_spinlock_unlock(&hw->lock);
4678
4679         return ret;
4680 }
4681
4682 static int
4683 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4684                             struct rte_eth_pfc_conf *pfc_conf)
4685 {
4686         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4688         uint8_t priority;
4689         int ret;
4690
4691         if (!hns3_dev_dcb_supported(hw)) {
4692                 hns3_err(hw, "This port does not support dcb configurations.");
4693                 return -EOPNOTSUPP;
4694         }
4695
4696         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4697             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4698                 hns3_err(hw, "Unsupported flow control settings specified, "
4699                          "high_water(%u), low_water(%u), send_xon(%u) and "
4700                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4701                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4702                          pfc_conf->fc.send_xon,
4703                          pfc_conf->fc.mac_ctrl_frame_fwd);
4704                 return -EINVAL;
4705         }
4706         if (pfc_conf->fc.autoneg) {
4707                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4708                 return -EINVAL;
4709         }
4710         if (pfc_conf->fc.pause_time == 0) {
4711                 hns3_err(hw, "Invalid pause time %d setting.",
4712                          pfc_conf->fc.pause_time);
4713                 return -EINVAL;
4714         }
4715
4716         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4717             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4718                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4719                              "current_fc_status = %d", hw->current_fc_status);
4720                 return -EOPNOTSUPP;
4721         }
4722
4723         priority = pfc_conf->priority;
4724         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4725         if (hw->dcb_info.pfc_en & BIT(priority) &&
4726             hw->requested_mode == hw->current_mode &&
4727             pfc_conf->fc.pause_time == pf->pause_time)
4728                 return 0;
4729
4730         rte_spinlock_lock(&hw->lock);
4731         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4732         rte_spinlock_unlock(&hw->lock);
4733
4734         return ret;
4735 }
4736
4737 static int
4738 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4739 {
4740         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4742         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4743         int i;
4744
4745         rte_spinlock_lock(&hw->lock);
4746         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4747                 dcb_info->nb_tcs = pf->local_max_tc;
4748         else
4749                 dcb_info->nb_tcs = 1;
4750
4751         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4752                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4753         for (i = 0; i < dcb_info->nb_tcs; i++)
4754                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4755
4756         for (i = 0; i < hw->num_tc; i++) {
4757                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4758                 dcb_info->tc_queue.tc_txq[0][i].base =
4759                                                 hw->tc_queue[i].tqp_offset;
4760                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4761                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4762                                                 hw->tc_queue[i].tqp_count;
4763         }
4764         rte_spinlock_unlock(&hw->lock);
4765
4766         return 0;
4767 }
4768
4769 static int
4770 hns3_reinit_dev(struct hns3_adapter *hns)
4771 {
4772         struct hns3_hw *hw = &hns->hw;
4773         int ret;
4774
4775         ret = hns3_cmd_init(hw);
4776         if (ret) {
4777                 hns3_err(hw, "Failed to init cmd: %d", ret);
4778                 return ret;
4779         }
4780
4781         ret = hns3_reset_all_queues(hns);
4782         if (ret) {
4783                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4784                 return ret;
4785         }
4786
4787         ret = hns3_init_hardware(hns);
4788         if (ret) {
4789                 hns3_err(hw, "Failed to init hardware: %d", ret);
4790                 return ret;
4791         }
4792
4793         ret = hns3_enable_hw_error_intr(hns, true);
4794         if (ret) {
4795                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4796                              ret);
4797                 return ret;
4798         }
4799         hns3_info(hw, "Reset done, driver initialization finished.");
4800
4801         return 0;
4802 }
4803
4804 static bool
4805 is_pf_reset_done(struct hns3_hw *hw)
4806 {
4807         uint32_t val, reg, reg_bit;
4808
4809         switch (hw->reset.level) {
4810         case HNS3_IMP_RESET:
4811                 reg = HNS3_GLOBAL_RESET_REG;
4812                 reg_bit = HNS3_IMP_RESET_BIT;
4813                 break;
4814         case HNS3_GLOBAL_RESET:
4815                 reg = HNS3_GLOBAL_RESET_REG;
4816                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4817                 break;
4818         case HNS3_FUNC_RESET:
4819                 reg = HNS3_FUN_RST_ING;
4820                 reg_bit = HNS3_FUN_RST_ING_B;
4821                 break;
4822         case HNS3_FLR_RESET:
4823         default:
4824                 hns3_err(hw, "Wait for unsupported reset level: %d",
4825                          hw->reset.level);
4826                 return true;
4827         }
4828         val = hns3_read_dev(hw, reg);
4829         if (hns3_get_bit(val, reg_bit))
4830                 return false;
4831         else
4832                 return true;
4833 }
4834
4835 bool
4836 hns3_is_reset_pending(struct hns3_adapter *hns)
4837 {
4838         struct hns3_hw *hw = &hns->hw;
4839         enum hns3_reset_level reset;
4840
4841         hns3_check_event_cause(hns, NULL);
4842         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4843         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4844                 hns3_warn(hw, "High level reset %d is pending", reset);
4845                 return true;
4846         }
4847         reset = hns3_get_reset_level(hns, &hw->reset.request);
4848         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4849                 hns3_warn(hw, "High level reset %d is request", reset);
4850                 return true;
4851         }
4852         return false;
4853 }
4854
4855 static int
4856 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4857 {
4858         struct hns3_hw *hw = &hns->hw;
4859         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4860         struct timeval tv;
4861
4862         if (wait_data->result == HNS3_WAIT_SUCCESS)
4863                 return 0;
4864         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4865                 gettimeofday(&tv, NULL);
4866                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4867                           tv.tv_sec, tv.tv_usec);
4868                 return -ETIME;
4869         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4870                 return -EAGAIN;
4871
4872         wait_data->hns = hns;
4873         wait_data->check_completion = is_pf_reset_done;
4874         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4875                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4876         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4877         wait_data->count = HNS3_RESET_WAIT_CNT;
4878         wait_data->result = HNS3_WAIT_REQUEST;
4879         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4880         return -EAGAIN;
4881 }
4882
4883 static int
4884 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4885 {
4886         struct hns3_cmd_desc desc;
4887         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4888
4889         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4890         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4891         req->fun_reset_vfid = func_id;
4892
4893         return hns3_cmd_send(hw, &desc, 1);
4894 }
4895
4896 static int
4897 hns3_imp_reset_cmd(struct hns3_hw *hw)
4898 {
4899         struct hns3_cmd_desc desc;
4900
4901         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4902         desc.data[0] = 0xeedd;
4903
4904         return hns3_cmd_send(hw, &desc, 1);
4905 }
4906
4907 static void
4908 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4909 {
4910         struct hns3_hw *hw = &hns->hw;
4911         struct timeval tv;
4912         uint32_t val;
4913
4914         gettimeofday(&tv, NULL);
4915         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4916             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4917                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4918                           tv.tv_sec, tv.tv_usec);
4919                 return;
4920         }
4921
4922         switch (reset_level) {
4923         case HNS3_IMP_RESET:
4924                 hns3_imp_reset_cmd(hw);
4925                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4926                           tv.tv_sec, tv.tv_usec);
4927                 break;
4928         case HNS3_GLOBAL_RESET:
4929                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4930                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4931                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4932                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4933                           tv.tv_sec, tv.tv_usec);
4934                 break;
4935         case HNS3_FUNC_RESET:
4936                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4937                           tv.tv_sec, tv.tv_usec);
4938                 /* schedule again to check later */
4939                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4940                 hns3_schedule_reset(hns);
4941                 break;
4942         default:
4943                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4944                 return;
4945         }
4946         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4947 }
4948
4949 static enum hns3_reset_level
4950 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4951 {
4952         struct hns3_hw *hw = &hns->hw;
4953         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4954
4955         /* Return the highest priority reset level amongst all */
4956         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4957                 reset_level = HNS3_IMP_RESET;
4958         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4959                 reset_level = HNS3_GLOBAL_RESET;
4960         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4961                 reset_level = HNS3_FUNC_RESET;
4962         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4963                 reset_level = HNS3_FLR_RESET;
4964
4965         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4966                 return HNS3_NONE_RESET;
4967
4968         return reset_level;
4969 }
4970
4971 static int
4972 hns3_prepare_reset(struct hns3_adapter *hns)
4973 {
4974         struct hns3_hw *hw = &hns->hw;
4975         uint32_t reg_val;
4976         int ret;
4977
4978         switch (hw->reset.level) {
4979         case HNS3_FUNC_RESET:
4980                 ret = hns3_func_reset_cmd(hw, 0);
4981                 if (ret)
4982                         return ret;
4983
4984                 /*
4985                  * After performaning pf reset, it is not necessary to do the
4986                  * mailbox handling or send any command to firmware, because
4987                  * any mailbox handling or command to firmware is only valid
4988                  * after hns3_cmd_init is called.
4989                  */
4990                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4991                 hw->reset.stats.request_cnt++;
4992                 break;
4993         case HNS3_IMP_RESET:
4994                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4995                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4996                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4997                 break;
4998         default:
4999                 break;
5000         }
5001         return 0;
5002 }
5003
5004 static int
5005 hns3_set_rst_done(struct hns3_hw *hw)
5006 {
5007         struct hns3_pf_rst_done_cmd *req;
5008         struct hns3_cmd_desc desc;
5009
5010         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5011         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5012         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5013         return hns3_cmd_send(hw, &desc, 1);
5014 }
5015
5016 static int
5017 hns3_stop_service(struct hns3_adapter *hns)
5018 {
5019         struct hns3_hw *hw = &hns->hw;
5020         struct rte_eth_dev *eth_dev;
5021
5022         eth_dev = &rte_eth_devices[hw->data->port_id];
5023         if (hw->adapter_state == HNS3_NIC_STARTED)
5024                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5025         hw->mac.link_status = ETH_LINK_DOWN;
5026
5027         hns3_set_rxtx_function(eth_dev);
5028         rte_wmb();
5029         /* Disable datapath on secondary process. */
5030         hns3_mp_req_stop_rxtx(eth_dev);
5031         rte_delay_ms(hw->tqps_num);
5032
5033         rte_spinlock_lock(&hw->lock);
5034         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5035             hw->adapter_state == HNS3_NIC_STOPPING) {
5036                 hns3_do_stop(hns);
5037                 hw->reset.mbuf_deferred_free = true;
5038         } else
5039                 hw->reset.mbuf_deferred_free = false;
5040
5041         /*
5042          * It is cumbersome for hardware to pick-and-choose entries for deletion
5043          * from table space. Hence, for function reset software intervention is
5044          * required to delete the entries
5045          */
5046         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5047                 hns3_configure_all_mc_mac_addr(hns, true);
5048         rte_spinlock_unlock(&hw->lock);
5049
5050         return 0;
5051 }
5052
5053 static int
5054 hns3_start_service(struct hns3_adapter *hns)
5055 {
5056         struct hns3_hw *hw = &hns->hw;
5057         struct rte_eth_dev *eth_dev;
5058
5059         if (hw->reset.level == HNS3_IMP_RESET ||
5060             hw->reset.level == HNS3_GLOBAL_RESET)
5061                 hns3_set_rst_done(hw);
5062         eth_dev = &rte_eth_devices[hw->data->port_id];
5063         hns3_set_rxtx_function(eth_dev);
5064         hns3_mp_req_start_rxtx(eth_dev);
5065         if (hw->adapter_state == HNS3_NIC_STARTED) {
5066                 hns3_service_handler(eth_dev);
5067
5068                 /* Enable interrupt of all rx queues before enabling queues */
5069                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5070                 /*
5071                  * When finished the initialization, enable queues to receive
5072                  * and transmit packets.
5073                  */
5074                 hns3_enable_all_queues(hw, true);
5075         }
5076
5077         return 0;
5078 }
5079
5080 static int
5081 hns3_restore_conf(struct hns3_adapter *hns)
5082 {
5083         struct hns3_hw *hw = &hns->hw;
5084         int ret;
5085
5086         ret = hns3_configure_all_mac_addr(hns, false);
5087         if (ret)
5088                 return ret;
5089
5090         ret = hns3_configure_all_mc_mac_addr(hns, false);
5091         if (ret)
5092                 goto err_mc_mac;
5093
5094         ret = hns3_dev_promisc_restore(hns);
5095         if (ret)
5096                 goto err_promisc;
5097
5098         ret = hns3_restore_vlan_table(hns);
5099         if (ret)
5100                 goto err_promisc;
5101
5102         ret = hns3_restore_vlan_conf(hns);
5103         if (ret)
5104                 goto err_promisc;
5105
5106         ret = hns3_restore_all_fdir_filter(hns);
5107         if (ret)
5108                 goto err_promisc;
5109
5110         ret = hns3_restore_rx_interrupt(hw);
5111         if (ret)
5112                 goto err_promisc;
5113
5114         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5115                 ret = hns3_do_start(hns, false);
5116                 if (ret)
5117                         goto err_promisc;
5118                 hns3_info(hw, "hns3 dev restart successful!");
5119         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5120                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5121         return 0;
5122
5123 err_promisc:
5124         hns3_configure_all_mc_mac_addr(hns, true);
5125 err_mc_mac:
5126         hns3_configure_all_mac_addr(hns, true);
5127         return ret;
5128 }
5129
5130 static void
5131 hns3_reset_service(void *param)
5132 {
5133         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5134         struct hns3_hw *hw = &hns->hw;
5135         enum hns3_reset_level reset_level;
5136         struct timeval tv_delta;
5137         struct timeval tv_start;
5138         struct timeval tv;
5139         uint64_t msec;
5140         int ret;
5141
5142         /*
5143          * The interrupt is not triggered within the delay time.
5144          * The interrupt may have been lost. It is necessary to handle
5145          * the interrupt to recover from the error.
5146          */
5147         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5148                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5149                 hns3_err(hw, "Handling interrupts in delayed tasks");
5150                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5151                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5152                 if (reset_level == HNS3_NONE_RESET) {
5153                         hns3_err(hw, "No reset level is set, try IMP reset");
5154                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5155                 }
5156         }
5157         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5158
5159         /*
5160          * Check if there is any ongoing reset in the hardware. This status can
5161          * be checked from reset_pending. If there is then, we need to wait for
5162          * hardware to complete reset.
5163          *    a. If we are able to figure out in reasonable time that hardware
5164          *       has fully resetted then, we can proceed with driver, client
5165          *       reset.
5166          *    b. else, we can come back later to check this status so re-sched
5167          *       now.
5168          */
5169         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5170         if (reset_level != HNS3_NONE_RESET) {
5171                 gettimeofday(&tv_start, NULL);
5172                 ret = hns3_reset_process(hns, reset_level);
5173                 gettimeofday(&tv, NULL);
5174                 timersub(&tv, &tv_start, &tv_delta);
5175                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5176                        tv_delta.tv_usec / USEC_PER_MSEC;
5177                 if (msec > HNS3_RESET_PROCESS_MS)
5178                         hns3_err(hw, "%d handle long time delta %" PRIx64
5179                                      " ms time=%ld.%.6ld",
5180                                  hw->reset.level, msec,
5181                                  tv.tv_sec, tv.tv_usec);
5182                 if (ret == -EAGAIN)
5183                         return;
5184         }
5185
5186         /* Check if we got any *new* reset requests to be honored */
5187         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5188         if (reset_level != HNS3_NONE_RESET)
5189                 hns3_msix_process(hns, reset_level);
5190 }
5191
5192 static const struct eth_dev_ops hns3_eth_dev_ops = {
5193         .dev_start          = hns3_dev_start,
5194         .dev_stop           = hns3_dev_stop,
5195         .dev_close          = hns3_dev_close,
5196         .promiscuous_enable = hns3_dev_promiscuous_enable,
5197         .promiscuous_disable = hns3_dev_promiscuous_disable,
5198         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5199         .allmulticast_disable = hns3_dev_allmulticast_disable,
5200         .mtu_set            = hns3_dev_mtu_set,
5201         .stats_get          = hns3_stats_get,
5202         .stats_reset        = hns3_stats_reset,
5203         .xstats_get         = hns3_dev_xstats_get,
5204         .xstats_get_names   = hns3_dev_xstats_get_names,
5205         .xstats_reset       = hns3_dev_xstats_reset,
5206         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5207         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5208         .dev_infos_get          = hns3_dev_infos_get,
5209         .fw_version_get         = hns3_fw_version_get,
5210         .rx_queue_setup         = hns3_rx_queue_setup,
5211         .tx_queue_setup         = hns3_tx_queue_setup,
5212         .rx_queue_release       = hns3_dev_rx_queue_release,
5213         .tx_queue_release       = hns3_dev_tx_queue_release,
5214         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5215         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5216         .dev_configure          = hns3_dev_configure,
5217         .flow_ctrl_get          = hns3_flow_ctrl_get,
5218         .flow_ctrl_set          = hns3_flow_ctrl_set,
5219         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5220         .mac_addr_add           = hns3_add_mac_addr,
5221         .mac_addr_remove        = hns3_remove_mac_addr,
5222         .mac_addr_set           = hns3_set_default_mac_addr,
5223         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5224         .link_update            = hns3_dev_link_update,
5225         .rss_hash_update        = hns3_dev_rss_hash_update,
5226         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5227         .reta_update            = hns3_dev_rss_reta_update,
5228         .reta_query             = hns3_dev_rss_reta_query,
5229         .filter_ctrl            = hns3_dev_filter_ctrl,
5230         .vlan_filter_set        = hns3_vlan_filter_set,
5231         .vlan_tpid_set          = hns3_vlan_tpid_set,
5232         .vlan_offload_set       = hns3_vlan_offload_set,
5233         .vlan_pvid_set          = hns3_vlan_pvid_set,
5234         .get_reg                = hns3_get_regs,
5235         .get_dcb_info           = hns3_get_dcb_info,
5236         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5237 };
5238
5239 static const struct hns3_reset_ops hns3_reset_ops = {
5240         .reset_service       = hns3_reset_service,
5241         .stop_service        = hns3_stop_service,
5242         .prepare_reset       = hns3_prepare_reset,
5243         .wait_hardware_ready = hns3_wait_hardware_ready,
5244         .reinit_dev          = hns3_reinit_dev,
5245         .restore_conf        = hns3_restore_conf,
5246         .start_service       = hns3_start_service,
5247 };
5248
5249 static int
5250 hns3_dev_init(struct rte_eth_dev *eth_dev)
5251 {
5252         struct rte_device *dev = eth_dev->device;
5253         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5254         struct hns3_adapter *hns = eth_dev->data->dev_private;
5255         struct hns3_hw *hw = &hns->hw;
5256         uint16_t device_id = pci_dev->id.device_id;
5257         int ret;
5258
5259         PMD_INIT_FUNC_TRACE();
5260         eth_dev->process_private = (struct hns3_process_private *)
5261             rte_zmalloc_socket("hns3_filter_list",
5262                                sizeof(struct hns3_process_private),
5263                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5264         if (eth_dev->process_private == NULL) {
5265                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5266                 return -ENOMEM;
5267         }
5268         /* initialize flow filter lists */
5269         hns3_filterlist_init(eth_dev);
5270
5271         hns3_set_rxtx_function(eth_dev);
5272         eth_dev->dev_ops = &hns3_eth_dev_ops;
5273         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5274                 hns3_mp_init_secondary();
5275                 hw->secondary_cnt++;
5276                 return 0;
5277         }
5278
5279         hns3_mp_init_primary();
5280         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5281
5282         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5283             device_id == HNS3_DEV_ID_50GE_RDMA ||
5284             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5285                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5286
5287         hns->is_vf = false;
5288         hw->data = eth_dev->data;
5289
5290         /*
5291          * Set default max packet size according to the mtu
5292          * default vale in DPDK frame.
5293          */
5294         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5295
5296         ret = hns3_reset_init(hw);
5297         if (ret)
5298                 goto err_init_reset;
5299         hw->reset.ops = &hns3_reset_ops;
5300
5301         ret = hns3_init_pf(eth_dev);
5302         if (ret) {
5303                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5304                 goto err_init_pf;
5305         }
5306
5307         /* Allocate memory for storing MAC addresses */
5308         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5309                                                sizeof(struct rte_ether_addr) *
5310                                                HNS3_UC_MACADDR_NUM, 0);
5311         if (eth_dev->data->mac_addrs == NULL) {
5312                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5313                              "to store MAC addresses",
5314                              sizeof(struct rte_ether_addr) *
5315                              HNS3_UC_MACADDR_NUM);
5316                 ret = -ENOMEM;
5317                 goto err_rte_zmalloc;
5318         }
5319
5320         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5321                             &eth_dev->data->mac_addrs[0]);
5322
5323         hw->adapter_state = HNS3_NIC_INITIALIZED;
5324         /*
5325          * Pass the information to the rte_eth_dev_close() that it should also
5326          * release the private port resources.
5327          */
5328         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5329
5330         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5331                 hns3_err(hw, "Reschedule reset service after dev_init");
5332                 hns3_schedule_reset(hns);
5333         } else {
5334                 /* IMP will wait ready flag before reset */
5335                 hns3_notify_reset_ready(hw, false);
5336         }
5337
5338         hns3_info(hw, "hns3 dev initialization successful!");
5339         return 0;
5340
5341 err_rte_zmalloc:
5342         hns3_uninit_pf(eth_dev);
5343
5344 err_init_pf:
5345         rte_free(hw->reset.wait_data);
5346 err_init_reset:
5347         eth_dev->dev_ops = NULL;
5348         eth_dev->rx_pkt_burst = NULL;
5349         eth_dev->tx_pkt_burst = NULL;
5350         eth_dev->tx_pkt_prepare = NULL;
5351         rte_free(eth_dev->process_private);
5352         eth_dev->process_private = NULL;
5353         return ret;
5354 }
5355
5356 static int
5357 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5358 {
5359         struct hns3_adapter *hns = eth_dev->data->dev_private;
5360         struct hns3_hw *hw = &hns->hw;
5361
5362         PMD_INIT_FUNC_TRACE();
5363
5364         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5365                 return -EPERM;
5366
5367         eth_dev->dev_ops = NULL;
5368         eth_dev->rx_pkt_burst = NULL;
5369         eth_dev->tx_pkt_burst = NULL;
5370         eth_dev->tx_pkt_prepare = NULL;
5371         if (hw->adapter_state < HNS3_NIC_CLOSING)
5372                 hns3_dev_close(eth_dev);
5373
5374         hw->adapter_state = HNS3_NIC_REMOVED;
5375         return 0;
5376 }
5377
5378 static int
5379 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5380                    struct rte_pci_device *pci_dev)
5381 {
5382         return rte_eth_dev_pci_generic_probe(pci_dev,
5383                                              sizeof(struct hns3_adapter),
5384                                              hns3_dev_init);
5385 }
5386
5387 static int
5388 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5389 {
5390         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5391 }
5392
5393 static const struct rte_pci_id pci_id_hns3_map[] = {
5394         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5395         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5396         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5397         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5398         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5399         { .vendor_id = 0, /* sentinel */ },
5400 };
5401
5402 static struct rte_pci_driver rte_hns3_pmd = {
5403         .id_table = pci_id_hns3_map,
5404         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5405         .probe = eth_hns3_pci_probe,
5406         .remove = eth_hns3_pci_remove,
5407 };
5408
5409 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5410 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5411 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5412
5413 RTE_INIT(hns3_init_log)
5414 {
5415         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5416         if (hns3_logtype_init >= 0)
5417                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5418         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5419         if (hns3_logtype_driver >= 0)
5420                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5421 }