drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <rte_ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  97
  98 static int hns3_add_mc_addr(struct hns3_hw *hw,
  99                             struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 101                             struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104
 105 void hns3_ether_format_addr(char *buf, uint16_t size,
 106                             const struct rte_ether_addr *ether_addr)
 107 {
 108         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 109                 ether_addr->addr_bytes[0],
 110                 ether_addr->addr_bytes[4],
 111                 ether_addr->addr_bytes[5]);
 112 }
 113
 114 static void
 115 hns3_pf_disable_irq0(struct hns3_hw *hw)
 116 {
 117         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 118 }
 119
 120 static void
 121 hns3_pf_enable_irq0(struct hns3_hw *hw)
 122 {
 123         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 124 }
 125
 126 static enum hns3_evt_cause
 127 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 128 {
 129         struct hns3_hw *hw = &hns->hw;
 130         uint32_t vector0_int_stats;
 131         uint32_t cmdq_src_val;
 132         uint32_t hw_err_src_reg;
 133         uint32_t val;
 134         enum hns3_evt_cause ret;
 135
 136         /* fetch the events from their corresponding regs */
 137         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 138         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 139         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 140
 141         /*
 142          * Assumption: If by any chance reset and mailbox events are reported
 143          * together then we will only process reset event and defer the
 144          * processing of the mailbox events. Since, we would have not cleared
 145          * RX CMDQ event this time we would receive again another interrupt
 146          * from H/W just for the mailbox.
 147          */
 148         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 149                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 150                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 151                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 152                 if (clearval) {
 153                         hw->reset.stats.imp_cnt++;
 154                         hns3_warn(hw, "IMP reset detected, clear reset status");
 155                 } else {
 156                         hns3_schedule_delayed_reset(hns);
 157                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 158                 }
 159
 160                 ret = HNS3_VECTOR0_EVENT_RST;
 161                 goto out;
 162         }
 163
 164         /* Global reset */
 165         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 166                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 167                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 168                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 169                 if (clearval) {
 170                         hw->reset.stats.global_cnt++;
 171                         hns3_warn(hw, "Global reset detected, clear reset status");
 172                 } else {
 173                         hns3_schedule_delayed_reset(hns);
 174                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 175                 }
 176
 177                 ret = HNS3_VECTOR0_EVENT_RST;
 178                 goto out;
 179         }
 180
 181         /* check for vector0 msix event source */
 182         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 183             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 184                 val = vector0_int_stats | hw_err_src_reg;
 185                 ret = HNS3_VECTOR0_EVENT_ERR;
 186                 goto out;
 187         }
 188
 189         /* check for vector0 mailbox(=CMDQ RX) event source */
 190         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 191                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 192                 val = cmdq_src_val;
 193                 ret = HNS3_VECTOR0_EVENT_MBX;
 194                 goto out;
 195         }
 196
 197         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 198                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 199                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 200         val = vector0_int_stats;
 201         ret = HNS3_VECTOR0_EVENT_OTHER;
 202 out:
 203
 204         if (clearval)
 205                 *clearval = val;
 206         return ret;
 207 }
 208
 209 static void
 210 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 211 {
 212         if (event_type == HNS3_VECTOR0_EVENT_RST)
 213                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 214         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 215                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 216 }
 217
 218 static void
 219 hns3_clear_all_event_cause(struct hns3_hw *hw)
 220 {
 221         uint32_t vector0_int_stats;
 222         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 223
 224         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 225                 hns3_warn(hw, "Probe during IMP reset interrupt");
 226
 227         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 228                 hns3_warn(hw, "Probe during Global reset interrupt");
 229
 230         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 231                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 232                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 233                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 234         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 235 }
 236
 237 static void
 238 hns3_interrupt_handler(void *param)
 239 {
 240         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 241         struct hns3_adapter *hns = dev->data->dev_private;
 242         struct hns3_hw *hw = &hns->hw;
 243         enum hns3_evt_cause event_cause;
 244         uint32_t clearval = 0;
 245
 246         /* Disable interrupt */
 247         hns3_pf_disable_irq0(hw);
 248
 249         event_cause = hns3_check_event_cause(hns, &clearval);
 250         /* vector 0 interrupt is shared with reset and mailbox source events. */
 251         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 252                 hns3_warn(hw, "Received err interrupt");
 253                 hns3_handle_msix_error(hns, &hw->reset.request);
 254                 hns3_handle_ras_error(hns, &hw->reset.request);
 255                 hns3_schedule_reset(hns);
 256         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 257                 hns3_warn(hw, "Received reset interrupt");
 258                 hns3_schedule_reset(hns);
 259         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 260                 hns3_dev_handle_mbx_msg(hw);
 261         else
 262                 hns3_err(hw, "Received unknown event");
 263
 264         hns3_clear_event_cause(hw, event_cause, clearval);
 265         /* Enable interrupt if it is not cause by reset */
 266         hns3_pf_enable_irq0(hw);
 267 }
 268
 269 static int
 270 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 271 {
 272 #define HNS3_VLAN_ID_OFFSET_STEP        160
 273 #define HNS3_VLAN_BYTE_SIZE             8
 274         struct hns3_vlan_filter_pf_cfg_cmd *req;
 275         struct hns3_hw *hw = &hns->hw;
 276         uint8_t vlan_offset_byte_val;
 277         struct hns3_cmd_desc desc;
 278         uint8_t vlan_offset_byte;
 279         uint8_t vlan_offset_base;
 280         int ret;
 281
 282         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 283
 284         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 285         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 286                            HNS3_VLAN_BYTE_SIZE;
 287         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 288
 289         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 290         req->vlan_offset = vlan_offset_base;
 291         req->vlan_cfg = on ? 0 : 1;
 292         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 293
 294         ret = hns3_cmd_send(hw, &desc, 1);
 295         if (ret)
 296                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 297                          vlan_id, ret);
 298
 299         return ret;
 300 }
 301
 302 static void
 303 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 304 {
 305         struct hns3_user_vlan_table *vlan_entry;
 306         struct hns3_pf *pf = &hns->pf;
 307
 308         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 309                 if (vlan_entry->vlan_id == vlan_id) {
 310                         if (vlan_entry->hd_tbl_status)
 311                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 312                         LIST_REMOVE(vlan_entry, next);
 313                         rte_free(vlan_entry);
 314                         break;
 315                 }
 316         }
 317 }
 318
 319 static void
 320 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 321                         bool writen_to_tbl)
 322 {
 323         struct hns3_user_vlan_table *vlan_entry;
 324         struct hns3_hw *hw = &hns->hw;
 325         struct hns3_pf *pf = &hns->pf;
 326
 327         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 328                 if (vlan_entry->vlan_id == vlan_id)
 329                         return;
 330         }
 331
 332         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 333         if (vlan_entry == NULL) {
 334                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 335                 return;
 336         }
 337
 338         vlan_entry->hd_tbl_status = writen_to_tbl;
 339         vlan_entry->vlan_id = vlan_id;
 340
 341         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 342 }
 343
 344 static int
 345 hns3_restore_vlan_table(struct hns3_adapter *hns)
 346 {
 347         struct hns3_user_vlan_table *vlan_entry;
 348         struct hns3_hw *hw = &hns->hw;
 349         struct hns3_pf *pf = &hns->pf;
 350         uint16_t vlan_id;
 351         int ret = 0;
 352
 353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 354                 return hns3_vlan_pvid_configure(hns,
 355                                                 hw->port_base_vlan_cfg.pvid, 1);
 356
 357         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 358                 if (vlan_entry->hd_tbl_status) {
 359                         vlan_id = vlan_entry->vlan_id;
 360                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 361                         if (ret)
 362                                 break;
 363                 }
 364         }
 365
 366         return ret;
 367 }
 368
 369 static int
 370 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 371 {
 372         struct hns3_hw *hw = &hns->hw;
 373         bool writen_to_tbl = false;
 374         int ret = 0;
 375
 376         /*
 377          * When vlan filter is enabled, hardware regards packets without vlan
 378          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 379          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 380          */
 381         if (on == 0 && vlan_id == 0)
 382                 return 0;
 383
 384         /*
 385          * When port base vlan enabled, we use port base vlan as the vlan
 386          * filter condition. In this case, we don't update vlan filter table
 387          * when user add new vlan or remove exist vlan, just update the
 388          * vlan list. The vlan id in vlan list will be writen in vlan filter
 389          * table until port base vlan disabled
 390          */
 391         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 392                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 393                 writen_to_tbl = true;
 394         }
 395
 396         if (ret == 0) {
 397                 if (on)
 398                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 399                 else
 400                         hns3_rm_dev_vlan_table(hns, vlan_id);
 401         }
 402         return ret;
 403 }
 404
 405 static int
 406 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 407 {
 408         struct hns3_adapter *hns = dev->data->dev_private;
 409         struct hns3_hw *hw = &hns->hw;
 410         int ret;
 411
 412         rte_spinlock_lock(&hw->lock);
 413         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 414         rte_spinlock_unlock(&hw->lock);
 415         return ret;
 416 }
 417
 418 static int
 419 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 420                          uint16_t tpid)
 421 {
 422         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 423         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 424         struct hns3_hw *hw = &hns->hw;
 425         struct hns3_cmd_desc desc;
 426         int ret;
 427
 428         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 429              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 430                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 431                 return -EINVAL;
 432         }
 433
 434         if (tpid != RTE_ETHER_TYPE_VLAN) {
 435                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 436                 return -EINVAL;
 437         }
 438
 439         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 440         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 441
 442         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 443                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 444                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 445         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 446                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 447                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 448                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 449                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 450         }
 451
 452         ret = hns3_cmd_send(hw, &desc, 1);
 453         if (ret) {
 454                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 455                          ret);
 456                 return ret;
 457         }
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 460
 461         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 462         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 463         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 464
 465         ret = hns3_cmd_send(hw, &desc, 1);
 466         if (ret)
 467                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 468                          ret);
 469         return ret;
 470 }
 471
 472 static int
 473 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 474                    uint16_t tpid)
 475 {
 476         struct hns3_adapter *hns = dev->data->dev_private;
 477         struct hns3_hw *hw = &hns->hw;
 478         int ret;
 479
 480         rte_spinlock_lock(&hw->lock);
 481         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 482         rte_spinlock_unlock(&hw->lock);
 483         return ret;
 484 }
 485
 486 static int
 487 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 488                              struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_vport_vtag_rx_cfg_cmd *req;
 491         struct hns3_hw *hw = &hns->hw;
 492         struct hns3_cmd_desc desc;
 493         uint16_t vport_id;
 494         uint8_t bitmap;
 495         int ret;
 496
 497         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 498
 499         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 500         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 501                      vcfg->strip_tag1_en ? 1 : 0);
 502         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 503                      vcfg->strip_tag2_en ? 1 : 0);
 504         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 505                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 506         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 507                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 508
 509         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 510         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 511                      vcfg->strip_tag1_discard_en ? 1 : 0);
 512         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 513                      vcfg->strip_tag2_discard_en ? 1 : 0);
 514         /*
 515          * In current version VF is not supported when PF is driven by DPDK
 516          * driver, just need to configure parameters for PF vport.
 517          */
 518         vport_id = HNS3_PF_FUNC_ID;
 519         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 520         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 521         req->vf_bitmap[req->vf_offset] = bitmap;
 522
 523         ret = hns3_cmd_send(hw, &desc, 1);
 524         if (ret)
 525                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 526         return ret;
 527 }
 528
 529 static void
 530 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 531                            struct hns3_rx_vtag_cfg *vcfg)
 532 {
 533         struct hns3_pf *pf = &hns->pf;
 534         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 535 }
 536
 537 static void
 538 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 539                            struct hns3_tx_vtag_cfg *vcfg)
 540 {
 541         struct hns3_pf *pf = &hns->pf;
 542         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 543 }
 544
 545 static int
 546 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 547 {
 548         struct hns3_rx_vtag_cfg rxvlan_cfg;
 549         struct hns3_hw *hw = &hns->hw;
 550         int ret;
 551
 552         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 553                 rxvlan_cfg.strip_tag1_en = false;
 554                 rxvlan_cfg.strip_tag2_en = enable;
 555                 rxvlan_cfg.strip_tag2_discard_en = false;
 556         } else {
 557                 rxvlan_cfg.strip_tag1_en = enable;
 558                 rxvlan_cfg.strip_tag2_en = true;
 559                 rxvlan_cfg.strip_tag2_discard_en = true;
 560         }
 561
 562         rxvlan_cfg.strip_tag1_discard_en = false;
 563         rxvlan_cfg.vlan1_vlan_prionly = false;
 564         rxvlan_cfg.vlan2_vlan_prionly = false;
 565         rxvlan_cfg.rx_vlan_offload_en = enable;
 566
 567         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 568         if (ret) {
 569                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 570                 return ret;
 571         }
 572
 573         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 574
 575         return ret;
 576 }
 577
 578 static int
 579 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 580                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 581 {
 582         struct hns3_vlan_filter_ctrl_cmd *req;
 583         struct hns3_cmd_desc desc;
 584         int ret;
 585
 586         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 587
 588         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 589         req->vlan_type = vlan_type;
 590         req->vlan_fe = filter_en ? fe_type : 0;
 591         req->vf_id = vf_id;
 592
 593         ret = hns3_cmd_send(hw, &desc, 1);
 594         if (ret)
 595                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 596
 597         return ret;
 598 }
 599
 600 static int
 601 hns3_vlan_filter_init(struct hns3_adapter *hns)
 602 {
 603         struct hns3_hw *hw = &hns->hw;
 604         int ret;
 605
 606         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 607                                         HNS3_FILTER_FE_EGRESS, false,
 608                                         HNS3_PF_FUNC_ID);
 609         if (ret) {
 610                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 611                 return ret;
 612         }
 613
 614         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 615                                         HNS3_FILTER_FE_INGRESS, false,
 616                                         HNS3_PF_FUNC_ID);
 617         if (ret)
 618                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 619
 620         return ret;
 621 }
 622
 623 static int
 624 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 625 {
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 630                                         HNS3_FILTER_FE_INGRESS, enable,
 631                                         HNS3_PF_FUNC_ID);
 632         if (ret)
 633                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 634                          enable ? "enable" : "disable", ret);
 635
 636         return ret;
 637 }
 638
 639 static int
 640 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 641 {
 642         struct hns3_adapter *hns = dev->data->dev_private;
 643         struct hns3_hw *hw = &hns->hw;
 644         struct rte_eth_rxmode *rxmode;
 645         unsigned int tmp_mask;
 646         bool enable;
 647         int ret = 0;
 648
 649         rte_spinlock_lock(&hw->lock);
 650         rxmode = &dev->data->dev_conf.rxmode;
 651         tmp_mask = (unsigned int)mask;
 652         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 653                 /* ignore vlan filter configuration during promiscuous mode */
 654                 if (!dev->data->promiscuous) {
 655                         /* Enable or disable VLAN filter */
 656                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 657                                  true : false;
 658
 659                         ret = hns3_enable_vlan_filter(hns, enable);
 660                         if (ret) {
 661                                 rte_spinlock_unlock(&hw->lock);
 662                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 663                                          enable ? "enable" : "disable", ret);
 664                                 return ret;
 665                         }
 666                 }
 667         }
 668
 669         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 670                 /* Enable or disable VLAN stripping */
 671                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 672                     true : false;
 673
 674                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 675                 if (ret) {
 676                         rte_spinlock_unlock(&hw->lock);
 677                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 678                                  enable ? "enable" : "disable", ret);
 679                         return ret;
 680                 }
 681         }
 682
 683         rte_spinlock_unlock(&hw->lock);
 684
 685         return ret;
 686 }
 687
 688 static int
 689 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 690                              struct hns3_tx_vtag_cfg *vcfg)
 691 {
 692         struct hns3_vport_vtag_tx_cfg_cmd *req;
 693         struct hns3_cmd_desc desc;
 694         struct hns3_hw *hw = &hns->hw;
 695         uint16_t vport_id;
 696         uint8_t bitmap;
 697         int ret;
 698
 699         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 700
 701         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 702         req->def_vlan_tag1 = vcfg->default_tag1;
 703         req->def_vlan_tag2 = vcfg->default_tag2;
 704         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 705                      vcfg->accept_tag1 ? 1 : 0);
 706         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 707                      vcfg->accept_untag1 ? 1 : 0);
 708         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 709                      vcfg->accept_tag2 ? 1 : 0);
 710         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 711                      vcfg->accept_untag2 ? 1 : 0);
 712         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 713                      vcfg->insert_tag1_en ? 1 : 0);
 714         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 715                      vcfg->insert_tag2_en ? 1 : 0);
 716         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 717
 718         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 719         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 720                      vcfg->tag_shift_mode_en ? 1 : 0);
 721
 722         /*
 723          * In current version VF is not supported when PF is driven by DPDK
 724          * driver, just need to configure parameters for PF vport.
 725          */
 726         vport_id = HNS3_PF_FUNC_ID;
 727         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 728         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 729         req->vf_bitmap[req->vf_offset] = bitmap;
 730
 731         ret = hns3_cmd_send(hw, &desc, 1);
 732         if (ret)
 733                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 734
 735         return ret;
 736 }
 737
 738 static int
 739 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 740                      uint16_t pvid)
 741 {
 742         struct hns3_hw *hw = &hns->hw;
 743         struct hns3_tx_vtag_cfg txvlan_cfg;
 744         int ret;
 745
 746         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 747                 txvlan_cfg.accept_tag1 = true;
 748                 txvlan_cfg.insert_tag1_en = false;
 749                 txvlan_cfg.default_tag1 = 0;
 750         } else {
 751                 txvlan_cfg.accept_tag1 =
 752                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 753                 txvlan_cfg.insert_tag1_en = true;
 754                 txvlan_cfg.default_tag1 = pvid;
 755         }
 756
 757         txvlan_cfg.accept_untag1 = true;
 758         txvlan_cfg.accept_tag2 = true;
 759         txvlan_cfg.accept_untag2 = true;
 760         txvlan_cfg.insert_tag2_en = false;
 761         txvlan_cfg.default_tag2 = 0;
 762         txvlan_cfg.tag_shift_mode_en = true;
 763
 764         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 765         if (ret) {
 766                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 767                          ret);
 768                 return ret;
 769         }
 770
 771         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 772         return ret;
 773 }
 774
 775
 776 static void
 777 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 778 {
 779         struct hns3_user_vlan_table *vlan_entry;
 780         struct hns3_pf *pf = &hns->pf;
 781
 782         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 783                 if (vlan_entry->hd_tbl_status) {
 784                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 785                         vlan_entry->hd_tbl_status = false;
 786                 }
 787         }
 788
 789         if (is_del_list) {
 790                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 791                 while (vlan_entry) {
 792                         LIST_REMOVE(vlan_entry, next);
 793                         rte_free(vlan_entry);
 794                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 795                 }
 796         }
 797 }
 798
 799 static void
 800 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 801 {
 802         struct hns3_user_vlan_table *vlan_entry;
 803         struct hns3_pf *pf = &hns->pf;
 804
 805         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 806                 if (!vlan_entry->hd_tbl_status) {
 807                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 808                         vlan_entry->hd_tbl_status = true;
 809                 }
 810         }
 811 }
 812
 813 static void
 814 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 815 {
 816         struct hns3_hw *hw = &hns->hw;
 817         int ret;
 818
 819         hns3_rm_all_vlan_table(hns, true);
 820         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 821                 ret = hns3_set_port_vlan_filter(hns,
 822                                                 hw->port_base_vlan_cfg.pvid, 0);
 823                 if (ret) {
 824                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 825                                  ret);
 826                         return;
 827                 }
 828         }
 829 }
 830
 831 static int
 832 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 833                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 834 {
 835         struct hns3_hw *hw = &hns->hw;
 836         uint16_t old_pvid;
 837         int ret;
 838
 839         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 840                 old_pvid = hw->port_base_vlan_cfg.pvid;
 841                 if (old_pvid != HNS3_INVALID_PVID) {
 842                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 843                         if (ret) {
 844                                 hns3_err(hw, "failed to remove old pvid %u, "
 845                                                 "ret = %d", old_pvid, ret);
 846                                 return ret;
 847                         }
 848                 }
 849
 850                 hns3_rm_all_vlan_table(hns, false);
 851                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 852                 if (ret) {
 853                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 854                                         new_pvid, ret);
 855                         return ret;
 856                 }
 857         } else {
 858                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 859                 if (ret) {
 860                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 861                                         new_pvid, ret);
 862                         return ret;
 863                 }
 864
 865                 hns3_add_all_vlan_table(hns);
 866         }
 867         return 0;
 868 }
 869
 870 static int
 871 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 872 {
 873         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 874         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 875         bool rx_strip_en;
 876         int ret;
 877
 878         rx_strip_en = old_cfg->rx_vlan_offload_en;
 879         if (on) {
 880                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 881                 rx_vlan_cfg.strip_tag2_en = true;
 882                 rx_vlan_cfg.strip_tag2_discard_en = true;
 883         } else {
 884                 rx_vlan_cfg.strip_tag1_en = false;
 885                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 886                 rx_vlan_cfg.strip_tag2_discard_en = false;
 887         }
 888         rx_vlan_cfg.strip_tag1_discard_en = false;
 889         rx_vlan_cfg.vlan1_vlan_prionly = false;
 890         rx_vlan_cfg.vlan2_vlan_prionly = false;
 891         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 892
 893         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 894         if (ret)
 895                 return ret;
 896
 897         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 898         return ret;
 899 }
 900
 901 static int
 902 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 903 {
 904         struct hns3_hw *hw = &hns->hw;
 905         uint16_t port_base_vlan_state;
 906         int ret;
 907
 908         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 909                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 910                         hns3_warn(hw, "Invalid operation! As current pvid set "
 911                                   "is %u, disable pvid %u is invalid",
 912                                   hw->port_base_vlan_cfg.pvid, pvid);
 913                 return 0;
 914         }
 915
 916         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 917                                     HNS3_PORT_BASE_VLAN_DISABLE;
 918         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 919         if (ret) {
 920                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 921                          ret);
 922                 return ret;
 923         }
 924
 925         ret = hns3_en_pvid_strip(hns, on);
 926         if (ret) {
 927                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 928                          "ret = %d", ret);
 929                 return ret;
 930         }
 931
 932         if (pvid == HNS3_INVALID_PVID)
 933                 goto out;
 934         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 935         if (ret) {
 936                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 937                          ret);
 938                 return ret;
 939         }
 940
 941 out:
 942         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 943         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 944         return ret;
 945 }
 946
 947 static int
 948 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 949 {
 950         struct hns3_adapter *hns = dev->data->dev_private;
 951         struct hns3_hw *hw = &hns->hw;
 952         bool pvid_en_state_change;
 953         uint16_t pvid_state;
 954         int ret;
 955
 956         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 957                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 958                          RTE_ETHER_MAX_VLAN_ID);
 959                 return -EINVAL;
 960         }
 961
 962         /*
 963          * If PVID configuration state change, should refresh the PVID
 964          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 965          */
 966         pvid_state = hw->port_base_vlan_cfg.state;
 967         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 968             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 969                 pvid_en_state_change = false;
 970         else
 971                 pvid_en_state_change = true;
 972
 973         rte_spinlock_lock(&hw->lock);
 974         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 975         rte_spinlock_unlock(&hw->lock);
 976         if (ret)
 977                 return ret;
 978         /*
 979          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 980          * need be processed by PMD driver.
 981          */
 982         if (pvid_en_state_change &&
 983             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 984                 hns3_update_all_queues_pvid_proc_en(hw);
 985
 986         return 0;
 987 }
 988
 989 static int
 990 hns3_default_vlan_config(struct hns3_adapter *hns)
 991 {
 992         struct hns3_hw *hw = &hns->hw;
 993         int ret;
 994
 995         /*
 996          * When vlan filter is enabled, hardware regards packets without vlan
 997          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
 998          * table, packets without vlan won't be received. So, add vlan 0 as
 999          * the default vlan.
1000          */
1001         ret = hns3_vlan_filter_configure(hns, 0, 1);
1002         if (ret)
1003                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1004         return ret;
1005 }
1006
1007 static int
1008 hns3_init_vlan_config(struct hns3_adapter *hns)
1009 {
1010         struct hns3_hw *hw = &hns->hw;
1011         int ret;
1012
1013         /*
1014          * This function can be called in the initialization and reset process,
1015          * when in reset process, it means that hardware had been reseted
1016          * successfully and we need to restore the hardware configuration to
1017          * ensure that the hardware configuration remains unchanged before and
1018          * after reset.
1019          */
1020         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1021                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1022                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1023         }
1024
1025         ret = hns3_vlan_filter_init(hns);
1026         if (ret) {
1027                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1028                 return ret;
1029         }
1030
1031         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1032                                        RTE_ETHER_TYPE_VLAN);
1033         if (ret) {
1034                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1035                 return ret;
1036         }
1037
1038         /*
1039          * When in the reinit dev stage of the reset process, the following
1040          * vlan-related configurations may differ from those at initialization,
1041          * we will restore configurations to hardware in hns3_restore_vlan_table
1042          * and hns3_restore_vlan_conf later.
1043          */
1044         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1045                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1046                 if (ret) {
1047                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1048                         return ret;
1049                 }
1050
1051                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1052                 if (ret) {
1053                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1054                                  ret);
1055                         return ret;
1056                 }
1057         }
1058
1059         return hns3_default_vlan_config(hns);
1060 }
1061
1062 static int
1063 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1064 {
1065         struct hns3_pf *pf = &hns->pf;
1066         struct hns3_hw *hw = &hns->hw;
1067         uint64_t offloads;
1068         bool enable;
1069         int ret;
1070
1071         if (!hw->data->promiscuous) {
1072                 /* restore vlan filter states */
1073                 offloads = hw->data->dev_conf.rxmode.offloads;
1074                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1075                 ret = hns3_enable_vlan_filter(hns, enable);
1076                 if (ret) {
1077                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1078                                  "ret = %d", ret);
1079                         return ret;
1080                 }
1081         }
1082
1083         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1084         if (ret) {
1085                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1086                 return ret;
1087         }
1088
1089         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1090         if (ret)
1091                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1092
1093         return ret;
1094 }
1095
1096 static int
1097 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1098 {
1099         struct hns3_adapter *hns = dev->data->dev_private;
1100         struct rte_eth_dev_data *data = dev->data;
1101         struct rte_eth_txmode *txmode;
1102         struct hns3_hw *hw = &hns->hw;
1103         int mask;
1104         int ret;
1105
1106         txmode = &data->dev_conf.txmode;
1107         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1108                 hns3_warn(hw,
1109                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1110                           "configuration is not supported! Ignore these two "
1111                           "parameters: hw_vlan_reject_tagged(%u), "
1112                           "hw_vlan_reject_untagged(%u)",
1113                           txmode->hw_vlan_reject_tagged,
1114                           txmode->hw_vlan_reject_untagged);
1115
1116         /* Apply vlan offload setting */
1117         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1118         ret = hns3_vlan_offload_set(dev, mask);
1119         if (ret) {
1120                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1121                          ret);
1122                 return ret;
1123         }
1124
1125         /*
1126          * If pvid config is not set in rte_eth_conf, driver needn't to set
1127          * VLAN pvid related configuration to hardware.
1128          */
1129         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1130                 return 0;
1131
1132         /* Apply pvid setting */
1133         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1134                                  txmode->hw_vlan_insert_pvid);
1135         if (ret)
1136                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1137                          txmode->pvid, ret);
1138
1139         return ret;
1140 }
1141
1142 static int
1143 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1144                 unsigned int tso_mss_max)
1145 {
1146         struct hns3_cfg_tso_status_cmd *req;
1147         struct hns3_cmd_desc desc;
1148         uint16_t tso_mss;
1149
1150         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1151
1152         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1153
1154         tso_mss = 0;
1155         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1156                        tso_mss_min);
1157         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1158
1159         tso_mss = 0;
1160         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1161                        tso_mss_max);
1162         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1163
1164         return hns3_cmd_send(hw, &desc, 1);
1165 }
1166
1167 static int
1168 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1169                    uint16_t *allocated_size, bool is_alloc)
1170 {
1171         struct hns3_umv_spc_alc_cmd *req;
1172         struct hns3_cmd_desc desc;
1173         int ret;
1174
1175         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1176         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1177         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1178         req->space_size = rte_cpu_to_le_32(space_size);
1179
1180         ret = hns3_cmd_send(hw, &desc, 1);
1181         if (ret) {
1182                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1183                              is_alloc ? "allocate" : "free", ret);
1184                 return ret;
1185         }
1186
1187         if (is_alloc && allocated_size)
1188                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1189
1190         return 0;
1191 }
1192
1193 static int
1194 hns3_init_umv_space(struct hns3_hw *hw)
1195 {
1196         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1197         struct hns3_pf *pf = &hns->pf;
1198         uint16_t allocated_size = 0;
1199         int ret;
1200
1201         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1202                                  true);
1203         if (ret)
1204                 return ret;
1205
1206         if (allocated_size < pf->wanted_umv_size)
1207                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1208                              pf->wanted_umv_size, allocated_size);
1209
1210         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1211                                                 pf->wanted_umv_size;
1212         pf->used_umv_size = 0;
1213         return 0;
1214 }
1215
1216 static int
1217 hns3_uninit_umv_space(struct hns3_hw *hw)
1218 {
1219         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1220         struct hns3_pf *pf = &hns->pf;
1221         int ret;
1222
1223         if (pf->max_umv_size == 0)
1224                 return 0;
1225
1226         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1227         if (ret)
1228                 return ret;
1229
1230         pf->max_umv_size = 0;
1231
1232         return 0;
1233 }
1234
1235 static bool
1236 hns3_is_umv_space_full(struct hns3_hw *hw)
1237 {
1238         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1239         struct hns3_pf *pf = &hns->pf;
1240         bool is_full;
1241
1242         is_full = (pf->used_umv_size >= pf->max_umv_size);
1243
1244         return is_full;
1245 }
1246
1247 static void
1248 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1249 {
1250         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1251         struct hns3_pf *pf = &hns->pf;
1252
1253         if (is_free) {
1254                 if (pf->used_umv_size > 0)
1255                         pf->used_umv_size--;
1256         } else
1257                 pf->used_umv_size++;
1258 }
1259
1260 static void
1261 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1262                       const uint8_t *addr, bool is_mc)
1263 {
1264         const unsigned char *mac_addr = addr;
1265         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1266                             ((uint32_t)mac_addr[2] << 16) |
1267                             ((uint32_t)mac_addr[1] << 8) |
1268                             (uint32_t)mac_addr[0];
1269         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1270
1271         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1272         if (is_mc) {
1273                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1274                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1275                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1276         }
1277
1278         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1279         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1280 }
1281
1282 static int
1283 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1284                              uint8_t resp_code,
1285                              enum hns3_mac_vlan_tbl_opcode op)
1286 {
1287         if (cmdq_resp) {
1288                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1289                          cmdq_resp);
1290                 return -EIO;
1291         }
1292
1293         if (op == HNS3_MAC_VLAN_ADD) {
1294                 if (resp_code == 0 || resp_code == 1) {
1295                         return 0;
1296                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1297                         hns3_err(hw, "add mac addr failed for uc_overflow");
1298                         return -ENOSPC;
1299                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1300                         hns3_err(hw, "add mac addr failed for mc_overflow");
1301                         return -ENOSPC;
1302                 }
1303
1304                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1305                          resp_code);
1306                 return -EIO;
1307         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1308                 if (resp_code == 0) {
1309                         return 0;
1310                 } else if (resp_code == 1) {
1311                         hns3_dbg(hw, "remove mac addr failed for miss");
1312                         return -ENOENT;
1313                 }
1314
1315                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1316                          resp_code);
1317                 return -EIO;
1318         } else if (op == HNS3_MAC_VLAN_LKUP) {
1319                 if (resp_code == 0) {
1320                         return 0;
1321                 } else if (resp_code == 1) {
1322                         hns3_dbg(hw, "lookup mac addr failed for miss");
1323                         return -ENOENT;
1324                 }
1325
1326                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1327                          resp_code);
1328                 return -EIO;
1329         }
1330
1331         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1332                  op);
1333
1334         return -EINVAL;
1335 }
1336
1337 static int
1338 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1339                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1340                          struct hns3_cmd_desc *desc, bool is_mc)
1341 {
1342         uint8_t resp_code;
1343         uint16_t retval;
1344         int ret;
1345
1346         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1347         if (is_mc) {
1348                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1349                 memcpy(desc[0].data, req,
1350                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1351                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1352                                           true);
1353                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1354                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1355                                           true);
1356                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1357         } else {
1358                 memcpy(desc[0].data, req,
1359                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1360                 ret = hns3_cmd_send(hw, desc, 1);
1361         }
1362         if (ret) {
1363                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1364                          ret);
1365                 return ret;
1366         }
1367         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1368         retval = rte_le_to_cpu_16(desc[0].retval);
1369
1370         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1371                                             HNS3_MAC_VLAN_LKUP);
1372 }
1373
1374 static int
1375 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1376                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1377                       struct hns3_cmd_desc *mc_desc)
1378 {
1379         uint8_t resp_code;
1380         uint16_t retval;
1381         int cfg_status;
1382         int ret;
1383
1384         if (mc_desc == NULL) {
1385                 struct hns3_cmd_desc desc;
1386
1387                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1388                 memcpy(desc.data, req,
1389                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1390                 ret = hns3_cmd_send(hw, &desc, 1);
1391                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392                 retval = rte_le_to_cpu_16(desc.retval);
1393
1394                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395                                                           HNS3_MAC_VLAN_ADD);
1396         } else {
1397                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1398                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1399                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1400                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1401                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1402                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1403                 memcpy(mc_desc[0].data, req,
1404                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1405                 mc_desc[0].retval = 0;
1406                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1407                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1408                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1409
1410                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1411                                                           HNS3_MAC_VLAN_ADD);
1412         }
1413
1414         if (ret) {
1415                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1416                 return ret;
1417         }
1418
1419         return cfg_status;
1420 }
1421
1422 static int
1423 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1424                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1425 {
1426         struct hns3_cmd_desc desc;
1427         uint8_t resp_code;
1428         uint16_t retval;
1429         int ret;
1430
1431         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1432
1433         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1434
1435         ret = hns3_cmd_send(hw, &desc, 1);
1436         if (ret) {
1437                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1438                 return ret;
1439         }
1440         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1441         retval = rte_le_to_cpu_16(desc.retval);
1442
1443         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1444                                             HNS3_MAC_VLAN_REMOVE);
1445 }
1446
1447 static int
1448 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1449 {
1450         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1451         struct hns3_mac_vlan_tbl_entry_cmd req;
1452         struct hns3_pf *pf = &hns->pf;
1453         struct hns3_cmd_desc desc[3];
1454         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1455         uint16_t egress_port = 0;
1456         uint8_t vf_id;
1457         int ret;
1458
1459         /* check if mac addr is valid */
1460         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1461                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1462                                       mac_addr);
1463                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1464                          mac_str);
1465                 return -EINVAL;
1466         }
1467
1468         memset(&req, 0, sizeof(req));
1469
1470         /*
1471          * In current version VF is not supported when PF is driven by DPDK
1472          * driver, just need to configure parameters for PF vport.
1473          */
1474         vf_id = HNS3_PF_FUNC_ID;
1475         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1476                        HNS3_MAC_EPORT_VFID_S, vf_id);
1477
1478         req.egress_port = rte_cpu_to_le_16(egress_port);
1479
1480         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1481
1482         /*
1483          * Lookup the mac address in the mac_vlan table, and add
1484          * it if the entry is inexistent. Repeated unicast entry
1485          * is not allowed in the mac vlan table.
1486          */
1487         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1488         if (ret == -ENOENT) {
1489                 if (!hns3_is_umv_space_full(hw)) {
1490                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1491                         if (!ret)
1492                                 hns3_update_umv_space(hw, false);
1493                         return ret;
1494                 }
1495
1496                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1497
1498                 return -ENOSPC;
1499         }
1500
1501         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1502
1503         /* check if we just hit the duplicate */
1504         if (ret == 0) {
1505                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1506                 return 0;
1507         }
1508
1509         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1510                  mac_str);
1511
1512         return ret;
1513 }
1514
1515 static int
1516 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1517 {
1518         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519         struct rte_ether_addr *addr;
1520         int ret;
1521         int i;
1522
1523         for (i = 0; i < hw->mc_addrs_num; i++) {
1524                 addr = &hw->mc_addrs[i];
1525                 /* Check if there are duplicate addresses */
1526                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1527                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1528                                               addr);
1529                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1530                                  "(%s) is added by the set_mc_mac_addr_list "
1531                                  "API", mac_str);
1532                         return -EINVAL;
1533                 }
1534         }
1535
1536         ret = hns3_add_mc_addr(hw, mac_addr);
1537         if (ret) {
1538                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1539                                       mac_addr);
1540                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1541                          mac_str, ret);
1542         }
1543         return ret;
1544 }
1545
1546 static int
1547 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1548 {
1549         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1550         int ret;
1551
1552         ret = hns3_remove_mc_addr(hw, mac_addr);
1553         if (ret) {
1554                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1555                                       mac_addr);
1556                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1557                          mac_str, ret);
1558         }
1559         return ret;
1560 }
1561
1562 static int
1563 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1564                   uint32_t idx, __rte_unused uint32_t pool)
1565 {
1566         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1568         int ret;
1569
1570         rte_spinlock_lock(&hw->lock);
1571
1572         /*
1573          * In hns3 network engine adding UC and MC mac address with different
1574          * commands with firmware. We need to determine whether the input
1575          * address is a UC or a MC address to call different commands.
1576          * By the way, it is recommended calling the API function named
1577          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1578          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1579          * may affect the specifications of UC mac addresses.
1580          */
1581         if (rte_is_multicast_ether_addr(mac_addr))
1582                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1583         else
1584                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1585
1586         if (ret) {
1587                 rte_spinlock_unlock(&hw->lock);
1588                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1589                                       mac_addr);
1590                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1591                          ret);
1592                 return ret;
1593         }
1594
1595         if (idx == 0)
1596                 hw->mac.default_addr_setted = true;
1597         rte_spinlock_unlock(&hw->lock);
1598
1599         return ret;
1600 }
1601
1602 static int
1603 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1604 {
1605         struct hns3_mac_vlan_tbl_entry_cmd req;
1606         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1607         int ret;
1608
1609         /* check if mac addr is valid */
1610         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1611                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1612                                       mac_addr);
1613                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1614                          mac_str);
1615                 return -EINVAL;
1616         }
1617
1618         memset(&req, 0, sizeof(req));
1619         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1620         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1621         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1622         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1623                 return 0;
1624         else if (ret == 0)
1625                 hns3_update_umv_space(hw, true);
1626
1627         return ret;
1628 }
1629
1630 static void
1631 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1632 {
1633         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         /* index will be checked by upper level rte interface */
1635         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1636         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1637         int ret;
1638
1639         rte_spinlock_lock(&hw->lock);
1640
1641         if (rte_is_multicast_ether_addr(mac_addr))
1642                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1643         else
1644                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1645         rte_spinlock_unlock(&hw->lock);
1646         if (ret) {
1647                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1648                                       mac_addr);
1649                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1650                          ret);
1651         }
1652 }
1653
1654 static int
1655 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1656                           struct rte_ether_addr *mac_addr)
1657 {
1658         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         struct rte_ether_addr *oaddr;
1660         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1661         bool default_addr_setted;
1662         bool rm_succes = false;
1663         int ret, ret_val;
1664
1665         /*
1666          * It has been guaranteed that input parameter named mac_addr is valid
1667          * address in the rte layer of DPDK framework.
1668          */
1669         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1670         default_addr_setted = hw->mac.default_addr_setted;
1671         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1672                 return 0;
1673
1674         rte_spinlock_lock(&hw->lock);
1675         if (default_addr_setted) {
1676                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1677                 if (ret) {
1678                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679                                               oaddr);
1680                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1681                                   mac_str, ret);
1682                         rm_succes = false;
1683                 } else
1684                         rm_succes = true;
1685         }
1686
1687         ret = hns3_add_uc_addr_common(hw, mac_addr);
1688         if (ret) {
1689                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1690                                       mac_addr);
1691                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1692                 goto err_add_uc_addr;
1693         }
1694
1695         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1696         if (ret) {
1697                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1698                 goto err_pause_addr_cfg;
1699         }
1700
1701         rte_ether_addr_copy(mac_addr,
1702                             (struct rte_ether_addr *)hw->mac.mac_addr);
1703         hw->mac.default_addr_setted = true;
1704         rte_spinlock_unlock(&hw->lock);
1705
1706         return 0;
1707
1708 err_pause_addr_cfg:
1709         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1710         if (ret_val) {
1711                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_warn(hw,
1714                           "Failed to roll back to del setted mac addr(%s): %d",
1715                           mac_str, ret_val);
1716         }
1717
1718 err_add_uc_addr:
1719         if (rm_succes) {
1720                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1721                 if (ret_val) {
1722                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1723                                               oaddr);
1724                         hns3_warn(hw,
1725                                   "Failed to restore old uc mac addr(%s): %d",
1726                                   mac_str, ret_val);
1727                         hw->mac.default_addr_setted = false;
1728                 }
1729         }
1730         rte_spinlock_unlock(&hw->lock);
1731
1732         return ret;
1733 }
1734
1735 static int
1736 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1737 {
1738         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1739         struct hns3_hw *hw = &hns->hw;
1740         struct rte_ether_addr *addr;
1741         int err = 0;
1742         int ret;
1743         int i;
1744
1745         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1746                 addr = &hw->data->mac_addrs[i];
1747                 if (rte_is_zero_ether_addr(addr))
1748                         continue;
1749                 if (rte_is_multicast_ether_addr(addr))
1750                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1751                               hns3_add_mc_addr(hw, addr);
1752                 else
1753                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1754                               hns3_add_uc_addr_common(hw, addr);
1755
1756                 if (ret) {
1757                         err = ret;
1758                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1759                                               addr);
1760                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1761                                  "ret = %d.", del ? "remove" : "restore",
1762                                  mac_str, i, ret);
1763                 }
1764         }
1765         return err;
1766 }
1767
1768 static void
1769 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1770 {
1771 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1772         uint8_t word_num;
1773         uint8_t bit_num;
1774
1775         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1776                 word_num = vfid / 32;
1777                 bit_num = vfid % 32;
1778                 if (clr)
1779                         desc[1].data[word_num] &=
1780                             rte_cpu_to_le_32(~(1UL << bit_num));
1781                 else
1782                         desc[1].data[word_num] |=
1783                             rte_cpu_to_le_32(1UL << bit_num);
1784         } else {
1785                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1786                 bit_num = vfid % 32;
1787                 if (clr)
1788                         desc[2].data[word_num] &=
1789                             rte_cpu_to_le_32(~(1UL << bit_num));
1790                 else
1791                         desc[2].data[word_num] |=
1792                             rte_cpu_to_le_32(1UL << bit_num);
1793         }
1794 }
1795
1796 static int
1797 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1798 {
1799         struct hns3_mac_vlan_tbl_entry_cmd req;
1800         struct hns3_cmd_desc desc[3];
1801         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1802         uint8_t vf_id;
1803         int ret;
1804
1805         /* Check if mac addr is valid */
1806         if (!rte_is_multicast_ether_addr(mac_addr)) {
1807                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1808                                       mac_addr);
1809                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1810                          mac_str);
1811                 return -EINVAL;
1812         }
1813
1814         memset(&req, 0, sizeof(req));
1815         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1816         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1817         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1818         if (ret) {
1819                 /* This mac addr do not exist, add new entry for it */
1820                 memset(desc[0].data, 0, sizeof(desc[0].data));
1821                 memset(desc[1].data, 0, sizeof(desc[0].data));
1822                 memset(desc[2].data, 0, sizeof(desc[0].data));
1823         }
1824
1825         /*
1826          * In current version VF is not supported when PF is driven by DPDK
1827          * driver, just need to configure parameters for PF vport.
1828          */
1829         vf_id = HNS3_PF_FUNC_ID;
1830         hns3_update_desc_vfid(desc, vf_id, false);
1831         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1832         if (ret) {
1833                 if (ret == -ENOSPC)
1834                         hns3_err(hw, "mc mac vlan table is full");
1835                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1836                                       mac_addr);
1837                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1838         }
1839
1840         return ret;
1841 }
1842
1843 static int
1844 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1845 {
1846         struct hns3_mac_vlan_tbl_entry_cmd req;
1847         struct hns3_cmd_desc desc[3];
1848         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1849         uint8_t vf_id;
1850         int ret;
1851
1852         /* Check if mac addr is valid */
1853         if (!rte_is_multicast_ether_addr(mac_addr)) {
1854                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1855                                       mac_addr);
1856                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1857                          mac_str);
1858                 return -EINVAL;
1859         }
1860
1861         memset(&req, 0, sizeof(req));
1862         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1863         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1864         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1865         if (ret == 0) {
1866                 /*
1867                  * This mac addr exist, remove this handle's VFID for it.
1868                  * In current version VF is not supported when PF is driven by
1869                  * DPDK driver, just need to configure parameters for PF vport.
1870                  */
1871                 vf_id = HNS3_PF_FUNC_ID;
1872                 hns3_update_desc_vfid(desc, vf_id, true);
1873
1874                 /* All the vfid is zero, so need to delete this entry */
1875                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1876         } else if (ret == -ENOENT) {
1877                 /* This mac addr doesn't exist. */
1878                 return 0;
1879         }
1880
1881         if (ret) {
1882                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1883                                       mac_addr);
1884                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1885         }
1886
1887         return ret;
1888 }
1889
1890 static int
1891 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1892                            struct rte_ether_addr *mc_addr_set,
1893                            uint32_t nb_mc_addr)
1894 {
1895         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1896         struct rte_ether_addr *addr;
1897         uint32_t i;
1898         uint32_t j;
1899
1900         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1901                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1902                          "invalid. valid range: 0~%d",
1903                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1904                 return -EINVAL;
1905         }
1906
1907         /* Check if input mac addresses are valid */
1908         for (i = 0; i < nb_mc_addr; i++) {
1909                 addr = &mc_addr_set[i];
1910                 if (!rte_is_multicast_ether_addr(addr)) {
1911                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1912                                               addr);
1913                         hns3_err(hw,
1914                                  "failed to set mc mac addr, addr(%s) invalid.",
1915                                  mac_str);
1916                         return -EINVAL;
1917                 }
1918
1919                 /* Check if there are duplicate addresses */
1920                 for (j = i + 1; j < nb_mc_addr; j++) {
1921                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1922                                 hns3_ether_format_addr(mac_str,
1923                                                       RTE_ETHER_ADDR_FMT_SIZE,
1924                                                       addr);
1925                                 hns3_err(hw, "failed to set mc mac addr, "
1926                                          "addrs invalid. two same addrs(%s).",
1927                                          mac_str);
1928                                 return -EINVAL;
1929                         }
1930                 }
1931
1932                 /*
1933                  * Check if there are duplicate addresses between mac_addrs
1934                  * and mc_addr_set
1935                  */
1936                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1937                         if (rte_is_same_ether_addr(addr,
1938                                                    &hw->data->mac_addrs[j])) {
1939                                 hns3_ether_format_addr(mac_str,
1940                                                       RTE_ETHER_ADDR_FMT_SIZE,
1941                                                       addr);
1942                                 hns3_err(hw, "failed to set mc mac addr, "
1943                                          "addrs invalid. addrs(%s) has already "
1944                                          "configured in mac_addr add API",
1945                                          mac_str);
1946                                 return -EINVAL;
1947                         }
1948                 }
1949         }
1950
1951         return 0;
1952 }
1953
1954 static void
1955 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1956                            struct rte_ether_addr *mc_addr_set,
1957                            int mc_addr_num,
1958                            struct rte_ether_addr *reserved_addr_list,
1959                            int *reserved_addr_num,
1960                            struct rte_ether_addr *add_addr_list,
1961                            int *add_addr_num,
1962                            struct rte_ether_addr *rm_addr_list,
1963                            int *rm_addr_num)
1964 {
1965         struct rte_ether_addr *addr;
1966         int current_addr_num;
1967         int reserved_num = 0;
1968         int add_num = 0;
1969         int rm_num = 0;
1970         int num;
1971         int i;
1972         int j;
1973         bool same_addr;
1974
1975         /* Calculate the mc mac address list that should be removed */
1976         current_addr_num = hw->mc_addrs_num;
1977         for (i = 0; i < current_addr_num; i++) {
1978                 addr = &hw->mc_addrs[i];
1979                 same_addr = false;
1980                 for (j = 0; j < mc_addr_num; j++) {
1981                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1982                                 same_addr = true;
1983                                 break;
1984                         }
1985                 }
1986
1987                 if (!same_addr) {
1988                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1989                         rm_num++;
1990                 } else {
1991                         rte_ether_addr_copy(addr,
1992                                             &reserved_addr_list[reserved_num]);
1993                         reserved_num++;
1994                 }
1995         }
1996
1997         /* Calculate the mc mac address list that should be added */
1998         for (i = 0; i < mc_addr_num; i++) {
1999                 addr = &mc_addr_set[i];
2000                 same_addr = false;
2001                 for (j = 0; j < current_addr_num; j++) {
2002                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2003                                 same_addr = true;
2004                                 break;
2005                         }
2006                 }
2007
2008                 if (!same_addr) {
2009                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2010                         add_num++;
2011                 }
2012         }
2013
2014         /* Reorder the mc mac address list maintained by driver */
2015         for (i = 0; i < reserved_num; i++)
2016                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2017
2018         for (i = 0; i < rm_num; i++) {
2019                 num = reserved_num + i;
2020                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2021         }
2022
2023         *reserved_addr_num = reserved_num;
2024         *add_addr_num = add_num;
2025         *rm_addr_num = rm_num;
2026 }
2027
2028 static int
2029 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2030                           struct rte_ether_addr *mc_addr_set,
2031                           uint32_t nb_mc_addr)
2032 {
2033         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2035         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2036         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2037         struct rte_ether_addr *addr;
2038         int reserved_addr_num;
2039         int add_addr_num;
2040         int rm_addr_num;
2041         int mc_addr_num;
2042         int num;
2043         int ret;
2044         int i;
2045
2046         /* Check if input parameters are valid */
2047         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2048         if (ret)
2049                 return ret;
2050
2051         rte_spinlock_lock(&hw->lock);
2052
2053         /*
2054          * Calculate the mc mac address lists those should be removed and be
2055          * added, Reorder the mc mac address list maintained by driver.
2056          */
2057         mc_addr_num = (int)nb_mc_addr;
2058         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2059                                    reserved_addr_list, &reserved_addr_num,
2060                                    add_addr_list, &add_addr_num,
2061                                    rm_addr_list, &rm_addr_num);
2062
2063         /* Remove mc mac addresses */
2064         for (i = 0; i < rm_addr_num; i++) {
2065                 num = rm_addr_num - i - 1;
2066                 addr = &rm_addr_list[num];
2067                 ret = hns3_remove_mc_addr(hw, addr);
2068                 if (ret) {
2069                         rte_spinlock_unlock(&hw->lock);
2070                         return ret;
2071                 }
2072                 hw->mc_addrs_num--;
2073         }
2074
2075         /* Add mc mac addresses */
2076         for (i = 0; i < add_addr_num; i++) {
2077                 addr = &add_addr_list[i];
2078                 ret = hns3_add_mc_addr(hw, addr);
2079                 if (ret) {
2080                         rte_spinlock_unlock(&hw->lock);
2081                         return ret;
2082                 }
2083
2084                 num = reserved_addr_num + i;
2085                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2086                 hw->mc_addrs_num++;
2087         }
2088         rte_spinlock_unlock(&hw->lock);
2089
2090         return 0;
2091 }
2092
2093 static int
2094 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2095 {
2096         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2097         struct hns3_hw *hw = &hns->hw;
2098         struct rte_ether_addr *addr;
2099         int err = 0;
2100         int ret;
2101         int i;
2102
2103         for (i = 0; i < hw->mc_addrs_num; i++) {
2104                 addr = &hw->mc_addrs[i];
2105                 if (!rte_is_multicast_ether_addr(addr))
2106                         continue;
2107                 if (del)
2108                         ret = hns3_remove_mc_addr(hw, addr);
2109                 else
2110                         ret = hns3_add_mc_addr(hw, addr);
2111                 if (ret) {
2112                         err = ret;
2113                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2114                                               addr);
2115                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2116                                  del ? "Remove" : "Restore", mac_str, ret);
2117                 }
2118         }
2119         return err;
2120 }
2121
2122 static int
2123 hns3_check_mq_mode(struct rte_eth_dev *dev)
2124 {
2125         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2126         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2127         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2129         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2130         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2131         uint8_t num_tc;
2132         int max_tc = 0;
2133         int i;
2134
2135         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2136         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2137
2138         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2139                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2140                          "rx_mq_mode = %d", rx_mq_mode);
2141                 return -EINVAL;
2142         }
2143
2144         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2145             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2146                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2147                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2148                          rx_mq_mode, tx_mq_mode);
2149                 return -EINVAL;
2150         }
2151
2152         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2153                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2154                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2155                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2156                         return -EINVAL;
2157                 }
2158
2159                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2160                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2161                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2162                                  "nb_tcs(%d) != %d or %d in rx direction.",
2163                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2164                         return -EINVAL;
2165                 }
2166
2167                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2168                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2169                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2170                         return -EINVAL;
2171                 }
2172
2173                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2174                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2175                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2176                                          "is not equal to one in tx direction.",
2177                                          i, dcb_rx_conf->dcb_tc[i]);
2178                                 return -EINVAL;
2179                         }
2180                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2181                                 max_tc = dcb_rx_conf->dcb_tc[i];
2182                 }
2183
2184                 num_tc = max_tc + 1;
2185                 if (num_tc > dcb_rx_conf->nb_tcs) {
2186                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2187                                  num_tc, dcb_rx_conf->nb_tcs);
2188                         return -EINVAL;
2189                 }
2190         }
2191
2192         return 0;
2193 }
2194
2195 static int
2196 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2197 {
2198         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199
2200         if (!hns3_dev_dcb_supported(hw)) {
2201                 hns3_err(hw, "this port does not support dcb configurations.");
2202                 return -EOPNOTSUPP;
2203         }
2204
2205         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2206                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2207                 return -EOPNOTSUPP;
2208         }
2209
2210         /* Check multiple queue mode */
2211         return hns3_check_mq_mode(dev);
2212 }
2213
2214 static int
2215 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2216                            enum hns3_ring_type queue_type, uint16_t queue_id)
2217 {
2218         struct hns3_cmd_desc desc;
2219         struct hns3_ctrl_vector_chain_cmd *req =
2220                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2221         enum hns3_cmd_status status;
2222         enum hns3_opcode_type op;
2223         uint16_t tqp_type_and_id = 0;
2224         const char *op_str;
2225         uint16_t type;
2226         uint16_t gl;
2227
2228         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2229         hns3_cmd_setup_basic_desc(&desc, op, false);
2230         req->int_vector_id = vector_id;
2231
2232         if (queue_type == HNS3_RING_TYPE_RX)
2233                 gl = HNS3_RING_GL_RX;
2234         else
2235                 gl = HNS3_RING_GL_TX;
2236
2237         type = queue_type;
2238
2239         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2240                        type);
2241         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2242         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2243                        gl);
2244         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2245         req->int_cause_num = 1;
2246         op_str = mmap ? "Map" : "Unmap";
2247         status = hns3_cmd_send(hw, &desc, 1);
2248         if (status) {
2249                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2250                          op_str, queue_id, req->int_vector_id, status);
2251                 return status;
2252         }
2253
2254         return 0;
2255 }
2256
2257 static int
2258 hns3_init_ring_with_vector(struct hns3_hw *hw)
2259 {
2260         uint16_t vec;
2261         int ret;
2262         int i;
2263
2264         /*
2265          * In hns3 network engine, vector 0 is always the misc interrupt of this
2266          * function, vector 1~N can be used respectively for the queues of the
2267          * function. Tx and Rx queues with the same number share the interrupt
2268          * vector. In the initialization clearing the all hardware mapping
2269          * relationship configurations between queues and interrupt vectors is
2270          * needed, so some error caused by the residual configurations, such as
2271          * the unexpected Tx interrupt, can be avoid.
2272          */
2273         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2274         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2275                 vec = vec - 1; /* the last interrupt is reserved */
2276         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2277         for (i = 0; i < hw->intr_tqps_num; i++) {
2278                 /*
2279                  * Set gap limiter/rate limiter/quanity limiter algorithm
2280                  * configuration for interrupt coalesce of queue's interrupt.
2281                  */
2282                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2283                                        HNS3_TQP_INTR_GL_DEFAULT);
2284                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2285                                        HNS3_TQP_INTR_GL_DEFAULT);
2286                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2287                 /*
2288                  * QL(quantity limiter) is not used currently, just set 0 to
2289                  * close it.
2290                  */
2291                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2292
2293                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2294                                                  HNS3_RING_TYPE_TX, i);
2295                 if (ret) {
2296                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2297                                           "vector: %u, ret=%d", i, vec, ret);
2298                         return ret;
2299                 }
2300
2301                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2302                                                  HNS3_RING_TYPE_RX, i);
2303                 if (ret) {
2304                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2305                                           "vector: %u, ret=%d", i, vec, ret);
2306                         return ret;
2307                 }
2308         }
2309
2310         return 0;
2311 }
2312
2313 static int
2314 hns3_dev_configure(struct rte_eth_dev *dev)
2315 {
2316         struct hns3_adapter *hns = dev->data->dev_private;
2317         struct rte_eth_conf *conf = &dev->data->dev_conf;
2318         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2319         struct hns3_hw *hw = &hns->hw;
2320         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2321         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2322         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2323         struct rte_eth_rss_conf rss_conf;
2324         uint16_t mtu;
2325         bool gro_en;
2326         int ret;
2327
2328         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2329
2330         /*
2331          * Some versions of hardware network engine does not support
2332          * individually enable/disable/reset the Tx or Rx queue. These devices
2333          * must enable/disable/reset Tx and Rx queues at the same time. When the
2334          * numbers of Tx queues allocated by upper applications are not equal to
2335          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2336          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2337          * work as usual. But these fake queues are imperceptible, and can not
2338          * be used by upper applications.
2339          */
2340         if (!hns3_dev_indep_txrx_supported(hw)) {
2341                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2342                 if (ret) {
2343                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2344                                  ret);
2345                         return ret;
2346                 }
2347         }
2348
2349         hw->adapter_state = HNS3_NIC_CONFIGURING;
2350         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2351                 hns3_err(hw, "setting link speed/duplex not supported");
2352                 ret = -EINVAL;
2353                 goto cfg_err;
2354         }
2355
2356         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2357                 ret = hns3_check_dcb_cfg(dev);
2358                 if (ret)
2359                         goto cfg_err;
2360         }
2361
2362         /* When RSS is not configured, redirect the packet queue 0 */
2363         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2364                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2365                 rss_conf = conf->rx_adv_conf.rss_conf;
2366                 hw->rss_dis_flag = false;
2367                 if (rss_conf.rss_key == NULL) {
2368                         rss_conf.rss_key = rss_cfg->key;
2369                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2370                 }
2371
2372                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2373                 if (ret)
2374                         goto cfg_err;
2375         }
2376
2377         /*
2378          * If jumbo frames are enabled, MTU needs to be refreshed
2379          * according to the maximum RX packet length.
2380          */
2381         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2382                 /*
2383                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2384                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2385                  * can safely assign to "uint16_t" type variable.
2386                  */
2387                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2388                 ret = hns3_dev_mtu_set(dev, mtu);
2389                 if (ret)
2390                         goto cfg_err;
2391                 dev->data->mtu = mtu;
2392         }
2393
2394         ret = hns3_dev_configure_vlan(dev);
2395         if (ret)
2396                 goto cfg_err;
2397
2398         /* config hardware GRO */
2399         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2400         ret = hns3_config_gro(hw, gro_en);
2401         if (ret)
2402                 goto cfg_err;
2403
2404         hns->rx_simple_allowed = true;
2405         hns->rx_vec_allowed = true;
2406         hns->tx_simple_allowed = true;
2407         hns->tx_vec_allowed = true;
2408
2409         hns3_init_rx_ptype_tble(dev);
2410         hw->adapter_state = HNS3_NIC_CONFIGURED;
2411
2412         return 0;
2413
2414 cfg_err:
2415         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2416         hw->adapter_state = HNS3_NIC_INITIALIZED;
2417
2418         return ret;
2419 }
2420
2421 static int
2422 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2423 {
2424         struct hns3_config_max_frm_size_cmd *req;
2425         struct hns3_cmd_desc desc;
2426
2427         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2428
2429         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2430         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2431         req->min_frm_size = RTE_ETHER_MIN_LEN;
2432
2433         return hns3_cmd_send(hw, &desc, 1);
2434 }
2435
2436 static int
2437 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2438 {
2439         int ret;
2440
2441         ret = hns3_set_mac_mtu(hw, mps);
2442         if (ret) {
2443                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2444                 return ret;
2445         }
2446
2447         ret = hns3_buffer_alloc(hw);
2448         if (ret)
2449                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2450
2451         return ret;
2452 }
2453
2454 static int
2455 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2456 {
2457         struct hns3_adapter *hns = dev->data->dev_private;
2458         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2459         struct hns3_hw *hw = &hns->hw;
2460         bool is_jumbo_frame;
2461         int ret;
2462
2463         if (dev->data->dev_started) {
2464                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2465                          "before configuration", dev->data->port_id);
2466                 return -EBUSY;
2467         }
2468
2469         rte_spinlock_lock(&hw->lock);
2470         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2471         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2472
2473         /*
2474          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2475          * assign to "uint16_t" type variable.
2476          */
2477         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2478         if (ret) {
2479                 rte_spinlock_unlock(&hw->lock);
2480                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2481                          dev->data->port_id, mtu, ret);
2482                 return ret;
2483         }
2484         hns->pf.mps = (uint16_t)frame_size;
2485         if (is_jumbo_frame)
2486                 dev->data->dev_conf.rxmode.offloads |=
2487                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2488         else
2489                 dev->data->dev_conf.rxmode.offloads &=
2490                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2491         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2492         rte_spinlock_unlock(&hw->lock);
2493
2494         return 0;
2495 }
2496
2497 static int
2498 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2499 {
2500         struct hns3_adapter *hns = eth_dev->data->dev_private;
2501         struct hns3_hw *hw = &hns->hw;
2502         uint16_t queue_num = hw->tqps_num;
2503
2504         /*
2505          * In interrupt mode, 'max_rx_queues' is set based on the number of
2506          * MSI-X interrupt resources of the hardware.
2507          */
2508         if (hw->data->dev_conf.intr_conf.rxq == 1)
2509                 queue_num = hw->intr_tqps_num;
2510
2511         info->max_rx_queues = queue_num;
2512         info->max_tx_queues = hw->tqps_num;
2513         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2514         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2515         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2516         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2517         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2518         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2519                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2520                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2521                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2522                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2523                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2524                                  DEV_RX_OFFLOAD_KEEP_CRC |
2525                                  DEV_RX_OFFLOAD_SCATTER |
2526                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2527                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2528                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2529                                  DEV_RX_OFFLOAD_RSS_HASH |
2530                                  DEV_RX_OFFLOAD_TCP_LRO);
2531         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2532                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2533                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2534                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2535                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2536                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2537                                  DEV_TX_OFFLOAD_TCP_TSO |
2538                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2539                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2540                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2541                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2542                                  hns3_txvlan_cap_get(hw));
2543
2544         if (hns3_dev_indep_txrx_supported(hw))
2545                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2546                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2547
2548         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2549                 .nb_max = HNS3_MAX_RING_DESC,
2550                 .nb_min = HNS3_MIN_RING_DESC,
2551                 .nb_align = HNS3_ALIGN_RING_DESC,
2552         };
2553
2554         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2555                 .nb_max = HNS3_MAX_RING_DESC,
2556                 .nb_min = HNS3_MIN_RING_DESC,
2557                 .nb_align = HNS3_ALIGN_RING_DESC,
2558                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2559                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2560         };
2561
2562         info->default_rxconf = (struct rte_eth_rxconf) {
2563                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2564                 /*
2565                  * If there are no available Rx buffer descriptors, incoming
2566                  * packets are always dropped by hardware based on hns3 network
2567                  * engine.
2568                  */
2569                 .rx_drop_en = 1,
2570                 .offloads = 0,
2571         };
2572         info->default_txconf = (struct rte_eth_txconf) {
2573                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2574                 .offloads = 0,
2575         };
2576
2577         info->vmdq_queue_num = 0;
2578
2579         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2580         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2581         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2582
2583         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2584         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2585         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2586         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2587         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2588         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2595                     size_t fw_size)
2596 {
2597         struct hns3_adapter *hns = eth_dev->data->dev_private;
2598         struct hns3_hw *hw = &hns->hw;
2599         uint32_t version = hw->fw_version;
2600         int ret;
2601
2602         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2603                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2604                                       HNS3_FW_VERSION_BYTE3_S),
2605                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2606                                       HNS3_FW_VERSION_BYTE2_S),
2607                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2608                                       HNS3_FW_VERSION_BYTE1_S),
2609                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2610                                       HNS3_FW_VERSION_BYTE0_S));
2611         ret += 1; /* add the size of '\0' */
2612         if (fw_size < (uint32_t)ret)
2613                 return ret;
2614         else
2615                 return 0;
2616 }
2617
2618 static int
2619 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2620                      __rte_unused int wait_to_complete)
2621 {
2622         struct hns3_adapter *hns = eth_dev->data->dev_private;
2623         struct hns3_hw *hw = &hns->hw;
2624         struct hns3_mac *mac = &hw->mac;
2625         struct rte_eth_link new_link;
2626
2627         if (!hns3_is_reset_pending(hns)) {
2628                 hns3_update_speed_duplex(eth_dev);
2629                 hns3_update_link_status(hw);
2630         }
2631
2632         memset(&new_link, 0, sizeof(new_link));
2633         switch (mac->link_speed) {
2634         case ETH_SPEED_NUM_10M:
2635         case ETH_SPEED_NUM_100M:
2636         case ETH_SPEED_NUM_1G:
2637         case ETH_SPEED_NUM_10G:
2638         case ETH_SPEED_NUM_25G:
2639         case ETH_SPEED_NUM_40G:
2640         case ETH_SPEED_NUM_50G:
2641         case ETH_SPEED_NUM_100G:
2642         case ETH_SPEED_NUM_200G:
2643                 new_link.link_speed = mac->link_speed;
2644                 break;
2645         default:
2646                 new_link.link_speed = ETH_SPEED_NUM_100M;
2647                 break;
2648         }
2649
2650         new_link.link_duplex = mac->link_duplex;
2651         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2652         new_link.link_autoneg =
2653             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2654
2655         return rte_eth_linkstatus_set(eth_dev, &new_link);
2656 }
2657
2658 static int
2659 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2660 {
2661         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2662         struct hns3_pf *pf = &hns->pf;
2663
2664         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2665                 return -EINVAL;
2666
2667         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2668
2669         return 0;
2670 }
2671
2672 static int
2673 hns3_query_function_status(struct hns3_hw *hw)
2674 {
2675 #define HNS3_QUERY_MAX_CNT              10
2676 #define HNS3_QUERY_SLEEP_MSCOEND        1
2677         struct hns3_func_status_cmd *req;
2678         struct hns3_cmd_desc desc;
2679         int timeout = 0;
2680         int ret;
2681
2682         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2683         req = (struct hns3_func_status_cmd *)desc.data;
2684
2685         do {
2686                 ret = hns3_cmd_send(hw, &desc, 1);
2687                 if (ret) {
2688                         PMD_INIT_LOG(ERR, "query function status failed %d",
2689                                      ret);
2690                         return ret;
2691                 }
2692
2693                 /* Check pf reset is done */
2694                 if (req->pf_state)
2695                         break;
2696
2697                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2698         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2699
2700         return hns3_parse_func_status(hw, req);
2701 }
2702
2703 static int
2704 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2705 {
2706         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2707         struct hns3_pf *pf = &hns->pf;
2708
2709         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2710                 /*
2711                  * The total_tqps_num obtained from firmware is maximum tqp
2712                  * numbers of this port, which should be used for PF and VFs.
2713                  * There is no need for pf to have so many tqp numbers in
2714                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2715                  * coming from config file, is assigned to maximum queue number
2716                  * for the PF of this port by user. So users can modify the
2717                  * maximum queue number of PF according to their own application
2718                  * scenarios, which is more flexible to use. In addition, many
2719                  * memories can be saved due to allocating queue statistics
2720                  * room according to the actual number of queues required. The
2721                  * maximum queue number of PF for network engine with
2722                  * revision_id greater than 0x30 is assigned by config file.
2723                  */
2724                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2725                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2726                                  "must be greater than 0.",
2727                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2728                         return -EINVAL;
2729                 }
2730
2731                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2732                                        hw->total_tqps_num);
2733         } else {
2734                 /*
2735                  * Due to the limitation on the number of PF interrupts
2736                  * available, the maximum queue number assigned to PF on
2737                  * the network engine with revision_id 0x21 is 64.
2738                  */
2739                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2740                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2741         }
2742
2743         return 0;
2744 }
2745
2746 static int
2747 hns3_query_pf_resource(struct hns3_hw *hw)
2748 {
2749         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2750         struct hns3_pf *pf = &hns->pf;
2751         struct hns3_pf_res_cmd *req;
2752         struct hns3_cmd_desc desc;
2753         int ret;
2754
2755         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2756         ret = hns3_cmd_send(hw, &desc, 1);
2757         if (ret) {
2758                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2759                 return ret;
2760         }
2761
2762         req = (struct hns3_pf_res_cmd *)desc.data;
2763         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2764                              rte_le_to_cpu_16(req->ext_tqp_num);
2765         ret = hns3_get_pf_max_tqp_num(hw);
2766         if (ret)
2767                 return ret;
2768
2769         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2770         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2771
2772         if (req->tx_buf_size)
2773                 pf->tx_buf_size =
2774                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2775         else
2776                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2777
2778         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2779
2780         if (req->dv_buf_size)
2781                 pf->dv_buf_size =
2782                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2783         else
2784                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2785
2786         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2787
2788         hw->num_msi =
2789                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2790                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2791
2792         return 0;
2793 }
2794
2795 static void
2796 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2797 {
2798         struct hns3_cfg_param_cmd *req;
2799         uint64_t mac_addr_tmp_high;
2800         uint8_t ext_rss_size_max;
2801         uint64_t mac_addr_tmp;
2802         uint32_t i;
2803
2804         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2805
2806         /* get the configuration */
2807         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2808                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2809         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2810                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2811         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2812                                            HNS3_CFG_TQP_DESC_N_M,
2813                                            HNS3_CFG_TQP_DESC_N_S);
2814
2815         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2816                                        HNS3_CFG_PHY_ADDR_M,
2817                                        HNS3_CFG_PHY_ADDR_S);
2818         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2819                                          HNS3_CFG_MEDIA_TP_M,
2820                                          HNS3_CFG_MEDIA_TP_S);
2821         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2822                                          HNS3_CFG_RX_BUF_LEN_M,
2823                                          HNS3_CFG_RX_BUF_LEN_S);
2824         /* get mac address */
2825         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2826         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2827                                            HNS3_CFG_MAC_ADDR_H_M,
2828                                            HNS3_CFG_MAC_ADDR_H_S);
2829
2830         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2831
2832         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2833                                             HNS3_CFG_DEFAULT_SPEED_M,
2834                                             HNS3_CFG_DEFAULT_SPEED_S);
2835         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2836                                            HNS3_CFG_RSS_SIZE_M,
2837                                            HNS3_CFG_RSS_SIZE_S);
2838
2839         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2840                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2841
2842         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2843         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2844
2845         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2846                                             HNS3_CFG_SPEED_ABILITY_M,
2847                                             HNS3_CFG_SPEED_ABILITY_S);
2848         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2849                                         HNS3_CFG_UMV_TBL_SPACE_M,
2850                                         HNS3_CFG_UMV_TBL_SPACE_S);
2851         if (!cfg->umv_space)
2852                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2853
2854         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2855                                                HNS3_CFG_EXT_RSS_SIZE_M,
2856                                                HNS3_CFG_EXT_RSS_SIZE_S);
2857
2858         /*
2859          * Field ext_rss_size_max obtained from firmware will be more flexible
2860          * for future changes and expansions, which is an exponent of 2, instead
2861          * of reading out directly. If this field is not zero, hns3 PF PMD
2862          * driver uses it as rss_size_max under one TC. Device, whose revision
2863          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2864          * maximum number of queues supported under a TC through this field.
2865          */
2866         if (ext_rss_size_max)
2867                 cfg->rss_size_max = 1U << ext_rss_size_max;
2868 }
2869
2870 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2871  * @hw: pointer to struct hns3_hw
2872  * @hcfg: the config structure to be getted
2873  */
2874 static int
2875 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2876 {
2877         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2878         struct hns3_cfg_param_cmd *req;
2879         uint32_t offset;
2880         uint32_t i;
2881         int ret;
2882
2883         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2884                 offset = 0;
2885                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2886                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2887                                           true);
2888                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2889                                i * HNS3_CFG_RD_LEN_BYTES);
2890                 /* Len should be divided by 4 when send to hardware */
2891                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2892                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2893                 req->offset = rte_cpu_to_le_32(offset);
2894         }
2895
2896         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2897         if (ret) {
2898                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2899                 return ret;
2900         }
2901
2902         hns3_parse_cfg(hcfg, desc);
2903
2904         return 0;
2905 }
2906
2907 static int
2908 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2909 {
2910         switch (speed_cmd) {
2911         case HNS3_CFG_SPEED_10M:
2912                 *speed = ETH_SPEED_NUM_10M;
2913                 break;
2914         case HNS3_CFG_SPEED_100M:
2915                 *speed = ETH_SPEED_NUM_100M;
2916                 break;
2917         case HNS3_CFG_SPEED_1G:
2918                 *speed = ETH_SPEED_NUM_1G;
2919                 break;
2920         case HNS3_CFG_SPEED_10G:
2921                 *speed = ETH_SPEED_NUM_10G;
2922                 break;
2923         case HNS3_CFG_SPEED_25G:
2924                 *speed = ETH_SPEED_NUM_25G;
2925                 break;
2926         case HNS3_CFG_SPEED_40G:
2927                 *speed = ETH_SPEED_NUM_40G;
2928                 break;
2929         case HNS3_CFG_SPEED_50G:
2930                 *speed = ETH_SPEED_NUM_50G;
2931                 break;
2932         case HNS3_CFG_SPEED_100G:
2933                 *speed = ETH_SPEED_NUM_100G;
2934                 break;
2935         case HNS3_CFG_SPEED_200G:
2936                 *speed = ETH_SPEED_NUM_200G;
2937                 break;
2938         default:
2939                 return -EINVAL;
2940         }
2941
2942         return 0;
2943 }
2944
2945 static void
2946 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2947 {
2948         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2949         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2950         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2951         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2952         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2953 }
2954
2955 static void
2956 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2957 {
2958         struct hns3_dev_specs_0_cmd *req0;
2959
2960         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2961
2962         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2963         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2964         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2965         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2966         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2967 }
2968
2969 static int
2970 hns3_query_dev_specifications(struct hns3_hw *hw)
2971 {
2972         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2973         int ret;
2974         int i;
2975
2976         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2977                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2978                                           true);
2979                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2980         }
2981         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2982
2983         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2984         if (ret)
2985                 return ret;
2986
2987         hns3_parse_dev_specifications(hw, desc);
2988
2989         return 0;
2990 }
2991
2992 static int
2993 hns3_get_capability(struct hns3_hw *hw)
2994 {
2995         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2996         struct rte_pci_device *pci_dev;
2997         struct hns3_pf *pf = &hns->pf;
2998         struct rte_eth_dev *eth_dev;
2999         uint16_t device_id;
3000         uint8_t revision;
3001         int ret;
3002
3003         eth_dev = &rte_eth_devices[hw->data->port_id];
3004         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3005         device_id = pci_dev->id.device_id;
3006
3007         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3008             device_id == HNS3_DEV_ID_50GE_RDMA ||
3009             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3010             device_id == HNS3_DEV_ID_200G_RDMA)
3011                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3012
3013         /* Get PCI revision id */
3014         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3015                                   HNS3_PCI_REVISION_ID);
3016         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3017                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3018                              ret);
3019                 return -EIO;
3020         }
3021         hw->revision = revision;
3022
3023         if (revision < PCI_REVISION_ID_HIP09_A) {
3024                 hns3_set_default_dev_specifications(hw);
3025                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3026                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3027                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3028                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3029                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3030                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3031                 hw->rss_info.ipv6_sctp_offload_supported = false;
3032                 return 0;
3033         }
3034
3035         ret = hns3_query_dev_specifications(hw);
3036         if (ret) {
3037                 PMD_INIT_LOG(ERR,
3038                              "failed to query dev specifications, ret = %d",
3039                              ret);
3040                 return ret;
3041         }
3042
3043         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3044         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3045         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3046         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3047         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3048         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3049         hw->rss_info.ipv6_sctp_offload_supported = true;
3050
3051         return 0;
3052 }
3053
3054 static int
3055 hns3_get_board_configuration(struct hns3_hw *hw)
3056 {
3057         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3058         struct hns3_pf *pf = &hns->pf;
3059         struct hns3_cfg cfg;
3060         int ret;
3061
3062         ret = hns3_get_board_cfg(hw, &cfg);
3063         if (ret) {
3064                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3065                 return ret;
3066         }
3067
3068         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3069             !hns3_dev_copper_supported(hw)) {
3070                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3071                 return -EOPNOTSUPP;
3072         }
3073
3074         hw->mac.media_type = cfg.media_type;
3075         hw->rss_size_max = cfg.rss_size_max;
3076         hw->rss_dis_flag = false;
3077         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3078         hw->mac.phy_addr = cfg.phy_addr;
3079         hw->mac.default_addr_setted = false;
3080         hw->num_tx_desc = cfg.tqp_desc_num;
3081         hw->num_rx_desc = cfg.tqp_desc_num;
3082         hw->dcb_info.num_pg = 1;
3083         hw->dcb_info.hw_pfc_map = 0;
3084
3085         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3086         if (ret) {
3087                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3088                              cfg.default_speed, ret);
3089                 return ret;
3090         }
3091
3092         pf->tc_max = cfg.tc_num;
3093         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3094                 PMD_INIT_LOG(WARNING,
3095                              "Get TC num(%u) from flash, set TC num to 1",
3096                              pf->tc_max);
3097                 pf->tc_max = 1;
3098         }
3099
3100         /* Dev does not support DCB */
3101         if (!hns3_dev_dcb_supported(hw)) {
3102                 pf->tc_max = 1;
3103                 pf->pfc_max = 0;
3104         } else
3105                 pf->pfc_max = pf->tc_max;
3106
3107         hw->dcb_info.num_tc = 1;
3108         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3109                                      hw->tqps_num / hw->dcb_info.num_tc);
3110         hns3_set_bit(hw->hw_tc_map, 0, 1);
3111         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3112
3113         pf->wanted_umv_size = cfg.umv_space;
3114
3115         return ret;
3116 }
3117
3118 static int
3119 hns3_get_configuration(struct hns3_hw *hw)
3120 {
3121         int ret;
3122
3123         ret = hns3_query_function_status(hw);
3124         if (ret) {
3125                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3126                 return ret;
3127         }
3128
3129         /* Get device capability */
3130         ret = hns3_get_capability(hw);
3131         if (ret) {
3132                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3133                 return ret;
3134         }
3135
3136         /* Get pf resource */
3137         ret = hns3_query_pf_resource(hw);
3138         if (ret) {
3139                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3140                 return ret;
3141         }
3142
3143         ret = hns3_get_board_configuration(hw);
3144         if (ret) {
3145                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3146                 return ret;
3147         }
3148
3149         ret = hns3_query_dev_fec_info(hw);
3150         if (ret)
3151                 PMD_INIT_LOG(ERR,
3152                              "failed to query FEC information, ret = %d", ret);
3153
3154         return ret;
3155 }
3156
3157 static int
3158 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3159                       uint16_t tqp_vid, bool is_pf)
3160 {
3161         struct hns3_tqp_map_cmd *req;
3162         struct hns3_cmd_desc desc;
3163         int ret;
3164
3165         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3166
3167         req = (struct hns3_tqp_map_cmd *)desc.data;
3168         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3169         req->tqp_vf = func_id;
3170         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3171         if (!is_pf)
3172                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3173         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3174
3175         ret = hns3_cmd_send(hw, &desc, 1);
3176         if (ret)
3177                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3178
3179         return ret;
3180 }
3181
3182 static int
3183 hns3_map_tqp(struct hns3_hw *hw)
3184 {
3185         int ret;
3186         int i;
3187
3188         /*
3189          * In current version, VF is not supported when PF is driven by DPDK
3190          * driver, so we assign total tqps_num tqps allocated to this port
3191          * to PF.
3192          */
3193         for (i = 0; i < hw->total_tqps_num; i++) {
3194                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3195                 if (ret)
3196                         return ret;
3197         }
3198
3199         return 0;
3200 }
3201
3202 static int
3203 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3204 {
3205         struct hns3_config_mac_speed_dup_cmd *req;
3206         struct hns3_cmd_desc desc;
3207         int ret;
3208
3209         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3210
3211         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3212
3213         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3214
3215         switch (speed) {
3216         case ETH_SPEED_NUM_10M:
3217                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3218                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3219                 break;
3220         case ETH_SPEED_NUM_100M:
3221                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3222                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3223                 break;
3224         case ETH_SPEED_NUM_1G:
3225                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3226                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3227                 break;
3228         case ETH_SPEED_NUM_10G:
3229                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3230                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3231                 break;
3232         case ETH_SPEED_NUM_25G:
3233                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3234                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3235                 break;
3236         case ETH_SPEED_NUM_40G:
3237                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3238                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3239                 break;
3240         case ETH_SPEED_NUM_50G:
3241                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3242                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3243                 break;
3244         case ETH_SPEED_NUM_100G:
3245                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3246                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3247                 break;
3248         case ETH_SPEED_NUM_200G:
3249                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3250                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3251                 break;
3252         default:
3253                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3254                 return -EINVAL;
3255         }
3256
3257         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3258
3259         ret = hns3_cmd_send(hw, &desc, 1);
3260         if (ret)
3261                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3262
3263         return ret;
3264 }
3265
3266 static int
3267 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3268 {
3269         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3270         struct hns3_pf *pf = &hns->pf;
3271         struct hns3_priv_buf *priv;
3272         uint32_t i, total_size;
3273
3274         total_size = pf->pkt_buf_size;
3275
3276         /* alloc tx buffer for all enabled tc */
3277         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3278                 priv = &buf_alloc->priv_buf[i];
3279
3280                 if (hw->hw_tc_map & BIT(i)) {
3281                         if (total_size < pf->tx_buf_size)
3282                                 return -ENOMEM;
3283
3284                         priv->tx_buf_size = pf->tx_buf_size;
3285                 } else
3286                         priv->tx_buf_size = 0;
3287
3288                 total_size -= priv->tx_buf_size;
3289         }
3290
3291         return 0;
3292 }
3293
3294 static int
3295 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3296 {
3297 /* TX buffer size is unit by 128 byte */
3298 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3299 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3300         struct hns3_tx_buff_alloc_cmd *req;
3301         struct hns3_cmd_desc desc;
3302         uint32_t buf_size;
3303         uint32_t i;
3304         int ret;
3305
3306         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3307
3308         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3309         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3310                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3311
3312                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3313                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3314                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3315         }
3316
3317         ret = hns3_cmd_send(hw, &desc, 1);
3318         if (ret)
3319                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3320
3321         return ret;
3322 }
3323
3324 static int
3325 hns3_get_tc_num(struct hns3_hw *hw)
3326 {
3327         int cnt = 0;
3328         uint8_t i;
3329
3330         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3331                 if (hw->hw_tc_map & BIT(i))
3332                         cnt++;
3333         return cnt;
3334 }
3335
3336 static uint32_t
3337 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3338 {
3339         struct hns3_priv_buf *priv;
3340         uint32_t rx_priv = 0;
3341         int i;
3342
3343         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3344                 priv = &buf_alloc->priv_buf[i];
3345                 if (priv->enable)
3346                         rx_priv += priv->buf_size;
3347         }
3348         return rx_priv;
3349 }
3350
3351 static uint32_t
3352 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3353 {
3354         uint32_t total_tx_size = 0;
3355         uint32_t i;
3356
3357         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3358                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3359
3360         return total_tx_size;
3361 }
3362
3363 /* Get the number of pfc enabled TCs, which have private buffer */
3364 static int
3365 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3366 {
3367         struct hns3_priv_buf *priv;
3368         int cnt = 0;
3369         uint8_t i;
3370
3371         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3372                 priv = &buf_alloc->priv_buf[i];
3373                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3374                         cnt++;
3375         }
3376
3377         return cnt;
3378 }
3379
3380 /* Get the number of pfc disabled TCs, which have private buffer */
3381 static int
3382 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3383                          struct hns3_pkt_buf_alloc *buf_alloc)
3384 {
3385         struct hns3_priv_buf *priv;
3386         int cnt = 0;
3387         uint8_t i;
3388
3389         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3390                 priv = &buf_alloc->priv_buf[i];
3391                 if (hw->hw_tc_map & BIT(i) &&
3392                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3393                         cnt++;
3394         }
3395
3396         return cnt;
3397 }
3398
3399 static bool
3400 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3401                   uint32_t rx_all)
3402 {
3403         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3404         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3405         struct hns3_pf *pf = &hns->pf;
3406         uint32_t shared_buf, aligned_mps;
3407         uint32_t rx_priv;
3408         uint8_t tc_num;
3409         uint8_t i;
3410
3411         tc_num = hns3_get_tc_num(hw);
3412         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3413
3414         if (hns3_dev_dcb_supported(hw))
3415                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3416                                         pf->dv_buf_size;
3417         else
3418                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3419                                         + pf->dv_buf_size;
3420
3421         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3422         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3423                              HNS3_BUF_SIZE_UNIT);
3424
3425         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3426         if (rx_all < rx_priv + shared_std)
3427                 return false;
3428
3429         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3430         buf_alloc->s_buf.buf_size = shared_buf;
3431         if (hns3_dev_dcb_supported(hw)) {
3432                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3433                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3434                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3435                                   HNS3_BUF_SIZE_UNIT);
3436         } else {
3437                 buf_alloc->s_buf.self.high =
3438                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3439                 buf_alloc->s_buf.self.low = aligned_mps;
3440         }
3441
3442         if (hns3_dev_dcb_supported(hw)) {
3443                 hi_thrd = shared_buf - pf->dv_buf_size;
3444
3445                 if (tc_num <= NEED_RESERVE_TC_NUM)
3446                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3447                                   BUF_MAX_PERCENT;
3448
3449                 if (tc_num)
3450                         hi_thrd = hi_thrd / tc_num;
3451
3452                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3453                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3454                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3455         } else {
3456                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3457                 lo_thrd = aligned_mps;
3458         }
3459
3460         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3461                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3462                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3463         }
3464
3465         return true;
3466 }
3467
3468 static bool
3469 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3470                      struct hns3_pkt_buf_alloc *buf_alloc)
3471 {
3472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3473         struct hns3_pf *pf = &hns->pf;
3474         struct hns3_priv_buf *priv;
3475         uint32_t aligned_mps;
3476         uint32_t rx_all;
3477         uint8_t i;
3478
3479         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3480         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3481
3482         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3483                 priv = &buf_alloc->priv_buf[i];
3484
3485                 priv->enable = 0;
3486                 priv->wl.low = 0;
3487                 priv->wl.high = 0;
3488                 priv->buf_size = 0;
3489
3490                 if (!(hw->hw_tc_map & BIT(i)))
3491                         continue;
3492
3493                 priv->enable = 1;
3494                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3495                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3496                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3497                                                 HNS3_BUF_SIZE_UNIT);
3498                 } else {
3499                         priv->wl.low = 0;
3500                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3501                                         aligned_mps;
3502                 }
3503
3504                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3505         }
3506
3507         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3508 }
3509
3510 static bool
3511 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3512                              struct hns3_pkt_buf_alloc *buf_alloc)
3513 {
3514         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3515         struct hns3_pf *pf = &hns->pf;
3516         struct hns3_priv_buf *priv;
3517         int no_pfc_priv_num;
3518         uint32_t rx_all;
3519         uint8_t mask;
3520         int i;
3521
3522         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3523         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3524
3525         /* let the last to be cleared first */
3526         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3527                 priv = &buf_alloc->priv_buf[i];
3528                 mask = BIT((uint8_t)i);
3529
3530                 if (hw->hw_tc_map & mask &&
3531                     !(hw->dcb_info.hw_pfc_map & mask)) {
3532                         /* Clear the no pfc TC private buffer */
3533                         priv->wl.low = 0;
3534                         priv->wl.high = 0;
3535                         priv->buf_size = 0;
3536                         priv->enable = 0;
3537                         no_pfc_priv_num--;
3538                 }
3539
3540                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3541                     no_pfc_priv_num == 0)
3542                         break;
3543         }
3544
3545         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3546 }
3547
3548 static bool
3549 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3550                            struct hns3_pkt_buf_alloc *buf_alloc)
3551 {
3552         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3553         struct hns3_pf *pf = &hns->pf;
3554         struct hns3_priv_buf *priv;
3555         uint32_t rx_all;
3556         int pfc_priv_num;
3557         uint8_t mask;
3558         int i;
3559
3560         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3561         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3562
3563         /* let the last to be cleared first */
3564         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3565                 priv = &buf_alloc->priv_buf[i];
3566                 mask = BIT((uint8_t)i);
3567                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3568                         /* Reduce the number of pfc TC with private buffer */
3569                         priv->wl.low = 0;
3570                         priv->enable = 0;
3571                         priv->wl.high = 0;
3572                         priv->buf_size = 0;
3573                         pfc_priv_num--;
3574                 }
3575                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3576                     pfc_priv_num == 0)
3577                         break;
3578         }
3579
3580         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3581 }
3582
3583 static bool
3584 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3585                           struct hns3_pkt_buf_alloc *buf_alloc)
3586 {
3587 #define COMPENSATE_BUFFER       0x3C00
3588 #define COMPENSATE_HALF_MPS_NUM 5
3589 #define PRIV_WL_GAP             0x1800
3590         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3591         struct hns3_pf *pf = &hns->pf;
3592         uint32_t tc_num = hns3_get_tc_num(hw);
3593         uint32_t half_mps = pf->mps >> 1;
3594         struct hns3_priv_buf *priv;
3595         uint32_t min_rx_priv;
3596         uint32_t rx_priv;
3597         uint8_t i;
3598
3599         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3600         if (tc_num)
3601                 rx_priv = rx_priv / tc_num;
3602
3603         if (tc_num <= NEED_RESERVE_TC_NUM)
3604                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3605
3606         /*
3607          * Minimum value of private buffer in rx direction (min_rx_priv) is
3608          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3609          * buffer if rx_priv is greater than min_rx_priv.
3610          */
3611         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3612                         COMPENSATE_HALF_MPS_NUM * half_mps;
3613         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3614         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3615
3616         if (rx_priv < min_rx_priv)
3617                 return false;
3618
3619         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3620                 priv = &buf_alloc->priv_buf[i];
3621                 priv->enable = 0;
3622                 priv->wl.low = 0;
3623                 priv->wl.high = 0;
3624                 priv->buf_size = 0;
3625
3626                 if (!(hw->hw_tc_map & BIT(i)))
3627                         continue;
3628
3629                 priv->enable = 1;
3630                 priv->buf_size = rx_priv;
3631                 priv->wl.high = rx_priv - pf->dv_buf_size;
3632                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3633         }
3634
3635         buf_alloc->s_buf.buf_size = 0;
3636
3637         return true;
3638 }
3639
3640 /*
3641  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3642  * @hw: pointer to struct hns3_hw
3643  * @buf_alloc: pointer to buffer calculation data
3644  * @return: 0: calculate sucessful, negative: fail
3645  */
3646 static int
3647 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3648 {
3649         /* When DCB is not supported, rx private buffer is not allocated. */
3650         if (!hns3_dev_dcb_supported(hw)) {
3651                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3652                 struct hns3_pf *pf = &hns->pf;
3653                 uint32_t rx_all = pf->pkt_buf_size;
3654
3655                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3656                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3657                         return -ENOMEM;
3658
3659                 return 0;
3660         }
3661
3662         /*
3663          * Try to allocate privated packet buffer for all TCs without share
3664          * buffer.
3665          */
3666         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3667                 return 0;
3668
3669         /*
3670          * Try to allocate privated packet buffer for all TCs with share
3671          * buffer.
3672          */
3673         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3674                 return 0;
3675
3676         /*
3677          * For different application scenes, the enabled port number, TC number
3678          * and no_drop TC number are different. In order to obtain the better
3679          * performance, software could allocate the buffer size and configure
3680          * the waterline by tring to decrease the private buffer size according
3681          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3682          * enabled tc.
3683          */
3684         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3685                 return 0;
3686
3687         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3688                 return 0;
3689
3690         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3691                 return 0;
3692
3693         return -ENOMEM;
3694 }
3695
3696 static int
3697 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3698 {
3699         struct hns3_rx_priv_buff_cmd *req;
3700         struct hns3_cmd_desc desc;
3701         uint32_t buf_size;
3702         int ret;
3703         int i;
3704
3705         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3706         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3707
3708         /* Alloc private buffer TCs */
3709         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3710                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3711
3712                 req->buf_num[i] =
3713                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3714                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3715         }
3716
3717         buf_size = buf_alloc->s_buf.buf_size;
3718         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3719                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3720
3721         ret = hns3_cmd_send(hw, &desc, 1);
3722         if (ret)
3723                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3724
3725         return ret;
3726 }
3727
3728 static int
3729 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3730 {
3731 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3732         struct hns3_rx_priv_wl_buf *req;
3733         struct hns3_priv_buf *priv;
3734         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3735         int i, j;
3736         int ret;
3737
3738         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3739                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3740                                           false);
3741                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3742
3743                 /* The first descriptor set the NEXT bit to 1 */
3744                 if (i == 0)
3745                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3746                 else
3747                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3748
3749                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3750                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3751
3752                         priv = &buf_alloc->priv_buf[idx];
3753                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3754                                                         HNS3_BUF_UNIT_S);
3755                         req->tc_wl[j].high |=
3756                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3757                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3758                                                         HNS3_BUF_UNIT_S);
3759                         req->tc_wl[j].low |=
3760                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3761                 }
3762         }
3763
3764         /* Send 2 descriptor at one time */
3765         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3766         if (ret)
3767                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3768                              ret);
3769         return ret;
3770 }
3771
3772 static int
3773 hns3_common_thrd_config(struct hns3_hw *hw,
3774                         struct hns3_pkt_buf_alloc *buf_alloc)
3775 {
3776 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3777         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3778         struct hns3_rx_com_thrd *req;
3779         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3780         struct hns3_tc_thrd *tc;
3781         int tc_idx;
3782         int i, j;
3783         int ret;
3784
3785         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3786                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3787                                           false);
3788                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3789
3790                 /* The first descriptor set the NEXT bit to 1 */
3791                 if (i == 0)
3792                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3793                 else
3794                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3795
3796                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3797                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3798                         tc = &s_buf->tc_thrd[tc_idx];
3799
3800                         req->com_thrd[j].high =
3801                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3802                         req->com_thrd[j].high |=
3803                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3804                         req->com_thrd[j].low =
3805                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3806                         req->com_thrd[j].low |=
3807                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3808                 }
3809         }
3810
3811         /* Send 2 descriptors at one time */
3812         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3813         if (ret)
3814                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3815
3816         return ret;
3817 }
3818
3819 static int
3820 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3821 {
3822         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3823         struct hns3_rx_com_wl *req;
3824         struct hns3_cmd_desc desc;
3825         int ret;
3826
3827         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3828
3829         req = (struct hns3_rx_com_wl *)desc.data;
3830         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3831         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3832
3833         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3834         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3835
3836         ret = hns3_cmd_send(hw, &desc, 1);
3837         if (ret)
3838                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3839
3840         return ret;
3841 }
3842
3843 int
3844 hns3_buffer_alloc(struct hns3_hw *hw)
3845 {
3846         struct hns3_pkt_buf_alloc pkt_buf;
3847         int ret;
3848
3849         memset(&pkt_buf, 0, sizeof(pkt_buf));
3850         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3851         if (ret) {
3852                 PMD_INIT_LOG(ERR,
3853                              "could not calc tx buffer size for all TCs %d",
3854                              ret);
3855                 return ret;
3856         }
3857
3858         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3859         if (ret) {
3860                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3861                 return ret;
3862         }
3863
3864         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3865         if (ret) {
3866                 PMD_INIT_LOG(ERR,
3867                              "could not calc rx priv buffer size for all TCs %d",
3868                              ret);
3869                 return ret;
3870         }
3871
3872         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3873         if (ret) {
3874                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3875                 return ret;
3876         }
3877
3878         if (hns3_dev_dcb_supported(hw)) {
3879                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3880                 if (ret) {
3881                         PMD_INIT_LOG(ERR,
3882                                      "could not configure rx private waterline %d",
3883                                      ret);
3884                         return ret;
3885                 }
3886
3887                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3888                 if (ret) {
3889                         PMD_INIT_LOG(ERR,
3890                                      "could not configure common threshold %d",
3891                                      ret);
3892                         return ret;
3893                 }
3894         }
3895
3896         ret = hns3_common_wl_config(hw, &pkt_buf);
3897         if (ret)
3898                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3899                              ret);
3900
3901         return ret;
3902 }
3903
3904 static int
3905 hns3_mac_init(struct hns3_hw *hw)
3906 {
3907         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3908         struct hns3_mac *mac = &hw->mac;
3909         struct hns3_pf *pf = &hns->pf;
3910         int ret;
3911
3912         pf->support_sfp_query = true;
3913         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3914         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3915         if (ret) {
3916                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3917                 return ret;
3918         }
3919
3920         mac->link_status = ETH_LINK_DOWN;
3921
3922         return hns3_config_mtu(hw, pf->mps);
3923 }
3924
3925 static int
3926 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3927 {
3928 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3929 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3930 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3931 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3932         int return_status;
3933
3934         if (cmdq_resp) {
3935                 PMD_INIT_LOG(ERR,
3936                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3937                              cmdq_resp);
3938                 return -EIO;
3939         }
3940
3941         switch (resp_code) {
3942         case HNS3_ETHERTYPE_SUCCESS_ADD:
3943         case HNS3_ETHERTYPE_ALREADY_ADD:
3944                 return_status = 0;
3945                 break;
3946         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3947                 PMD_INIT_LOG(ERR,
3948                              "add mac ethertype failed for manager table overflow.");
3949                 return_status = -EIO;
3950                 break;
3951         case HNS3_ETHERTYPE_KEY_CONFLICT:
3952                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3953                 return_status = -EIO;
3954                 break;
3955         default:
3956                 PMD_INIT_LOG(ERR,
3957                              "add mac ethertype failed for undefined, code=%u.",
3958                              resp_code);
3959                 return_status = -EIO;
3960                 break;
3961         }
3962
3963         return return_status;
3964 }
3965
3966 static int
3967 hns3_add_mgr_tbl(struct hns3_hw *hw,
3968                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3969 {
3970         struct hns3_cmd_desc desc;
3971         uint8_t resp_code;
3972         uint16_t retval;
3973         int ret;
3974
3975         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3976         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3977
3978         ret = hns3_cmd_send(hw, &desc, 1);
3979         if (ret) {
3980                 PMD_INIT_LOG(ERR,
3981                              "add mac ethertype failed for cmd_send, ret =%d.",
3982                              ret);
3983                 return ret;
3984         }
3985
3986         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3987         retval = rte_le_to_cpu_16(desc.retval);
3988
3989         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3990 }
3991
3992 static void
3993 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3994                      int *table_item_num)
3995 {
3996         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3997
3998         /*
3999          * In current version, we add one item in management table as below:
4000          * 0x0180C200000E -- LLDP MC address
4001          */
4002         tbl = mgr_table;
4003         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4004         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4005         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4006         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4007         tbl->i_port_bitmap = 0x1;
4008         *table_item_num = 1;
4009 }
4010
4011 static int
4012 hns3_init_mgr_tbl(struct hns3_hw *hw)
4013 {
4014 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4015         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4016         int table_item_num;
4017         int ret;
4018         int i;
4019
4020         memset(mgr_table, 0, sizeof(mgr_table));
4021         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4022         for (i = 0; i < table_item_num; i++) {
4023                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4024                 if (ret) {
4025                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4026                                      ret);
4027                         return ret;
4028                 }
4029         }
4030
4031         return 0;
4032 }
4033
4034 static void
4035 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4036                         bool en_mc, bool en_bc, int vport_id)
4037 {
4038         if (!param)
4039                 return;
4040
4041         memset(param, 0, sizeof(struct hns3_promisc_param));
4042         if (en_uc)
4043                 param->enable = HNS3_PROMISC_EN_UC;
4044         if (en_mc)
4045                 param->enable |= HNS3_PROMISC_EN_MC;
4046         if (en_bc)
4047                 param->enable |= HNS3_PROMISC_EN_BC;
4048         param->vf_id = vport_id;
4049 }
4050
4051 static int
4052 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4053 {
4054         struct hns3_promisc_cfg_cmd *req;
4055         struct hns3_cmd_desc desc;
4056         int ret;
4057
4058         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4059
4060         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4061         req->vf_id = param->vf_id;
4062         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4063             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4064
4065         ret = hns3_cmd_send(hw, &desc, 1);
4066         if (ret)
4067                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4068
4069         return ret;
4070 }
4071
4072 static int
4073 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4074 {
4075         struct hns3_promisc_param param;
4076         bool en_bc_pmc = true;
4077         uint8_t vf_id;
4078
4079         /*
4080          * In current version VF is not supported when PF is driven by DPDK
4081          * driver, just need to configure parameters for PF vport.
4082          */
4083         vf_id = HNS3_PF_FUNC_ID;
4084
4085         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4086         return hns3_cmd_set_promisc_mode(hw, &param);
4087 }
4088
4089 static int
4090 hns3_promisc_init(struct hns3_hw *hw)
4091 {
4092         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4093         struct hns3_pf *pf = &hns->pf;
4094         struct hns3_promisc_param param;
4095         uint16_t func_id;
4096         int ret;
4097
4098         ret = hns3_set_promisc_mode(hw, false, false);
4099         if (ret) {
4100                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4101                 return ret;
4102         }
4103
4104         /*
4105          * In current version VFs are not supported when PF is driven by DPDK
4106          * driver. After PF has been taken over by DPDK, the original VF will
4107          * be invalid. So, there is a possibility of entry residues. It should
4108          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4109          * during init.
4110          */
4111         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4112                 hns3_promisc_param_init(&param, false, false, false, func_id);
4113                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4114                 if (ret) {
4115                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4116                                         " ret = %d", func_id, ret);
4117                         return ret;
4118                 }
4119         }
4120
4121         return 0;
4122 }
4123
4124 static void
4125 hns3_promisc_uninit(struct hns3_hw *hw)
4126 {
4127         struct hns3_promisc_param param;
4128         uint16_t func_id;
4129         int ret;
4130
4131         func_id = HNS3_PF_FUNC_ID;
4132
4133         /*
4134          * In current version VFs are not supported when PF is driven by
4135          * DPDK driver, and VFs' promisc mode status has been cleared during
4136          * init and their status will not change. So just clear PF's promisc
4137          * mode status during uninit.
4138          */
4139         hns3_promisc_param_init(&param, false, false, false, func_id);
4140         ret = hns3_cmd_set_promisc_mode(hw, &param);
4141         if (ret)
4142                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4143                                 " uninit, ret = %d", ret);
4144 }
4145
4146 static int
4147 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4148 {
4149         bool allmulti = dev->data->all_multicast ? true : false;
4150         struct hns3_adapter *hns = dev->data->dev_private;
4151         struct hns3_hw *hw = &hns->hw;
4152         uint64_t offloads;
4153         int err;
4154         int ret;
4155
4156         rte_spinlock_lock(&hw->lock);
4157         ret = hns3_set_promisc_mode(hw, true, true);
4158         if (ret) {
4159                 rte_spinlock_unlock(&hw->lock);
4160                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4161                          ret);
4162                 return ret;
4163         }
4164
4165         /*
4166          * When promiscuous mode was enabled, disable the vlan filter to let
4167          * all packets coming in in the receiving direction.
4168          */
4169         offloads = dev->data->dev_conf.rxmode.offloads;
4170         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4171                 ret = hns3_enable_vlan_filter(hns, false);
4172                 if (ret) {
4173                         hns3_err(hw, "failed to enable promiscuous mode due to "
4174                                      "failure to disable vlan filter, ret = %d",
4175                                  ret);
4176                         err = hns3_set_promisc_mode(hw, false, allmulti);
4177                         if (err)
4178                                 hns3_err(hw, "failed to restore promiscuous "
4179                                          "status after disable vlan filter "
4180                                          "failed during enabling promiscuous "
4181                                          "mode, ret = %d", ret);
4182                 }
4183         }
4184
4185         rte_spinlock_unlock(&hw->lock);
4186
4187         return ret;
4188 }
4189
4190 static int
4191 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4192 {
4193         bool allmulti = dev->data->all_multicast ? true : false;
4194         struct hns3_adapter *hns = dev->data->dev_private;
4195         struct hns3_hw *hw = &hns->hw;
4196         uint64_t offloads;
4197         int err;
4198         int ret;
4199
4200         /* If now in all_multicast mode, must remain in all_multicast mode. */
4201         rte_spinlock_lock(&hw->lock);
4202         ret = hns3_set_promisc_mode(hw, false, allmulti);
4203         if (ret) {
4204                 rte_spinlock_unlock(&hw->lock);
4205                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4206                          ret);
4207                 return ret;
4208         }
4209         /* when promiscuous mode was disabled, restore the vlan filter status */
4210         offloads = dev->data->dev_conf.rxmode.offloads;
4211         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4212                 ret = hns3_enable_vlan_filter(hns, true);
4213                 if (ret) {
4214                         hns3_err(hw, "failed to disable promiscuous mode due to"
4215                                  " failure to restore vlan filter, ret = %d",
4216                                  ret);
4217                         err = hns3_set_promisc_mode(hw, true, true);
4218                         if (err)
4219                                 hns3_err(hw, "failed to restore promiscuous "
4220                                          "status after enabling vlan filter "
4221                                          "failed during disabling promiscuous "
4222                                          "mode, ret = %d", ret);
4223                 }
4224         }
4225         rte_spinlock_unlock(&hw->lock);
4226
4227         return ret;
4228 }
4229
4230 static int
4231 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4232 {
4233         struct hns3_adapter *hns = dev->data->dev_private;
4234         struct hns3_hw *hw = &hns->hw;
4235         int ret;
4236
4237         if (dev->data->promiscuous)
4238                 return 0;
4239
4240         rte_spinlock_lock(&hw->lock);
4241         ret = hns3_set_promisc_mode(hw, false, true);
4242         rte_spinlock_unlock(&hw->lock);
4243         if (ret)
4244                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4245                          ret);
4246
4247         return ret;
4248 }
4249
4250 static int
4251 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4252 {
4253         struct hns3_adapter *hns = dev->data->dev_private;
4254         struct hns3_hw *hw = &hns->hw;
4255         int ret;
4256
4257         /* If now in promiscuous mode, must remain in all_multicast mode. */
4258         if (dev->data->promiscuous)
4259                 return 0;
4260
4261         rte_spinlock_lock(&hw->lock);
4262         ret = hns3_set_promisc_mode(hw, false, false);
4263         rte_spinlock_unlock(&hw->lock);
4264         if (ret)
4265                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4266                          ret);
4267
4268         return ret;
4269 }
4270
4271 static int
4272 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4273 {
4274         struct hns3_hw *hw = &hns->hw;
4275         bool allmulti = hw->data->all_multicast ? true : false;
4276         int ret;
4277
4278         if (hw->data->promiscuous) {
4279                 ret = hns3_set_promisc_mode(hw, true, true);
4280                 if (ret)
4281                         hns3_err(hw, "failed to restore promiscuous mode, "
4282                                  "ret = %d", ret);
4283                 return ret;
4284         }
4285
4286         ret = hns3_set_promisc_mode(hw, false, allmulti);
4287         if (ret)
4288                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4289                          ret);
4290         return ret;
4291 }
4292
4293 static int
4294 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4295 {
4296         struct hns3_sfp_speed_cmd *resp;
4297         struct hns3_cmd_desc desc;
4298         int ret;
4299
4300         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4301         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4302         ret = hns3_cmd_send(hw, &desc, 1);
4303         if (ret == -EOPNOTSUPP) {
4304                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4305                 return ret;
4306         } else if (ret) {
4307                 hns3_err(hw, "get sfp speed failed %d", ret);
4308                 return ret;
4309         }
4310
4311         *speed = resp->sfp_speed;
4312
4313         return 0;
4314 }
4315
4316 static uint8_t
4317 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4318 {
4319         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4320                 duplex = ETH_LINK_FULL_DUPLEX;
4321
4322         return duplex;
4323 }
4324
4325 static int
4326 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4327 {
4328         struct hns3_mac *mac = &hw->mac;
4329         uint32_t cur_speed = mac->link_speed;
4330         int ret;
4331
4332         duplex = hns3_check_speed_dup(duplex, speed);
4333         if (mac->link_speed == speed && mac->link_duplex == duplex)
4334                 return 0;
4335
4336         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4337         if (ret)
4338                 return ret;
4339
4340         mac->link_speed = speed;
4341         ret = hns3_dcb_port_shaper_cfg(hw);
4342         if (ret) {
4343                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4344                 mac->link_speed = cur_speed;
4345                 return ret;
4346         }
4347
4348         mac->link_duplex = duplex;
4349
4350         return 0;
4351 }
4352
4353 static int
4354 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4355 {
4356         struct hns3_adapter *hns = eth_dev->data->dev_private;
4357         struct hns3_hw *hw = &hns->hw;
4358         struct hns3_pf *pf = &hns->pf;
4359         uint32_t speed;
4360         int ret;
4361
4362         /* If IMP do not support get SFP/qSFP speed, return directly */
4363         if (!pf->support_sfp_query)
4364                 return 0;
4365
4366         ret = hns3_get_sfp_speed(hw, &speed);
4367         if (ret == -EOPNOTSUPP) {
4368                 pf->support_sfp_query = false;
4369                 return ret;
4370         } else if (ret)
4371                 return ret;
4372
4373         if (speed == ETH_SPEED_NUM_NONE)
4374                 return 0; /* do nothing if no SFP */
4375
4376         /* Config full duplex for SFP */
4377         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4378 }
4379
4380 static int
4381 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4382 {
4383         struct hns3_config_mac_mode_cmd *req;
4384         struct hns3_cmd_desc desc;
4385         uint32_t loop_en = 0;
4386         uint8_t val = 0;
4387         int ret;
4388
4389         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4390
4391         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4392         if (enable)
4393                 val = 1;
4394         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4395         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4396         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4397         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4398         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4399         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4400         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4401         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4402         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4403         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4404
4405         /*
4406          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4407          * when receiving frames. Otherwise, CRC will be stripped.
4408          */
4409         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4410                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4411         else
4412                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4413         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4414         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4415         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4416         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4417
4418         ret = hns3_cmd_send(hw, &desc, 1);
4419         if (ret)
4420                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4421
4422         return ret;
4423 }
4424
4425 static int
4426 hns3_get_mac_link_status(struct hns3_hw *hw)
4427 {
4428         struct hns3_link_status_cmd *req;
4429         struct hns3_cmd_desc desc;
4430         int link_status;
4431         int ret;
4432
4433         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4434         ret = hns3_cmd_send(hw, &desc, 1);
4435         if (ret) {
4436                 hns3_err(hw, "get link status cmd failed %d", ret);
4437                 return ETH_LINK_DOWN;
4438         }
4439
4440         req = (struct hns3_link_status_cmd *)desc.data;
4441         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4442
4443         return !!link_status;
4444 }
4445
4446 void
4447 hns3_update_link_status(struct hns3_hw *hw)
4448 {
4449         int state;
4450
4451         state = hns3_get_mac_link_status(hw);
4452         if (state != hw->mac.link_status) {
4453                 hw->mac.link_status = state;
4454                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4455         }
4456 }
4457
4458 static void
4459 hns3_service_handler(void *param)
4460 {
4461         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4462         struct hns3_adapter *hns = eth_dev->data->dev_private;
4463         struct hns3_hw *hw = &hns->hw;
4464
4465         if (!hns3_is_reset_pending(hns)) {
4466                 hns3_update_speed_duplex(eth_dev);
4467                 hns3_update_link_status(hw);
4468         } else
4469                 hns3_warn(hw, "Cancel the query when reset is pending");
4470
4471         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4472 }
4473
4474 static int
4475 hns3_init_hardware(struct hns3_adapter *hns)
4476 {
4477         struct hns3_hw *hw = &hns->hw;
4478         int ret;
4479
4480         ret = hns3_map_tqp(hw);
4481         if (ret) {
4482                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4483                 return ret;
4484         }
4485
4486         ret = hns3_init_umv_space(hw);
4487         if (ret) {
4488                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4489                 return ret;
4490         }
4491
4492         ret = hns3_mac_init(hw);
4493         if (ret) {
4494                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4495                 goto err_mac_init;
4496         }
4497
4498         ret = hns3_init_mgr_tbl(hw);
4499         if (ret) {
4500                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4501                 goto err_mac_init;
4502         }
4503
4504         ret = hns3_promisc_init(hw);
4505         if (ret) {
4506                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4507                              ret);
4508                 goto err_mac_init;
4509         }
4510
4511         ret = hns3_init_vlan_config(hns);
4512         if (ret) {
4513                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4514                 goto err_mac_init;
4515         }
4516
4517         ret = hns3_dcb_init(hw);
4518         if (ret) {
4519                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4520                 goto err_mac_init;
4521         }
4522
4523         ret = hns3_init_fd_config(hns);
4524         if (ret) {
4525                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4526                 goto err_mac_init;
4527         }
4528
4529         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4530         if (ret) {
4531                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4532                 goto err_mac_init;
4533         }
4534
4535         ret = hns3_config_gro(hw, false);
4536         if (ret) {
4537                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4538                 goto err_mac_init;
4539         }
4540
4541         /*
4542          * In the initialization clearing the all hardware mapping relationship
4543          * configurations between queues and interrupt vectors is needed, so
4544          * some error caused by the residual configurations, such as the
4545          * unexpected interrupt, can be avoid.
4546          */
4547         ret = hns3_init_ring_with_vector(hw);
4548         if (ret) {
4549                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4550                 goto err_mac_init;
4551         }
4552
4553         return 0;
4554
4555 err_mac_init:
4556         hns3_uninit_umv_space(hw);
4557         return ret;
4558 }
4559
4560 static int
4561 hns3_clear_hw(struct hns3_hw *hw)
4562 {
4563         struct hns3_cmd_desc desc;
4564         int ret;
4565
4566         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4567
4568         ret = hns3_cmd_send(hw, &desc, 1);
4569         if (ret && ret != -EOPNOTSUPP)
4570                 return ret;
4571
4572         return 0;
4573 }
4574
4575 static void
4576 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4577 {
4578         uint32_t val;
4579
4580         /*
4581          * The new firmware support report more hardware error types by
4582          * msix mode. These errors are defined as RAS errors in hardware
4583          * and belong to a different type from the MSI-x errors processed
4584          * by the network driver.
4585          *
4586          * Network driver should open the new error report on initialition
4587          */
4588         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4589         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4590         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4591 }
4592
4593 static int
4594 hns3_init_pf(struct rte_eth_dev *eth_dev)
4595 {
4596         struct rte_device *dev = eth_dev->device;
4597         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4598         struct hns3_adapter *hns = eth_dev->data->dev_private;
4599         struct hns3_hw *hw = &hns->hw;
4600         int ret;
4601
4602         PMD_INIT_FUNC_TRACE();
4603
4604         /* Get hardware io base address from pcie BAR2 IO space */
4605         hw->io_base = pci_dev->mem_resource[2].addr;
4606
4607         /* Firmware command queue initialize */
4608         ret = hns3_cmd_init_queue(hw);
4609         if (ret) {
4610                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4611                 goto err_cmd_init_queue;
4612         }
4613
4614         hns3_clear_all_event_cause(hw);
4615
4616         /* Firmware command initialize */
4617         ret = hns3_cmd_init(hw);
4618         if (ret) {
4619                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4620                 goto err_cmd_init;
4621         }
4622
4623         /*
4624          * To ensure that the hardware environment is clean during
4625          * initialization, the driver actively clear the hardware environment
4626          * during initialization, including PF and corresponding VFs' vlan, mac,
4627          * flow table configurations, etc.
4628          */
4629         ret = hns3_clear_hw(hw);
4630         if (ret) {
4631                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4632                 goto err_cmd_init;
4633         }
4634
4635         hns3_config_all_msix_error(hw, true);
4636
4637         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4638                                          hns3_interrupt_handler,
4639                                          eth_dev);
4640         if (ret) {
4641                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4642                 goto err_intr_callback_register;
4643         }
4644
4645         /* Enable interrupt */
4646         rte_intr_enable(&pci_dev->intr_handle);
4647         hns3_pf_enable_irq0(hw);
4648
4649         /* Get configuration */
4650         ret = hns3_get_configuration(hw);
4651         if (ret) {
4652                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4653                 goto err_get_config;
4654         }
4655
4656         ret = hns3_tqp_stats_init(hw);
4657         if (ret)
4658                 goto err_get_config;
4659
4660         ret = hns3_init_hardware(hns);
4661         if (ret) {
4662                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4663                 goto err_init_hw;
4664         }
4665
4666         /* Initialize flow director filter list & hash */
4667         ret = hns3_fdir_filter_init(hns);
4668         if (ret) {
4669                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4670                 goto err_fdir;
4671         }
4672
4673         hns3_set_default_rss_args(hw);
4674
4675         ret = hns3_enable_hw_error_intr(hns, true);
4676         if (ret) {
4677                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4678                              ret);
4679                 goto err_enable_intr;
4680         }
4681
4682         return 0;
4683
4684 err_enable_intr:
4685         hns3_fdir_filter_uninit(hns);
4686 err_fdir:
4687         hns3_uninit_umv_space(hw);
4688 err_init_hw:
4689         hns3_tqp_stats_uninit(hw);
4690 err_get_config:
4691         hns3_pf_disable_irq0(hw);
4692         rte_intr_disable(&pci_dev->intr_handle);
4693         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4694                              eth_dev);
4695 err_intr_callback_register:
4696 err_cmd_init:
4697         hns3_cmd_uninit(hw);
4698         hns3_cmd_destroy_queue(hw);
4699 err_cmd_init_queue:
4700         hw->io_base = NULL;
4701
4702         return ret;
4703 }
4704
4705 static void
4706 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4707 {
4708         struct hns3_adapter *hns = eth_dev->data->dev_private;
4709         struct rte_device *dev = eth_dev->device;
4710         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4711         struct hns3_hw *hw = &hns->hw;
4712
4713         PMD_INIT_FUNC_TRACE();
4714
4715         hns3_enable_hw_error_intr(hns, false);
4716         hns3_rss_uninit(hns);
4717         (void)hns3_config_gro(hw, false);
4718         hns3_promisc_uninit(hw);
4719         hns3_fdir_filter_uninit(hns);
4720         hns3_uninit_umv_space(hw);
4721         hns3_tqp_stats_uninit(hw);
4722         hns3_pf_disable_irq0(hw);
4723         rte_intr_disable(&pci_dev->intr_handle);
4724         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4725                              eth_dev);
4726         hns3_config_all_msix_error(hw, false);
4727         hns3_cmd_uninit(hw);
4728         hns3_cmd_destroy_queue(hw);
4729         hw->io_base = NULL;
4730 }
4731
4732 static int
4733 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4734 {
4735         struct hns3_hw *hw = &hns->hw;
4736         int ret;
4737
4738         ret = hns3_dcb_cfg_update(hns);
4739         if (ret)
4740                 return ret;
4741
4742         ret = hns3_init_queues(hns, reset_queue);
4743         if (ret) {
4744                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4745                 return ret;
4746         }
4747
4748         ret = hns3_cfg_mac_mode(hw, true);
4749         if (ret) {
4750                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4751                 goto err_config_mac_mode;
4752         }
4753         return 0;
4754
4755 err_config_mac_mode:
4756         hns3_dev_release_mbufs(hns);
4757         /*
4758          * Here is exception handling, hns3_reset_all_tqps will have the
4759          * corresponding error message if it is handled incorrectly, so it is
4760          * not necessary to check hns3_reset_all_tqps return value, here keep
4761          * ret as the error code causing the exception.
4762          */
4763         (void)hns3_reset_all_tqps(hns);
4764         return ret;
4765 }
4766
4767 static int
4768 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4769 {
4770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4771         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4772         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4773         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4774         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4775         uint32_t intr_vector;
4776         uint16_t q_id;
4777         int ret;
4778
4779         if (dev->data->dev_conf.intr_conf.rxq == 0)
4780                 return 0;
4781
4782         /* disable uio/vfio intr/eventfd mapping */
4783         rte_intr_disable(intr_handle);
4784
4785         /* check and configure queue intr-vector mapping */
4786         if (rte_intr_cap_multiple(intr_handle) ||
4787             !RTE_ETH_DEV_SRIOV(dev).active) {
4788                 intr_vector = hw->used_rx_queues;
4789                 /* creates event fd for each intr vector when MSIX is used */
4790                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4791                         return -EINVAL;
4792         }
4793         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4794                 intr_handle->intr_vec =
4795                         rte_zmalloc("intr_vec",
4796                                     hw->used_rx_queues * sizeof(int), 0);
4797                 if (intr_handle->intr_vec == NULL) {
4798                         hns3_err(hw, "Failed to allocate %u rx_queues"
4799                                      " intr_vec", hw->used_rx_queues);
4800                         ret = -ENOMEM;
4801                         goto alloc_intr_vec_error;
4802                 }
4803         }
4804
4805         if (rte_intr_allow_others(intr_handle)) {
4806                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4807                 base = RTE_INTR_VEC_RXTX_OFFSET;
4808         }
4809         if (rte_intr_dp_is_en(intr_handle)) {
4810                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4811                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4812                                                          HNS3_RING_TYPE_RX,
4813                                                          q_id);
4814                         if (ret)
4815                                 goto bind_vector_error;
4816                         intr_handle->intr_vec[q_id] = vec;
4817                         if (vec < base + intr_handle->nb_efd - 1)
4818                                 vec++;
4819                 }
4820         }
4821         rte_intr_enable(intr_handle);
4822         return 0;
4823
4824 bind_vector_error:
4825         rte_intr_efd_disable(intr_handle);
4826         if (intr_handle->intr_vec) {
4827                 free(intr_handle->intr_vec);
4828                 intr_handle->intr_vec = NULL;
4829         }
4830         return ret;
4831 alloc_intr_vec_error:
4832         rte_intr_efd_disable(intr_handle);
4833         return ret;
4834 }
4835
4836 static int
4837 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4838 {
4839         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4840         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4841         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4842         uint16_t q_id;
4843         int ret;
4844
4845         if (dev->data->dev_conf.intr_conf.rxq == 0)
4846                 return 0;
4847
4848         if (rte_intr_dp_is_en(intr_handle)) {
4849                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4850                         ret = hns3_bind_ring_with_vector(hw,
4851                                         intr_handle->intr_vec[q_id], true,
4852                                         HNS3_RING_TYPE_RX, q_id);
4853                         if (ret)
4854                                 return ret;
4855                 }
4856         }
4857
4858         return 0;
4859 }
4860
4861 static void
4862 hns3_restore_filter(struct rte_eth_dev *dev)
4863 {
4864         hns3_restore_rss_filter(dev);
4865 }
4866
4867 static int
4868 hns3_dev_start(struct rte_eth_dev *dev)
4869 {
4870         struct hns3_adapter *hns = dev->data->dev_private;
4871         struct hns3_hw *hw = &hns->hw;
4872         int ret;
4873
4874         PMD_INIT_FUNC_TRACE();
4875         if (rte_atomic16_read(&hw->reset.resetting))
4876                 return -EBUSY;
4877
4878         rte_spinlock_lock(&hw->lock);
4879         hw->adapter_state = HNS3_NIC_STARTING;
4880
4881         ret = hns3_do_start(hns, true);
4882         if (ret) {
4883                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4884                 rte_spinlock_unlock(&hw->lock);
4885                 return ret;
4886         }
4887         ret = hns3_map_rx_interrupt(dev);
4888         if (ret) {
4889                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4890                 rte_spinlock_unlock(&hw->lock);
4891                 return ret;
4892         }
4893
4894         /*
4895          * There are three register used to control the status of a TQP
4896          * (contains a pair of Tx queue and Rx queue) in the new version network
4897          * engine. One is used to control the enabling of Tx queue, the other is
4898          * used to control the enabling of Rx queue, and the last is the master
4899          * switch used to control the enabling of the tqp. The Tx register and
4900          * TQP register must be enabled at the same time to enable a Tx queue.
4901          * The same applies to the Rx queue. For the older network engine, this
4902          * function only refresh the enabled flag, and it is used to update the
4903          * status of queue in the dpdk framework.
4904          */
4905         ret = hns3_start_all_txqs(dev);
4906         if (ret) {
4907                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4908                 rte_spinlock_unlock(&hw->lock);
4909                 return ret;
4910         }
4911
4912         ret = hns3_start_all_rxqs(dev);
4913         if (ret) {
4914                 hns3_stop_all_txqs(dev);
4915                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4916                 rte_spinlock_unlock(&hw->lock);
4917                 return ret;
4918         }
4919
4920         hw->adapter_state = HNS3_NIC_STARTED;
4921         rte_spinlock_unlock(&hw->lock);
4922
4923         hns3_rx_scattered_calc(dev);
4924         hns3_set_rxtx_function(dev);
4925         hns3_mp_req_start_rxtx(dev);
4926         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4927
4928         hns3_restore_filter(dev);
4929
4930         /* Enable interrupt of all rx queues before enabling queues */
4931         hns3_dev_all_rx_queue_intr_enable(hw, true);
4932
4933         /*
4934          * After finished the initialization, enable tqps to receive/transmit
4935          * packets and refresh all queue status.
4936          */
4937         hns3_start_tqps(hw);
4938
4939         hns3_info(hw, "hns3 dev start successful!");
4940         return 0;
4941 }
4942
4943 static int
4944 hns3_do_stop(struct hns3_adapter *hns)
4945 {
4946         struct hns3_hw *hw = &hns->hw;
4947         int ret;
4948
4949         ret = hns3_cfg_mac_mode(hw, false);
4950         if (ret)
4951                 return ret;
4952         hw->mac.link_status = ETH_LINK_DOWN;
4953
4954         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4955                 hns3_configure_all_mac_addr(hns, true);
4956                 ret = hns3_reset_all_tqps(hns);
4957                 if (ret) {
4958                         hns3_err(hw, "failed to reset all queues ret = %d.",
4959                                  ret);
4960                         return ret;
4961                 }
4962         }
4963         hw->mac.default_addr_setted = false;
4964         return 0;
4965 }
4966
4967 static void
4968 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4969 {
4970         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4971         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4972         struct hns3_adapter *hns = dev->data->dev_private;
4973         struct hns3_hw *hw = &hns->hw;
4974         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4975         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4976         uint16_t q_id;
4977
4978         if (dev->data->dev_conf.intr_conf.rxq == 0)
4979                 return;
4980
4981         /* unmap the ring with vector */
4982         if (rte_intr_allow_others(intr_handle)) {
4983                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4984                 base = RTE_INTR_VEC_RXTX_OFFSET;
4985         }
4986         if (rte_intr_dp_is_en(intr_handle)) {
4987                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4988                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4989                                                          HNS3_RING_TYPE_RX,
4990                                                          q_id);
4991                         if (vec < base + intr_handle->nb_efd - 1)
4992                                 vec++;
4993                 }
4994         }
4995         /* Clean datapath event and queue/vec mapping */
4996         rte_intr_efd_disable(intr_handle);
4997         if (intr_handle->intr_vec) {
4998                 rte_free(intr_handle->intr_vec);
4999                 intr_handle->intr_vec = NULL;
5000         }
5001 }
5002
5003 static int
5004 hns3_dev_stop(struct rte_eth_dev *dev)
5005 {
5006         struct hns3_adapter *hns = dev->data->dev_private;
5007         struct hns3_hw *hw = &hns->hw;
5008
5009         PMD_INIT_FUNC_TRACE();
5010         dev->data->dev_started = 0;
5011
5012         hw->adapter_state = HNS3_NIC_STOPPING;
5013         hns3_set_rxtx_function(dev);
5014         rte_wmb();
5015         /* Disable datapath on secondary process. */
5016         hns3_mp_req_stop_rxtx(dev);
5017         /* Prevent crashes when queues are still in use. */
5018         rte_delay_ms(hw->tqps_num);
5019
5020         rte_spinlock_lock(&hw->lock);
5021         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
5022                 hns3_stop_tqps(hw);
5023                 hns3_do_stop(hns);
5024                 hns3_unmap_rx_interrupt(dev);
5025                 hns3_dev_release_mbufs(hns);
5026                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5027         }
5028         hns3_rx_scattered_reset(dev);
5029         rte_eal_alarm_cancel(hns3_service_handler, dev);
5030         rte_spinlock_unlock(&hw->lock);
5031
5032         return 0;
5033 }
5034
5035 static int
5036 hns3_dev_close(struct rte_eth_dev *eth_dev)
5037 {
5038         struct hns3_adapter *hns = eth_dev->data->dev_private;
5039         struct hns3_hw *hw = &hns->hw;
5040         int ret = 0;
5041
5042         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5043                 rte_free(eth_dev->process_private);
5044                 eth_dev->process_private = NULL;
5045                 return 0;
5046         }
5047
5048         if (hw->adapter_state == HNS3_NIC_STARTED)
5049                 ret = hns3_dev_stop(eth_dev);
5050
5051         hw->adapter_state = HNS3_NIC_CLOSING;
5052         hns3_reset_abort(hns);
5053         hw->adapter_state = HNS3_NIC_CLOSED;
5054
5055         hns3_configure_all_mc_mac_addr(hns, true);
5056         hns3_remove_all_vlan_table(hns);
5057         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5058         hns3_uninit_pf(eth_dev);
5059         hns3_free_all_queues(eth_dev);
5060         rte_free(hw->reset.wait_data);
5061         rte_free(eth_dev->process_private);
5062         eth_dev->process_private = NULL;
5063         hns3_mp_uninit_primary();
5064         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5065
5066         return ret;
5067 }
5068
5069 static int
5070 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5071 {
5072         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5074
5075         fc_conf->pause_time = pf->pause_time;
5076
5077         /* return fc current mode */
5078         switch (hw->current_mode) {
5079         case HNS3_FC_FULL:
5080                 fc_conf->mode = RTE_FC_FULL;
5081                 break;
5082         case HNS3_FC_TX_PAUSE:
5083                 fc_conf->mode = RTE_FC_TX_PAUSE;
5084                 break;
5085         case HNS3_FC_RX_PAUSE:
5086                 fc_conf->mode = RTE_FC_RX_PAUSE;
5087                 break;
5088         case HNS3_FC_NONE:
5089         default:
5090                 fc_conf->mode = RTE_FC_NONE;
5091                 break;
5092         }
5093
5094         return 0;
5095 }
5096
5097 static void
5098 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5099 {
5100         switch (mode) {
5101         case RTE_FC_NONE:
5102                 hw->requested_mode = HNS3_FC_NONE;
5103                 break;
5104         case RTE_FC_RX_PAUSE:
5105                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5106                 break;
5107         case RTE_FC_TX_PAUSE:
5108                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5109                 break;
5110         case RTE_FC_FULL:
5111                 hw->requested_mode = HNS3_FC_FULL;
5112                 break;
5113         default:
5114                 hw->requested_mode = HNS3_FC_NONE;
5115                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5116                           "configured to RTE_FC_NONE", mode);
5117                 break;
5118         }
5119 }
5120
5121 static int
5122 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5123 {
5124         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5126         int ret;
5127
5128         if (fc_conf->high_water || fc_conf->low_water ||
5129             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5130                 hns3_err(hw, "Unsupported flow control settings specified, "
5131                          "high_water(%u), low_water(%u), send_xon(%u) and "
5132                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5133                          fc_conf->high_water, fc_conf->low_water,
5134                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5135                 return -EINVAL;
5136         }
5137         if (fc_conf->autoneg) {
5138                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5139                 return -EINVAL;
5140         }
5141         if (!fc_conf->pause_time) {
5142                 hns3_err(hw, "Invalid pause time %u setting.",
5143                          fc_conf->pause_time);
5144                 return -EINVAL;
5145         }
5146
5147         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5148             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5149                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5150                          "current_fc_status = %d", hw->current_fc_status);
5151                 return -EOPNOTSUPP;
5152         }
5153
5154         hns3_get_fc_mode(hw, fc_conf->mode);
5155         if (hw->requested_mode == hw->current_mode &&
5156             pf->pause_time == fc_conf->pause_time)
5157                 return 0;
5158
5159         rte_spinlock_lock(&hw->lock);
5160         ret = hns3_fc_enable(dev, fc_conf);
5161         rte_spinlock_unlock(&hw->lock);
5162
5163         return ret;
5164 }
5165
5166 static int
5167 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5168                             struct rte_eth_pfc_conf *pfc_conf)
5169 {
5170         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5172         uint8_t priority;
5173         int ret;
5174
5175         if (!hns3_dev_dcb_supported(hw)) {
5176                 hns3_err(hw, "This port does not support dcb configurations.");
5177                 return -EOPNOTSUPP;
5178         }
5179
5180         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5181             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5182                 hns3_err(hw, "Unsupported flow control settings specified, "
5183                          "high_water(%u), low_water(%u), send_xon(%u) and "
5184                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5185                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5186                          pfc_conf->fc.send_xon,
5187                          pfc_conf->fc.mac_ctrl_frame_fwd);
5188                 return -EINVAL;
5189         }
5190         if (pfc_conf->fc.autoneg) {
5191                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5192                 return -EINVAL;
5193         }
5194         if (pfc_conf->fc.pause_time == 0) {
5195                 hns3_err(hw, "Invalid pause time %u setting.",
5196                          pfc_conf->fc.pause_time);
5197                 return -EINVAL;
5198         }
5199
5200         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5201             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5202                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5203                              "current_fc_status = %d", hw->current_fc_status);
5204                 return -EOPNOTSUPP;
5205         }
5206
5207         priority = pfc_conf->priority;
5208         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5209         if (hw->dcb_info.pfc_en & BIT(priority) &&
5210             hw->requested_mode == hw->current_mode &&
5211             pfc_conf->fc.pause_time == pf->pause_time)
5212                 return 0;
5213
5214         rte_spinlock_lock(&hw->lock);
5215         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5216         rte_spinlock_unlock(&hw->lock);
5217
5218         return ret;
5219 }
5220
5221 static int
5222 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5223 {
5224         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5226         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5227         int i;
5228
5229         rte_spinlock_lock(&hw->lock);
5230         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5231                 dcb_info->nb_tcs = pf->local_max_tc;
5232         else
5233                 dcb_info->nb_tcs = 1;
5234
5235         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5236                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5237         for (i = 0; i < dcb_info->nb_tcs; i++)
5238                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5239
5240         for (i = 0; i < hw->num_tc; i++) {
5241                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5242                 dcb_info->tc_queue.tc_txq[0][i].base =
5243                                                 hw->tc_queue[i].tqp_offset;
5244                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5245                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5246                                                 hw->tc_queue[i].tqp_count;
5247         }
5248         rte_spinlock_unlock(&hw->lock);
5249
5250         return 0;
5251 }
5252
5253 static int
5254 hns3_reinit_dev(struct hns3_adapter *hns)
5255 {
5256         struct hns3_hw *hw = &hns->hw;
5257         int ret;
5258
5259         ret = hns3_cmd_init(hw);
5260         if (ret) {
5261                 hns3_err(hw, "Failed to init cmd: %d", ret);
5262                 return ret;
5263         }
5264
5265         ret = hns3_reset_all_tqps(hns);
5266         if (ret) {
5267                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5268                 return ret;
5269         }
5270
5271         ret = hns3_init_hardware(hns);
5272         if (ret) {
5273                 hns3_err(hw, "Failed to init hardware: %d", ret);
5274                 return ret;
5275         }
5276
5277         ret = hns3_enable_hw_error_intr(hns, true);
5278         if (ret) {
5279                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5280                              ret);
5281                 return ret;
5282         }
5283         hns3_info(hw, "Reset done, driver initialization finished.");
5284
5285         return 0;
5286 }
5287
5288 static bool
5289 is_pf_reset_done(struct hns3_hw *hw)
5290 {
5291         uint32_t val, reg, reg_bit;
5292
5293         switch (hw->reset.level) {
5294         case HNS3_IMP_RESET:
5295                 reg = HNS3_GLOBAL_RESET_REG;
5296                 reg_bit = HNS3_IMP_RESET_BIT;
5297                 break;
5298         case HNS3_GLOBAL_RESET:
5299                 reg = HNS3_GLOBAL_RESET_REG;
5300                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5301                 break;
5302         case HNS3_FUNC_RESET:
5303                 reg = HNS3_FUN_RST_ING;
5304                 reg_bit = HNS3_FUN_RST_ING_B;
5305                 break;
5306         case HNS3_FLR_RESET:
5307         default:
5308                 hns3_err(hw, "Wait for unsupported reset level: %d",
5309                          hw->reset.level);
5310                 return true;
5311         }
5312         val = hns3_read_dev(hw, reg);
5313         if (hns3_get_bit(val, reg_bit))
5314                 return false;
5315         else
5316                 return true;
5317 }
5318
5319 bool
5320 hns3_is_reset_pending(struct hns3_adapter *hns)
5321 {
5322         struct hns3_hw *hw = &hns->hw;
5323         enum hns3_reset_level reset;
5324
5325         hns3_check_event_cause(hns, NULL);
5326         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5327         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5328                 hns3_warn(hw, "High level reset %d is pending", reset);
5329                 return true;
5330         }
5331         reset = hns3_get_reset_level(hns, &hw->reset.request);
5332         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5333                 hns3_warn(hw, "High level reset %d is request", reset);
5334                 return true;
5335         }
5336         return false;
5337 }
5338
5339 static int
5340 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5341 {
5342         struct hns3_hw *hw = &hns->hw;
5343         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5344         struct timeval tv;
5345
5346         if (wait_data->result == HNS3_WAIT_SUCCESS)
5347                 return 0;
5348         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5349                 gettimeofday(&tv, NULL);
5350                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5351                           tv.tv_sec, tv.tv_usec);
5352                 return -ETIME;
5353         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5354                 return -EAGAIN;
5355
5356         wait_data->hns = hns;
5357         wait_data->check_completion = is_pf_reset_done;
5358         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5359                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5360         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5361         wait_data->count = HNS3_RESET_WAIT_CNT;
5362         wait_data->result = HNS3_WAIT_REQUEST;
5363         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5364         return -EAGAIN;
5365 }
5366
5367 static int
5368 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5369 {
5370         struct hns3_cmd_desc desc;
5371         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5372
5373         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5374         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5375         req->fun_reset_vfid = func_id;
5376
5377         return hns3_cmd_send(hw, &desc, 1);
5378 }
5379
5380 static int
5381 hns3_imp_reset_cmd(struct hns3_hw *hw)
5382 {
5383         struct hns3_cmd_desc desc;
5384
5385         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5386         desc.data[0] = 0xeedd;
5387
5388         return hns3_cmd_send(hw, &desc, 1);
5389 }
5390
5391 static void
5392 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5393 {
5394         struct hns3_hw *hw = &hns->hw;
5395         struct timeval tv;
5396         uint32_t val;
5397
5398         gettimeofday(&tv, NULL);
5399         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5400             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5401                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5402                           tv.tv_sec, tv.tv_usec);
5403                 return;
5404         }
5405
5406         switch (reset_level) {
5407         case HNS3_IMP_RESET:
5408                 hns3_imp_reset_cmd(hw);
5409                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5410                           tv.tv_sec, tv.tv_usec);
5411                 break;
5412         case HNS3_GLOBAL_RESET:
5413                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5414                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5415                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5416                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5417                           tv.tv_sec, tv.tv_usec);
5418                 break;
5419         case HNS3_FUNC_RESET:
5420                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5421                           tv.tv_sec, tv.tv_usec);
5422                 /* schedule again to check later */
5423                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5424                 hns3_schedule_reset(hns);
5425                 break;
5426         default:
5427                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5428                 return;
5429         }
5430         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5431 }
5432
5433 static enum hns3_reset_level
5434 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5435 {
5436         struct hns3_hw *hw = &hns->hw;
5437         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5438
5439         /* Return the highest priority reset level amongst all */
5440         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5441                 reset_level = HNS3_IMP_RESET;
5442         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5443                 reset_level = HNS3_GLOBAL_RESET;
5444         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5445                 reset_level = HNS3_FUNC_RESET;
5446         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5447                 reset_level = HNS3_FLR_RESET;
5448
5449         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5450                 return HNS3_NONE_RESET;
5451
5452         return reset_level;
5453 }
5454
5455 static void
5456 hns3_record_imp_error(struct hns3_adapter *hns)
5457 {
5458         struct hns3_hw *hw = &hns->hw;
5459         uint32_t reg_val;
5460
5461         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5462         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5463                 hns3_warn(hw, "Detected IMP RD poison!");
5464                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5465                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5466                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5467         }
5468
5469         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5470                 hns3_warn(hw, "Detected IMP CMDQ error!");
5471                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5472                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5473                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5474         }
5475 }
5476
5477 static int
5478 hns3_prepare_reset(struct hns3_adapter *hns)
5479 {
5480         struct hns3_hw *hw = &hns->hw;
5481         uint32_t reg_val;
5482         int ret;
5483
5484         switch (hw->reset.level) {
5485         case HNS3_FUNC_RESET:
5486                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5487                 if (ret)
5488                         return ret;
5489
5490                 /*
5491                  * After performaning pf reset, it is not necessary to do the
5492                  * mailbox handling or send any command to firmware, because
5493                  * any mailbox handling or command to firmware is only valid
5494                  * after hns3_cmd_init is called.
5495                  */
5496                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5497                 hw->reset.stats.request_cnt++;
5498                 break;
5499         case HNS3_IMP_RESET:
5500                 hns3_record_imp_error(hns);
5501                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5502                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5503                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5504                 break;
5505         default:
5506                 break;
5507         }
5508         return 0;
5509 }
5510
5511 static int
5512 hns3_set_rst_done(struct hns3_hw *hw)
5513 {
5514         struct hns3_pf_rst_done_cmd *req;
5515         struct hns3_cmd_desc desc;
5516
5517         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5518         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5519         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5520         return hns3_cmd_send(hw, &desc, 1);
5521 }
5522
5523 static int
5524 hns3_stop_service(struct hns3_adapter *hns)
5525 {
5526         struct hns3_hw *hw = &hns->hw;
5527         struct rte_eth_dev *eth_dev;
5528
5529         eth_dev = &rte_eth_devices[hw->data->port_id];
5530         if (hw->adapter_state == HNS3_NIC_STARTED)
5531                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5532         hw->mac.link_status = ETH_LINK_DOWN;
5533
5534         hns3_set_rxtx_function(eth_dev);
5535         rte_wmb();
5536         /* Disable datapath on secondary process. */
5537         hns3_mp_req_stop_rxtx(eth_dev);
5538         rte_delay_ms(hw->tqps_num);
5539
5540         rte_spinlock_lock(&hw->lock);
5541         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5542             hw->adapter_state == HNS3_NIC_STOPPING) {
5543                 hns3_enable_all_queues(hw, false);
5544                 hns3_do_stop(hns);
5545                 hw->reset.mbuf_deferred_free = true;
5546         } else
5547                 hw->reset.mbuf_deferred_free = false;
5548
5549         /*
5550          * It is cumbersome for hardware to pick-and-choose entries for deletion
5551          * from table space. Hence, for function reset software intervention is
5552          * required to delete the entries
5553          */
5554         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5555                 hns3_configure_all_mc_mac_addr(hns, true);
5556         rte_spinlock_unlock(&hw->lock);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 hns3_start_service(struct hns3_adapter *hns)
5563 {
5564         struct hns3_hw *hw = &hns->hw;
5565         struct rte_eth_dev *eth_dev;
5566
5567         if (hw->reset.level == HNS3_IMP_RESET ||
5568             hw->reset.level == HNS3_GLOBAL_RESET)
5569                 hns3_set_rst_done(hw);
5570         eth_dev = &rte_eth_devices[hw->data->port_id];
5571         hns3_set_rxtx_function(eth_dev);
5572         hns3_mp_req_start_rxtx(eth_dev);
5573         if (hw->adapter_state == HNS3_NIC_STARTED) {
5574                 hns3_service_handler(eth_dev);
5575
5576                 /* Enable interrupt of all rx queues before enabling queues */
5577                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5578                 /*
5579                  * Enable state of each rxq and txq will be recovered after
5580                  * reset, so we need to restore them before enable all tqps;
5581                  */
5582                 hns3_restore_tqp_enable_state(hw);
5583                 /*
5584                  * When finished the initialization, enable queues to receive
5585                  * and transmit packets.
5586                  */
5587                 hns3_enable_all_queues(hw, true);
5588         }
5589
5590         return 0;
5591 }
5592
5593 static int
5594 hns3_restore_conf(struct hns3_adapter *hns)
5595 {
5596         struct hns3_hw *hw = &hns->hw;
5597         int ret;
5598
5599         ret = hns3_configure_all_mac_addr(hns, false);
5600         if (ret)
5601                 return ret;
5602
5603         ret = hns3_configure_all_mc_mac_addr(hns, false);
5604         if (ret)
5605                 goto err_mc_mac;
5606
5607         ret = hns3_dev_promisc_restore(hns);
5608         if (ret)
5609                 goto err_promisc;
5610
5611         ret = hns3_restore_vlan_table(hns);
5612         if (ret)
5613                 goto err_promisc;
5614
5615         ret = hns3_restore_vlan_conf(hns);
5616         if (ret)
5617                 goto err_promisc;
5618
5619         ret = hns3_restore_all_fdir_filter(hns);
5620         if (ret)
5621                 goto err_promisc;
5622
5623         ret = hns3_restore_rx_interrupt(hw);
5624         if (ret)
5625                 goto err_promisc;
5626
5627         ret = hns3_restore_gro_conf(hw);
5628         if (ret)
5629                 goto err_promisc;
5630
5631         ret = hns3_restore_fec(hw);
5632         if (ret)
5633                 goto err_promisc;
5634
5635         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5636                 ret = hns3_do_start(hns, false);
5637                 if (ret)
5638                         goto err_promisc;
5639                 hns3_info(hw, "hns3 dev restart successful!");
5640         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5641                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5642         return 0;
5643
5644 err_promisc:
5645         hns3_configure_all_mc_mac_addr(hns, true);
5646 err_mc_mac:
5647         hns3_configure_all_mac_addr(hns, true);
5648         return ret;
5649 }
5650
5651 static void
5652 hns3_reset_service(void *param)
5653 {
5654         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5655         struct hns3_hw *hw = &hns->hw;
5656         enum hns3_reset_level reset_level;
5657         struct timeval tv_delta;
5658         struct timeval tv_start;
5659         struct timeval tv;
5660         uint64_t msec;
5661         int ret;
5662
5663         /*
5664          * The interrupt is not triggered within the delay time.
5665          * The interrupt may have been lost. It is necessary to handle
5666          * the interrupt to recover from the error.
5667          */
5668         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5669                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5670                 hns3_err(hw, "Handling interrupts in delayed tasks");
5671                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5672                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5673                 if (reset_level == HNS3_NONE_RESET) {
5674                         hns3_err(hw, "No reset level is set, try IMP reset");
5675                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5676                 }
5677         }
5678         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5679
5680         /*
5681          * Check if there is any ongoing reset in the hardware. This status can
5682          * be checked from reset_pending. If there is then, we need to wait for
5683          * hardware to complete reset.
5684          *    a. If we are able to figure out in reasonable time that hardware
5685          *       has fully resetted then, we can proceed with driver, client
5686          *       reset.
5687          *    b. else, we can come back later to check this status so re-sched
5688          *       now.
5689          */
5690         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5691         if (reset_level != HNS3_NONE_RESET) {
5692                 gettimeofday(&tv_start, NULL);
5693                 ret = hns3_reset_process(hns, reset_level);
5694                 gettimeofday(&tv, NULL);
5695                 timersub(&tv, &tv_start, &tv_delta);
5696                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5697                        tv_delta.tv_usec / USEC_PER_MSEC;
5698                 if (msec > HNS3_RESET_PROCESS_MS)
5699                         hns3_err(hw, "%d handle long time delta %" PRIx64
5700                                      " ms time=%ld.%.6ld",
5701                                  hw->reset.level, msec,
5702                                  tv.tv_sec, tv.tv_usec);
5703                 if (ret == -EAGAIN)
5704                         return;
5705         }
5706
5707         /* Check if we got any *new* reset requests to be honored */
5708         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5709         if (reset_level != HNS3_NONE_RESET)
5710                 hns3_msix_process(hns, reset_level);
5711 }
5712
5713 static unsigned int
5714 hns3_get_speed_capa_num(uint16_t device_id)
5715 {
5716         unsigned int num;
5717
5718         switch (device_id) {
5719         case HNS3_DEV_ID_25GE:
5720         case HNS3_DEV_ID_25GE_RDMA:
5721                 num = 2;
5722                 break;
5723         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5724         case HNS3_DEV_ID_200G_RDMA:
5725                 num = 1;
5726                 break;
5727         default:
5728                 num = 0;
5729                 break;
5730         }
5731
5732         return num;
5733 }
5734
5735 static int
5736 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5737                         uint16_t device_id)
5738 {
5739         switch (device_id) {
5740         case HNS3_DEV_ID_25GE:
5741         /* fallthrough */
5742         case HNS3_DEV_ID_25GE_RDMA:
5743                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5744                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5745
5746                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5747                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5748                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5749                 break;
5750         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5751                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5752                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5753                 break;
5754         case HNS3_DEV_ID_200G_RDMA:
5755                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5756                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5757                 break;
5758         default:
5759                 return -ENOTSUP;
5760         }
5761
5762         return 0;
5763 }
5764
5765 static int
5766 hns3_fec_get_capability(struct rte_eth_dev *dev,
5767                         struct rte_eth_fec_capa *speed_fec_capa,
5768                         unsigned int num)
5769 {
5770         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5771         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5772         uint16_t device_id = pci_dev->id.device_id;
5773         unsigned int capa_num;
5774         int ret;
5775
5776         capa_num = hns3_get_speed_capa_num(device_id);
5777         if (capa_num == 0) {
5778                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5779                          device_id);
5780                 return -ENOTSUP;
5781         }
5782
5783         if (speed_fec_capa == NULL || num < capa_num)
5784                 return capa_num;
5785
5786         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5787         if (ret)
5788                 return -ENOTSUP;
5789
5790         return capa_num;
5791 }
5792
5793 static int
5794 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5795 {
5796         struct hns3_config_fec_cmd *req;
5797         struct hns3_cmd_desc desc;
5798         int ret;
5799
5800         /*
5801          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5802          * in device of link speed
5803          * below 10 Gbps.
5804          */
5805         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5806                 *state = 0;
5807                 return 0;
5808         }
5809
5810         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5811         req = (struct hns3_config_fec_cmd *)desc.data;
5812         ret = hns3_cmd_send(hw, &desc, 1);
5813         if (ret) {
5814                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5815                          ret);
5816                 return ret;
5817         }
5818
5819         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5820         return 0;
5821 }
5822
5823 static int
5824 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5825 {
5826 #define QUERY_ACTIVE_SPEED      1
5827         struct hns3_sfp_speed_cmd *resp;
5828         uint32_t tmp_fec_capa;
5829         uint8_t auto_state;
5830         struct hns3_cmd_desc desc;
5831         int ret;
5832
5833         /*
5834          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5835          * configured FEC mode is returned.
5836          * If link is up, current FEC mode is returned.
5837          */
5838         if (hw->mac.link_status == ETH_LINK_DOWN) {
5839                 ret = get_current_fec_auto_state(hw, &auto_state);
5840                 if (ret)
5841                         return ret;
5842
5843                 if (auto_state == 0x1) {
5844                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5845                         return 0;
5846                 }
5847         }
5848
5849         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5850         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5851         resp->query_type = QUERY_ACTIVE_SPEED;
5852
5853         ret = hns3_cmd_send(hw, &desc, 1);
5854         if (ret == -EOPNOTSUPP) {
5855                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5856                 return ret;
5857         } else if (ret) {
5858                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5859                 return ret;
5860         }
5861
5862         /*
5863          * FEC mode order defined in hns3 hardware is inconsistend with
5864          * that defined in the ethdev library. So the sequence needs
5865          * to be converted.
5866          */
5867         switch (resp->active_fec) {
5868         case HNS3_HW_FEC_MODE_NOFEC:
5869                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5870                 break;
5871         case HNS3_HW_FEC_MODE_BASER:
5872                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5873                 break;
5874         case HNS3_HW_FEC_MODE_RS:
5875                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5876                 break;
5877         default:
5878                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5879                 break;
5880         }
5881
5882         *fec_capa = tmp_fec_capa;
5883         return 0;
5884 }
5885
5886 static int
5887 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5888 {
5889         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5890
5891         return hns3_fec_get_internal(hw, fec_capa);
5892 }
5893
5894 static int
5895 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5896 {
5897         struct hns3_config_fec_cmd *req;
5898         struct hns3_cmd_desc desc;
5899         int ret;
5900
5901         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5902
5903         req = (struct hns3_config_fec_cmd *)desc.data;
5904         switch (mode) {
5905         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5906                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5907                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5908                 break;
5909         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5910                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5911                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5912                 break;
5913         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5914                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5915                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5916                 break;
5917         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5918                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5919                 break;
5920         default:
5921                 return 0;
5922         }
5923         ret = hns3_cmd_send(hw, &desc, 1);
5924         if (ret)
5925                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5926
5927         return ret;
5928 }
5929
5930 static uint32_t
5931 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5932 {
5933         struct hns3_mac *mac = &hw->mac;
5934         uint32_t cur_capa;
5935
5936         switch (mac->link_speed) {
5937         case ETH_SPEED_NUM_10G:
5938                 cur_capa = fec_capa[1].capa;
5939                 break;
5940         case ETH_SPEED_NUM_25G:
5941         case ETH_SPEED_NUM_100G:
5942         case ETH_SPEED_NUM_200G:
5943                 cur_capa = fec_capa[0].capa;
5944                 break;
5945         default:
5946                 cur_capa = 0;
5947                 break;
5948         }
5949
5950         return cur_capa;
5951 }
5952
5953 static bool
5954 is_fec_mode_one_bit_set(uint32_t mode)
5955 {
5956         int cnt = 0;
5957         uint8_t i;
5958
5959         for (i = 0; i < sizeof(mode); i++)
5960                 if (mode >> i & 0x1)
5961                         cnt++;
5962
5963         return cnt == 1 ? true : false;
5964 }
5965
5966 static int
5967 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5968 {
5969 #define FEC_CAPA_NUM 2
5970         struct hns3_adapter *hns = dev->data->dev_private;
5971         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5972         struct hns3_pf *pf = &hns->pf;
5973
5974         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5975         uint32_t cur_capa;
5976         uint32_t num = FEC_CAPA_NUM;
5977         int ret;
5978
5979         ret = hns3_fec_get_capability(dev, fec_capa, num);
5980         if (ret < 0)
5981                 return ret;
5982
5983         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5984         if (!is_fec_mode_one_bit_set(mode))
5985                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
5986                              "FEC mode should be only one bit set", mode);
5987
5988         /*
5989          * Check whether the configured mode is within the FEC capability.
5990          * If not, the configured mode will not be supported.
5991          */
5992         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
5993         if (!(cur_capa & mode)) {
5994                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
5995                 return -EINVAL;
5996         }
5997
5998         ret = hns3_set_fec_hw(hw, mode);
5999         if (ret)
6000                 return ret;
6001
6002         pf->fec_mode = mode;
6003         return 0;
6004 }
6005
6006 static int
6007 hns3_restore_fec(struct hns3_hw *hw)
6008 {
6009         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6010         struct hns3_pf *pf = &hns->pf;
6011         uint32_t mode = pf->fec_mode;
6012         int ret;
6013
6014         ret = hns3_set_fec_hw(hw, mode);
6015         if (ret)
6016                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6017                          mode, ret);
6018
6019         return ret;
6020 }
6021
6022 static int
6023 hns3_query_dev_fec_info(struct hns3_hw *hw)
6024 {
6025         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6026         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6027         int ret;
6028
6029         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6030         if (ret)
6031                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6032
6033         return ret;
6034 }
6035
6036 static const struct eth_dev_ops hns3_eth_dev_ops = {
6037         .dev_configure      = hns3_dev_configure,
6038         .dev_start          = hns3_dev_start,
6039         .dev_stop           = hns3_dev_stop,
6040         .dev_close          = hns3_dev_close,
6041         .promiscuous_enable = hns3_dev_promiscuous_enable,
6042         .promiscuous_disable = hns3_dev_promiscuous_disable,
6043         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6044         .allmulticast_disable = hns3_dev_allmulticast_disable,
6045         .mtu_set            = hns3_dev_mtu_set,
6046         .stats_get          = hns3_stats_get,
6047         .stats_reset        = hns3_stats_reset,
6048         .xstats_get         = hns3_dev_xstats_get,
6049         .xstats_get_names   = hns3_dev_xstats_get_names,
6050         .xstats_reset       = hns3_dev_xstats_reset,
6051         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6052         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6053         .dev_infos_get          = hns3_dev_infos_get,
6054         .fw_version_get         = hns3_fw_version_get,
6055         .rx_queue_setup         = hns3_rx_queue_setup,
6056         .tx_queue_setup         = hns3_tx_queue_setup,
6057         .rx_queue_release       = hns3_dev_rx_queue_release,
6058         .tx_queue_release       = hns3_dev_tx_queue_release,
6059         .rx_queue_start         = hns3_dev_rx_queue_start,
6060         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6061         .tx_queue_start         = hns3_dev_tx_queue_start,
6062         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6063         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6064         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6065         .rxq_info_get           = hns3_rxq_info_get,
6066         .txq_info_get           = hns3_txq_info_get,
6067         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6068         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6069         .flow_ctrl_get          = hns3_flow_ctrl_get,
6070         .flow_ctrl_set          = hns3_flow_ctrl_set,
6071         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6072         .mac_addr_add           = hns3_add_mac_addr,
6073         .mac_addr_remove        = hns3_remove_mac_addr,
6074         .mac_addr_set           = hns3_set_default_mac_addr,
6075         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6076         .link_update            = hns3_dev_link_update,
6077         .rss_hash_update        = hns3_dev_rss_hash_update,
6078         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6079         .reta_update            = hns3_dev_rss_reta_update,
6080         .reta_query             = hns3_dev_rss_reta_query,
6081         .filter_ctrl            = hns3_dev_filter_ctrl,
6082         .vlan_filter_set        = hns3_vlan_filter_set,
6083         .vlan_tpid_set          = hns3_vlan_tpid_set,
6084         .vlan_offload_set       = hns3_vlan_offload_set,
6085         .vlan_pvid_set          = hns3_vlan_pvid_set,
6086         .get_reg                = hns3_get_regs,
6087         .get_dcb_info           = hns3_get_dcb_info,
6088         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6089         .fec_get_capability     = hns3_fec_get_capability,
6090         .fec_get                = hns3_fec_get,
6091         .fec_set                = hns3_fec_set,
6092 };
6093
6094 static const struct hns3_reset_ops hns3_reset_ops = {
6095         .reset_service       = hns3_reset_service,
6096         .stop_service        = hns3_stop_service,
6097         .prepare_reset       = hns3_prepare_reset,
6098         .wait_hardware_ready = hns3_wait_hardware_ready,
6099         .reinit_dev          = hns3_reinit_dev,
6100         .restore_conf        = hns3_restore_conf,
6101         .start_service       = hns3_start_service,
6102 };
6103
6104 static int
6105 hns3_dev_init(struct rte_eth_dev *eth_dev)
6106 {
6107         struct hns3_adapter *hns = eth_dev->data->dev_private;
6108         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6109         struct rte_ether_addr *eth_addr;
6110         struct hns3_hw *hw = &hns->hw;
6111         int ret;
6112
6113         PMD_INIT_FUNC_TRACE();
6114
6115         eth_dev->process_private = (struct hns3_process_private *)
6116             rte_zmalloc_socket("hns3_filter_list",
6117                                sizeof(struct hns3_process_private),
6118                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6119         if (eth_dev->process_private == NULL) {
6120                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6121                 return -ENOMEM;
6122         }
6123         /* initialize flow filter lists */
6124         hns3_filterlist_init(eth_dev);
6125
6126         hns3_set_rxtx_function(eth_dev);
6127         eth_dev->dev_ops = &hns3_eth_dev_ops;
6128         eth_dev->rx_queue_count = hns3_rx_queue_count;
6129         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6130                 ret = hns3_mp_init_secondary();
6131                 if (ret) {
6132                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6133                                      "process, ret = %d", ret);
6134                         goto err_mp_init_secondary;
6135                 }
6136
6137                 hw->secondary_cnt++;
6138                 return 0;
6139         }
6140
6141         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6142
6143         ret = hns3_mp_init_primary();
6144         if (ret) {
6145                 PMD_INIT_LOG(ERR,
6146                              "Failed to init for primary process, ret = %d",
6147                              ret);
6148                 goto err_mp_init_primary;
6149         }
6150
6151         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6152         hns->is_vf = false;
6153         hw->data = eth_dev->data;
6154
6155         /*
6156          * Set default max packet size according to the mtu
6157          * default vale in DPDK frame.
6158          */
6159         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6160
6161         ret = hns3_reset_init(hw);
6162         if (ret)
6163                 goto err_init_reset;
6164         hw->reset.ops = &hns3_reset_ops;
6165
6166         ret = hns3_init_pf(eth_dev);
6167         if (ret) {
6168                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6169                 goto err_init_pf;
6170         }
6171
6172         /* Allocate memory for storing MAC addresses */
6173         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6174                                                sizeof(struct rte_ether_addr) *
6175                                                HNS3_UC_MACADDR_NUM, 0);
6176         if (eth_dev->data->mac_addrs == NULL) {
6177                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6178                              "to store MAC addresses",
6179                              sizeof(struct rte_ether_addr) *
6180                              HNS3_UC_MACADDR_NUM);
6181                 ret = -ENOMEM;
6182                 goto err_rte_zmalloc;
6183         }
6184
6185         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6186         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6187                 rte_eth_random_addr(hw->mac.mac_addr);
6188                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6189                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6190                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6191                           "unicast address, using random MAC address %s",
6192                           mac_str);
6193         }
6194         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6195                             &eth_dev->data->mac_addrs[0]);
6196
6197         hw->adapter_state = HNS3_NIC_INITIALIZED;
6198
6199         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6200                 hns3_err(hw, "Reschedule reset service after dev_init");
6201                 hns3_schedule_reset(hns);
6202         } else {
6203                 /* IMP will wait ready flag before reset */
6204                 hns3_notify_reset_ready(hw, false);
6205         }
6206
6207         hns3_info(hw, "hns3 dev initialization successful!");
6208         return 0;
6209
6210 err_rte_zmalloc:
6211         hns3_uninit_pf(eth_dev);
6212
6213 err_init_pf:
6214         rte_free(hw->reset.wait_data);
6215
6216 err_init_reset:
6217         hns3_mp_uninit_primary();
6218
6219 err_mp_init_primary:
6220 err_mp_init_secondary:
6221         eth_dev->dev_ops = NULL;
6222         eth_dev->rx_pkt_burst = NULL;
6223         eth_dev->tx_pkt_burst = NULL;
6224         eth_dev->tx_pkt_prepare = NULL;
6225         rte_free(eth_dev->process_private);
6226         eth_dev->process_private = NULL;
6227         return ret;
6228 }
6229
6230 static int
6231 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6232 {
6233         struct hns3_adapter *hns = eth_dev->data->dev_private;
6234         struct hns3_hw *hw = &hns->hw;
6235
6236         PMD_INIT_FUNC_TRACE();
6237
6238         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6239                 return -EPERM;
6240
6241         if (hw->adapter_state < HNS3_NIC_CLOSING)
6242                 hns3_dev_close(eth_dev);
6243
6244         hw->adapter_state = HNS3_NIC_REMOVED;
6245         return 0;
6246 }
6247
6248 static int
6249 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6250                    struct rte_pci_device *pci_dev)
6251 {
6252         return rte_eth_dev_pci_generic_probe(pci_dev,
6253                                              sizeof(struct hns3_adapter),
6254                                              hns3_dev_init);
6255 }
6256
6257 static int
6258 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6259 {
6260         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6261 }
6262
6263 static const struct rte_pci_id pci_id_hns3_map[] = {
6264         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6265         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6266         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6267         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6268         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6269         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6270         { .vendor_id = 0, }, /* sentinel */
6271 };
6272
6273 static struct rte_pci_driver rte_hns3_pmd = {
6274         .id_table = pci_id_hns3_map,
6275         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6276         .probe = eth_hns3_pci_probe,
6277         .remove = eth_hns3_pci_remove,
6278 };
6279
6280 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6281 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6282 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6283 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6284 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);