drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 109
 110 void hns3_ether_format_addr(char *buf, uint16_t size,
 111                             const struct rte_ether_addr *ether_addr)
 112 {
 113         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 114                 ether_addr->addr_bytes[0],
 115                 ether_addr->addr_bytes[4],
 116                 ether_addr->addr_bytes[5]);
 117 }
 118
 119 static void
 120 hns3_pf_disable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 123 }
 124
 125 static void
 126 hns3_pf_enable_irq0(struct hns3_hw *hw)
 127 {
 128         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 129 }
 130
 131 static enum hns3_evt_cause
 132 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 133                           uint32_t *vec_val)
 134 {
 135         struct hns3_hw *hw = &hns->hw;
 136
 137         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 138         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 139         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 140         if (!is_delay) {
 141                 hw->reset.stats.imp_cnt++;
 142                 hns3_warn(hw, "IMP reset detected, clear reset status");
 143         } else {
 144                 hns3_schedule_delayed_reset(hns);
 145                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 146         }
 147
 148         return HNS3_VECTOR0_EVENT_RST;
 149 }
 150
 151 static enum hns3_evt_cause
 152 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 153                              uint32_t *vec_val)
 154 {
 155         struct hns3_hw *hw = &hns->hw;
 156
 157         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 158         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 159         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 160         if (!is_delay) {
 161                 hw->reset.stats.global_cnt++;
 162                 hns3_warn(hw, "Global reset detected, clear reset status");
 163         } else {
 164                 hns3_schedule_delayed_reset(hns);
 165                 hns3_warn(hw,
 166                           "Global reset detected, don't clear reset status");
 167         }
 168
 169         return HNS3_VECTOR0_EVENT_RST;
 170 }
 171
 172 static enum hns3_evt_cause
 173 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 174 {
 175         struct hns3_hw *hw = &hns->hw;
 176         uint32_t vector0_int_stats;
 177         uint32_t cmdq_src_val;
 178         uint32_t hw_err_src_reg;
 179         uint32_t val;
 180         enum hns3_evt_cause ret;
 181         bool is_delay;
 182
 183         /* fetch the events from their corresponding regs */
 184         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 185         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 186         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 187
 188         is_delay = clearval == NULL ? true : false;
 189         /*
 190          * Assumption: If by any chance reset and mailbox events are reported
 191          * together then we will only process reset event and defer the
 192          * processing of the mailbox events. Since, we would have not cleared
 193          * RX CMDQ event this time we would receive again another interrupt
 194          * from H/W just for the mailbox.
 195          */
 196         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 197                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 198                 goto out;
 199         }
 200
 201         /* Global reset */
 202         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 203                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 204                 goto out;
 205         }
 206
 207         /* Check for vector0 1588 event source */
 208         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 209                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 210                 ret = HNS3_VECTOR0_EVENT_PTP;
 211                 goto out;
 212         }
 213
 214         /* check for vector0 msix event source */
 215         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 216             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 217                 val = vector0_int_stats | hw_err_src_reg;
 218                 ret = HNS3_VECTOR0_EVENT_ERR;
 219                 goto out;
 220         }
 221
 222         /* check for vector0 mailbox(=CMDQ RX) event source */
 223         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 224                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 225                 val = cmdq_src_val;
 226                 ret = HNS3_VECTOR0_EVENT_MBX;
 227                 goto out;
 228         }
 229
 230         val = vector0_int_stats;
 231         ret = HNS3_VECTOR0_EVENT_OTHER;
 232 out:
 233
 234         if (clearval)
 235                 *clearval = val;
 236         return ret;
 237 }
 238
 239 static bool
 240 hns3_is_1588_event_type(uint32_t event_type)
 241 {
 242         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 243 }
 244
 245 static void
 246 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 247 {
 248         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 249             hns3_is_1588_event_type(event_type))
 250                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 251         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 252                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 253 }
 254
 255 static void
 256 hns3_clear_all_event_cause(struct hns3_hw *hw)
 257 {
 258         uint32_t vector0_int_stats;
 259         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 260
 261         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 262                 hns3_warn(hw, "Probe during IMP reset interrupt");
 263
 264         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 265                 hns3_warn(hw, "Probe during Global reset interrupt");
 266
 267         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 268                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 270                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 272         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 273                                 BIT(HNS3_VECTOR0_1588_INT_B));
 274 }
 275
 276 static void
 277 hns3_handle_mac_tnl(struct hns3_hw *hw)
 278 {
 279         struct hns3_cmd_desc desc;
 280         uint32_t status;
 281         int ret;
 282
 283         /* query and clear mac tnl interrupt */
 284         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 285         ret = hns3_cmd_send(hw, &desc, 1);
 286         if (ret) {
 287                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 288                 return;
 289         }
 290
 291         status = rte_le_to_cpu_32(desc.data[0]);
 292         if (status) {
 293                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 294                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 295                                           false);
 296                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 297                 ret = hns3_cmd_send(hw, &desc, 1);
 298                 if (ret)
 299                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 300                                  ret);
 301         }
 302 }
 303
 304 static void
 305 hns3_interrupt_handler(void *param)
 306 {
 307         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 308         struct hns3_adapter *hns = dev->data->dev_private;
 309         struct hns3_hw *hw = &hns->hw;
 310         enum hns3_evt_cause event_cause;
 311         uint32_t clearval = 0;
 312         uint32_t vector0_int;
 313         uint32_t ras_int;
 314         uint32_t cmdq_int;
 315
 316         /* Disable interrupt */
 317         hns3_pf_disable_irq0(hw);
 318
 319         event_cause = hns3_check_event_cause(hns, &clearval);
 320         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 321         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 322         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 323         /* vector 0 interrupt is shared with reset and mailbox source events. */
 324         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 325                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 326                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 327                           vector0_int, ras_int, cmdq_int);
 328                 hns3_handle_mac_tnl(hw);
 329                 hns3_handle_error(hns);
 330         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 331                 hns3_warn(hw, "received reset interrupt");
 332                 hns3_schedule_reset(hns);
 333         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 334                 hns3_dev_handle_mbx_msg(hw);
 335         } else {
 336                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 337                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 338                           vector0_int, ras_int, cmdq_int);
 339         }
 340
 341         hns3_clear_event_cause(hw, event_cause, clearval);
 342         /* Enable interrupt if it is not cause by reset */
 343         hns3_pf_enable_irq0(hw);
 344 }
 345
 346 static int
 347 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 348 {
 349 #define HNS3_VLAN_ID_OFFSET_STEP        160
 350 #define HNS3_VLAN_BYTE_SIZE             8
 351         struct hns3_vlan_filter_pf_cfg_cmd *req;
 352         struct hns3_hw *hw = &hns->hw;
 353         uint8_t vlan_offset_byte_val;
 354         struct hns3_cmd_desc desc;
 355         uint8_t vlan_offset_byte;
 356         uint8_t vlan_offset_base;
 357         int ret;
 358
 359         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 360
 361         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 362         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 363                            HNS3_VLAN_BYTE_SIZE;
 364         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 365
 366         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 367         req->vlan_offset = vlan_offset_base;
 368         req->vlan_cfg = on ? 0 : 1;
 369         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 370
 371         ret = hns3_cmd_send(hw, &desc, 1);
 372         if (ret)
 373                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 374                          vlan_id, ret);
 375
 376         return ret;
 377 }
 378
 379 static void
 380 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 381 {
 382         struct hns3_user_vlan_table *vlan_entry;
 383         struct hns3_pf *pf = &hns->pf;
 384
 385         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 386                 if (vlan_entry->vlan_id == vlan_id) {
 387                         if (vlan_entry->hd_tbl_status)
 388                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 389                         LIST_REMOVE(vlan_entry, next);
 390                         rte_free(vlan_entry);
 391                         break;
 392                 }
 393         }
 394 }
 395
 396 static void
 397 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 398                         bool writen_to_tbl)
 399 {
 400         struct hns3_user_vlan_table *vlan_entry;
 401         struct hns3_hw *hw = &hns->hw;
 402         struct hns3_pf *pf = &hns->pf;
 403
 404         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 405                 if (vlan_entry->vlan_id == vlan_id)
 406                         return;
 407         }
 408
 409         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 410         if (vlan_entry == NULL) {
 411                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 412                 return;
 413         }
 414
 415         vlan_entry->hd_tbl_status = writen_to_tbl;
 416         vlan_entry->vlan_id = vlan_id;
 417
 418         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 419 }
 420
 421 static int
 422 hns3_restore_vlan_table(struct hns3_adapter *hns)
 423 {
 424         struct hns3_user_vlan_table *vlan_entry;
 425         struct hns3_hw *hw = &hns->hw;
 426         struct hns3_pf *pf = &hns->pf;
 427         uint16_t vlan_id;
 428         int ret = 0;
 429
 430         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 431                 return hns3_vlan_pvid_configure(hns,
 432                                                 hw->port_base_vlan_cfg.pvid, 1);
 433
 434         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 435                 if (vlan_entry->hd_tbl_status) {
 436                         vlan_id = vlan_entry->vlan_id;
 437                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 438                         if (ret)
 439                                 break;
 440                 }
 441         }
 442
 443         return ret;
 444 }
 445
 446 static int
 447 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 448 {
 449         struct hns3_hw *hw = &hns->hw;
 450         bool writen_to_tbl = false;
 451         int ret = 0;
 452
 453         /*
 454          * When vlan filter is enabled, hardware regards packets without vlan
 455          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 456          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 457          */
 458         if (on == 0 && vlan_id == 0)
 459                 return 0;
 460
 461         /*
 462          * When port base vlan enabled, we use port base vlan as the vlan
 463          * filter condition. In this case, we don't update vlan filter table
 464          * when user add new vlan or remove exist vlan, just update the
 465          * vlan list. The vlan id in vlan list will be written in vlan filter
 466          * table until port base vlan disabled
 467          */
 468         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 469                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 470                 writen_to_tbl = true;
 471         }
 472
 473         if (ret == 0) {
 474                 if (on)
 475                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 476                 else
 477                         hns3_rm_dev_vlan_table(hns, vlan_id);
 478         }
 479         return ret;
 480 }
 481
 482 static int
 483 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 484 {
 485         struct hns3_adapter *hns = dev->data->dev_private;
 486         struct hns3_hw *hw = &hns->hw;
 487         int ret;
 488
 489         rte_spinlock_lock(&hw->lock);
 490         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 491         rte_spinlock_unlock(&hw->lock);
 492         return ret;
 493 }
 494
 495 static int
 496 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 497                          uint16_t tpid)
 498 {
 499         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 500         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 501         struct hns3_hw *hw = &hns->hw;
 502         struct hns3_cmd_desc desc;
 503         int ret;
 504
 505         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 506              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 507                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 508                 return -EINVAL;
 509         }
 510
 511         if (tpid != RTE_ETHER_TYPE_VLAN) {
 512                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 513                 return -EINVAL;
 514         }
 515
 516         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 517         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 518
 519         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 520                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 521                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 522         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 523                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 527         }
 528
 529         ret = hns3_cmd_send(hw, &desc, 1);
 530         if (ret) {
 531                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 532                          ret);
 533                 return ret;
 534         }
 535
 536         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 537
 538         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 539         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 540         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 541
 542         ret = hns3_cmd_send(hw, &desc, 1);
 543         if (ret)
 544                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 545                          ret);
 546         return ret;
 547 }
 548
 549 static int
 550 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 551                    uint16_t tpid)
 552 {
 553         struct hns3_adapter *hns = dev->data->dev_private;
 554         struct hns3_hw *hw = &hns->hw;
 555         int ret;
 556
 557         rte_spinlock_lock(&hw->lock);
 558         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 559         rte_spinlock_unlock(&hw->lock);
 560         return ret;
 561 }
 562
 563 static int
 564 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 565                              struct hns3_rx_vtag_cfg *vcfg)
 566 {
 567         struct hns3_vport_vtag_rx_cfg_cmd *req;
 568         struct hns3_hw *hw = &hns->hw;
 569         struct hns3_cmd_desc desc;
 570         uint16_t vport_id;
 571         uint8_t bitmap;
 572         int ret;
 573
 574         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 575
 576         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 578                      vcfg->strip_tag1_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 580                      vcfg->strip_tag2_en ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 582                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 583         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 584                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 585
 586         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 588                      vcfg->strip_tag1_discard_en ? 1 : 0);
 589         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 590                      vcfg->strip_tag2_discard_en ? 1 : 0);
 591         /*
 592          * In current version VF is not supported when PF is driven by DPDK
 593          * driver, just need to configure parameters for PF vport.
 594          */
 595         vport_id = HNS3_PF_FUNC_ID;
 596         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 597         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 598         req->vf_bitmap[req->vf_offset] = bitmap;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 603         return ret;
 604 }
 605
 606 static void
 607 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 608                            struct hns3_rx_vtag_cfg *vcfg)
 609 {
 610         struct hns3_pf *pf = &hns->pf;
 611         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 612 }
 613
 614 static void
 615 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 616                            struct hns3_tx_vtag_cfg *vcfg)
 617 {
 618         struct hns3_pf *pf = &hns->pf;
 619         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 620 }
 621
 622 static int
 623 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 624 {
 625         struct hns3_rx_vtag_cfg rxvlan_cfg;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 630                 rxvlan_cfg.strip_tag1_en = false;
 631                 rxvlan_cfg.strip_tag2_en = enable;
 632                 rxvlan_cfg.strip_tag2_discard_en = false;
 633         } else {
 634                 rxvlan_cfg.strip_tag1_en = enable;
 635                 rxvlan_cfg.strip_tag2_en = true;
 636                 rxvlan_cfg.strip_tag2_discard_en = true;
 637         }
 638
 639         rxvlan_cfg.strip_tag1_discard_en = false;
 640         rxvlan_cfg.vlan1_vlan_prionly = false;
 641         rxvlan_cfg.vlan2_vlan_prionly = false;
 642         rxvlan_cfg.rx_vlan_offload_en = enable;
 643
 644         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 645         if (ret) {
 646                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 647                 return ret;
 648         }
 649
 650         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 651
 652         return ret;
 653 }
 654
 655 static int
 656 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 657                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 658 {
 659         struct hns3_vlan_filter_ctrl_cmd *req;
 660         struct hns3_cmd_desc desc;
 661         int ret;
 662
 663         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 664
 665         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 666         req->vlan_type = vlan_type;
 667         req->vlan_fe = filter_en ? fe_type : 0;
 668         req->vf_id = vf_id;
 669
 670         ret = hns3_cmd_send(hw, &desc, 1);
 671         if (ret)
 672                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 673
 674         return ret;
 675 }
 676
 677 static int
 678 hns3_vlan_filter_init(struct hns3_adapter *hns)
 679 {
 680         struct hns3_hw *hw = &hns->hw;
 681         int ret;
 682
 683         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 684                                         HNS3_FILTER_FE_EGRESS, false,
 685                                         HNS3_PF_FUNC_ID);
 686         if (ret) {
 687                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 688                 return ret;
 689         }
 690
 691         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 692                                         HNS3_FILTER_FE_INGRESS, false,
 693                                         HNS3_PF_FUNC_ID);
 694         if (ret)
 695                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 702 {
 703         struct hns3_hw *hw = &hns->hw;
 704         int ret;
 705
 706         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 707                                         HNS3_FILTER_FE_INGRESS, enable,
 708                                         HNS3_PF_FUNC_ID);
 709         if (ret)
 710                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 711                          enable ? "enable" : "disable", ret);
 712
 713         return ret;
 714 }
 715
 716 static int
 717 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 718 {
 719         struct hns3_adapter *hns = dev->data->dev_private;
 720         struct hns3_hw *hw = &hns->hw;
 721         struct rte_eth_rxmode *rxmode;
 722         unsigned int tmp_mask;
 723         bool enable;
 724         int ret = 0;
 725
 726         rte_spinlock_lock(&hw->lock);
 727         rxmode = &dev->data->dev_conf.rxmode;
 728         tmp_mask = (unsigned int)mask;
 729         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 730                 /* ignore vlan filter configuration during promiscuous mode */
 731                 if (!dev->data->promiscuous) {
 732                         /* Enable or disable VLAN filter */
 733                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 734                                  true : false;
 735
 736                         ret = hns3_enable_vlan_filter(hns, enable);
 737                         if (ret) {
 738                                 rte_spinlock_unlock(&hw->lock);
 739                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 740                                          enable ? "enable" : "disable", ret);
 741                                 return ret;
 742                         }
 743                 }
 744         }
 745
 746         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 747                 /* Enable or disable VLAN stripping */
 748                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 749                     true : false;
 750
 751                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 752                 if (ret) {
 753                         rte_spinlock_unlock(&hw->lock);
 754                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 755                                  enable ? "enable" : "disable", ret);
 756                         return ret;
 757                 }
 758         }
 759
 760         rte_spinlock_unlock(&hw->lock);
 761
 762         return ret;
 763 }
 764
 765 static int
 766 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 767                              struct hns3_tx_vtag_cfg *vcfg)
 768 {
 769         struct hns3_vport_vtag_tx_cfg_cmd *req;
 770         struct hns3_cmd_desc desc;
 771         struct hns3_hw *hw = &hns->hw;
 772         uint16_t vport_id;
 773         uint8_t bitmap;
 774         int ret;
 775
 776         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 777
 778         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 779         req->def_vlan_tag1 = vcfg->default_tag1;
 780         req->def_vlan_tag2 = vcfg->default_tag2;
 781         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 782                      vcfg->accept_tag1 ? 1 : 0);
 783         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 784                      vcfg->accept_untag1 ? 1 : 0);
 785         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 786                      vcfg->accept_tag2 ? 1 : 0);
 787         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 788                      vcfg->accept_untag2 ? 1 : 0);
 789         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 790                      vcfg->insert_tag1_en ? 1 : 0);
 791         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 792                      vcfg->insert_tag2_en ? 1 : 0);
 793         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 794
 795         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 796         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 797                      vcfg->tag_shift_mode_en ? 1 : 0);
 798
 799         /*
 800          * In current version VF is not supported when PF is driven by DPDK
 801          * driver, just need to configure parameters for PF vport.
 802          */
 803         vport_id = HNS3_PF_FUNC_ID;
 804         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 805         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 806         req->vf_bitmap[req->vf_offset] = bitmap;
 807
 808         ret = hns3_cmd_send(hw, &desc, 1);
 809         if (ret)
 810                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 811
 812         return ret;
 813 }
 814
 815 static int
 816 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 817                      uint16_t pvid)
 818 {
 819         struct hns3_hw *hw = &hns->hw;
 820         struct hns3_tx_vtag_cfg txvlan_cfg;
 821         int ret;
 822
 823         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 824                 txvlan_cfg.accept_tag1 = true;
 825                 txvlan_cfg.insert_tag1_en = false;
 826                 txvlan_cfg.default_tag1 = 0;
 827         } else {
 828                 txvlan_cfg.accept_tag1 =
 829                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 830                 txvlan_cfg.insert_tag1_en = true;
 831                 txvlan_cfg.default_tag1 = pvid;
 832         }
 833
 834         txvlan_cfg.accept_untag1 = true;
 835         txvlan_cfg.accept_tag2 = true;
 836         txvlan_cfg.accept_untag2 = true;
 837         txvlan_cfg.insert_tag2_en = false;
 838         txvlan_cfg.default_tag2 = 0;
 839         txvlan_cfg.tag_shift_mode_en = true;
 840
 841         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 842         if (ret) {
 843                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 844                          ret);
 845                 return ret;
 846         }
 847
 848         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 849         return ret;
 850 }
 851
 852
 853 static void
 854 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 855 {
 856         struct hns3_user_vlan_table *vlan_entry;
 857         struct hns3_pf *pf = &hns->pf;
 858
 859         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 860                 if (vlan_entry->hd_tbl_status) {
 861                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 862                         vlan_entry->hd_tbl_status = false;
 863                 }
 864         }
 865
 866         if (is_del_list) {
 867                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 868                 while (vlan_entry) {
 869                         LIST_REMOVE(vlan_entry, next);
 870                         rte_free(vlan_entry);
 871                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 872                 }
 873         }
 874 }
 875
 876 static void
 877 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 878 {
 879         struct hns3_user_vlan_table *vlan_entry;
 880         struct hns3_pf *pf = &hns->pf;
 881
 882         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 883                 if (!vlan_entry->hd_tbl_status) {
 884                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 885                         vlan_entry->hd_tbl_status = true;
 886                 }
 887         }
 888 }
 889
 890 static void
 891 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         hns3_rm_all_vlan_table(hns, true);
 897         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 898                 ret = hns3_set_port_vlan_filter(hns,
 899                                                 hw->port_base_vlan_cfg.pvid, 0);
 900                 if (ret) {
 901                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 902                                  ret);
 903                         return;
 904                 }
 905         }
 906 }
 907
 908 static int
 909 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 910                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 911 {
 912         struct hns3_hw *hw = &hns->hw;
 913         uint16_t old_pvid;
 914         int ret;
 915
 916         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 917                 old_pvid = hw->port_base_vlan_cfg.pvid;
 918                 if (old_pvid != HNS3_INVALID_PVID) {
 919                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 920                         if (ret) {
 921                                 hns3_err(hw, "failed to remove old pvid %u, "
 922                                                 "ret = %d", old_pvid, ret);
 923                                 return ret;
 924                         }
 925                 }
 926
 927                 hns3_rm_all_vlan_table(hns, false);
 928                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 929                 if (ret) {
 930                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 931                                         new_pvid, ret);
 932                         return ret;
 933                 }
 934         } else {
 935                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 936                 if (ret) {
 937                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 938                                         new_pvid, ret);
 939                         return ret;
 940                 }
 941
 942                 hns3_add_all_vlan_table(hns);
 943         }
 944         return 0;
 945 }
 946
 947 static int
 948 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 949 {
 950         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 951         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 952         bool rx_strip_en;
 953         int ret;
 954
 955         rx_strip_en = old_cfg->rx_vlan_offload_en;
 956         if (on) {
 957                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 958                 rx_vlan_cfg.strip_tag2_en = true;
 959                 rx_vlan_cfg.strip_tag2_discard_en = true;
 960         } else {
 961                 rx_vlan_cfg.strip_tag1_en = false;
 962                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 963                 rx_vlan_cfg.strip_tag2_discard_en = false;
 964         }
 965         rx_vlan_cfg.strip_tag1_discard_en = false;
 966         rx_vlan_cfg.vlan1_vlan_prionly = false;
 967         rx_vlan_cfg.vlan2_vlan_prionly = false;
 968         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 969
 970         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 971         if (ret)
 972                 return ret;
 973
 974         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 975         return ret;
 976 }
 977
 978 static int
 979 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 980 {
 981         struct hns3_hw *hw = &hns->hw;
 982         uint16_t port_base_vlan_state;
 983         int ret, err;
 984
 985         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 986                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 987                         hns3_warn(hw, "Invalid operation! As current pvid set "
 988                                   "is %u, disable pvid %u is invalid",
 989                                   hw->port_base_vlan_cfg.pvid, pvid);
 990                 return 0;
 991         }
 992
 993         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 994                                     HNS3_PORT_BASE_VLAN_DISABLE;
 995         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 996         if (ret) {
 997                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 998                          ret);
 999                 return ret;
1000         }
1001
1002         ret = hns3_en_pvid_strip(hns, on);
1003         if (ret) {
1004                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1005                          "ret = %d", ret);
1006                 goto pvid_vlan_strip_fail;
1007         }
1008
1009         if (pvid == HNS3_INVALID_PVID)
1010                 goto out;
1011         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1012         if (ret) {
1013                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1014                          ret);
1015                 goto vlan_filter_set_fail;
1016         }
1017
1018 out:
1019         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1020         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1021         return ret;
1022
1023 vlan_filter_set_fail:
1024         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1025                                         HNS3_PORT_BASE_VLAN_ENABLE);
1026         if (err)
1027                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1028
1029 pvid_vlan_strip_fail:
1030         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1031                                         hw->port_base_vlan_cfg.pvid);
1032         if (err)
1033                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1034
1035         return ret;
1036 }
1037
1038 static int
1039 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1040 {
1041         struct hns3_adapter *hns = dev->data->dev_private;
1042         struct hns3_hw *hw = &hns->hw;
1043         bool pvid_en_state_change;
1044         uint16_t pvid_state;
1045         int ret;
1046
1047         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1048                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1049                          RTE_ETHER_MAX_VLAN_ID);
1050                 return -EINVAL;
1051         }
1052
1053         /*
1054          * If PVID configuration state change, should refresh the PVID
1055          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1056          */
1057         pvid_state = hw->port_base_vlan_cfg.state;
1058         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1059             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1060                 pvid_en_state_change = false;
1061         else
1062                 pvid_en_state_change = true;
1063
1064         rte_spinlock_lock(&hw->lock);
1065         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1066         rte_spinlock_unlock(&hw->lock);
1067         if (ret)
1068                 return ret;
1069         /*
1070          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1071          * need be processed by PMD driver.
1072          */
1073         if (pvid_en_state_change &&
1074             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1075                 hns3_update_all_queues_pvid_proc_en(hw);
1076
1077         return 0;
1078 }
1079
1080 static int
1081 hns3_default_vlan_config(struct hns3_adapter *hns)
1082 {
1083         struct hns3_hw *hw = &hns->hw;
1084         int ret;
1085
1086         /*
1087          * When vlan filter is enabled, hardware regards packets without vlan
1088          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1089          * table, packets without vlan won't be received. So, add vlan 0 as
1090          * the default vlan.
1091          */
1092         ret = hns3_vlan_filter_configure(hns, 0, 1);
1093         if (ret)
1094                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1095         return ret;
1096 }
1097
1098 static int
1099 hns3_init_vlan_config(struct hns3_adapter *hns)
1100 {
1101         struct hns3_hw *hw = &hns->hw;
1102         int ret;
1103
1104         /*
1105          * This function can be called in the initialization and reset process,
1106          * when in reset process, it means that hardware had been reseted
1107          * successfully and we need to restore the hardware configuration to
1108          * ensure that the hardware configuration remains unchanged before and
1109          * after reset.
1110          */
1111         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1112                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1113                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1114         }
1115
1116         ret = hns3_vlan_filter_init(hns);
1117         if (ret) {
1118                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1119                 return ret;
1120         }
1121
1122         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1123                                        RTE_ETHER_TYPE_VLAN);
1124         if (ret) {
1125                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1126                 return ret;
1127         }
1128
1129         /*
1130          * When in the reinit dev stage of the reset process, the following
1131          * vlan-related configurations may differ from those at initialization,
1132          * we will restore configurations to hardware in hns3_restore_vlan_table
1133          * and hns3_restore_vlan_conf later.
1134          */
1135         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1136                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1137                 if (ret) {
1138                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1139                         return ret;
1140                 }
1141
1142                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1143                 if (ret) {
1144                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1145                                  ret);
1146                         return ret;
1147                 }
1148         }
1149
1150         return hns3_default_vlan_config(hns);
1151 }
1152
1153 static int
1154 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1155 {
1156         struct hns3_pf *pf = &hns->pf;
1157         struct hns3_hw *hw = &hns->hw;
1158         uint64_t offloads;
1159         bool enable;
1160         int ret;
1161
1162         if (!hw->data->promiscuous) {
1163                 /* restore vlan filter states */
1164                 offloads = hw->data->dev_conf.rxmode.offloads;
1165                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1166                 ret = hns3_enable_vlan_filter(hns, enable);
1167                 if (ret) {
1168                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1169                                  "ret = %d", ret);
1170                         return ret;
1171                 }
1172         }
1173
1174         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1175         if (ret) {
1176                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1177                 return ret;
1178         }
1179
1180         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1181         if (ret)
1182                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1183
1184         return ret;
1185 }
1186
1187 static int
1188 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1189 {
1190         struct hns3_adapter *hns = dev->data->dev_private;
1191         struct rte_eth_dev_data *data = dev->data;
1192         struct rte_eth_txmode *txmode;
1193         struct hns3_hw *hw = &hns->hw;
1194         int mask;
1195         int ret;
1196
1197         txmode = &data->dev_conf.txmode;
1198         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1199                 hns3_warn(hw,
1200                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1201                           "configuration is not supported! Ignore these two "
1202                           "parameters: hw_vlan_reject_tagged(%u), "
1203                           "hw_vlan_reject_untagged(%u)",
1204                           txmode->hw_vlan_reject_tagged,
1205                           txmode->hw_vlan_reject_untagged);
1206
1207         /* Apply vlan offload setting */
1208         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1209         ret = hns3_vlan_offload_set(dev, mask);
1210         if (ret) {
1211                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1212                          ret);
1213                 return ret;
1214         }
1215
1216         /*
1217          * If pvid config is not set in rte_eth_conf, driver needn't to set
1218          * VLAN pvid related configuration to hardware.
1219          */
1220         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1221                 return 0;
1222
1223         /* Apply pvid setting */
1224         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1225                                  txmode->hw_vlan_insert_pvid);
1226         if (ret)
1227                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1228                          txmode->pvid, ret);
1229
1230         return ret;
1231 }
1232
1233 static int
1234 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1235                 unsigned int tso_mss_max)
1236 {
1237         struct hns3_cfg_tso_status_cmd *req;
1238         struct hns3_cmd_desc desc;
1239         uint16_t tso_mss;
1240
1241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1242
1243         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1244
1245         tso_mss = 0;
1246         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1247                        tso_mss_min);
1248         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1249
1250         tso_mss = 0;
1251         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1252                        tso_mss_max);
1253         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1254
1255         return hns3_cmd_send(hw, &desc, 1);
1256 }
1257
1258 static int
1259 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1260                    uint16_t *allocated_size, bool is_alloc)
1261 {
1262         struct hns3_umv_spc_alc_cmd *req;
1263         struct hns3_cmd_desc desc;
1264         int ret;
1265
1266         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1267         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1268         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1269         req->space_size = rte_cpu_to_le_32(space_size);
1270
1271         ret = hns3_cmd_send(hw, &desc, 1);
1272         if (ret) {
1273                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1274                              is_alloc ? "allocate" : "free", ret);
1275                 return ret;
1276         }
1277
1278         if (is_alloc && allocated_size)
1279                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 hns3_init_umv_space(struct hns3_hw *hw)
1286 {
1287         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1288         struct hns3_pf *pf = &hns->pf;
1289         uint16_t allocated_size = 0;
1290         int ret;
1291
1292         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1293                                  true);
1294         if (ret)
1295                 return ret;
1296
1297         if (allocated_size < pf->wanted_umv_size)
1298                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1299                              pf->wanted_umv_size, allocated_size);
1300
1301         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1302                                                 pf->wanted_umv_size;
1303         pf->used_umv_size = 0;
1304         return 0;
1305 }
1306
1307 static int
1308 hns3_uninit_umv_space(struct hns3_hw *hw)
1309 {
1310         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1311         struct hns3_pf *pf = &hns->pf;
1312         int ret;
1313
1314         if (pf->max_umv_size == 0)
1315                 return 0;
1316
1317         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1318         if (ret)
1319                 return ret;
1320
1321         pf->max_umv_size = 0;
1322
1323         return 0;
1324 }
1325
1326 static bool
1327 hns3_is_umv_space_full(struct hns3_hw *hw)
1328 {
1329         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1330         struct hns3_pf *pf = &hns->pf;
1331         bool is_full;
1332
1333         is_full = (pf->used_umv_size >= pf->max_umv_size);
1334
1335         return is_full;
1336 }
1337
1338 static void
1339 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1340 {
1341         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1342         struct hns3_pf *pf = &hns->pf;
1343
1344         if (is_free) {
1345                 if (pf->used_umv_size > 0)
1346                         pf->used_umv_size--;
1347         } else
1348                 pf->used_umv_size++;
1349 }
1350
1351 static void
1352 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1353                       const uint8_t *addr, bool is_mc)
1354 {
1355         const unsigned char *mac_addr = addr;
1356         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1357                             ((uint32_t)mac_addr[2] << 16) |
1358                             ((uint32_t)mac_addr[1] << 8) |
1359                             (uint32_t)mac_addr[0];
1360         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1361
1362         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1363         if (is_mc) {
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1366                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1367         }
1368
1369         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1370         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1371 }
1372
1373 static int
1374 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1375                              uint8_t resp_code,
1376                              enum hns3_mac_vlan_tbl_opcode op)
1377 {
1378         if (cmdq_resp) {
1379                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1380                          cmdq_resp);
1381                 return -EIO;
1382         }
1383
1384         if (op == HNS3_MAC_VLAN_ADD) {
1385                 if (resp_code == 0 || resp_code == 1) {
1386                         return 0;
1387                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1388                         hns3_err(hw, "add mac addr failed for uc_overflow");
1389                         return -ENOSPC;
1390                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1391                         hns3_err(hw, "add mac addr failed for mc_overflow");
1392                         return -ENOSPC;
1393                 }
1394
1395                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1396                          resp_code);
1397                 return -EIO;
1398         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1399                 if (resp_code == 0) {
1400                         return 0;
1401                 } else if (resp_code == 1) {
1402                         hns3_dbg(hw, "remove mac addr failed for miss");
1403                         return -ENOENT;
1404                 }
1405
1406                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1407                          resp_code);
1408                 return -EIO;
1409         } else if (op == HNS3_MAC_VLAN_LKUP) {
1410                 if (resp_code == 0) {
1411                         return 0;
1412                 } else if (resp_code == 1) {
1413                         hns3_dbg(hw, "lookup mac addr failed for miss");
1414                         return -ENOENT;
1415                 }
1416
1417                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1418                          resp_code);
1419                 return -EIO;
1420         }
1421
1422         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1423                  op);
1424
1425         return -EINVAL;
1426 }
1427
1428 static int
1429 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1430                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1431                          struct hns3_cmd_desc *desc, bool is_mc)
1432 {
1433         uint8_t resp_code;
1434         uint16_t retval;
1435         int ret;
1436
1437         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1438         if (is_mc) {
1439                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1440                 memcpy(desc[0].data, req,
1441                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1442                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1443                                           true);
1444                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1445                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1446                                           true);
1447                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1448         } else {
1449                 memcpy(desc[0].data, req,
1450                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451                 ret = hns3_cmd_send(hw, desc, 1);
1452         }
1453         if (ret) {
1454                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1455                          ret);
1456                 return ret;
1457         }
1458         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1459         retval = rte_le_to_cpu_16(desc[0].retval);
1460
1461         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462                                             HNS3_MAC_VLAN_LKUP);
1463 }
1464
1465 static int
1466 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1467                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1468                       struct hns3_cmd_desc *mc_desc)
1469 {
1470         uint8_t resp_code;
1471         uint16_t retval;
1472         int cfg_status;
1473         int ret;
1474
1475         if (mc_desc == NULL) {
1476                 struct hns3_cmd_desc desc;
1477
1478                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1479                 memcpy(desc.data, req,
1480                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1481                 ret = hns3_cmd_send(hw, &desc, 1);
1482                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1483                 retval = rte_le_to_cpu_16(desc.retval);
1484
1485                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1486                                                           HNS3_MAC_VLAN_ADD);
1487         } else {
1488                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1489                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1491                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1492                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1493                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494                 memcpy(mc_desc[0].data, req,
1495                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1496                 mc_desc[0].retval = 0;
1497                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1498                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1499                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1500
1501                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1502                                                           HNS3_MAC_VLAN_ADD);
1503         }
1504
1505         if (ret) {
1506                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1507                 return ret;
1508         }
1509
1510         return cfg_status;
1511 }
1512
1513 static int
1514 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1515                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1516 {
1517         struct hns3_cmd_desc desc;
1518         uint8_t resp_code;
1519         uint16_t retval;
1520         int ret;
1521
1522         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1523
1524         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1525
1526         ret = hns3_cmd_send(hw, &desc, 1);
1527         if (ret) {
1528                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1529                 return ret;
1530         }
1531         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1532         retval = rte_le_to_cpu_16(desc.retval);
1533
1534         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1535                                             HNS3_MAC_VLAN_REMOVE);
1536 }
1537
1538 static int
1539 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1540 {
1541         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1542         struct hns3_mac_vlan_tbl_entry_cmd req;
1543         struct hns3_pf *pf = &hns->pf;
1544         struct hns3_cmd_desc desc[3];
1545         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1546         uint16_t egress_port = 0;
1547         uint8_t vf_id;
1548         int ret;
1549
1550         /* check if mac addr is valid */
1551         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1552                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                       mac_addr);
1554                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1555                          mac_str);
1556                 return -EINVAL;
1557         }
1558
1559         memset(&req, 0, sizeof(req));
1560
1561         /*
1562          * In current version VF is not supported when PF is driven by DPDK
1563          * driver, just need to configure parameters for PF vport.
1564          */
1565         vf_id = HNS3_PF_FUNC_ID;
1566         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1567                        HNS3_MAC_EPORT_VFID_S, vf_id);
1568
1569         req.egress_port = rte_cpu_to_le_16(egress_port);
1570
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572
1573         /*
1574          * Lookup the mac address in the mac_vlan table, and add
1575          * it if the entry is inexistent. Repeated unicast entry
1576          * is not allowed in the mac vlan table.
1577          */
1578         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1579         if (ret == -ENOENT) {
1580                 if (!hns3_is_umv_space_full(hw)) {
1581                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1582                         if (!ret)
1583                                 hns3_update_umv_space(hw, false);
1584                         return ret;
1585                 }
1586
1587                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1588
1589                 return -ENOSPC;
1590         }
1591
1592         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1593
1594         /* check if we just hit the duplicate */
1595         if (ret == 0) {
1596                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1597                 return 0;
1598         }
1599
1600         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1601                  mac_str);
1602
1603         return ret;
1604 }
1605
1606 static int
1607 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1608 {
1609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610         struct rte_ether_addr *addr;
1611         int ret;
1612         int i;
1613
1614         for (i = 0; i < hw->mc_addrs_num; i++) {
1615                 addr = &hw->mc_addrs[i];
1616                 /* Check if there are duplicate addresses */
1617                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1618                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1619                                               addr);
1620                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1621                                  "(%s) is added by the set_mc_mac_addr_list "
1622                                  "API", mac_str);
1623                         return -EINVAL;
1624                 }
1625         }
1626
1627         ret = hns3_add_mc_addr(hw, mac_addr);
1628         if (ret) {
1629                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                       mac_addr);
1631                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1632                          mac_str, ret);
1633         }
1634         return ret;
1635 }
1636
1637 static int
1638 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1639 {
1640         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641         int ret;
1642
1643         ret = hns3_remove_mc_addr(hw, mac_addr);
1644         if (ret) {
1645                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1646                                       mac_addr);
1647                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1648                          mac_str, ret);
1649         }
1650         return ret;
1651 }
1652
1653 static int
1654 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1655                   uint32_t idx, __rte_unused uint32_t pool)
1656 {
1657         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         /*
1664          * In hns3 network engine adding UC and MC mac address with different
1665          * commands with firmware. We need to determine whether the input
1666          * address is a UC or a MC address to call different commands.
1667          * By the way, it is recommended calling the API function named
1668          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1669          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1670          * may affect the specifications of UC mac addresses.
1671          */
1672         if (rte_is_multicast_ether_addr(mac_addr))
1673                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1674         else
1675                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1676
1677         if (ret) {
1678                 rte_spinlock_unlock(&hw->lock);
1679                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                       mac_addr);
1681                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1682                          ret);
1683                 return ret;
1684         }
1685
1686         if (idx == 0)
1687                 hw->mac.default_addr_setted = true;
1688         rte_spinlock_unlock(&hw->lock);
1689
1690         return ret;
1691 }
1692
1693 static int
1694 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1695 {
1696         struct hns3_mac_vlan_tbl_entry_cmd req;
1697         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698         int ret;
1699
1700         /* check if mac addr is valid */
1701         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1702                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1703                                       mac_addr);
1704                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1705                          mac_str);
1706                 return -EINVAL;
1707         }
1708
1709         memset(&req, 0, sizeof(req));
1710         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1711         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1712         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1713         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1714                 return 0;
1715         else if (ret == 0)
1716                 hns3_update_umv_space(hw, true);
1717
1718         return ret;
1719 }
1720
1721 static void
1722 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1723 {
1724         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         /* index will be checked by upper level rte interface */
1726         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1727         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728         int ret;
1729
1730         rte_spinlock_lock(&hw->lock);
1731
1732         if (rte_is_multicast_ether_addr(mac_addr))
1733                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1734         else
1735                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1736         rte_spinlock_unlock(&hw->lock);
1737         if (ret) {
1738                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1739                                       mac_addr);
1740                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1741                          ret);
1742         }
1743 }
1744
1745 static int
1746 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1747                           struct rte_ether_addr *mac_addr)
1748 {
1749         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         struct rte_ether_addr *oaddr;
1751         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752         bool default_addr_setted;
1753         bool rm_succes = false;
1754         int ret, ret_val;
1755
1756         /*
1757          * It has been guaranteed that input parameter named mac_addr is valid
1758          * address in the rte layer of DPDK framework.
1759          */
1760         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1761         default_addr_setted = hw->mac.default_addr_setted;
1762         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1763                 return 0;
1764
1765         rte_spinlock_lock(&hw->lock);
1766         if (default_addr_setted) {
1767                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1768                 if (ret) {
1769                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1770                                               oaddr);
1771                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1772                                   mac_str, ret);
1773                         rm_succes = false;
1774                 } else
1775                         rm_succes = true;
1776         }
1777
1778         ret = hns3_add_uc_addr_common(hw, mac_addr);
1779         if (ret) {
1780                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                       mac_addr);
1782                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1783                 goto err_add_uc_addr;
1784         }
1785
1786         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1787         if (ret) {
1788                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1789                 goto err_pause_addr_cfg;
1790         }
1791
1792         rte_ether_addr_copy(mac_addr,
1793                             (struct rte_ether_addr *)hw->mac.mac_addr);
1794         hw->mac.default_addr_setted = true;
1795         rte_spinlock_unlock(&hw->lock);
1796
1797         return 0;
1798
1799 err_pause_addr_cfg:
1800         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1801         if (ret_val) {
1802                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803                                       mac_addr);
1804                 hns3_warn(hw,
1805                           "Failed to roll back to del setted mac addr(%s): %d",
1806                           mac_str, ret_val);
1807         }
1808
1809 err_add_uc_addr:
1810         if (rm_succes) {
1811                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1812                 if (ret_val) {
1813                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                               oaddr);
1815                         hns3_warn(hw,
1816                                   "Failed to restore old uc mac addr(%s): %d",
1817                                   mac_str, ret_val);
1818                         hw->mac.default_addr_setted = false;
1819                 }
1820         }
1821         rte_spinlock_unlock(&hw->lock);
1822
1823         return ret;
1824 }
1825
1826 static int
1827 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1828 {
1829         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1830         struct hns3_hw *hw = &hns->hw;
1831         struct rte_ether_addr *addr;
1832         int err = 0;
1833         int ret;
1834         int i;
1835
1836         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1837                 addr = &hw->data->mac_addrs[i];
1838                 if (rte_is_zero_ether_addr(addr))
1839                         continue;
1840                 if (rte_is_multicast_ether_addr(addr))
1841                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1842                               hns3_add_mc_addr(hw, addr);
1843                 else
1844                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1845                               hns3_add_uc_addr_common(hw, addr);
1846
1847                 if (ret) {
1848                         err = ret;
1849                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1850                                               addr);
1851                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1852                                  "ret = %d.", del ? "remove" : "restore",
1853                                  mac_str, i, ret);
1854                 }
1855         }
1856         return err;
1857 }
1858
1859 static void
1860 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1861 {
1862 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1863         uint8_t word_num;
1864         uint8_t bit_num;
1865
1866         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1867                 word_num = vfid / 32;
1868                 bit_num = vfid % 32;
1869                 if (clr)
1870                         desc[1].data[word_num] &=
1871                             rte_cpu_to_le_32(~(1UL << bit_num));
1872                 else
1873                         desc[1].data[word_num] |=
1874                             rte_cpu_to_le_32(1UL << bit_num);
1875         } else {
1876                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1877                 bit_num = vfid % 32;
1878                 if (clr)
1879                         desc[2].data[word_num] &=
1880                             rte_cpu_to_le_32(~(1UL << bit_num));
1881                 else
1882                         desc[2].data[word_num] |=
1883                             rte_cpu_to_le_32(1UL << bit_num);
1884         }
1885 }
1886
1887 static int
1888 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1889 {
1890         struct hns3_mac_vlan_tbl_entry_cmd req;
1891         struct hns3_cmd_desc desc[3];
1892         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1893         uint8_t vf_id;
1894         int ret;
1895
1896         /* Check if mac addr is valid */
1897         if (!rte_is_multicast_ether_addr(mac_addr)) {
1898                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1899                                       mac_addr);
1900                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1901                          mac_str);
1902                 return -EINVAL;
1903         }
1904
1905         memset(&req, 0, sizeof(req));
1906         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1907         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1908         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1909         if (ret) {
1910                 /* This mac addr do not exist, add new entry for it */
1911                 memset(desc[0].data, 0, sizeof(desc[0].data));
1912                 memset(desc[1].data, 0, sizeof(desc[0].data));
1913                 memset(desc[2].data, 0, sizeof(desc[0].data));
1914         }
1915
1916         /*
1917          * In current version VF is not supported when PF is driven by DPDK
1918          * driver, just need to configure parameters for PF vport.
1919          */
1920         vf_id = HNS3_PF_FUNC_ID;
1921         hns3_update_desc_vfid(desc, vf_id, false);
1922         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1923         if (ret) {
1924                 if (ret == -ENOSPC)
1925                         hns3_err(hw, "mc mac vlan table is full");
1926                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1927                                       mac_addr);
1928                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1929         }
1930
1931         return ret;
1932 }
1933
1934 static int
1935 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1936 {
1937         struct hns3_mac_vlan_tbl_entry_cmd req;
1938         struct hns3_cmd_desc desc[3];
1939         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1940         uint8_t vf_id;
1941         int ret;
1942
1943         /* Check if mac addr is valid */
1944         if (!rte_is_multicast_ether_addr(mac_addr)) {
1945                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1946                                       mac_addr);
1947                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1948                          mac_str);
1949                 return -EINVAL;
1950         }
1951
1952         memset(&req, 0, sizeof(req));
1953         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1954         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1955         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1956         if (ret == 0) {
1957                 /*
1958                  * This mac addr exist, remove this handle's VFID for it.
1959                  * In current version VF is not supported when PF is driven by
1960                  * DPDK driver, just need to configure parameters for PF vport.
1961                  */
1962                 vf_id = HNS3_PF_FUNC_ID;
1963                 hns3_update_desc_vfid(desc, vf_id, true);
1964
1965                 /* All the vfid is zero, so need to delete this entry */
1966                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1967         } else if (ret == -ENOENT) {
1968                 /* This mac addr doesn't exist. */
1969                 return 0;
1970         }
1971
1972         if (ret) {
1973                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1974                                       mac_addr);
1975                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1976         }
1977
1978         return ret;
1979 }
1980
1981 static int
1982 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1983                            struct rte_ether_addr *mc_addr_set,
1984                            uint32_t nb_mc_addr)
1985 {
1986         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1987         struct rte_ether_addr *addr;
1988         uint32_t i;
1989         uint32_t j;
1990
1991         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1992                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1993                          "invalid. valid range: 0~%d",
1994                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1995                 return -EINVAL;
1996         }
1997
1998         /* Check if input mac addresses are valid */
1999         for (i = 0; i < nb_mc_addr; i++) {
2000                 addr = &mc_addr_set[i];
2001                 if (!rte_is_multicast_ether_addr(addr)) {
2002                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2003                                               addr);
2004                         hns3_err(hw,
2005                                  "failed to set mc mac addr, addr(%s) invalid.",
2006                                  mac_str);
2007                         return -EINVAL;
2008                 }
2009
2010                 /* Check if there are duplicate addresses */
2011                 for (j = i + 1; j < nb_mc_addr; j++) {
2012                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2013                                 hns3_ether_format_addr(mac_str,
2014                                                       RTE_ETHER_ADDR_FMT_SIZE,
2015                                                       addr);
2016                                 hns3_err(hw, "failed to set mc mac addr, "
2017                                          "addrs invalid. two same addrs(%s).",
2018                                          mac_str);
2019                                 return -EINVAL;
2020                         }
2021                 }
2022
2023                 /*
2024                  * Check if there are duplicate addresses between mac_addrs
2025                  * and mc_addr_set
2026                  */
2027                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2028                         if (rte_is_same_ether_addr(addr,
2029                                                    &hw->data->mac_addrs[j])) {
2030                                 hns3_ether_format_addr(mac_str,
2031                                                       RTE_ETHER_ADDR_FMT_SIZE,
2032                                                       addr);
2033                                 hns3_err(hw, "failed to set mc mac addr, "
2034                                          "addrs invalid. addrs(%s) has already "
2035                                          "configured in mac_addr add API",
2036                                          mac_str);
2037                                 return -EINVAL;
2038                         }
2039                 }
2040         }
2041
2042         return 0;
2043 }
2044
2045 static void
2046 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2047                            struct rte_ether_addr *mc_addr_set,
2048                            int mc_addr_num,
2049                            struct rte_ether_addr *reserved_addr_list,
2050                            int *reserved_addr_num,
2051                            struct rte_ether_addr *add_addr_list,
2052                            int *add_addr_num,
2053                            struct rte_ether_addr *rm_addr_list,
2054                            int *rm_addr_num)
2055 {
2056         struct rte_ether_addr *addr;
2057         int current_addr_num;
2058         int reserved_num = 0;
2059         int add_num = 0;
2060         int rm_num = 0;
2061         int num;
2062         int i;
2063         int j;
2064         bool same_addr;
2065
2066         /* Calculate the mc mac address list that should be removed */
2067         current_addr_num = hw->mc_addrs_num;
2068         for (i = 0; i < current_addr_num; i++) {
2069                 addr = &hw->mc_addrs[i];
2070                 same_addr = false;
2071                 for (j = 0; j < mc_addr_num; j++) {
2072                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2073                                 same_addr = true;
2074                                 break;
2075                         }
2076                 }
2077
2078                 if (!same_addr) {
2079                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2080                         rm_num++;
2081                 } else {
2082                         rte_ether_addr_copy(addr,
2083                                             &reserved_addr_list[reserved_num]);
2084                         reserved_num++;
2085                 }
2086         }
2087
2088         /* Calculate the mc mac address list that should be added */
2089         for (i = 0; i < mc_addr_num; i++) {
2090                 addr = &mc_addr_set[i];
2091                 same_addr = false;
2092                 for (j = 0; j < current_addr_num; j++) {
2093                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2094                                 same_addr = true;
2095                                 break;
2096                         }
2097                 }
2098
2099                 if (!same_addr) {
2100                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2101                         add_num++;
2102                 }
2103         }
2104
2105         /* Reorder the mc mac address list maintained by driver */
2106         for (i = 0; i < reserved_num; i++)
2107                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2108
2109         for (i = 0; i < rm_num; i++) {
2110                 num = reserved_num + i;
2111                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2112         }
2113
2114         *reserved_addr_num = reserved_num;
2115         *add_addr_num = add_num;
2116         *rm_addr_num = rm_num;
2117 }
2118
2119 static int
2120 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2121                           struct rte_ether_addr *mc_addr_set,
2122                           uint32_t nb_mc_addr)
2123 {
2124         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2126         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr *addr;
2129         int reserved_addr_num;
2130         int add_addr_num;
2131         int rm_addr_num;
2132         int mc_addr_num;
2133         int num;
2134         int ret;
2135         int i;
2136
2137         /* Check if input parameters are valid */
2138         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2139         if (ret)
2140                 return ret;
2141
2142         rte_spinlock_lock(&hw->lock);
2143
2144         /*
2145          * Calculate the mc mac address lists those should be removed and be
2146          * added, Reorder the mc mac address list maintained by driver.
2147          */
2148         mc_addr_num = (int)nb_mc_addr;
2149         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2150                                    reserved_addr_list, &reserved_addr_num,
2151                                    add_addr_list, &add_addr_num,
2152                                    rm_addr_list, &rm_addr_num);
2153
2154         /* Remove mc mac addresses */
2155         for (i = 0; i < rm_addr_num; i++) {
2156                 num = rm_addr_num - i - 1;
2157                 addr = &rm_addr_list[num];
2158                 ret = hns3_remove_mc_addr(hw, addr);
2159                 if (ret) {
2160                         rte_spinlock_unlock(&hw->lock);
2161                         return ret;
2162                 }
2163                 hw->mc_addrs_num--;
2164         }
2165
2166         /* Add mc mac addresses */
2167         for (i = 0; i < add_addr_num; i++) {
2168                 addr = &add_addr_list[i];
2169                 ret = hns3_add_mc_addr(hw, addr);
2170                 if (ret) {
2171                         rte_spinlock_unlock(&hw->lock);
2172                         return ret;
2173                 }
2174
2175                 num = reserved_addr_num + i;
2176                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2177                 hw->mc_addrs_num++;
2178         }
2179         rte_spinlock_unlock(&hw->lock);
2180
2181         return 0;
2182 }
2183
2184 static int
2185 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2186 {
2187         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2188         struct hns3_hw *hw = &hns->hw;
2189         struct rte_ether_addr *addr;
2190         int err = 0;
2191         int ret;
2192         int i;
2193
2194         for (i = 0; i < hw->mc_addrs_num; i++) {
2195                 addr = &hw->mc_addrs[i];
2196                 if (!rte_is_multicast_ether_addr(addr))
2197                         continue;
2198                 if (del)
2199                         ret = hns3_remove_mc_addr(hw, addr);
2200                 else
2201                         ret = hns3_add_mc_addr(hw, addr);
2202                 if (ret) {
2203                         err = ret;
2204                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2205                                               addr);
2206                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2207                                  del ? "Remove" : "Restore", mac_str, ret);
2208                 }
2209         }
2210         return err;
2211 }
2212
2213 static int
2214 hns3_check_mq_mode(struct rte_eth_dev *dev)
2215 {
2216         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2217         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2221         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2222         uint8_t num_tc;
2223         int max_tc = 0;
2224         int i;
2225
2226         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2227             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2228              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2229                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2230                          rx_mq_mode, tx_mq_mode);
2231                 return -EOPNOTSUPP;
2232         }
2233
2234         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2235         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2236         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2237                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2238                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2239                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2240                         return -EINVAL;
2241                 }
2242
2243                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2244                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2245                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2246                                  "nb_tcs(%d) != %d or %d in rx direction.",
2247                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2252                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2253                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2254                         return -EINVAL;
2255                 }
2256
2257                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2258                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2259                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2260                                          "is not equal to one in tx direction.",
2261                                          i, dcb_rx_conf->dcb_tc[i]);
2262                                 return -EINVAL;
2263                         }
2264                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2265                                 max_tc = dcb_rx_conf->dcb_tc[i];
2266                 }
2267
2268                 num_tc = max_tc + 1;
2269                 if (num_tc > dcb_rx_conf->nb_tcs) {
2270                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2271                                  num_tc, dcb_rx_conf->nb_tcs);
2272                         return -EINVAL;
2273                 }
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int
2280 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2281 {
2282         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283
2284         if (!hns3_dev_dcb_supported(hw)) {
2285                 hns3_err(hw, "this port does not support dcb configurations.");
2286                 return -EOPNOTSUPP;
2287         }
2288
2289         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2290                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2291                 return -EOPNOTSUPP;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int
2298 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2299                            enum hns3_ring_type queue_type, uint16_t queue_id)
2300 {
2301         struct hns3_cmd_desc desc;
2302         struct hns3_ctrl_vector_chain_cmd *req =
2303                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2304         enum hns3_opcode_type op;
2305         uint16_t tqp_type_and_id = 0;
2306         uint16_t type;
2307         uint16_t gl;
2308         int ret;
2309
2310         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2311         hns3_cmd_setup_basic_desc(&desc, op, false);
2312         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2313                                               HNS3_TQP_INT_ID_L_S);
2314         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2315                                               HNS3_TQP_INT_ID_H_S);
2316
2317         if (queue_type == HNS3_RING_TYPE_RX)
2318                 gl = HNS3_RING_GL_RX;
2319         else
2320                 gl = HNS3_RING_GL_TX;
2321
2322         type = queue_type;
2323
2324         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2325                        type);
2326         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2327         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2328                        gl);
2329         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2330         req->int_cause_num = 1;
2331         ret = hns3_cmd_send(hw, &desc, 1);
2332         if (ret) {
2333                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2334                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2335                 return ret;
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int
2342 hns3_init_ring_with_vector(struct hns3_hw *hw)
2343 {
2344         uint16_t vec;
2345         int ret;
2346         int i;
2347
2348         /*
2349          * In hns3 network engine, vector 0 is always the misc interrupt of this
2350          * function, vector 1~N can be used respectively for the queues of the
2351          * function. Tx and Rx queues with the same number share the interrupt
2352          * vector. In the initialization clearing the all hardware mapping
2353          * relationship configurations between queues and interrupt vectors is
2354          * needed, so some error caused by the residual configurations, such as
2355          * the unexpected Tx interrupt, can be avoid.
2356          */
2357         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2358         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2359                 vec = vec - 1; /* the last interrupt is reserved */
2360         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2361         for (i = 0; i < hw->intr_tqps_num; i++) {
2362                 /*
2363                  * Set gap limiter/rate limiter/quanity limiter algorithm
2364                  * configuration for interrupt coalesce of queue's interrupt.
2365                  */
2366                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2367                                        HNS3_TQP_INTR_GL_DEFAULT);
2368                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2369                                        HNS3_TQP_INTR_GL_DEFAULT);
2370                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2371                 /*
2372                  * QL(quantity limiter) is not used currently, just set 0 to
2373                  * close it.
2374                  */
2375                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2376
2377                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2378                                                  HNS3_RING_TYPE_TX, i);
2379                 if (ret) {
2380                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2381                                           "vector: %u, ret=%d", i, vec, ret);
2382                         return ret;
2383                 }
2384
2385                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2386                                                  HNS3_RING_TYPE_RX, i);
2387                 if (ret) {
2388                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2389                                           "vector: %u, ret=%d", i, vec, ret);
2390                         return ret;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static int
2398 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2399 {
2400         struct hns3_adapter *hns = dev->data->dev_private;
2401         struct hns3_hw *hw = &hns->hw;
2402         uint32_t max_rx_pkt_len;
2403         uint16_t mtu;
2404         int ret;
2405
2406         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2407                 return 0;
2408
2409         /*
2410          * If jumbo frames are enabled, MTU needs to be refreshed
2411          * according to the maximum RX packet length.
2412          */
2413         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2414         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2415             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2416                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2417                          "and no more than %u when jumbo frame enabled.",
2418                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2419                          (uint16_t)HNS3_MAX_FRAME_LEN);
2420                 return -EINVAL;
2421         }
2422
2423         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2424         ret = hns3_dev_mtu_set(dev, mtu);
2425         if (ret)
2426                 return ret;
2427         dev->data->mtu = mtu;
2428
2429         return 0;
2430 }
2431
2432 static int
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2434 {
2435         int ret;
2436
2437         /*
2438          * Some hardware doesn't support auto-negotiation, but users may not
2439          * configure link_speeds (default 0), which means auto-negotiation.
2440          * In this case, a warning message need to be printed, instead of
2441          * an error.
2442          */
2443         if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2444             hw->mac.support_autoneg == 0) {
2445                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2446                 return 0;
2447         }
2448
2449         if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2450                 ret = hns3_check_port_speed(hw, link_speeds);
2451                 if (ret)
2452                         return ret;
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 hns3_check_dev_conf(struct rte_eth_dev *dev)
2460 {
2461         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct rte_eth_conf *conf = &dev->data->dev_conf;
2463         int ret;
2464
2465         ret = hns3_check_mq_mode(dev);
2466         if (ret)
2467                 return ret;
2468
2469         return hns3_check_link_speed(hw, conf->link_speeds);
2470 }
2471
2472 static int
2473 hns3_dev_configure(struct rte_eth_dev *dev)
2474 {
2475         struct hns3_adapter *hns = dev->data->dev_private;
2476         struct rte_eth_conf *conf = &dev->data->dev_conf;
2477         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2478         struct hns3_hw *hw = &hns->hw;
2479         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2480         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2481         struct rte_eth_rss_conf rss_conf;
2482         bool gro_en;
2483         int ret;
2484
2485         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2486
2487         /*
2488          * Some versions of hardware network engine does not support
2489          * individually enable/disable/reset the Tx or Rx queue. These devices
2490          * must enable/disable/reset Tx and Rx queues at the same time. When the
2491          * numbers of Tx queues allocated by upper applications are not equal to
2492          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2493          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2494          * work as usual. But these fake queues are imperceptible, and can not
2495          * be used by upper applications.
2496          */
2497         if (!hns3_dev_indep_txrx_supported(hw)) {
2498                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2499                 if (ret) {
2500                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2501                                  ret);
2502                         return ret;
2503                 }
2504         }
2505
2506         hw->adapter_state = HNS3_NIC_CONFIGURING;
2507         ret = hns3_check_dev_conf(dev);
2508         if (ret)
2509                 goto cfg_err;
2510
2511         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2512                 ret = hns3_check_dcb_cfg(dev);
2513                 if (ret)
2514                         goto cfg_err;
2515         }
2516
2517         /* When RSS is not configured, redirect the packet queue 0 */
2518         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2519                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2520                 rss_conf = conf->rx_adv_conf.rss_conf;
2521                 hw->rss_dis_flag = false;
2522                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2523                 if (ret)
2524                         goto cfg_err;
2525         }
2526
2527         ret = hns3_refresh_mtu(dev, conf);
2528         if (ret)
2529                 goto cfg_err;
2530
2531         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2532         if (ret)
2533                 goto cfg_err;
2534
2535         ret = hns3_dev_configure_vlan(dev);
2536         if (ret)
2537                 goto cfg_err;
2538
2539         /* config hardware GRO */
2540         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2541         ret = hns3_config_gro(hw, gro_en);
2542         if (ret)
2543                 goto cfg_err;
2544
2545         hns3_init_rx_ptype_tble(dev);
2546         hw->adapter_state = HNS3_NIC_CONFIGURED;
2547
2548         return 0;
2549
2550 cfg_err:
2551         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2552         hw->adapter_state = HNS3_NIC_INITIALIZED;
2553
2554         return ret;
2555 }
2556
2557 static int
2558 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2559 {
2560         struct hns3_config_max_frm_size_cmd *req;
2561         struct hns3_cmd_desc desc;
2562
2563         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2564
2565         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2566         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2567         req->min_frm_size = RTE_ETHER_MIN_LEN;
2568
2569         return hns3_cmd_send(hw, &desc, 1);
2570 }
2571
2572 static int
2573 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2574 {
2575         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2576         uint16_t original_mps = hns->pf.mps;
2577         int err;
2578         int ret;
2579
2580         ret = hns3_set_mac_mtu(hw, mps);
2581         if (ret) {
2582                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2583                 return ret;
2584         }
2585
2586         hns->pf.mps = mps;
2587         ret = hns3_buffer_alloc(hw);
2588         if (ret) {
2589                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2590                 goto rollback;
2591         }
2592
2593         return 0;
2594
2595 rollback:
2596         err = hns3_set_mac_mtu(hw, original_mps);
2597         if (err) {
2598                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2599                 return ret;
2600         }
2601         hns->pf.mps = original_mps;
2602
2603         return ret;
2604 }
2605
2606 static int
2607 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2608 {
2609         struct hns3_adapter *hns = dev->data->dev_private;
2610         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2611         struct hns3_hw *hw = &hns->hw;
2612         bool is_jumbo_frame;
2613         int ret;
2614
2615         if (dev->data->dev_started) {
2616                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2617                          "before configuration", dev->data->port_id);
2618                 return -EBUSY;
2619         }
2620
2621         rte_spinlock_lock(&hw->lock);
2622         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2623         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2624
2625         /*
2626          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2627          * assign to "uint16_t" type variable.
2628          */
2629         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2630         if (ret) {
2631                 rte_spinlock_unlock(&hw->lock);
2632                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2633                          dev->data->port_id, mtu, ret);
2634                 return ret;
2635         }
2636
2637         if (is_jumbo_frame)
2638                 dev->data->dev_conf.rxmode.offloads |=
2639                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2640         else
2641                 dev->data->dev_conf.rxmode.offloads &=
2642                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2643         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2644         rte_spinlock_unlock(&hw->lock);
2645
2646         return 0;
2647 }
2648
2649 static uint32_t
2650 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2651 {
2652         uint32_t speed_capa = 0;
2653
2654         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2655                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2656         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2657                 speed_capa |= ETH_LINK_SPEED_10M;
2658         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2659                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2660         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2661                 speed_capa |= ETH_LINK_SPEED_100M;
2662         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2663                 speed_capa |= ETH_LINK_SPEED_1G;
2664
2665         return speed_capa;
2666 }
2667
2668 static uint32_t
2669 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2670 {
2671         uint32_t speed_capa = 0;
2672
2673         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2674                 speed_capa |= ETH_LINK_SPEED_1G;
2675         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2676                 speed_capa |= ETH_LINK_SPEED_10G;
2677         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2678                 speed_capa |= ETH_LINK_SPEED_25G;
2679         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2680                 speed_capa |= ETH_LINK_SPEED_40G;
2681         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2682                 speed_capa |= ETH_LINK_SPEED_50G;
2683         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2684                 speed_capa |= ETH_LINK_SPEED_100G;
2685         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2686                 speed_capa |= ETH_LINK_SPEED_200G;
2687
2688         return speed_capa;
2689 }
2690
2691 static uint32_t
2692 hns3_get_speed_capa(struct hns3_hw *hw)
2693 {
2694         struct hns3_mac *mac = &hw->mac;
2695         uint32_t speed_capa;
2696
2697         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2698                 speed_capa =
2699                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2700         else
2701                 speed_capa =
2702                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2703
2704         if (mac->support_autoneg == 0)
2705                 speed_capa |= ETH_LINK_SPEED_FIXED;
2706
2707         return speed_capa;
2708 }
2709
2710 int
2711 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2712 {
2713         struct hns3_adapter *hns = eth_dev->data->dev_private;
2714         struct hns3_hw *hw = &hns->hw;
2715         uint16_t queue_num = hw->tqps_num;
2716
2717         /*
2718          * In interrupt mode, 'max_rx_queues' is set based on the number of
2719          * MSI-X interrupt resources of the hardware.
2720          */
2721         if (hw->data->dev_conf.intr_conf.rxq == 1)
2722                 queue_num = hw->intr_tqps_num;
2723
2724         info->max_rx_queues = queue_num;
2725         info->max_tx_queues = hw->tqps_num;
2726         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2727         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2728         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2729         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2730         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2731         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2732                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2733                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2734                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2735                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2736                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2737                                  DEV_RX_OFFLOAD_KEEP_CRC |
2738                                  DEV_RX_OFFLOAD_SCATTER |
2739                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2740                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2741                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2742                                  DEV_RX_OFFLOAD_RSS_HASH |
2743                                  DEV_RX_OFFLOAD_TCP_LRO);
2744         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2745                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2746                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2747                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2748                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2749                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2750                                  DEV_TX_OFFLOAD_TCP_TSO |
2751                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2752                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2753                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2754                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2755                                  hns3_txvlan_cap_get(hw));
2756
2757         if (hns3_dev_outer_udp_cksum_supported(hw))
2758                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2759
2760         if (hns3_dev_indep_txrx_supported(hw))
2761                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2762                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2763
2764         if (hns3_dev_ptp_supported(hw))
2765                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2766
2767         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2768                 .nb_max = HNS3_MAX_RING_DESC,
2769                 .nb_min = HNS3_MIN_RING_DESC,
2770                 .nb_align = HNS3_ALIGN_RING_DESC,
2771         };
2772
2773         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2774                 .nb_max = HNS3_MAX_RING_DESC,
2775                 .nb_min = HNS3_MIN_RING_DESC,
2776                 .nb_align = HNS3_ALIGN_RING_DESC,
2777                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2778                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2779         };
2780
2781         info->speed_capa = hns3_get_speed_capa(hw);
2782         info->default_rxconf = (struct rte_eth_rxconf) {
2783                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2784                 /*
2785                  * If there are no available Rx buffer descriptors, incoming
2786                  * packets are always dropped by hardware based on hns3 network
2787                  * engine.
2788                  */
2789                 .rx_drop_en = 1,
2790                 .offloads = 0,
2791         };
2792         info->default_txconf = (struct rte_eth_txconf) {
2793                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2794                 .offloads = 0,
2795         };
2796
2797         info->vmdq_queue_num = 0;
2798
2799         info->reta_size = hw->rss_ind_tbl_size;
2800         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2801         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2802
2803         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2804         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2805         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2806         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2807         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2808         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2809
2810         return 0;
2811 }
2812
2813 static int
2814 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2815                     size_t fw_size)
2816 {
2817         struct hns3_adapter *hns = eth_dev->data->dev_private;
2818         struct hns3_hw *hw = &hns->hw;
2819         uint32_t version = hw->fw_version;
2820         int ret;
2821
2822         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2823                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2824                                       HNS3_FW_VERSION_BYTE3_S),
2825                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2826                                       HNS3_FW_VERSION_BYTE2_S),
2827                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2828                                       HNS3_FW_VERSION_BYTE1_S),
2829                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2830                                       HNS3_FW_VERSION_BYTE0_S));
2831         if (ret < 0)
2832                 return -EINVAL;
2833
2834         ret += 1; /* add the size of '\0' */
2835         if (fw_size < (size_t)ret)
2836                 return ret;
2837         else
2838                 return 0;
2839 }
2840
2841 static int
2842 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2843 {
2844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2845         int ret;
2846
2847         (void)hns3_update_link_status(hw);
2848
2849         ret = hns3_update_link_info(eth_dev);
2850         if (ret)
2851                 hw->mac.link_status = ETH_LINK_DOWN;
2852
2853         return ret;
2854 }
2855
2856 static void
2857 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2858                       struct rte_eth_link *new_link)
2859 {
2860         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2861         struct hns3_mac *mac = &hw->mac;
2862
2863         switch (mac->link_speed) {
2864         case ETH_SPEED_NUM_10M:
2865         case ETH_SPEED_NUM_100M:
2866         case ETH_SPEED_NUM_1G:
2867         case ETH_SPEED_NUM_10G:
2868         case ETH_SPEED_NUM_25G:
2869         case ETH_SPEED_NUM_40G:
2870         case ETH_SPEED_NUM_50G:
2871         case ETH_SPEED_NUM_100G:
2872         case ETH_SPEED_NUM_200G:
2873                 new_link->link_speed = mac->link_speed;
2874                 break;
2875         default:
2876                 if (mac->link_status)
2877                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2878                 else
2879                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2880                 break;
2881         }
2882
2883         new_link->link_duplex = mac->link_duplex;
2884         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2885         new_link->link_autoneg = mac->link_autoneg;
2886 }
2887
2888 static int
2889 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2890 {
2891 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2892 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2893
2894         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2895         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2896         struct hns3_mac *mac = &hw->mac;
2897         struct rte_eth_link new_link;
2898         int ret;
2899
2900         do {
2901                 ret = hns3_update_port_link_info(eth_dev);
2902                 if (ret) {
2903                         hns3_err(hw, "failed to get port link info, ret = %d.",
2904                                  ret);
2905                         break;
2906                 }
2907
2908                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2909                         break;
2910
2911                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2912         } while (retry_cnt--);
2913
2914         memset(&new_link, 0, sizeof(new_link));
2915         hns3_setup_linkstatus(eth_dev, &new_link);
2916
2917         return rte_eth_linkstatus_set(eth_dev, &new_link);
2918 }
2919
2920 static int
2921 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2922 {
2923         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2924         struct hns3_pf *pf = &hns->pf;
2925
2926         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2927                 return -EINVAL;
2928
2929         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2930
2931         return 0;
2932 }
2933
2934 static int
2935 hns3_query_function_status(struct hns3_hw *hw)
2936 {
2937 #define HNS3_QUERY_MAX_CNT              10
2938 #define HNS3_QUERY_SLEEP_MSCOEND        1
2939         struct hns3_func_status_cmd *req;
2940         struct hns3_cmd_desc desc;
2941         int timeout = 0;
2942         int ret;
2943
2944         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2945         req = (struct hns3_func_status_cmd *)desc.data;
2946
2947         do {
2948                 ret = hns3_cmd_send(hw, &desc, 1);
2949                 if (ret) {
2950                         PMD_INIT_LOG(ERR, "query function status failed %d",
2951                                      ret);
2952                         return ret;
2953                 }
2954
2955                 /* Check pf reset is done */
2956                 if (req->pf_state)
2957                         break;
2958
2959                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2960         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2961
2962         return hns3_parse_func_status(hw, req);
2963 }
2964
2965 static int
2966 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2967 {
2968         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2969         struct hns3_pf *pf = &hns->pf;
2970
2971         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2972                 /*
2973                  * The total_tqps_num obtained from firmware is maximum tqp
2974                  * numbers of this port, which should be used for PF and VFs.
2975                  * There is no need for pf to have so many tqp numbers in
2976                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2977                  * coming from config file, is assigned to maximum queue number
2978                  * for the PF of this port by user. So users can modify the
2979                  * maximum queue number of PF according to their own application
2980                  * scenarios, which is more flexible to use. In addition, many
2981                  * memories can be saved due to allocating queue statistics
2982                  * room according to the actual number of queues required. The
2983                  * maximum queue number of PF for network engine with
2984                  * revision_id greater than 0x30 is assigned by config file.
2985                  */
2986                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2987                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2988                                  "must be greater than 0.",
2989                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2990                         return -EINVAL;
2991                 }
2992
2993                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2994                                        hw->total_tqps_num);
2995         } else {
2996                 /*
2997                  * Due to the limitation on the number of PF interrupts
2998                  * available, the maximum queue number assigned to PF on
2999                  * the network engine with revision_id 0x21 is 64.
3000                  */
3001                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3002                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3003         }
3004
3005         return 0;
3006 }
3007
3008 static int
3009 hns3_query_pf_resource(struct hns3_hw *hw)
3010 {
3011         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3012         struct hns3_pf *pf = &hns->pf;
3013         struct hns3_pf_res_cmd *req;
3014         struct hns3_cmd_desc desc;
3015         int ret;
3016
3017         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3018         ret = hns3_cmd_send(hw, &desc, 1);
3019         if (ret) {
3020                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3021                 return ret;
3022         }
3023
3024         req = (struct hns3_pf_res_cmd *)desc.data;
3025         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3026                              rte_le_to_cpu_16(req->ext_tqp_num);
3027         ret = hns3_get_pf_max_tqp_num(hw);
3028         if (ret)
3029                 return ret;
3030
3031         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3032         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3033
3034         if (req->tx_buf_size)
3035                 pf->tx_buf_size =
3036                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3037         else
3038                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3039
3040         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3041
3042         if (req->dv_buf_size)
3043                 pf->dv_buf_size =
3044                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3045         else
3046                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3047
3048         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3049
3050         hw->num_msi =
3051                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3052                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3053
3054         return 0;
3055 }
3056
3057 static void
3058 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3059 {
3060         struct hns3_cfg_param_cmd *req;
3061         uint64_t mac_addr_tmp_high;
3062         uint8_t ext_rss_size_max;
3063         uint64_t mac_addr_tmp;
3064         uint32_t i;
3065
3066         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3067
3068         /* get the configuration */
3069         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3070                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3071         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3072                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3073         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3074                                            HNS3_CFG_TQP_DESC_N_M,
3075                                            HNS3_CFG_TQP_DESC_N_S);
3076
3077         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3078                                        HNS3_CFG_PHY_ADDR_M,
3079                                        HNS3_CFG_PHY_ADDR_S);
3080         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3081                                          HNS3_CFG_MEDIA_TP_M,
3082                                          HNS3_CFG_MEDIA_TP_S);
3083         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3084                                          HNS3_CFG_RX_BUF_LEN_M,
3085                                          HNS3_CFG_RX_BUF_LEN_S);
3086         /* get mac address */
3087         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3088         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3089                                            HNS3_CFG_MAC_ADDR_H_M,
3090                                            HNS3_CFG_MAC_ADDR_H_S);
3091
3092         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3093
3094         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3095                                             HNS3_CFG_DEFAULT_SPEED_M,
3096                                             HNS3_CFG_DEFAULT_SPEED_S);
3097         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3098                                            HNS3_CFG_RSS_SIZE_M,
3099                                            HNS3_CFG_RSS_SIZE_S);
3100
3101         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3102                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3103
3104         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3105         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3106
3107         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3108                                             HNS3_CFG_SPEED_ABILITY_M,
3109                                             HNS3_CFG_SPEED_ABILITY_S);
3110         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3111                                         HNS3_CFG_UMV_TBL_SPACE_M,
3112                                         HNS3_CFG_UMV_TBL_SPACE_S);
3113         if (!cfg->umv_space)
3114                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3115
3116         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3117                                                HNS3_CFG_EXT_RSS_SIZE_M,
3118                                                HNS3_CFG_EXT_RSS_SIZE_S);
3119
3120         /*
3121          * Field ext_rss_size_max obtained from firmware will be more flexible
3122          * for future changes and expansions, which is an exponent of 2, instead
3123          * of reading out directly. If this field is not zero, hns3 PF PMD
3124          * driver uses it as rss_size_max under one TC. Device, whose revision
3125          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3126          * maximum number of queues supported under a TC through this field.
3127          */
3128         if (ext_rss_size_max)
3129                 cfg->rss_size_max = 1U << ext_rss_size_max;
3130 }
3131
3132 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3133  * @hw: pointer to struct hns3_hw
3134  * @hcfg: the config structure to be getted
3135  */
3136 static int
3137 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3138 {
3139         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3140         struct hns3_cfg_param_cmd *req;
3141         uint32_t offset;
3142         uint32_t i;
3143         int ret;
3144
3145         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3146                 offset = 0;
3147                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3148                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3149                                           true);
3150                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3151                                i * HNS3_CFG_RD_LEN_BYTES);
3152                 /* Len should be divided by 4 when send to hardware */
3153                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3154                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3155                 req->offset = rte_cpu_to_le_32(offset);
3156         }
3157
3158         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3159         if (ret) {
3160                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3161                 return ret;
3162         }
3163
3164         hns3_parse_cfg(hcfg, desc);
3165
3166         return 0;
3167 }
3168
3169 static int
3170 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3171 {
3172         switch (speed_cmd) {
3173         case HNS3_CFG_SPEED_10M:
3174                 *speed = ETH_SPEED_NUM_10M;
3175                 break;
3176         case HNS3_CFG_SPEED_100M:
3177                 *speed = ETH_SPEED_NUM_100M;
3178                 break;
3179         case HNS3_CFG_SPEED_1G:
3180                 *speed = ETH_SPEED_NUM_1G;
3181                 break;
3182         case HNS3_CFG_SPEED_10G:
3183                 *speed = ETH_SPEED_NUM_10G;
3184                 break;
3185         case HNS3_CFG_SPEED_25G:
3186                 *speed = ETH_SPEED_NUM_25G;
3187                 break;
3188         case HNS3_CFG_SPEED_40G:
3189                 *speed = ETH_SPEED_NUM_40G;
3190                 break;
3191         case HNS3_CFG_SPEED_50G:
3192                 *speed = ETH_SPEED_NUM_50G;
3193                 break;
3194         case HNS3_CFG_SPEED_100G:
3195                 *speed = ETH_SPEED_NUM_100G;
3196                 break;
3197         case HNS3_CFG_SPEED_200G:
3198                 *speed = ETH_SPEED_NUM_200G;
3199                 break;
3200         default:
3201                 return -EINVAL;
3202         }
3203
3204         return 0;
3205 }
3206
3207 static void
3208 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3209 {
3210         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3211         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3212         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3213         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3214         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3215 }
3216
3217 static void
3218 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3219 {
3220         struct hns3_dev_specs_0_cmd *req0;
3221
3222         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3223
3224         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3225         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3226         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3227         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3228         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3229 }
3230
3231 static int
3232 hns3_check_dev_specifications(struct hns3_hw *hw)
3233 {
3234         if (hw->rss_ind_tbl_size == 0 ||
3235             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3236                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3237                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3238                               HNS3_RSS_IND_TBL_SIZE_MAX);
3239                 return -EINVAL;
3240         }
3241
3242         return 0;
3243 }
3244
3245 static int
3246 hns3_query_dev_specifications(struct hns3_hw *hw)
3247 {
3248         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3249         int ret;
3250         int i;
3251
3252         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3253                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3254                                           true);
3255                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3256         }
3257         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3258
3259         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3260         if (ret)
3261                 return ret;
3262
3263         hns3_parse_dev_specifications(hw, desc);
3264
3265         return hns3_check_dev_specifications(hw);
3266 }
3267
3268 static int
3269 hns3_get_capability(struct hns3_hw *hw)
3270 {
3271         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3272         struct rte_pci_device *pci_dev;
3273         struct hns3_pf *pf = &hns->pf;
3274         struct rte_eth_dev *eth_dev;
3275         uint16_t device_id;
3276         uint8_t revision;
3277         int ret;
3278
3279         eth_dev = &rte_eth_devices[hw->data->port_id];
3280         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3281         device_id = pci_dev->id.device_id;
3282
3283         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3284             device_id == HNS3_DEV_ID_50GE_RDMA ||
3285             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3286             device_id == HNS3_DEV_ID_200G_RDMA)
3287                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3288
3289         /* Get PCI revision id */
3290         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3291                                   HNS3_PCI_REVISION_ID);
3292         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3293                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3294                              ret);
3295                 return -EIO;
3296         }
3297         hw->revision = revision;
3298
3299         if (revision < PCI_REVISION_ID_HIP09_A) {
3300                 hns3_set_default_dev_specifications(hw);
3301                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3302                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3303                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3304                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3305                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3306                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3307                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3308                 hw->rss_info.ipv6_sctp_offload_supported = false;
3309                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3310                 return 0;
3311         }
3312
3313         ret = hns3_query_dev_specifications(hw);
3314         if (ret) {
3315                 PMD_INIT_LOG(ERR,
3316                              "failed to query dev specifications, ret = %d",
3317                              ret);
3318                 return ret;
3319         }
3320
3321         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3322         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3323         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3324         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3325         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3326         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3327         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3328         hw->rss_info.ipv6_sctp_offload_supported = true;
3329         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3330
3331         return 0;
3332 }
3333
3334 static int
3335 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3336 {
3337         int ret;
3338
3339         switch (media_type) {
3340         case HNS3_MEDIA_TYPE_COPPER:
3341                 if (!hns3_dev_copper_supported(hw)) {
3342                         PMD_INIT_LOG(ERR,
3343                                      "Media type is copper, not supported.");
3344                         ret = -EOPNOTSUPP;
3345                 } else {
3346                         ret = 0;
3347                 }
3348                 break;
3349         case HNS3_MEDIA_TYPE_FIBER:
3350                 ret = 0;
3351                 break;
3352         case HNS3_MEDIA_TYPE_BACKPLANE:
3353                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3354                 ret = -EOPNOTSUPP;
3355                 break;
3356         default:
3357                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3358                 ret = -EINVAL;
3359                 break;
3360         }
3361
3362         return ret;
3363 }
3364
3365 static int
3366 hns3_get_board_configuration(struct hns3_hw *hw)
3367 {
3368         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3369         struct hns3_pf *pf = &hns->pf;
3370         struct hns3_cfg cfg;
3371         int ret;
3372
3373         ret = hns3_get_board_cfg(hw, &cfg);
3374         if (ret) {
3375                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3376                 return ret;
3377         }
3378
3379         ret = hns3_check_media_type(hw, cfg.media_type);
3380         if (ret)
3381                 return ret;
3382
3383         hw->mac.media_type = cfg.media_type;
3384         hw->rss_size_max = cfg.rss_size_max;
3385         hw->rss_dis_flag = false;
3386         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3387         hw->mac.phy_addr = cfg.phy_addr;
3388         hw->mac.default_addr_setted = false;
3389         hw->num_tx_desc = cfg.tqp_desc_num;
3390         hw->num_rx_desc = cfg.tqp_desc_num;
3391         hw->dcb_info.num_pg = 1;
3392         hw->dcb_info.hw_pfc_map = 0;
3393
3394         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3395         if (ret) {
3396                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3397                              cfg.default_speed, ret);
3398                 return ret;
3399         }
3400
3401         pf->tc_max = cfg.tc_num;
3402         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3403                 PMD_INIT_LOG(WARNING,
3404                              "Get TC num(%u) from flash, set TC num to 1",
3405                              pf->tc_max);
3406                 pf->tc_max = 1;
3407         }
3408
3409         /* Dev does not support DCB */
3410         if (!hns3_dev_dcb_supported(hw)) {
3411                 pf->tc_max = 1;
3412                 pf->pfc_max = 0;
3413         } else
3414                 pf->pfc_max = pf->tc_max;
3415
3416         hw->dcb_info.num_tc = 1;
3417         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3418                                      hw->tqps_num / hw->dcb_info.num_tc);
3419         hns3_set_bit(hw->hw_tc_map, 0, 1);
3420         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3421
3422         pf->wanted_umv_size = cfg.umv_space;
3423
3424         return ret;
3425 }
3426
3427 static int
3428 hns3_get_configuration(struct hns3_hw *hw)
3429 {
3430         int ret;
3431
3432         ret = hns3_query_function_status(hw);
3433         if (ret) {
3434                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3435                 return ret;
3436         }
3437
3438         /* Get device capability */
3439         ret = hns3_get_capability(hw);
3440         if (ret) {
3441                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3442                 return ret;
3443         }
3444
3445         /* Get pf resource */
3446         ret = hns3_query_pf_resource(hw);
3447         if (ret) {
3448                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3449                 return ret;
3450         }
3451
3452         ret = hns3_get_board_configuration(hw);
3453         if (ret) {
3454                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3455                 return ret;
3456         }
3457
3458         ret = hns3_query_dev_fec_info(hw);
3459         if (ret)
3460                 PMD_INIT_LOG(ERR,
3461                              "failed to query FEC information, ret = %d", ret);
3462
3463         return ret;
3464 }
3465
3466 static int
3467 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3468                       uint16_t tqp_vid, bool is_pf)
3469 {
3470         struct hns3_tqp_map_cmd *req;
3471         struct hns3_cmd_desc desc;
3472         int ret;
3473
3474         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3475
3476         req = (struct hns3_tqp_map_cmd *)desc.data;
3477         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3478         req->tqp_vf = func_id;
3479         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3480         if (!is_pf)
3481                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3482         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3483
3484         ret = hns3_cmd_send(hw, &desc, 1);
3485         if (ret)
3486                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3487
3488         return ret;
3489 }
3490
3491 static int
3492 hns3_map_tqp(struct hns3_hw *hw)
3493 {
3494         int ret;
3495         int i;
3496
3497         /*
3498          * In current version, VF is not supported when PF is driven by DPDK
3499          * driver, so we assign total tqps_num tqps allocated to this port
3500          * to PF.
3501          */
3502         for (i = 0; i < hw->total_tqps_num; i++) {
3503                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3504                 if (ret)
3505                         return ret;
3506         }
3507
3508         return 0;
3509 }
3510
3511 static int
3512 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3513 {
3514         struct hns3_config_mac_speed_dup_cmd *req;
3515         struct hns3_cmd_desc desc;
3516         int ret;
3517
3518         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3519
3520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3521
3522         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3523
3524         switch (speed) {
3525         case ETH_SPEED_NUM_10M:
3526                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3527                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3528                 break;
3529         case ETH_SPEED_NUM_100M:
3530                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3531                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3532                 break;
3533         case ETH_SPEED_NUM_1G:
3534                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3535                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3536                 break;
3537         case ETH_SPEED_NUM_10G:
3538                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3539                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3540                 break;
3541         case ETH_SPEED_NUM_25G:
3542                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3543                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3544                 break;
3545         case ETH_SPEED_NUM_40G:
3546                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3547                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3548                 break;
3549         case ETH_SPEED_NUM_50G:
3550                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3551                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3552                 break;
3553         case ETH_SPEED_NUM_100G:
3554                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3555                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3556                 break;
3557         case ETH_SPEED_NUM_200G:
3558                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3559                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3560                 break;
3561         default:
3562                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3563                 return -EINVAL;
3564         }
3565
3566         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3567
3568         ret = hns3_cmd_send(hw, &desc, 1);
3569         if (ret)
3570                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3571
3572         return ret;
3573 }
3574
3575 static int
3576 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3577 {
3578         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3579         struct hns3_pf *pf = &hns->pf;
3580         struct hns3_priv_buf *priv;
3581         uint32_t i, total_size;
3582
3583         total_size = pf->pkt_buf_size;
3584
3585         /* alloc tx buffer for all enabled tc */
3586         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3587                 priv = &buf_alloc->priv_buf[i];
3588
3589                 if (hw->hw_tc_map & BIT(i)) {
3590                         if (total_size < pf->tx_buf_size)
3591                                 return -ENOMEM;
3592
3593                         priv->tx_buf_size = pf->tx_buf_size;
3594                 } else
3595                         priv->tx_buf_size = 0;
3596
3597                 total_size -= priv->tx_buf_size;
3598         }
3599
3600         return 0;
3601 }
3602
3603 static int
3604 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3605 {
3606 /* TX buffer size is unit by 128 byte */
3607 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3608 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3609         struct hns3_tx_buff_alloc_cmd *req;
3610         struct hns3_cmd_desc desc;
3611         uint32_t buf_size;
3612         uint32_t i;
3613         int ret;
3614
3615         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3616
3617         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3618         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3619                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3620
3621                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3622                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3623                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3624         }
3625
3626         ret = hns3_cmd_send(hw, &desc, 1);
3627         if (ret)
3628                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3629
3630         return ret;
3631 }
3632
3633 static int
3634 hns3_get_tc_num(struct hns3_hw *hw)
3635 {
3636         int cnt = 0;
3637         uint8_t i;
3638
3639         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3640                 if (hw->hw_tc_map & BIT(i))
3641                         cnt++;
3642         return cnt;
3643 }
3644
3645 static uint32_t
3646 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3647 {
3648         struct hns3_priv_buf *priv;
3649         uint32_t rx_priv = 0;
3650         int i;
3651
3652         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3653                 priv = &buf_alloc->priv_buf[i];
3654                 if (priv->enable)
3655                         rx_priv += priv->buf_size;
3656         }
3657         return rx_priv;
3658 }
3659
3660 static uint32_t
3661 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3662 {
3663         uint32_t total_tx_size = 0;
3664         uint32_t i;
3665
3666         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3667                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3668
3669         return total_tx_size;
3670 }
3671
3672 /* Get the number of pfc enabled TCs, which have private buffer */
3673 static int
3674 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3675 {
3676         struct hns3_priv_buf *priv;
3677         int cnt = 0;
3678         uint8_t i;
3679
3680         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3681                 priv = &buf_alloc->priv_buf[i];
3682                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3683                         cnt++;
3684         }
3685
3686         return cnt;
3687 }
3688
3689 /* Get the number of pfc disabled TCs, which have private buffer */
3690 static int
3691 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3692                          struct hns3_pkt_buf_alloc *buf_alloc)
3693 {
3694         struct hns3_priv_buf *priv;
3695         int cnt = 0;
3696         uint8_t i;
3697
3698         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3699                 priv = &buf_alloc->priv_buf[i];
3700                 if (hw->hw_tc_map & BIT(i) &&
3701                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3702                         cnt++;
3703         }
3704
3705         return cnt;
3706 }
3707
3708 static bool
3709 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3710                   uint32_t rx_all)
3711 {
3712         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3713         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3714         struct hns3_pf *pf = &hns->pf;
3715         uint32_t shared_buf, aligned_mps;
3716         uint32_t rx_priv;
3717         uint8_t tc_num;
3718         uint8_t i;
3719
3720         tc_num = hns3_get_tc_num(hw);
3721         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3722
3723         if (hns3_dev_dcb_supported(hw))
3724                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3725                                         pf->dv_buf_size;
3726         else
3727                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3728                                         + pf->dv_buf_size;
3729
3730         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3731         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3732                              HNS3_BUF_SIZE_UNIT);
3733
3734         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3735         if (rx_all < rx_priv + shared_std)
3736                 return false;
3737
3738         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3739         buf_alloc->s_buf.buf_size = shared_buf;
3740         if (hns3_dev_dcb_supported(hw)) {
3741                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3742                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3743                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3744                                   HNS3_BUF_SIZE_UNIT);
3745         } else {
3746                 buf_alloc->s_buf.self.high =
3747                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3748                 buf_alloc->s_buf.self.low = aligned_mps;
3749         }
3750
3751         if (hns3_dev_dcb_supported(hw)) {
3752                 hi_thrd = shared_buf - pf->dv_buf_size;
3753
3754                 if (tc_num <= NEED_RESERVE_TC_NUM)
3755                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3756                                   BUF_MAX_PERCENT;
3757
3758                 if (tc_num)
3759                         hi_thrd = hi_thrd / tc_num;
3760
3761                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3762                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3763                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3764         } else {
3765                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3766                 lo_thrd = aligned_mps;
3767         }
3768
3769         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3770                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3771                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3772         }
3773
3774         return true;
3775 }
3776
3777 static bool
3778 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3779                      struct hns3_pkt_buf_alloc *buf_alloc)
3780 {
3781         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3782         struct hns3_pf *pf = &hns->pf;
3783         struct hns3_priv_buf *priv;
3784         uint32_t aligned_mps;
3785         uint32_t rx_all;
3786         uint8_t i;
3787
3788         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3789         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3790
3791         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3792                 priv = &buf_alloc->priv_buf[i];
3793
3794                 priv->enable = 0;
3795                 priv->wl.low = 0;
3796                 priv->wl.high = 0;
3797                 priv->buf_size = 0;
3798
3799                 if (!(hw->hw_tc_map & BIT(i)))
3800                         continue;
3801
3802                 priv->enable = 1;
3803                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3804                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3805                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3806                                                 HNS3_BUF_SIZE_UNIT);
3807                 } else {
3808                         priv->wl.low = 0;
3809                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3810                                         aligned_mps;
3811                 }
3812
3813                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3814         }
3815
3816         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3817 }
3818
3819 static bool
3820 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3821                              struct hns3_pkt_buf_alloc *buf_alloc)
3822 {
3823         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3824         struct hns3_pf *pf = &hns->pf;
3825         struct hns3_priv_buf *priv;
3826         int no_pfc_priv_num;
3827         uint32_t rx_all;
3828         uint8_t mask;
3829         int i;
3830
3831         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3832         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3833
3834         /* let the last to be cleared first */
3835         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3836                 priv = &buf_alloc->priv_buf[i];
3837                 mask = BIT((uint8_t)i);
3838
3839                 if (hw->hw_tc_map & mask &&
3840                     !(hw->dcb_info.hw_pfc_map & mask)) {
3841                         /* Clear the no pfc TC private buffer */
3842                         priv->wl.low = 0;
3843                         priv->wl.high = 0;
3844                         priv->buf_size = 0;
3845                         priv->enable = 0;
3846                         no_pfc_priv_num--;
3847                 }
3848
3849                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3850                     no_pfc_priv_num == 0)
3851                         break;
3852         }
3853
3854         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3855 }
3856
3857 static bool
3858 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3859                            struct hns3_pkt_buf_alloc *buf_alloc)
3860 {
3861         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3862         struct hns3_pf *pf = &hns->pf;
3863         struct hns3_priv_buf *priv;
3864         uint32_t rx_all;
3865         int pfc_priv_num;
3866         uint8_t mask;
3867         int i;
3868
3869         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3870         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3871
3872         /* let the last to be cleared first */
3873         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3874                 priv = &buf_alloc->priv_buf[i];
3875                 mask = BIT((uint8_t)i);
3876                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3877                         /* Reduce the number of pfc TC with private buffer */
3878                         priv->wl.low = 0;
3879                         priv->enable = 0;
3880                         priv->wl.high = 0;
3881                         priv->buf_size = 0;
3882                         pfc_priv_num--;
3883                 }
3884                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3885                     pfc_priv_num == 0)
3886                         break;
3887         }
3888
3889         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3890 }
3891
3892 static bool
3893 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3894                           struct hns3_pkt_buf_alloc *buf_alloc)
3895 {
3896 #define COMPENSATE_BUFFER       0x3C00
3897 #define COMPENSATE_HALF_MPS_NUM 5
3898 #define PRIV_WL_GAP             0x1800
3899         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3900         struct hns3_pf *pf = &hns->pf;
3901         uint32_t tc_num = hns3_get_tc_num(hw);
3902         uint32_t half_mps = pf->mps >> 1;
3903         struct hns3_priv_buf *priv;
3904         uint32_t min_rx_priv;
3905         uint32_t rx_priv;
3906         uint8_t i;
3907
3908         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3909         if (tc_num)
3910                 rx_priv = rx_priv / tc_num;
3911
3912         if (tc_num <= NEED_RESERVE_TC_NUM)
3913                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3914
3915         /*
3916          * Minimum value of private buffer in rx direction (min_rx_priv) is
3917          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3918          * buffer if rx_priv is greater than min_rx_priv.
3919          */
3920         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3921                         COMPENSATE_HALF_MPS_NUM * half_mps;
3922         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3923         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3924
3925         if (rx_priv < min_rx_priv)
3926                 return false;
3927
3928         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3929                 priv = &buf_alloc->priv_buf[i];
3930                 priv->enable = 0;
3931                 priv->wl.low = 0;
3932                 priv->wl.high = 0;
3933                 priv->buf_size = 0;
3934
3935                 if (!(hw->hw_tc_map & BIT(i)))
3936                         continue;
3937
3938                 priv->enable = 1;
3939                 priv->buf_size = rx_priv;
3940                 priv->wl.high = rx_priv - pf->dv_buf_size;
3941                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3942         }
3943
3944         buf_alloc->s_buf.buf_size = 0;
3945
3946         return true;
3947 }
3948
3949 /*
3950  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3951  * @hw: pointer to struct hns3_hw
3952  * @buf_alloc: pointer to buffer calculation data
3953  * @return: 0: calculate sucessful, negative: fail
3954  */
3955 static int
3956 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3957 {
3958         /* When DCB is not supported, rx private buffer is not allocated. */
3959         if (!hns3_dev_dcb_supported(hw)) {
3960                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3961                 struct hns3_pf *pf = &hns->pf;
3962                 uint32_t rx_all = pf->pkt_buf_size;
3963
3964                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3965                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3966                         return -ENOMEM;
3967
3968                 return 0;
3969         }
3970
3971         /*
3972          * Try to allocate privated packet buffer for all TCs without share
3973          * buffer.
3974          */
3975         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3976                 return 0;
3977
3978         /*
3979          * Try to allocate privated packet buffer for all TCs with share
3980          * buffer.
3981          */
3982         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3983                 return 0;
3984
3985         /*
3986          * For different application scenes, the enabled port number, TC number
3987          * and no_drop TC number are different. In order to obtain the better
3988          * performance, software could allocate the buffer size and configure
3989          * the waterline by trying to decrease the private buffer size according
3990          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3991          * enabled tc.
3992          */
3993         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3994                 return 0;
3995
3996         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3997                 return 0;
3998
3999         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4000                 return 0;
4001
4002         return -ENOMEM;
4003 }
4004
4005 static int
4006 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4007 {
4008         struct hns3_rx_priv_buff_cmd *req;
4009         struct hns3_cmd_desc desc;
4010         uint32_t buf_size;
4011         int ret;
4012         int i;
4013
4014         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4015         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4016
4017         /* Alloc private buffer TCs */
4018         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4019                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4020
4021                 req->buf_num[i] =
4022                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4023                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4024         }
4025
4026         buf_size = buf_alloc->s_buf.buf_size;
4027         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4028                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4029
4030         ret = hns3_cmd_send(hw, &desc, 1);
4031         if (ret)
4032                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4033
4034         return ret;
4035 }
4036
4037 static int
4038 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4039 {
4040 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4041         struct hns3_rx_priv_wl_buf *req;
4042         struct hns3_priv_buf *priv;
4043         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4044         int i, j;
4045         int ret;
4046
4047         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4048                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4049                                           false);
4050                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4051
4052                 /* The first descriptor set the NEXT bit to 1 */
4053                 if (i == 0)
4054                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4055                 else
4056                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4057
4058                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4059                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4060
4061                         priv = &buf_alloc->priv_buf[idx];
4062                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4063                                                         HNS3_BUF_UNIT_S);
4064                         req->tc_wl[j].high |=
4065                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4066                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4067                                                         HNS3_BUF_UNIT_S);
4068                         req->tc_wl[j].low |=
4069                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4070                 }
4071         }
4072
4073         /* Send 2 descriptor at one time */
4074         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4075         if (ret)
4076                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4077                              ret);
4078         return ret;
4079 }
4080
4081 static int
4082 hns3_common_thrd_config(struct hns3_hw *hw,
4083                         struct hns3_pkt_buf_alloc *buf_alloc)
4084 {
4085 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4086         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4087         struct hns3_rx_com_thrd *req;
4088         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4089         struct hns3_tc_thrd *tc;
4090         int tc_idx;
4091         int i, j;
4092         int ret;
4093
4094         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4095                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4096                                           false);
4097                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4098
4099                 /* The first descriptor set the NEXT bit to 1 */
4100                 if (i == 0)
4101                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4102                 else
4103                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4104
4105                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4106                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4107                         tc = &s_buf->tc_thrd[tc_idx];
4108
4109                         req->com_thrd[j].high =
4110                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4111                         req->com_thrd[j].high |=
4112                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4113                         req->com_thrd[j].low =
4114                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4115                         req->com_thrd[j].low |=
4116                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4117                 }
4118         }
4119
4120         /* Send 2 descriptors at one time */
4121         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4122         if (ret)
4123                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4124
4125         return ret;
4126 }
4127
4128 static int
4129 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4130 {
4131         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4132         struct hns3_rx_com_wl *req;
4133         struct hns3_cmd_desc desc;
4134         int ret;
4135
4136         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4137
4138         req = (struct hns3_rx_com_wl *)desc.data;
4139         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4140         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4141
4142         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4143         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4144
4145         ret = hns3_cmd_send(hw, &desc, 1);
4146         if (ret)
4147                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4148
4149         return ret;
4150 }
4151
4152 int
4153 hns3_buffer_alloc(struct hns3_hw *hw)
4154 {
4155         struct hns3_pkt_buf_alloc pkt_buf;
4156         int ret;
4157
4158         memset(&pkt_buf, 0, sizeof(pkt_buf));
4159         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4160         if (ret) {
4161                 PMD_INIT_LOG(ERR,
4162                              "could not calc tx buffer size for all TCs %d",
4163                              ret);
4164                 return ret;
4165         }
4166
4167         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4168         if (ret) {
4169                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4170                 return ret;
4171         }
4172
4173         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4174         if (ret) {
4175                 PMD_INIT_LOG(ERR,
4176                              "could not calc rx priv buffer size for all TCs %d",
4177                              ret);
4178                 return ret;
4179         }
4180
4181         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4182         if (ret) {
4183                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4184                 return ret;
4185         }
4186
4187         if (hns3_dev_dcb_supported(hw)) {
4188                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4189                 if (ret) {
4190                         PMD_INIT_LOG(ERR,
4191                                      "could not configure rx private waterline %d",
4192                                      ret);
4193                         return ret;
4194                 }
4195
4196                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4197                 if (ret) {
4198                         PMD_INIT_LOG(ERR,
4199                                      "could not configure common threshold %d",
4200                                      ret);
4201                         return ret;
4202                 }
4203         }
4204
4205         ret = hns3_common_wl_config(hw, &pkt_buf);
4206         if (ret)
4207                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4208                              ret);
4209
4210         return ret;
4211 }
4212
4213 static int
4214 hns3_mac_init(struct hns3_hw *hw)
4215 {
4216         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4217         struct hns3_mac *mac = &hw->mac;
4218         struct hns3_pf *pf = &hns->pf;
4219         int ret;
4220
4221         pf->support_sfp_query = true;
4222         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4223         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4224         if (ret) {
4225                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4226                 return ret;
4227         }
4228
4229         mac->link_status = ETH_LINK_DOWN;
4230
4231         return hns3_config_mtu(hw, pf->mps);
4232 }
4233
4234 static int
4235 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4236 {
4237 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4238 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4239 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4240 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4241         int return_status;
4242
4243         if (cmdq_resp) {
4244                 PMD_INIT_LOG(ERR,
4245                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4246                              cmdq_resp);
4247                 return -EIO;
4248         }
4249
4250         switch (resp_code) {
4251         case HNS3_ETHERTYPE_SUCCESS_ADD:
4252         case HNS3_ETHERTYPE_ALREADY_ADD:
4253                 return_status = 0;
4254                 break;
4255         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4256                 PMD_INIT_LOG(ERR,
4257                              "add mac ethertype failed for manager table overflow.");
4258                 return_status = -EIO;
4259                 break;
4260         case HNS3_ETHERTYPE_KEY_CONFLICT:
4261                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4262                 return_status = -EIO;
4263                 break;
4264         default:
4265                 PMD_INIT_LOG(ERR,
4266                              "add mac ethertype failed for undefined, code=%u.",
4267                              resp_code);
4268                 return_status = -EIO;
4269                 break;
4270         }
4271
4272         return return_status;
4273 }
4274
4275 static int
4276 hns3_add_mgr_tbl(struct hns3_hw *hw,
4277                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4278 {
4279         struct hns3_cmd_desc desc;
4280         uint8_t resp_code;
4281         uint16_t retval;
4282         int ret;
4283
4284         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4285         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4286
4287         ret = hns3_cmd_send(hw, &desc, 1);
4288         if (ret) {
4289                 PMD_INIT_LOG(ERR,
4290                              "add mac ethertype failed for cmd_send, ret =%d.",
4291                              ret);
4292                 return ret;
4293         }
4294
4295         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4296         retval = rte_le_to_cpu_16(desc.retval);
4297
4298         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4299 }
4300
4301 static void
4302 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4303                      int *table_item_num)
4304 {
4305         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4306
4307         /*
4308          * In current version, we add one item in management table as below:
4309          * 0x0180C200000E -- LLDP MC address
4310          */
4311         tbl = mgr_table;
4312         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4313         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4314         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4315         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4316         tbl->i_port_bitmap = 0x1;
4317         *table_item_num = 1;
4318 }
4319
4320 static int
4321 hns3_init_mgr_tbl(struct hns3_hw *hw)
4322 {
4323 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4324         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4325         int table_item_num;
4326         int ret;
4327         int i;
4328
4329         memset(mgr_table, 0, sizeof(mgr_table));
4330         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4331         for (i = 0; i < table_item_num; i++) {
4332                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4333                 if (ret) {
4334                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4335                                      ret);
4336                         return ret;
4337                 }
4338         }
4339
4340         return 0;
4341 }
4342
4343 static void
4344 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4345                         bool en_mc, bool en_bc, int vport_id)
4346 {
4347         if (!param)
4348                 return;
4349
4350         memset(param, 0, sizeof(struct hns3_promisc_param));
4351         if (en_uc)
4352                 param->enable = HNS3_PROMISC_EN_UC;
4353         if (en_mc)
4354                 param->enable |= HNS3_PROMISC_EN_MC;
4355         if (en_bc)
4356                 param->enable |= HNS3_PROMISC_EN_BC;
4357         param->vf_id = vport_id;
4358 }
4359
4360 static int
4361 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4362 {
4363         struct hns3_promisc_cfg_cmd *req;
4364         struct hns3_cmd_desc desc;
4365         int ret;
4366
4367         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4368
4369         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4370         req->vf_id = param->vf_id;
4371         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4372             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4373
4374         ret = hns3_cmd_send(hw, &desc, 1);
4375         if (ret)
4376                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4377
4378         return ret;
4379 }
4380
4381 static int
4382 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4383 {
4384         struct hns3_promisc_param param;
4385         bool en_bc_pmc = true;
4386         uint8_t vf_id;
4387
4388         /*
4389          * In current version VF is not supported when PF is driven by DPDK
4390          * driver, just need to configure parameters for PF vport.
4391          */
4392         vf_id = HNS3_PF_FUNC_ID;
4393
4394         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4395         return hns3_cmd_set_promisc_mode(hw, &param);
4396 }
4397
4398 static int
4399 hns3_promisc_init(struct hns3_hw *hw)
4400 {
4401         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4402         struct hns3_pf *pf = &hns->pf;
4403         struct hns3_promisc_param param;
4404         uint16_t func_id;
4405         int ret;
4406
4407         ret = hns3_set_promisc_mode(hw, false, false);
4408         if (ret) {
4409                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4410                 return ret;
4411         }
4412
4413         /*
4414          * In current version VFs are not supported when PF is driven by DPDK
4415          * driver. After PF has been taken over by DPDK, the original VF will
4416          * be invalid. So, there is a possibility of entry residues. It should
4417          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4418          * during init.
4419          */
4420         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4421                 hns3_promisc_param_init(&param, false, false, false, func_id);
4422                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4423                 if (ret) {
4424                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4425                                         " ret = %d", func_id, ret);
4426                         return ret;
4427                 }
4428         }
4429
4430         return 0;
4431 }
4432
4433 static void
4434 hns3_promisc_uninit(struct hns3_hw *hw)
4435 {
4436         struct hns3_promisc_param param;
4437         uint16_t func_id;
4438         int ret;
4439
4440         func_id = HNS3_PF_FUNC_ID;
4441
4442         /*
4443          * In current version VFs are not supported when PF is driven by
4444          * DPDK driver, and VFs' promisc mode status has been cleared during
4445          * init and their status will not change. So just clear PF's promisc
4446          * mode status during uninit.
4447          */
4448         hns3_promisc_param_init(&param, false, false, false, func_id);
4449         ret = hns3_cmd_set_promisc_mode(hw, &param);
4450         if (ret)
4451                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4452                                 " uninit, ret = %d", ret);
4453 }
4454
4455 static int
4456 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4457 {
4458         bool allmulti = dev->data->all_multicast ? true : false;
4459         struct hns3_adapter *hns = dev->data->dev_private;
4460         struct hns3_hw *hw = &hns->hw;
4461         uint64_t offloads;
4462         int err;
4463         int ret;
4464
4465         rte_spinlock_lock(&hw->lock);
4466         ret = hns3_set_promisc_mode(hw, true, true);
4467         if (ret) {
4468                 rte_spinlock_unlock(&hw->lock);
4469                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4470                          ret);
4471                 return ret;
4472         }
4473
4474         /*
4475          * When promiscuous mode was enabled, disable the vlan filter to let
4476          * all packets coming in in the receiving direction.
4477          */
4478         offloads = dev->data->dev_conf.rxmode.offloads;
4479         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4480                 ret = hns3_enable_vlan_filter(hns, false);
4481                 if (ret) {
4482                         hns3_err(hw, "failed to enable promiscuous mode due to "
4483                                      "failure to disable vlan filter, ret = %d",
4484                                  ret);
4485                         err = hns3_set_promisc_mode(hw, false, allmulti);
4486                         if (err)
4487                                 hns3_err(hw, "failed to restore promiscuous "
4488                                          "status after disable vlan filter "
4489                                          "failed during enabling promiscuous "
4490                                          "mode, ret = %d", ret);
4491                 }
4492         }
4493
4494         rte_spinlock_unlock(&hw->lock);
4495
4496         return ret;
4497 }
4498
4499 static int
4500 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4501 {
4502         bool allmulti = dev->data->all_multicast ? true : false;
4503         struct hns3_adapter *hns = dev->data->dev_private;
4504         struct hns3_hw *hw = &hns->hw;
4505         uint64_t offloads;
4506         int err;
4507         int ret;
4508
4509         /* If now in all_multicast mode, must remain in all_multicast mode. */
4510         rte_spinlock_lock(&hw->lock);
4511         ret = hns3_set_promisc_mode(hw, false, allmulti);
4512         if (ret) {
4513                 rte_spinlock_unlock(&hw->lock);
4514                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4515                          ret);
4516                 return ret;
4517         }
4518         /* when promiscuous mode was disabled, restore the vlan filter status */
4519         offloads = dev->data->dev_conf.rxmode.offloads;
4520         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4521                 ret = hns3_enable_vlan_filter(hns, true);
4522                 if (ret) {
4523                         hns3_err(hw, "failed to disable promiscuous mode due to"
4524                                  " failure to restore vlan filter, ret = %d",
4525                                  ret);
4526                         err = hns3_set_promisc_mode(hw, true, true);
4527                         if (err)
4528                                 hns3_err(hw, "failed to restore promiscuous "
4529                                          "status after enabling vlan filter "
4530                                          "failed during disabling promiscuous "
4531                                          "mode, ret = %d", ret);
4532                 }
4533         }
4534         rte_spinlock_unlock(&hw->lock);
4535
4536         return ret;
4537 }
4538
4539 static int
4540 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4541 {
4542         struct hns3_adapter *hns = dev->data->dev_private;
4543         struct hns3_hw *hw = &hns->hw;
4544         int ret;
4545
4546         if (dev->data->promiscuous)
4547                 return 0;
4548
4549         rte_spinlock_lock(&hw->lock);
4550         ret = hns3_set_promisc_mode(hw, false, true);
4551         rte_spinlock_unlock(&hw->lock);
4552         if (ret)
4553                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4554                          ret);
4555
4556         return ret;
4557 }
4558
4559 static int
4560 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4561 {
4562         struct hns3_adapter *hns = dev->data->dev_private;
4563         struct hns3_hw *hw = &hns->hw;
4564         int ret;
4565
4566         /* If now in promiscuous mode, must remain in all_multicast mode. */
4567         if (dev->data->promiscuous)
4568                 return 0;
4569
4570         rte_spinlock_lock(&hw->lock);
4571         ret = hns3_set_promisc_mode(hw, false, false);
4572         rte_spinlock_unlock(&hw->lock);
4573         if (ret)
4574                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4575                          ret);
4576
4577         return ret;
4578 }
4579
4580 static int
4581 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4582 {
4583         struct hns3_hw *hw = &hns->hw;
4584         bool allmulti = hw->data->all_multicast ? true : false;
4585         int ret;
4586
4587         if (hw->data->promiscuous) {
4588                 ret = hns3_set_promisc_mode(hw, true, true);
4589                 if (ret)
4590                         hns3_err(hw, "failed to restore promiscuous mode, "
4591                                  "ret = %d", ret);
4592                 return ret;
4593         }
4594
4595         ret = hns3_set_promisc_mode(hw, false, allmulti);
4596         if (ret)
4597                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4598                          ret);
4599         return ret;
4600 }
4601
4602 static int
4603 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4604 {
4605         struct hns3_sfp_info_cmd *resp;
4606         struct hns3_cmd_desc desc;
4607         int ret;
4608
4609         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4610         resp = (struct hns3_sfp_info_cmd *)desc.data;
4611         resp->query_type = HNS3_ACTIVE_QUERY;
4612
4613         ret = hns3_cmd_send(hw, &desc, 1);
4614         if (ret == -EOPNOTSUPP) {
4615                 hns3_warn(hw, "firmware does not support get SFP info,"
4616                           " ret = %d.", ret);
4617                 return ret;
4618         } else if (ret) {
4619                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4620                 return ret;
4621         }
4622
4623         /*
4624          * In some case, the speed of MAC obtained from firmware may be 0, it
4625          * shouldn't be set to mac->speed.
4626          */
4627         if (!rte_le_to_cpu_32(resp->sfp_speed))
4628                 return 0;
4629
4630         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4631         /*
4632          * if resp->supported_speed is 0, it means it's an old version
4633          * firmware, do not update these params.
4634          */
4635         if (resp->supported_speed) {
4636                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4637                 mac_info->supported_speed =
4638                                         rte_le_to_cpu_32(resp->supported_speed);
4639                 mac_info->support_autoneg = resp->autoneg_ability;
4640                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4641                                         : ETH_LINK_AUTONEG;
4642         } else {
4643                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4644         }
4645
4646         return 0;
4647 }
4648
4649 static uint8_t
4650 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4651 {
4652         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4653                 duplex = ETH_LINK_FULL_DUPLEX;
4654
4655         return duplex;
4656 }
4657
4658 static int
4659 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4660 {
4661         struct hns3_mac *mac = &hw->mac;
4662         int ret;
4663
4664         duplex = hns3_check_speed_dup(duplex, speed);
4665         if (mac->link_speed == speed && mac->link_duplex == duplex)
4666                 return 0;
4667
4668         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4669         if (ret)
4670                 return ret;
4671
4672         ret = hns3_port_shaper_update(hw, speed);
4673         if (ret)
4674                 return ret;
4675
4676         mac->link_speed = speed;
4677         mac->link_duplex = duplex;
4678
4679         return 0;
4680 }
4681
4682 static int
4683 hns3_update_fiber_link_info(struct hns3_hw *hw)
4684 {
4685         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4686         struct hns3_mac *mac = &hw->mac;
4687         struct hns3_mac mac_info;
4688         int ret;
4689
4690         /* If firmware do not support get SFP/qSFP speed, return directly */
4691         if (!pf->support_sfp_query)
4692                 return 0;
4693
4694         memset(&mac_info, 0, sizeof(struct hns3_mac));
4695         ret = hns3_get_sfp_info(hw, &mac_info);
4696         if (ret == -EOPNOTSUPP) {
4697                 pf->support_sfp_query = false;
4698                 return ret;
4699         } else if (ret)
4700                 return ret;
4701
4702         /* Do nothing if no SFP */
4703         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4704                 return 0;
4705
4706         /*
4707          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4708          * to reconfigure the speed of MAC. Otherwise, it indicates
4709          * that the current firmware only supports to obtain the
4710          * speed of the SFP, and the speed of MAC needs to reconfigure.
4711          */
4712         mac->query_type = mac_info.query_type;
4713         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4714                 if (mac_info.link_speed != mac->link_speed) {
4715                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4716                         if (ret)
4717                                 return ret;
4718                 }
4719
4720                 mac->link_speed = mac_info.link_speed;
4721                 mac->supported_speed = mac_info.supported_speed;
4722                 mac->support_autoneg = mac_info.support_autoneg;
4723                 mac->link_autoneg = mac_info.link_autoneg;
4724
4725                 return 0;
4726         }
4727
4728         /* Config full duplex for SFP */
4729         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4730                                       ETH_LINK_FULL_DUPLEX);
4731 }
4732
4733 static void
4734 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4735 {
4736 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4737
4738         struct hns3_phy_params_bd0_cmd *req;
4739         uint32_t supported;
4740
4741         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4742         mac->link_speed = rte_le_to_cpu_32(req->speed);
4743         mac->link_duplex = hns3_get_bit(req->duplex,
4744                                            HNS3_PHY_DUPLEX_CFG_B);
4745         mac->link_autoneg = hns3_get_bit(req->autoneg,
4746                                            HNS3_PHY_AUTONEG_CFG_B);
4747         mac->advertising = rte_le_to_cpu_32(req->advertising);
4748         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4749         supported = rte_le_to_cpu_32(req->supported);
4750         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4751         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4752 }
4753
4754 static int
4755 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4756 {
4757         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4758         uint16_t i;
4759         int ret;
4760
4761         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4762                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4763                                           true);
4764                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4765         }
4766         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4767
4768         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4769         if (ret) {
4770                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4771                 return ret;
4772         }
4773
4774         hns3_parse_copper_phy_params(desc, mac);
4775
4776         return 0;
4777 }
4778
4779 static int
4780 hns3_update_copper_link_info(struct hns3_hw *hw)
4781 {
4782         struct hns3_mac *mac = &hw->mac;
4783         struct hns3_mac mac_info;
4784         int ret;
4785
4786         memset(&mac_info, 0, sizeof(struct hns3_mac));
4787         ret = hns3_get_copper_phy_params(hw, &mac_info);
4788         if (ret)
4789                 return ret;
4790
4791         if (mac_info.link_speed != mac->link_speed) {
4792                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4793                 if (ret)
4794                         return ret;
4795         }
4796
4797         mac->link_speed = mac_info.link_speed;
4798         mac->link_duplex = mac_info.link_duplex;
4799         mac->link_autoneg = mac_info.link_autoneg;
4800         mac->supported_speed = mac_info.supported_speed;
4801         mac->advertising = mac_info.advertising;
4802         mac->lp_advertising = mac_info.lp_advertising;
4803         mac->support_autoneg = mac_info.support_autoneg;
4804
4805         return 0;
4806 }
4807
4808 static int
4809 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4810 {
4811         struct hns3_adapter *hns = eth_dev->data->dev_private;
4812         struct hns3_hw *hw = &hns->hw;
4813         int ret = 0;
4814
4815         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4816                 ret = hns3_update_copper_link_info(hw);
4817         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4818                 ret = hns3_update_fiber_link_info(hw);
4819
4820         return ret;
4821 }
4822
4823 static int
4824 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4825 {
4826         struct hns3_config_mac_mode_cmd *req;
4827         struct hns3_cmd_desc desc;
4828         uint32_t loop_en = 0;
4829         uint8_t val = 0;
4830         int ret;
4831
4832         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4833
4834         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4835         if (enable)
4836                 val = 1;
4837         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4838         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4839         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4840         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4841         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4842         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4843         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4844         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4845         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4846         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4847
4848         /*
4849          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4850          * when receiving frames. Otherwise, CRC will be stripped.
4851          */
4852         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4853                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4854         else
4855                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4856         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4857         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4858         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4859         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4860
4861         ret = hns3_cmd_send(hw, &desc, 1);
4862         if (ret)
4863                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4864
4865         return ret;
4866 }
4867
4868 static int
4869 hns3_get_mac_link_status(struct hns3_hw *hw)
4870 {
4871         struct hns3_link_status_cmd *req;
4872         struct hns3_cmd_desc desc;
4873         int link_status;
4874         int ret;
4875
4876         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4877         ret = hns3_cmd_send(hw, &desc, 1);
4878         if (ret) {
4879                 hns3_err(hw, "get link status cmd failed %d", ret);
4880                 return ETH_LINK_DOWN;
4881         }
4882
4883         req = (struct hns3_link_status_cmd *)desc.data;
4884         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4885
4886         return !!link_status;
4887 }
4888
4889 static bool
4890 hns3_update_link_status(struct hns3_hw *hw)
4891 {
4892         int state;
4893
4894         state = hns3_get_mac_link_status(hw);
4895         if (state != hw->mac.link_status) {
4896                 hw->mac.link_status = state;
4897                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4898                 return true;
4899         }
4900
4901         return false;
4902 }
4903
4904 void
4905 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4906 {
4907         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4908         struct rte_eth_link new_link;
4909         int ret;
4910
4911         if (query)
4912                 hns3_update_port_link_info(dev);
4913
4914         memset(&new_link, 0, sizeof(new_link));
4915         hns3_setup_linkstatus(dev, &new_link);
4916
4917         ret = rte_eth_linkstatus_set(dev, &new_link);
4918         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4919                 hns3_start_report_lse(dev);
4920 }
4921
4922 static void
4923 hns3_service_handler(void *param)
4924 {
4925         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4926         struct hns3_adapter *hns = eth_dev->data->dev_private;
4927         struct hns3_hw *hw = &hns->hw;
4928
4929         if (!hns3_is_reset_pending(hns))
4930                 hns3_update_linkstatus_and_event(hw, true);
4931         else
4932                 hns3_warn(hw, "Cancel the query when reset is pending");
4933
4934         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4935 }
4936
4937 static int
4938 hns3_init_hardware(struct hns3_adapter *hns)
4939 {
4940         struct hns3_hw *hw = &hns->hw;
4941         int ret;
4942
4943         ret = hns3_map_tqp(hw);
4944         if (ret) {
4945                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4946                 return ret;
4947         }
4948
4949         ret = hns3_init_umv_space(hw);
4950         if (ret) {
4951                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4952                 return ret;
4953         }
4954
4955         ret = hns3_mac_init(hw);
4956         if (ret) {
4957                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4958                 goto err_mac_init;
4959         }
4960
4961         ret = hns3_init_mgr_tbl(hw);
4962         if (ret) {
4963                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4964                 goto err_mac_init;
4965         }
4966
4967         ret = hns3_promisc_init(hw);
4968         if (ret) {
4969                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4970                              ret);
4971                 goto err_mac_init;
4972         }
4973
4974         ret = hns3_init_vlan_config(hns);
4975         if (ret) {
4976                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4977                 goto err_mac_init;
4978         }
4979
4980         ret = hns3_dcb_init(hw);
4981         if (ret) {
4982                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4983                 goto err_mac_init;
4984         }
4985
4986         ret = hns3_init_fd_config(hns);
4987         if (ret) {
4988                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4989                 goto err_mac_init;
4990         }
4991
4992         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4993         if (ret) {
4994                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4995                 goto err_mac_init;
4996         }
4997
4998         ret = hns3_config_gro(hw, false);
4999         if (ret) {
5000                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5001                 goto err_mac_init;
5002         }
5003
5004         /*
5005          * In the initialization clearing the all hardware mapping relationship
5006          * configurations between queues and interrupt vectors is needed, so
5007          * some error caused by the residual configurations, such as the
5008          * unexpected interrupt, can be avoid.
5009          */
5010         ret = hns3_init_ring_with_vector(hw);
5011         if (ret) {
5012                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5013                 goto err_mac_init;
5014         }
5015
5016         return 0;
5017
5018 err_mac_init:
5019         hns3_uninit_umv_space(hw);
5020         return ret;
5021 }
5022
5023 static int
5024 hns3_clear_hw(struct hns3_hw *hw)
5025 {
5026         struct hns3_cmd_desc desc;
5027         int ret;
5028
5029         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5030
5031         ret = hns3_cmd_send(hw, &desc, 1);
5032         if (ret && ret != -EOPNOTSUPP)
5033                 return ret;
5034
5035         return 0;
5036 }
5037
5038 static void
5039 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5040 {
5041         uint32_t val;
5042
5043         /*
5044          * The new firmware support report more hardware error types by
5045          * msix mode. These errors are defined as RAS errors in hardware
5046          * and belong to a different type from the MSI-x errors processed
5047          * by the network driver.
5048          *
5049          * Network driver should open the new error report on initialization.
5050          */
5051         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5052         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5053         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5054 }
5055
5056 static uint32_t
5057 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5058 {
5059         struct hns3_mac *mac = &hw->mac;
5060
5061         switch (mac->link_speed) {
5062         case ETH_SPEED_NUM_1G:
5063                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5064         case ETH_SPEED_NUM_10G:
5065                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5066         case ETH_SPEED_NUM_25G:
5067                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5068         case ETH_SPEED_NUM_40G:
5069                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5070         case ETH_SPEED_NUM_50G:
5071                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5072         case ETH_SPEED_NUM_100G:
5073                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5074         case ETH_SPEED_NUM_200G:
5075                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5076         default:
5077                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5078                 return 0;
5079         }
5080 }
5081
5082 /*
5083  * Validity of supported_speed for firber and copper media type can be
5084  * guaranteed by the following policy:
5085  * Copper:
5086  *       Although the initialization of the phy in the firmware may not be
5087  *       completed, the firmware can guarantees that the supported_speed is
5088  *       an valid value.
5089  * Firber:
5090  *       If the version of firmware supports the acitive query way of the
5091  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5092  *       through it. If unsupported, use the SFP's speed as the value of the
5093  *       supported_speed.
5094  */
5095 static int
5096 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5097 {
5098         struct hns3_adapter *hns = eth_dev->data->dev_private;
5099         struct hns3_hw *hw = &hns->hw;
5100         struct hns3_mac *mac = &hw->mac;
5101         int ret;
5102
5103         ret = hns3_update_link_info(eth_dev);
5104         if (ret)
5105                 return ret;
5106
5107         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5108                 /*
5109                  * Some firmware does not support the report of supported_speed,
5110                  * and only report the effective speed of SFP. In this case, it
5111                  * is necessary to use the SFP's speed as the supported_speed.
5112                  */
5113                 if (mac->supported_speed == 0)
5114                         mac->supported_speed =
5115                                 hns3_set_firber_default_support_speed(hw);
5116         }
5117
5118         return 0;
5119 }
5120
5121 static void
5122 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5123 {
5124         struct hns3_mac *mac = &hns->hw.mac;
5125
5126         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5127                 hns->pf.support_fc_autoneg = true;
5128                 return;
5129         }
5130
5131         /*
5132          * Flow control auto-negotiation requires the cooperation of the driver
5133          * and firmware. Currently, the optical port does not support flow
5134          * control auto-negotiation.
5135          */
5136         hns->pf.support_fc_autoneg = false;
5137 }
5138
5139 static int
5140 hns3_init_pf(struct rte_eth_dev *eth_dev)
5141 {
5142         struct rte_device *dev = eth_dev->device;
5143         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5144         struct hns3_adapter *hns = eth_dev->data->dev_private;
5145         struct hns3_hw *hw = &hns->hw;
5146         int ret;
5147
5148         PMD_INIT_FUNC_TRACE();
5149
5150         /* Get hardware io base address from pcie BAR2 IO space */
5151         hw->io_base = pci_dev->mem_resource[2].addr;
5152
5153         /* Firmware command queue initialize */
5154         ret = hns3_cmd_init_queue(hw);
5155         if (ret) {
5156                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5157                 goto err_cmd_init_queue;
5158         }
5159
5160         hns3_clear_all_event_cause(hw);
5161
5162         /* Firmware command initialize */
5163         ret = hns3_cmd_init(hw);
5164         if (ret) {
5165                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5166                 goto err_cmd_init;
5167         }
5168
5169         /*
5170          * To ensure that the hardware environment is clean during
5171          * initialization, the driver actively clear the hardware environment
5172          * during initialization, including PF and corresponding VFs' vlan, mac,
5173          * flow table configurations, etc.
5174          */
5175         ret = hns3_clear_hw(hw);
5176         if (ret) {
5177                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5178                 goto err_cmd_init;
5179         }
5180
5181         /* Hardware statistics of imissed registers cleared. */
5182         ret = hns3_update_imissed_stats(hw, true);
5183         if (ret) {
5184                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5185                 goto err_cmd_init;
5186         }
5187
5188         hns3_config_all_msix_error(hw, true);
5189
5190         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5191                                          hns3_interrupt_handler,
5192                                          eth_dev);
5193         if (ret) {
5194                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5195                 goto err_intr_callback_register;
5196         }
5197
5198         ret = hns3_ptp_init(hw);
5199         if (ret)
5200                 goto err_get_config;
5201
5202         /* Enable interrupt */
5203         rte_intr_enable(&pci_dev->intr_handle);
5204         hns3_pf_enable_irq0(hw);
5205
5206         /* Get configuration */
5207         ret = hns3_get_configuration(hw);
5208         if (ret) {
5209                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5210                 goto err_get_config;
5211         }
5212
5213         ret = hns3_tqp_stats_init(hw);
5214         if (ret)
5215                 goto err_get_config;
5216
5217         ret = hns3_init_hardware(hns);
5218         if (ret) {
5219                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5220                 goto err_init_hw;
5221         }
5222
5223         /* Initialize flow director filter list & hash */
5224         ret = hns3_fdir_filter_init(hns);
5225         if (ret) {
5226                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5227                 goto err_fdir;
5228         }
5229
5230         hns3_rss_set_default_args(hw);
5231
5232         ret = hns3_enable_hw_error_intr(hns, true);
5233         if (ret) {
5234                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5235                              ret);
5236                 goto err_enable_intr;
5237         }
5238
5239         ret = hns3_get_port_supported_speed(eth_dev);
5240         if (ret) {
5241                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5242                              "by device, ret = %d.", ret);
5243                 goto err_supported_speed;
5244         }
5245
5246         hns3_get_fc_autoneg_capability(hns);
5247
5248         hns3_tm_conf_init(eth_dev);
5249
5250         return 0;
5251
5252 err_supported_speed:
5253         (void)hns3_enable_hw_error_intr(hns, false);
5254 err_enable_intr:
5255         hns3_fdir_filter_uninit(hns);
5256 err_fdir:
5257         hns3_uninit_umv_space(hw);
5258 err_init_hw:
5259         hns3_tqp_stats_uninit(hw);
5260 err_get_config:
5261         hns3_pf_disable_irq0(hw);
5262         rte_intr_disable(&pci_dev->intr_handle);
5263         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5264                              eth_dev);
5265 err_intr_callback_register:
5266 err_cmd_init:
5267         hns3_cmd_uninit(hw);
5268         hns3_cmd_destroy_queue(hw);
5269 err_cmd_init_queue:
5270         hw->io_base = NULL;
5271
5272         return ret;
5273 }
5274
5275 static void
5276 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5277 {
5278         struct hns3_adapter *hns = eth_dev->data->dev_private;
5279         struct rte_device *dev = eth_dev->device;
5280         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5281         struct hns3_hw *hw = &hns->hw;
5282
5283         PMD_INIT_FUNC_TRACE();
5284
5285         hns3_tm_conf_uninit(eth_dev);
5286         hns3_enable_hw_error_intr(hns, false);
5287         hns3_rss_uninit(hns);
5288         (void)hns3_config_gro(hw, false);
5289         hns3_promisc_uninit(hw);
5290         hns3_fdir_filter_uninit(hns);
5291         hns3_uninit_umv_space(hw);
5292         hns3_tqp_stats_uninit(hw);
5293         hns3_config_mac_tnl_int(hw, false);
5294         hns3_pf_disable_irq0(hw);
5295         rte_intr_disable(&pci_dev->intr_handle);
5296         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5297                              eth_dev);
5298         hns3_config_all_msix_error(hw, false);
5299         hns3_cmd_uninit(hw);
5300         hns3_cmd_destroy_queue(hw);
5301         hw->io_base = NULL;
5302 }
5303
5304 static uint32_t
5305 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5306 {
5307         uint32_t speed_bit;
5308
5309         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5310         case ETH_LINK_SPEED_10M:
5311                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5312                 break;
5313         case ETH_LINK_SPEED_10M_HD:
5314                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5315                 break;
5316         case ETH_LINK_SPEED_100M:
5317                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5318                 break;
5319         case ETH_LINK_SPEED_100M_HD:
5320                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5321                 break;
5322         case ETH_LINK_SPEED_1G:
5323                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5324                 break;
5325         default:
5326                 speed_bit = 0;
5327                 break;
5328         }
5329
5330         return speed_bit;
5331 }
5332
5333 static uint32_t
5334 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5335 {
5336         uint32_t speed_bit;
5337
5338         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5339         case ETH_LINK_SPEED_1G:
5340                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5341                 break;
5342         case ETH_LINK_SPEED_10G:
5343                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5344                 break;
5345         case ETH_LINK_SPEED_25G:
5346                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5347                 break;
5348         case ETH_LINK_SPEED_40G:
5349                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5350                 break;
5351         case ETH_LINK_SPEED_50G:
5352                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5353                 break;
5354         case ETH_LINK_SPEED_100G:
5355                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5356                 break;
5357         case ETH_LINK_SPEED_200G:
5358                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5359                 break;
5360         default:
5361                 speed_bit = 0;
5362                 break;
5363         }
5364
5365         return speed_bit;
5366 }
5367
5368 static int
5369 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5370 {
5371         struct hns3_mac *mac = &hw->mac;
5372         uint32_t supported_speed = mac->supported_speed;
5373         uint32_t speed_bit = 0;
5374
5375         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5376                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5377         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5378                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5379
5380         if (!(speed_bit & supported_speed)) {
5381                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5382                          link_speeds);
5383                 return -EINVAL;
5384         }
5385
5386         return 0;
5387 }
5388
5389 static inline uint32_t
5390 hns3_get_link_speed(uint32_t link_speeds)
5391 {
5392         uint32_t speed = ETH_SPEED_NUM_NONE;
5393
5394         if (link_speeds & ETH_LINK_SPEED_10M ||
5395             link_speeds & ETH_LINK_SPEED_10M_HD)
5396                 speed = ETH_SPEED_NUM_10M;
5397         if (link_speeds & ETH_LINK_SPEED_100M ||
5398             link_speeds & ETH_LINK_SPEED_100M_HD)
5399                 speed = ETH_SPEED_NUM_100M;
5400         if (link_speeds & ETH_LINK_SPEED_1G)
5401                 speed = ETH_SPEED_NUM_1G;
5402         if (link_speeds & ETH_LINK_SPEED_10G)
5403                 speed = ETH_SPEED_NUM_10G;
5404         if (link_speeds & ETH_LINK_SPEED_25G)
5405                 speed = ETH_SPEED_NUM_25G;
5406         if (link_speeds & ETH_LINK_SPEED_40G)
5407                 speed = ETH_SPEED_NUM_40G;
5408         if (link_speeds & ETH_LINK_SPEED_50G)
5409                 speed = ETH_SPEED_NUM_50G;
5410         if (link_speeds & ETH_LINK_SPEED_100G)
5411                 speed = ETH_SPEED_NUM_100G;
5412         if (link_speeds & ETH_LINK_SPEED_200G)
5413                 speed = ETH_SPEED_NUM_200G;
5414
5415         return speed;
5416 }
5417
5418 static uint8_t
5419 hns3_get_link_duplex(uint32_t link_speeds)
5420 {
5421         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5422             (link_speeds & ETH_LINK_SPEED_100M_HD))
5423                 return ETH_LINK_HALF_DUPLEX;
5424         else
5425                 return ETH_LINK_FULL_DUPLEX;
5426 }
5427
5428 static int
5429 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5430                                 struct hns3_set_link_speed_cfg *cfg)
5431 {
5432         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5433         struct hns3_phy_params_bd0_cmd *req;
5434         uint16_t i;
5435
5436         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5437                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5438                                           false);
5439                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5440         }
5441         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5442         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5443         req->autoneg = cfg->autoneg;
5444
5445         /*
5446          * The full speed capability is used to negotiate when
5447          * auto-negotiation is enabled.
5448          */
5449         if (cfg->autoneg) {
5450                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5451                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5452                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5453                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5454                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5455         } else {
5456                 req->speed = cfg->speed;
5457                 req->duplex = cfg->duplex;
5458         }
5459
5460         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5461 }
5462
5463 static int
5464 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5465 {
5466         struct hns3_config_auto_neg_cmd *req;
5467         struct hns3_cmd_desc desc;
5468         uint32_t flag = 0;
5469         int ret;
5470
5471         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5472
5473         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5474         if (enable)
5475                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5476         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5477
5478         ret = hns3_cmd_send(hw, &desc, 1);
5479         if (ret)
5480                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5481
5482         return ret;
5483 }
5484
5485 static int
5486 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5487                                struct hns3_set_link_speed_cfg *cfg)
5488 {
5489         int ret;
5490
5491         if (hw->mac.support_autoneg) {
5492                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5493                 if (ret) {
5494                         hns3_err(hw, "failed to configure auto-negotiation.");
5495                         return ret;
5496                 }
5497
5498                 /*
5499                  * To enable auto-negotiation, we only need to open the switch
5500                  * of auto-negotiation, then firmware sets all speed
5501                  * capabilities.
5502                  */
5503                 if (cfg->autoneg)
5504                         return 0;
5505         }
5506
5507         /*
5508          * Some hardware doesn't support auto-negotiation, but users may not
5509          * configure link_speeds (default 0), which means auto-negotiation.
5510          * In this case, it should return success.
5511          */
5512         if (cfg->autoneg)
5513                 return 0;
5514
5515         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5516 }
5517
5518 static int
5519 hns3_set_port_link_speed(struct hns3_hw *hw,
5520                          struct hns3_set_link_speed_cfg *cfg)
5521 {
5522         int ret;
5523
5524         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5525 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5526                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5527                 if (pf->is_tmp_phy)
5528                         return 0;
5529 #endif
5530
5531                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5532                 if (ret) {
5533                         hns3_err(hw, "failed to set copper port link speed,"
5534                                  "ret = %d.", ret);
5535                         return ret;
5536                 }
5537         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5538                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5539                 if (ret) {
5540                         hns3_err(hw, "failed to set fiber port link speed,"
5541                                  "ret = %d.", ret);
5542                         return ret;
5543                 }
5544         }
5545
5546         return 0;
5547 }
5548
5549 static int
5550 hns3_apply_link_speed(struct hns3_hw *hw)
5551 {
5552         struct rte_eth_conf *conf = &hw->data->dev_conf;
5553         struct hns3_set_link_speed_cfg cfg;
5554
5555         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5556         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5557                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5558         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5559                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5560                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5561         }
5562
5563         return hns3_set_port_link_speed(hw, &cfg);
5564 }
5565
5566 static int
5567 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5568 {
5569         struct hns3_hw *hw = &hns->hw;
5570         int ret;
5571
5572         ret = hns3_dcb_cfg_update(hns);
5573         if (ret)
5574                 return ret;
5575
5576         /*
5577          * The hns3_dcb_cfg_update may configure TM module, so
5578          * hns3_tm_conf_update must called later.
5579          */
5580         ret = hns3_tm_conf_update(hw);
5581         if (ret) {
5582                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5583                 return ret;
5584         }
5585
5586         hns3_enable_rxd_adv_layout(hw);
5587
5588         ret = hns3_init_queues(hns, reset_queue);
5589         if (ret) {
5590                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5591                 return ret;
5592         }
5593
5594         ret = hns3_cfg_mac_mode(hw, true);
5595         if (ret) {
5596                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5597                 goto err_config_mac_mode;
5598         }
5599
5600         ret = hns3_apply_link_speed(hw);
5601         if (ret)
5602                 goto err_config_mac_mode;
5603
5604         return 0;
5605
5606 err_config_mac_mode:
5607         (void)hns3_cfg_mac_mode(hw, false);
5608         hns3_dev_release_mbufs(hns);
5609         /*
5610          * Here is exception handling, hns3_reset_all_tqps will have the
5611          * corresponding error message if it is handled incorrectly, so it is
5612          * not necessary to check hns3_reset_all_tqps return value, here keep
5613          * ret as the error code causing the exception.
5614          */
5615         (void)hns3_reset_all_tqps(hns);
5616         return ret;
5617 }
5618
5619 static int
5620 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5621 {
5622         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5623         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5624         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5626         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5627         uint32_t intr_vector;
5628         uint16_t q_id;
5629         int ret;
5630
5631         /*
5632          * hns3 needs a separate interrupt to be used as event interrupt which
5633          * could not be shared with task queue pair, so KERNEL drivers need
5634          * support multiple interrupt vectors.
5635          */
5636         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5637             !rte_intr_cap_multiple(intr_handle))
5638                 return 0;
5639
5640         rte_intr_disable(intr_handle);
5641         intr_vector = hw->used_rx_queues;
5642         /* creates event fd for each intr vector when MSIX is used */
5643         if (rte_intr_efd_enable(intr_handle, intr_vector))
5644                 return -EINVAL;
5645
5646         if (intr_handle->intr_vec == NULL) {
5647                 intr_handle->intr_vec =
5648                         rte_zmalloc("intr_vec",
5649                                     hw->used_rx_queues * sizeof(int), 0);
5650                 if (intr_handle->intr_vec == NULL) {
5651                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5652                                         hw->used_rx_queues);
5653                         ret = -ENOMEM;
5654                         goto alloc_intr_vec_error;
5655                 }
5656         }
5657
5658         if (rte_intr_allow_others(intr_handle)) {
5659                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5660                 base = RTE_INTR_VEC_RXTX_OFFSET;
5661         }
5662
5663         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5664                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5665                                                  HNS3_RING_TYPE_RX, q_id);
5666                 if (ret)
5667                         goto bind_vector_error;
5668                 intr_handle->intr_vec[q_id] = vec;
5669                 /*
5670                  * If there are not enough efds (e.g. not enough interrupt),
5671                  * remaining queues will be bond to the last interrupt.
5672                  */
5673                 if (vec < base + intr_handle->nb_efd - 1)
5674                         vec++;
5675         }
5676         rte_intr_enable(intr_handle);
5677         return 0;
5678
5679 bind_vector_error:
5680         rte_free(intr_handle->intr_vec);
5681         intr_handle->intr_vec = NULL;
5682 alloc_intr_vec_error:
5683         rte_intr_efd_disable(intr_handle);
5684         return ret;
5685 }
5686
5687 static int
5688 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5689 {
5690         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5691         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5692         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5693         uint16_t q_id;
5694         int ret;
5695
5696         if (dev->data->dev_conf.intr_conf.rxq == 0)
5697                 return 0;
5698
5699         if (rte_intr_dp_is_en(intr_handle)) {
5700                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5701                         ret = hns3_bind_ring_with_vector(hw,
5702                                         intr_handle->intr_vec[q_id], true,
5703                                         HNS3_RING_TYPE_RX, q_id);
5704                         if (ret)
5705                                 return ret;
5706                 }
5707         }
5708
5709         return 0;
5710 }
5711
5712 static void
5713 hns3_restore_filter(struct rte_eth_dev *dev)
5714 {
5715         hns3_restore_rss_filter(dev);
5716 }
5717
5718 static int
5719 hns3_dev_start(struct rte_eth_dev *dev)
5720 {
5721         struct hns3_adapter *hns = dev->data->dev_private;
5722         struct hns3_hw *hw = &hns->hw;
5723         int ret;
5724
5725         PMD_INIT_FUNC_TRACE();
5726         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5727                 return -EBUSY;
5728
5729         rte_spinlock_lock(&hw->lock);
5730         hw->adapter_state = HNS3_NIC_STARTING;
5731
5732         ret = hns3_do_start(hns, true);
5733         if (ret) {
5734                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5735                 rte_spinlock_unlock(&hw->lock);
5736                 return ret;
5737         }
5738         ret = hns3_map_rx_interrupt(dev);
5739         if (ret)
5740                 goto map_rx_inter_err;
5741
5742         /*
5743          * There are three register used to control the status of a TQP
5744          * (contains a pair of Tx queue and Rx queue) in the new version network
5745          * engine. One is used to control the enabling of Tx queue, the other is
5746          * used to control the enabling of Rx queue, and the last is the master
5747          * switch used to control the enabling of the tqp. The Tx register and
5748          * TQP register must be enabled at the same time to enable a Tx queue.
5749          * The same applies to the Rx queue. For the older network engine, this
5750          * function only refresh the enabled flag, and it is used to update the
5751          * status of queue in the dpdk framework.
5752          */
5753         ret = hns3_start_all_txqs(dev);
5754         if (ret)
5755                 goto map_rx_inter_err;
5756
5757         ret = hns3_start_all_rxqs(dev);
5758         if (ret)
5759                 goto start_all_rxqs_fail;
5760
5761         hw->adapter_state = HNS3_NIC_STARTED;
5762         rte_spinlock_unlock(&hw->lock);
5763
5764         hns3_rx_scattered_calc(dev);
5765         hns3_set_rxtx_function(dev);
5766         hns3_mp_req_start_rxtx(dev);
5767
5768         hns3_restore_filter(dev);
5769
5770         /* Enable interrupt of all rx queues before enabling queues */
5771         hns3_dev_all_rx_queue_intr_enable(hw, true);
5772
5773         /*
5774          * After finished the initialization, enable tqps to receive/transmit
5775          * packets and refresh all queue status.
5776          */
5777         hns3_start_tqps(hw);
5778
5779         hns3_tm_dev_start_proc(hw);
5780
5781         if (dev->data->dev_conf.intr_conf.lsc != 0)
5782                 hns3_dev_link_update(dev, 0);
5783         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5784
5785         hns3_info(hw, "hns3 dev start successful!");
5786
5787         return 0;
5788
5789 start_all_rxqs_fail:
5790         hns3_stop_all_txqs(dev);
5791 map_rx_inter_err:
5792         (void)hns3_do_stop(hns);
5793         hw->adapter_state = HNS3_NIC_CONFIGURED;
5794         rte_spinlock_unlock(&hw->lock);
5795
5796         return ret;
5797 }
5798
5799 static int
5800 hns3_do_stop(struct hns3_adapter *hns)
5801 {
5802         struct hns3_hw *hw = &hns->hw;
5803         int ret;
5804
5805         /*
5806          * The "hns3_do_stop" function will also be called by .stop_service to
5807          * prepare reset. At the time of global or IMP reset, the command cannot
5808          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5809          * accessed during the reset process. So the mbuf can not be released
5810          * during reset and is required to be released after the reset is
5811          * completed.
5812          */
5813         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5814                 hns3_dev_release_mbufs(hns);
5815
5816         ret = hns3_cfg_mac_mode(hw, false);
5817         if (ret)
5818                 return ret;
5819         hw->mac.link_status = ETH_LINK_DOWN;
5820
5821         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5822                 hns3_configure_all_mac_addr(hns, true);
5823                 ret = hns3_reset_all_tqps(hns);
5824                 if (ret) {
5825                         hns3_err(hw, "failed to reset all queues ret = %d.",
5826                                  ret);
5827                         return ret;
5828                 }
5829         }
5830         hw->mac.default_addr_setted = false;
5831         return 0;
5832 }
5833
5834 static void
5835 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5836 {
5837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5839         struct hns3_adapter *hns = dev->data->dev_private;
5840         struct hns3_hw *hw = &hns->hw;
5841         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5842         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5843         uint16_t q_id;
5844
5845         if (dev->data->dev_conf.intr_conf.rxq == 0)
5846                 return;
5847
5848         /* unmap the ring with vector */
5849         if (rte_intr_allow_others(intr_handle)) {
5850                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5851                 base = RTE_INTR_VEC_RXTX_OFFSET;
5852         }
5853         if (rte_intr_dp_is_en(intr_handle)) {
5854                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5855                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5856                                                          HNS3_RING_TYPE_RX,
5857                                                          q_id);
5858                         if (vec < base + intr_handle->nb_efd - 1)
5859                                 vec++;
5860                 }
5861         }
5862         /* Clean datapath event and queue/vec mapping */
5863         rte_intr_efd_disable(intr_handle);
5864         if (intr_handle->intr_vec) {
5865                 rte_free(intr_handle->intr_vec);
5866                 intr_handle->intr_vec = NULL;
5867         }
5868 }
5869
5870 static int
5871 hns3_dev_stop(struct rte_eth_dev *dev)
5872 {
5873         struct hns3_adapter *hns = dev->data->dev_private;
5874         struct hns3_hw *hw = &hns->hw;
5875
5876         PMD_INIT_FUNC_TRACE();
5877         dev->data->dev_started = 0;
5878
5879         hw->adapter_state = HNS3_NIC_STOPPING;
5880         hns3_set_rxtx_function(dev);
5881         rte_wmb();
5882         /* Disable datapath on secondary process. */
5883         hns3_mp_req_stop_rxtx(dev);
5884         /* Prevent crashes when queues are still in use. */
5885         rte_delay_ms(hw->tqps_num);
5886
5887         rte_spinlock_lock(&hw->lock);
5888         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5889                 hns3_tm_dev_stop_proc(hw);
5890                 hns3_config_mac_tnl_int(hw, false);
5891                 hns3_stop_tqps(hw);
5892                 hns3_do_stop(hns);
5893                 hns3_unmap_rx_interrupt(dev);
5894                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5895         }
5896         hns3_rx_scattered_reset(dev);
5897         rte_eal_alarm_cancel(hns3_service_handler, dev);
5898         hns3_stop_report_lse(dev);
5899         rte_spinlock_unlock(&hw->lock);
5900
5901         return 0;
5902 }
5903
5904 static int
5905 hns3_dev_close(struct rte_eth_dev *eth_dev)
5906 {
5907         struct hns3_adapter *hns = eth_dev->data->dev_private;
5908         struct hns3_hw *hw = &hns->hw;
5909         int ret = 0;
5910
5911         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5912                 rte_free(eth_dev->process_private);
5913                 eth_dev->process_private = NULL;
5914                 return 0;
5915         }
5916
5917         if (hw->adapter_state == HNS3_NIC_STARTED)
5918                 ret = hns3_dev_stop(eth_dev);
5919
5920         hw->adapter_state = HNS3_NIC_CLOSING;
5921         hns3_reset_abort(hns);
5922         hw->adapter_state = HNS3_NIC_CLOSED;
5923
5924         hns3_configure_all_mc_mac_addr(hns, true);
5925         hns3_remove_all_vlan_table(hns);
5926         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5927         hns3_uninit_pf(eth_dev);
5928         hns3_free_all_queues(eth_dev);
5929         rte_free(hw->reset.wait_data);
5930         rte_free(eth_dev->process_private);
5931         eth_dev->process_private = NULL;
5932         hns3_mp_uninit_primary();
5933         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5934
5935         return ret;
5936 }
5937
5938 static void
5939 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5940                                    bool *tx_pause)
5941 {
5942         struct hns3_mac *mac = &hw->mac;
5943         uint32_t advertising = mac->advertising;
5944         uint32_t lp_advertising = mac->lp_advertising;
5945         *rx_pause = false;
5946         *tx_pause = false;
5947
5948         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5949                 *rx_pause = true;
5950                 *tx_pause = true;
5951         } else if (advertising & lp_advertising &
5952                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5953                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5954                         *rx_pause = true;
5955                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5956                         *tx_pause = true;
5957         }
5958 }
5959
5960 static enum hns3_fc_mode
5961 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5962 {
5963         enum hns3_fc_mode current_mode;
5964         bool rx_pause = false;
5965         bool tx_pause = false;
5966
5967         switch (hw->mac.media_type) {
5968         case HNS3_MEDIA_TYPE_COPPER:
5969                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5970                 break;
5971
5972         /*
5973          * Flow control auto-negotiation is not supported for fiber and
5974          * backpalne media type.
5975          */
5976         case HNS3_MEDIA_TYPE_FIBER:
5977         case HNS3_MEDIA_TYPE_BACKPLANE:
5978                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5979                 current_mode = hw->requested_fc_mode;
5980                 goto out;
5981         default:
5982                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5983                          hw->mac.media_type);
5984                 current_mode = HNS3_FC_NONE;
5985                 goto out;
5986         }
5987
5988         if (rx_pause && tx_pause)
5989                 current_mode = HNS3_FC_FULL;
5990         else if (rx_pause)
5991                 current_mode = HNS3_FC_RX_PAUSE;
5992         else if (tx_pause)
5993                 current_mode = HNS3_FC_TX_PAUSE;
5994         else
5995                 current_mode = HNS3_FC_NONE;
5996
5997 out:
5998         return current_mode;
5999 }
6000
6001 static enum hns3_fc_mode
6002 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6003 {
6004         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6006         struct hns3_mac *mac = &hw->mac;
6007
6008         /*
6009          * When the flow control mode is obtained, the device may not complete
6010          * auto-negotiation. It is necessary to wait for link establishment.
6011          */
6012         (void)hns3_dev_link_update(dev, 1);
6013
6014         /*
6015          * If the link auto-negotiation of the nic is disabled, or the flow
6016          * control auto-negotiation is not supported, the forced flow control
6017          * mode is used.
6018          */
6019         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6020                 return hw->requested_fc_mode;
6021
6022         return hns3_get_autoneg_fc_mode(hw);
6023 }
6024
6025 static int
6026 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6027 {
6028         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6029         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6030         enum hns3_fc_mode current_mode;
6031
6032         current_mode = hns3_get_current_fc_mode(dev);
6033         switch (current_mode) {
6034         case HNS3_FC_FULL:
6035                 fc_conf->mode = RTE_FC_FULL;
6036                 break;
6037         case HNS3_FC_TX_PAUSE:
6038                 fc_conf->mode = RTE_FC_TX_PAUSE;
6039                 break;
6040         case HNS3_FC_RX_PAUSE:
6041                 fc_conf->mode = RTE_FC_RX_PAUSE;
6042                 break;
6043         case HNS3_FC_NONE:
6044         default:
6045                 fc_conf->mode = RTE_FC_NONE;
6046                 break;
6047         }
6048
6049         fc_conf->pause_time = pf->pause_time;
6050         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6051
6052         return 0;
6053 }
6054
6055 static void
6056 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6057 {
6058         switch (mode) {
6059         case RTE_FC_NONE:
6060                 hw->requested_fc_mode = HNS3_FC_NONE;
6061                 break;
6062         case RTE_FC_RX_PAUSE:
6063                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6064                 break;
6065         case RTE_FC_TX_PAUSE:
6066                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6067                 break;
6068         case RTE_FC_FULL:
6069                 hw->requested_fc_mode = HNS3_FC_FULL;
6070                 break;
6071         default:
6072                 hw->requested_fc_mode = HNS3_FC_NONE;
6073                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6074                           "configured to RTE_FC_NONE", mode);
6075                 break;
6076         }
6077 }
6078
6079 static int
6080 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6081 {
6082         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6083
6084         if (!pf->support_fc_autoneg) {
6085                 if (autoneg != 0) {
6086                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6087                         return -EOPNOTSUPP;
6088                 }
6089
6090                 /*
6091                  * Flow control auto-negotiation of the NIC is not supported,
6092                  * but other auto-negotiation features may be supported.
6093                  */
6094                 if (autoneg != hw->mac.link_autoneg) {
6095                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6096                         return -EOPNOTSUPP;
6097                 }
6098
6099                 return 0;
6100         }
6101
6102         /*
6103          * If flow control auto-negotiation of the NIC is supported, all
6104          * auto-negotiation features are supported.
6105          */
6106         if (autoneg != hw->mac.link_autoneg) {
6107                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6108                 return -EOPNOTSUPP;
6109         }
6110
6111         return 0;
6112 }
6113
6114 static int
6115 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6116 {
6117         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6118         int ret;
6119
6120         if (fc_conf->high_water || fc_conf->low_water ||
6121             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6122                 hns3_err(hw, "Unsupported flow control settings specified, "
6123                          "high_water(%u), low_water(%u), send_xon(%u) and "
6124                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6125                          fc_conf->high_water, fc_conf->low_water,
6126                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6127                 return -EINVAL;
6128         }
6129
6130         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6131         if (ret)
6132                 return ret;
6133
6134         if (!fc_conf->pause_time) {
6135                 hns3_err(hw, "Invalid pause time %u setting.",
6136                          fc_conf->pause_time);
6137                 return -EINVAL;
6138         }
6139
6140         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6141             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6142                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6143                          "current_fc_status = %d", hw->current_fc_status);
6144                 return -EOPNOTSUPP;
6145         }
6146
6147         if (hw->num_tc > 1) {
6148                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6149                 return -EOPNOTSUPP;
6150         }
6151
6152         hns3_get_fc_mode(hw, fc_conf->mode);
6153
6154         rte_spinlock_lock(&hw->lock);
6155         ret = hns3_fc_enable(dev, fc_conf);
6156         rte_spinlock_unlock(&hw->lock);
6157
6158         return ret;
6159 }
6160
6161 static int
6162 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6163                             struct rte_eth_pfc_conf *pfc_conf)
6164 {
6165         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         int ret;
6167
6168         if (!hns3_dev_dcb_supported(hw)) {
6169                 hns3_err(hw, "This port does not support dcb configurations.");
6170                 return -EOPNOTSUPP;
6171         }
6172
6173         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6174             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6175                 hns3_err(hw, "Unsupported flow control settings specified, "
6176                          "high_water(%u), low_water(%u), send_xon(%u) and "
6177                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6178                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6179                          pfc_conf->fc.send_xon,
6180                          pfc_conf->fc.mac_ctrl_frame_fwd);
6181                 return -EINVAL;
6182         }
6183         if (pfc_conf->fc.autoneg) {
6184                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6185                 return -EINVAL;
6186         }
6187         if (pfc_conf->fc.pause_time == 0) {
6188                 hns3_err(hw, "Invalid pause time %u setting.",
6189                          pfc_conf->fc.pause_time);
6190                 return -EINVAL;
6191         }
6192
6193         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6194             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6195                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6196                              "current_fc_status = %d", hw->current_fc_status);
6197                 return -EOPNOTSUPP;
6198         }
6199
6200         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6201
6202         rte_spinlock_lock(&hw->lock);
6203         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6204         rte_spinlock_unlock(&hw->lock);
6205
6206         return ret;
6207 }
6208
6209 static int
6210 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6211 {
6212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6213         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6214         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6215         int i;
6216
6217         rte_spinlock_lock(&hw->lock);
6218         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6219                 dcb_info->nb_tcs = pf->local_max_tc;
6220         else
6221                 dcb_info->nb_tcs = 1;
6222
6223         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6224                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6225         for (i = 0; i < dcb_info->nb_tcs; i++)
6226                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6227
6228         for (i = 0; i < hw->num_tc; i++) {
6229                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6230                 dcb_info->tc_queue.tc_txq[0][i].base =
6231                                                 hw->tc_queue[i].tqp_offset;
6232                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6233                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6234                                                 hw->tc_queue[i].tqp_count;
6235         }
6236         rte_spinlock_unlock(&hw->lock);
6237
6238         return 0;
6239 }
6240
6241 static int
6242 hns3_reinit_dev(struct hns3_adapter *hns)
6243 {
6244         struct hns3_hw *hw = &hns->hw;
6245         int ret;
6246
6247         ret = hns3_cmd_init(hw);
6248         if (ret) {
6249                 hns3_err(hw, "Failed to init cmd: %d", ret);
6250                 return ret;
6251         }
6252
6253         ret = hns3_reset_all_tqps(hns);
6254         if (ret) {
6255                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6256                 return ret;
6257         }
6258
6259         ret = hns3_init_hardware(hns);
6260         if (ret) {
6261                 hns3_err(hw, "Failed to init hardware: %d", ret);
6262                 return ret;
6263         }
6264
6265         ret = hns3_enable_hw_error_intr(hns, true);
6266         if (ret) {
6267                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6268                              ret);
6269                 return ret;
6270         }
6271         hns3_info(hw, "Reset done, driver initialization finished.");
6272
6273         return 0;
6274 }
6275
6276 static bool
6277 is_pf_reset_done(struct hns3_hw *hw)
6278 {
6279         uint32_t val, reg, reg_bit;
6280
6281         switch (hw->reset.level) {
6282         case HNS3_IMP_RESET:
6283                 reg = HNS3_GLOBAL_RESET_REG;
6284                 reg_bit = HNS3_IMP_RESET_BIT;
6285                 break;
6286         case HNS3_GLOBAL_RESET:
6287                 reg = HNS3_GLOBAL_RESET_REG;
6288                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6289                 break;
6290         case HNS3_FUNC_RESET:
6291                 reg = HNS3_FUN_RST_ING;
6292                 reg_bit = HNS3_FUN_RST_ING_B;
6293                 break;
6294         case HNS3_FLR_RESET:
6295         default:
6296                 hns3_err(hw, "Wait for unsupported reset level: %d",
6297                          hw->reset.level);
6298                 return true;
6299         }
6300         val = hns3_read_dev(hw, reg);
6301         if (hns3_get_bit(val, reg_bit))
6302                 return false;
6303         else
6304                 return true;
6305 }
6306
6307 bool
6308 hns3_is_reset_pending(struct hns3_adapter *hns)
6309 {
6310         struct hns3_hw *hw = &hns->hw;
6311         enum hns3_reset_level reset;
6312
6313         hns3_check_event_cause(hns, NULL);
6314         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6315
6316         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6317             hw->reset.level < reset) {
6318                 hns3_warn(hw, "High level reset %d is pending", reset);
6319                 return true;
6320         }
6321         reset = hns3_get_reset_level(hns, &hw->reset.request);
6322         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6323             hw->reset.level < reset) {
6324                 hns3_warn(hw, "High level reset %d is request", reset);
6325                 return true;
6326         }
6327         return false;
6328 }
6329
6330 static int
6331 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6332 {
6333         struct hns3_hw *hw = &hns->hw;
6334         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6335         struct timeval tv;
6336
6337         if (wait_data->result == HNS3_WAIT_SUCCESS)
6338                 return 0;
6339         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6340                 gettimeofday(&tv, NULL);
6341                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6342                           tv.tv_sec, tv.tv_usec);
6343                 return -ETIME;
6344         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6345                 return -EAGAIN;
6346
6347         wait_data->hns = hns;
6348         wait_data->check_completion = is_pf_reset_done;
6349         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6350                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6351         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6352         wait_data->count = HNS3_RESET_WAIT_CNT;
6353         wait_data->result = HNS3_WAIT_REQUEST;
6354         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6355         return -EAGAIN;
6356 }
6357
6358 static int
6359 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6360 {
6361         struct hns3_cmd_desc desc;
6362         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6363
6364         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6365         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6366         req->fun_reset_vfid = func_id;
6367
6368         return hns3_cmd_send(hw, &desc, 1);
6369 }
6370
6371 static int
6372 hns3_imp_reset_cmd(struct hns3_hw *hw)
6373 {
6374         struct hns3_cmd_desc desc;
6375
6376         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6377         desc.data[0] = 0xeedd;
6378
6379         return hns3_cmd_send(hw, &desc, 1);
6380 }
6381
6382 static void
6383 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6384 {
6385         struct hns3_hw *hw = &hns->hw;
6386         struct timeval tv;
6387         uint32_t val;
6388
6389         gettimeofday(&tv, NULL);
6390         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6391             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6392                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6393                           tv.tv_sec, tv.tv_usec);
6394                 return;
6395         }
6396
6397         switch (reset_level) {
6398         case HNS3_IMP_RESET:
6399                 hns3_imp_reset_cmd(hw);
6400                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6401                           tv.tv_sec, tv.tv_usec);
6402                 break;
6403         case HNS3_GLOBAL_RESET:
6404                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6405                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6406                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6407                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6408                           tv.tv_sec, tv.tv_usec);
6409                 break;
6410         case HNS3_FUNC_RESET:
6411                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6412                           tv.tv_sec, tv.tv_usec);
6413                 /* schedule again to check later */
6414                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6415                 hns3_schedule_reset(hns);
6416                 break;
6417         default:
6418                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6419                 return;
6420         }
6421         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6422 }
6423
6424 static enum hns3_reset_level
6425 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6426 {
6427         struct hns3_hw *hw = &hns->hw;
6428         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6429
6430         /* Return the highest priority reset level amongst all */
6431         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6432                 reset_level = HNS3_IMP_RESET;
6433         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6434                 reset_level = HNS3_GLOBAL_RESET;
6435         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6436                 reset_level = HNS3_FUNC_RESET;
6437         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6438                 reset_level = HNS3_FLR_RESET;
6439
6440         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6441                 return HNS3_NONE_RESET;
6442
6443         return reset_level;
6444 }
6445
6446 static void
6447 hns3_record_imp_error(struct hns3_adapter *hns)
6448 {
6449         struct hns3_hw *hw = &hns->hw;
6450         uint32_t reg_val;
6451
6452         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6453         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6454                 hns3_warn(hw, "Detected IMP RD poison!");
6455                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6456                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6457         }
6458
6459         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6460                 hns3_warn(hw, "Detected IMP CMDQ error!");
6461                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6462                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6463         }
6464 }
6465
6466 static int
6467 hns3_prepare_reset(struct hns3_adapter *hns)
6468 {
6469         struct hns3_hw *hw = &hns->hw;
6470         uint32_t reg_val;
6471         int ret;
6472
6473         switch (hw->reset.level) {
6474         case HNS3_FUNC_RESET:
6475                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6476                 if (ret)
6477                         return ret;
6478
6479                 /*
6480                  * After performaning pf reset, it is not necessary to do the
6481                  * mailbox handling or send any command to firmware, because
6482                  * any mailbox handling or command to firmware is only valid
6483                  * after hns3_cmd_init is called.
6484                  */
6485                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6486                 hw->reset.stats.request_cnt++;
6487                 break;
6488         case HNS3_IMP_RESET:
6489                 hns3_record_imp_error(hns);
6490                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6491                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6492                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6493                 break;
6494         default:
6495                 break;
6496         }
6497         return 0;
6498 }
6499
6500 static int
6501 hns3_set_rst_done(struct hns3_hw *hw)
6502 {
6503         struct hns3_pf_rst_done_cmd *req;
6504         struct hns3_cmd_desc desc;
6505
6506         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6507         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6508         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6509         return hns3_cmd_send(hw, &desc, 1);
6510 }
6511
6512 static int
6513 hns3_stop_service(struct hns3_adapter *hns)
6514 {
6515         struct hns3_hw *hw = &hns->hw;
6516         struct rte_eth_dev *eth_dev;
6517
6518         eth_dev = &rte_eth_devices[hw->data->port_id];
6519         hw->mac.link_status = ETH_LINK_DOWN;
6520         if (hw->adapter_state == HNS3_NIC_STARTED) {
6521                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6522                 hns3_update_linkstatus_and_event(hw, false);
6523         }
6524
6525         hns3_set_rxtx_function(eth_dev);
6526         rte_wmb();
6527         /* Disable datapath on secondary process. */
6528         hns3_mp_req_stop_rxtx(eth_dev);
6529         rte_delay_ms(hw->tqps_num);
6530
6531         rte_spinlock_lock(&hw->lock);
6532         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6533             hw->adapter_state == HNS3_NIC_STOPPING) {
6534                 hns3_enable_all_queues(hw, false);
6535                 hns3_do_stop(hns);
6536                 hw->reset.mbuf_deferred_free = true;
6537         } else
6538                 hw->reset.mbuf_deferred_free = false;
6539
6540         /*
6541          * It is cumbersome for hardware to pick-and-choose entries for deletion
6542          * from table space. Hence, for function reset software intervention is
6543          * required to delete the entries
6544          */
6545         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6546                 hns3_configure_all_mc_mac_addr(hns, true);
6547         rte_spinlock_unlock(&hw->lock);
6548
6549         return 0;
6550 }
6551
6552 static int
6553 hns3_start_service(struct hns3_adapter *hns)
6554 {
6555         struct hns3_hw *hw = &hns->hw;
6556         struct rte_eth_dev *eth_dev;
6557
6558         if (hw->reset.level == HNS3_IMP_RESET ||
6559             hw->reset.level == HNS3_GLOBAL_RESET)
6560                 hns3_set_rst_done(hw);
6561         eth_dev = &rte_eth_devices[hw->data->port_id];
6562         hns3_set_rxtx_function(eth_dev);
6563         hns3_mp_req_start_rxtx(eth_dev);
6564         if (hw->adapter_state == HNS3_NIC_STARTED) {
6565                 /*
6566                  * This API parent function already hold the hns3_hw.lock, the
6567                  * hns3_service_handler may report lse, in bonding application
6568                  * it will call driver's ops which may acquire the hns3_hw.lock
6569                  * again, thus lead to deadlock.
6570                  * We defer calls hns3_service_handler to avoid the deadlock.
6571                  */
6572                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6573                                   hns3_service_handler, eth_dev);
6574
6575                 /* Enable interrupt of all rx queues before enabling queues */
6576                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6577                 /*
6578                  * Enable state of each rxq and txq will be recovered after
6579                  * reset, so we need to restore them before enable all tqps;
6580                  */
6581                 hns3_restore_tqp_enable_state(hw);
6582                 /*
6583                  * When finished the initialization, enable queues to receive
6584                  * and transmit packets.
6585                  */
6586                 hns3_enable_all_queues(hw, true);
6587         }
6588
6589         return 0;
6590 }
6591
6592 static int
6593 hns3_restore_conf(struct hns3_adapter *hns)
6594 {
6595         struct hns3_hw *hw = &hns->hw;
6596         int ret;
6597
6598         ret = hns3_configure_all_mac_addr(hns, false);
6599         if (ret)
6600                 return ret;
6601
6602         ret = hns3_configure_all_mc_mac_addr(hns, false);
6603         if (ret)
6604                 goto err_mc_mac;
6605
6606         ret = hns3_dev_promisc_restore(hns);
6607         if (ret)
6608                 goto err_promisc;
6609
6610         ret = hns3_restore_vlan_table(hns);
6611         if (ret)
6612                 goto err_promisc;
6613
6614         ret = hns3_restore_vlan_conf(hns);
6615         if (ret)
6616                 goto err_promisc;
6617
6618         ret = hns3_restore_all_fdir_filter(hns);
6619         if (ret)
6620                 goto err_promisc;
6621
6622         ret = hns3_restore_ptp(hns);
6623         if (ret)
6624                 goto err_promisc;
6625
6626         ret = hns3_restore_rx_interrupt(hw);
6627         if (ret)
6628                 goto err_promisc;
6629
6630         ret = hns3_restore_gro_conf(hw);
6631         if (ret)
6632                 goto err_promisc;
6633
6634         ret = hns3_restore_fec(hw);
6635         if (ret)
6636                 goto err_promisc;
6637
6638         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6639                 ret = hns3_do_start(hns, false);
6640                 if (ret)
6641                         goto err_promisc;
6642                 hns3_info(hw, "hns3 dev restart successful!");
6643         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6644                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6645         return 0;
6646
6647 err_promisc:
6648         hns3_configure_all_mc_mac_addr(hns, true);
6649 err_mc_mac:
6650         hns3_configure_all_mac_addr(hns, true);
6651         return ret;
6652 }
6653
6654 static void
6655 hns3_reset_service(void *param)
6656 {
6657         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6658         struct hns3_hw *hw = &hns->hw;
6659         enum hns3_reset_level reset_level;
6660         struct timeval tv_delta;
6661         struct timeval tv_start;
6662         struct timeval tv;
6663         uint64_t msec;
6664         int ret;
6665
6666         /*
6667          * The interrupt is not triggered within the delay time.
6668          * The interrupt may have been lost. It is necessary to handle
6669          * the interrupt to recover from the error.
6670          */
6671         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6672                             SCHEDULE_DEFERRED) {
6673                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6674                                   __ATOMIC_RELAXED);
6675                 hns3_err(hw, "Handling interrupts in delayed tasks");
6676                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6677                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6678                 if (reset_level == HNS3_NONE_RESET) {
6679                         hns3_err(hw, "No reset level is set, try IMP reset");
6680                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6681                 }
6682         }
6683         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6684
6685         /*
6686          * Check if there is any ongoing reset in the hardware. This status can
6687          * be checked from reset_pending. If there is then, we need to wait for
6688          * hardware to complete reset.
6689          *    a. If we are able to figure out in reasonable time that hardware
6690          *       has fully resetted then, we can proceed with driver, client
6691          *       reset.
6692          *    b. else, we can come back later to check this status so re-sched
6693          *       now.
6694          */
6695         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6696         if (reset_level != HNS3_NONE_RESET) {
6697                 gettimeofday(&tv_start, NULL);
6698                 ret = hns3_reset_process(hns, reset_level);
6699                 gettimeofday(&tv, NULL);
6700                 timersub(&tv, &tv_start, &tv_delta);
6701                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6702                        tv_delta.tv_usec / USEC_PER_MSEC;
6703                 if (msec > HNS3_RESET_PROCESS_MS)
6704                         hns3_err(hw, "%d handle long time delta %" PRIx64
6705                                      " ms time=%ld.%.6ld",
6706                                  hw->reset.level, msec,
6707                                  tv.tv_sec, tv.tv_usec);
6708                 if (ret == -EAGAIN)
6709                         return;
6710         }
6711
6712         /* Check if we got any *new* reset requests to be honored */
6713         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6714         if (reset_level != HNS3_NONE_RESET)
6715                 hns3_msix_process(hns, reset_level);
6716 }
6717
6718 static unsigned int
6719 hns3_get_speed_capa_num(uint16_t device_id)
6720 {
6721         unsigned int num;
6722
6723         switch (device_id) {
6724         case HNS3_DEV_ID_25GE:
6725         case HNS3_DEV_ID_25GE_RDMA:
6726                 num = 2;
6727                 break;
6728         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6729         case HNS3_DEV_ID_200G_RDMA:
6730                 num = 1;
6731                 break;
6732         default:
6733                 num = 0;
6734                 break;
6735         }
6736
6737         return num;
6738 }
6739
6740 static int
6741 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6742                         uint16_t device_id)
6743 {
6744         switch (device_id) {
6745         case HNS3_DEV_ID_25GE:
6746         /* fallthrough */
6747         case HNS3_DEV_ID_25GE_RDMA:
6748                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6749                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6750
6751                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6752                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6753                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6754                 break;
6755         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6756                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6757                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6758                 break;
6759         case HNS3_DEV_ID_200G_RDMA:
6760                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6761                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6762                 break;
6763         default:
6764                 return -ENOTSUP;
6765         }
6766
6767         return 0;
6768 }
6769
6770 static int
6771 hns3_fec_get_capability(struct rte_eth_dev *dev,
6772                         struct rte_eth_fec_capa *speed_fec_capa,
6773                         unsigned int num)
6774 {
6775         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6777         uint16_t device_id = pci_dev->id.device_id;
6778         unsigned int capa_num;
6779         int ret;
6780
6781         capa_num = hns3_get_speed_capa_num(device_id);
6782         if (capa_num == 0) {
6783                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6784                          device_id);
6785                 return -ENOTSUP;
6786         }
6787
6788         if (speed_fec_capa == NULL || num < capa_num)
6789                 return capa_num;
6790
6791         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6792         if (ret)
6793                 return -ENOTSUP;
6794
6795         return capa_num;
6796 }
6797
6798 static int
6799 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6800 {
6801         struct hns3_config_fec_cmd *req;
6802         struct hns3_cmd_desc desc;
6803         int ret;
6804
6805         /*
6806          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6807          * in device of link speed
6808          * below 10 Gbps.
6809          */
6810         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6811                 *state = 0;
6812                 return 0;
6813         }
6814
6815         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6816         req = (struct hns3_config_fec_cmd *)desc.data;
6817         ret = hns3_cmd_send(hw, &desc, 1);
6818         if (ret) {
6819                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6820                          ret);
6821                 return ret;
6822         }
6823
6824         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6825         return 0;
6826 }
6827
6828 static int
6829 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6830 {
6831         struct hns3_sfp_info_cmd *resp;
6832         uint32_t tmp_fec_capa;
6833         uint8_t auto_state;
6834         struct hns3_cmd_desc desc;
6835         int ret;
6836
6837         /*
6838          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6839          * configured FEC mode is returned.
6840          * If link is up, current FEC mode is returned.
6841          */
6842         if (hw->mac.link_status == ETH_LINK_DOWN) {
6843                 ret = get_current_fec_auto_state(hw, &auto_state);
6844                 if (ret)
6845                         return ret;
6846
6847                 if (auto_state == 0x1) {
6848                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6849                         return 0;
6850                 }
6851         }
6852
6853         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6854         resp = (struct hns3_sfp_info_cmd *)desc.data;
6855         resp->query_type = HNS3_ACTIVE_QUERY;
6856
6857         ret = hns3_cmd_send(hw, &desc, 1);
6858         if (ret == -EOPNOTSUPP) {
6859                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6860                 return ret;
6861         } else if (ret) {
6862                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6863                 return ret;
6864         }
6865
6866         /*
6867          * FEC mode order defined in hns3 hardware is inconsistend with
6868          * that defined in the ethdev library. So the sequence needs
6869          * to be converted.
6870          */
6871         switch (resp->active_fec) {
6872         case HNS3_HW_FEC_MODE_NOFEC:
6873                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6874                 break;
6875         case HNS3_HW_FEC_MODE_BASER:
6876                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6877                 break;
6878         case HNS3_HW_FEC_MODE_RS:
6879                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6880                 break;
6881         default:
6882                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6883                 break;
6884         }
6885
6886         *fec_capa = tmp_fec_capa;
6887         return 0;
6888 }
6889
6890 static int
6891 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6892 {
6893         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894
6895         return hns3_fec_get_internal(hw, fec_capa);
6896 }
6897
6898 static int
6899 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6900 {
6901         struct hns3_config_fec_cmd *req;
6902         struct hns3_cmd_desc desc;
6903         int ret;
6904
6905         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6906
6907         req = (struct hns3_config_fec_cmd *)desc.data;
6908         switch (mode) {
6909         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6910                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6911                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6912                 break;
6913         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6914                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6915                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6916                 break;
6917         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6918                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6919                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6920                 break;
6921         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6922                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6923                 break;
6924         default:
6925                 return 0;
6926         }
6927         ret = hns3_cmd_send(hw, &desc, 1);
6928         if (ret)
6929                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6930
6931         return ret;
6932 }
6933
6934 static uint32_t
6935 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6936 {
6937         struct hns3_mac *mac = &hw->mac;
6938         uint32_t cur_capa;
6939
6940         switch (mac->link_speed) {
6941         case ETH_SPEED_NUM_10G:
6942                 cur_capa = fec_capa[1].capa;
6943                 break;
6944         case ETH_SPEED_NUM_25G:
6945         case ETH_SPEED_NUM_100G:
6946         case ETH_SPEED_NUM_200G:
6947                 cur_capa = fec_capa[0].capa;
6948                 break;
6949         default:
6950                 cur_capa = 0;
6951                 break;
6952         }
6953
6954         return cur_capa;
6955 }
6956
6957 static bool
6958 is_fec_mode_one_bit_set(uint32_t mode)
6959 {
6960         int cnt = 0;
6961         uint8_t i;
6962
6963         for (i = 0; i < sizeof(mode); i++)
6964                 if (mode >> i & 0x1)
6965                         cnt++;
6966
6967         return cnt == 1 ? true : false;
6968 }
6969
6970 static int
6971 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6972 {
6973 #define FEC_CAPA_NUM 2
6974         struct hns3_adapter *hns = dev->data->dev_private;
6975         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6976         struct hns3_pf *pf = &hns->pf;
6977
6978         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6979         uint32_t cur_capa;
6980         uint32_t num = FEC_CAPA_NUM;
6981         int ret;
6982
6983         ret = hns3_fec_get_capability(dev, fec_capa, num);
6984         if (ret < 0)
6985                 return ret;
6986
6987         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6988         if (!is_fec_mode_one_bit_set(mode))
6989                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6990                              "FEC mode should be only one bit set", mode);
6991
6992         /*
6993          * Check whether the configured mode is within the FEC capability.
6994          * If not, the configured mode will not be supported.
6995          */
6996         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6997         if (!(cur_capa & mode)) {
6998                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6999                 return -EINVAL;
7000         }
7001
7002         rte_spinlock_lock(&hw->lock);
7003         ret = hns3_set_fec_hw(hw, mode);
7004         if (ret) {
7005                 rte_spinlock_unlock(&hw->lock);
7006                 return ret;
7007         }
7008
7009         pf->fec_mode = mode;
7010         rte_spinlock_unlock(&hw->lock);
7011
7012         return 0;
7013 }
7014
7015 static int
7016 hns3_restore_fec(struct hns3_hw *hw)
7017 {
7018         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7019         struct hns3_pf *pf = &hns->pf;
7020         uint32_t mode = pf->fec_mode;
7021         int ret;
7022
7023         ret = hns3_set_fec_hw(hw, mode);
7024         if (ret)
7025                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7026                          mode, ret);
7027
7028         return ret;
7029 }
7030
7031 static int
7032 hns3_query_dev_fec_info(struct hns3_hw *hw)
7033 {
7034         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7035         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7036         int ret;
7037
7038         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7039         if (ret)
7040                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7041
7042         return ret;
7043 }
7044
7045 static bool
7046 hns3_optical_module_existed(struct hns3_hw *hw)
7047 {
7048         struct hns3_cmd_desc desc;
7049         bool existed;
7050         int ret;
7051
7052         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7053         ret = hns3_cmd_send(hw, &desc, 1);
7054         if (ret) {
7055                 hns3_err(hw,
7056                          "fail to get optical module exist state, ret = %d.\n",
7057                          ret);
7058                 return false;
7059         }
7060         existed = !!desc.data[0];
7061
7062         return existed;
7063 }
7064
7065 static int
7066 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7067                                 uint32_t len, uint8_t *data)
7068 {
7069 #define HNS3_SFP_INFO_CMD_NUM 6
7070 #define HNS3_SFP_INFO_MAX_LEN \
7071         (HNS3_SFP_INFO_BD0_LEN + \
7072         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7073         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7074         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7075         uint16_t read_len;
7076         uint16_t copy_len;
7077         int ret;
7078         int i;
7079
7080         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7081                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7082                                           true);
7083                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7084                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7085         }
7086
7087         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7088         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7089         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7090         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7091
7092         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7093         if (ret) {
7094                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7095                                 ret);
7096                 return ret;
7097         }
7098
7099         /* The data format in BD0 is different with the others. */
7100         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7101         memcpy(data, sfp_info_bd0->data, copy_len);
7102         read_len = copy_len;
7103
7104         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7105                 if (read_len >= len)
7106                         break;
7107
7108                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7109                 memcpy(data + read_len, desc[i].data, copy_len);
7110                 read_len += copy_len;
7111         }
7112
7113         return (int)read_len;
7114 }
7115
7116 static int
7117 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7118                        struct rte_dev_eeprom_info *info)
7119 {
7120         struct hns3_adapter *hns = dev->data->dev_private;
7121         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7122         uint32_t offset = info->offset;
7123         uint32_t len = info->length;
7124         uint8_t *data = info->data;
7125         uint32_t read_len = 0;
7126
7127         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7128                 return -ENOTSUP;
7129
7130         if (!hns3_optical_module_existed(hw)) {
7131                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7132                 return -EIO;
7133         }
7134
7135         while (read_len < len) {
7136                 int ret;
7137                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7138                                                   len - read_len,
7139                                                   data + read_len);
7140                 if (ret < 0)
7141                         return -EIO;
7142                 read_len += ret;
7143         }
7144
7145         return 0;
7146 }
7147
7148 static int
7149 hns3_get_module_info(struct rte_eth_dev *dev,
7150                      struct rte_eth_dev_module_info *modinfo)
7151 {
7152 #define HNS3_SFF8024_ID_SFP             0x03
7153 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7154 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7155 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7156 #define HNS3_SFF_8636_V1_3              0x03
7157         struct hns3_adapter *hns = dev->data->dev_private;
7158         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7159         struct rte_dev_eeprom_info info;
7160         struct hns3_sfp_type sfp_type;
7161         int ret;
7162
7163         memset(&sfp_type, 0, sizeof(sfp_type));
7164         memset(&info, 0, sizeof(info));
7165         info.data = (uint8_t *)&sfp_type;
7166         info.length = sizeof(sfp_type);
7167         ret = hns3_get_module_eeprom(dev, &info);
7168         if (ret)
7169                 return ret;
7170
7171         switch (sfp_type.type) {
7172         case HNS3_SFF8024_ID_SFP:
7173                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7174                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7175                 break;
7176         case HNS3_SFF8024_ID_QSFP_8438:
7177                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7178                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7179                 break;
7180         case HNS3_SFF8024_ID_QSFP_8436_8636:
7181                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7182                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7183                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7184                 } else {
7185                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7186                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7187                 }
7188                 break;
7189         case HNS3_SFF8024_ID_QSFP28_8636:
7190                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7191                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7192                 break;
7193         default:
7194                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7195                          sfp_type.type, sfp_type.ext_type);
7196                 return -EINVAL;
7197         }
7198
7199         return 0;
7200 }
7201
7202 static int
7203 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7204 {
7205         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7206
7207         RTE_SET_USED(key);
7208
7209         if (strcmp(value, "vec") == 0)
7210                 hint = HNS3_IO_FUNC_HINT_VEC;
7211         else if (strcmp(value, "sve") == 0)
7212                 hint = HNS3_IO_FUNC_HINT_SVE;
7213         else if (strcmp(value, "simple") == 0)
7214                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7215         else if (strcmp(value, "common") == 0)
7216                 hint = HNS3_IO_FUNC_HINT_COMMON;
7217
7218         /* If the hint is valid then update output parameters */
7219         if (hint != HNS3_IO_FUNC_HINT_NONE)
7220                 *(uint32_t *)extra_args = hint;
7221
7222         return 0;
7223 }
7224
7225 static const char *
7226 hns3_get_io_hint_func_name(uint32_t hint)
7227 {
7228         switch (hint) {
7229         case HNS3_IO_FUNC_HINT_VEC:
7230                 return "vec";
7231         case HNS3_IO_FUNC_HINT_SVE:
7232                 return "sve";
7233         case HNS3_IO_FUNC_HINT_SIMPLE:
7234                 return "simple";
7235         case HNS3_IO_FUNC_HINT_COMMON:
7236                 return "common";
7237         default:
7238                 return "none";
7239         }
7240 }
7241
7242 static int
7243 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7244 {
7245         uint64_t val;
7246
7247         RTE_SET_USED(key);
7248
7249         val = strtoull(value, NULL, 16);
7250         *(uint64_t *)extra_args = val;
7251
7252         return 0;
7253 }
7254
7255 void
7256 hns3_parse_devargs(struct rte_eth_dev *dev)
7257 {
7258         struct hns3_adapter *hns = dev->data->dev_private;
7259         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7260         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7261         struct hns3_hw *hw = &hns->hw;
7262         uint64_t dev_caps_mask = 0;
7263         struct rte_kvargs *kvlist;
7264
7265         if (dev->device->devargs == NULL)
7266                 return;
7267
7268         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7269         if (!kvlist)
7270                 return;
7271
7272         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7273                            &hns3_parse_io_hint_func, &rx_func_hint);
7274         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7275                            &hns3_parse_io_hint_func, &tx_func_hint);
7276         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7277                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7278         rte_kvargs_free(kvlist);
7279
7280         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7281                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7282                           hns3_get_io_hint_func_name(rx_func_hint));
7283         hns->rx_func_hint = rx_func_hint;
7284         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7285                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7286                           hns3_get_io_hint_func_name(tx_func_hint));
7287         hns->tx_func_hint = tx_func_hint;
7288
7289         if (dev_caps_mask != 0)
7290                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7291                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7292         hns->dev_caps_mask = dev_caps_mask;
7293 }
7294
7295 static const struct eth_dev_ops hns3_eth_dev_ops = {
7296         .dev_configure      = hns3_dev_configure,
7297         .dev_start          = hns3_dev_start,
7298         .dev_stop           = hns3_dev_stop,
7299         .dev_close          = hns3_dev_close,
7300         .promiscuous_enable = hns3_dev_promiscuous_enable,
7301         .promiscuous_disable = hns3_dev_promiscuous_disable,
7302         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7303         .allmulticast_disable = hns3_dev_allmulticast_disable,
7304         .mtu_set            = hns3_dev_mtu_set,
7305         .stats_get          = hns3_stats_get,
7306         .stats_reset        = hns3_stats_reset,
7307         .xstats_get         = hns3_dev_xstats_get,
7308         .xstats_get_names   = hns3_dev_xstats_get_names,
7309         .xstats_reset       = hns3_dev_xstats_reset,
7310         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7311         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7312         .dev_infos_get          = hns3_dev_infos_get,
7313         .fw_version_get         = hns3_fw_version_get,
7314         .rx_queue_setup         = hns3_rx_queue_setup,
7315         .tx_queue_setup         = hns3_tx_queue_setup,
7316         .rx_queue_release       = hns3_dev_rx_queue_release,
7317         .tx_queue_release       = hns3_dev_tx_queue_release,
7318         .rx_queue_start         = hns3_dev_rx_queue_start,
7319         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7320         .tx_queue_start         = hns3_dev_tx_queue_start,
7321         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7322         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7323         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7324         .rxq_info_get           = hns3_rxq_info_get,
7325         .txq_info_get           = hns3_txq_info_get,
7326         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7327         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7328         .flow_ctrl_get          = hns3_flow_ctrl_get,
7329         .flow_ctrl_set          = hns3_flow_ctrl_set,
7330         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7331         .mac_addr_add           = hns3_add_mac_addr,
7332         .mac_addr_remove        = hns3_remove_mac_addr,
7333         .mac_addr_set           = hns3_set_default_mac_addr,
7334         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7335         .link_update            = hns3_dev_link_update,
7336         .rss_hash_update        = hns3_dev_rss_hash_update,
7337         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7338         .reta_update            = hns3_dev_rss_reta_update,
7339         .reta_query             = hns3_dev_rss_reta_query,
7340         .flow_ops_get           = hns3_dev_flow_ops_get,
7341         .vlan_filter_set        = hns3_vlan_filter_set,
7342         .vlan_tpid_set          = hns3_vlan_tpid_set,
7343         .vlan_offload_set       = hns3_vlan_offload_set,
7344         .vlan_pvid_set          = hns3_vlan_pvid_set,
7345         .get_reg                = hns3_get_regs,
7346         .get_module_info        = hns3_get_module_info,
7347         .get_module_eeprom      = hns3_get_module_eeprom,
7348         .get_dcb_info           = hns3_get_dcb_info,
7349         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7350         .fec_get_capability     = hns3_fec_get_capability,
7351         .fec_get                = hns3_fec_get,
7352         .fec_set                = hns3_fec_set,
7353         .tm_ops_get             = hns3_tm_ops_get,
7354         .tx_done_cleanup        = hns3_tx_done_cleanup,
7355         .timesync_enable            = hns3_timesync_enable,
7356         .timesync_disable           = hns3_timesync_disable,
7357         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7358         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7359         .timesync_adjust_time       = hns3_timesync_adjust_time,
7360         .timesync_read_time         = hns3_timesync_read_time,
7361         .timesync_write_time        = hns3_timesync_write_time,
7362 };
7363
7364 static const struct hns3_reset_ops hns3_reset_ops = {
7365         .reset_service       = hns3_reset_service,
7366         .stop_service        = hns3_stop_service,
7367         .prepare_reset       = hns3_prepare_reset,
7368         .wait_hardware_ready = hns3_wait_hardware_ready,
7369         .reinit_dev          = hns3_reinit_dev,
7370         .restore_conf        = hns3_restore_conf,
7371         .start_service       = hns3_start_service,
7372 };
7373
7374 static int
7375 hns3_dev_init(struct rte_eth_dev *eth_dev)
7376 {
7377         struct hns3_adapter *hns = eth_dev->data->dev_private;
7378         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7379         struct rte_ether_addr *eth_addr;
7380         struct hns3_hw *hw = &hns->hw;
7381         int ret;
7382
7383         PMD_INIT_FUNC_TRACE();
7384
7385         eth_dev->process_private = (struct hns3_process_private *)
7386             rte_zmalloc_socket("hns3_filter_list",
7387                                sizeof(struct hns3_process_private),
7388                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7389         if (eth_dev->process_private == NULL) {
7390                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7391                 return -ENOMEM;
7392         }
7393
7394         hns3_flow_init(eth_dev);
7395
7396         hns3_set_rxtx_function(eth_dev);
7397         eth_dev->dev_ops = &hns3_eth_dev_ops;
7398         eth_dev->rx_queue_count = hns3_rx_queue_count;
7399         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7400                 ret = hns3_mp_init_secondary();
7401                 if (ret) {
7402                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7403                                      "process, ret = %d", ret);
7404                         goto err_mp_init_secondary;
7405                 }
7406
7407                 hw->secondary_cnt++;
7408                 return 0;
7409         }
7410
7411         ret = hns3_mp_init_primary();
7412         if (ret) {
7413                 PMD_INIT_LOG(ERR,
7414                              "Failed to init for primary process, ret = %d",
7415                              ret);
7416                 goto err_mp_init_primary;
7417         }
7418
7419         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7420         hns->is_vf = false;
7421         hw->data = eth_dev->data;
7422         hns3_parse_devargs(eth_dev);
7423
7424         /*
7425          * Set default max packet size according to the mtu
7426          * default vale in DPDK frame.
7427          */
7428         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7429
7430         ret = hns3_reset_init(hw);
7431         if (ret)
7432                 goto err_init_reset;
7433         hw->reset.ops = &hns3_reset_ops;
7434
7435         ret = hns3_init_pf(eth_dev);
7436         if (ret) {
7437                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7438                 goto err_init_pf;
7439         }
7440
7441         /* Allocate memory for storing MAC addresses */
7442         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7443                                                sizeof(struct rte_ether_addr) *
7444                                                HNS3_UC_MACADDR_NUM, 0);
7445         if (eth_dev->data->mac_addrs == NULL) {
7446                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7447                              "to store MAC addresses",
7448                              sizeof(struct rte_ether_addr) *
7449                              HNS3_UC_MACADDR_NUM);
7450                 ret = -ENOMEM;
7451                 goto err_rte_zmalloc;
7452         }
7453
7454         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7455         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7456                 rte_eth_random_addr(hw->mac.mac_addr);
7457                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7458                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7459                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7460                           "unicast address, using random MAC address %s",
7461                           mac_str);
7462         }
7463         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7464                             &eth_dev->data->mac_addrs[0]);
7465
7466         hw->adapter_state = HNS3_NIC_INITIALIZED;
7467
7468         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7469                             SCHEDULE_PENDING) {
7470                 hns3_err(hw, "Reschedule reset service after dev_init");
7471                 hns3_schedule_reset(hns);
7472         } else {
7473                 /* IMP will wait ready flag before reset */
7474                 hns3_notify_reset_ready(hw, false);
7475         }
7476
7477         hns3_info(hw, "hns3 dev initialization successful!");
7478         return 0;
7479
7480 err_rte_zmalloc:
7481         hns3_uninit_pf(eth_dev);
7482
7483 err_init_pf:
7484         rte_free(hw->reset.wait_data);
7485
7486 err_init_reset:
7487         hns3_mp_uninit_primary();
7488
7489 err_mp_init_primary:
7490 err_mp_init_secondary:
7491         eth_dev->dev_ops = NULL;
7492         eth_dev->rx_pkt_burst = NULL;
7493         eth_dev->rx_descriptor_status = NULL;
7494         eth_dev->tx_pkt_burst = NULL;
7495         eth_dev->tx_pkt_prepare = NULL;
7496         eth_dev->tx_descriptor_status = NULL;
7497         rte_free(eth_dev->process_private);
7498         eth_dev->process_private = NULL;
7499         return ret;
7500 }
7501
7502 static int
7503 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7504 {
7505         struct hns3_adapter *hns = eth_dev->data->dev_private;
7506         struct hns3_hw *hw = &hns->hw;
7507
7508         PMD_INIT_FUNC_TRACE();
7509
7510         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7511                 rte_free(eth_dev->process_private);
7512                 eth_dev->process_private = NULL;
7513                 return 0;
7514         }
7515
7516         if (hw->adapter_state < HNS3_NIC_CLOSING)
7517                 hns3_dev_close(eth_dev);
7518
7519         hw->adapter_state = HNS3_NIC_REMOVED;
7520         return 0;
7521 }
7522
7523 static int
7524 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7525                    struct rte_pci_device *pci_dev)
7526 {
7527         return rte_eth_dev_pci_generic_probe(pci_dev,
7528                                              sizeof(struct hns3_adapter),
7529                                              hns3_dev_init);
7530 }
7531
7532 static int
7533 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7534 {
7535         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7536 }
7537
7538 static const struct rte_pci_id pci_id_hns3_map[] = {
7539         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7540         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7541         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7542         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7543         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7544         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7545         { .vendor_id = 0, }, /* sentinel */
7546 };
7547
7548 static struct rte_pci_driver rte_hns3_pmd = {
7549         .id_table = pci_id_hns3_map,
7550         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7551         .probe = eth_hns3_pci_probe,
7552         .remove = eth_hns3_pci_remove,
7553 };
7554
7555 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7556 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7557 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7558 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7559                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7560                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7561                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7562 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7563 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);