drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  20 #define HNS3_SERVICE_QUICK_INTERVAL     10
  21 #define HNS3_INVALID_PVID               0xFFFF
  22
  23 #define HNS3_FILTER_TYPE_VF             0
  24 #define HNS3_FILTER_TYPE_PORT           1
  25 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  26 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  27 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  28 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  29 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  30 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  31                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  32 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  34
  35 /* Reset related Registers */
  36 #define HNS3_GLOBAL_RESET_BIT           0
  37 #define HNS3_CORE_RESET_BIT             1
  38 #define HNS3_IMP_RESET_BIT              2
  39 #define HNS3_FUN_RST_ING_B              0
  40
  41 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  43 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  45
  46 #define HNS3_RESET_WAIT_MS      100
  47 #define HNS3_RESET_WAIT_CNT     200
  48
  49 /* FEC mode order defined in HNS3 hardware */
  50 #define HNS3_HW_FEC_MODE_NOFEC  0
  51 #define HNS3_HW_FEC_MODE_BASER  1
  52 #define HNS3_HW_FEC_MODE_RS     2
  53
  54 enum hns3_evt_cause {
  55         HNS3_VECTOR0_EVENT_RST,
  56         HNS3_VECTOR0_EVENT_MBX,
  57         HNS3_VECTOR0_EVENT_ERR,
  58         HNS3_VECTOR0_EVENT_PTP,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  96 static bool hns3_update_link_status(struct hns3_hw *hw);
  97
  98 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
  99                                 struct rte_ether_addr *mac_addr);
 100 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 101                                    struct rte_ether_addr *mac_addr);
 102 static int hns3_restore_fec(struct hns3_hw *hw);
 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 104 static int hns3_do_stop(struct hns3_adapter *hns);
 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 106 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 107
 108 void hns3_ether_format_addr(char *buf, uint16_t size,
 109                             const struct rte_ether_addr *ether_addr)
 110 {
 111         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 112                 ether_addr->addr_bytes[0],
 113                 ether_addr->addr_bytes[4],
 114                 ether_addr->addr_bytes[5]);
 115 }
 116
 117 static void
 118 hns3_pf_disable_irq0(struct hns3_hw *hw)
 119 {
 120         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 121 }
 122
 123 static void
 124 hns3_pf_enable_irq0(struct hns3_hw *hw)
 125 {
 126         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 127 }
 128
 129 static enum hns3_evt_cause
 130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 131                           uint32_t *vec_val)
 132 {
 133         struct hns3_hw *hw = &hns->hw;
 134
 135         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 136         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 137         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 138         if (!is_delay) {
 139                 hw->reset.stats.imp_cnt++;
 140                 hns3_warn(hw, "IMP reset detected, clear reset status");
 141         } else {
 142                 hns3_schedule_delayed_reset(hns);
 143                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 144         }
 145
 146         return HNS3_VECTOR0_EVENT_RST;
 147 }
 148
 149 static enum hns3_evt_cause
 150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 151                              uint32_t *vec_val)
 152 {
 153         struct hns3_hw *hw = &hns->hw;
 154
 155         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 156         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 157         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 158         if (!is_delay) {
 159                 hw->reset.stats.global_cnt++;
 160                 hns3_warn(hw, "Global reset detected, clear reset status");
 161         } else {
 162                 hns3_schedule_delayed_reset(hns);
 163                 hns3_warn(hw,
 164                           "Global reset detected, don't clear reset status");
 165         }
 166
 167         return HNS3_VECTOR0_EVENT_RST;
 168 }
 169
 170 static enum hns3_evt_cause
 171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 172 {
 173         struct hns3_hw *hw = &hns->hw;
 174         uint32_t vector0_int_stats;
 175         uint32_t cmdq_src_val;
 176         uint32_t hw_err_src_reg;
 177         uint32_t val;
 178         enum hns3_evt_cause ret;
 179         bool is_delay;
 180
 181         /* fetch the events from their corresponding regs */
 182         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 183         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 184         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 185
 186         is_delay = clearval == NULL ? true : false;
 187         /*
 188          * Assumption: If by any chance reset and mailbox events are reported
 189          * together then we will only process reset event and defer the
 190          * processing of the mailbox events. Since, we would have not cleared
 191          * RX CMDQ event this time we would receive again another interrupt
 192          * from H/W just for the mailbox.
 193          */
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 195                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 196                 goto out;
 197         }
 198
 199         /* Global reset */
 200         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 201                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 202                 goto out;
 203         }
 204
 205         /* Check for vector0 1588 event source */
 206         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 207                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 208                 ret = HNS3_VECTOR0_EVENT_PTP;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 msix event source */
 213         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 214             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 215                 val = vector0_int_stats | hw_err_src_reg;
 216                 ret = HNS3_VECTOR0_EVENT_ERR;
 217                 goto out;
 218         }
 219
 220         /* check for vector0 mailbox(=CMDQ RX) event source */
 221         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 222                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 223                 val = cmdq_src_val;
 224                 ret = HNS3_VECTOR0_EVENT_MBX;
 225                 goto out;
 226         }
 227
 228         val = vector0_int_stats;
 229         ret = HNS3_VECTOR0_EVENT_OTHER;
 230 out:
 231
 232         if (clearval)
 233                 *clearval = val;
 234         return ret;
 235 }
 236
 237 static bool
 238 hns3_is_1588_event_type(uint32_t event_type)
 239 {
 240         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 241 }
 242
 243 static void
 244 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 245 {
 246         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 247             hns3_is_1588_event_type(event_type))
 248                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 249         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 250                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 251 }
 252
 253 static void
 254 hns3_clear_all_event_cause(struct hns3_hw *hw)
 255 {
 256         uint32_t vector0_int_stats;
 257
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 260                 hns3_warn(hw, "Probe during IMP reset interrupt");
 261
 262         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 263                 hns3_warn(hw, "Probe during Global reset interrupt");
 264
 265         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 266                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 267                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 269         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 271                                 BIT(HNS3_VECTOR0_1588_INT_B));
 272 }
 273
 274 static void
 275 hns3_handle_mac_tnl(struct hns3_hw *hw)
 276 {
 277         struct hns3_cmd_desc desc;
 278         uint32_t status;
 279         int ret;
 280
 281         /* query and clear mac tnl interrupt */
 282         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 283         ret = hns3_cmd_send(hw, &desc, 1);
 284         if (ret) {
 285                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 286                 return;
 287         }
 288
 289         status = rte_le_to_cpu_32(desc.data[0]);
 290         if (status) {
 291                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 292                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 293                                           false);
 294                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 295                 ret = hns3_cmd_send(hw, &desc, 1);
 296                 if (ret)
 297                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 298                                  ret);
 299         }
 300 }
 301
 302 static void
 303 hns3_interrupt_handler(void *param)
 304 {
 305         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 306         struct hns3_adapter *hns = dev->data->dev_private;
 307         struct hns3_hw *hw = &hns->hw;
 308         enum hns3_evt_cause event_cause;
 309         uint32_t clearval = 0;
 310         uint32_t vector0_int;
 311         uint32_t ras_int;
 312         uint32_t cmdq_int;
 313
 314         /* Disable interrupt */
 315         hns3_pf_disable_irq0(hw);
 316
 317         event_cause = hns3_check_event_cause(hns, &clearval);
 318         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 319         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 320         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 321         hns3_clear_event_cause(hw, event_cause, clearval);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_mac_tnl(hw);
 328                 hns3_handle_error(hns);
 329         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 330                 hns3_warn(hw, "received reset interrupt");
 331                 hns3_schedule_reset(hns);
 332         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 333                 hns3_dev_handle_mbx_msg(hw);
 334         } else {
 335                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 336                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 337                           vector0_int, ras_int, cmdq_int);
 338         }
 339
 340         /* Enable interrupt if it is not cause by reset */
 341         hns3_pf_enable_irq0(hw);
 342 }
 343
 344 static int
 345 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 346 {
 347 #define HNS3_VLAN_ID_OFFSET_STEP        160
 348 #define HNS3_VLAN_BYTE_SIZE             8
 349         struct hns3_vlan_filter_pf_cfg_cmd *req;
 350         struct hns3_hw *hw = &hns->hw;
 351         uint8_t vlan_offset_byte_val;
 352         struct hns3_cmd_desc desc;
 353         uint8_t vlan_offset_byte;
 354         uint8_t vlan_offset_base;
 355         int ret;
 356
 357         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 358
 359         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 360         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 361                            HNS3_VLAN_BYTE_SIZE;
 362         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 363
 364         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 365         req->vlan_offset = vlan_offset_base;
 366         req->vlan_cfg = on ? 0 : 1;
 367         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 368
 369         ret = hns3_cmd_send(hw, &desc, 1);
 370         if (ret)
 371                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 372                          vlan_id, ret);
 373
 374         return ret;
 375 }
 376
 377 static void
 378 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 379 {
 380         struct hns3_user_vlan_table *vlan_entry;
 381         struct hns3_pf *pf = &hns->pf;
 382
 383         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 384                 if (vlan_entry->vlan_id == vlan_id) {
 385                         if (vlan_entry->hd_tbl_status)
 386                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 387                         LIST_REMOVE(vlan_entry, next);
 388                         rte_free(vlan_entry);
 389                         break;
 390                 }
 391         }
 392 }
 393
 394 static void
 395 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 396                         bool writen_to_tbl)
 397 {
 398         struct hns3_user_vlan_table *vlan_entry;
 399         struct hns3_hw *hw = &hns->hw;
 400         struct hns3_pf *pf = &hns->pf;
 401
 402         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 403                 if (vlan_entry->vlan_id == vlan_id)
 404                         return;
 405         }
 406
 407         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 408         if (vlan_entry == NULL) {
 409                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 410                 return;
 411         }
 412
 413         vlan_entry->hd_tbl_status = writen_to_tbl;
 414         vlan_entry->vlan_id = vlan_id;
 415
 416         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 417 }
 418
 419 static int
 420 hns3_restore_vlan_table(struct hns3_adapter *hns)
 421 {
 422         struct hns3_user_vlan_table *vlan_entry;
 423         struct hns3_hw *hw = &hns->hw;
 424         struct hns3_pf *pf = &hns->pf;
 425         uint16_t vlan_id;
 426         int ret = 0;
 427
 428         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 429                 return hns3_vlan_pvid_configure(hns,
 430                                                 hw->port_base_vlan_cfg.pvid, 1);
 431
 432         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 433                 if (vlan_entry->hd_tbl_status) {
 434                         vlan_id = vlan_entry->vlan_id;
 435                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 436                         if (ret)
 437                                 break;
 438                 }
 439         }
 440
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 446 {
 447         struct hns3_hw *hw = &hns->hw;
 448         bool writen_to_tbl = false;
 449         int ret = 0;
 450
 451         /*
 452          * When vlan filter is enabled, hardware regards packets without vlan
 453          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 454          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 455          */
 456         if (on == 0 && vlan_id == 0)
 457                 return 0;
 458
 459         /*
 460          * When port base vlan enabled, we use port base vlan as the vlan
 461          * filter condition. In this case, we don't update vlan filter table
 462          * when user add new vlan or remove exist vlan, just update the
 463          * vlan list. The vlan id in vlan list will be written in vlan filter
 464          * table until port base vlan disabled
 465          */
 466         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 467                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 468                 writen_to_tbl = true;
 469         }
 470
 471         if (ret == 0) {
 472                 if (on)
 473                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 474                 else
 475                         hns3_rm_dev_vlan_table(hns, vlan_id);
 476         }
 477         return ret;
 478 }
 479
 480 static int
 481 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 482 {
 483         struct hns3_adapter *hns = dev->data->dev_private;
 484         struct hns3_hw *hw = &hns->hw;
 485         int ret;
 486
 487         rte_spinlock_lock(&hw->lock);
 488         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 489         rte_spinlock_unlock(&hw->lock);
 490         return ret;
 491 }
 492
 493 static int
 494 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 495                          uint16_t tpid)
 496 {
 497         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 498         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 499         struct hns3_hw *hw = &hns->hw;
 500         struct hns3_cmd_desc desc;
 501         int ret;
 502
 503         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 504              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 505                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 506                 return -EINVAL;
 507         }
 508
 509         if (tpid != RTE_ETHER_TYPE_VLAN) {
 510                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 511                 return -EINVAL;
 512         }
 513
 514         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 515         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 516
 517         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 518                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 519                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 520         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525         }
 526
 527         ret = hns3_cmd_send(hw, &desc, 1);
 528         if (ret) {
 529                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 530                          ret);
 531                 return ret;
 532         }
 533
 534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 535
 536         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 537         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 538         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 539
 540         ret = hns3_cmd_send(hw, &desc, 1);
 541         if (ret)
 542                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 543                          ret);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 549                    uint16_t tpid)
 550 {
 551         struct hns3_adapter *hns = dev->data->dev_private;
 552         struct hns3_hw *hw = &hns->hw;
 553         int ret;
 554
 555         rte_spinlock_lock(&hw->lock);
 556         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 557         rte_spinlock_unlock(&hw->lock);
 558         return ret;
 559 }
 560
 561 static int
 562 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 563                              struct hns3_rx_vtag_cfg *vcfg)
 564 {
 565         struct hns3_vport_vtag_rx_cfg_cmd *req;
 566         struct hns3_hw *hw = &hns->hw;
 567         struct hns3_cmd_desc desc;
 568         uint16_t vport_id;
 569         uint8_t bitmap;
 570         int ret;
 571
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 573
 574         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 575         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 576                      vcfg->strip_tag1_en ? 1 : 0);
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 578                      vcfg->strip_tag2_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 580                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 582                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 583
 584         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 585         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 586                      vcfg->strip_tag1_discard_en ? 1 : 0);
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 588                      vcfg->strip_tag2_discard_en ? 1 : 0);
 589         /*
 590          * In current version VF is not supported when PF is driven by DPDK
 591          * driver, just need to configure parameters for PF vport.
 592          */
 593         vport_id = HNS3_PF_FUNC_ID;
 594         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 595         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 596         req->vf_bitmap[req->vf_offset] = bitmap;
 597
 598         ret = hns3_cmd_send(hw, &desc, 1);
 599         if (ret)
 600                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 601         return ret;
 602 }
 603
 604 static void
 605 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 606                            struct hns3_rx_vtag_cfg *vcfg)
 607 {
 608         struct hns3_pf *pf = &hns->pf;
 609         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 610 }
 611
 612 static void
 613 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 614                            struct hns3_tx_vtag_cfg *vcfg)
 615 {
 616         struct hns3_pf *pf = &hns->pf;
 617         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 618 }
 619
 620 static int
 621 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 622 {
 623         struct hns3_rx_vtag_cfg rxvlan_cfg;
 624         struct hns3_hw *hw = &hns->hw;
 625         int ret;
 626
 627         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 628                 rxvlan_cfg.strip_tag1_en = false;
 629                 rxvlan_cfg.strip_tag2_en = enable;
 630                 rxvlan_cfg.strip_tag2_discard_en = false;
 631         } else {
 632                 rxvlan_cfg.strip_tag1_en = enable;
 633                 rxvlan_cfg.strip_tag2_en = true;
 634                 rxvlan_cfg.strip_tag2_discard_en = true;
 635         }
 636
 637         rxvlan_cfg.strip_tag1_discard_en = false;
 638         rxvlan_cfg.vlan1_vlan_prionly = false;
 639         rxvlan_cfg.vlan2_vlan_prionly = false;
 640         rxvlan_cfg.rx_vlan_offload_en = enable;
 641
 642         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 643         if (ret) {
 644                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 645                                 enable ? "enable" : "disable", ret);
 646                 return ret;
 647         }
 648
 649         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 656                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 657 {
 658         struct hns3_vlan_filter_ctrl_cmd *req;
 659         struct hns3_cmd_desc desc;
 660         int ret;
 661
 662         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 663
 664         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 665         req->vlan_type = vlan_type;
 666         req->vlan_fe = filter_en ? fe_type : 0;
 667         req->vf_id = vf_id;
 668
 669         ret = hns3_cmd_send(hw, &desc, 1);
 670         if (ret)
 671                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 672
 673         return ret;
 674 }
 675
 676 static int
 677 hns3_vlan_filter_init(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         int ret;
 681
 682         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 683                                         HNS3_FILTER_FE_EGRESS, false,
 684                                         HNS3_PF_FUNC_ID);
 685         if (ret) {
 686                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 687                 return ret;
 688         }
 689
 690         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 691                                         HNS3_FILTER_FE_INGRESS, false,
 692                                         HNS3_PF_FUNC_ID);
 693         if (ret)
 694                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 701 {
 702         struct hns3_hw *hw = &hns->hw;
 703         int ret;
 704
 705         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 706                                         HNS3_FILTER_FE_INGRESS, enable,
 707                                         HNS3_PF_FUNC_ID);
 708         if (ret)
 709                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 710                          enable ? "enable" : "disable", ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 717 {
 718         struct hns3_adapter *hns = dev->data->dev_private;
 719         struct hns3_hw *hw = &hns->hw;
 720         struct rte_eth_rxmode *rxmode;
 721         unsigned int tmp_mask;
 722         bool enable;
 723         int ret = 0;
 724
 725         rte_spinlock_lock(&hw->lock);
 726         rxmode = &dev->data->dev_conf.rxmode;
 727         tmp_mask = (unsigned int)mask;
 728         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 729                 /* ignore vlan filter configuration during promiscuous mode */
 730                 if (!dev->data->promiscuous) {
 731                         /* Enable or disable VLAN filter */
 732                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 733                                  true : false;
 734
 735                         ret = hns3_enable_vlan_filter(hns, enable);
 736                         if (ret) {
 737                                 rte_spinlock_unlock(&hw->lock);
 738                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 739                                          enable ? "enable" : "disable", ret);
 740                                 return ret;
 741                         }
 742                 }
 743         }
 744
 745         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 746                 /* Enable or disable VLAN stripping */
 747                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 748                     true : false;
 749
 750                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 751                 if (ret) {
 752                         rte_spinlock_unlock(&hw->lock);
 753                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 754                                  enable ? "enable" : "disable", ret);
 755                         return ret;
 756                 }
 757         }
 758
 759         rte_spinlock_unlock(&hw->lock);
 760
 761         return ret;
 762 }
 763
 764 static int
 765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 766                              struct hns3_tx_vtag_cfg *vcfg)
 767 {
 768         struct hns3_vport_vtag_tx_cfg_cmd *req;
 769         struct hns3_cmd_desc desc;
 770         struct hns3_hw *hw = &hns->hw;
 771         uint16_t vport_id;
 772         uint8_t bitmap;
 773         int ret;
 774
 775         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 776
 777         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 778         req->def_vlan_tag1 = vcfg->default_tag1;
 779         req->def_vlan_tag2 = vcfg->default_tag2;
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 781                      vcfg->accept_tag1 ? 1 : 0);
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 783                      vcfg->accept_untag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 785                      vcfg->accept_tag2 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 787                      vcfg->accept_untag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 789                      vcfg->insert_tag1_en ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 791                      vcfg->insert_tag2_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 793
 794         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 795         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 796                      vcfg->tag_shift_mode_en ? 1 : 0);
 797
 798         /*
 799          * In current version VF is not supported when PF is driven by DPDK
 800          * driver, just need to configure parameters for PF vport.
 801          */
 802         vport_id = HNS3_PF_FUNC_ID;
 803         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 804         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 805         req->vf_bitmap[req->vf_offset] = bitmap;
 806
 807         ret = hns3_cmd_send(hw, &desc, 1);
 808         if (ret)
 809                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 810
 811         return ret;
 812 }
 813
 814 static int
 815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 816                      uint16_t pvid)
 817 {
 818         struct hns3_hw *hw = &hns->hw;
 819         struct hns3_tx_vtag_cfg txvlan_cfg;
 820         int ret;
 821
 822         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 823                 txvlan_cfg.accept_tag1 = true;
 824                 txvlan_cfg.insert_tag1_en = false;
 825                 txvlan_cfg.default_tag1 = 0;
 826         } else {
 827                 txvlan_cfg.accept_tag1 =
 828                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 829                 txvlan_cfg.insert_tag1_en = true;
 830                 txvlan_cfg.default_tag1 = pvid;
 831         }
 832
 833         txvlan_cfg.accept_untag1 = true;
 834         txvlan_cfg.accept_tag2 = true;
 835         txvlan_cfg.accept_untag2 = true;
 836         txvlan_cfg.insert_tag2_en = false;
 837         txvlan_cfg.default_tag2 = 0;
 838         txvlan_cfg.tag_shift_mode_en = true;
 839
 840         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 841         if (ret) {
 842                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 843                          ret);
 844                 return ret;
 845         }
 846
 847         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 848         return ret;
 849 }
 850
 851
 852 static void
 853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 854 {
 855         struct hns3_user_vlan_table *vlan_entry;
 856         struct hns3_pf *pf = &hns->pf;
 857
 858         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 859                 if (vlan_entry->hd_tbl_status) {
 860                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 861                         vlan_entry->hd_tbl_status = false;
 862                 }
 863         }
 864
 865         if (is_del_list) {
 866                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 867                 while (vlan_entry) {
 868                         LIST_REMOVE(vlan_entry, next);
 869                         rte_free(vlan_entry);
 870                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 871                 }
 872         }
 873 }
 874
 875 static void
 876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 877 {
 878         struct hns3_user_vlan_table *vlan_entry;
 879         struct hns3_pf *pf = &hns->pf;
 880
 881         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 882                 if (!vlan_entry->hd_tbl_status) {
 883                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 884                         vlan_entry->hd_tbl_status = true;
 885                 }
 886         }
 887 }
 888
 889 static void
 890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 891 {
 892         struct hns3_hw *hw = &hns->hw;
 893         int ret;
 894
 895         hns3_rm_all_vlan_table(hns, true);
 896         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 897                 ret = hns3_set_port_vlan_filter(hns,
 898                                                 hw->port_base_vlan_cfg.pvid, 0);
 899                 if (ret) {
 900                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 901                                  ret);
 902                         return;
 903                 }
 904         }
 905 }
 906
 907 static int
 908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 909                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         uint16_t old_pvid;
 913         int ret;
 914
 915         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 916                 old_pvid = hw->port_base_vlan_cfg.pvid;
 917                 if (old_pvid != HNS3_INVALID_PVID) {
 918                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 919                         if (ret) {
 920                                 hns3_err(hw, "failed to remove old pvid %u, "
 921                                                 "ret = %d", old_pvid, ret);
 922                                 return ret;
 923                         }
 924                 }
 925
 926                 hns3_rm_all_vlan_table(hns, false);
 927                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 928                 if (ret) {
 929                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 930                                         new_pvid, ret);
 931                         return ret;
 932                 }
 933         } else {
 934                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 935                 if (ret) {
 936                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 937                                         new_pvid, ret);
 938                         return ret;
 939                 }
 940
 941                 hns3_add_all_vlan_table(hns);
 942         }
 943         return 0;
 944 }
 945
 946 static int
 947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 948 {
 949         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 950         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 951         bool rx_strip_en;
 952         int ret;
 953
 954         rx_strip_en = old_cfg->rx_vlan_offload_en;
 955         if (on) {
 956                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 957                 rx_vlan_cfg.strip_tag2_en = true;
 958                 rx_vlan_cfg.strip_tag2_discard_en = true;
 959         } else {
 960                 rx_vlan_cfg.strip_tag1_en = false;
 961                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 962                 rx_vlan_cfg.strip_tag2_discard_en = false;
 963         }
 964         rx_vlan_cfg.strip_tag1_discard_en = false;
 965         rx_vlan_cfg.vlan1_vlan_prionly = false;
 966         rx_vlan_cfg.vlan2_vlan_prionly = false;
 967         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 968
 969         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 970         if (ret)
 971                 return ret;
 972
 973         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 974         return ret;
 975 }
 976
 977 static int
 978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 979 {
 980         struct hns3_hw *hw = &hns->hw;
 981         uint16_t port_base_vlan_state;
 982         int ret, err;
 983
 984         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 985                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 986                         hns3_warn(hw, "Invalid operation! As current pvid set "
 987                                   "is %u, disable pvid %u is invalid",
 988                                   hw->port_base_vlan_cfg.pvid, pvid);
 989                 return 0;
 990         }
 991
 992         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 993                                     HNS3_PORT_BASE_VLAN_DISABLE;
 994         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 995         if (ret) {
 996                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 997                          ret);
 998                 return ret;
 999         }
1000
1001         ret = hns3_en_pvid_strip(hns, on);
1002         if (ret) {
1003                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004                          "ret = %d", ret);
1005                 goto pvid_vlan_strip_fail;
1006         }
1007
1008         if (pvid == HNS3_INVALID_PVID)
1009                 goto out;
1010         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011         if (ret) {
1012                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013                          ret);
1014                 goto vlan_filter_set_fail;
1015         }
1016
1017 out:
1018         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1020         return ret;
1021
1022 vlan_filter_set_fail:
1023         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024                                         HNS3_PORT_BASE_VLAN_ENABLE);
1025         if (err)
1026                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027
1028 pvid_vlan_strip_fail:
1029         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030                                         hw->port_base_vlan_cfg.pvid);
1031         if (err)
1032                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 {
1040         struct hns3_adapter *hns = dev->data->dev_private;
1041         struct hns3_hw *hw = &hns->hw;
1042         bool pvid_en_state_change;
1043         uint16_t pvid_state;
1044         int ret;
1045
1046         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048                          RTE_ETHER_MAX_VLAN_ID);
1049                 return -EINVAL;
1050         }
1051
1052         /*
1053          * If PVID configuration state change, should refresh the PVID
1054          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055          */
1056         pvid_state = hw->port_base_vlan_cfg.state;
1057         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059                 pvid_en_state_change = false;
1060         else
1061                 pvid_en_state_change = true;
1062
1063         rte_spinlock_lock(&hw->lock);
1064         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065         rte_spinlock_unlock(&hw->lock);
1066         if (ret)
1067                 return ret;
1068         /*
1069          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070          * need be processed by PMD driver.
1071          */
1072         if (pvid_en_state_change &&
1073             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074                 hns3_update_all_queues_pvid_proc_en(hw);
1075
1076         return 0;
1077 }
1078
1079 static int
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 {
1082         struct hns3_hw *hw = &hns->hw;
1083         int ret;
1084
1085         /*
1086          * When vlan filter is enabled, hardware regards packets without vlan
1087          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088          * table, packets without vlan won't be received. So, add vlan 0 as
1089          * the default vlan.
1090          */
1091         ret = hns3_vlan_filter_configure(hns, 0, 1);
1092         if (ret)
1093                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1094         return ret;
1095 }
1096
1097 static int
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 {
1100         struct hns3_hw *hw = &hns->hw;
1101         int ret;
1102
1103         /*
1104          * This function can be called in the initialization and reset process,
1105          * when in reset process, it means that hardware had been reseted
1106          * successfully and we need to restore the hardware configuration to
1107          * ensure that the hardware configuration remains unchanged before and
1108          * after reset.
1109          */
1110         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1113         }
1114
1115         ret = hns3_vlan_filter_init(hns);
1116         if (ret) {
1117                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1118                 return ret;
1119         }
1120
1121         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1122                                        RTE_ETHER_TYPE_VLAN);
1123         if (ret) {
1124                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1125                 return ret;
1126         }
1127
1128         /*
1129          * When in the reinit dev stage of the reset process, the following
1130          * vlan-related configurations may differ from those at initialization,
1131          * we will restore configurations to hardware in hns3_restore_vlan_table
1132          * and hns3_restore_vlan_conf later.
1133          */
1134         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136                 if (ret) {
1137                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1138                         return ret;
1139                 }
1140
1141                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142                 if (ret) {
1143                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1144                                  ret);
1145                         return ret;
1146                 }
1147         }
1148
1149         return hns3_default_vlan_config(hns);
1150 }
1151
1152 static int
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 {
1155         struct hns3_pf *pf = &hns->pf;
1156         struct hns3_hw *hw = &hns->hw;
1157         uint64_t offloads;
1158         bool enable;
1159         int ret;
1160
1161         if (!hw->data->promiscuous) {
1162                 /* restore vlan filter states */
1163                 offloads = hw->data->dev_conf.rxmode.offloads;
1164                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165                 ret = hns3_enable_vlan_filter(hns, enable);
1166                 if (ret) {
1167                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1168                                  "ret = %d", ret);
1169                         return ret;
1170                 }
1171         }
1172
1173         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174         if (ret) {
1175                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1176                 return ret;
1177         }
1178
1179         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180         if (ret)
1181                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1182
1183         return ret;
1184 }
1185
1186 static int
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 {
1189         struct hns3_adapter *hns = dev->data->dev_private;
1190         struct rte_eth_dev_data *data = dev->data;
1191         struct rte_eth_txmode *txmode;
1192         struct hns3_hw *hw = &hns->hw;
1193         int mask;
1194         int ret;
1195
1196         txmode = &data->dev_conf.txmode;
1197         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198                 hns3_warn(hw,
1199                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200                           "configuration is not supported! Ignore these two "
1201                           "parameters: hw_vlan_reject_tagged(%u), "
1202                           "hw_vlan_reject_untagged(%u)",
1203                           txmode->hw_vlan_reject_tagged,
1204                           txmode->hw_vlan_reject_untagged);
1205
1206         /* Apply vlan offload setting */
1207         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1208         ret = hns3_vlan_offload_set(dev, mask);
1209         if (ret) {
1210                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1211                          ret);
1212                 return ret;
1213         }
1214
1215         /*
1216          * If pvid config is not set in rte_eth_conf, driver needn't to set
1217          * VLAN pvid related configuration to hardware.
1218          */
1219         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1220                 return 0;
1221
1222         /* Apply pvid setting */
1223         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224                                  txmode->hw_vlan_insert_pvid);
1225         if (ret)
1226                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1227                          txmode->pvid, ret);
1228
1229         return ret;
1230 }
1231
1232 static int
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234                 unsigned int tso_mss_max)
1235 {
1236         struct hns3_cfg_tso_status_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         uint16_t tso_mss;
1239
1240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241
1242         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1243
1244         tso_mss = 0;
1245         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246                        tso_mss_min);
1247         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1248
1249         tso_mss = 0;
1250         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251                        tso_mss_max);
1252         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253
1254         return hns3_cmd_send(hw, &desc, 1);
1255 }
1256
1257 static int
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259                    uint16_t *allocated_size, bool is_alloc)
1260 {
1261         struct hns3_umv_spc_alc_cmd *req;
1262         struct hns3_cmd_desc desc;
1263         int ret;
1264
1265         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268         req->space_size = rte_cpu_to_le_32(space_size);
1269
1270         ret = hns3_cmd_send(hw, &desc, 1);
1271         if (ret) {
1272                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273                              is_alloc ? "allocate" : "free", ret);
1274                 return ret;
1275         }
1276
1277         if (is_alloc && allocated_size)
1278                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 hns3_init_umv_space(struct hns3_hw *hw)
1285 {
1286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287         struct hns3_pf *pf = &hns->pf;
1288         uint16_t allocated_size = 0;
1289         int ret;
1290
1291         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1292                                  true);
1293         if (ret)
1294                 return ret;
1295
1296         if (allocated_size < pf->wanted_umv_size)
1297                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298                              pf->wanted_umv_size, allocated_size);
1299
1300         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301                                                 pf->wanted_umv_size;
1302         pf->used_umv_size = 0;
1303         return 0;
1304 }
1305
1306 static int
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 {
1309         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310         struct hns3_pf *pf = &hns->pf;
1311         int ret;
1312
1313         if (pf->max_umv_size == 0)
1314                 return 0;
1315
1316         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1317         if (ret)
1318                 return ret;
1319
1320         pf->max_umv_size = 0;
1321
1322         return 0;
1323 }
1324
1325 static bool
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 {
1328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329         struct hns3_pf *pf = &hns->pf;
1330         bool is_full;
1331
1332         is_full = (pf->used_umv_size >= pf->max_umv_size);
1333
1334         return is_full;
1335 }
1336
1337 static void
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 {
1340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341         struct hns3_pf *pf = &hns->pf;
1342
1343         if (is_free) {
1344                 if (pf->used_umv_size > 0)
1345                         pf->used_umv_size--;
1346         } else
1347                 pf->used_umv_size++;
1348 }
1349
1350 static void
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352                       const uint8_t *addr, bool is_mc)
1353 {
1354         const unsigned char *mac_addr = addr;
1355         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356                             ((uint32_t)mac_addr[2] << 16) |
1357                             ((uint32_t)mac_addr[1] << 8) |
1358                             (uint32_t)mac_addr[0];
1359         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360
1361         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362         if (is_mc) {
1363                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1366         }
1367
1368         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1370 }
1371
1372 static int
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374                              uint8_t resp_code,
1375                              enum hns3_mac_vlan_tbl_opcode op)
1376 {
1377         if (cmdq_resp) {
1378                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1379                          cmdq_resp);
1380                 return -EIO;
1381         }
1382
1383         if (op == HNS3_MAC_VLAN_ADD) {
1384                 if (resp_code == 0 || resp_code == 1) {
1385                         return 0;
1386                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387                         hns3_err(hw, "add mac addr failed for uc_overflow");
1388                         return -ENOSPC;
1389                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390                         hns3_err(hw, "add mac addr failed for mc_overflow");
1391                         return -ENOSPC;
1392                 }
1393
1394                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1395                          resp_code);
1396                 return -EIO;
1397         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398                 if (resp_code == 0) {
1399                         return 0;
1400                 } else if (resp_code == 1) {
1401                         hns3_dbg(hw, "remove mac addr failed for miss");
1402                         return -ENOENT;
1403                 }
1404
1405                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1406                          resp_code);
1407                 return -EIO;
1408         } else if (op == HNS3_MAC_VLAN_LKUP) {
1409                 if (resp_code == 0) {
1410                         return 0;
1411                 } else if (resp_code == 1) {
1412                         hns3_dbg(hw, "lookup mac addr failed for miss");
1413                         return -ENOENT;
1414                 }
1415
1416                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1417                          resp_code);
1418                 return -EIO;
1419         }
1420
1421         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1422                  op);
1423
1424         return -EINVAL;
1425 }
1426
1427 static int
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1430                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1431 {
1432         uint8_t resp_code;
1433         uint16_t retval;
1434         int ret;
1435         int i;
1436
1437         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1438                 for (i = 0; i < desc_num - 1; i++) {
1439                         hns3_cmd_setup_basic_desc(&desc[i],
1440                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1441                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1442                         if (i == 0)
1443                                 memcpy(desc[i].data, req,
1444                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1445                 }
1446                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448         } else {
1449                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1450                                           true);
1451                 memcpy(desc[0].data, req,
1452                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1453         }
1454         ret = hns3_cmd_send(hw, desc, desc_num);
1455         if (ret) {
1456                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1457                          ret);
1458                 return ret;
1459         }
1460         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1461         retval = rte_le_to_cpu_16(desc[0].retval);
1462
1463         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464                                             HNS3_MAC_VLAN_LKUP);
1465 }
1466
1467 static int
1468 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1469                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1470                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1471 {
1472         uint8_t resp_code;
1473         uint16_t retval;
1474         int cfg_status;
1475         int ret;
1476         int i;
1477
1478         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1479                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc->data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, desc, desc_num);
1483                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc->retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 for (i = 0; i < desc_num; i++) {
1490                         hns3_cmd_reuse_desc(&desc[i], false);
1491                         if (i == desc_num - 1)
1492                                 desc[i].flag &=
1493                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494                         else
1495                                 desc[i].flag |=
1496                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1497                 }
1498                 memcpy(desc[0].data, req,
1499                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1500                 desc[0].retval = 0;
1501                 ret = hns3_cmd_send(hw, desc, desc_num);
1502                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1503                 retval = rte_le_to_cpu_16(desc[0].retval);
1504
1505                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1506                                                           HNS3_MAC_VLAN_ADD);
1507         }
1508
1509         if (ret) {
1510                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1511                 return ret;
1512         }
1513
1514         return cfg_status;
1515 }
1516
1517 static int
1518 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1519                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1520 {
1521         struct hns3_cmd_desc desc;
1522         uint8_t resp_code;
1523         uint16_t retval;
1524         int ret;
1525
1526         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1527
1528         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1529
1530         ret = hns3_cmd_send(hw, &desc, 1);
1531         if (ret) {
1532                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1533                 return ret;
1534         }
1535         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1536         retval = rte_le_to_cpu_16(desc.retval);
1537
1538         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1539                                             HNS3_MAC_VLAN_REMOVE);
1540 }
1541
1542 static int
1543 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1544 {
1545         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1546         struct hns3_mac_vlan_tbl_entry_cmd req;
1547         struct hns3_pf *pf = &hns->pf;
1548         struct hns3_cmd_desc desc;
1549         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1550         uint16_t egress_port = 0;
1551         uint8_t vf_id;
1552         int ret;
1553
1554         /* check if mac addr is valid */
1555         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1556                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1557                                       mac_addr);
1558                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1559                          mac_str);
1560                 return -EINVAL;
1561         }
1562
1563         memset(&req, 0, sizeof(req));
1564
1565         /*
1566          * In current version VF is not supported when PF is driven by DPDK
1567          * driver, just need to configure parameters for PF vport.
1568          */
1569         vf_id = HNS3_PF_FUNC_ID;
1570         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1571                        HNS3_MAC_EPORT_VFID_S, vf_id);
1572
1573         req.egress_port = rte_cpu_to_le_16(egress_port);
1574
1575         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1576
1577         /*
1578          * Lookup the mac address in the mac_vlan table, and add
1579          * it if the entry is inexistent. Repeated unicast entry
1580          * is not allowed in the mac vlan table.
1581          */
1582         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1583                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1584         if (ret == -ENOENT) {
1585                 if (!hns3_is_umv_space_full(hw)) {
1586                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1587                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1588                         if (!ret)
1589                                 hns3_update_umv_space(hw, false);
1590                         return ret;
1591                 }
1592
1593                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1594
1595                 return -ENOSPC;
1596         }
1597
1598         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1599
1600         /* check if we just hit the duplicate */
1601         if (ret == 0) {
1602                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1603                 return 0;
1604         }
1605
1606         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1607                  mac_str);
1608
1609         return ret;
1610 }
1611
1612 bool
1613 hns3_find_duplicate_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mc_addr)
1614 {
1615         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1616         struct rte_ether_addr *addr;
1617         int i;
1618
1619         for (i = 0; i < hw->mc_addrs_num; i++) {
1620                 addr = &hw->mc_addrs[i];
1621                 /* Check if there are duplicate addresses in mc_addrs[] */
1622                 if (rte_is_same_ether_addr(addr, mc_addr)) {
1623                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1624                                                addr);
1625                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1626                                  "(%s) is added by the set_mc_mac_addr_list "
1627                                  "API", mac_str);
1628                         return true;
1629                 }
1630         }
1631
1632         return false;
1633 }
1634
1635 static int
1636 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1637                   __rte_unused uint32_t idx, __rte_unused uint32_t pool)
1638 {
1639         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641         int ret;
1642
1643         rte_spinlock_lock(&hw->lock);
1644
1645         /*
1646          * In hns3 network engine adding UC and MC mac address with different
1647          * commands with firmware. We need to determine whether the input
1648          * address is a UC or a MC address to call different commands.
1649          * By the way, it is recommended calling the API function named
1650          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1651          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1652          * may affect the specifications of UC mac addresses.
1653          */
1654         if (rte_is_multicast_ether_addr(mac_addr)) {
1655                 if (hns3_find_duplicate_mc_addr(hw, mac_addr)) {
1656                         rte_spinlock_unlock(&hw->lock);
1657                         return -EINVAL;
1658                 }
1659                 ret = hns3_add_mc_mac_addr(hw, mac_addr);
1660         } else {
1661                 ret = hns3_add_uc_mac_addr(hw, mac_addr);
1662         }
1663         if (ret) {
1664                 rte_spinlock_unlock(&hw->lock);
1665                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1666                                       mac_addr);
1667                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1668                          ret);
1669                 return ret;
1670         }
1671
1672         rte_spinlock_unlock(&hw->lock);
1673
1674         return ret;
1675 }
1676
1677 static int
1678 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1679 {
1680         struct hns3_mac_vlan_tbl_entry_cmd req;
1681         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1682         int ret;
1683
1684         /* check if mac addr is valid */
1685         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1686                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1687                                       mac_addr);
1688                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1689                          mac_str);
1690                 return -EINVAL;
1691         }
1692
1693         memset(&req, 0, sizeof(req));
1694         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1695         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1696         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1697         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1698                 return 0;
1699         else if (ret == 0)
1700                 hns3_update_umv_space(hw, true);
1701
1702         return ret;
1703 }
1704
1705 static void
1706 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1707 {
1708         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         /* index will be checked by upper level rte interface */
1710         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1711         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1712         int ret;
1713
1714         rte_spinlock_lock(&hw->lock);
1715
1716         if (rte_is_multicast_ether_addr(mac_addr))
1717                 ret = hns3_remove_mc_mac_addr(hw, mac_addr);
1718         else
1719                 ret = hns3_remove_uc_mac_addr(hw, mac_addr);
1720         rte_spinlock_unlock(&hw->lock);
1721         if (ret) {
1722                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1723                                       mac_addr);
1724                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1725                          ret);
1726         }
1727 }
1728
1729 static int
1730 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1731                           struct rte_ether_addr *mac_addr)
1732 {
1733         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734         struct rte_ether_addr *oaddr;
1735         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1736         int ret, ret_val;
1737
1738         rte_spinlock_lock(&hw->lock);
1739         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1740         ret = hns3_remove_uc_mac_addr(hw, oaddr);
1741         if (ret) {
1742                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1743                                       oaddr);
1744                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1745                           mac_str, ret);
1746
1747                 rte_spinlock_unlock(&hw->lock);
1748                 return ret;
1749         }
1750
1751         ret = hns3_add_uc_mac_addr(hw, mac_addr);
1752         if (ret) {
1753                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1754                                       mac_addr);
1755                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1756                 goto err_add_uc_addr;
1757         }
1758
1759         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1760         if (ret) {
1761                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1762                 goto err_pause_addr_cfg;
1763         }
1764
1765         rte_ether_addr_copy(mac_addr,
1766                             (struct rte_ether_addr *)hw->mac.mac_addr);
1767         rte_spinlock_unlock(&hw->lock);
1768
1769         return 0;
1770
1771 err_pause_addr_cfg:
1772         ret_val = hns3_remove_uc_mac_addr(hw, mac_addr);
1773         if (ret_val) {
1774                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1775                                       mac_addr);
1776                 hns3_warn(hw,
1777                           "Failed to roll back to del setted mac addr(%s): %d",
1778                           mac_str, ret_val);
1779         }
1780
1781 err_add_uc_addr:
1782         ret_val = hns3_add_uc_mac_addr(hw, oaddr);
1783         if (ret_val) {
1784                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1785                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1786                                   mac_str, ret_val);
1787         }
1788         rte_spinlock_unlock(&hw->lock);
1789
1790         return ret;
1791 }
1792
1793 static int
1794 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1795 {
1796         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1797         struct hns3_hw *hw = &hns->hw;
1798         struct rte_ether_addr *addr;
1799         int err = 0;
1800         int ret;
1801         int i;
1802
1803         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1804                 addr = &hw->data->mac_addrs[i];
1805                 if (rte_is_zero_ether_addr(addr))
1806                         continue;
1807                 if (rte_is_multicast_ether_addr(addr))
1808                         ret = del ? hns3_remove_mc_mac_addr(hw, addr) :
1809                               hns3_add_mc_mac_addr(hw, addr);
1810                 else
1811                         ret = del ? hns3_remove_uc_mac_addr(hw, addr) :
1812                               hns3_add_uc_mac_addr(hw, addr);
1813
1814                 if (ret) {
1815                         err = ret;
1816                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1817                                               addr);
1818                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1819                                  "ret = %d.", del ? "remove" : "restore",
1820                                  mac_str, i, ret);
1821                 }
1822         }
1823         return err;
1824 }
1825
1826 static void
1827 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1828 {
1829 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1830         uint8_t word_num;
1831         uint8_t bit_num;
1832
1833         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1834                 word_num = vfid / 32;
1835                 bit_num = vfid % 32;
1836                 if (clr)
1837                         desc[1].data[word_num] &=
1838                             rte_cpu_to_le_32(~(1UL << bit_num));
1839                 else
1840                         desc[1].data[word_num] |=
1841                             rte_cpu_to_le_32(1UL << bit_num);
1842         } else {
1843                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1844                 bit_num = vfid % 32;
1845                 if (clr)
1846                         desc[2].data[word_num] &=
1847                             rte_cpu_to_le_32(~(1UL << bit_num));
1848                 else
1849                         desc[2].data[word_num] |=
1850                             rte_cpu_to_le_32(1UL << bit_num);
1851         }
1852 }
1853
1854 static int
1855 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1856 {
1857         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1858         struct hns3_mac_vlan_tbl_entry_cmd req;
1859         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1860         uint8_t vf_id;
1861         int ret;
1862
1863         /* Check if mac addr is valid */
1864         if (!rte_is_multicast_ether_addr(mac_addr)) {
1865                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1866                                       mac_addr);
1867                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1868                          mac_str);
1869                 return -EINVAL;
1870         }
1871
1872         memset(&req, 0, sizeof(req));
1873         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1874         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1875         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1876                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1877         if (ret) {
1878                 /* This mac addr do not exist, add new entry for it */
1879                 memset(desc[0].data, 0, sizeof(desc[0].data));
1880                 memset(desc[1].data, 0, sizeof(desc[0].data));
1881                 memset(desc[2].data, 0, sizeof(desc[0].data));
1882         }
1883
1884         /*
1885          * In current version VF is not supported when PF is driven by DPDK
1886          * driver, just need to configure parameters for PF vport.
1887          */
1888         vf_id = HNS3_PF_FUNC_ID;
1889         hns3_update_desc_vfid(desc, vf_id, false);
1890         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1891                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1892         if (ret) {
1893                 if (ret == -ENOSPC)
1894                         hns3_err(hw, "mc mac vlan table is full");
1895                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1896                                       mac_addr);
1897                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1898         }
1899
1900         return ret;
1901 }
1902
1903 static int
1904 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1905 {
1906         struct hns3_mac_vlan_tbl_entry_cmd req;
1907         struct hns3_cmd_desc desc[3];
1908         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1909         uint8_t vf_id;
1910         int ret;
1911
1912         /* Check if mac addr is valid */
1913         if (!rte_is_multicast_ether_addr(mac_addr)) {
1914                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1915                                       mac_addr);
1916                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1917                          mac_str);
1918                 return -EINVAL;
1919         }
1920
1921         memset(&req, 0, sizeof(req));
1922         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1923         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1924         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1925                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1926         if (ret == 0) {
1927                 /*
1928                  * This mac addr exist, remove this handle's VFID for it.
1929                  * In current version VF is not supported when PF is driven by
1930                  * DPDK driver, just need to configure parameters for PF vport.
1931                  */
1932                 vf_id = HNS3_PF_FUNC_ID;
1933                 hns3_update_desc_vfid(desc, vf_id, true);
1934
1935                 /* All the vfid is zero, so need to delete this entry */
1936                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1937         } else if (ret == -ENOENT) {
1938                 /* This mac addr doesn't exist. */
1939                 return 0;
1940         }
1941
1942         if (ret) {
1943                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1944                                       mac_addr);
1945                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1946         }
1947
1948         return ret;
1949 }
1950
1951 static int
1952 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1953                            struct rte_ether_addr *mc_addr_set,
1954                            uint32_t nb_mc_addr)
1955 {
1956         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1957         struct rte_ether_addr *addr;
1958         uint32_t i;
1959         uint32_t j;
1960
1961         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1962                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1963                          "invalid. valid range: 0~%d",
1964                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1965                 return -EINVAL;
1966         }
1967
1968         /* Check if input mac addresses are valid */
1969         for (i = 0; i < nb_mc_addr; i++) {
1970                 addr = &mc_addr_set[i];
1971                 if (!rte_is_multicast_ether_addr(addr)) {
1972                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1973                                               addr);
1974                         hns3_err(hw,
1975                                  "failed to set mc mac addr, addr(%s) invalid.",
1976                                  mac_str);
1977                         return -EINVAL;
1978                 }
1979
1980                 /* Check if there are duplicate addresses */
1981                 for (j = i + 1; j < nb_mc_addr; j++) {
1982                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1983                                 hns3_ether_format_addr(mac_str,
1984                                                       RTE_ETHER_ADDR_FMT_SIZE,
1985                                                       addr);
1986                                 hns3_err(hw, "failed to set mc mac addr, "
1987                                          "addrs invalid. two same addrs(%s).",
1988                                          mac_str);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 /*
1994                  * Check if there are duplicate addresses between mac_addrs
1995                  * and mc_addr_set
1996                  */
1997                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1998                         if (rte_is_same_ether_addr(addr,
1999                                                    &hw->data->mac_addrs[j])) {
2000                                 hns3_ether_format_addr(mac_str,
2001                                                       RTE_ETHER_ADDR_FMT_SIZE,
2002                                                       addr);
2003                                 hns3_err(hw, "failed to set mc mac addr, "
2004                                          "addrs invalid. addrs(%s) has already "
2005                                          "configured in mac_addr add API",
2006                                          mac_str);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010         }
2011
2012         return 0;
2013 }
2014
2015 static void
2016 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2017                            struct rte_ether_addr *mc_addr_set,
2018                            int mc_addr_num,
2019                            struct rte_ether_addr *reserved_addr_list,
2020                            int *reserved_addr_num,
2021                            struct rte_ether_addr *add_addr_list,
2022                            int *add_addr_num,
2023                            struct rte_ether_addr *rm_addr_list,
2024                            int *rm_addr_num)
2025 {
2026         struct rte_ether_addr *addr;
2027         int current_addr_num;
2028         int reserved_num = 0;
2029         int add_num = 0;
2030         int rm_num = 0;
2031         int num;
2032         int i;
2033         int j;
2034         bool same_addr;
2035
2036         /* Calculate the mc mac address list that should be removed */
2037         current_addr_num = hw->mc_addrs_num;
2038         for (i = 0; i < current_addr_num; i++) {
2039                 addr = &hw->mc_addrs[i];
2040                 same_addr = false;
2041                 for (j = 0; j < mc_addr_num; j++) {
2042                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2043                                 same_addr = true;
2044                                 break;
2045                         }
2046                 }
2047
2048                 if (!same_addr) {
2049                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2050                         rm_num++;
2051                 } else {
2052                         rte_ether_addr_copy(addr,
2053                                             &reserved_addr_list[reserved_num]);
2054                         reserved_num++;
2055                 }
2056         }
2057
2058         /* Calculate the mc mac address list that should be added */
2059         for (i = 0; i < mc_addr_num; i++) {
2060                 addr = &mc_addr_set[i];
2061                 same_addr = false;
2062                 for (j = 0; j < current_addr_num; j++) {
2063                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2064                                 same_addr = true;
2065                                 break;
2066                         }
2067                 }
2068
2069                 if (!same_addr) {
2070                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2071                         add_num++;
2072                 }
2073         }
2074
2075         /* Reorder the mc mac address list maintained by driver */
2076         for (i = 0; i < reserved_num; i++)
2077                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2078
2079         for (i = 0; i < rm_num; i++) {
2080                 num = reserved_num + i;
2081                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2082         }
2083
2084         *reserved_addr_num = reserved_num;
2085         *add_addr_num = add_num;
2086         *rm_addr_num = rm_num;
2087 }
2088
2089 static int
2090 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2091                           struct rte_ether_addr *mc_addr_set,
2092                           uint32_t nb_mc_addr)
2093 {
2094         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2096         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2097         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2098         struct rte_ether_addr *addr;
2099         int reserved_addr_num;
2100         int add_addr_num;
2101         int rm_addr_num;
2102         int mc_addr_num;
2103         int num;
2104         int ret;
2105         int i;
2106
2107         /* Check if input parameters are valid */
2108         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2109         if (ret)
2110                 return ret;
2111
2112         rte_spinlock_lock(&hw->lock);
2113
2114         /*
2115          * Calculate the mc mac address lists those should be removed and be
2116          * added, Reorder the mc mac address list maintained by driver.
2117          */
2118         mc_addr_num = (int)nb_mc_addr;
2119         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2120                                    reserved_addr_list, &reserved_addr_num,
2121                                    add_addr_list, &add_addr_num,
2122                                    rm_addr_list, &rm_addr_num);
2123
2124         /* Remove mc mac addresses */
2125         for (i = 0; i < rm_addr_num; i++) {
2126                 num = rm_addr_num - i - 1;
2127                 addr = &rm_addr_list[num];
2128                 ret = hns3_remove_mc_mac_addr(hw, addr);
2129                 if (ret) {
2130                         rte_spinlock_unlock(&hw->lock);
2131                         return ret;
2132                 }
2133                 hw->mc_addrs_num--;
2134         }
2135
2136         /* Add mc mac addresses */
2137         for (i = 0; i < add_addr_num; i++) {
2138                 addr = &add_addr_list[i];
2139                 ret = hns3_add_mc_mac_addr(hw, addr);
2140                 if (ret) {
2141                         rte_spinlock_unlock(&hw->lock);
2142                         return ret;
2143                 }
2144
2145                 num = reserved_addr_num + i;
2146                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2147                 hw->mc_addrs_num++;
2148         }
2149         rte_spinlock_unlock(&hw->lock);
2150
2151         return 0;
2152 }
2153
2154 static int
2155 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2156 {
2157         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2158         struct hns3_hw *hw = &hns->hw;
2159         struct rte_ether_addr *addr;
2160         int err = 0;
2161         int ret;
2162         int i;
2163
2164         for (i = 0; i < hw->mc_addrs_num; i++) {
2165                 addr = &hw->mc_addrs[i];
2166                 if (!rte_is_multicast_ether_addr(addr))
2167                         continue;
2168                 if (del)
2169                         ret = hns3_remove_mc_mac_addr(hw, addr);
2170                 else
2171                         ret = hns3_add_mc_mac_addr(hw, addr);
2172                 if (ret) {
2173                         err = ret;
2174                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2175                                               addr);
2176                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2177                                  del ? "Remove" : "Restore", mac_str, ret);
2178                 }
2179         }
2180         return err;
2181 }
2182
2183 static int
2184 hns3_check_mq_mode(struct rte_eth_dev *dev)
2185 {
2186         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2187         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2188         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2190         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2191         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2192         uint8_t num_tc;
2193         int max_tc = 0;
2194         int i;
2195
2196         if ((rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
2197             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
2198              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
2199                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2200                          rx_mq_mode, tx_mq_mode);
2201                 return -EOPNOTSUPP;
2202         }
2203
2204         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2205         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2206         if (rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2207                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2208                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2209                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2210                         return -EINVAL;
2211                 }
2212
2213                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2214                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2215                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
2216                                  "nb_tcs(%d) != %d or %d in rx direction.",
2217                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2218                         return -EINVAL;
2219                 }
2220
2221                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2222                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2223                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2224                         return -EINVAL;
2225                 }
2226
2227                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2228                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2229                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2230                                          "is not equal to one in tx direction.",
2231                                          i, dcb_rx_conf->dcb_tc[i]);
2232                                 return -EINVAL;
2233                         }
2234                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2235                                 max_tc = dcb_rx_conf->dcb_tc[i];
2236                 }
2237
2238                 num_tc = max_tc + 1;
2239                 if (num_tc > dcb_rx_conf->nb_tcs) {
2240                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2241                                  num_tc, dcb_rx_conf->nb_tcs);
2242                         return -EINVAL;
2243                 }
2244         }
2245
2246         return 0;
2247 }
2248
2249 static int
2250 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2251                            enum hns3_ring_type queue_type, uint16_t queue_id)
2252 {
2253         struct hns3_cmd_desc desc;
2254         struct hns3_ctrl_vector_chain_cmd *req =
2255                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2256         enum hns3_opcode_type op;
2257         uint16_t tqp_type_and_id = 0;
2258         uint16_t type;
2259         uint16_t gl;
2260         int ret;
2261
2262         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2263         hns3_cmd_setup_basic_desc(&desc, op, false);
2264         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2265                                               HNS3_TQP_INT_ID_L_S);
2266         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2267                                               HNS3_TQP_INT_ID_H_S);
2268
2269         if (queue_type == HNS3_RING_TYPE_RX)
2270                 gl = HNS3_RING_GL_RX;
2271         else
2272                 gl = HNS3_RING_GL_TX;
2273
2274         type = queue_type;
2275
2276         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2277                        type);
2278         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2279         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2280                        gl);
2281         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2282         req->int_cause_num = 1;
2283         ret = hns3_cmd_send(hw, &desc, 1);
2284         if (ret) {
2285                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2286                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2287                 return ret;
2288         }
2289
2290         return 0;
2291 }
2292
2293 static int
2294 hns3_init_ring_with_vector(struct hns3_hw *hw)
2295 {
2296         uint16_t vec;
2297         int ret;
2298         int i;
2299
2300         /*
2301          * In hns3 network engine, vector 0 is always the misc interrupt of this
2302          * function, vector 1~N can be used respectively for the queues of the
2303          * function. Tx and Rx queues with the same number share the interrupt
2304          * vector. In the initialization clearing the all hardware mapping
2305          * relationship configurations between queues and interrupt vectors is
2306          * needed, so some error caused by the residual configurations, such as
2307          * the unexpected Tx interrupt, can be avoid.
2308          */
2309         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2310         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2311                 vec = vec - 1; /* the last interrupt is reserved */
2312         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2313         for (i = 0; i < hw->intr_tqps_num; i++) {
2314                 /*
2315                  * Set gap limiter/rate limiter/quanity limiter algorithm
2316                  * configuration for interrupt coalesce of queue's interrupt.
2317                  */
2318                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2319                                        HNS3_TQP_INTR_GL_DEFAULT);
2320                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2321                                        HNS3_TQP_INTR_GL_DEFAULT);
2322                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2323                 /*
2324                  * QL(quantity limiter) is not used currently, just set 0 to
2325                  * close it.
2326                  */
2327                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2328
2329                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2330                                                  HNS3_RING_TYPE_TX, i);
2331                 if (ret) {
2332                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2333                                           "vector: %u, ret=%d", i, vec, ret);
2334                         return ret;
2335                 }
2336
2337                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2338                                                  HNS3_RING_TYPE_RX, i);
2339                 if (ret) {
2340                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2341                                           "vector: %u, ret=%d", i, vec, ret);
2342                         return ret;
2343                 }
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int
2350 hns3_setup_dcb(struct rte_eth_dev *dev)
2351 {
2352         struct hns3_adapter *hns = dev->data->dev_private;
2353         struct hns3_hw *hw = &hns->hw;
2354         int ret;
2355
2356         if (!hns3_dev_get_support(hw, DCB)) {
2357                 hns3_err(hw, "this port does not support dcb configurations.");
2358                 return -EOPNOTSUPP;
2359         }
2360
2361         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2362                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2363                 return -EOPNOTSUPP;
2364         }
2365
2366         ret = hns3_dcb_configure(hns);
2367         if (ret)
2368                 hns3_err(hw, "failed to config dcb: %d", ret);
2369
2370         return ret;
2371 }
2372
2373 static int
2374 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2375 {
2376         int ret;
2377
2378         /*
2379          * Some hardware doesn't support auto-negotiation, but users may not
2380          * configure link_speeds (default 0), which means auto-negotiation.
2381          * In this case, it should return success.
2382          */
2383         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
2384             hw->mac.support_autoneg == 0)
2385                 return 0;
2386
2387         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
2388                 ret = hns3_check_port_speed(hw, link_speeds);
2389                 if (ret)
2390                         return ret;
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int
2397 hns3_check_dev_conf(struct rte_eth_dev *dev)
2398 {
2399         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         struct rte_eth_conf *conf = &dev->data->dev_conf;
2401         int ret;
2402
2403         ret = hns3_check_mq_mode(dev);
2404         if (ret)
2405                 return ret;
2406
2407         return hns3_check_link_speed(hw, conf->link_speeds);
2408 }
2409
2410 static int
2411 hns3_dev_configure(struct rte_eth_dev *dev)
2412 {
2413         struct hns3_adapter *hns = dev->data->dev_private;
2414         struct rte_eth_conf *conf = &dev->data->dev_conf;
2415         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2416         struct hns3_hw *hw = &hns->hw;
2417         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2418         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2419         struct rte_eth_rss_conf rss_conf;
2420         bool gro_en;
2421         int ret;
2422
2423         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2424
2425         /*
2426          * Some versions of hardware network engine does not support
2427          * individually enable/disable/reset the Tx or Rx queue. These devices
2428          * must enable/disable/reset Tx and Rx queues at the same time. When the
2429          * numbers of Tx queues allocated by upper applications are not equal to
2430          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2431          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2432          * work as usual. But these fake queues are imperceptible, and can not
2433          * be used by upper applications.
2434          */
2435         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2436         if (ret) {
2437                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2438                 hw->cfg_max_queues = 0;
2439                 return ret;
2440         }
2441
2442         hw->adapter_state = HNS3_NIC_CONFIGURING;
2443         ret = hns3_check_dev_conf(dev);
2444         if (ret)
2445                 goto cfg_err;
2446
2447         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2448                 ret = hns3_setup_dcb(dev);
2449                 if (ret)
2450                         goto cfg_err;
2451         }
2452
2453         /* When RSS is not configured, redirect the packet queue 0 */
2454         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2455                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2456                 rss_conf = conf->rx_adv_conf.rss_conf;
2457                 hw->rss_dis_flag = false;
2458                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2459                 if (ret)
2460                         goto cfg_err;
2461         }
2462
2463         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2464         if (ret != 0)
2465                 goto cfg_err;
2466
2467         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2468         if (ret)
2469                 goto cfg_err;
2470
2471         ret = hns3_dev_configure_vlan(dev);
2472         if (ret)
2473                 goto cfg_err;
2474
2475         /* config hardware GRO */
2476         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2477         ret = hns3_config_gro(hw, gro_en);
2478         if (ret)
2479                 goto cfg_err;
2480
2481         hns3_init_rx_ptype_tble(dev);
2482         hw->adapter_state = HNS3_NIC_CONFIGURED;
2483
2484         return 0;
2485
2486 cfg_err:
2487         hw->cfg_max_queues = 0;
2488         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2489         hw->adapter_state = HNS3_NIC_INITIALIZED;
2490
2491         return ret;
2492 }
2493
2494 static int
2495 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2496 {
2497         struct hns3_config_max_frm_size_cmd *req;
2498         struct hns3_cmd_desc desc;
2499
2500         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2501
2502         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2503         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2504         req->min_frm_size = RTE_ETHER_MIN_LEN;
2505
2506         return hns3_cmd_send(hw, &desc, 1);
2507 }
2508
2509 static int
2510 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2511 {
2512         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2513         uint16_t original_mps = hns->pf.mps;
2514         int err;
2515         int ret;
2516
2517         ret = hns3_set_mac_mtu(hw, mps);
2518         if (ret) {
2519                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2520                 return ret;
2521         }
2522
2523         hns->pf.mps = mps;
2524         ret = hns3_buffer_alloc(hw);
2525         if (ret) {
2526                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2527                 goto rollback;
2528         }
2529
2530         return 0;
2531
2532 rollback:
2533         err = hns3_set_mac_mtu(hw, original_mps);
2534         if (err) {
2535                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2536                 return ret;
2537         }
2538         hns->pf.mps = original_mps;
2539
2540         return ret;
2541 }
2542
2543 static int
2544 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2545 {
2546         struct hns3_adapter *hns = dev->data->dev_private;
2547         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2548         struct hns3_hw *hw = &hns->hw;
2549         int ret;
2550
2551         if (dev->data->dev_started) {
2552                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2553                          "before configuration", dev->data->port_id);
2554                 return -EBUSY;
2555         }
2556
2557         rte_spinlock_lock(&hw->lock);
2558         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2559
2560         /*
2561          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2562          * assign to "uint16_t" type variable.
2563          */
2564         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2565         if (ret) {
2566                 rte_spinlock_unlock(&hw->lock);
2567                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2568                          dev->data->port_id, mtu, ret);
2569                 return ret;
2570         }
2571
2572         rte_spinlock_unlock(&hw->lock);
2573
2574         return 0;
2575 }
2576
2577 static uint32_t
2578 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2579 {
2580         uint32_t speed_capa = 0;
2581
2582         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2583                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2584         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2585                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2586         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2587                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2588         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2589                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2590         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2591                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2592
2593         return speed_capa;
2594 }
2595
2596 static uint32_t
2597 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2598 {
2599         uint32_t speed_capa = 0;
2600
2601         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2602                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2603         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2604                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2605         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2606                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2607         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2608                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2609         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2610                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2611         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2612                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2613         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2614                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2615
2616         return speed_capa;
2617 }
2618
2619 static uint32_t
2620 hns3_get_speed_capa(struct hns3_hw *hw)
2621 {
2622         struct hns3_mac *mac = &hw->mac;
2623         uint32_t speed_capa;
2624
2625         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2626                 speed_capa =
2627                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2628         else
2629                 speed_capa =
2630                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2631
2632         if (mac->support_autoneg == 0)
2633                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2634
2635         return speed_capa;
2636 }
2637
2638 int
2639 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2640 {
2641         struct hns3_adapter *hns = eth_dev->data->dev_private;
2642         struct hns3_hw *hw = &hns->hw;
2643         uint16_t queue_num = hw->tqps_num;
2644
2645         /*
2646          * In interrupt mode, 'max_rx_queues' is set based on the number of
2647          * MSI-X interrupt resources of the hardware.
2648          */
2649         if (hw->data->dev_conf.intr_conf.rxq == 1)
2650                 queue_num = hw->intr_tqps_num;
2651
2652         info->max_rx_queues = queue_num;
2653         info->max_tx_queues = hw->tqps_num;
2654         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2655         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2656         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2657         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2658         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2659         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
2660                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
2661                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
2662                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
2663                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2664                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
2665                                  RTE_ETH_RX_OFFLOAD_KEEP_CRC |
2666                                  RTE_ETH_RX_OFFLOAD_SCATTER |
2667                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
2668                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
2669                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
2670                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
2671         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2672                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
2673                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
2674                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
2675                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
2676                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
2677                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
2678                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
2679                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
2680                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
2681                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
2682                                  hns3_txvlan_cap_get(hw));
2683
2684         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
2685                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
2686
2687         if (hns3_dev_get_support(hw, INDEP_TXRX))
2688                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2689                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2690
2691         if (hns3_dev_get_support(hw, PTP))
2692                 info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
2693
2694         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2695                 .nb_max = HNS3_MAX_RING_DESC,
2696                 .nb_min = HNS3_MIN_RING_DESC,
2697                 .nb_align = HNS3_ALIGN_RING_DESC,
2698         };
2699
2700         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2701                 .nb_max = HNS3_MAX_RING_DESC,
2702                 .nb_min = HNS3_MIN_RING_DESC,
2703                 .nb_align = HNS3_ALIGN_RING_DESC,
2704                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2705                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2706         };
2707
2708         info->speed_capa = hns3_get_speed_capa(hw);
2709         info->default_rxconf = (struct rte_eth_rxconf) {
2710                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2711                 /*
2712                  * If there are no available Rx buffer descriptors, incoming
2713                  * packets are always dropped by hardware based on hns3 network
2714                  * engine.
2715                  */
2716                 .rx_drop_en = 1,
2717                 .offloads = 0,
2718         };
2719         info->default_txconf = (struct rte_eth_txconf) {
2720                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2721                 .offloads = 0,
2722         };
2723
2724         info->reta_size = hw->rss_ind_tbl_size;
2725         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2726         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2727
2728         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2729         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2730         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2731         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2732         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2733         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2734
2735         return 0;
2736 }
2737
2738 static int
2739 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2740                     size_t fw_size)
2741 {
2742         struct hns3_adapter *hns = eth_dev->data->dev_private;
2743         struct hns3_hw *hw = &hns->hw;
2744         uint32_t version = hw->fw_version;
2745         int ret;
2746
2747         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2748                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2749                                       HNS3_FW_VERSION_BYTE3_S),
2750                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2751                                       HNS3_FW_VERSION_BYTE2_S),
2752                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2753                                       HNS3_FW_VERSION_BYTE1_S),
2754                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2755                                       HNS3_FW_VERSION_BYTE0_S));
2756         if (ret < 0)
2757                 return -EINVAL;
2758
2759         ret += 1; /* add the size of '\0' */
2760         if (fw_size < (size_t)ret)
2761                 return ret;
2762         else
2763                 return 0;
2764 }
2765
2766 static int
2767 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2768 {
2769         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2770         int ret;
2771
2772         (void)hns3_update_link_status(hw);
2773
2774         ret = hns3_update_link_info(eth_dev);
2775         if (ret)
2776                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2777
2778         return ret;
2779 }
2780
2781 static void
2782 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2783                       struct rte_eth_link *new_link)
2784 {
2785         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2786         struct hns3_mac *mac = &hw->mac;
2787
2788         switch (mac->link_speed) {
2789         case RTE_ETH_SPEED_NUM_10M:
2790         case RTE_ETH_SPEED_NUM_100M:
2791         case RTE_ETH_SPEED_NUM_1G:
2792         case RTE_ETH_SPEED_NUM_10G:
2793         case RTE_ETH_SPEED_NUM_25G:
2794         case RTE_ETH_SPEED_NUM_40G:
2795         case RTE_ETH_SPEED_NUM_50G:
2796         case RTE_ETH_SPEED_NUM_100G:
2797         case RTE_ETH_SPEED_NUM_200G:
2798                 if (mac->link_status)
2799                         new_link->link_speed = mac->link_speed;
2800                 break;
2801         default:
2802                 if (mac->link_status)
2803                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2804                 break;
2805         }
2806
2807         if (!mac->link_status)
2808                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2809
2810         new_link->link_duplex = mac->link_duplex;
2811         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2812         new_link->link_autoneg = mac->link_autoneg;
2813 }
2814
2815 static int
2816 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2817 {
2818 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2819 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2820
2821         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2822         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2823         struct hns3_mac *mac = &hw->mac;
2824         struct rte_eth_link new_link;
2825         int ret;
2826
2827         /* When port is stopped, report link down. */
2828         if (eth_dev->data->dev_started == 0) {
2829                 new_link.link_autoneg = mac->link_autoneg;
2830                 new_link.link_duplex = mac->link_duplex;
2831                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2832                 new_link.link_status = RTE_ETH_LINK_DOWN;
2833                 goto out;
2834         }
2835
2836         do {
2837                 ret = hns3_update_port_link_info(eth_dev);
2838                 if (ret) {
2839                         hns3_err(hw, "failed to get port link info, ret = %d.",
2840                                  ret);
2841                         break;
2842                 }
2843
2844                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2845                         break;
2846
2847                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2848         } while (retry_cnt--);
2849
2850         memset(&new_link, 0, sizeof(new_link));
2851         hns3_setup_linkstatus(eth_dev, &new_link);
2852
2853 out:
2854         return rte_eth_linkstatus_set(eth_dev, &new_link);
2855 }
2856
2857 static int
2858 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2859 {
2860         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         int ret;
2862
2863         /*
2864          * The "tx_pkt_burst" will be restored. But the secondary process does
2865          * not support the mechanism for notifying the primary process.
2866          */
2867         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2868                 hns3_err(hw, "secondary process does not support to set link up.");
2869                 return -ENOTSUP;
2870         }
2871
2872         /*
2873          * If device isn't started Rx/Tx function is still disabled, setting
2874          * link up is not allowed. But it is probably better to return success
2875          * to reduce the impact on the upper layer.
2876          */
2877         if (hw->adapter_state != HNS3_NIC_STARTED) {
2878                 hns3_info(hw, "device isn't started, can't set link up.");
2879                 return 0;
2880         }
2881
2882         if (!hw->set_link_down)
2883                 return 0;
2884
2885         rte_spinlock_lock(&hw->lock);
2886         ret = hns3_cfg_mac_mode(hw, true);
2887         if (ret) {
2888                 rte_spinlock_unlock(&hw->lock);
2889                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2890                 return ret;
2891         }
2892
2893         hw->set_link_down = false;
2894         hns3_start_tx_datapath(dev);
2895         rte_spinlock_unlock(&hw->lock);
2896
2897         return 0;
2898 }
2899
2900 static int
2901 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2902 {
2903         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904         int ret;
2905
2906         /*
2907          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2908          * process does not support the mechanism for notifying the primary
2909          * process.
2910          */
2911         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2912                 hns3_err(hw, "secondary process does not support to set link down.");
2913                 return -ENOTSUP;
2914         }
2915
2916         /*
2917          * If device isn't started or the API has been called, link status is
2918          * down, return success.
2919          */
2920         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2921                 return 0;
2922
2923         rte_spinlock_lock(&hw->lock);
2924         hns3_stop_tx_datapath(dev);
2925         ret = hns3_cfg_mac_mode(hw, false);
2926         if (ret) {
2927                 hns3_start_tx_datapath(dev);
2928                 rte_spinlock_unlock(&hw->lock);
2929                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2930                 return ret;
2931         }
2932
2933         hw->set_link_down = true;
2934         rte_spinlock_unlock(&hw->lock);
2935
2936         return 0;
2937 }
2938
2939 static int
2940 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2941 {
2942         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2943         struct hns3_pf *pf = &hns->pf;
2944
2945         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2946                 return -EINVAL;
2947
2948         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2949
2950         return 0;
2951 }
2952
2953 static int
2954 hns3_query_function_status(struct hns3_hw *hw)
2955 {
2956 #define HNS3_QUERY_MAX_CNT              10
2957 #define HNS3_QUERY_SLEEP_MSCOEND        1
2958         struct hns3_func_status_cmd *req;
2959         struct hns3_cmd_desc desc;
2960         int timeout = 0;
2961         int ret;
2962
2963         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2964         req = (struct hns3_func_status_cmd *)desc.data;
2965
2966         do {
2967                 ret = hns3_cmd_send(hw, &desc, 1);
2968                 if (ret) {
2969                         PMD_INIT_LOG(ERR, "query function status failed %d",
2970                                      ret);
2971                         return ret;
2972                 }
2973
2974                 /* Check pf reset is done */
2975                 if (req->pf_state)
2976                         break;
2977
2978                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2979         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2980
2981         return hns3_parse_func_status(hw, req);
2982 }
2983
2984 static int
2985 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2986 {
2987         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2988         struct hns3_pf *pf = &hns->pf;
2989
2990         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2991                 /*
2992                  * The total_tqps_num obtained from firmware is maximum tqp
2993                  * numbers of this port, which should be used for PF and VFs.
2994                  * There is no need for pf to have so many tqp numbers in
2995                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2996                  * coming from config file, is assigned to maximum queue number
2997                  * for the PF of this port by user. So users can modify the
2998                  * maximum queue number of PF according to their own application
2999                  * scenarios, which is more flexible to use. In addition, many
3000                  * memories can be saved due to allocating queue statistics
3001                  * room according to the actual number of queues required. The
3002                  * maximum queue number of PF for network engine with
3003                  * revision_id greater than 0x30 is assigned by config file.
3004                  */
3005                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
3006                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
3007                                  "must be greater than 0.",
3008                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
3009                         return -EINVAL;
3010                 }
3011
3012                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
3013                                        hw->total_tqps_num);
3014         } else {
3015                 /*
3016                  * Due to the limitation on the number of PF interrupts
3017                  * available, the maximum queue number assigned to PF on
3018                  * the network engine with revision_id 0x21 is 64.
3019                  */
3020                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
3021                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3022         }
3023
3024         return 0;
3025 }
3026
3027 static int
3028 hns3_query_pf_resource(struct hns3_hw *hw)
3029 {
3030         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3031         struct hns3_pf *pf = &hns->pf;
3032         struct hns3_pf_res_cmd *req;
3033         struct hns3_cmd_desc desc;
3034         int ret;
3035
3036         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3037         ret = hns3_cmd_send(hw, &desc, 1);
3038         if (ret) {
3039                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3040                 return ret;
3041         }
3042
3043         req = (struct hns3_pf_res_cmd *)desc.data;
3044         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3045                              rte_le_to_cpu_16(req->ext_tqp_num);
3046         ret = hns3_get_pf_max_tqp_num(hw);
3047         if (ret)
3048                 return ret;
3049
3050         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3051         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3052
3053         if (req->tx_buf_size)
3054                 pf->tx_buf_size =
3055                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3056         else
3057                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3058
3059         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3060
3061         if (req->dv_buf_size)
3062                 pf->dv_buf_size =
3063                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3064         else
3065                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3066
3067         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3068
3069         hw->num_msi =
3070                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3071                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3072
3073         return 0;
3074 }
3075
3076 static void
3077 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3078 {
3079         struct hns3_cfg_param_cmd *req;
3080         uint64_t mac_addr_tmp_high;
3081         uint8_t ext_rss_size_max;
3082         uint64_t mac_addr_tmp;
3083         uint32_t i;
3084
3085         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3086
3087         /* get the configuration */
3088         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3089                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3090         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3091                                            HNS3_CFG_TQP_DESC_N_M,
3092                                            HNS3_CFG_TQP_DESC_N_S);
3093
3094         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3095                                        HNS3_CFG_PHY_ADDR_M,
3096                                        HNS3_CFG_PHY_ADDR_S);
3097         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3098                                          HNS3_CFG_MEDIA_TP_M,
3099                                          HNS3_CFG_MEDIA_TP_S);
3100         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3101                                          HNS3_CFG_RX_BUF_LEN_M,
3102                                          HNS3_CFG_RX_BUF_LEN_S);
3103         /* get mac address */
3104         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3105         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3106                                            HNS3_CFG_MAC_ADDR_H_M,
3107                                            HNS3_CFG_MAC_ADDR_H_S);
3108
3109         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3110
3111         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3112                                             HNS3_CFG_DEFAULT_SPEED_M,
3113                                             HNS3_CFG_DEFAULT_SPEED_S);
3114         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3115                                            HNS3_CFG_RSS_SIZE_M,
3116                                            HNS3_CFG_RSS_SIZE_S);
3117
3118         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3119                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3120
3121         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3122         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3123
3124         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3125                                             HNS3_CFG_SPEED_ABILITY_M,
3126                                             HNS3_CFG_SPEED_ABILITY_S);
3127         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3128                                         HNS3_CFG_UMV_TBL_SPACE_M,
3129                                         HNS3_CFG_UMV_TBL_SPACE_S);
3130         if (!cfg->umv_space)
3131                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3132
3133         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3134                                                HNS3_CFG_EXT_RSS_SIZE_M,
3135                                                HNS3_CFG_EXT_RSS_SIZE_S);
3136         /*
3137          * Field ext_rss_size_max obtained from firmware will be more flexible
3138          * for future changes and expansions, which is an exponent of 2, instead
3139          * of reading out directly. If this field is not zero, hns3 PF PMD
3140          * driver uses it as rss_size_max under one TC. Device, whose revision
3141          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3142          * maximum number of queues supported under a TC through this field.
3143          */
3144         if (ext_rss_size_max)
3145                 cfg->rss_size_max = 1U << ext_rss_size_max;
3146 }
3147
3148 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3149  * @hw: pointer to struct hns3_hw
3150  * @hcfg: the config structure to be getted
3151  */
3152 static int
3153 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3154 {
3155         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3156         struct hns3_cfg_param_cmd *req;
3157         uint32_t offset;
3158         uint32_t i;
3159         int ret;
3160
3161         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3162                 offset = 0;
3163                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3164                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3165                                           true);
3166                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3167                                i * HNS3_CFG_RD_LEN_BYTES);
3168                 /* Len should be divided by 4 when send to hardware */
3169                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3170                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3171                 req->offset = rte_cpu_to_le_32(offset);
3172         }
3173
3174         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3175         if (ret) {
3176                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3177                 return ret;
3178         }
3179
3180         hns3_parse_cfg(hcfg, desc);
3181
3182         return 0;
3183 }
3184
3185 static int
3186 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3187 {
3188         switch (speed_cmd) {
3189         case HNS3_CFG_SPEED_10M:
3190                 *speed = RTE_ETH_SPEED_NUM_10M;
3191                 break;
3192         case HNS3_CFG_SPEED_100M:
3193                 *speed = RTE_ETH_SPEED_NUM_100M;
3194                 break;
3195         case HNS3_CFG_SPEED_1G:
3196                 *speed = RTE_ETH_SPEED_NUM_1G;
3197                 break;
3198         case HNS3_CFG_SPEED_10G:
3199                 *speed = RTE_ETH_SPEED_NUM_10G;
3200                 break;
3201         case HNS3_CFG_SPEED_25G:
3202                 *speed = RTE_ETH_SPEED_NUM_25G;
3203                 break;
3204         case HNS3_CFG_SPEED_40G:
3205                 *speed = RTE_ETH_SPEED_NUM_40G;
3206                 break;
3207         case HNS3_CFG_SPEED_50G:
3208                 *speed = RTE_ETH_SPEED_NUM_50G;
3209                 break;
3210         case HNS3_CFG_SPEED_100G:
3211                 *speed = RTE_ETH_SPEED_NUM_100G;
3212                 break;
3213         case HNS3_CFG_SPEED_200G:
3214                 *speed = RTE_ETH_SPEED_NUM_200G;
3215                 break;
3216         default:
3217                 return -EINVAL;
3218         }
3219
3220         return 0;
3221 }
3222
3223 static void
3224 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3225 {
3226         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3227         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3228         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3229         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3230         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3231 }
3232
3233 static void
3234 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3235 {
3236         struct hns3_dev_specs_0_cmd *req0;
3237
3238         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3239
3240         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3241         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3242         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3243         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3244         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3245 }
3246
3247 static int
3248 hns3_check_dev_specifications(struct hns3_hw *hw)
3249 {
3250         if (hw->rss_ind_tbl_size == 0 ||
3251             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3252                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3253                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3254                               HNS3_RSS_IND_TBL_SIZE_MAX);
3255                 return -EINVAL;
3256         }
3257
3258         return 0;
3259 }
3260
3261 static int
3262 hns3_query_dev_specifications(struct hns3_hw *hw)
3263 {
3264         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3265         int ret;
3266         int i;
3267
3268         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3269                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3270                                           true);
3271                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3272         }
3273         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3274
3275         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3276         if (ret)
3277                 return ret;
3278
3279         hns3_parse_dev_specifications(hw, desc);
3280
3281         return hns3_check_dev_specifications(hw);
3282 }
3283
3284 static int
3285 hns3_get_capability(struct hns3_hw *hw)
3286 {
3287         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3288         struct rte_pci_device *pci_dev;
3289         struct hns3_pf *pf = &hns->pf;
3290         struct rte_eth_dev *eth_dev;
3291         uint16_t device_id;
3292         uint8_t revision;
3293         int ret;
3294
3295         eth_dev = &rte_eth_devices[hw->data->port_id];
3296         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3297         device_id = pci_dev->id.device_id;
3298
3299         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3300             device_id == HNS3_DEV_ID_50GE_RDMA ||
3301             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3302             device_id == HNS3_DEV_ID_200G_RDMA)
3303                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3304
3305         /* Get PCI revision id */
3306         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3307                                   HNS3_PCI_REVISION_ID);
3308         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3309                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3310                              ret);
3311                 return -EIO;
3312         }
3313         hw->revision = revision;
3314
3315         if (revision < PCI_REVISION_ID_HIP09_A) {
3316                 hns3_set_default_dev_specifications(hw);
3317                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3318                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3319                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3320                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3321                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3322                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3323                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3324                 hw->rss_info.ipv6_sctp_offload_supported = false;
3325                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3326                 pf->support_multi_tc_pause = false;
3327                 return 0;
3328         }
3329
3330         ret = hns3_query_dev_specifications(hw);
3331         if (ret) {
3332                 PMD_INIT_LOG(ERR,
3333                              "failed to query dev specifications, ret = %d",
3334                              ret);
3335                 return ret;
3336         }
3337
3338         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3339         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3340         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3341         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3342         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3343         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3344         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3345         hw->rss_info.ipv6_sctp_offload_supported = true;
3346         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3347         pf->support_multi_tc_pause = true;
3348
3349         return 0;
3350 }
3351
3352 static int
3353 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3354 {
3355         int ret;
3356
3357         switch (media_type) {
3358         case HNS3_MEDIA_TYPE_COPPER:
3359                 if (!hns3_dev_get_support(hw, COPPER)) {
3360                         PMD_INIT_LOG(ERR,
3361                                      "Media type is copper, not supported.");
3362                         ret = -EOPNOTSUPP;
3363                 } else {
3364                         ret = 0;
3365                 }
3366                 break;
3367         case HNS3_MEDIA_TYPE_FIBER:
3368                 ret = 0;
3369                 break;
3370         case HNS3_MEDIA_TYPE_BACKPLANE:
3371                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3372                 ret = -EOPNOTSUPP;
3373                 break;
3374         default:
3375                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3376                 ret = -EINVAL;
3377                 break;
3378         }
3379
3380         return ret;
3381 }
3382
3383 static int
3384 hns3_get_board_configuration(struct hns3_hw *hw)
3385 {
3386         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3387         struct hns3_pf *pf = &hns->pf;
3388         struct hns3_cfg cfg;
3389         int ret;
3390
3391         ret = hns3_get_board_cfg(hw, &cfg);
3392         if (ret) {
3393                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3394                 return ret;
3395         }
3396
3397         ret = hns3_check_media_type(hw, cfg.media_type);
3398         if (ret)
3399                 return ret;
3400
3401         hw->mac.media_type = cfg.media_type;
3402         hw->rss_size_max = cfg.rss_size_max;
3403         hw->rss_dis_flag = false;
3404         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3405         hw->mac.phy_addr = cfg.phy_addr;
3406         hw->num_tx_desc = cfg.tqp_desc_num;
3407         hw->num_rx_desc = cfg.tqp_desc_num;
3408         hw->dcb_info.num_pg = 1;
3409         hw->dcb_info.hw_pfc_map = 0;
3410
3411         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3412         if (ret) {
3413                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3414                              cfg.default_speed, ret);
3415                 return ret;
3416         }
3417
3418         pf->tc_max = cfg.tc_num;
3419         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3420                 PMD_INIT_LOG(WARNING,
3421                              "Get TC num(%u) from flash, set TC num to 1",
3422                              pf->tc_max);
3423                 pf->tc_max = 1;
3424         }
3425
3426         /* Dev does not support DCB */
3427         if (!hns3_dev_get_support(hw, DCB)) {
3428                 pf->tc_max = 1;
3429                 pf->pfc_max = 0;
3430         } else
3431                 pf->pfc_max = pf->tc_max;
3432
3433         hw->dcb_info.num_tc = 1;
3434         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3435                                      hw->tqps_num / hw->dcb_info.num_tc);
3436         hns3_set_bit(hw->hw_tc_map, 0, 1);
3437         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3438
3439         pf->wanted_umv_size = cfg.umv_space;
3440
3441         return ret;
3442 }
3443
3444 static int
3445 hns3_get_configuration(struct hns3_hw *hw)
3446 {
3447         int ret;
3448
3449         ret = hns3_query_function_status(hw);
3450         if (ret) {
3451                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3452                 return ret;
3453         }
3454
3455         /* Get device capability */
3456         ret = hns3_get_capability(hw);
3457         if (ret) {
3458                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3459                 return ret;
3460         }
3461
3462         /* Get pf resource */
3463         ret = hns3_query_pf_resource(hw);
3464         if (ret) {
3465                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3466                 return ret;
3467         }
3468
3469         ret = hns3_get_board_configuration(hw);
3470         if (ret) {
3471                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3472                 return ret;
3473         }
3474
3475         ret = hns3_query_dev_fec_info(hw);
3476         if (ret)
3477                 PMD_INIT_LOG(ERR,
3478                              "failed to query FEC information, ret = %d", ret);
3479
3480         return ret;
3481 }
3482
3483 static int
3484 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3485                       uint16_t tqp_vid, bool is_pf)
3486 {
3487         struct hns3_tqp_map_cmd *req;
3488         struct hns3_cmd_desc desc;
3489         int ret;
3490
3491         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3492
3493         req = (struct hns3_tqp_map_cmd *)desc.data;
3494         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3495         req->tqp_vf = func_id;
3496         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3497         if (!is_pf)
3498                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3499         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3500
3501         ret = hns3_cmd_send(hw, &desc, 1);
3502         if (ret)
3503                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3504
3505         return ret;
3506 }
3507
3508 static int
3509 hns3_map_tqp(struct hns3_hw *hw)
3510 {
3511         int ret;
3512         int i;
3513
3514         /*
3515          * In current version, VF is not supported when PF is driven by DPDK
3516          * driver, so we assign total tqps_num tqps allocated to this port
3517          * to PF.
3518          */
3519         for (i = 0; i < hw->total_tqps_num; i++) {
3520                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3521                 if (ret)
3522                         return ret;
3523         }
3524
3525         return 0;
3526 }
3527
3528 static int
3529 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3530 {
3531         struct hns3_config_mac_speed_dup_cmd *req;
3532         struct hns3_cmd_desc desc;
3533         int ret;
3534
3535         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3536
3537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3538
3539         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3540
3541         switch (speed) {
3542         case RTE_ETH_SPEED_NUM_10M:
3543                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3544                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3545                 break;
3546         case RTE_ETH_SPEED_NUM_100M:
3547                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3548                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3549                 break;
3550         case RTE_ETH_SPEED_NUM_1G:
3551                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3552                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3553                 break;
3554         case RTE_ETH_SPEED_NUM_10G:
3555                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3556                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3557                 break;
3558         case RTE_ETH_SPEED_NUM_25G:
3559                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3560                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3561                 break;
3562         case RTE_ETH_SPEED_NUM_40G:
3563                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3564                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3565                 break;
3566         case RTE_ETH_SPEED_NUM_50G:
3567                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3568                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3569                 break;
3570         case RTE_ETH_SPEED_NUM_100G:
3571                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3572                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3573                 break;
3574         case RTE_ETH_SPEED_NUM_200G:
3575                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3576                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3577                 break;
3578         default:
3579                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3580                 return -EINVAL;
3581         }
3582
3583         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3584
3585         ret = hns3_cmd_send(hw, &desc, 1);
3586         if (ret)
3587                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3588
3589         return ret;
3590 }
3591
3592 static int
3593 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3594 {
3595         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3596         struct hns3_pf *pf = &hns->pf;
3597         struct hns3_priv_buf *priv;
3598         uint32_t i, total_size;
3599
3600         total_size = pf->pkt_buf_size;
3601
3602         /* alloc tx buffer for all enabled tc */
3603         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3604                 priv = &buf_alloc->priv_buf[i];
3605
3606                 if (hw->hw_tc_map & BIT(i)) {
3607                         if (total_size < pf->tx_buf_size)
3608                                 return -ENOMEM;
3609
3610                         priv->tx_buf_size = pf->tx_buf_size;
3611                 } else
3612                         priv->tx_buf_size = 0;
3613
3614                 total_size -= priv->tx_buf_size;
3615         }
3616
3617         return 0;
3618 }
3619
3620 static int
3621 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3622 {
3623 /* TX buffer size is unit by 128 byte */
3624 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3625 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3626         struct hns3_tx_buff_alloc_cmd *req;
3627         struct hns3_cmd_desc desc;
3628         uint32_t buf_size;
3629         uint32_t i;
3630         int ret;
3631
3632         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3633
3634         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3635         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3636                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3637
3638                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3639                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3640                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3641         }
3642
3643         ret = hns3_cmd_send(hw, &desc, 1);
3644         if (ret)
3645                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3646
3647         return ret;
3648 }
3649
3650 static int
3651 hns3_get_tc_num(struct hns3_hw *hw)
3652 {
3653         int cnt = 0;
3654         uint8_t i;
3655
3656         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3657                 if (hw->hw_tc_map & BIT(i))
3658                         cnt++;
3659         return cnt;
3660 }
3661
3662 static uint32_t
3663 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3664 {
3665         struct hns3_priv_buf *priv;
3666         uint32_t rx_priv = 0;
3667         int i;
3668
3669         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3670                 priv = &buf_alloc->priv_buf[i];
3671                 if (priv->enable)
3672                         rx_priv += priv->buf_size;
3673         }
3674         return rx_priv;
3675 }
3676
3677 static uint32_t
3678 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3679 {
3680         uint32_t total_tx_size = 0;
3681         uint32_t i;
3682
3683         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3684                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3685
3686         return total_tx_size;
3687 }
3688
3689 /* Get the number of pfc enabled TCs, which have private buffer */
3690 static int
3691 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3692 {
3693         struct hns3_priv_buf *priv;
3694         int cnt = 0;
3695         uint8_t i;
3696
3697         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3698                 priv = &buf_alloc->priv_buf[i];
3699                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3700                         cnt++;
3701         }
3702
3703         return cnt;
3704 }
3705
3706 /* Get the number of pfc disabled TCs, which have private buffer */
3707 static int
3708 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3709                          struct hns3_pkt_buf_alloc *buf_alloc)
3710 {
3711         struct hns3_priv_buf *priv;
3712         int cnt = 0;
3713         uint8_t i;
3714
3715         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3716                 priv = &buf_alloc->priv_buf[i];
3717                 if (hw->hw_tc_map & BIT(i) &&
3718                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3719                         cnt++;
3720         }
3721
3722         return cnt;
3723 }
3724
3725 static bool
3726 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3727                   uint32_t rx_all)
3728 {
3729         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3730         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3731         struct hns3_pf *pf = &hns->pf;
3732         uint32_t shared_buf, aligned_mps;
3733         uint32_t rx_priv;
3734         uint8_t tc_num;
3735         uint8_t i;
3736
3737         tc_num = hns3_get_tc_num(hw);
3738         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3739
3740         if (hns3_dev_get_support(hw, DCB))
3741                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3742                                         pf->dv_buf_size;
3743         else
3744                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3745                                         + pf->dv_buf_size;
3746
3747         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3748         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3749                              HNS3_BUF_SIZE_UNIT);
3750
3751         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3752         if (rx_all < rx_priv + shared_std)
3753                 return false;
3754
3755         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3756         buf_alloc->s_buf.buf_size = shared_buf;
3757         if (hns3_dev_get_support(hw, DCB)) {
3758                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3759                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3760                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3761                                   HNS3_BUF_SIZE_UNIT);
3762         } else {
3763                 buf_alloc->s_buf.self.high =
3764                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3765                 buf_alloc->s_buf.self.low = aligned_mps;
3766         }
3767
3768         if (hns3_dev_get_support(hw, DCB)) {
3769                 hi_thrd = shared_buf - pf->dv_buf_size;
3770
3771                 if (tc_num <= NEED_RESERVE_TC_NUM)
3772                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3773                                   BUF_MAX_PERCENT;
3774
3775                 if (tc_num)
3776                         hi_thrd = hi_thrd / tc_num;
3777
3778                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3779                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3780                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3781         } else {
3782                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3783                 lo_thrd = aligned_mps;
3784         }
3785
3786         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3787                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3788                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3789         }
3790
3791         return true;
3792 }
3793
3794 static bool
3795 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3796                      struct hns3_pkt_buf_alloc *buf_alloc)
3797 {
3798         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3799         struct hns3_pf *pf = &hns->pf;
3800         struct hns3_priv_buf *priv;
3801         uint32_t aligned_mps;
3802         uint32_t rx_all;
3803         uint8_t i;
3804
3805         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3806         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3807
3808         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3809                 priv = &buf_alloc->priv_buf[i];
3810
3811                 priv->enable = 0;
3812                 priv->wl.low = 0;
3813                 priv->wl.high = 0;
3814                 priv->buf_size = 0;
3815
3816                 if (!(hw->hw_tc_map & BIT(i)))
3817                         continue;
3818
3819                 priv->enable = 1;
3820                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3821                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3822                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3823                                                 HNS3_BUF_SIZE_UNIT);
3824                 } else {
3825                         priv->wl.low = 0;
3826                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3827                                         aligned_mps;
3828                 }
3829
3830                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3831         }
3832
3833         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3834 }
3835
3836 static bool
3837 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3838                              struct hns3_pkt_buf_alloc *buf_alloc)
3839 {
3840         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3841         struct hns3_pf *pf = &hns->pf;
3842         struct hns3_priv_buf *priv;
3843         int no_pfc_priv_num;
3844         uint32_t rx_all;
3845         uint8_t mask;
3846         int i;
3847
3848         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3849         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3850
3851         /* let the last to be cleared first */
3852         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3853                 priv = &buf_alloc->priv_buf[i];
3854                 mask = BIT((uint8_t)i);
3855                 if (hw->hw_tc_map & mask &&
3856                     !(hw->dcb_info.hw_pfc_map & mask)) {
3857                         /* Clear the no pfc TC private buffer */
3858                         priv->wl.low = 0;
3859                         priv->wl.high = 0;
3860                         priv->buf_size = 0;
3861                         priv->enable = 0;
3862                         no_pfc_priv_num--;
3863                 }
3864
3865                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3866                     no_pfc_priv_num == 0)
3867                         break;
3868         }
3869
3870         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3871 }
3872
3873 static bool
3874 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3875                            struct hns3_pkt_buf_alloc *buf_alloc)
3876 {
3877         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3878         struct hns3_pf *pf = &hns->pf;
3879         struct hns3_priv_buf *priv;
3880         uint32_t rx_all;
3881         int pfc_priv_num;
3882         uint8_t mask;
3883         int i;
3884
3885         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3886         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3887
3888         /* let the last to be cleared first */
3889         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3890                 priv = &buf_alloc->priv_buf[i];
3891                 mask = BIT((uint8_t)i);
3892                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3893                         /* Reduce the number of pfc TC with private buffer */
3894                         priv->wl.low = 0;
3895                         priv->enable = 0;
3896                         priv->wl.high = 0;
3897                         priv->buf_size = 0;
3898                         pfc_priv_num--;
3899                 }
3900                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3901                     pfc_priv_num == 0)
3902                         break;
3903         }
3904
3905         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3906 }
3907
3908 static bool
3909 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3910                           struct hns3_pkt_buf_alloc *buf_alloc)
3911 {
3912 #define COMPENSATE_BUFFER       0x3C00
3913 #define COMPENSATE_HALF_MPS_NUM 5
3914 #define PRIV_WL_GAP             0x1800
3915         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3916         struct hns3_pf *pf = &hns->pf;
3917         uint32_t tc_num = hns3_get_tc_num(hw);
3918         uint32_t half_mps = pf->mps >> 1;
3919         struct hns3_priv_buf *priv;
3920         uint32_t min_rx_priv;
3921         uint32_t rx_priv;
3922         uint8_t i;
3923
3924         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3925         if (tc_num)
3926                 rx_priv = rx_priv / tc_num;
3927
3928         if (tc_num <= NEED_RESERVE_TC_NUM)
3929                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3930
3931         /*
3932          * Minimum value of private buffer in rx direction (min_rx_priv) is
3933          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3934          * buffer if rx_priv is greater than min_rx_priv.
3935          */
3936         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3937                         COMPENSATE_HALF_MPS_NUM * half_mps;
3938         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3939         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3940         if (rx_priv < min_rx_priv)
3941                 return false;
3942
3943         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3944                 priv = &buf_alloc->priv_buf[i];
3945                 priv->enable = 0;
3946                 priv->wl.low = 0;
3947                 priv->wl.high = 0;
3948                 priv->buf_size = 0;
3949
3950                 if (!(hw->hw_tc_map & BIT(i)))
3951                         continue;
3952
3953                 priv->enable = 1;
3954                 priv->buf_size = rx_priv;
3955                 priv->wl.high = rx_priv - pf->dv_buf_size;
3956                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3957         }
3958
3959         buf_alloc->s_buf.buf_size = 0;
3960
3961         return true;
3962 }
3963
3964 /*
3965  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3966  * @hw: pointer to struct hns3_hw
3967  * @buf_alloc: pointer to buffer calculation data
3968  * @return: 0: calculate sucessful, negative: fail
3969  */
3970 static int
3971 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3972 {
3973         /* When DCB is not supported, rx private buffer is not allocated. */
3974         if (!hns3_dev_get_support(hw, DCB)) {
3975                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3976                 struct hns3_pf *pf = &hns->pf;
3977                 uint32_t rx_all = pf->pkt_buf_size;
3978
3979                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3980                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3981                         return -ENOMEM;
3982
3983                 return 0;
3984         }
3985
3986         /*
3987          * Try to allocate privated packet buffer for all TCs without share
3988          * buffer.
3989          */
3990         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3991                 return 0;
3992
3993         /*
3994          * Try to allocate privated packet buffer for all TCs with share
3995          * buffer.
3996          */
3997         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3998                 return 0;
3999
4000         /*
4001          * For different application scenes, the enabled port number, TC number
4002          * and no_drop TC number are different. In order to obtain the better
4003          * performance, software could allocate the buffer size and configure
4004          * the waterline by trying to decrease the private buffer size according
4005          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
4006          * enabled tc.
4007          */
4008         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
4009                 return 0;
4010
4011         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
4012                 return 0;
4013
4014         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
4015                 return 0;
4016
4017         return -ENOMEM;
4018 }
4019
4020 static int
4021 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4022 {
4023         struct hns3_rx_priv_buff_cmd *req;
4024         struct hns3_cmd_desc desc;
4025         uint32_t buf_size;
4026         int ret;
4027         int i;
4028
4029         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4030         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4031
4032         /* Alloc private buffer TCs */
4033         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4034                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4035
4036                 req->buf_num[i] =
4037                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4038                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4039         }
4040
4041         buf_size = buf_alloc->s_buf.buf_size;
4042         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4043                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4044
4045         ret = hns3_cmd_send(hw, &desc, 1);
4046         if (ret)
4047                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4048
4049         return ret;
4050 }
4051
4052 static int
4053 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4054 {
4055 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4056         struct hns3_rx_priv_wl_buf *req;
4057         struct hns3_priv_buf *priv;
4058         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4059         int i, j;
4060         int ret;
4061
4062         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4063                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4064                                           false);
4065                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4066
4067                 /* The first descriptor set the NEXT bit to 1 */
4068                 if (i == 0)
4069                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4070                 else
4071                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4072
4073                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4074                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4075
4076                         priv = &buf_alloc->priv_buf[idx];
4077                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4078                                                         HNS3_BUF_UNIT_S);
4079                         req->tc_wl[j].high |=
4080                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4081                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4082                                                         HNS3_BUF_UNIT_S);
4083                         req->tc_wl[j].low |=
4084                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4085                 }
4086         }
4087
4088         /* Send 2 descriptor at one time */
4089         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4090         if (ret)
4091                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4092                              ret);
4093         return ret;
4094 }
4095
4096 static int
4097 hns3_common_thrd_config(struct hns3_hw *hw,
4098                         struct hns3_pkt_buf_alloc *buf_alloc)
4099 {
4100 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4101         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4102         struct hns3_rx_com_thrd *req;
4103         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4104         struct hns3_tc_thrd *tc;
4105         int tc_idx;
4106         int i, j;
4107         int ret;
4108
4109         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4110                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4111                                           false);
4112                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4113
4114                 /* The first descriptor set the NEXT bit to 1 */
4115                 if (i == 0)
4116                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4117                 else
4118                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4119
4120                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4121                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4122                         tc = &s_buf->tc_thrd[tc_idx];
4123
4124                         req->com_thrd[j].high =
4125                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4126                         req->com_thrd[j].high |=
4127                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4128                         req->com_thrd[j].low =
4129                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4130                         req->com_thrd[j].low |=
4131                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4132                 }
4133         }
4134
4135         /* Send 2 descriptors at one time */
4136         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4137         if (ret)
4138                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4139
4140         return ret;
4141 }
4142
4143 static int
4144 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4145 {
4146         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4147         struct hns3_rx_com_wl *req;
4148         struct hns3_cmd_desc desc;
4149         int ret;
4150
4151         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4152
4153         req = (struct hns3_rx_com_wl *)desc.data;
4154         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4155         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4156
4157         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4158         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4159
4160         ret = hns3_cmd_send(hw, &desc, 1);
4161         if (ret)
4162                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4163
4164         return ret;
4165 }
4166
4167 int
4168 hns3_buffer_alloc(struct hns3_hw *hw)
4169 {
4170         struct hns3_pkt_buf_alloc pkt_buf;
4171         int ret;
4172
4173         memset(&pkt_buf, 0, sizeof(pkt_buf));
4174         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4175         if (ret) {
4176                 PMD_INIT_LOG(ERR,
4177                              "could not calc tx buffer size for all TCs %d",
4178                              ret);
4179                 return ret;
4180         }
4181
4182         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4183         if (ret) {
4184                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4185                 return ret;
4186         }
4187
4188         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4189         if (ret) {
4190                 PMD_INIT_LOG(ERR,
4191                              "could not calc rx priv buffer size for all TCs %d",
4192                              ret);
4193                 return ret;
4194         }
4195
4196         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4197         if (ret) {
4198                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4199                 return ret;
4200         }
4201
4202         if (hns3_dev_get_support(hw, DCB)) {
4203                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4204                 if (ret) {
4205                         PMD_INIT_LOG(ERR,
4206                                      "could not configure rx private waterline %d",
4207                                      ret);
4208                         return ret;
4209                 }
4210
4211                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4212                 if (ret) {
4213                         PMD_INIT_LOG(ERR,
4214                                      "could not configure common threshold %d",
4215                                      ret);
4216                         return ret;
4217                 }
4218         }
4219
4220         ret = hns3_common_wl_config(hw, &pkt_buf);
4221         if (ret)
4222                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4223                              ret);
4224
4225         return ret;
4226 }
4227
4228 static int
4229 hns3_mac_init(struct hns3_hw *hw)
4230 {
4231         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4232         struct hns3_mac *mac = &hw->mac;
4233         struct hns3_pf *pf = &hns->pf;
4234         int ret;
4235
4236         pf->support_sfp_query = true;
4237         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4238         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4239         if (ret) {
4240                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4241                 return ret;
4242         }
4243
4244         mac->link_status = RTE_ETH_LINK_DOWN;
4245
4246         return hns3_config_mtu(hw, pf->mps);
4247 }
4248
4249 static int
4250 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4251 {
4252 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4253 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4254 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4255 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4256         int return_status;
4257
4258         if (cmdq_resp) {
4259                 PMD_INIT_LOG(ERR,
4260                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4261                              cmdq_resp);
4262                 return -EIO;
4263         }
4264
4265         switch (resp_code) {
4266         case HNS3_ETHERTYPE_SUCCESS_ADD:
4267         case HNS3_ETHERTYPE_ALREADY_ADD:
4268                 return_status = 0;
4269                 break;
4270         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4271                 PMD_INIT_LOG(ERR,
4272                              "add mac ethertype failed for manager table overflow.");
4273                 return_status = -EIO;
4274                 break;
4275         case HNS3_ETHERTYPE_KEY_CONFLICT:
4276                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4277                 return_status = -EIO;
4278                 break;
4279         default:
4280                 PMD_INIT_LOG(ERR,
4281                              "add mac ethertype failed for undefined, code=%u.",
4282                              resp_code);
4283                 return_status = -EIO;
4284                 break;
4285         }
4286
4287         return return_status;
4288 }
4289
4290 static int
4291 hns3_add_mgr_tbl(struct hns3_hw *hw,
4292                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4293 {
4294         struct hns3_cmd_desc desc;
4295         uint8_t resp_code;
4296         uint16_t retval;
4297         int ret;
4298
4299         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4300         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4301
4302         ret = hns3_cmd_send(hw, &desc, 1);
4303         if (ret) {
4304                 PMD_INIT_LOG(ERR,
4305                              "add mac ethertype failed for cmd_send, ret =%d.",
4306                              ret);
4307                 return ret;
4308         }
4309
4310         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4311         retval = rte_le_to_cpu_16(desc.retval);
4312
4313         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4314 }
4315
4316 static void
4317 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4318                      int *table_item_num)
4319 {
4320         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4321
4322         /*
4323          * In current version, we add one item in management table as below:
4324          * 0x0180C200000E -- LLDP MC address
4325          */
4326         tbl = mgr_table;
4327         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4328         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4329         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4330         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4331         tbl->i_port_bitmap = 0x1;
4332         *table_item_num = 1;
4333 }
4334
4335 static int
4336 hns3_init_mgr_tbl(struct hns3_hw *hw)
4337 {
4338 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4339         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4340         int table_item_num;
4341         int ret;
4342         int i;
4343
4344         memset(mgr_table, 0, sizeof(mgr_table));
4345         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4346         for (i = 0; i < table_item_num; i++) {
4347                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4348                 if (ret) {
4349                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4350                                      ret);
4351                         return ret;
4352                 }
4353         }
4354
4355         return 0;
4356 }
4357
4358 static void
4359 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4360                         bool en_mc, bool en_bc, int vport_id)
4361 {
4362         if (!param)
4363                 return;
4364
4365         memset(param, 0, sizeof(struct hns3_promisc_param));
4366         if (en_uc)
4367                 param->enable = HNS3_PROMISC_EN_UC;
4368         if (en_mc)
4369                 param->enable |= HNS3_PROMISC_EN_MC;
4370         if (en_bc)
4371                 param->enable |= HNS3_PROMISC_EN_BC;
4372         param->vf_id = vport_id;
4373 }
4374
4375 static int
4376 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4377 {
4378         struct hns3_promisc_cfg_cmd *req;
4379         struct hns3_cmd_desc desc;
4380         int ret;
4381
4382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4383
4384         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4385         req->vf_id = param->vf_id;
4386         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4387             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4388
4389         ret = hns3_cmd_send(hw, &desc, 1);
4390         if (ret)
4391                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4392
4393         return ret;
4394 }
4395
4396 static int
4397 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4398 {
4399         struct hns3_promisc_param param;
4400         bool en_bc_pmc = true;
4401         uint8_t vf_id;
4402
4403         /*
4404          * In current version VF is not supported when PF is driven by DPDK
4405          * driver, just need to configure parameters for PF vport.
4406          */
4407         vf_id = HNS3_PF_FUNC_ID;
4408
4409         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4410         return hns3_cmd_set_promisc_mode(hw, &param);
4411 }
4412
4413 static int
4414 hns3_promisc_init(struct hns3_hw *hw)
4415 {
4416         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4417         struct hns3_pf *pf = &hns->pf;
4418         struct hns3_promisc_param param;
4419         uint16_t func_id;
4420         int ret;
4421
4422         ret = hns3_set_promisc_mode(hw, false, false);
4423         if (ret) {
4424                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4425                 return ret;
4426         }
4427
4428         /*
4429          * In current version VFs are not supported when PF is driven by DPDK
4430          * driver. After PF has been taken over by DPDK, the original VF will
4431          * be invalid. So, there is a possibility of entry residues. It should
4432          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4433          * during init.
4434          */
4435         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4436                 hns3_promisc_param_init(&param, false, false, false, func_id);
4437                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4438                 if (ret) {
4439                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4440                                         " ret = %d", func_id, ret);
4441                         return ret;
4442                 }
4443         }
4444
4445         return 0;
4446 }
4447
4448 static void
4449 hns3_promisc_uninit(struct hns3_hw *hw)
4450 {
4451         struct hns3_promisc_param param;
4452         uint16_t func_id;
4453         int ret;
4454
4455         func_id = HNS3_PF_FUNC_ID;
4456
4457         /*
4458          * In current version VFs are not supported when PF is driven by
4459          * DPDK driver, and VFs' promisc mode status has been cleared during
4460          * init and their status will not change. So just clear PF's promisc
4461          * mode status during uninit.
4462          */
4463         hns3_promisc_param_init(&param, false, false, false, func_id);
4464         ret = hns3_cmd_set_promisc_mode(hw, &param);
4465         if (ret)
4466                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4467                                 " uninit, ret = %d", ret);
4468 }
4469
4470 static int
4471 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4472 {
4473         bool allmulti = dev->data->all_multicast ? true : false;
4474         struct hns3_adapter *hns = dev->data->dev_private;
4475         struct hns3_hw *hw = &hns->hw;
4476         uint64_t offloads;
4477         int err;
4478         int ret;
4479
4480         rte_spinlock_lock(&hw->lock);
4481         ret = hns3_set_promisc_mode(hw, true, true);
4482         if (ret) {
4483                 rte_spinlock_unlock(&hw->lock);
4484                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4485                          ret);
4486                 return ret;
4487         }
4488
4489         /*
4490          * When promiscuous mode was enabled, disable the vlan filter to let
4491          * all packets coming in in the receiving direction.
4492          */
4493         offloads = dev->data->dev_conf.rxmode.offloads;
4494         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4495                 ret = hns3_enable_vlan_filter(hns, false);
4496                 if (ret) {
4497                         hns3_err(hw, "failed to enable promiscuous mode due to "
4498                                      "failure to disable vlan filter, ret = %d",
4499                                  ret);
4500                         err = hns3_set_promisc_mode(hw, false, allmulti);
4501                         if (err)
4502                                 hns3_err(hw, "failed to restore promiscuous "
4503                                          "status after disable vlan filter "
4504                                          "failed during enabling promiscuous "
4505                                          "mode, ret = %d", ret);
4506                 }
4507         }
4508
4509         rte_spinlock_unlock(&hw->lock);
4510
4511         return ret;
4512 }
4513
4514 static int
4515 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4516 {
4517         bool allmulti = dev->data->all_multicast ? true : false;
4518         struct hns3_adapter *hns = dev->data->dev_private;
4519         struct hns3_hw *hw = &hns->hw;
4520         uint64_t offloads;
4521         int err;
4522         int ret;
4523
4524         /* If now in all_multicast mode, must remain in all_multicast mode. */
4525         rte_spinlock_lock(&hw->lock);
4526         ret = hns3_set_promisc_mode(hw, false, allmulti);
4527         if (ret) {
4528                 rte_spinlock_unlock(&hw->lock);
4529                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4530                          ret);
4531                 return ret;
4532         }
4533         /* when promiscuous mode was disabled, restore the vlan filter status */
4534         offloads = dev->data->dev_conf.rxmode.offloads;
4535         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
4536                 ret = hns3_enable_vlan_filter(hns, true);
4537                 if (ret) {
4538                         hns3_err(hw, "failed to disable promiscuous mode due to"
4539                                  " failure to restore vlan filter, ret = %d",
4540                                  ret);
4541                         err = hns3_set_promisc_mode(hw, true, true);
4542                         if (err)
4543                                 hns3_err(hw, "failed to restore promiscuous "
4544                                          "status after enabling vlan filter "
4545                                          "failed during disabling promiscuous "
4546                                          "mode, ret = %d", ret);
4547                 }
4548         }
4549         rte_spinlock_unlock(&hw->lock);
4550
4551         return ret;
4552 }
4553
4554 static int
4555 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4556 {
4557         struct hns3_adapter *hns = dev->data->dev_private;
4558         struct hns3_hw *hw = &hns->hw;
4559         int ret;
4560
4561         if (dev->data->promiscuous)
4562                 return 0;
4563
4564         rte_spinlock_lock(&hw->lock);
4565         ret = hns3_set_promisc_mode(hw, false, true);
4566         rte_spinlock_unlock(&hw->lock);
4567         if (ret)
4568                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4569                          ret);
4570
4571         return ret;
4572 }
4573
4574 static int
4575 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4576 {
4577         struct hns3_adapter *hns = dev->data->dev_private;
4578         struct hns3_hw *hw = &hns->hw;
4579         int ret;
4580
4581         /* If now in promiscuous mode, must remain in all_multicast mode. */
4582         if (dev->data->promiscuous)
4583                 return 0;
4584
4585         rte_spinlock_lock(&hw->lock);
4586         ret = hns3_set_promisc_mode(hw, false, false);
4587         rte_spinlock_unlock(&hw->lock);
4588         if (ret)
4589                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4590                          ret);
4591
4592         return ret;
4593 }
4594
4595 static int
4596 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4597 {
4598         struct hns3_hw *hw = &hns->hw;
4599         bool allmulti = hw->data->all_multicast ? true : false;
4600         int ret;
4601
4602         if (hw->data->promiscuous) {
4603                 ret = hns3_set_promisc_mode(hw, true, true);
4604                 if (ret)
4605                         hns3_err(hw, "failed to restore promiscuous mode, "
4606                                  "ret = %d", ret);
4607                 return ret;
4608         }
4609
4610         ret = hns3_set_promisc_mode(hw, false, allmulti);
4611         if (ret)
4612                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4613                          ret);
4614         return ret;
4615 }
4616
4617 static int
4618 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4619 {
4620         struct hns3_sfp_info_cmd *resp;
4621         struct hns3_cmd_desc desc;
4622         int ret;
4623
4624         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4625         resp = (struct hns3_sfp_info_cmd *)desc.data;
4626         resp->query_type = HNS3_ACTIVE_QUERY;
4627
4628         ret = hns3_cmd_send(hw, &desc, 1);
4629         if (ret == -EOPNOTSUPP) {
4630                 hns3_warn(hw, "firmware does not support get SFP info,"
4631                           " ret = %d.", ret);
4632                 return ret;
4633         } else if (ret) {
4634                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4635                 return ret;
4636         }
4637
4638         /*
4639          * In some case, the speed of MAC obtained from firmware may be 0, it
4640          * shouldn't be set to mac->speed.
4641          */
4642         if (!rte_le_to_cpu_32(resp->sfp_speed))
4643                 return 0;
4644
4645         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4646         /*
4647          * if resp->supported_speed is 0, it means it's an old version
4648          * firmware, do not update these params.
4649          */
4650         if (resp->supported_speed) {
4651                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4652                 mac_info->supported_speed =
4653                                         rte_le_to_cpu_32(resp->supported_speed);
4654                 mac_info->support_autoneg = resp->autoneg_ability;
4655                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4656                                         : RTE_ETH_LINK_AUTONEG;
4657         } else {
4658                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4659         }
4660
4661         return 0;
4662 }
4663
4664 static uint8_t
4665 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4666 {
4667         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4668                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4669
4670         return duplex;
4671 }
4672
4673 static int
4674 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4675 {
4676         struct hns3_mac *mac = &hw->mac;
4677         int ret;
4678
4679         duplex = hns3_check_speed_dup(duplex, speed);
4680         if (mac->link_speed == speed && mac->link_duplex == duplex)
4681                 return 0;
4682
4683         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4684         if (ret)
4685                 return ret;
4686
4687         ret = hns3_port_shaper_update(hw, speed);
4688         if (ret)
4689                 return ret;
4690
4691         mac->link_speed = speed;
4692         mac->link_duplex = duplex;
4693
4694         return 0;
4695 }
4696
4697 static int
4698 hns3_update_fiber_link_info(struct hns3_hw *hw)
4699 {
4700         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4701         struct hns3_mac *mac = &hw->mac;
4702         struct hns3_mac mac_info;
4703         int ret;
4704
4705         /* If firmware do not support get SFP/qSFP speed, return directly */
4706         if (!pf->support_sfp_query)
4707                 return 0;
4708
4709         memset(&mac_info, 0, sizeof(struct hns3_mac));
4710         ret = hns3_get_sfp_info(hw, &mac_info);
4711         if (ret == -EOPNOTSUPP) {
4712                 pf->support_sfp_query = false;
4713                 return ret;
4714         } else if (ret)
4715                 return ret;
4716
4717         /* Do nothing if no SFP */
4718         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4719                 return 0;
4720
4721         /*
4722          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4723          * to reconfigure the speed of MAC. Otherwise, it indicates
4724          * that the current firmware only supports to obtain the
4725          * speed of the SFP, and the speed of MAC needs to reconfigure.
4726          */
4727         mac->query_type = mac_info.query_type;
4728         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4729                 if (mac_info.link_speed != mac->link_speed) {
4730                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4731                         if (ret)
4732                                 return ret;
4733                 }
4734
4735                 mac->link_speed = mac_info.link_speed;
4736                 mac->supported_speed = mac_info.supported_speed;
4737                 mac->support_autoneg = mac_info.support_autoneg;
4738                 mac->link_autoneg = mac_info.link_autoneg;
4739
4740                 return 0;
4741         }
4742
4743         /* Config full duplex for SFP */
4744         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4745                                       RTE_ETH_LINK_FULL_DUPLEX);
4746 }
4747
4748 static void
4749 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4750 {
4751 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4752
4753         struct hns3_phy_params_bd0_cmd *req;
4754         uint32_t supported;
4755
4756         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4757         mac->link_speed = rte_le_to_cpu_32(req->speed);
4758         mac->link_duplex = hns3_get_bit(req->duplex,
4759                                            HNS3_PHY_DUPLEX_CFG_B);
4760         mac->link_autoneg = hns3_get_bit(req->autoneg,
4761                                            HNS3_PHY_AUTONEG_CFG_B);
4762         mac->advertising = rte_le_to_cpu_32(req->advertising);
4763         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4764         supported = rte_le_to_cpu_32(req->supported);
4765         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4766         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4767 }
4768
4769 static int
4770 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4771 {
4772         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4773         uint16_t i;
4774         int ret;
4775
4776         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4777                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4778                                           true);
4779                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4780         }
4781         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4782
4783         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4784         if (ret) {
4785                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4786                 return ret;
4787         }
4788
4789         hns3_parse_copper_phy_params(desc, mac);
4790
4791         return 0;
4792 }
4793
4794 static int
4795 hns3_update_copper_link_info(struct hns3_hw *hw)
4796 {
4797         struct hns3_mac *mac = &hw->mac;
4798         struct hns3_mac mac_info;
4799         int ret;
4800
4801         memset(&mac_info, 0, sizeof(struct hns3_mac));
4802         ret = hns3_get_copper_phy_params(hw, &mac_info);
4803         if (ret)
4804                 return ret;
4805
4806         if (mac_info.link_speed != mac->link_speed) {
4807                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4808                 if (ret)
4809                         return ret;
4810         }
4811
4812         mac->link_speed = mac_info.link_speed;
4813         mac->link_duplex = mac_info.link_duplex;
4814         mac->link_autoneg = mac_info.link_autoneg;
4815         mac->supported_speed = mac_info.supported_speed;
4816         mac->advertising = mac_info.advertising;
4817         mac->lp_advertising = mac_info.lp_advertising;
4818         mac->support_autoneg = mac_info.support_autoneg;
4819
4820         return 0;
4821 }
4822
4823 static int
4824 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4825 {
4826         struct hns3_adapter *hns = eth_dev->data->dev_private;
4827         struct hns3_hw *hw = &hns->hw;
4828         int ret = 0;
4829
4830         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4831                 ret = hns3_update_copper_link_info(hw);
4832         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4833                 ret = hns3_update_fiber_link_info(hw);
4834
4835         return ret;
4836 }
4837
4838 static int
4839 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4840 {
4841         struct hns3_config_mac_mode_cmd *req;
4842         struct hns3_cmd_desc desc;
4843         uint32_t loop_en = 0;
4844         uint8_t val = 0;
4845         int ret;
4846
4847         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4848
4849         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4850         if (enable)
4851                 val = 1;
4852         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4853         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4854         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4855         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4856         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4857         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4858         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4859         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4860         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4861         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4862
4863         /*
4864          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4865          * when receiving frames. Otherwise, CRC will be stripped.
4866          */
4867         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4868                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4869         else
4870                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4871         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4872         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4873         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4874         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4875
4876         ret = hns3_cmd_send(hw, &desc, 1);
4877         if (ret)
4878                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4879
4880         return ret;
4881 }
4882
4883 static int
4884 hns3_get_mac_link_status(struct hns3_hw *hw)
4885 {
4886         struct hns3_link_status_cmd *req;
4887         struct hns3_cmd_desc desc;
4888         int link_status;
4889         int ret;
4890
4891         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4892         ret = hns3_cmd_send(hw, &desc, 1);
4893         if (ret) {
4894                 hns3_err(hw, "get link status cmd failed %d", ret);
4895                 return RTE_ETH_LINK_DOWN;
4896         }
4897
4898         req = (struct hns3_link_status_cmd *)desc.data;
4899         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4900
4901         return !!link_status;
4902 }
4903
4904 static bool
4905 hns3_update_link_status(struct hns3_hw *hw)
4906 {
4907         int state;
4908
4909         state = hns3_get_mac_link_status(hw);
4910         if (state != hw->mac.link_status) {
4911                 hw->mac.link_status = state;
4912                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4913                 return true;
4914         }
4915
4916         return false;
4917 }
4918
4919 void
4920 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4921 {
4922         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4923         struct rte_eth_link new_link;
4924         int ret;
4925
4926         if (query)
4927                 hns3_update_port_link_info(dev);
4928
4929         memset(&new_link, 0, sizeof(new_link));
4930         hns3_setup_linkstatus(dev, &new_link);
4931
4932         ret = rte_eth_linkstatus_set(dev, &new_link);
4933         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4934                 hns3_start_report_lse(dev);
4935 }
4936
4937 static void
4938 hns3_service_handler(void *param)
4939 {
4940         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4941         struct hns3_adapter *hns = eth_dev->data->dev_private;
4942         struct hns3_hw *hw = &hns->hw;
4943
4944         if (!hns3_is_reset_pending(hns))
4945                 hns3_update_linkstatus_and_event(hw, true);
4946         else
4947                 hns3_warn(hw, "Cancel the query when reset is pending");
4948
4949         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4950 }
4951
4952 static int
4953 hns3_init_hardware(struct hns3_adapter *hns)
4954 {
4955         struct hns3_hw *hw = &hns->hw;
4956         int ret;
4957
4958         ret = hns3_map_tqp(hw);
4959         if (ret) {
4960                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4961                 return ret;
4962         }
4963
4964         ret = hns3_init_umv_space(hw);
4965         if (ret) {
4966                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4967                 return ret;
4968         }
4969
4970         ret = hns3_mac_init(hw);
4971         if (ret) {
4972                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4973                 goto err_mac_init;
4974         }
4975
4976         ret = hns3_init_mgr_tbl(hw);
4977         if (ret) {
4978                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4979                 goto err_mac_init;
4980         }
4981
4982         ret = hns3_promisc_init(hw);
4983         if (ret) {
4984                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4985                              ret);
4986                 goto err_mac_init;
4987         }
4988
4989         ret = hns3_init_vlan_config(hns);
4990         if (ret) {
4991                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4992                 goto err_mac_init;
4993         }
4994
4995         ret = hns3_dcb_init(hw);
4996         if (ret) {
4997                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4998                 goto err_mac_init;
4999         }
5000
5001         ret = hns3_init_fd_config(hns);
5002         if (ret) {
5003                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
5004                 goto err_mac_init;
5005         }
5006
5007         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
5008         if (ret) {
5009                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
5010                 goto err_mac_init;
5011         }
5012
5013         ret = hns3_config_gro(hw, false);
5014         if (ret) {
5015                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5016                 goto err_mac_init;
5017         }
5018
5019         /*
5020          * In the initialization clearing the all hardware mapping relationship
5021          * configurations between queues and interrupt vectors is needed, so
5022          * some error caused by the residual configurations, such as the
5023          * unexpected interrupt, can be avoid.
5024          */
5025         ret = hns3_init_ring_with_vector(hw);
5026         if (ret) {
5027                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5028                 goto err_mac_init;
5029         }
5030
5031         return 0;
5032
5033 err_mac_init:
5034         hns3_uninit_umv_space(hw);
5035         return ret;
5036 }
5037
5038 static int
5039 hns3_clear_hw(struct hns3_hw *hw)
5040 {
5041         struct hns3_cmd_desc desc;
5042         int ret;
5043
5044         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5045
5046         ret = hns3_cmd_send(hw, &desc, 1);
5047         if (ret && ret != -EOPNOTSUPP)
5048                 return ret;
5049
5050         return 0;
5051 }
5052
5053 static void
5054 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5055 {
5056         uint32_t val;
5057
5058         /*
5059          * The new firmware support report more hardware error types by
5060          * msix mode. These errors are defined as RAS errors in hardware
5061          * and belong to a different type from the MSI-x errors processed
5062          * by the network driver.
5063          *
5064          * Network driver should open the new error report on initialization.
5065          */
5066         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5067         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5068         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5069 }
5070
5071 static uint32_t
5072 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5073 {
5074         struct hns3_mac *mac = &hw->mac;
5075
5076         switch (mac->link_speed) {
5077         case RTE_ETH_SPEED_NUM_1G:
5078                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5079         case RTE_ETH_SPEED_NUM_10G:
5080                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5081         case RTE_ETH_SPEED_NUM_25G:
5082                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5083         case RTE_ETH_SPEED_NUM_40G:
5084                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5085         case RTE_ETH_SPEED_NUM_50G:
5086                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5087         case RTE_ETH_SPEED_NUM_100G:
5088                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5089         case RTE_ETH_SPEED_NUM_200G:
5090                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5091         default:
5092                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5093                 return 0;
5094         }
5095 }
5096
5097 /*
5098  * Validity of supported_speed for firber and copper media type can be
5099  * guaranteed by the following policy:
5100  * Copper:
5101  *       Although the initialization of the phy in the firmware may not be
5102  *       completed, the firmware can guarantees that the supported_speed is
5103  *       an valid value.
5104  * Firber:
5105  *       If the version of firmware supports the acitive query way of the
5106  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5107  *       through it. If unsupported, use the SFP's speed as the value of the
5108  *       supported_speed.
5109  */
5110 static int
5111 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5112 {
5113         struct hns3_adapter *hns = eth_dev->data->dev_private;
5114         struct hns3_hw *hw = &hns->hw;
5115         struct hns3_mac *mac = &hw->mac;
5116         int ret;
5117
5118         ret = hns3_update_link_info(eth_dev);
5119         if (ret)
5120                 return ret;
5121
5122         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5123                 /*
5124                  * Some firmware does not support the report of supported_speed,
5125                  * and only report the effective speed of SFP. In this case, it
5126                  * is necessary to use the SFP's speed as the supported_speed.
5127                  */
5128                 if (mac->supported_speed == 0)
5129                         mac->supported_speed =
5130                                 hns3_set_firber_default_support_speed(hw);
5131         }
5132
5133         return 0;
5134 }
5135
5136 static void
5137 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5138 {
5139         struct hns3_mac *mac = &hns->hw.mac;
5140
5141         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5142                 hns->pf.support_fc_autoneg = true;
5143                 return;
5144         }
5145
5146         /*
5147          * Flow control auto-negotiation requires the cooperation of the driver
5148          * and firmware. Currently, the optical port does not support flow
5149          * control auto-negotiation.
5150          */
5151         hns->pf.support_fc_autoneg = false;
5152 }
5153
5154 static int
5155 hns3_init_pf(struct rte_eth_dev *eth_dev)
5156 {
5157         struct rte_device *dev = eth_dev->device;
5158         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5159         struct hns3_adapter *hns = eth_dev->data->dev_private;
5160         struct hns3_hw *hw = &hns->hw;
5161         int ret;
5162
5163         PMD_INIT_FUNC_TRACE();
5164
5165         /* Get hardware io base address from pcie BAR2 IO space */
5166         hw->io_base = pci_dev->mem_resource[2].addr;
5167
5168         /* Firmware command queue initialize */
5169         ret = hns3_cmd_init_queue(hw);
5170         if (ret) {
5171                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5172                 goto err_cmd_init_queue;
5173         }
5174
5175         hns3_clear_all_event_cause(hw);
5176
5177         /* Firmware command initialize */
5178         ret = hns3_cmd_init(hw);
5179         if (ret) {
5180                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5181                 goto err_cmd_init;
5182         }
5183
5184         hns3_tx_push_init(eth_dev);
5185
5186         /*
5187          * To ensure that the hardware environment is clean during
5188          * initialization, the driver actively clear the hardware environment
5189          * during initialization, including PF and corresponding VFs' vlan, mac,
5190          * flow table configurations, etc.
5191          */
5192         ret = hns3_clear_hw(hw);
5193         if (ret) {
5194                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5195                 goto err_cmd_init;
5196         }
5197
5198         /* Hardware statistics of imissed registers cleared. */
5199         ret = hns3_update_imissed_stats(hw, true);
5200         if (ret) {
5201                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5202                 goto err_cmd_init;
5203         }
5204
5205         hns3_config_all_msix_error(hw, true);
5206
5207         ret = rte_intr_callback_register(pci_dev->intr_handle,
5208                                          hns3_interrupt_handler,
5209                                          eth_dev);
5210         if (ret) {
5211                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5212                 goto err_intr_callback_register;
5213         }
5214
5215         ret = hns3_ptp_init(hw);
5216         if (ret)
5217                 goto err_get_config;
5218
5219         /* Enable interrupt */
5220         rte_intr_enable(pci_dev->intr_handle);
5221         hns3_pf_enable_irq0(hw);
5222
5223         /* Get configuration */
5224         ret = hns3_get_configuration(hw);
5225         if (ret) {
5226                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5227                 goto err_get_config;
5228         }
5229
5230         ret = hns3_tqp_stats_init(hw);
5231         if (ret)
5232                 goto err_get_config;
5233
5234         ret = hns3_init_hardware(hns);
5235         if (ret) {
5236                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5237                 goto err_init_hw;
5238         }
5239
5240         /* Initialize flow director filter list & hash */
5241         ret = hns3_fdir_filter_init(hns);
5242         if (ret) {
5243                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5244                 goto err_fdir;
5245         }
5246
5247         hns3_rss_set_default_args(hw);
5248
5249         ret = hns3_enable_hw_error_intr(hns, true);
5250         if (ret) {
5251                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5252                              ret);
5253                 goto err_enable_intr;
5254         }
5255
5256         ret = hns3_get_port_supported_speed(eth_dev);
5257         if (ret) {
5258                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5259                              "by device, ret = %d.", ret);
5260                 goto err_supported_speed;
5261         }
5262
5263         hns3_get_fc_autoneg_capability(hns);
5264
5265         hns3_tm_conf_init(eth_dev);
5266
5267         return 0;
5268
5269 err_supported_speed:
5270         (void)hns3_enable_hw_error_intr(hns, false);
5271 err_enable_intr:
5272         hns3_fdir_filter_uninit(hns);
5273 err_fdir:
5274         hns3_uninit_umv_space(hw);
5275 err_init_hw:
5276         hns3_tqp_stats_uninit(hw);
5277 err_get_config:
5278         hns3_pf_disable_irq0(hw);
5279         rte_intr_disable(pci_dev->intr_handle);
5280         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5281                              eth_dev);
5282 err_intr_callback_register:
5283 err_cmd_init:
5284         hns3_cmd_uninit(hw);
5285         hns3_cmd_destroy_queue(hw);
5286 err_cmd_init_queue:
5287         hw->io_base = NULL;
5288
5289         return ret;
5290 }
5291
5292 static void
5293 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5294 {
5295         struct hns3_adapter *hns = eth_dev->data->dev_private;
5296         struct rte_device *dev = eth_dev->device;
5297         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5298         struct hns3_hw *hw = &hns->hw;
5299
5300         PMD_INIT_FUNC_TRACE();
5301
5302         hns3_tm_conf_uninit(eth_dev);
5303         hns3_enable_hw_error_intr(hns, false);
5304         hns3_rss_uninit(hns);
5305         (void)hns3_config_gro(hw, false);
5306         hns3_promisc_uninit(hw);
5307         hns3_flow_uninit(eth_dev);
5308         hns3_fdir_filter_uninit(hns);
5309         hns3_uninit_umv_space(hw);
5310         hns3_tqp_stats_uninit(hw);
5311         hns3_config_mac_tnl_int(hw, false);
5312         hns3_pf_disable_irq0(hw);
5313         rte_intr_disable(pci_dev->intr_handle);
5314         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
5315                              eth_dev);
5316         hns3_config_all_msix_error(hw, false);
5317         hns3_cmd_uninit(hw);
5318         hns3_cmd_destroy_queue(hw);
5319         hw->io_base = NULL;
5320 }
5321
5322 static uint32_t
5323 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5324 {
5325         uint32_t speed_bit;
5326
5327         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5328         case RTE_ETH_LINK_SPEED_10M:
5329                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5330                 break;
5331         case RTE_ETH_LINK_SPEED_10M_HD:
5332                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5333                 break;
5334         case RTE_ETH_LINK_SPEED_100M:
5335                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5336                 break;
5337         case RTE_ETH_LINK_SPEED_100M_HD:
5338                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5339                 break;
5340         case RTE_ETH_LINK_SPEED_1G:
5341                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5342                 break;
5343         default:
5344                 speed_bit = 0;
5345                 break;
5346         }
5347
5348         return speed_bit;
5349 }
5350
5351 static uint32_t
5352 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5353 {
5354         uint32_t speed_bit;
5355
5356         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
5357         case RTE_ETH_LINK_SPEED_1G:
5358                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5359                 break;
5360         case RTE_ETH_LINK_SPEED_10G:
5361                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5362                 break;
5363         case RTE_ETH_LINK_SPEED_25G:
5364                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5365                 break;
5366         case RTE_ETH_LINK_SPEED_40G:
5367                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5368                 break;
5369         case RTE_ETH_LINK_SPEED_50G:
5370                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5371                 break;
5372         case RTE_ETH_LINK_SPEED_100G:
5373                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5374                 break;
5375         case RTE_ETH_LINK_SPEED_200G:
5376                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5377                 break;
5378         default:
5379                 speed_bit = 0;
5380                 break;
5381         }
5382
5383         return speed_bit;
5384 }
5385
5386 static int
5387 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5388 {
5389         struct hns3_mac *mac = &hw->mac;
5390         uint32_t supported_speed = mac->supported_speed;
5391         uint32_t speed_bit = 0;
5392
5393         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5394                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5395         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5396                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5397
5398         if (!(speed_bit & supported_speed)) {
5399                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5400                          link_speeds);
5401                 return -EINVAL;
5402         }
5403
5404         return 0;
5405 }
5406
5407 static inline uint32_t
5408 hns3_get_link_speed(uint32_t link_speeds)
5409 {
5410         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
5411
5412         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
5413             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
5414                 speed = RTE_ETH_SPEED_NUM_10M;
5415         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
5416             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
5417                 speed = RTE_ETH_SPEED_NUM_100M;
5418         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
5419                 speed = RTE_ETH_SPEED_NUM_1G;
5420         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
5421                 speed = RTE_ETH_SPEED_NUM_10G;
5422         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
5423                 speed = RTE_ETH_SPEED_NUM_25G;
5424         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
5425                 speed = RTE_ETH_SPEED_NUM_40G;
5426         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
5427                 speed = RTE_ETH_SPEED_NUM_50G;
5428         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
5429                 speed = RTE_ETH_SPEED_NUM_100G;
5430         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
5431                 speed = RTE_ETH_SPEED_NUM_200G;
5432
5433         return speed;
5434 }
5435
5436 static uint8_t
5437 hns3_get_link_duplex(uint32_t link_speeds)
5438 {
5439         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
5440             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
5441                 return RTE_ETH_LINK_HALF_DUPLEX;
5442         else
5443                 return RTE_ETH_LINK_FULL_DUPLEX;
5444 }
5445
5446 static int
5447 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5448                                 struct hns3_set_link_speed_cfg *cfg)
5449 {
5450         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5451         struct hns3_phy_params_bd0_cmd *req;
5452         uint16_t i;
5453
5454         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5455                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5456                                           false);
5457                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5458         }
5459         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5460         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5461         req->autoneg = cfg->autoneg;
5462
5463         /*
5464          * The full speed capability is used to negotiate when
5465          * auto-negotiation is enabled.
5466          */
5467         if (cfg->autoneg) {
5468                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5469                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5470                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5471                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5472                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5473         } else {
5474                 req->speed = cfg->speed;
5475                 req->duplex = cfg->duplex;
5476         }
5477
5478         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5479 }
5480
5481 static int
5482 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5483 {
5484         struct hns3_config_auto_neg_cmd *req;
5485         struct hns3_cmd_desc desc;
5486         uint32_t flag = 0;
5487         int ret;
5488
5489         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5490
5491         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5492         if (enable)
5493                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5494         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5495
5496         ret = hns3_cmd_send(hw, &desc, 1);
5497         if (ret)
5498                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5499
5500         return ret;
5501 }
5502
5503 static int
5504 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5505                                struct hns3_set_link_speed_cfg *cfg)
5506 {
5507         int ret;
5508
5509         if (hw->mac.support_autoneg) {
5510                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5511                 if (ret) {
5512                         hns3_err(hw, "failed to configure auto-negotiation.");
5513                         return ret;
5514                 }
5515
5516                 /*
5517                  * To enable auto-negotiation, we only need to open the switch
5518                  * of auto-negotiation, then firmware sets all speed
5519                  * capabilities.
5520                  */
5521                 if (cfg->autoneg)
5522                         return 0;
5523         }
5524
5525         /*
5526          * Some hardware doesn't support auto-negotiation, but users may not
5527          * configure link_speeds (default 0), which means auto-negotiation.
5528          * In this case, a warning message need to be printed, instead of
5529          * an error.
5530          */
5531         if (cfg->autoneg) {
5532                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
5533                 return 0;
5534         }
5535
5536         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5537 }
5538
5539 static int
5540 hns3_set_port_link_speed(struct hns3_hw *hw,
5541                          struct hns3_set_link_speed_cfg *cfg)
5542 {
5543         int ret;
5544
5545         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5546 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5547                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5548                 if (pf->is_tmp_phy)
5549                         return 0;
5550 #endif
5551
5552                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5553                 if (ret) {
5554                         hns3_err(hw, "failed to set copper port link speed,"
5555                                  "ret = %d.", ret);
5556                         return ret;
5557                 }
5558         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5559                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5560                 if (ret) {
5561                         hns3_err(hw, "failed to set fiber port link speed,"
5562                                  "ret = %d.", ret);
5563                         return ret;
5564                 }
5565         }
5566
5567         return 0;
5568 }
5569
5570 static int
5571 hns3_apply_link_speed(struct hns3_hw *hw)
5572 {
5573         struct rte_eth_conf *conf = &hw->data->dev_conf;
5574         struct hns3_set_link_speed_cfg cfg;
5575
5576         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5577         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5578                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5579         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5580                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5581                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5582         }
5583
5584         return hns3_set_port_link_speed(hw, &cfg);
5585 }
5586
5587 static int
5588 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5589 {
5590         struct hns3_hw *hw = &hns->hw;
5591         bool link_en;
5592         int ret;
5593
5594         ret = hns3_update_queue_map_configure(hns);
5595         if (ret) {
5596                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5597                          ret);
5598                 return ret;
5599         }
5600
5601         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5602         ret = hns3_tm_conf_update(hw);
5603         if (ret) {
5604                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5605                 return ret;
5606         }
5607
5608         hns3_enable_rxd_adv_layout(hw);
5609
5610         ret = hns3_init_queues(hns, reset_queue);
5611         if (ret) {
5612                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5613                 return ret;
5614         }
5615
5616         link_en = hw->set_link_down ? false : true;
5617         ret = hns3_cfg_mac_mode(hw, link_en);
5618         if (ret) {
5619                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5620                 goto err_config_mac_mode;
5621         }
5622
5623         ret = hns3_apply_link_speed(hw);
5624         if (ret)
5625                 goto err_set_link_speed;
5626
5627         return 0;
5628
5629 err_set_link_speed:
5630         (void)hns3_cfg_mac_mode(hw, false);
5631
5632 err_config_mac_mode:
5633         hns3_dev_release_mbufs(hns);
5634         /*
5635          * Here is exception handling, hns3_reset_all_tqps will have the
5636          * corresponding error message if it is handled incorrectly, so it is
5637          * not necessary to check hns3_reset_all_tqps return value, here keep
5638          * ret as the error code causing the exception.
5639          */
5640         (void)hns3_reset_all_tqps(hns);
5641         return ret;
5642 }
5643
5644 static int
5645 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5646 {
5647         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5648         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5649         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5651         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5652         uint32_t intr_vector;
5653         uint16_t q_id;
5654         int ret;
5655
5656         /*
5657          * hns3 needs a separate interrupt to be used as event interrupt which
5658          * could not be shared with task queue pair, so KERNEL drivers need
5659          * support multiple interrupt vectors.
5660          */
5661         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5662             !rte_intr_cap_multiple(intr_handle))
5663                 return 0;
5664
5665         rte_intr_disable(intr_handle);
5666         intr_vector = hw->used_rx_queues;
5667         /* creates event fd for each intr vector when MSIX is used */
5668         if (rte_intr_efd_enable(intr_handle, intr_vector))
5669                 return -EINVAL;
5670
5671         /* Allocate vector list */
5672         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5673                                     hw->used_rx_queues)) {
5674                 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5675                          hw->used_rx_queues);
5676                 ret = -ENOMEM;
5677                 goto alloc_intr_vec_error;
5678         }
5679
5680         if (rte_intr_allow_others(intr_handle)) {
5681                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5682                 base = RTE_INTR_VEC_RXTX_OFFSET;
5683         }
5684
5685         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5686                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5687                                                  HNS3_RING_TYPE_RX, q_id);
5688                 if (ret)
5689                         goto bind_vector_error;
5690
5691                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
5692                         goto bind_vector_error;
5693                 /*
5694                  * If there are not enough efds (e.g. not enough interrupt),
5695                  * remaining queues will be bond to the last interrupt.
5696                  */
5697                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
5698                         vec++;
5699         }
5700         rte_intr_enable(intr_handle);
5701         return 0;
5702
5703 bind_vector_error:
5704         rte_intr_vec_list_free(intr_handle);
5705 alloc_intr_vec_error:
5706         rte_intr_efd_disable(intr_handle);
5707         return ret;
5708 }
5709
5710 static int
5711 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5712 {
5713         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5714         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5715         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5716         uint16_t q_id;
5717         int ret;
5718
5719         if (dev->data->dev_conf.intr_conf.rxq == 0)
5720                 return 0;
5721
5722         if (rte_intr_dp_is_en(intr_handle)) {
5723                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5724                         ret = hns3_bind_ring_with_vector(hw,
5725                                 rte_intr_vec_list_index_get(intr_handle,
5726                                                                    q_id),
5727                                 true, HNS3_RING_TYPE_RX, q_id);
5728                         if (ret)
5729                                 return ret;
5730                 }
5731         }
5732
5733         return 0;
5734 }
5735
5736 static void
5737 hns3_restore_filter(struct rte_eth_dev *dev)
5738 {
5739         hns3_restore_rss_filter(dev);
5740 }
5741
5742 static int
5743 hns3_dev_start(struct rte_eth_dev *dev)
5744 {
5745         struct hns3_adapter *hns = dev->data->dev_private;
5746         struct hns3_hw *hw = &hns->hw;
5747         bool old_state = hw->set_link_down;
5748         int ret;
5749
5750         PMD_INIT_FUNC_TRACE();
5751         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5752                 return -EBUSY;
5753
5754         rte_spinlock_lock(&hw->lock);
5755         hw->adapter_state = HNS3_NIC_STARTING;
5756
5757         /*
5758          * If the dev_set_link_down() API has been called, the "set_link_down"
5759          * flag can be cleared by dev_start() API. In addition, the flag should
5760          * also be cleared before calling hns3_do_start() so that MAC can be
5761          * enabled in dev_start stage.
5762          */
5763         hw->set_link_down = false;
5764         ret = hns3_do_start(hns, true);
5765         if (ret)
5766                 goto do_start_fail;
5767
5768         ret = hns3_map_rx_interrupt(dev);
5769         if (ret)
5770                 goto map_rx_inter_err;
5771
5772         /*
5773          * There are three register used to control the status of a TQP
5774          * (contains a pair of Tx queue and Rx queue) in the new version network
5775          * engine. One is used to control the enabling of Tx queue, the other is
5776          * used to control the enabling of Rx queue, and the last is the master
5777          * switch used to control the enabling of the tqp. The Tx register and
5778          * TQP register must be enabled at the same time to enable a Tx queue.
5779          * The same applies to the Rx queue. For the older network engine, this
5780          * function only refresh the enabled flag, and it is used to update the
5781          * status of queue in the dpdk framework.
5782          */
5783         ret = hns3_start_all_txqs(dev);
5784         if (ret)
5785                 goto map_rx_inter_err;
5786
5787         ret = hns3_start_all_rxqs(dev);
5788         if (ret)
5789                 goto start_all_rxqs_fail;
5790
5791         hw->adapter_state = HNS3_NIC_STARTED;
5792         rte_spinlock_unlock(&hw->lock);
5793
5794         hns3_rx_scattered_calc(dev);
5795         hns3_set_rxtx_function(dev);
5796         hns3_mp_req_start_rxtx(dev);
5797
5798         hns3_restore_filter(dev);
5799
5800         /* Enable interrupt of all rx queues before enabling queues */
5801         hns3_dev_all_rx_queue_intr_enable(hw, true);
5802
5803         /*
5804          * After finished the initialization, enable tqps to receive/transmit
5805          * packets and refresh all queue status.
5806          */
5807         hns3_start_tqps(hw);
5808
5809         hns3_tm_dev_start_proc(hw);
5810
5811         if (dev->data->dev_conf.intr_conf.lsc != 0)
5812                 hns3_dev_link_update(dev, 0);
5813         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5814
5815         hns3_info(hw, "hns3 dev start successful!");
5816
5817         return 0;
5818
5819 start_all_rxqs_fail:
5820         hns3_stop_all_txqs(dev);
5821 map_rx_inter_err:
5822         (void)hns3_do_stop(hns);
5823 do_start_fail:
5824         hw->set_link_down = old_state;
5825         hw->adapter_state = HNS3_NIC_CONFIGURED;
5826         rte_spinlock_unlock(&hw->lock);
5827
5828         return ret;
5829 }
5830
5831 static int
5832 hns3_do_stop(struct hns3_adapter *hns)
5833 {
5834         struct hns3_hw *hw = &hns->hw;
5835         int ret;
5836
5837         /*
5838          * The "hns3_do_stop" function will also be called by .stop_service to
5839          * prepare reset. At the time of global or IMP reset, the command cannot
5840          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5841          * accessed during the reset process. So the mbuf can not be released
5842          * during reset and is required to be released after the reset is
5843          * completed.
5844          */
5845         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5846                 hns3_dev_release_mbufs(hns);
5847
5848         ret = hns3_cfg_mac_mode(hw, false);
5849         if (ret)
5850                 return ret;
5851         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5852
5853         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5854                 hns3_configure_all_mac_addr(hns, true);
5855                 ret = hns3_reset_all_tqps(hns);
5856                 if (ret) {
5857                         hns3_err(hw, "failed to reset all queues ret = %d.",
5858                                  ret);
5859                         return ret;
5860                 }
5861         }
5862
5863         return 0;
5864 }
5865
5866 static void
5867 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5868 {
5869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5870         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5871         struct hns3_adapter *hns = dev->data->dev_private;
5872         struct hns3_hw *hw = &hns->hw;
5873         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5874         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5875         uint16_t q_id;
5876
5877         if (dev->data->dev_conf.intr_conf.rxq == 0)
5878                 return;
5879
5880         /* unmap the ring with vector */
5881         if (rte_intr_allow_others(intr_handle)) {
5882                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5883                 base = RTE_INTR_VEC_RXTX_OFFSET;
5884         }
5885         if (rte_intr_dp_is_en(intr_handle)) {
5886                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5887                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5888                                                          HNS3_RING_TYPE_RX,
5889                                                          q_id);
5890                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
5891                                                                         - 1)
5892                                 vec++;
5893                 }
5894         }
5895         /* Clean datapath event and queue/vec mapping */
5896         rte_intr_efd_disable(intr_handle);
5897         rte_intr_vec_list_free(intr_handle);
5898 }
5899
5900 static int
5901 hns3_dev_stop(struct rte_eth_dev *dev)
5902 {
5903         struct hns3_adapter *hns = dev->data->dev_private;
5904         struct hns3_hw *hw = &hns->hw;
5905
5906         PMD_INIT_FUNC_TRACE();
5907         dev->data->dev_started = 0;
5908
5909         hw->adapter_state = HNS3_NIC_STOPPING;
5910         hns3_set_rxtx_function(dev);
5911         rte_wmb();
5912         /* Disable datapath on secondary process. */
5913         hns3_mp_req_stop_rxtx(dev);
5914         /* Prevent crashes when queues are still in use. */
5915         rte_delay_ms(hw->cfg_max_queues);
5916
5917         rte_spinlock_lock(&hw->lock);
5918         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5919                 hns3_tm_dev_stop_proc(hw);
5920                 hns3_config_mac_tnl_int(hw, false);
5921                 hns3_stop_tqps(hw);
5922                 hns3_do_stop(hns);
5923                 hns3_unmap_rx_interrupt(dev);
5924                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5925         }
5926         hns3_rx_scattered_reset(dev);
5927         rte_eal_alarm_cancel(hns3_service_handler, dev);
5928         hns3_stop_report_lse(dev);
5929         rte_spinlock_unlock(&hw->lock);
5930
5931         return 0;
5932 }
5933
5934 static int
5935 hns3_dev_close(struct rte_eth_dev *eth_dev)
5936 {
5937         struct hns3_adapter *hns = eth_dev->data->dev_private;
5938         struct hns3_hw *hw = &hns->hw;
5939         int ret = 0;
5940
5941         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5942                 return 0;
5943
5944         if (hw->adapter_state == HNS3_NIC_STARTED)
5945                 ret = hns3_dev_stop(eth_dev);
5946
5947         hw->adapter_state = HNS3_NIC_CLOSING;
5948         hns3_reset_abort(hns);
5949         hw->adapter_state = HNS3_NIC_CLOSED;
5950
5951         hns3_configure_all_mc_mac_addr(hns, true);
5952         hns3_remove_all_vlan_table(hns);
5953         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5954         hns3_uninit_pf(eth_dev);
5955         hns3_free_all_queues(eth_dev);
5956         rte_free(hw->reset.wait_data);
5957         hns3_mp_uninit_primary();
5958         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5959
5960         return ret;
5961 }
5962
5963 static void
5964 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5965                                    bool *tx_pause)
5966 {
5967         struct hns3_mac *mac = &hw->mac;
5968         uint32_t advertising = mac->advertising;
5969         uint32_t lp_advertising = mac->lp_advertising;
5970         *rx_pause = false;
5971         *tx_pause = false;
5972
5973         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5974                 *rx_pause = true;
5975                 *tx_pause = true;
5976         } else if (advertising & lp_advertising &
5977                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5978                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5979                         *rx_pause = true;
5980                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5981                         *tx_pause = true;
5982         }
5983 }
5984
5985 static enum hns3_fc_mode
5986 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5987 {
5988         enum hns3_fc_mode current_mode;
5989         bool rx_pause = false;
5990         bool tx_pause = false;
5991
5992         switch (hw->mac.media_type) {
5993         case HNS3_MEDIA_TYPE_COPPER:
5994                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5995                 break;
5996
5997         /*
5998          * Flow control auto-negotiation is not supported for fiber and
5999          * backpalne media type.
6000          */
6001         case HNS3_MEDIA_TYPE_FIBER:
6002         case HNS3_MEDIA_TYPE_BACKPLANE:
6003                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
6004                 current_mode = hw->requested_fc_mode;
6005                 goto out;
6006         default:
6007                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
6008                          hw->mac.media_type);
6009                 current_mode = HNS3_FC_NONE;
6010                 goto out;
6011         }
6012
6013         if (rx_pause && tx_pause)
6014                 current_mode = HNS3_FC_FULL;
6015         else if (rx_pause)
6016                 current_mode = HNS3_FC_RX_PAUSE;
6017         else if (tx_pause)
6018                 current_mode = HNS3_FC_TX_PAUSE;
6019         else
6020                 current_mode = HNS3_FC_NONE;
6021
6022 out:
6023         return current_mode;
6024 }
6025
6026 static enum hns3_fc_mode
6027 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6028 {
6029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6030         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6031         struct hns3_mac *mac = &hw->mac;
6032
6033         /*
6034          * When the flow control mode is obtained, the device may not complete
6035          * auto-negotiation. It is necessary to wait for link establishment.
6036          */
6037         (void)hns3_dev_link_update(dev, 1);
6038
6039         /*
6040          * If the link auto-negotiation of the nic is disabled, or the flow
6041          * control auto-negotiation is not supported, the forced flow control
6042          * mode is used.
6043          */
6044         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6045                 return hw->requested_fc_mode;
6046
6047         return hns3_get_autoneg_fc_mode(hw);
6048 }
6049
6050 static int
6051 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6052 {
6053         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6055         enum hns3_fc_mode current_mode;
6056
6057         current_mode = hns3_get_current_fc_mode(dev);
6058         switch (current_mode) {
6059         case HNS3_FC_FULL:
6060                 fc_conf->mode = RTE_ETH_FC_FULL;
6061                 break;
6062         case HNS3_FC_TX_PAUSE:
6063                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
6064                 break;
6065         case HNS3_FC_RX_PAUSE:
6066                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
6067                 break;
6068         case HNS3_FC_NONE:
6069         default:
6070                 fc_conf->mode = RTE_ETH_FC_NONE;
6071                 break;
6072         }
6073
6074         fc_conf->pause_time = pf->pause_time;
6075         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6076
6077         return 0;
6078 }
6079
6080 static int
6081 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6082 {
6083         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6084
6085         if (!pf->support_fc_autoneg) {
6086                 if (autoneg != 0) {
6087                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6088                         return -EOPNOTSUPP;
6089                 }
6090
6091                 /*
6092                  * Flow control auto-negotiation of the NIC is not supported,
6093                  * but other auto-negotiation features may be supported.
6094                  */
6095                 if (autoneg != hw->mac.link_autoneg) {
6096                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6097                         return -EOPNOTSUPP;
6098                 }
6099
6100                 return 0;
6101         }
6102
6103         /*
6104          * If flow control auto-negotiation of the NIC is supported, all
6105          * auto-negotiation features are supported.
6106          */
6107         if (autoneg != hw->mac.link_autoneg) {
6108                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6109                 return -EOPNOTSUPP;
6110         }
6111
6112         return 0;
6113 }
6114
6115 static int
6116 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6117 {
6118         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6119         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6120         int ret;
6121
6122         if (fc_conf->high_water || fc_conf->low_water ||
6123             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6124                 hns3_err(hw, "Unsupported flow control settings specified, "
6125                          "high_water(%u), low_water(%u), send_xon(%u) and "
6126                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6127                          fc_conf->high_water, fc_conf->low_water,
6128                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6129                 return -EINVAL;
6130         }
6131
6132         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6133         if (ret)
6134                 return ret;
6135
6136         if (!fc_conf->pause_time) {
6137                 hns3_err(hw, "Invalid pause time %u setting.",
6138                          fc_conf->pause_time);
6139                 return -EINVAL;
6140         }
6141
6142         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6143             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6144                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6145                          "current_fc_status = %d", hw->current_fc_status);
6146                 return -EOPNOTSUPP;
6147         }
6148
6149         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
6150                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6151                 return -EOPNOTSUPP;
6152         }
6153
6154         rte_spinlock_lock(&hw->lock);
6155         ret = hns3_fc_enable(dev, fc_conf);
6156         rte_spinlock_unlock(&hw->lock);
6157
6158         return ret;
6159 }
6160
6161 static int
6162 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6163                             struct rte_eth_pfc_conf *pfc_conf)
6164 {
6165         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         int ret;
6167
6168         if (!hns3_dev_get_support(hw, DCB)) {
6169                 hns3_err(hw, "This port does not support dcb configurations.");
6170                 return -EOPNOTSUPP;
6171         }
6172
6173         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6174             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6175                 hns3_err(hw, "Unsupported flow control settings specified, "
6176                          "high_water(%u), low_water(%u), send_xon(%u) and "
6177                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6178                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6179                          pfc_conf->fc.send_xon,
6180                          pfc_conf->fc.mac_ctrl_frame_fwd);
6181                 return -EINVAL;
6182         }
6183         if (pfc_conf->fc.autoneg) {
6184                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6185                 return -EINVAL;
6186         }
6187         if (pfc_conf->fc.pause_time == 0) {
6188                 hns3_err(hw, "Invalid pause time %u setting.",
6189                          pfc_conf->fc.pause_time);
6190                 return -EINVAL;
6191         }
6192
6193         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6194             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6195                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6196                              "current_fc_status = %d", hw->current_fc_status);
6197                 return -EOPNOTSUPP;
6198         }
6199
6200         rte_spinlock_lock(&hw->lock);
6201         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6202         rte_spinlock_unlock(&hw->lock);
6203
6204         return ret;
6205 }
6206
6207 static int
6208 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6209 {
6210         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6211         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6212         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6213         int i;
6214
6215         rte_spinlock_lock(&hw->lock);
6216         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
6217                 dcb_info->nb_tcs = pf->local_max_tc;
6218         else
6219                 dcb_info->nb_tcs = 1;
6220
6221         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6222                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6223         for (i = 0; i < dcb_info->nb_tcs; i++)
6224                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6225
6226         for (i = 0; i < hw->num_tc; i++) {
6227                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6228                 dcb_info->tc_queue.tc_txq[0][i].base =
6229                                                 hw->tc_queue[i].tqp_offset;
6230                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6231                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6232                                                 hw->tc_queue[i].tqp_count;
6233         }
6234         rte_spinlock_unlock(&hw->lock);
6235
6236         return 0;
6237 }
6238
6239 static int
6240 hns3_reinit_dev(struct hns3_adapter *hns)
6241 {
6242         struct hns3_hw *hw = &hns->hw;
6243         int ret;
6244
6245         ret = hns3_cmd_init(hw);
6246         if (ret) {
6247                 hns3_err(hw, "Failed to init cmd: %d", ret);
6248                 return ret;
6249         }
6250
6251         ret = hns3_reset_all_tqps(hns);
6252         if (ret) {
6253                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6254                 return ret;
6255         }
6256
6257         ret = hns3_init_hardware(hns);
6258         if (ret) {
6259                 hns3_err(hw, "Failed to init hardware: %d", ret);
6260                 return ret;
6261         }
6262
6263         ret = hns3_enable_hw_error_intr(hns, true);
6264         if (ret) {
6265                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6266                              ret);
6267                 return ret;
6268         }
6269         hns3_info(hw, "Reset done, driver initialization finished.");
6270
6271         return 0;
6272 }
6273
6274 static bool
6275 is_pf_reset_done(struct hns3_hw *hw)
6276 {
6277         uint32_t val, reg, reg_bit;
6278
6279         switch (hw->reset.level) {
6280         case HNS3_IMP_RESET:
6281                 reg = HNS3_GLOBAL_RESET_REG;
6282                 reg_bit = HNS3_IMP_RESET_BIT;
6283                 break;
6284         case HNS3_GLOBAL_RESET:
6285                 reg = HNS3_GLOBAL_RESET_REG;
6286                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6287                 break;
6288         case HNS3_FUNC_RESET:
6289                 reg = HNS3_FUN_RST_ING;
6290                 reg_bit = HNS3_FUN_RST_ING_B;
6291                 break;
6292         case HNS3_FLR_RESET:
6293         default:
6294                 hns3_err(hw, "Wait for unsupported reset level: %d",
6295                          hw->reset.level);
6296                 return true;
6297         }
6298         val = hns3_read_dev(hw, reg);
6299         if (hns3_get_bit(val, reg_bit))
6300                 return false;
6301         else
6302                 return true;
6303 }
6304
6305 bool
6306 hns3_is_reset_pending(struct hns3_adapter *hns)
6307 {
6308         struct hns3_hw *hw = &hns->hw;
6309         enum hns3_reset_level reset;
6310
6311         hns3_check_event_cause(hns, NULL);
6312         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6313         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6314             hw->reset.level < reset) {
6315                 hns3_warn(hw, "High level reset %d is pending", reset);
6316                 return true;
6317         }
6318         reset = hns3_get_reset_level(hns, &hw->reset.request);
6319         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6320             hw->reset.level < reset) {
6321                 hns3_warn(hw, "High level reset %d is request", reset);
6322                 return true;
6323         }
6324         return false;
6325 }
6326
6327 static int
6328 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6329 {
6330         struct hns3_hw *hw = &hns->hw;
6331         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6332         struct timeval tv;
6333
6334         if (wait_data->result == HNS3_WAIT_SUCCESS)
6335                 return 0;
6336         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6337                 hns3_clock_gettime(&tv);
6338                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6339                           tv.tv_sec, tv.tv_usec);
6340                 return -ETIME;
6341         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6342                 return -EAGAIN;
6343
6344         wait_data->hns = hns;
6345         wait_data->check_completion = is_pf_reset_done;
6346         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6347                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
6348         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6349         wait_data->count = HNS3_RESET_WAIT_CNT;
6350         wait_data->result = HNS3_WAIT_REQUEST;
6351         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6352         return -EAGAIN;
6353 }
6354
6355 static int
6356 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6357 {
6358         struct hns3_cmd_desc desc;
6359         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6360
6361         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6362         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6363         req->fun_reset_vfid = func_id;
6364
6365         return hns3_cmd_send(hw, &desc, 1);
6366 }
6367
6368 static int
6369 hns3_imp_reset_cmd(struct hns3_hw *hw)
6370 {
6371         struct hns3_cmd_desc desc;
6372
6373         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6374         desc.data[0] = 0xeedd;
6375
6376         return hns3_cmd_send(hw, &desc, 1);
6377 }
6378
6379 static void
6380 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6381 {
6382         struct hns3_hw *hw = &hns->hw;
6383         struct timeval tv;
6384         uint32_t val;
6385
6386         hns3_clock_gettime(&tv);
6387         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6388             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6389                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6390                           tv.tv_sec, tv.tv_usec);
6391                 return;
6392         }
6393
6394         switch (reset_level) {
6395         case HNS3_IMP_RESET:
6396                 hns3_imp_reset_cmd(hw);
6397                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6398                           tv.tv_sec, tv.tv_usec);
6399                 break;
6400         case HNS3_GLOBAL_RESET:
6401                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6402                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6403                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6404                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6405                           tv.tv_sec, tv.tv_usec);
6406                 break;
6407         case HNS3_FUNC_RESET:
6408                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6409                           tv.tv_sec, tv.tv_usec);
6410                 /* schedule again to check later */
6411                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6412                 hns3_schedule_reset(hns);
6413                 break;
6414         default:
6415                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6416                 return;
6417         }
6418         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6419 }
6420
6421 static enum hns3_reset_level
6422 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6423 {
6424         struct hns3_hw *hw = &hns->hw;
6425         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6426
6427         /* Return the highest priority reset level amongst all */
6428         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6429                 reset_level = HNS3_IMP_RESET;
6430         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6431                 reset_level = HNS3_GLOBAL_RESET;
6432         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6433                 reset_level = HNS3_FUNC_RESET;
6434         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6435                 reset_level = HNS3_FLR_RESET;
6436
6437         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6438                 return HNS3_NONE_RESET;
6439
6440         return reset_level;
6441 }
6442
6443 static void
6444 hns3_record_imp_error(struct hns3_adapter *hns)
6445 {
6446         struct hns3_hw *hw = &hns->hw;
6447         uint32_t reg_val;
6448
6449         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6450         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6451                 hns3_warn(hw, "Detected IMP RD poison!");
6452                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6453                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6454         }
6455
6456         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6457                 hns3_warn(hw, "Detected IMP CMDQ error!");
6458                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6459                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6460         }
6461 }
6462
6463 static int
6464 hns3_prepare_reset(struct hns3_adapter *hns)
6465 {
6466         struct hns3_hw *hw = &hns->hw;
6467         uint32_t reg_val;
6468         int ret;
6469
6470         switch (hw->reset.level) {
6471         case HNS3_FUNC_RESET:
6472                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6473                 if (ret)
6474                         return ret;
6475
6476                 /*
6477                  * After performaning pf reset, it is not necessary to do the
6478                  * mailbox handling or send any command to firmware, because
6479                  * any mailbox handling or command to firmware is only valid
6480                  * after hns3_cmd_init is called.
6481                  */
6482                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6483                 hw->reset.stats.request_cnt++;
6484                 break;
6485         case HNS3_IMP_RESET:
6486                 hns3_record_imp_error(hns);
6487                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6488                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6489                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6490                 break;
6491         default:
6492                 break;
6493         }
6494         return 0;
6495 }
6496
6497 static int
6498 hns3_set_rst_done(struct hns3_hw *hw)
6499 {
6500         struct hns3_pf_rst_done_cmd *req;
6501         struct hns3_cmd_desc desc;
6502
6503         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6504         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6505         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6506         return hns3_cmd_send(hw, &desc, 1);
6507 }
6508
6509 static int
6510 hns3_stop_service(struct hns3_adapter *hns)
6511 {
6512         struct hns3_hw *hw = &hns->hw;
6513         struct rte_eth_dev *eth_dev;
6514
6515         eth_dev = &rte_eth_devices[hw->data->port_id];
6516         hw->mac.link_status = RTE_ETH_LINK_DOWN;
6517         if (hw->adapter_state == HNS3_NIC_STARTED) {
6518                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6519                 hns3_update_linkstatus_and_event(hw, false);
6520         }
6521
6522         hns3_set_rxtx_function(eth_dev);
6523         rte_wmb();
6524         /* Disable datapath on secondary process. */
6525         hns3_mp_req_stop_rxtx(eth_dev);
6526         rte_delay_ms(hw->cfg_max_queues);
6527
6528         rte_spinlock_lock(&hw->lock);
6529         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6530             hw->adapter_state == HNS3_NIC_STOPPING) {
6531                 hns3_enable_all_queues(hw, false);
6532                 hns3_do_stop(hns);
6533                 hw->reset.mbuf_deferred_free = true;
6534         } else
6535                 hw->reset.mbuf_deferred_free = false;
6536
6537         /*
6538          * It is cumbersome for hardware to pick-and-choose entries for deletion
6539          * from table space. Hence, for function reset software intervention is
6540          * required to delete the entries
6541          */
6542         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6543                 hns3_configure_all_mc_mac_addr(hns, true);
6544         rte_spinlock_unlock(&hw->lock);
6545
6546         return 0;
6547 }
6548
6549 static int
6550 hns3_start_service(struct hns3_adapter *hns)
6551 {
6552         struct hns3_hw *hw = &hns->hw;
6553         struct rte_eth_dev *eth_dev;
6554
6555         if (hw->reset.level == HNS3_IMP_RESET ||
6556             hw->reset.level == HNS3_GLOBAL_RESET)
6557                 hns3_set_rst_done(hw);
6558         eth_dev = &rte_eth_devices[hw->data->port_id];
6559         hns3_set_rxtx_function(eth_dev);
6560         hns3_mp_req_start_rxtx(eth_dev);
6561         if (hw->adapter_state == HNS3_NIC_STARTED) {
6562                 /*
6563                  * This API parent function already hold the hns3_hw.lock, the
6564                  * hns3_service_handler may report lse, in bonding application
6565                  * it will call driver's ops which may acquire the hns3_hw.lock
6566                  * again, thus lead to deadlock.
6567                  * We defer calls hns3_service_handler to avoid the deadlock.
6568                  */
6569                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6570                                   hns3_service_handler, eth_dev);
6571
6572                 /* Enable interrupt of all rx queues before enabling queues */
6573                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6574                 /*
6575                  * Enable state of each rxq and txq will be recovered after
6576                  * reset, so we need to restore them before enable all tqps;
6577                  */
6578                 hns3_restore_tqp_enable_state(hw);
6579                 /*
6580                  * When finished the initialization, enable queues to receive
6581                  * and transmit packets.
6582                  */
6583                 hns3_enable_all_queues(hw, true);
6584         }
6585
6586         return 0;
6587 }
6588
6589 static int
6590 hns3_restore_conf(struct hns3_adapter *hns)
6591 {
6592         struct hns3_hw *hw = &hns->hw;
6593         int ret;
6594
6595         ret = hns3_configure_all_mac_addr(hns, false);
6596         if (ret)
6597                 return ret;
6598
6599         ret = hns3_configure_all_mc_mac_addr(hns, false);
6600         if (ret)
6601                 goto err_mc_mac;
6602
6603         ret = hns3_dev_promisc_restore(hns);
6604         if (ret)
6605                 goto err_promisc;
6606
6607         ret = hns3_restore_vlan_table(hns);
6608         if (ret)
6609                 goto err_promisc;
6610
6611         ret = hns3_restore_vlan_conf(hns);
6612         if (ret)
6613                 goto err_promisc;
6614
6615         ret = hns3_restore_all_fdir_filter(hns);
6616         if (ret)
6617                 goto err_promisc;
6618
6619         ret = hns3_restore_ptp(hns);
6620         if (ret)
6621                 goto err_promisc;
6622
6623         ret = hns3_restore_rx_interrupt(hw);
6624         if (ret)
6625                 goto err_promisc;
6626
6627         ret = hns3_restore_gro_conf(hw);
6628         if (ret)
6629                 goto err_promisc;
6630
6631         ret = hns3_restore_fec(hw);
6632         if (ret)
6633                 goto err_promisc;
6634
6635         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6636                 ret = hns3_do_start(hns, false);
6637                 if (ret)
6638                         goto err_promisc;
6639                 hns3_info(hw, "hns3 dev restart successful!");
6640         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6641                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6642         return 0;
6643
6644 err_promisc:
6645         hns3_configure_all_mc_mac_addr(hns, true);
6646 err_mc_mac:
6647         hns3_configure_all_mac_addr(hns, true);
6648         return ret;
6649 }
6650
6651 static void
6652 hns3_reset_service(void *param)
6653 {
6654         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6655         struct hns3_hw *hw = &hns->hw;
6656         enum hns3_reset_level reset_level;
6657         struct timeval tv_delta;
6658         struct timeval tv_start;
6659         struct timeval tv;
6660         uint64_t msec;
6661         int ret;
6662
6663         /*
6664          * The interrupt is not triggered within the delay time.
6665          * The interrupt may have been lost. It is necessary to handle
6666          * the interrupt to recover from the error.
6667          */
6668         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6669                             SCHEDULE_DEFERRED) {
6670                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6671                                   __ATOMIC_RELAXED);
6672                 hns3_err(hw, "Handling interrupts in delayed tasks");
6673                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6674                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6675                 if (reset_level == HNS3_NONE_RESET) {
6676                         hns3_err(hw, "No reset level is set, try IMP reset");
6677                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6678                 }
6679         }
6680         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6681
6682         /*
6683          * Check if there is any ongoing reset in the hardware. This status can
6684          * be checked from reset_pending. If there is then, we need to wait for
6685          * hardware to complete reset.
6686          *    a. If we are able to figure out in reasonable time that hardware
6687          *       has fully resetted then, we can proceed with driver, client
6688          *       reset.
6689          *    b. else, we can come back later to check this status so re-sched
6690          *       now.
6691          */
6692         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6693         if (reset_level != HNS3_NONE_RESET) {
6694                 hns3_clock_gettime(&tv_start);
6695                 ret = hns3_reset_process(hns, reset_level);
6696                 hns3_clock_gettime(&tv);
6697                 timersub(&tv, &tv_start, &tv_delta);
6698                 msec = hns3_clock_calctime_ms(&tv_delta);
6699                 if (msec > HNS3_RESET_PROCESS_MS)
6700                         hns3_err(hw, "%d handle long time delta %" PRIu64
6701                                      " ms time=%ld.%.6ld",
6702                                  hw->reset.level, msec,
6703                                  tv.tv_sec, tv.tv_usec);
6704                 if (ret == -EAGAIN)
6705                         return;
6706         }
6707
6708         /* Check if we got any *new* reset requests to be honored */
6709         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6710         if (reset_level != HNS3_NONE_RESET)
6711                 hns3_msix_process(hns, reset_level);
6712 }
6713
6714 static unsigned int
6715 hns3_get_speed_capa_num(uint16_t device_id)
6716 {
6717         unsigned int num;
6718
6719         switch (device_id) {
6720         case HNS3_DEV_ID_25GE:
6721         case HNS3_DEV_ID_25GE_RDMA:
6722                 num = 2;
6723                 break;
6724         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6725         case HNS3_DEV_ID_200G_RDMA:
6726                 num = 1;
6727                 break;
6728         default:
6729                 num = 0;
6730                 break;
6731         }
6732
6733         return num;
6734 }
6735
6736 static int
6737 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6738                         uint16_t device_id)
6739 {
6740         switch (device_id) {
6741         case HNS3_DEV_ID_25GE:
6742         /* fallthrough */
6743         case HNS3_DEV_ID_25GE_RDMA:
6744                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6745                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6746
6747                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6748                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6749                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6750                 break;
6751         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6752                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6753                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6754                 break;
6755         case HNS3_DEV_ID_200G_RDMA:
6756                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6757                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6758                 break;
6759         default:
6760                 return -ENOTSUP;
6761         }
6762
6763         return 0;
6764 }
6765
6766 static int
6767 hns3_fec_get_capability(struct rte_eth_dev *dev,
6768                         struct rte_eth_fec_capa *speed_fec_capa,
6769                         unsigned int num)
6770 {
6771         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6773         uint16_t device_id = pci_dev->id.device_id;
6774         unsigned int capa_num;
6775         int ret;
6776
6777         capa_num = hns3_get_speed_capa_num(device_id);
6778         if (capa_num == 0) {
6779                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6780                          device_id);
6781                 return -ENOTSUP;
6782         }
6783
6784         if (speed_fec_capa == NULL || num < capa_num)
6785                 return capa_num;
6786
6787         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6788         if (ret)
6789                 return -ENOTSUP;
6790
6791         return capa_num;
6792 }
6793
6794 static int
6795 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6796 {
6797         struct hns3_config_fec_cmd *req;
6798         struct hns3_cmd_desc desc;
6799         int ret;
6800
6801         /*
6802          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6803          * in device of link speed
6804          * below 10 Gbps.
6805          */
6806         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6807                 *state = 0;
6808                 return 0;
6809         }
6810
6811         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6812         req = (struct hns3_config_fec_cmd *)desc.data;
6813         ret = hns3_cmd_send(hw, &desc, 1);
6814         if (ret) {
6815                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6816                          ret);
6817                 return ret;
6818         }
6819
6820         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6821         return 0;
6822 }
6823
6824 static int
6825 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6826 {
6827         struct hns3_sfp_info_cmd *resp;
6828         uint32_t tmp_fec_capa;
6829         uint8_t auto_state;
6830         struct hns3_cmd_desc desc;
6831         int ret;
6832
6833         /*
6834          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6835          * configured FEC mode is returned.
6836          * If link is up, current FEC mode is returned.
6837          */
6838         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6839                 ret = get_current_fec_auto_state(hw, &auto_state);
6840                 if (ret)
6841                         return ret;
6842
6843                 if (auto_state == 0x1) {
6844                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6845                         return 0;
6846                 }
6847         }
6848
6849         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6850         resp = (struct hns3_sfp_info_cmd *)desc.data;
6851         resp->query_type = HNS3_ACTIVE_QUERY;
6852
6853         ret = hns3_cmd_send(hw, &desc, 1);
6854         if (ret == -EOPNOTSUPP) {
6855                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6856                 return ret;
6857         } else if (ret) {
6858                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6859                 return ret;
6860         }
6861
6862         /*
6863          * FEC mode order defined in hns3 hardware is inconsistend with
6864          * that defined in the ethdev library. So the sequence needs
6865          * to be converted.
6866          */
6867         switch (resp->active_fec) {
6868         case HNS3_HW_FEC_MODE_NOFEC:
6869                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6870                 break;
6871         case HNS3_HW_FEC_MODE_BASER:
6872                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6873                 break;
6874         case HNS3_HW_FEC_MODE_RS:
6875                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6876                 break;
6877         default:
6878                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6879                 break;
6880         }
6881
6882         *fec_capa = tmp_fec_capa;
6883         return 0;
6884 }
6885
6886 static int
6887 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6888 {
6889         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6890
6891         return hns3_fec_get_internal(hw, fec_capa);
6892 }
6893
6894 static int
6895 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6896 {
6897         struct hns3_config_fec_cmd *req;
6898         struct hns3_cmd_desc desc;
6899         int ret;
6900
6901         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6902
6903         req = (struct hns3_config_fec_cmd *)desc.data;
6904         switch (mode) {
6905         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6906                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6907                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6908                 break;
6909         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6910                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6911                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6912                 break;
6913         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6914                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6915                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6916                 break;
6917         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6918                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6919                 break;
6920         default:
6921                 return 0;
6922         }
6923         ret = hns3_cmd_send(hw, &desc, 1);
6924         if (ret)
6925                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6926
6927         return ret;
6928 }
6929
6930 static uint32_t
6931 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6932 {
6933         struct hns3_mac *mac = &hw->mac;
6934         uint32_t cur_capa;
6935
6936         switch (mac->link_speed) {
6937         case RTE_ETH_SPEED_NUM_10G:
6938                 cur_capa = fec_capa[1].capa;
6939                 break;
6940         case RTE_ETH_SPEED_NUM_25G:
6941         case RTE_ETH_SPEED_NUM_100G:
6942         case RTE_ETH_SPEED_NUM_200G:
6943                 cur_capa = fec_capa[0].capa;
6944                 break;
6945         default:
6946                 cur_capa = 0;
6947                 break;
6948         }
6949
6950         return cur_capa;
6951 }
6952
6953 static bool
6954 is_fec_mode_one_bit_set(uint32_t mode)
6955 {
6956         int cnt = 0;
6957         uint8_t i;
6958
6959         for (i = 0; i < sizeof(mode); i++)
6960                 if (mode >> i & 0x1)
6961                         cnt++;
6962
6963         return cnt == 1 ? true : false;
6964 }
6965
6966 static int
6967 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6968 {
6969 #define FEC_CAPA_NUM 2
6970         struct hns3_adapter *hns = dev->data->dev_private;
6971         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6972         struct hns3_pf *pf = &hns->pf;
6973
6974         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6975         uint32_t cur_capa;
6976         uint32_t num = FEC_CAPA_NUM;
6977         int ret;
6978
6979         ret = hns3_fec_get_capability(dev, fec_capa, num);
6980         if (ret < 0)
6981                 return ret;
6982
6983         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6984         if (!is_fec_mode_one_bit_set(mode)) {
6985                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6986                              "FEC mode should be only one bit set", mode);
6987                 return -EINVAL;
6988         }
6989
6990         /*
6991          * Check whether the configured mode is within the FEC capability.
6992          * If not, the configured mode will not be supported.
6993          */
6994         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6995         if (!(cur_capa & mode)) {
6996                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6997                 return -EINVAL;
6998         }
6999
7000         rte_spinlock_lock(&hw->lock);
7001         ret = hns3_set_fec_hw(hw, mode);
7002         if (ret) {
7003                 rte_spinlock_unlock(&hw->lock);
7004                 return ret;
7005         }
7006
7007         pf->fec_mode = mode;
7008         rte_spinlock_unlock(&hw->lock);
7009
7010         return 0;
7011 }
7012
7013 static int
7014 hns3_restore_fec(struct hns3_hw *hw)
7015 {
7016         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7017         struct hns3_pf *pf = &hns->pf;
7018         uint32_t mode = pf->fec_mode;
7019         int ret;
7020
7021         ret = hns3_set_fec_hw(hw, mode);
7022         if (ret)
7023                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7024                          mode, ret);
7025
7026         return ret;
7027 }
7028
7029 static int
7030 hns3_query_dev_fec_info(struct hns3_hw *hw)
7031 {
7032         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7033         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7034         int ret;
7035
7036         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7037         if (ret)
7038                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7039
7040         return ret;
7041 }
7042
7043 static bool
7044 hns3_optical_module_existed(struct hns3_hw *hw)
7045 {
7046         struct hns3_cmd_desc desc;
7047         bool existed;
7048         int ret;
7049
7050         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7051         ret = hns3_cmd_send(hw, &desc, 1);
7052         if (ret) {
7053                 hns3_err(hw,
7054                          "fail to get optical module exist state, ret = %d.\n",
7055                          ret);
7056                 return false;
7057         }
7058         existed = !!desc.data[0];
7059
7060         return existed;
7061 }
7062
7063 static int
7064 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7065                                 uint32_t len, uint8_t *data)
7066 {
7067 #define HNS3_SFP_INFO_CMD_NUM 6
7068 #define HNS3_SFP_INFO_MAX_LEN \
7069         (HNS3_SFP_INFO_BD0_LEN + \
7070         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7071         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7072         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7073         uint16_t read_len;
7074         uint16_t copy_len;
7075         int ret;
7076         int i;
7077
7078         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7079                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7080                                           true);
7081                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7082                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7083         }
7084
7085         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7086         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7087         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7088         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7089
7090         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7091         if (ret) {
7092                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7093                                 ret);
7094                 return ret;
7095         }
7096
7097         /* The data format in BD0 is different with the others. */
7098         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7099         memcpy(data, sfp_info_bd0->data, copy_len);
7100         read_len = copy_len;
7101
7102         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7103                 if (read_len >= len)
7104                         break;
7105
7106                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7107                 memcpy(data + read_len, desc[i].data, copy_len);
7108                 read_len += copy_len;
7109         }
7110
7111         return (int)read_len;
7112 }
7113
7114 static int
7115 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7116                        struct rte_dev_eeprom_info *info)
7117 {
7118         struct hns3_adapter *hns = dev->data->dev_private;
7119         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7120         uint32_t offset = info->offset;
7121         uint32_t len = info->length;
7122         uint8_t *data = info->data;
7123         uint32_t read_len = 0;
7124
7125         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7126                 return -ENOTSUP;
7127
7128         if (!hns3_optical_module_existed(hw)) {
7129                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7130                 return -EIO;
7131         }
7132
7133         while (read_len < len) {
7134                 int ret;
7135                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7136                                                   len - read_len,
7137                                                   data + read_len);
7138                 if (ret < 0)
7139                         return -EIO;
7140                 read_len += ret;
7141         }
7142
7143         return 0;
7144 }
7145
7146 static int
7147 hns3_get_module_info(struct rte_eth_dev *dev,
7148                      struct rte_eth_dev_module_info *modinfo)
7149 {
7150 #define HNS3_SFF8024_ID_SFP             0x03
7151 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7152 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7153 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7154 #define HNS3_SFF_8636_V1_3              0x03
7155         struct hns3_adapter *hns = dev->data->dev_private;
7156         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7157         struct rte_dev_eeprom_info info;
7158         struct hns3_sfp_type sfp_type;
7159         int ret;
7160
7161         memset(&sfp_type, 0, sizeof(sfp_type));
7162         memset(&info, 0, sizeof(info));
7163         info.data = (uint8_t *)&sfp_type;
7164         info.length = sizeof(sfp_type);
7165         ret = hns3_get_module_eeprom(dev, &info);
7166         if (ret)
7167                 return ret;
7168
7169         switch (sfp_type.type) {
7170         case HNS3_SFF8024_ID_SFP:
7171                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7172                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7173                 break;
7174         case HNS3_SFF8024_ID_QSFP_8438:
7175                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7176                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7177                 break;
7178         case HNS3_SFF8024_ID_QSFP_8436_8636:
7179                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7180                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7181                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7182                 } else {
7183                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7184                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7185                 }
7186                 break;
7187         case HNS3_SFF8024_ID_QSFP28_8636:
7188                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7189                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7190                 break;
7191         default:
7192                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7193                          sfp_type.type, sfp_type.ext_type);
7194                 return -EINVAL;
7195         }
7196
7197         return 0;
7198 }
7199
7200 void
7201 hns3_clock_gettime(struct timeval *tv)
7202 {
7203 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */
7204 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW
7205 #else
7206 #define CLOCK_TYPE CLOCK_MONOTONIC
7207 #endif
7208 #define NSEC_TO_USEC_DIV 1000
7209
7210         struct timespec spec;
7211         (void)clock_gettime(CLOCK_TYPE, &spec);
7212
7213         tv->tv_sec = spec.tv_sec;
7214         tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV;
7215 }
7216
7217 uint64_t
7218 hns3_clock_calctime_ms(struct timeval *tv)
7219 {
7220         return (uint64_t)tv->tv_sec * MSEC_PER_SEC +
7221                 tv->tv_usec / USEC_PER_MSEC;
7222 }
7223
7224 uint64_t
7225 hns3_clock_gettime_ms(void)
7226 {
7227         struct timeval tv;
7228
7229         hns3_clock_gettime(&tv);
7230         return hns3_clock_calctime_ms(&tv);
7231 }
7232
7233 static int
7234 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7235 {
7236         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7237
7238         RTE_SET_USED(key);
7239
7240         if (strcmp(value, "vec") == 0)
7241                 hint = HNS3_IO_FUNC_HINT_VEC;
7242         else if (strcmp(value, "sve") == 0)
7243                 hint = HNS3_IO_FUNC_HINT_SVE;
7244         else if (strcmp(value, "simple") == 0)
7245                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7246         else if (strcmp(value, "common") == 0)
7247                 hint = HNS3_IO_FUNC_HINT_COMMON;
7248
7249         /* If the hint is valid then update output parameters */
7250         if (hint != HNS3_IO_FUNC_HINT_NONE)
7251                 *(uint32_t *)extra_args = hint;
7252
7253         return 0;
7254 }
7255
7256 static const char *
7257 hns3_get_io_hint_func_name(uint32_t hint)
7258 {
7259         switch (hint) {
7260         case HNS3_IO_FUNC_HINT_VEC:
7261                 return "vec";
7262         case HNS3_IO_FUNC_HINT_SVE:
7263                 return "sve";
7264         case HNS3_IO_FUNC_HINT_SIMPLE:
7265                 return "simple";
7266         case HNS3_IO_FUNC_HINT_COMMON:
7267                 return "common";
7268         default:
7269                 return "none";
7270         }
7271 }
7272
7273 static int
7274 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7275 {
7276         uint64_t val;
7277
7278         RTE_SET_USED(key);
7279
7280         val = strtoull(value, NULL, 16);
7281         *(uint64_t *)extra_args = val;
7282
7283         return 0;
7284 }
7285
7286 static int
7287 hns3_parse_mbx_time_limit(const char *key, const char *value, void *extra_args)
7288 {
7289         uint32_t val;
7290
7291         RTE_SET_USED(key);
7292
7293         val = strtoul(value, NULL, 10);
7294
7295         /*
7296          * 500ms is empirical value in process of mailbox communication. If
7297          * the delay value is set to one lower thanthe empirical value, mailbox
7298          * communication may fail.
7299          */
7300         if (val > HNS3_MBX_DEF_TIME_LIMIT_MS && val <= UINT16_MAX)
7301                 *(uint16_t *)extra_args = val;
7302
7303         return 0;
7304 }
7305
7306 void
7307 hns3_parse_devargs(struct rte_eth_dev *dev)
7308 {
7309         uint16_t mbx_time_limit_ms = HNS3_MBX_DEF_TIME_LIMIT_MS;
7310         struct hns3_adapter *hns = dev->data->dev_private;
7311         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7312         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7313         struct hns3_hw *hw = &hns->hw;
7314         uint64_t dev_caps_mask = 0;
7315         struct rte_kvargs *kvlist;
7316
7317         if (dev->device->devargs == NULL)
7318                 return;
7319
7320         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7321         if (!kvlist)
7322                 return;
7323
7324         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7325                            &hns3_parse_io_hint_func, &rx_func_hint);
7326         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7327                            &hns3_parse_io_hint_func, &tx_func_hint);
7328         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7329                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7330         (void)rte_kvargs_process(kvlist, HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7331                            &hns3_parse_mbx_time_limit, &mbx_time_limit_ms);
7332
7333         rte_kvargs_free(kvlist);
7334
7335         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7336                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7337                           hns3_get_io_hint_func_name(rx_func_hint));
7338         hns->rx_func_hint = rx_func_hint;
7339         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7340                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7341                           hns3_get_io_hint_func_name(tx_func_hint));
7342         hns->tx_func_hint = tx_func_hint;
7343
7344         if (dev_caps_mask != 0)
7345                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7346                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7347         hns->dev_caps_mask = dev_caps_mask;
7348
7349         if (mbx_time_limit_ms != HNS3_MBX_DEF_TIME_LIMIT_MS)
7350                 hns3_warn(hw, "parsed %s = %u.", HNS3_DEVARG_MBX_TIME_LIMIT_MS,
7351                                 mbx_time_limit_ms);
7352         hns->mbx_time_limit_ms = mbx_time_limit_ms;
7353 }
7354
7355 static const struct eth_dev_ops hns3_eth_dev_ops = {
7356         .dev_configure      = hns3_dev_configure,
7357         .dev_start          = hns3_dev_start,
7358         .dev_stop           = hns3_dev_stop,
7359         .dev_close          = hns3_dev_close,
7360         .promiscuous_enable = hns3_dev_promiscuous_enable,
7361         .promiscuous_disable = hns3_dev_promiscuous_disable,
7362         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7363         .allmulticast_disable = hns3_dev_allmulticast_disable,
7364         .mtu_set            = hns3_dev_mtu_set,
7365         .stats_get          = hns3_stats_get,
7366         .stats_reset        = hns3_stats_reset,
7367         .xstats_get         = hns3_dev_xstats_get,
7368         .xstats_get_names   = hns3_dev_xstats_get_names,
7369         .xstats_reset       = hns3_dev_xstats_reset,
7370         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7371         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7372         .dev_infos_get          = hns3_dev_infos_get,
7373         .fw_version_get         = hns3_fw_version_get,
7374         .rx_queue_setup         = hns3_rx_queue_setup,
7375         .tx_queue_setup         = hns3_tx_queue_setup,
7376         .rx_queue_release       = hns3_dev_rx_queue_release,
7377         .tx_queue_release       = hns3_dev_tx_queue_release,
7378         .rx_queue_start         = hns3_dev_rx_queue_start,
7379         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7380         .tx_queue_start         = hns3_dev_tx_queue_start,
7381         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7382         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7383         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7384         .rxq_info_get           = hns3_rxq_info_get,
7385         .txq_info_get           = hns3_txq_info_get,
7386         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7387         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7388         .flow_ctrl_get          = hns3_flow_ctrl_get,
7389         .flow_ctrl_set          = hns3_flow_ctrl_set,
7390         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7391         .mac_addr_add           = hns3_add_mac_addr,
7392         .mac_addr_remove        = hns3_remove_mac_addr,
7393         .mac_addr_set           = hns3_set_default_mac_addr,
7394         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7395         .link_update            = hns3_dev_link_update,
7396         .dev_set_link_up        = hns3_dev_set_link_up,
7397         .dev_set_link_down      = hns3_dev_set_link_down,
7398         .rss_hash_update        = hns3_dev_rss_hash_update,
7399         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7400         .reta_update            = hns3_dev_rss_reta_update,
7401         .reta_query             = hns3_dev_rss_reta_query,
7402         .flow_ops_get           = hns3_dev_flow_ops_get,
7403         .vlan_filter_set        = hns3_vlan_filter_set,
7404         .vlan_tpid_set          = hns3_vlan_tpid_set,
7405         .vlan_offload_set       = hns3_vlan_offload_set,
7406         .vlan_pvid_set          = hns3_vlan_pvid_set,
7407         .get_reg                = hns3_get_regs,
7408         .get_module_info        = hns3_get_module_info,
7409         .get_module_eeprom      = hns3_get_module_eeprom,
7410         .get_dcb_info           = hns3_get_dcb_info,
7411         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7412         .fec_get_capability     = hns3_fec_get_capability,
7413         .fec_get                = hns3_fec_get,
7414         .fec_set                = hns3_fec_set,
7415         .tm_ops_get             = hns3_tm_ops_get,
7416         .tx_done_cleanup        = hns3_tx_done_cleanup,
7417         .timesync_enable            = hns3_timesync_enable,
7418         .timesync_disable           = hns3_timesync_disable,
7419         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7420         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7421         .timesync_adjust_time       = hns3_timesync_adjust_time,
7422         .timesync_read_time         = hns3_timesync_read_time,
7423         .timesync_write_time        = hns3_timesync_write_time,
7424 };
7425
7426 static const struct hns3_reset_ops hns3_reset_ops = {
7427         .reset_service       = hns3_reset_service,
7428         .stop_service        = hns3_stop_service,
7429         .prepare_reset       = hns3_prepare_reset,
7430         .wait_hardware_ready = hns3_wait_hardware_ready,
7431         .reinit_dev          = hns3_reinit_dev,
7432         .restore_conf        = hns3_restore_conf,
7433         .start_service       = hns3_start_service,
7434 };
7435
7436 static void
7437 hns3_init_hw_ops(struct hns3_hw *hw)
7438 {
7439         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
7440         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
7441         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
7442         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
7443 }
7444
7445 static int
7446 hns3_dev_init(struct rte_eth_dev *eth_dev)
7447 {
7448         struct hns3_adapter *hns = eth_dev->data->dev_private;
7449         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7450         struct rte_ether_addr *eth_addr;
7451         struct hns3_hw *hw = &hns->hw;
7452         int ret;
7453
7454         PMD_INIT_FUNC_TRACE();
7455
7456         hns3_flow_init(eth_dev);
7457
7458         hns3_set_rxtx_function(eth_dev);
7459         eth_dev->dev_ops = &hns3_eth_dev_ops;
7460         eth_dev->rx_queue_count = hns3_rx_queue_count;
7461         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7462                 ret = hns3_mp_init_secondary();
7463                 if (ret) {
7464                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7465                                      "process, ret = %d", ret);
7466                         goto err_mp_init_secondary;
7467                 }
7468                 hw->secondary_cnt++;
7469                 hns3_tx_push_init(eth_dev);
7470                 return 0;
7471         }
7472
7473         ret = hns3_mp_init_primary();
7474         if (ret) {
7475                 PMD_INIT_LOG(ERR,
7476                              "Failed to init for primary process, ret = %d",
7477                              ret);
7478                 goto err_mp_init_primary;
7479         }
7480
7481         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7482         hns->is_vf = false;
7483         hw->data = eth_dev->data;
7484         hns3_parse_devargs(eth_dev);
7485
7486         /*
7487          * Set default max packet size according to the mtu
7488          * default vale in DPDK frame.
7489          */
7490         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7491
7492         ret = hns3_reset_init(hw);
7493         if (ret)
7494                 goto err_init_reset;
7495         hw->reset.ops = &hns3_reset_ops;
7496
7497         hns3_init_hw_ops(hw);
7498         ret = hns3_init_pf(eth_dev);
7499         if (ret) {
7500                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7501                 goto err_init_pf;
7502         }
7503
7504         /* Allocate memory for storing MAC addresses */
7505         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7506                                                sizeof(struct rte_ether_addr) *
7507                                                HNS3_UC_MACADDR_NUM, 0);
7508         if (eth_dev->data->mac_addrs == NULL) {
7509                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7510                              "to store MAC addresses",
7511                              sizeof(struct rte_ether_addr) *
7512                              HNS3_UC_MACADDR_NUM);
7513                 ret = -ENOMEM;
7514                 goto err_rte_zmalloc;
7515         }
7516
7517         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7518         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7519                 rte_eth_random_addr(hw->mac.mac_addr);
7520                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7521                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7522                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7523                           "unicast address, using random MAC address %s",
7524                           mac_str);
7525         }
7526         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7527                             &eth_dev->data->mac_addrs[0]);
7528
7529         hw->adapter_state = HNS3_NIC_INITIALIZED;
7530
7531         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7532                             SCHEDULE_PENDING) {
7533                 hns3_err(hw, "Reschedule reset service after dev_init");
7534                 hns3_schedule_reset(hns);
7535         } else {
7536                 /* IMP will wait ready flag before reset */
7537                 hns3_notify_reset_ready(hw, false);
7538         }
7539
7540         hns3_info(hw, "hns3 dev initialization successful!");
7541         return 0;
7542
7543 err_rte_zmalloc:
7544         hns3_uninit_pf(eth_dev);
7545
7546 err_init_pf:
7547         rte_free(hw->reset.wait_data);
7548
7549 err_init_reset:
7550         hns3_mp_uninit_primary();
7551
7552 err_mp_init_primary:
7553 err_mp_init_secondary:
7554         eth_dev->dev_ops = NULL;
7555         eth_dev->rx_pkt_burst = NULL;
7556         eth_dev->rx_descriptor_status = NULL;
7557         eth_dev->tx_pkt_burst = NULL;
7558         eth_dev->tx_pkt_prepare = NULL;
7559         eth_dev->tx_descriptor_status = NULL;
7560         return ret;
7561 }
7562
7563 static int
7564 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7565 {
7566         struct hns3_adapter *hns = eth_dev->data->dev_private;
7567         struct hns3_hw *hw = &hns->hw;
7568
7569         PMD_INIT_FUNC_TRACE();
7570
7571         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
7572                 return 0;
7573
7574         if (hw->adapter_state < HNS3_NIC_CLOSING)
7575                 hns3_dev_close(eth_dev);
7576
7577         hw->adapter_state = HNS3_NIC_REMOVED;
7578         return 0;
7579 }
7580
7581 static int
7582 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7583                    struct rte_pci_device *pci_dev)
7584 {
7585         return rte_eth_dev_pci_generic_probe(pci_dev,
7586                                              sizeof(struct hns3_adapter),
7587                                              hns3_dev_init);
7588 }
7589
7590 static int
7591 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7592 {
7593         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7594 }
7595
7596 static const struct rte_pci_id pci_id_hns3_map[] = {
7597         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7598         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7599         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7600         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7601         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7602         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7603         { .vendor_id = 0, }, /* sentinel */
7604 };
7605
7606 static struct rte_pci_driver rte_hns3_pmd = {
7607         .id_table = pci_id_hns3_map,
7608         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7609         .probe = eth_hns3_pci_probe,
7610         .remove = eth_hns3_pci_remove,
7611 };
7612
7613 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7614 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7615 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7616 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7617                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7618                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7619                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
7620                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
7621 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
7622 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);