drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108
 109 void hns3_ether_format_addr(char *buf, uint16_t size,
 110                             const struct rte_ether_addr *ether_addr)
 111 {
 112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 113                 ether_addr->addr_bytes[0],
 114                 ether_addr->addr_bytes[4],
 115                 ether_addr->addr_bytes[5]);
 116 }
 117
 118 static void
 119 hns3_pf_disable_irq0(struct hns3_hw *hw)
 120 {
 121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 122 }
 123
 124 static void
 125 hns3_pf_enable_irq0(struct hns3_hw *hw)
 126 {
 127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 128 }
 129
 130 static enum hns3_evt_cause
 131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 132                           uint32_t *vec_val)
 133 {
 134         struct hns3_hw *hw = &hns->hw;
 135
 136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 139         if (!is_delay) {
 140                 hw->reset.stats.imp_cnt++;
 141                 hns3_warn(hw, "IMP reset detected, clear reset status");
 142         } else {
 143                 hns3_schedule_delayed_reset(hns);
 144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 145         }
 146
 147         return HNS3_VECTOR0_EVENT_RST;
 148 }
 149
 150 static enum hns3_evt_cause
 151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 152                              uint32_t *vec_val)
 153 {
 154         struct hns3_hw *hw = &hns->hw;
 155
 156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 159         if (!is_delay) {
 160                 hw->reset.stats.global_cnt++;
 161                 hns3_warn(hw, "Global reset detected, clear reset status");
 162         } else {
 163                 hns3_schedule_delayed_reset(hns);
 164                 hns3_warn(hw,
 165                           "Global reset detected, don't clear reset status");
 166         }
 167
 168         return HNS3_VECTOR0_EVENT_RST;
 169 }
 170
 171 static enum hns3_evt_cause
 172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 173 {
 174         struct hns3_hw *hw = &hns->hw;
 175         uint32_t vector0_int_stats;
 176         uint32_t cmdq_src_val;
 177         uint32_t hw_err_src_reg;
 178         uint32_t val;
 179         enum hns3_evt_cause ret;
 180         bool is_delay;
 181
 182         /* fetch the events from their corresponding regs */
 183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 186
 187         is_delay = clearval == NULL ? true : false;
 188         /*
 189          * Assumption: If by any chance reset and mailbox events are reported
 190          * together then we will only process reset event and defer the
 191          * processing of the mailbox events. Since, we would have not cleared
 192          * RX CMDQ event this time we would receive again another interrupt
 193          * from H/W just for the mailbox.
 194          */
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 197                 goto out;
 198         }
 199
 200         /* Global reset */
 201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 203                 goto out;
 204         }
 205
 206         /* Check for vector0 1588 event source */
 207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 209                 ret = HNS3_VECTOR0_EVENT_PTP;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 msix event source */
 214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 216                 val = vector0_int_stats | hw_err_src_reg;
 217                 ret = HNS3_VECTOR0_EVENT_ERR;
 218                 goto out;
 219         }
 220
 221         /* check for vector0 mailbox(=CMDQ RX) event source */
 222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 224                 val = cmdq_src_val;
 225                 ret = HNS3_VECTOR0_EVENT_MBX;
 226                 goto out;
 227         }
 228
 229         val = vector0_int_stats;
 230         ret = HNS3_VECTOR0_EVENT_OTHER;
 231 out:
 232
 233         if (clearval)
 234                 *clearval = val;
 235         return ret;
 236 }
 237
 238 static bool
 239 hns3_is_1588_event_type(uint32_t event_type)
 240 {
 241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 242 }
 243
 244 static void
 245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 246 {
 247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 248             hns3_is_1588_event_type(event_type))
 249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 252 }
 253
 254 static void
 255 hns3_clear_all_event_cause(struct hns3_hw *hw)
 256 {
 257         uint32_t vector0_int_stats;
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259
 260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 261                 hns3_warn(hw, "Probe during IMP reset interrupt");
 262
 263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 264                 hns3_warn(hw, "Probe during Global reset interrupt");
 265
 266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 272                                 BIT(HNS3_VECTOR0_1588_INT_B));
 273 }
 274
 275 static void
 276 hns3_handle_mac_tnl(struct hns3_hw *hw)
 277 {
 278         struct hns3_cmd_desc desc;
 279         uint32_t status;
 280         int ret;
 281
 282         /* query and clear mac tnl interruptions */
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 284         ret = hns3_cmd_send(hw, &desc, 1);
 285         if (ret) {
 286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 287                 return;
 288         }
 289
 290         status = rte_le_to_cpu_32(desc.data[0]);
 291         if (status) {
 292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 294                                           false);
 295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 296                 ret = hns3_cmd_send(hw, &desc, 1);
 297                 if (ret)
 298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 299                                  ret);
 300         }
 301 }
 302
 303 static void
 304 hns3_interrupt_handler(void *param)
 305 {
 306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 307         struct hns3_adapter *hns = dev->data->dev_private;
 308         struct hns3_hw *hw = &hns->hw;
 309         enum hns3_evt_cause event_cause;
 310         uint32_t clearval = 0;
 311         uint32_t vector0_int;
 312         uint32_t ras_int;
 313         uint32_t cmdq_int;
 314
 315         /* Disable interrupt */
 316         hns3_pf_disable_irq0(hw);
 317
 318         event_cause = hns3_check_event_cause(hns, &clearval);
 319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_msix_error(hns, &hw->reset.request);
 328                 hns3_handle_ras_error(hns, &hw->reset.request);
 329                 hns3_handle_mac_tnl(hw);
 330                 hns3_schedule_reset(hns);
 331         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 332                 hns3_warn(hw, "received reset interrupt");
 333                 hns3_schedule_reset(hns);
 334         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 335                 hns3_dev_handle_mbx_msg(hw);
 336         } else {
 337                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 338                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 339                           vector0_int, ras_int, cmdq_int);
 340         }
 341
 342         hns3_clear_event_cause(hw, event_cause, clearval);
 343         /* Enable interrupt if it is not cause by reset */
 344         hns3_pf_enable_irq0(hw);
 345 }
 346
 347 static int
 348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 349 {
 350 #define HNS3_VLAN_ID_OFFSET_STEP        160
 351 #define HNS3_VLAN_BYTE_SIZE             8
 352         struct hns3_vlan_filter_pf_cfg_cmd *req;
 353         struct hns3_hw *hw = &hns->hw;
 354         uint8_t vlan_offset_byte_val;
 355         struct hns3_cmd_desc desc;
 356         uint8_t vlan_offset_byte;
 357         uint8_t vlan_offset_base;
 358         int ret;
 359
 360         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 361
 362         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 363         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 364                            HNS3_VLAN_BYTE_SIZE;
 365         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 366
 367         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 368         req->vlan_offset = vlan_offset_base;
 369         req->vlan_cfg = on ? 0 : 1;
 370         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 371
 372         ret = hns3_cmd_send(hw, &desc, 1);
 373         if (ret)
 374                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 375                          vlan_id, ret);
 376
 377         return ret;
 378 }
 379
 380 static void
 381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 382 {
 383         struct hns3_user_vlan_table *vlan_entry;
 384         struct hns3_pf *pf = &hns->pf;
 385
 386         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 387                 if (vlan_entry->vlan_id == vlan_id) {
 388                         if (vlan_entry->hd_tbl_status)
 389                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 390                         LIST_REMOVE(vlan_entry, next);
 391                         rte_free(vlan_entry);
 392                         break;
 393                 }
 394         }
 395 }
 396
 397 static void
 398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 399                         bool writen_to_tbl)
 400 {
 401         struct hns3_user_vlan_table *vlan_entry;
 402         struct hns3_hw *hw = &hns->hw;
 403         struct hns3_pf *pf = &hns->pf;
 404
 405         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 406                 if (vlan_entry->vlan_id == vlan_id)
 407                         return;
 408         }
 409
 410         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 411         if (vlan_entry == NULL) {
 412                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 413                 return;
 414         }
 415
 416         vlan_entry->hd_tbl_status = writen_to_tbl;
 417         vlan_entry->vlan_id = vlan_id;
 418
 419         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 420 }
 421
 422 static int
 423 hns3_restore_vlan_table(struct hns3_adapter *hns)
 424 {
 425         struct hns3_user_vlan_table *vlan_entry;
 426         struct hns3_hw *hw = &hns->hw;
 427         struct hns3_pf *pf = &hns->pf;
 428         uint16_t vlan_id;
 429         int ret = 0;
 430
 431         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 432                 return hns3_vlan_pvid_configure(hns,
 433                                                 hw->port_base_vlan_cfg.pvid, 1);
 434
 435         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 436                 if (vlan_entry->hd_tbl_status) {
 437                         vlan_id = vlan_entry->vlan_id;
 438                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 439                         if (ret)
 440                                 break;
 441                 }
 442         }
 443
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 449 {
 450         struct hns3_hw *hw = &hns->hw;
 451         bool writen_to_tbl = false;
 452         int ret = 0;
 453
 454         /*
 455          * When vlan filter is enabled, hardware regards packets without vlan
 456          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 457          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 458          */
 459         if (on == 0 && vlan_id == 0)
 460                 return 0;
 461
 462         /*
 463          * When port base vlan enabled, we use port base vlan as the vlan
 464          * filter condition. In this case, we don't update vlan filter table
 465          * when user add new vlan or remove exist vlan, just update the
 466          * vlan list. The vlan id in vlan list will be writen in vlan filter
 467          * table until port base vlan disabled
 468          */
 469         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 470                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 471                 writen_to_tbl = true;
 472         }
 473
 474         if (ret == 0) {
 475                 if (on)
 476                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 477                 else
 478                         hns3_rm_dev_vlan_table(hns, vlan_id);
 479         }
 480         return ret;
 481 }
 482
 483 static int
 484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 485 {
 486         struct hns3_adapter *hns = dev->data->dev_private;
 487         struct hns3_hw *hw = &hns->hw;
 488         int ret;
 489
 490         rte_spinlock_lock(&hw->lock);
 491         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 492         rte_spinlock_unlock(&hw->lock);
 493         return ret;
 494 }
 495
 496 static int
 497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 498                          uint16_t tpid)
 499 {
 500         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 501         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 502         struct hns3_hw *hw = &hns->hw;
 503         struct hns3_cmd_desc desc;
 504         int ret;
 505
 506         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 507              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 508                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 509                 return -EINVAL;
 510         }
 511
 512         if (tpid != RTE_ETHER_TYPE_VLAN) {
 513                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 514                 return -EINVAL;
 515         }
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 518         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 519
 520         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 524                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 527                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 528         }
 529
 530         ret = hns3_cmd_send(hw, &desc, 1);
 531         if (ret) {
 532                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 533                          ret);
 534                 return ret;
 535         }
 536
 537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 538
 539         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 540         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 541         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 546                          ret);
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 552                    uint16_t tpid)
 553 {
 554         struct hns3_adapter *hns = dev->data->dev_private;
 555         struct hns3_hw *hw = &hns->hw;
 556         int ret;
 557
 558         rte_spinlock_lock(&hw->lock);
 559         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 560         rte_spinlock_unlock(&hw->lock);
 561         return ret;
 562 }
 563
 564 static int
 565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 566                              struct hns3_rx_vtag_cfg *vcfg)
 567 {
 568         struct hns3_vport_vtag_rx_cfg_cmd *req;
 569         struct hns3_hw *hw = &hns->hw;
 570         struct hns3_cmd_desc desc;
 571         uint16_t vport_id;
 572         uint8_t bitmap;
 573         int ret;
 574
 575         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 576
 577         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 579                      vcfg->strip_tag1_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 581                      vcfg->strip_tag2_en ? 1 : 0);
 582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 583                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 584         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 585                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 586
 587         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 589                      vcfg->strip_tag1_discard_en ? 1 : 0);
 590         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 591                      vcfg->strip_tag2_discard_en ? 1 : 0);
 592         /*
 593          * In current version VF is not supported when PF is driven by DPDK
 594          * driver, just need to configure parameters for PF vport.
 595          */
 596         vport_id = HNS3_PF_FUNC_ID;
 597         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 598         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 599         req->vf_bitmap[req->vf_offset] = bitmap;
 600
 601         ret = hns3_cmd_send(hw, &desc, 1);
 602         if (ret)
 603                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 604         return ret;
 605 }
 606
 607 static void
 608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 609                            struct hns3_rx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_pf *pf = &hns->pf;
 612         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 613 }
 614
 615 static void
 616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 617                            struct hns3_tx_vtag_cfg *vcfg)
 618 {
 619         struct hns3_pf *pf = &hns->pf;
 620         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 621 }
 622
 623 static int
 624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 625 {
 626         struct hns3_rx_vtag_cfg rxvlan_cfg;
 627         struct hns3_hw *hw = &hns->hw;
 628         int ret;
 629
 630         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 631                 rxvlan_cfg.strip_tag1_en = false;
 632                 rxvlan_cfg.strip_tag2_en = enable;
 633                 rxvlan_cfg.strip_tag2_discard_en = false;
 634         } else {
 635                 rxvlan_cfg.strip_tag1_en = enable;
 636                 rxvlan_cfg.strip_tag2_en = true;
 637                 rxvlan_cfg.strip_tag2_discard_en = true;
 638         }
 639
 640         rxvlan_cfg.strip_tag1_discard_en = false;
 641         rxvlan_cfg.vlan1_vlan_prionly = false;
 642         rxvlan_cfg.vlan2_vlan_prionly = false;
 643         rxvlan_cfg.rx_vlan_offload_en = enable;
 644
 645         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 646         if (ret) {
 647                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 648                 return ret;
 649         }
 650
 651         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 658                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 659 {
 660         struct hns3_vlan_filter_ctrl_cmd *req;
 661         struct hns3_cmd_desc desc;
 662         int ret;
 663
 664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 665
 666         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 667         req->vlan_type = vlan_type;
 668         req->vlan_fe = filter_en ? fe_type : 0;
 669         req->vf_id = vf_id;
 670
 671         ret = hns3_cmd_send(hw, &desc, 1);
 672         if (ret)
 673                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 674
 675         return ret;
 676 }
 677
 678 static int
 679 hns3_vlan_filter_init(struct hns3_adapter *hns)
 680 {
 681         struct hns3_hw *hw = &hns->hw;
 682         int ret;
 683
 684         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 685                                         HNS3_FILTER_FE_EGRESS, false,
 686                                         HNS3_PF_FUNC_ID);
 687         if (ret) {
 688                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 689                 return ret;
 690         }
 691
 692         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 693                                         HNS3_FILTER_FE_INGRESS, false,
 694                                         HNS3_PF_FUNC_ID);
 695         if (ret)
 696                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 697
 698         return ret;
 699 }
 700
 701 static int
 702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 703 {
 704         struct hns3_hw *hw = &hns->hw;
 705         int ret;
 706
 707         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 708                                         HNS3_FILTER_FE_INGRESS, enable,
 709                                         HNS3_PF_FUNC_ID);
 710         if (ret)
 711                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 712                          enable ? "enable" : "disable", ret);
 713
 714         return ret;
 715 }
 716
 717 static int
 718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 719 {
 720         struct hns3_adapter *hns = dev->data->dev_private;
 721         struct hns3_hw *hw = &hns->hw;
 722         struct rte_eth_rxmode *rxmode;
 723         unsigned int tmp_mask;
 724         bool enable;
 725         int ret = 0;
 726
 727         rte_spinlock_lock(&hw->lock);
 728         rxmode = &dev->data->dev_conf.rxmode;
 729         tmp_mask = (unsigned int)mask;
 730         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 731                 /* ignore vlan filter configuration during promiscuous mode */
 732                 if (!dev->data->promiscuous) {
 733                         /* Enable or disable VLAN filter */
 734                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 735                                  true : false;
 736
 737                         ret = hns3_enable_vlan_filter(hns, enable);
 738                         if (ret) {
 739                                 rte_spinlock_unlock(&hw->lock);
 740                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 741                                          enable ? "enable" : "disable", ret);
 742                                 return ret;
 743                         }
 744                 }
 745         }
 746
 747         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 748                 /* Enable or disable VLAN stripping */
 749                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 750                     true : false;
 751
 752                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 753                 if (ret) {
 754                         rte_spinlock_unlock(&hw->lock);
 755                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 756                                  enable ? "enable" : "disable", ret);
 757                         return ret;
 758                 }
 759         }
 760
 761         rte_spinlock_unlock(&hw->lock);
 762
 763         return ret;
 764 }
 765
 766 static int
 767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 768                              struct hns3_tx_vtag_cfg *vcfg)
 769 {
 770         struct hns3_vport_vtag_tx_cfg_cmd *req;
 771         struct hns3_cmd_desc desc;
 772         struct hns3_hw *hw = &hns->hw;
 773         uint16_t vport_id;
 774         uint8_t bitmap;
 775         int ret;
 776
 777         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 778
 779         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 780         req->def_vlan_tag1 = vcfg->default_tag1;
 781         req->def_vlan_tag2 = vcfg->default_tag2;
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 783                      vcfg->accept_tag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 785                      vcfg->accept_untag1 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 787                      vcfg->accept_tag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 789                      vcfg->accept_untag2 ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 791                      vcfg->insert_tag1_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 793                      vcfg->insert_tag2_en ? 1 : 0);
 794         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 795
 796         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 797         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 798                      vcfg->tag_shift_mode_en ? 1 : 0);
 799
 800         /*
 801          * In current version VF is not supported when PF is driven by DPDK
 802          * driver, just need to configure parameters for PF vport.
 803          */
 804         vport_id = HNS3_PF_FUNC_ID;
 805         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 806         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 807         req->vf_bitmap[req->vf_offset] = bitmap;
 808
 809         ret = hns3_cmd_send(hw, &desc, 1);
 810         if (ret)
 811                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 812
 813         return ret;
 814 }
 815
 816 static int
 817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 818                      uint16_t pvid)
 819 {
 820         struct hns3_hw *hw = &hns->hw;
 821         struct hns3_tx_vtag_cfg txvlan_cfg;
 822         int ret;
 823
 824         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 825                 txvlan_cfg.accept_tag1 = true;
 826                 txvlan_cfg.insert_tag1_en = false;
 827                 txvlan_cfg.default_tag1 = 0;
 828         } else {
 829                 txvlan_cfg.accept_tag1 =
 830                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 831                 txvlan_cfg.insert_tag1_en = true;
 832                 txvlan_cfg.default_tag1 = pvid;
 833         }
 834
 835         txvlan_cfg.accept_untag1 = true;
 836         txvlan_cfg.accept_tag2 = true;
 837         txvlan_cfg.accept_untag2 = true;
 838         txvlan_cfg.insert_tag2_en = false;
 839         txvlan_cfg.default_tag2 = 0;
 840         txvlan_cfg.tag_shift_mode_en = true;
 841
 842         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 843         if (ret) {
 844                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 845                          ret);
 846                 return ret;
 847         }
 848
 849         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 850         return ret;
 851 }
 852
 853
 854 static void
 855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 856 {
 857         struct hns3_user_vlan_table *vlan_entry;
 858         struct hns3_pf *pf = &hns->pf;
 859
 860         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 861                 if (vlan_entry->hd_tbl_status) {
 862                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 863                         vlan_entry->hd_tbl_status = false;
 864                 }
 865         }
 866
 867         if (is_del_list) {
 868                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 869                 while (vlan_entry) {
 870                         LIST_REMOVE(vlan_entry, next);
 871                         rte_free(vlan_entry);
 872                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 873                 }
 874         }
 875 }
 876
 877 static void
 878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 879 {
 880         struct hns3_user_vlan_table *vlan_entry;
 881         struct hns3_pf *pf = &hns->pf;
 882
 883         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 884                 if (!vlan_entry->hd_tbl_status) {
 885                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 886                         vlan_entry->hd_tbl_status = true;
 887                 }
 888         }
 889 }
 890
 891 static void
 892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 893 {
 894         struct hns3_hw *hw = &hns->hw;
 895         int ret;
 896
 897         hns3_rm_all_vlan_table(hns, true);
 898         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 899                 ret = hns3_set_port_vlan_filter(hns,
 900                                                 hw->port_base_vlan_cfg.pvid, 0);
 901                 if (ret) {
 902                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 903                                  ret);
 904                         return;
 905                 }
 906         }
 907 }
 908
 909 static int
 910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 911                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         uint16_t old_pvid;
 915         int ret;
 916
 917         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 918                 old_pvid = hw->port_base_vlan_cfg.pvid;
 919                 if (old_pvid != HNS3_INVALID_PVID) {
 920                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 921                         if (ret) {
 922                                 hns3_err(hw, "failed to remove old pvid %u, "
 923                                                 "ret = %d", old_pvid, ret);
 924                                 return ret;
 925                         }
 926                 }
 927
 928                 hns3_rm_all_vlan_table(hns, false);
 929                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 930                 if (ret) {
 931                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 932                                         new_pvid, ret);
 933                         return ret;
 934                 }
 935         } else {
 936                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 937                 if (ret) {
 938                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 939                                         new_pvid, ret);
 940                         return ret;
 941                 }
 942
 943                 hns3_add_all_vlan_table(hns);
 944         }
 945         return 0;
 946 }
 947
 948 static int
 949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 950 {
 951         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 952         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 953         bool rx_strip_en;
 954         int ret;
 955
 956         rx_strip_en = old_cfg->rx_vlan_offload_en;
 957         if (on) {
 958                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 959                 rx_vlan_cfg.strip_tag2_en = true;
 960                 rx_vlan_cfg.strip_tag2_discard_en = true;
 961         } else {
 962                 rx_vlan_cfg.strip_tag1_en = false;
 963                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 964                 rx_vlan_cfg.strip_tag2_discard_en = false;
 965         }
 966         rx_vlan_cfg.strip_tag1_discard_en = false;
 967         rx_vlan_cfg.vlan1_vlan_prionly = false;
 968         rx_vlan_cfg.vlan2_vlan_prionly = false;
 969         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 970
 971         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 972         if (ret)
 973                 return ret;
 974
 975         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         uint16_t port_base_vlan_state;
 984         int ret, err;
 985
 986         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 987                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 988                         hns3_warn(hw, "Invalid operation! As current pvid set "
 989                                   "is %u, disable pvid %u is invalid",
 990                                   hw->port_base_vlan_cfg.pvid, pvid);
 991                 return 0;
 992         }
 993
 994         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 995                                     HNS3_PORT_BASE_VLAN_DISABLE;
 996         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 997         if (ret) {
 998                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 999                          ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_en_pvid_strip(hns, on);
1004         if (ret) {
1005                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006                          "ret = %d", ret);
1007                 goto pvid_vlan_strip_fail;
1008         }
1009
1010         if (pvid == HNS3_INVALID_PVID)
1011                 goto out;
1012         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013         if (ret) {
1014                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015                          ret);
1016                 goto vlan_filter_set_fail;
1017         }
1018
1019 out:
1020         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022         return ret;
1023
1024 vlan_filter_set_fail:
1025         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1026                                         HNS3_PORT_BASE_VLAN_ENABLE);
1027         if (err)
1028                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1029
1030 pvid_vlan_strip_fail:
1031         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1032                                         hw->port_base_vlan_cfg.pvid);
1033         if (err)
1034                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1041 {
1042         struct hns3_adapter *hns = dev->data->dev_private;
1043         struct hns3_hw *hw = &hns->hw;
1044         bool pvid_en_state_change;
1045         uint16_t pvid_state;
1046         int ret;
1047
1048         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1049                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1050                          RTE_ETHER_MAX_VLAN_ID);
1051                 return -EINVAL;
1052         }
1053
1054         /*
1055          * If PVID configuration state change, should refresh the PVID
1056          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1057          */
1058         pvid_state = hw->port_base_vlan_cfg.state;
1059         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1060             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1061                 pvid_en_state_change = false;
1062         else
1063                 pvid_en_state_change = true;
1064
1065         rte_spinlock_lock(&hw->lock);
1066         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1067         rte_spinlock_unlock(&hw->lock);
1068         if (ret)
1069                 return ret;
1070         /*
1071          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1072          * need be processed by PMD driver.
1073          */
1074         if (pvid_en_state_change &&
1075             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1076                 hns3_update_all_queues_pvid_proc_en(hw);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_default_vlan_config(struct hns3_adapter *hns)
1083 {
1084         struct hns3_hw *hw = &hns->hw;
1085         int ret;
1086
1087         /*
1088          * When vlan filter is enabled, hardware regards packets without vlan
1089          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1090          * table, packets without vlan won't be received. So, add vlan 0 as
1091          * the default vlan.
1092          */
1093         ret = hns3_vlan_filter_configure(hns, 0, 1);
1094         if (ret)
1095                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1096         return ret;
1097 }
1098
1099 static int
1100 hns3_init_vlan_config(struct hns3_adapter *hns)
1101 {
1102         struct hns3_hw *hw = &hns->hw;
1103         int ret;
1104
1105         /*
1106          * This function can be called in the initialization and reset process,
1107          * when in reset process, it means that hardware had been reseted
1108          * successfully and we need to restore the hardware configuration to
1109          * ensure that the hardware configuration remains unchanged before and
1110          * after reset.
1111          */
1112         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1113                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1114                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115         }
1116
1117         ret = hns3_vlan_filter_init(hns);
1118         if (ret) {
1119                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120                 return ret;
1121         }
1122
1123         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1124                                        RTE_ETHER_TYPE_VLAN);
1125         if (ret) {
1126                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1127                 return ret;
1128         }
1129
1130         /*
1131          * When in the reinit dev stage of the reset process, the following
1132          * vlan-related configurations may differ from those at initialization,
1133          * we will restore configurations to hardware in hns3_restore_vlan_table
1134          * and hns3_restore_vlan_conf later.
1135          */
1136         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1137                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1138                 if (ret) {
1139                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140                         return ret;
1141                 }
1142
1143                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1144                 if (ret) {
1145                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1146                                  ret);
1147                         return ret;
1148                 }
1149         }
1150
1151         return hns3_default_vlan_config(hns);
1152 }
1153
1154 static int
1155 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1156 {
1157         struct hns3_pf *pf = &hns->pf;
1158         struct hns3_hw *hw = &hns->hw;
1159         uint64_t offloads;
1160         bool enable;
1161         int ret;
1162
1163         if (!hw->data->promiscuous) {
1164                 /* restore vlan filter states */
1165                 offloads = hw->data->dev_conf.rxmode.offloads;
1166                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1167                 ret = hns3_enable_vlan_filter(hns, enable);
1168                 if (ret) {
1169                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1170                                  "ret = %d", ret);
1171                         return ret;
1172                 }
1173         }
1174
1175         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1176         if (ret) {
1177                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178                 return ret;
1179         }
1180
1181         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1182         if (ret)
1183                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1184
1185         return ret;
1186 }
1187
1188 static int
1189 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1190 {
1191         struct hns3_adapter *hns = dev->data->dev_private;
1192         struct rte_eth_dev_data *data = dev->data;
1193         struct rte_eth_txmode *txmode;
1194         struct hns3_hw *hw = &hns->hw;
1195         int mask;
1196         int ret;
1197
1198         txmode = &data->dev_conf.txmode;
1199         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1200                 hns3_warn(hw,
1201                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1202                           "configuration is not supported! Ignore these two "
1203                           "parameters: hw_vlan_reject_tagged(%u), "
1204                           "hw_vlan_reject_untagged(%u)",
1205                           txmode->hw_vlan_reject_tagged,
1206                           txmode->hw_vlan_reject_untagged);
1207
1208         /* Apply vlan offload setting */
1209         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1210         ret = hns3_vlan_offload_set(dev, mask);
1211         if (ret) {
1212                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1213                          ret);
1214                 return ret;
1215         }
1216
1217         /*
1218          * If pvid config is not set in rte_eth_conf, driver needn't to set
1219          * VLAN pvid related configuration to hardware.
1220          */
1221         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222                 return 0;
1223
1224         /* Apply pvid setting */
1225         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1226                                  txmode->hw_vlan_insert_pvid);
1227         if (ret)
1228                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1229                          txmode->pvid, ret);
1230
1231         return ret;
1232 }
1233
1234 static int
1235 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1236                 unsigned int tso_mss_max)
1237 {
1238         struct hns3_cfg_tso_status_cmd *req;
1239         struct hns3_cmd_desc desc;
1240         uint16_t tso_mss;
1241
1242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1243
1244         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245
1246         tso_mss = 0;
1247         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1248                        tso_mss_min);
1249         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250
1251         tso_mss = 0;
1252         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1253                        tso_mss_max);
1254         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1255
1256         return hns3_cmd_send(hw, &desc, 1);
1257 }
1258
1259 static int
1260 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1261                    uint16_t *allocated_size, bool is_alloc)
1262 {
1263         struct hns3_umv_spc_alc_cmd *req;
1264         struct hns3_cmd_desc desc;
1265         int ret;
1266
1267         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1269         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1270         req->space_size = rte_cpu_to_le_32(space_size);
1271
1272         ret = hns3_cmd_send(hw, &desc, 1);
1273         if (ret) {
1274                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1275                              is_alloc ? "allocate" : "free", ret);
1276                 return ret;
1277         }
1278
1279         if (is_alloc && allocated_size)
1280                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 hns3_init_umv_space(struct hns3_hw *hw)
1287 {
1288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1289         struct hns3_pf *pf = &hns->pf;
1290         uint16_t allocated_size = 0;
1291         int ret;
1292
1293         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1294                                  true);
1295         if (ret)
1296                 return ret;
1297
1298         if (allocated_size < pf->wanted_umv_size)
1299                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1300                              pf->wanted_umv_size, allocated_size);
1301
1302         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1303                                                 pf->wanted_umv_size;
1304         pf->used_umv_size = 0;
1305         return 0;
1306 }
1307
1308 static int
1309 hns3_uninit_umv_space(struct hns3_hw *hw)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313         int ret;
1314
1315         if (pf->max_umv_size == 0)
1316                 return 0;
1317
1318         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319         if (ret)
1320                 return ret;
1321
1322         pf->max_umv_size = 0;
1323
1324         return 0;
1325 }
1326
1327 static bool
1328 hns3_is_umv_space_full(struct hns3_hw *hw)
1329 {
1330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331         struct hns3_pf *pf = &hns->pf;
1332         bool is_full;
1333
1334         is_full = (pf->used_umv_size >= pf->max_umv_size);
1335
1336         return is_full;
1337 }
1338
1339 static void
1340 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1341 {
1342         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1343         struct hns3_pf *pf = &hns->pf;
1344
1345         if (is_free) {
1346                 if (pf->used_umv_size > 0)
1347                         pf->used_umv_size--;
1348         } else
1349                 pf->used_umv_size++;
1350 }
1351
1352 static void
1353 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1354                       const uint8_t *addr, bool is_mc)
1355 {
1356         const unsigned char *mac_addr = addr;
1357         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1358                             ((uint32_t)mac_addr[2] << 16) |
1359                             ((uint32_t)mac_addr[1] << 8) |
1360                             (uint32_t)mac_addr[0];
1361         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1362
1363         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1364         if (is_mc) {
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1366                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1367                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368         }
1369
1370         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1371         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 }
1373
1374 static int
1375 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1376                              uint8_t resp_code,
1377                              enum hns3_mac_vlan_tbl_opcode op)
1378 {
1379         if (cmdq_resp) {
1380                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1381                          cmdq_resp);
1382                 return -EIO;
1383         }
1384
1385         if (op == HNS3_MAC_VLAN_ADD) {
1386                 if (resp_code == 0 || resp_code == 1) {
1387                         return 0;
1388                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1389                         hns3_err(hw, "add mac addr failed for uc_overflow");
1390                         return -ENOSPC;
1391                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1392                         hns3_err(hw, "add mac addr failed for mc_overflow");
1393                         return -ENOSPC;
1394                 }
1395
1396                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397                          resp_code);
1398                 return -EIO;
1399         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1400                 if (resp_code == 0) {
1401                         return 0;
1402                 } else if (resp_code == 1) {
1403                         hns3_dbg(hw, "remove mac addr failed for miss");
1404                         return -ENOENT;
1405                 }
1406
1407                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408                          resp_code);
1409                 return -EIO;
1410         } else if (op == HNS3_MAC_VLAN_LKUP) {
1411                 if (resp_code == 0) {
1412                         return 0;
1413                 } else if (resp_code == 1) {
1414                         hns3_dbg(hw, "lookup mac addr failed for miss");
1415                         return -ENOENT;
1416                 }
1417
1418                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1419                          resp_code);
1420                 return -EIO;
1421         }
1422
1423         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1424                  op);
1425
1426         return -EINVAL;
1427 }
1428
1429 static int
1430 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1431                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1432                          struct hns3_cmd_desc *desc, bool is_mc)
1433 {
1434         uint8_t resp_code;
1435         uint16_t retval;
1436         int ret;
1437
1438         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1439         if (is_mc) {
1440                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1441                 memcpy(desc[0].data, req,
1442                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1443                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1444                                           true);
1445                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1446                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1449         } else {
1450                 memcpy(desc[0].data, req,
1451                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1452                 ret = hns3_cmd_send(hw, desc, 1);
1453         }
1454         if (ret) {
1455                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456                          ret);
1457                 return ret;
1458         }
1459         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1460         retval = rte_le_to_cpu_16(desc[0].retval);
1461
1462         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1463                                             HNS3_MAC_VLAN_LKUP);
1464 }
1465
1466 static int
1467 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1468                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1469                       struct hns3_cmd_desc *mc_desc)
1470 {
1471         uint8_t resp_code;
1472         uint16_t retval;
1473         int cfg_status;
1474         int ret;
1475
1476         if (mc_desc == NULL) {
1477                 struct hns3_cmd_desc desc;
1478
1479                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc.data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, &desc, 1);
1483                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc.retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1490                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1492                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1493                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1494                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1495                 memcpy(mc_desc[0].data, req,
1496                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1497                 mc_desc[0].retval = 0;
1498                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1499                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1500                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1501
1502                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1503                                                           HNS3_MAC_VLAN_ADD);
1504         }
1505
1506         if (ret) {
1507                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510
1511         return cfg_status;
1512 }
1513
1514 static int
1515 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1516                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1517 {
1518         struct hns3_cmd_desc desc;
1519         uint8_t resp_code;
1520         uint16_t retval;
1521         int ret;
1522
1523         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1524
1525         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1526
1527         ret = hns3_cmd_send(hw, &desc, 1);
1528         if (ret) {
1529                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1530                 return ret;
1531         }
1532         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1533         retval = rte_le_to_cpu_16(desc.retval);
1534
1535         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1536                                             HNS3_MAC_VLAN_REMOVE);
1537 }
1538
1539 static int
1540 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1541 {
1542         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1543         struct hns3_mac_vlan_tbl_entry_cmd req;
1544         struct hns3_pf *pf = &hns->pf;
1545         struct hns3_cmd_desc desc[3];
1546         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1547         uint16_t egress_port = 0;
1548         uint8_t vf_id;
1549         int ret;
1550
1551         /* check if mac addr is valid */
1552         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1553                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                       mac_addr);
1555                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1556                          mac_str);
1557                 return -EINVAL;
1558         }
1559
1560         memset(&req, 0, sizeof(req));
1561
1562         /*
1563          * In current version VF is not supported when PF is driven by DPDK
1564          * driver, just need to configure parameters for PF vport.
1565          */
1566         vf_id = HNS3_PF_FUNC_ID;
1567         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1568                        HNS3_MAC_EPORT_VFID_S, vf_id);
1569
1570         req.egress_port = rte_cpu_to_le_16(egress_port);
1571
1572         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1573
1574         /*
1575          * Lookup the mac address in the mac_vlan table, and add
1576          * it if the entry is inexistent. Repeated unicast entry
1577          * is not allowed in the mac vlan table.
1578          */
1579         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1580         if (ret == -ENOENT) {
1581                 if (!hns3_is_umv_space_full(hw)) {
1582                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1583                         if (!ret)
1584                                 hns3_update_umv_space(hw, false);
1585                         return ret;
1586                 }
1587
1588                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1589
1590                 return -ENOSPC;
1591         }
1592
1593         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1594
1595         /* check if we just hit the duplicate */
1596         if (ret == 0) {
1597                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598                 return 0;
1599         }
1600
1601         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1602                  mac_str);
1603
1604         return ret;
1605 }
1606
1607 static int
1608 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 {
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         struct rte_ether_addr *addr;
1612         int ret;
1613         int i;
1614
1615         for (i = 0; i < hw->mc_addrs_num; i++) {
1616                 addr = &hw->mc_addrs[i];
1617                 /* Check if there are duplicate addresses */
1618                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1619                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                               addr);
1621                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1622                                  "(%s) is added by the set_mc_mac_addr_list "
1623                                  "API", mac_str);
1624                         return -EINVAL;
1625                 }
1626         }
1627
1628         ret = hns3_add_mc_addr(hw, mac_addr);
1629         if (ret) {
1630                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631                                       mac_addr);
1632                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1633                          mac_str, ret);
1634         }
1635         return ret;
1636 }
1637
1638 static int
1639 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1640 {
1641         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1642         int ret;
1643
1644         ret = hns3_remove_mc_addr(hw, mac_addr);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1649                          mac_str, ret);
1650         }
1651         return ret;
1652 }
1653
1654 static int
1655 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1656                   uint32_t idx, __rte_unused uint32_t pool)
1657 {
1658         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         int ret;
1661
1662         rte_spinlock_lock(&hw->lock);
1663
1664         /*
1665          * In hns3 network engine adding UC and MC mac address with different
1666          * commands with firmware. We need to determine whether the input
1667          * address is a UC or a MC address to call different commands.
1668          * By the way, it is recommended calling the API function named
1669          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1670          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1671          * may affect the specifications of UC mac addresses.
1672          */
1673         if (rte_is_multicast_ether_addr(mac_addr))
1674                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1675         else
1676                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1677
1678         if (ret) {
1679                 rte_spinlock_unlock(&hw->lock);
1680                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681                                       mac_addr);
1682                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1683                          ret);
1684                 return ret;
1685         }
1686
1687         if (idx == 0)
1688                 hw->mac.default_addr_setted = true;
1689         rte_spinlock_unlock(&hw->lock);
1690
1691         return ret;
1692 }
1693
1694 static int
1695 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1696 {
1697         struct hns3_mac_vlan_tbl_entry_cmd req;
1698         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1699         int ret;
1700
1701         /* check if mac addr is valid */
1702         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1703                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704                                       mac_addr);
1705                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1706                          mac_str);
1707                 return -EINVAL;
1708         }
1709
1710         memset(&req, 0, sizeof(req));
1711         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1712         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1713         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1714         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1715                 return 0;
1716         else if (ret == 0)
1717                 hns3_update_umv_space(hw, true);
1718
1719         return ret;
1720 }
1721
1722 static void
1723 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1724 {
1725         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         /* index will be checked by upper level rte interface */
1727         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1728         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1729         int ret;
1730
1731         rte_spinlock_lock(&hw->lock);
1732
1733         if (rte_is_multicast_ether_addr(mac_addr))
1734                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1735         else
1736                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1737         rte_spinlock_unlock(&hw->lock);
1738         if (ret) {
1739                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       mac_addr);
1741                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1742                          ret);
1743         }
1744 }
1745
1746 static int
1747 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1748                           struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751         struct rte_ether_addr *oaddr;
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         bool default_addr_setted;
1754         bool rm_succes = false;
1755         int ret, ret_val;
1756
1757         /*
1758          * It has been guaranteed that input parameter named mac_addr is valid
1759          * address in the rte layer of DPDK framework.
1760          */
1761         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1762         default_addr_setted = hw->mac.default_addr_setted;
1763         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1764                 return 0;
1765
1766         rte_spinlock_lock(&hw->lock);
1767         if (default_addr_setted) {
1768                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1769                 if (ret) {
1770                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1771                                               oaddr);
1772                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1773                                   mac_str, ret);
1774                         rm_succes = false;
1775                 } else
1776                         rm_succes = true;
1777         }
1778
1779         ret = hns3_add_uc_addr_common(hw, mac_addr);
1780         if (ret) {
1781                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                       mac_addr);
1783                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1784                 goto err_add_uc_addr;
1785         }
1786
1787         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1788         if (ret) {
1789                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1790                 goto err_pause_addr_cfg;
1791         }
1792
1793         rte_ether_addr_copy(mac_addr,
1794                             (struct rte_ether_addr *)hw->mac.mac_addr);
1795         hw->mac.default_addr_setted = true;
1796         rte_spinlock_unlock(&hw->lock);
1797
1798         return 0;
1799
1800 err_pause_addr_cfg:
1801         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1802         if (ret_val) {
1803                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1804                                       mac_addr);
1805                 hns3_warn(hw,
1806                           "Failed to roll back to del setted mac addr(%s): %d",
1807                           mac_str, ret_val);
1808         }
1809
1810 err_add_uc_addr:
1811         if (rm_succes) {
1812                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1813                 if (ret_val) {
1814                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                               oaddr);
1816                         hns3_warn(hw,
1817                                   "Failed to restore old uc mac addr(%s): %d",
1818                                   mac_str, ret_val);
1819                         hw->mac.default_addr_setted = false;
1820                 }
1821         }
1822         rte_spinlock_unlock(&hw->lock);
1823
1824         return ret;
1825 }
1826
1827 static int
1828 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1829 {
1830         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1831         struct hns3_hw *hw = &hns->hw;
1832         struct rte_ether_addr *addr;
1833         int err = 0;
1834         int ret;
1835         int i;
1836
1837         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1838                 addr = &hw->data->mac_addrs[i];
1839                 if (rte_is_zero_ether_addr(addr))
1840                         continue;
1841                 if (rte_is_multicast_ether_addr(addr))
1842                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1843                               hns3_add_mc_addr(hw, addr);
1844                 else
1845                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1846                               hns3_add_uc_addr_common(hw, addr);
1847
1848                 if (ret) {
1849                         err = ret;
1850                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1851                                               addr);
1852                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1853                                  "ret = %d.", del ? "remove" : "restore",
1854                                  mac_str, i, ret);
1855                 }
1856         }
1857         return err;
1858 }
1859
1860 static void
1861 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1862 {
1863 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864         uint8_t word_num;
1865         uint8_t bit_num;
1866
1867         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1868                 word_num = vfid / 32;
1869                 bit_num = vfid % 32;
1870                 if (clr)
1871                         desc[1].data[word_num] &=
1872                             rte_cpu_to_le_32(~(1UL << bit_num));
1873                 else
1874                         desc[1].data[word_num] |=
1875                             rte_cpu_to_le_32(1UL << bit_num);
1876         } else {
1877                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1878                 bit_num = vfid % 32;
1879                 if (clr)
1880                         desc[2].data[word_num] &=
1881                             rte_cpu_to_le_32(~(1UL << bit_num));
1882                 else
1883                         desc[2].data[word_num] |=
1884                             rte_cpu_to_le_32(1UL << bit_num);
1885         }
1886 }
1887
1888 static int
1889 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1890 {
1891         struct hns3_mac_vlan_tbl_entry_cmd req;
1892         struct hns3_cmd_desc desc[3];
1893         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894         uint8_t vf_id;
1895         int ret;
1896
1897         /* Check if mac addr is valid */
1898         if (!rte_is_multicast_ether_addr(mac_addr)) {
1899                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1900                                       mac_addr);
1901                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1902                          mac_str);
1903                 return -EINVAL;
1904         }
1905
1906         memset(&req, 0, sizeof(req));
1907         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1908         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1909         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1910         if (ret) {
1911                 /* This mac addr do not exist, add new entry for it */
1912                 memset(desc[0].data, 0, sizeof(desc[0].data));
1913                 memset(desc[1].data, 0, sizeof(desc[0].data));
1914                 memset(desc[2].data, 0, sizeof(desc[0].data));
1915         }
1916
1917         /*
1918          * In current version VF is not supported when PF is driven by DPDK
1919          * driver, just need to configure parameters for PF vport.
1920          */
1921         vf_id = HNS3_PF_FUNC_ID;
1922         hns3_update_desc_vfid(desc, vf_id, false);
1923         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1924         if (ret) {
1925                 if (ret == -ENOSPC)
1926                         hns3_err(hw, "mc mac vlan table is full");
1927                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                       mac_addr);
1929                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1930         }
1931
1932         return ret;
1933 }
1934
1935 static int
1936 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 {
1938         struct hns3_mac_vlan_tbl_entry_cmd req;
1939         struct hns3_cmd_desc desc[3];
1940         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1941         uint8_t vf_id;
1942         int ret;
1943
1944         /* Check if mac addr is valid */
1945         if (!rte_is_multicast_ether_addr(mac_addr)) {
1946                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947                                       mac_addr);
1948                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1949                          mac_str);
1950                 return -EINVAL;
1951         }
1952
1953         memset(&req, 0, sizeof(req));
1954         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1955         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1956         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1957         if (ret == 0) {
1958                 /*
1959                  * This mac addr exist, remove this handle's VFID for it.
1960                  * In current version VF is not supported when PF is driven by
1961                  * DPDK driver, just need to configure parameters for PF vport.
1962                  */
1963                 vf_id = HNS3_PF_FUNC_ID;
1964                 hns3_update_desc_vfid(desc, vf_id, true);
1965
1966                 /* All the vfid is zero, so need to delete this entry */
1967                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968         } else if (ret == -ENOENT) {
1969                 /* This mac addr doesn't exist. */
1970                 return 0;
1971         }
1972
1973         if (ret) {
1974                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975                                       mac_addr);
1976                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984                            struct rte_ether_addr *mc_addr_set,
1985                            uint32_t nb_mc_addr)
1986 {
1987         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988         struct rte_ether_addr *addr;
1989         uint32_t i;
1990         uint32_t j;
1991
1992         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994                          "invalid. valid range: 0~%d",
1995                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1996                 return -EINVAL;
1997         }
1998
1999         /* Check if input mac addresses are valid */
2000         for (i = 0; i < nb_mc_addr; i++) {
2001                 addr = &mc_addr_set[i];
2002                 if (!rte_is_multicast_ether_addr(addr)) {
2003                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2004                                               addr);
2005                         hns3_err(hw,
2006                                  "failed to set mc mac addr, addr(%s) invalid.",
2007                                  mac_str);
2008                         return -EINVAL;
2009                 }
2010
2011                 /* Check if there are duplicate addresses */
2012                 for (j = i + 1; j < nb_mc_addr; j++) {
2013                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014                                 hns3_ether_format_addr(mac_str,
2015                                                       RTE_ETHER_ADDR_FMT_SIZE,
2016                                                       addr);
2017                                 hns3_err(hw, "failed to set mc mac addr, "
2018                                          "addrs invalid. two same addrs(%s).",
2019                                          mac_str);
2020                                 return -EINVAL;
2021                         }
2022                 }
2023
2024                 /*
2025                  * Check if there are duplicate addresses between mac_addrs
2026                  * and mc_addr_set
2027                  */
2028                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029                         if (rte_is_same_ether_addr(addr,
2030                                                    &hw->data->mac_addrs[j])) {
2031                                 hns3_ether_format_addr(mac_str,
2032                                                       RTE_ETHER_ADDR_FMT_SIZE,
2033                                                       addr);
2034                                 hns3_err(hw, "failed to set mc mac addr, "
2035                                          "addrs invalid. addrs(%s) has already "
2036                                          "configured in mac_addr add API",
2037                                          mac_str);
2038                                 return -EINVAL;
2039                         }
2040                 }
2041         }
2042
2043         return 0;
2044 }
2045
2046 static void
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048                            struct rte_ether_addr *mc_addr_set,
2049                            int mc_addr_num,
2050                            struct rte_ether_addr *reserved_addr_list,
2051                            int *reserved_addr_num,
2052                            struct rte_ether_addr *add_addr_list,
2053                            int *add_addr_num,
2054                            struct rte_ether_addr *rm_addr_list,
2055                            int *rm_addr_num)
2056 {
2057         struct rte_ether_addr *addr;
2058         int current_addr_num;
2059         int reserved_num = 0;
2060         int add_num = 0;
2061         int rm_num = 0;
2062         int num;
2063         int i;
2064         int j;
2065         bool same_addr;
2066
2067         /* Calculate the mc mac address list that should be removed */
2068         current_addr_num = hw->mc_addrs_num;
2069         for (i = 0; i < current_addr_num; i++) {
2070                 addr = &hw->mc_addrs[i];
2071                 same_addr = false;
2072                 for (j = 0; j < mc_addr_num; j++) {
2073                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2074                                 same_addr = true;
2075                                 break;
2076                         }
2077                 }
2078
2079                 if (!same_addr) {
2080                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2081                         rm_num++;
2082                 } else {
2083                         rte_ether_addr_copy(addr,
2084                                             &reserved_addr_list[reserved_num]);
2085                         reserved_num++;
2086                 }
2087         }
2088
2089         /* Calculate the mc mac address list that should be added */
2090         for (i = 0; i < mc_addr_num; i++) {
2091                 addr = &mc_addr_set[i];
2092                 same_addr = false;
2093                 for (j = 0; j < current_addr_num; j++) {
2094                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2095                                 same_addr = true;
2096                                 break;
2097                         }
2098                 }
2099
2100                 if (!same_addr) {
2101                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2102                         add_num++;
2103                 }
2104         }
2105
2106         /* Reorder the mc mac address list maintained by driver */
2107         for (i = 0; i < reserved_num; i++)
2108                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2109
2110         for (i = 0; i < rm_num; i++) {
2111                 num = reserved_num + i;
2112                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2113         }
2114
2115         *reserved_addr_num = reserved_num;
2116         *add_addr_num = add_num;
2117         *rm_addr_num = rm_num;
2118 }
2119
2120 static int
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122                           struct rte_ether_addr *mc_addr_set,
2123                           uint32_t nb_mc_addr)
2124 {
2125         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129         struct rte_ether_addr *addr;
2130         int reserved_addr_num;
2131         int add_addr_num;
2132         int rm_addr_num;
2133         int mc_addr_num;
2134         int num;
2135         int ret;
2136         int i;
2137
2138         /* Check if input parameters are valid */
2139         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2140         if (ret)
2141                 return ret;
2142
2143         rte_spinlock_lock(&hw->lock);
2144
2145         /*
2146          * Calculate the mc mac address lists those should be removed and be
2147          * added, Reorder the mc mac address list maintained by driver.
2148          */
2149         mc_addr_num = (int)nb_mc_addr;
2150         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151                                    reserved_addr_list, &reserved_addr_num,
2152                                    add_addr_list, &add_addr_num,
2153                                    rm_addr_list, &rm_addr_num);
2154
2155         /* Remove mc mac addresses */
2156         for (i = 0; i < rm_addr_num; i++) {
2157                 num = rm_addr_num - i - 1;
2158                 addr = &rm_addr_list[num];
2159                 ret = hns3_remove_mc_addr(hw, addr);
2160                 if (ret) {
2161                         rte_spinlock_unlock(&hw->lock);
2162                         return ret;
2163                 }
2164                 hw->mc_addrs_num--;
2165         }
2166
2167         /* Add mc mac addresses */
2168         for (i = 0; i < add_addr_num; i++) {
2169                 addr = &add_addr_list[i];
2170                 ret = hns3_add_mc_addr(hw, addr);
2171                 if (ret) {
2172                         rte_spinlock_unlock(&hw->lock);
2173                         return ret;
2174                 }
2175
2176                 num = reserved_addr_num + i;
2177                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2178                 hw->mc_addrs_num++;
2179         }
2180         rte_spinlock_unlock(&hw->lock);
2181
2182         return 0;
2183 }
2184
2185 static int
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2187 {
2188         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189         struct hns3_hw *hw = &hns->hw;
2190         struct rte_ether_addr *addr;
2191         int err = 0;
2192         int ret;
2193         int i;
2194
2195         for (i = 0; i < hw->mc_addrs_num; i++) {
2196                 addr = &hw->mc_addrs[i];
2197                 if (!rte_is_multicast_ether_addr(addr))
2198                         continue;
2199                 if (del)
2200                         ret = hns3_remove_mc_addr(hw, addr);
2201                 else
2202                         ret = hns3_add_mc_addr(hw, addr);
2203                 if (ret) {
2204                         err = ret;
2205                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2206                                               addr);
2207                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208                                  del ? "Remove" : "Restore", mac_str, ret);
2209                 }
2210         }
2211         return err;
2212 }
2213
2214 static int
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2216 {
2217         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2223         uint8_t num_tc;
2224         int max_tc = 0;
2225         int i;
2226
2227         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2228         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2229
2230         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2231                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2232                          "rx_mq_mode = %d", rx_mq_mode);
2233                 return -EINVAL;
2234         }
2235
2236         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2237             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2238                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2239                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2240                          rx_mq_mode, tx_mq_mode);
2241                 return -EINVAL;
2242         }
2243
2244         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2245                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2246                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2247                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2252                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2253                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2254                                  "nb_tcs(%d) != %d or %d in rx direction.",
2255                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2256                         return -EINVAL;
2257                 }
2258
2259                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2260                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2261                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2262                         return -EINVAL;
2263                 }
2264
2265                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2266                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2267                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2268                                          "is not equal to one in tx direction.",
2269                                          i, dcb_rx_conf->dcb_tc[i]);
2270                                 return -EINVAL;
2271                         }
2272                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2273                                 max_tc = dcb_rx_conf->dcb_tc[i];
2274                 }
2275
2276                 num_tc = max_tc + 1;
2277                 if (num_tc > dcb_rx_conf->nb_tcs) {
2278                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2279                                  num_tc, dcb_rx_conf->nb_tcs);
2280                         return -EINVAL;
2281                 }
2282         }
2283
2284         return 0;
2285 }
2286
2287 static int
2288 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2289 {
2290         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291
2292         if (!hns3_dev_dcb_supported(hw)) {
2293                 hns3_err(hw, "this port does not support dcb configurations.");
2294                 return -EOPNOTSUPP;
2295         }
2296
2297         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2298                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2299                 return -EOPNOTSUPP;
2300         }
2301
2302         /* Check multiple queue mode */
2303         return hns3_check_mq_mode(dev);
2304 }
2305
2306 static int
2307 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2308                            enum hns3_ring_type queue_type, uint16_t queue_id)
2309 {
2310         struct hns3_cmd_desc desc;
2311         struct hns3_ctrl_vector_chain_cmd *req =
2312                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2313         enum hns3_opcode_type op;
2314         uint16_t tqp_type_and_id = 0;
2315         uint16_t type;
2316         uint16_t gl;
2317         int ret;
2318
2319         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2320         hns3_cmd_setup_basic_desc(&desc, op, false);
2321         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2322                                               HNS3_TQP_INT_ID_L_S);
2323         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2324                                               HNS3_TQP_INT_ID_H_S);
2325
2326         if (queue_type == HNS3_RING_TYPE_RX)
2327                 gl = HNS3_RING_GL_RX;
2328         else
2329                 gl = HNS3_RING_GL_TX;
2330
2331         type = queue_type;
2332
2333         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2334                        type);
2335         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2336         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2337                        gl);
2338         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2339         req->int_cause_num = 1;
2340         ret = hns3_cmd_send(hw, &desc, 1);
2341         if (ret) {
2342                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2343                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2344                 return ret;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int
2351 hns3_init_ring_with_vector(struct hns3_hw *hw)
2352 {
2353         uint16_t vec;
2354         int ret;
2355         int i;
2356
2357         /*
2358          * In hns3 network engine, vector 0 is always the misc interrupt of this
2359          * function, vector 1~N can be used respectively for the queues of the
2360          * function. Tx and Rx queues with the same number share the interrupt
2361          * vector. In the initialization clearing the all hardware mapping
2362          * relationship configurations between queues and interrupt vectors is
2363          * needed, so some error caused by the residual configurations, such as
2364          * the unexpected Tx interrupt, can be avoid.
2365          */
2366         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2367         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2368                 vec = vec - 1; /* the last interrupt is reserved */
2369         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2370         for (i = 0; i < hw->intr_tqps_num; i++) {
2371                 /*
2372                  * Set gap limiter/rate limiter/quanity limiter algorithm
2373                  * configuration for interrupt coalesce of queue's interrupt.
2374                  */
2375                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2376                                        HNS3_TQP_INTR_GL_DEFAULT);
2377                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2378                                        HNS3_TQP_INTR_GL_DEFAULT);
2379                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2380                 /*
2381                  * QL(quantity limiter) is not used currently, just set 0 to
2382                  * close it.
2383                  */
2384                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2385
2386                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2387                                                  HNS3_RING_TYPE_TX, i);
2388                 if (ret) {
2389                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2390                                           "vector: %u, ret=%d", i, vec, ret);
2391                         return ret;
2392                 }
2393
2394                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2395                                                  HNS3_RING_TYPE_RX, i);
2396                 if (ret) {
2397                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2398                                           "vector: %u, ret=%d", i, vec, ret);
2399                         return ret;
2400                 }
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int
2407 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2408 {
2409         struct hns3_adapter *hns = dev->data->dev_private;
2410         struct hns3_hw *hw = &hns->hw;
2411         uint32_t max_rx_pkt_len;
2412         uint16_t mtu;
2413         int ret;
2414
2415         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2416                 return 0;
2417
2418         /*
2419          * If jumbo frames are enabled, MTU needs to be refreshed
2420          * according to the maximum RX packet length.
2421          */
2422         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2423         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2424             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2425                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2426                          "and no more than %u when jumbo frame enabled.",
2427                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2428                          (uint16_t)HNS3_MAX_FRAME_LEN);
2429                 return -EINVAL;
2430         }
2431
2432         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2433         ret = hns3_dev_mtu_set(dev, mtu);
2434         if (ret)
2435                 return ret;
2436         dev->data->mtu = mtu;
2437
2438         return 0;
2439 }
2440
2441 static int
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2443 {
2444         struct hns3_adapter *hns = dev->data->dev_private;
2445         struct rte_eth_conf *conf = &dev->data->dev_conf;
2446         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447         struct hns3_hw *hw = &hns->hw;
2448         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450         struct rte_eth_rss_conf rss_conf;
2451         bool gro_en;
2452         int ret;
2453
2454         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2455
2456         /*
2457          * Some versions of hardware network engine does not support
2458          * individually enable/disable/reset the Tx or Rx queue. These devices
2459          * must enable/disable/reset Tx and Rx queues at the same time. When the
2460          * numbers of Tx queues allocated by upper applications are not equal to
2461          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463          * work as usual. But these fake queues are imperceptible, and can not
2464          * be used by upper applications.
2465          */
2466         if (!hns3_dev_indep_txrx_supported(hw)) {
2467                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2468                 if (ret) {
2469                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2470                                  ret);
2471                         return ret;
2472                 }
2473         }
2474
2475         hw->adapter_state = HNS3_NIC_CONFIGURING;
2476         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2477                 hns3_err(hw, "setting link speed/duplex not supported");
2478                 ret = -EINVAL;
2479                 goto cfg_err;
2480         }
2481
2482         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2483                 ret = hns3_check_dcb_cfg(dev);
2484                 if (ret)
2485                         goto cfg_err;
2486         }
2487
2488         /* When RSS is not configured, redirect the packet queue 0 */
2489         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2490                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2491                 rss_conf = conf->rx_adv_conf.rss_conf;
2492                 hw->rss_dis_flag = false;
2493                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2494                 if (ret)
2495                         goto cfg_err;
2496         }
2497
2498         ret = hns3_refresh_mtu(dev, conf);
2499         if (ret)
2500                 goto cfg_err;
2501
2502         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2503         if (ret)
2504                 goto cfg_err;
2505
2506         ret = hns3_dev_configure_vlan(dev);
2507         if (ret)
2508                 goto cfg_err;
2509
2510         /* config hardware GRO */
2511         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2512         ret = hns3_config_gro(hw, gro_en);
2513         if (ret)
2514                 goto cfg_err;
2515
2516         hns3_init_rx_ptype_tble(dev);
2517         hw->adapter_state = HNS3_NIC_CONFIGURED;
2518
2519         return 0;
2520
2521 cfg_err:
2522         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2523         hw->adapter_state = HNS3_NIC_INITIALIZED;
2524
2525         return ret;
2526 }
2527
2528 static int
2529 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2530 {
2531         struct hns3_config_max_frm_size_cmd *req;
2532         struct hns3_cmd_desc desc;
2533
2534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2535
2536         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2537         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2538         req->min_frm_size = RTE_ETHER_MIN_LEN;
2539
2540         return hns3_cmd_send(hw, &desc, 1);
2541 }
2542
2543 static int
2544 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2545 {
2546         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2547         uint16_t original_mps = hns->pf.mps;
2548         int err;
2549         int ret;
2550
2551         ret = hns3_set_mac_mtu(hw, mps);
2552         if (ret) {
2553                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2554                 return ret;
2555         }
2556
2557         hns->pf.mps = mps;
2558         ret = hns3_buffer_alloc(hw);
2559         if (ret) {
2560                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2561                 goto rollback;
2562         }
2563
2564         return 0;
2565
2566 rollback:
2567         err = hns3_set_mac_mtu(hw, original_mps);
2568         if (err) {
2569                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2570                 return ret;
2571         }
2572         hns->pf.mps = original_mps;
2573
2574         return ret;
2575 }
2576
2577 static int
2578 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2579 {
2580         struct hns3_adapter *hns = dev->data->dev_private;
2581         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2582         struct hns3_hw *hw = &hns->hw;
2583         bool is_jumbo_frame;
2584         int ret;
2585
2586         if (dev->data->dev_started) {
2587                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2588                          "before configuration", dev->data->port_id);
2589                 return -EBUSY;
2590         }
2591
2592         rte_spinlock_lock(&hw->lock);
2593         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2594         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2595
2596         /*
2597          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2598          * assign to "uint16_t" type variable.
2599          */
2600         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2601         if (ret) {
2602                 rte_spinlock_unlock(&hw->lock);
2603                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2604                          dev->data->port_id, mtu, ret);
2605                 return ret;
2606         }
2607
2608         if (is_jumbo_frame)
2609                 dev->data->dev_conf.rxmode.offloads |=
2610                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2611         else
2612                 dev->data->dev_conf.rxmode.offloads &=
2613                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2614         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2615         rte_spinlock_unlock(&hw->lock);
2616
2617         return 0;
2618 }
2619
2620 static uint32_t
2621 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2622 {
2623         uint32_t speed_capa = 0;
2624
2625         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2626                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2627         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2628                 speed_capa |= ETH_LINK_SPEED_10M;
2629         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2630                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2631         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2632                 speed_capa |= ETH_LINK_SPEED_100M;
2633         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2634                 speed_capa |= ETH_LINK_SPEED_1G;
2635
2636         return speed_capa;
2637 }
2638
2639 static uint32_t
2640 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2641 {
2642         uint32_t speed_capa = 0;
2643
2644         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2645                 speed_capa |= ETH_LINK_SPEED_1G;
2646         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2647                 speed_capa |= ETH_LINK_SPEED_10G;
2648         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2649                 speed_capa |= ETH_LINK_SPEED_25G;
2650         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2651                 speed_capa |= ETH_LINK_SPEED_40G;
2652         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2653                 speed_capa |= ETH_LINK_SPEED_50G;
2654         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2655                 speed_capa |= ETH_LINK_SPEED_100G;
2656         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2657                 speed_capa |= ETH_LINK_SPEED_200G;
2658
2659         return speed_capa;
2660 }
2661
2662 static uint32_t
2663 hns3_get_speed_capa(struct hns3_hw *hw)
2664 {
2665         struct hns3_mac *mac = &hw->mac;
2666         uint32_t speed_capa;
2667
2668         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2669                 speed_capa =
2670                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2671         else
2672                 speed_capa =
2673                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2674
2675         if (mac->support_autoneg == 0)
2676                 speed_capa |= ETH_LINK_SPEED_FIXED;
2677
2678         return speed_capa;
2679 }
2680
2681 int
2682 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2683 {
2684         struct hns3_adapter *hns = eth_dev->data->dev_private;
2685         struct hns3_hw *hw = &hns->hw;
2686         uint16_t queue_num = hw->tqps_num;
2687
2688         /*
2689          * In interrupt mode, 'max_rx_queues' is set based on the number of
2690          * MSI-X interrupt resources of the hardware.
2691          */
2692         if (hw->data->dev_conf.intr_conf.rxq == 1)
2693                 queue_num = hw->intr_tqps_num;
2694
2695         info->max_rx_queues = queue_num;
2696         info->max_tx_queues = hw->tqps_num;
2697         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2698         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2699         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2700         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2701         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2702         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2703                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2704                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2705                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2706                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2707                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2708                                  DEV_RX_OFFLOAD_KEEP_CRC |
2709                                  DEV_RX_OFFLOAD_SCATTER |
2710                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2711                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2712                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2713                                  DEV_RX_OFFLOAD_RSS_HASH |
2714                                  DEV_RX_OFFLOAD_TCP_LRO);
2715         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2716                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2717                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2718                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2719                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2720                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2721                                  DEV_TX_OFFLOAD_TCP_TSO |
2722                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2723                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2724                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2725                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2726                                  hns3_txvlan_cap_get(hw));
2727
2728         if (hns3_dev_outer_udp_cksum_supported(hw))
2729                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2730
2731         if (hns3_dev_indep_txrx_supported(hw))
2732                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2733                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2734
2735         if (hns3_dev_ptp_supported(hw))
2736                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2737
2738         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2739                 .nb_max = HNS3_MAX_RING_DESC,
2740                 .nb_min = HNS3_MIN_RING_DESC,
2741                 .nb_align = HNS3_ALIGN_RING_DESC,
2742         };
2743
2744         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2745                 .nb_max = HNS3_MAX_RING_DESC,
2746                 .nb_min = HNS3_MIN_RING_DESC,
2747                 .nb_align = HNS3_ALIGN_RING_DESC,
2748                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2749                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2750         };
2751
2752         info->speed_capa = hns3_get_speed_capa(hw);
2753         info->default_rxconf = (struct rte_eth_rxconf) {
2754                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2755                 /*
2756                  * If there are no available Rx buffer descriptors, incoming
2757                  * packets are always dropped by hardware based on hns3 network
2758                  * engine.
2759                  */
2760                 .rx_drop_en = 1,
2761                 .offloads = 0,
2762         };
2763         info->default_txconf = (struct rte_eth_txconf) {
2764                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2765                 .offloads = 0,
2766         };
2767
2768         info->vmdq_queue_num = 0;
2769
2770         info->reta_size = hw->rss_ind_tbl_size;
2771         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2772         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2773
2774         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2775         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2776         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2777         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2778         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2779         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2780
2781         return 0;
2782 }
2783
2784 static int
2785 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2786                     size_t fw_size)
2787 {
2788         struct hns3_adapter *hns = eth_dev->data->dev_private;
2789         struct hns3_hw *hw = &hns->hw;
2790         uint32_t version = hw->fw_version;
2791         int ret;
2792
2793         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2794                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2795                                       HNS3_FW_VERSION_BYTE3_S),
2796                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2797                                       HNS3_FW_VERSION_BYTE2_S),
2798                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2799                                       HNS3_FW_VERSION_BYTE1_S),
2800                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2801                                       HNS3_FW_VERSION_BYTE0_S));
2802         ret += 1; /* add the size of '\0' */
2803         if (fw_size < (uint32_t)ret)
2804                 return ret;
2805         else
2806                 return 0;
2807 }
2808
2809 static int
2810 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2811 {
2812         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2813         int ret;
2814
2815         (void)hns3_update_link_status(hw);
2816
2817         ret = hns3_update_link_info(eth_dev);
2818         if (ret)
2819                 hw->mac.link_status = ETH_LINK_DOWN;
2820
2821         return ret;
2822 }
2823
2824 static void
2825 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2826                       struct rte_eth_link *new_link)
2827 {
2828         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2829         struct hns3_mac *mac = &hw->mac;
2830
2831         switch (mac->link_speed) {
2832         case ETH_SPEED_NUM_10M:
2833         case ETH_SPEED_NUM_100M:
2834         case ETH_SPEED_NUM_1G:
2835         case ETH_SPEED_NUM_10G:
2836         case ETH_SPEED_NUM_25G:
2837         case ETH_SPEED_NUM_40G:
2838         case ETH_SPEED_NUM_50G:
2839         case ETH_SPEED_NUM_100G:
2840         case ETH_SPEED_NUM_200G:
2841                 new_link->link_speed = mac->link_speed;
2842                 break;
2843         default:
2844                 if (mac->link_status)
2845                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2846                 else
2847                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2848                 break;
2849         }
2850
2851         new_link->link_duplex = mac->link_duplex;
2852         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2853         new_link->link_autoneg =
2854             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2855 }
2856
2857 static int
2858 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2859 {
2860 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2861 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2862
2863         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2864         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2865         struct hns3_mac *mac = &hw->mac;
2866         struct rte_eth_link new_link;
2867         int ret;
2868
2869         do {
2870                 ret = hns3_update_port_link_info(eth_dev);
2871                 if (ret) {
2872                         hns3_err(hw, "failed to get port link info, ret = %d.",
2873                                  ret);
2874                         break;
2875                 }
2876
2877                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2878                         break;
2879
2880                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2881         } while (retry_cnt--);
2882
2883         memset(&new_link, 0, sizeof(new_link));
2884         hns3_setup_linkstatus(eth_dev, &new_link);
2885
2886         return rte_eth_linkstatus_set(eth_dev, &new_link);
2887 }
2888
2889 static int
2890 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2891 {
2892         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2893         struct hns3_pf *pf = &hns->pf;
2894
2895         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2896                 return -EINVAL;
2897
2898         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2899
2900         return 0;
2901 }
2902
2903 static int
2904 hns3_query_function_status(struct hns3_hw *hw)
2905 {
2906 #define HNS3_QUERY_MAX_CNT              10
2907 #define HNS3_QUERY_SLEEP_MSCOEND        1
2908         struct hns3_func_status_cmd *req;
2909         struct hns3_cmd_desc desc;
2910         int timeout = 0;
2911         int ret;
2912
2913         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2914         req = (struct hns3_func_status_cmd *)desc.data;
2915
2916         do {
2917                 ret = hns3_cmd_send(hw, &desc, 1);
2918                 if (ret) {
2919                         PMD_INIT_LOG(ERR, "query function status failed %d",
2920                                      ret);
2921                         return ret;
2922                 }
2923
2924                 /* Check pf reset is done */
2925                 if (req->pf_state)
2926                         break;
2927
2928                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2929         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2930
2931         return hns3_parse_func_status(hw, req);
2932 }
2933
2934 static int
2935 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2936 {
2937         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2938         struct hns3_pf *pf = &hns->pf;
2939
2940         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2941                 /*
2942                  * The total_tqps_num obtained from firmware is maximum tqp
2943                  * numbers of this port, which should be used for PF and VFs.
2944                  * There is no need for pf to have so many tqp numbers in
2945                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2946                  * coming from config file, is assigned to maximum queue number
2947                  * for the PF of this port by user. So users can modify the
2948                  * maximum queue number of PF according to their own application
2949                  * scenarios, which is more flexible to use. In addition, many
2950                  * memories can be saved due to allocating queue statistics
2951                  * room according to the actual number of queues required. The
2952                  * maximum queue number of PF for network engine with
2953                  * revision_id greater than 0x30 is assigned by config file.
2954                  */
2955                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2956                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2957                                  "must be greater than 0.",
2958                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2959                         return -EINVAL;
2960                 }
2961
2962                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2963                                        hw->total_tqps_num);
2964         } else {
2965                 /*
2966                  * Due to the limitation on the number of PF interrupts
2967                  * available, the maximum queue number assigned to PF on
2968                  * the network engine with revision_id 0x21 is 64.
2969                  */
2970                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2971                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2972         }
2973
2974         return 0;
2975 }
2976
2977 static int
2978 hns3_query_pf_resource(struct hns3_hw *hw)
2979 {
2980         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2981         struct hns3_pf *pf = &hns->pf;
2982         struct hns3_pf_res_cmd *req;
2983         struct hns3_cmd_desc desc;
2984         int ret;
2985
2986         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2987         ret = hns3_cmd_send(hw, &desc, 1);
2988         if (ret) {
2989                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2990                 return ret;
2991         }
2992
2993         req = (struct hns3_pf_res_cmd *)desc.data;
2994         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2995                              rte_le_to_cpu_16(req->ext_tqp_num);
2996         ret = hns3_get_pf_max_tqp_num(hw);
2997         if (ret)
2998                 return ret;
2999
3000         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3001         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3002
3003         if (req->tx_buf_size)
3004                 pf->tx_buf_size =
3005                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3006         else
3007                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3008
3009         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3010
3011         if (req->dv_buf_size)
3012                 pf->dv_buf_size =
3013                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3014         else
3015                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3016
3017         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3018
3019         hw->num_msi =
3020                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3021                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3022
3023         return 0;
3024 }
3025
3026 static void
3027 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3028 {
3029         struct hns3_cfg_param_cmd *req;
3030         uint64_t mac_addr_tmp_high;
3031         uint8_t ext_rss_size_max;
3032         uint64_t mac_addr_tmp;
3033         uint32_t i;
3034
3035         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3036
3037         /* get the configuration */
3038         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3039                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3040         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3041                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3042         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3043                                            HNS3_CFG_TQP_DESC_N_M,
3044                                            HNS3_CFG_TQP_DESC_N_S);
3045
3046         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3047                                        HNS3_CFG_PHY_ADDR_M,
3048                                        HNS3_CFG_PHY_ADDR_S);
3049         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3050                                          HNS3_CFG_MEDIA_TP_M,
3051                                          HNS3_CFG_MEDIA_TP_S);
3052         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3053                                          HNS3_CFG_RX_BUF_LEN_M,
3054                                          HNS3_CFG_RX_BUF_LEN_S);
3055         /* get mac address */
3056         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3057         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3058                                            HNS3_CFG_MAC_ADDR_H_M,
3059                                            HNS3_CFG_MAC_ADDR_H_S);
3060
3061         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3062
3063         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3064                                             HNS3_CFG_DEFAULT_SPEED_M,
3065                                             HNS3_CFG_DEFAULT_SPEED_S);
3066         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3067                                            HNS3_CFG_RSS_SIZE_M,
3068                                            HNS3_CFG_RSS_SIZE_S);
3069
3070         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3071                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3072
3073         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3074         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3075
3076         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3077                                             HNS3_CFG_SPEED_ABILITY_M,
3078                                             HNS3_CFG_SPEED_ABILITY_S);
3079         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3080                                         HNS3_CFG_UMV_TBL_SPACE_M,
3081                                         HNS3_CFG_UMV_TBL_SPACE_S);
3082         if (!cfg->umv_space)
3083                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3084
3085         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3086                                                HNS3_CFG_EXT_RSS_SIZE_M,
3087                                                HNS3_CFG_EXT_RSS_SIZE_S);
3088
3089         /*
3090          * Field ext_rss_size_max obtained from firmware will be more flexible
3091          * for future changes and expansions, which is an exponent of 2, instead
3092          * of reading out directly. If this field is not zero, hns3 PF PMD
3093          * driver uses it as rss_size_max under one TC. Device, whose revision
3094          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3095          * maximum number of queues supported under a TC through this field.
3096          */
3097         if (ext_rss_size_max)
3098                 cfg->rss_size_max = 1U << ext_rss_size_max;
3099 }
3100
3101 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3102  * @hw: pointer to struct hns3_hw
3103  * @hcfg: the config structure to be getted
3104  */
3105 static int
3106 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3107 {
3108         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3109         struct hns3_cfg_param_cmd *req;
3110         uint32_t offset;
3111         uint32_t i;
3112         int ret;
3113
3114         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3115                 offset = 0;
3116                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3117                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3118                                           true);
3119                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3120                                i * HNS3_CFG_RD_LEN_BYTES);
3121                 /* Len should be divided by 4 when send to hardware */
3122                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3123                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3124                 req->offset = rte_cpu_to_le_32(offset);
3125         }
3126
3127         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3128         if (ret) {
3129                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3130                 return ret;
3131         }
3132
3133         hns3_parse_cfg(hcfg, desc);
3134
3135         return 0;
3136 }
3137
3138 static int
3139 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3140 {
3141         switch (speed_cmd) {
3142         case HNS3_CFG_SPEED_10M:
3143                 *speed = ETH_SPEED_NUM_10M;
3144                 break;
3145         case HNS3_CFG_SPEED_100M:
3146                 *speed = ETH_SPEED_NUM_100M;
3147                 break;
3148         case HNS3_CFG_SPEED_1G:
3149                 *speed = ETH_SPEED_NUM_1G;
3150                 break;
3151         case HNS3_CFG_SPEED_10G:
3152                 *speed = ETH_SPEED_NUM_10G;
3153                 break;
3154         case HNS3_CFG_SPEED_25G:
3155                 *speed = ETH_SPEED_NUM_25G;
3156                 break;
3157         case HNS3_CFG_SPEED_40G:
3158                 *speed = ETH_SPEED_NUM_40G;
3159                 break;
3160         case HNS3_CFG_SPEED_50G:
3161                 *speed = ETH_SPEED_NUM_50G;
3162                 break;
3163         case HNS3_CFG_SPEED_100G:
3164                 *speed = ETH_SPEED_NUM_100G;
3165                 break;
3166         case HNS3_CFG_SPEED_200G:
3167                 *speed = ETH_SPEED_NUM_200G;
3168                 break;
3169         default:
3170                 return -EINVAL;
3171         }
3172
3173         return 0;
3174 }
3175
3176 static void
3177 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3178 {
3179         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3180         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3181         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3182         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3183         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3184 }
3185
3186 static void
3187 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3188 {
3189         struct hns3_dev_specs_0_cmd *req0;
3190
3191         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3192
3193         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3194         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3195         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3196         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3197         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3198 }
3199
3200 static int
3201 hns3_check_dev_specifications(struct hns3_hw *hw)
3202 {
3203         if (hw->rss_ind_tbl_size == 0 ||
3204             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3205                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3206                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3207                               HNS3_RSS_IND_TBL_SIZE_MAX);
3208                 return -EINVAL;
3209         }
3210
3211         return 0;
3212 }
3213
3214 static int
3215 hns3_query_dev_specifications(struct hns3_hw *hw)
3216 {
3217         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3218         int ret;
3219         int i;
3220
3221         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3222                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3223                                           true);
3224                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3225         }
3226         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3227
3228         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3229         if (ret)
3230                 return ret;
3231
3232         hns3_parse_dev_specifications(hw, desc);
3233
3234         return hns3_check_dev_specifications(hw);
3235 }
3236
3237 static int
3238 hns3_get_capability(struct hns3_hw *hw)
3239 {
3240         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3241         struct rte_pci_device *pci_dev;
3242         struct hns3_pf *pf = &hns->pf;
3243         struct rte_eth_dev *eth_dev;
3244         uint16_t device_id;
3245         uint8_t revision;
3246         int ret;
3247
3248         eth_dev = &rte_eth_devices[hw->data->port_id];
3249         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3250         device_id = pci_dev->id.device_id;
3251
3252         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3253             device_id == HNS3_DEV_ID_50GE_RDMA ||
3254             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3255             device_id == HNS3_DEV_ID_200G_RDMA)
3256                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3257
3258         /* Get PCI revision id */
3259         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3260                                   HNS3_PCI_REVISION_ID);
3261         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3262                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3263                              ret);
3264                 return -EIO;
3265         }
3266         hw->revision = revision;
3267
3268         if (revision < PCI_REVISION_ID_HIP09_A) {
3269                 hns3_set_default_dev_specifications(hw);
3270                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3271                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3272                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3273                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3274                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3275                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3276                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3277                 hw->rss_info.ipv6_sctp_offload_supported = false;
3278                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3279                 return 0;
3280         }
3281
3282         ret = hns3_query_dev_specifications(hw);
3283         if (ret) {
3284                 PMD_INIT_LOG(ERR,
3285                              "failed to query dev specifications, ret = %d",
3286                              ret);
3287                 return ret;
3288         }
3289
3290         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3291         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3292         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3293         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3294         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3295         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3296         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3297         hw->rss_info.ipv6_sctp_offload_supported = true;
3298         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3299
3300         return 0;
3301 }
3302
3303 static int
3304 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3305 {
3306         int ret;
3307
3308         switch (media_type) {
3309         case HNS3_MEDIA_TYPE_COPPER:
3310                 if (!hns3_dev_copper_supported(hw)) {
3311                         PMD_INIT_LOG(ERR,
3312                                      "Media type is copper, not supported.");
3313                         ret = -EOPNOTSUPP;
3314                 } else {
3315                         ret = 0;
3316                 }
3317                 break;
3318         case HNS3_MEDIA_TYPE_FIBER:
3319                 ret = 0;
3320                 break;
3321         case HNS3_MEDIA_TYPE_BACKPLANE:
3322                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3323                 ret = -EOPNOTSUPP;
3324                 break;
3325         default:
3326                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3327                 ret = -EINVAL;
3328                 break;
3329         }
3330
3331         return ret;
3332 }
3333
3334 static int
3335 hns3_get_board_configuration(struct hns3_hw *hw)
3336 {
3337         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3338         struct hns3_pf *pf = &hns->pf;
3339         struct hns3_cfg cfg;
3340         int ret;
3341
3342         ret = hns3_get_board_cfg(hw, &cfg);
3343         if (ret) {
3344                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3345                 return ret;
3346         }
3347
3348         ret = hns3_check_media_type(hw, cfg.media_type);
3349         if (ret)
3350                 return ret;
3351
3352         hw->mac.media_type = cfg.media_type;
3353         hw->rss_size_max = cfg.rss_size_max;
3354         hw->rss_dis_flag = false;
3355         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3356         hw->mac.phy_addr = cfg.phy_addr;
3357         hw->mac.default_addr_setted = false;
3358         hw->num_tx_desc = cfg.tqp_desc_num;
3359         hw->num_rx_desc = cfg.tqp_desc_num;
3360         hw->dcb_info.num_pg = 1;
3361         hw->dcb_info.hw_pfc_map = 0;
3362
3363         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3364         if (ret) {
3365                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3366                              cfg.default_speed, ret);
3367                 return ret;
3368         }
3369
3370         pf->tc_max = cfg.tc_num;
3371         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3372                 PMD_INIT_LOG(WARNING,
3373                              "Get TC num(%u) from flash, set TC num to 1",
3374                              pf->tc_max);
3375                 pf->tc_max = 1;
3376         }
3377
3378         /* Dev does not support DCB */
3379         if (!hns3_dev_dcb_supported(hw)) {
3380                 pf->tc_max = 1;
3381                 pf->pfc_max = 0;
3382         } else
3383                 pf->pfc_max = pf->tc_max;
3384
3385         hw->dcb_info.num_tc = 1;
3386         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3387                                      hw->tqps_num / hw->dcb_info.num_tc);
3388         hns3_set_bit(hw->hw_tc_map, 0, 1);
3389         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3390
3391         pf->wanted_umv_size = cfg.umv_space;
3392
3393         return ret;
3394 }
3395
3396 static int
3397 hns3_get_configuration(struct hns3_hw *hw)
3398 {
3399         int ret;
3400
3401         ret = hns3_query_function_status(hw);
3402         if (ret) {
3403                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3404                 return ret;
3405         }
3406
3407         /* Get device capability */
3408         ret = hns3_get_capability(hw);
3409         if (ret) {
3410                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3411                 return ret;
3412         }
3413
3414         /* Get pf resource */
3415         ret = hns3_query_pf_resource(hw);
3416         if (ret) {
3417                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3418                 return ret;
3419         }
3420
3421         ret = hns3_get_board_configuration(hw);
3422         if (ret) {
3423                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3424                 return ret;
3425         }
3426
3427         ret = hns3_query_dev_fec_info(hw);
3428         if (ret)
3429                 PMD_INIT_LOG(ERR,
3430                              "failed to query FEC information, ret = %d", ret);
3431
3432         return ret;
3433 }
3434
3435 static int
3436 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3437                       uint16_t tqp_vid, bool is_pf)
3438 {
3439         struct hns3_tqp_map_cmd *req;
3440         struct hns3_cmd_desc desc;
3441         int ret;
3442
3443         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3444
3445         req = (struct hns3_tqp_map_cmd *)desc.data;
3446         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3447         req->tqp_vf = func_id;
3448         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3449         if (!is_pf)
3450                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3451         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3452
3453         ret = hns3_cmd_send(hw, &desc, 1);
3454         if (ret)
3455                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3456
3457         return ret;
3458 }
3459
3460 static int
3461 hns3_map_tqp(struct hns3_hw *hw)
3462 {
3463         int ret;
3464         int i;
3465
3466         /*
3467          * In current version, VF is not supported when PF is driven by DPDK
3468          * driver, so we assign total tqps_num tqps allocated to this port
3469          * to PF.
3470          */
3471         for (i = 0; i < hw->total_tqps_num; i++) {
3472                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3473                 if (ret)
3474                         return ret;
3475         }
3476
3477         return 0;
3478 }
3479
3480 static int
3481 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3482 {
3483         struct hns3_config_mac_speed_dup_cmd *req;
3484         struct hns3_cmd_desc desc;
3485         int ret;
3486
3487         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3488
3489         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3490
3491         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3492
3493         switch (speed) {
3494         case ETH_SPEED_NUM_10M:
3495                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3496                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3497                 break;
3498         case ETH_SPEED_NUM_100M:
3499                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3500                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3501                 break;
3502         case ETH_SPEED_NUM_1G:
3503                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3504                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3505                 break;
3506         case ETH_SPEED_NUM_10G:
3507                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3508                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3509                 break;
3510         case ETH_SPEED_NUM_25G:
3511                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3512                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3513                 break;
3514         case ETH_SPEED_NUM_40G:
3515                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3516                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3517                 break;
3518         case ETH_SPEED_NUM_50G:
3519                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3520                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3521                 break;
3522         case ETH_SPEED_NUM_100G:
3523                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3524                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3525                 break;
3526         case ETH_SPEED_NUM_200G:
3527                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3528                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3529                 break;
3530         default:
3531                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3532                 return -EINVAL;
3533         }
3534
3535         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3536
3537         ret = hns3_cmd_send(hw, &desc, 1);
3538         if (ret)
3539                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3540
3541         return ret;
3542 }
3543
3544 static int
3545 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3546 {
3547         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3548         struct hns3_pf *pf = &hns->pf;
3549         struct hns3_priv_buf *priv;
3550         uint32_t i, total_size;
3551
3552         total_size = pf->pkt_buf_size;
3553
3554         /* alloc tx buffer for all enabled tc */
3555         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3556                 priv = &buf_alloc->priv_buf[i];
3557
3558                 if (hw->hw_tc_map & BIT(i)) {
3559                         if (total_size < pf->tx_buf_size)
3560                                 return -ENOMEM;
3561
3562                         priv->tx_buf_size = pf->tx_buf_size;
3563                 } else
3564                         priv->tx_buf_size = 0;
3565
3566                 total_size -= priv->tx_buf_size;
3567         }
3568
3569         return 0;
3570 }
3571
3572 static int
3573 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3574 {
3575 /* TX buffer size is unit by 128 byte */
3576 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3577 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3578         struct hns3_tx_buff_alloc_cmd *req;
3579         struct hns3_cmd_desc desc;
3580         uint32_t buf_size;
3581         uint32_t i;
3582         int ret;
3583
3584         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3585
3586         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3587         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3588                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3589
3590                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3591                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3592                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3593         }
3594
3595         ret = hns3_cmd_send(hw, &desc, 1);
3596         if (ret)
3597                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3598
3599         return ret;
3600 }
3601
3602 static int
3603 hns3_get_tc_num(struct hns3_hw *hw)
3604 {
3605         int cnt = 0;
3606         uint8_t i;
3607
3608         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3609                 if (hw->hw_tc_map & BIT(i))
3610                         cnt++;
3611         return cnt;
3612 }
3613
3614 static uint32_t
3615 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3616 {
3617         struct hns3_priv_buf *priv;
3618         uint32_t rx_priv = 0;
3619         int i;
3620
3621         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3622                 priv = &buf_alloc->priv_buf[i];
3623                 if (priv->enable)
3624                         rx_priv += priv->buf_size;
3625         }
3626         return rx_priv;
3627 }
3628
3629 static uint32_t
3630 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3631 {
3632         uint32_t total_tx_size = 0;
3633         uint32_t i;
3634
3635         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3636                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3637
3638         return total_tx_size;
3639 }
3640
3641 /* Get the number of pfc enabled TCs, which have private buffer */
3642 static int
3643 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3644 {
3645         struct hns3_priv_buf *priv;
3646         int cnt = 0;
3647         uint8_t i;
3648
3649         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3650                 priv = &buf_alloc->priv_buf[i];
3651                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3652                         cnt++;
3653         }
3654
3655         return cnt;
3656 }
3657
3658 /* Get the number of pfc disabled TCs, which have private buffer */
3659 static int
3660 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3661                          struct hns3_pkt_buf_alloc *buf_alloc)
3662 {
3663         struct hns3_priv_buf *priv;
3664         int cnt = 0;
3665         uint8_t i;
3666
3667         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3668                 priv = &buf_alloc->priv_buf[i];
3669                 if (hw->hw_tc_map & BIT(i) &&
3670                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3671                         cnt++;
3672         }
3673
3674         return cnt;
3675 }
3676
3677 static bool
3678 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3679                   uint32_t rx_all)
3680 {
3681         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3682         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3683         struct hns3_pf *pf = &hns->pf;
3684         uint32_t shared_buf, aligned_mps;
3685         uint32_t rx_priv;
3686         uint8_t tc_num;
3687         uint8_t i;
3688
3689         tc_num = hns3_get_tc_num(hw);
3690         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3691
3692         if (hns3_dev_dcb_supported(hw))
3693                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3694                                         pf->dv_buf_size;
3695         else
3696                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3697                                         + pf->dv_buf_size;
3698
3699         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3700         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3701                              HNS3_BUF_SIZE_UNIT);
3702
3703         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3704         if (rx_all < rx_priv + shared_std)
3705                 return false;
3706
3707         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3708         buf_alloc->s_buf.buf_size = shared_buf;
3709         if (hns3_dev_dcb_supported(hw)) {
3710                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3711                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3712                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3713                                   HNS3_BUF_SIZE_UNIT);
3714         } else {
3715                 buf_alloc->s_buf.self.high =
3716                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3717                 buf_alloc->s_buf.self.low = aligned_mps;
3718         }
3719
3720         if (hns3_dev_dcb_supported(hw)) {
3721                 hi_thrd = shared_buf - pf->dv_buf_size;
3722
3723                 if (tc_num <= NEED_RESERVE_TC_NUM)
3724                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3725                                   BUF_MAX_PERCENT;
3726
3727                 if (tc_num)
3728                         hi_thrd = hi_thrd / tc_num;
3729
3730                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3731                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3732                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3733         } else {
3734                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3735                 lo_thrd = aligned_mps;
3736         }
3737
3738         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3739                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3740                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3741         }
3742
3743         return true;
3744 }
3745
3746 static bool
3747 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3748                      struct hns3_pkt_buf_alloc *buf_alloc)
3749 {
3750         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3751         struct hns3_pf *pf = &hns->pf;
3752         struct hns3_priv_buf *priv;
3753         uint32_t aligned_mps;
3754         uint32_t rx_all;
3755         uint8_t i;
3756
3757         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3758         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3759
3760         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3761                 priv = &buf_alloc->priv_buf[i];
3762
3763                 priv->enable = 0;
3764                 priv->wl.low = 0;
3765                 priv->wl.high = 0;
3766                 priv->buf_size = 0;
3767
3768                 if (!(hw->hw_tc_map & BIT(i)))
3769                         continue;
3770
3771                 priv->enable = 1;
3772                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3773                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3774                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3775                                                 HNS3_BUF_SIZE_UNIT);
3776                 } else {
3777                         priv->wl.low = 0;
3778                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3779                                         aligned_mps;
3780                 }
3781
3782                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3783         }
3784
3785         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3786 }
3787
3788 static bool
3789 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3790                              struct hns3_pkt_buf_alloc *buf_alloc)
3791 {
3792         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3793         struct hns3_pf *pf = &hns->pf;
3794         struct hns3_priv_buf *priv;
3795         int no_pfc_priv_num;
3796         uint32_t rx_all;
3797         uint8_t mask;
3798         int i;
3799
3800         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3801         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3802
3803         /* let the last to be cleared first */
3804         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3805                 priv = &buf_alloc->priv_buf[i];
3806                 mask = BIT((uint8_t)i);
3807
3808                 if (hw->hw_tc_map & mask &&
3809                     !(hw->dcb_info.hw_pfc_map & mask)) {
3810                         /* Clear the no pfc TC private buffer */
3811                         priv->wl.low = 0;
3812                         priv->wl.high = 0;
3813                         priv->buf_size = 0;
3814                         priv->enable = 0;
3815                         no_pfc_priv_num--;
3816                 }
3817
3818                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3819                     no_pfc_priv_num == 0)
3820                         break;
3821         }
3822
3823         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3824 }
3825
3826 static bool
3827 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3828                            struct hns3_pkt_buf_alloc *buf_alloc)
3829 {
3830         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3831         struct hns3_pf *pf = &hns->pf;
3832         struct hns3_priv_buf *priv;
3833         uint32_t rx_all;
3834         int pfc_priv_num;
3835         uint8_t mask;
3836         int i;
3837
3838         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3839         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3840
3841         /* let the last to be cleared first */
3842         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3843                 priv = &buf_alloc->priv_buf[i];
3844                 mask = BIT((uint8_t)i);
3845                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3846                         /* Reduce the number of pfc TC with private buffer */
3847                         priv->wl.low = 0;
3848                         priv->enable = 0;
3849                         priv->wl.high = 0;
3850                         priv->buf_size = 0;
3851                         pfc_priv_num--;
3852                 }
3853                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3854                     pfc_priv_num == 0)
3855                         break;
3856         }
3857
3858         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3859 }
3860
3861 static bool
3862 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3863                           struct hns3_pkt_buf_alloc *buf_alloc)
3864 {
3865 #define COMPENSATE_BUFFER       0x3C00
3866 #define COMPENSATE_HALF_MPS_NUM 5
3867 #define PRIV_WL_GAP             0x1800
3868         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3869         struct hns3_pf *pf = &hns->pf;
3870         uint32_t tc_num = hns3_get_tc_num(hw);
3871         uint32_t half_mps = pf->mps >> 1;
3872         struct hns3_priv_buf *priv;
3873         uint32_t min_rx_priv;
3874         uint32_t rx_priv;
3875         uint8_t i;
3876
3877         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3878         if (tc_num)
3879                 rx_priv = rx_priv / tc_num;
3880
3881         if (tc_num <= NEED_RESERVE_TC_NUM)
3882                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3883
3884         /*
3885          * Minimum value of private buffer in rx direction (min_rx_priv) is
3886          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3887          * buffer if rx_priv is greater than min_rx_priv.
3888          */
3889         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3890                         COMPENSATE_HALF_MPS_NUM * half_mps;
3891         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3892         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3893
3894         if (rx_priv < min_rx_priv)
3895                 return false;
3896
3897         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3898                 priv = &buf_alloc->priv_buf[i];
3899                 priv->enable = 0;
3900                 priv->wl.low = 0;
3901                 priv->wl.high = 0;
3902                 priv->buf_size = 0;
3903
3904                 if (!(hw->hw_tc_map & BIT(i)))
3905                         continue;
3906
3907                 priv->enable = 1;
3908                 priv->buf_size = rx_priv;
3909                 priv->wl.high = rx_priv - pf->dv_buf_size;
3910                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3911         }
3912
3913         buf_alloc->s_buf.buf_size = 0;
3914
3915         return true;
3916 }
3917
3918 /*
3919  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3920  * @hw: pointer to struct hns3_hw
3921  * @buf_alloc: pointer to buffer calculation data
3922  * @return: 0: calculate sucessful, negative: fail
3923  */
3924 static int
3925 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3926 {
3927         /* When DCB is not supported, rx private buffer is not allocated. */
3928         if (!hns3_dev_dcb_supported(hw)) {
3929                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3930                 struct hns3_pf *pf = &hns->pf;
3931                 uint32_t rx_all = pf->pkt_buf_size;
3932
3933                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3934                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3935                         return -ENOMEM;
3936
3937                 return 0;
3938         }
3939
3940         /*
3941          * Try to allocate privated packet buffer for all TCs without share
3942          * buffer.
3943          */
3944         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3945                 return 0;
3946
3947         /*
3948          * Try to allocate privated packet buffer for all TCs with share
3949          * buffer.
3950          */
3951         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3952                 return 0;
3953
3954         /*
3955          * For different application scenes, the enabled port number, TC number
3956          * and no_drop TC number are different. In order to obtain the better
3957          * performance, software could allocate the buffer size and configure
3958          * the waterline by tring to decrease the private buffer size according
3959          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3960          * enabled tc.
3961          */
3962         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3963                 return 0;
3964
3965         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3966                 return 0;
3967
3968         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3969                 return 0;
3970
3971         return -ENOMEM;
3972 }
3973
3974 static int
3975 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3976 {
3977         struct hns3_rx_priv_buff_cmd *req;
3978         struct hns3_cmd_desc desc;
3979         uint32_t buf_size;
3980         int ret;
3981         int i;
3982
3983         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3984         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3985
3986         /* Alloc private buffer TCs */
3987         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3988                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3989
3990                 req->buf_num[i] =
3991                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3992                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3993         }
3994
3995         buf_size = buf_alloc->s_buf.buf_size;
3996         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3997                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3998
3999         ret = hns3_cmd_send(hw, &desc, 1);
4000         if (ret)
4001                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4002
4003         return ret;
4004 }
4005
4006 static int
4007 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4008 {
4009 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4010         struct hns3_rx_priv_wl_buf *req;
4011         struct hns3_priv_buf *priv;
4012         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4013         int i, j;
4014         int ret;
4015
4016         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4017                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4018                                           false);
4019                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4020
4021                 /* The first descriptor set the NEXT bit to 1 */
4022                 if (i == 0)
4023                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4024                 else
4025                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4026
4027                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4028                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4029
4030                         priv = &buf_alloc->priv_buf[idx];
4031                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4032                                                         HNS3_BUF_UNIT_S);
4033                         req->tc_wl[j].high |=
4034                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4035                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4036                                                         HNS3_BUF_UNIT_S);
4037                         req->tc_wl[j].low |=
4038                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4039                 }
4040         }
4041
4042         /* Send 2 descriptor at one time */
4043         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4044         if (ret)
4045                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4046                              ret);
4047         return ret;
4048 }
4049
4050 static int
4051 hns3_common_thrd_config(struct hns3_hw *hw,
4052                         struct hns3_pkt_buf_alloc *buf_alloc)
4053 {
4054 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4055         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4056         struct hns3_rx_com_thrd *req;
4057         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4058         struct hns3_tc_thrd *tc;
4059         int tc_idx;
4060         int i, j;
4061         int ret;
4062
4063         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4064                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4065                                           false);
4066                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4067
4068                 /* The first descriptor set the NEXT bit to 1 */
4069                 if (i == 0)
4070                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4071                 else
4072                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4073
4074                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4075                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4076                         tc = &s_buf->tc_thrd[tc_idx];
4077
4078                         req->com_thrd[j].high =
4079                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4080                         req->com_thrd[j].high |=
4081                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4082                         req->com_thrd[j].low =
4083                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4084                         req->com_thrd[j].low |=
4085                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4086                 }
4087         }
4088
4089         /* Send 2 descriptors at one time */
4090         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4091         if (ret)
4092                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4093
4094         return ret;
4095 }
4096
4097 static int
4098 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4099 {
4100         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4101         struct hns3_rx_com_wl *req;
4102         struct hns3_cmd_desc desc;
4103         int ret;
4104
4105         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4106
4107         req = (struct hns3_rx_com_wl *)desc.data;
4108         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4109         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4110
4111         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4112         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4113
4114         ret = hns3_cmd_send(hw, &desc, 1);
4115         if (ret)
4116                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4117
4118         return ret;
4119 }
4120
4121 int
4122 hns3_buffer_alloc(struct hns3_hw *hw)
4123 {
4124         struct hns3_pkt_buf_alloc pkt_buf;
4125         int ret;
4126
4127         memset(&pkt_buf, 0, sizeof(pkt_buf));
4128         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4129         if (ret) {
4130                 PMD_INIT_LOG(ERR,
4131                              "could not calc tx buffer size for all TCs %d",
4132                              ret);
4133                 return ret;
4134         }
4135
4136         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4137         if (ret) {
4138                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4139                 return ret;
4140         }
4141
4142         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4143         if (ret) {
4144                 PMD_INIT_LOG(ERR,
4145                              "could not calc rx priv buffer size for all TCs %d",
4146                              ret);
4147                 return ret;
4148         }
4149
4150         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4151         if (ret) {
4152                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4153                 return ret;
4154         }
4155
4156         if (hns3_dev_dcb_supported(hw)) {
4157                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4158                 if (ret) {
4159                         PMD_INIT_LOG(ERR,
4160                                      "could not configure rx private waterline %d",
4161                                      ret);
4162                         return ret;
4163                 }
4164
4165                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4166                 if (ret) {
4167                         PMD_INIT_LOG(ERR,
4168                                      "could not configure common threshold %d",
4169                                      ret);
4170                         return ret;
4171                 }
4172         }
4173
4174         ret = hns3_common_wl_config(hw, &pkt_buf);
4175         if (ret)
4176                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4177                              ret);
4178
4179         return ret;
4180 }
4181
4182 static int
4183 hns3_mac_init(struct hns3_hw *hw)
4184 {
4185         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4186         struct hns3_mac *mac = &hw->mac;
4187         struct hns3_pf *pf = &hns->pf;
4188         int ret;
4189
4190         pf->support_sfp_query = true;
4191         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4192         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4193         if (ret) {
4194                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4195                 return ret;
4196         }
4197
4198         mac->link_status = ETH_LINK_DOWN;
4199
4200         return hns3_config_mtu(hw, pf->mps);
4201 }
4202
4203 static int
4204 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4205 {
4206 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4207 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4208 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4209 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4210         int return_status;
4211
4212         if (cmdq_resp) {
4213                 PMD_INIT_LOG(ERR,
4214                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4215                              cmdq_resp);
4216                 return -EIO;
4217         }
4218
4219         switch (resp_code) {
4220         case HNS3_ETHERTYPE_SUCCESS_ADD:
4221         case HNS3_ETHERTYPE_ALREADY_ADD:
4222                 return_status = 0;
4223                 break;
4224         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4225                 PMD_INIT_LOG(ERR,
4226                              "add mac ethertype failed for manager table overflow.");
4227                 return_status = -EIO;
4228                 break;
4229         case HNS3_ETHERTYPE_KEY_CONFLICT:
4230                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4231                 return_status = -EIO;
4232                 break;
4233         default:
4234                 PMD_INIT_LOG(ERR,
4235                              "add mac ethertype failed for undefined, code=%u.",
4236                              resp_code);
4237                 return_status = -EIO;
4238                 break;
4239         }
4240
4241         return return_status;
4242 }
4243
4244 static int
4245 hns3_add_mgr_tbl(struct hns3_hw *hw,
4246                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4247 {
4248         struct hns3_cmd_desc desc;
4249         uint8_t resp_code;
4250         uint16_t retval;
4251         int ret;
4252
4253         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4254         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4255
4256         ret = hns3_cmd_send(hw, &desc, 1);
4257         if (ret) {
4258                 PMD_INIT_LOG(ERR,
4259                              "add mac ethertype failed for cmd_send, ret =%d.",
4260                              ret);
4261                 return ret;
4262         }
4263
4264         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4265         retval = rte_le_to_cpu_16(desc.retval);
4266
4267         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4268 }
4269
4270 static void
4271 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4272                      int *table_item_num)
4273 {
4274         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4275
4276         /*
4277          * In current version, we add one item in management table as below:
4278          * 0x0180C200000E -- LLDP MC address
4279          */
4280         tbl = mgr_table;
4281         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4282         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4283         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4284         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4285         tbl->i_port_bitmap = 0x1;
4286         *table_item_num = 1;
4287 }
4288
4289 static int
4290 hns3_init_mgr_tbl(struct hns3_hw *hw)
4291 {
4292 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4293         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4294         int table_item_num;
4295         int ret;
4296         int i;
4297
4298         memset(mgr_table, 0, sizeof(mgr_table));
4299         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4300         for (i = 0; i < table_item_num; i++) {
4301                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4302                 if (ret) {
4303                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4304                                      ret);
4305                         return ret;
4306                 }
4307         }
4308
4309         return 0;
4310 }
4311
4312 static void
4313 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4314                         bool en_mc, bool en_bc, int vport_id)
4315 {
4316         if (!param)
4317                 return;
4318
4319         memset(param, 0, sizeof(struct hns3_promisc_param));
4320         if (en_uc)
4321                 param->enable = HNS3_PROMISC_EN_UC;
4322         if (en_mc)
4323                 param->enable |= HNS3_PROMISC_EN_MC;
4324         if (en_bc)
4325                 param->enable |= HNS3_PROMISC_EN_BC;
4326         param->vf_id = vport_id;
4327 }
4328
4329 static int
4330 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4331 {
4332         struct hns3_promisc_cfg_cmd *req;
4333         struct hns3_cmd_desc desc;
4334         int ret;
4335
4336         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4337
4338         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4339         req->vf_id = param->vf_id;
4340         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4341             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4342
4343         ret = hns3_cmd_send(hw, &desc, 1);
4344         if (ret)
4345                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4346
4347         return ret;
4348 }
4349
4350 static int
4351 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4352 {
4353         struct hns3_promisc_param param;
4354         bool en_bc_pmc = true;
4355         uint8_t vf_id;
4356
4357         /*
4358          * In current version VF is not supported when PF is driven by DPDK
4359          * driver, just need to configure parameters for PF vport.
4360          */
4361         vf_id = HNS3_PF_FUNC_ID;
4362
4363         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4364         return hns3_cmd_set_promisc_mode(hw, &param);
4365 }
4366
4367 static int
4368 hns3_promisc_init(struct hns3_hw *hw)
4369 {
4370         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4371         struct hns3_pf *pf = &hns->pf;
4372         struct hns3_promisc_param param;
4373         uint16_t func_id;
4374         int ret;
4375
4376         ret = hns3_set_promisc_mode(hw, false, false);
4377         if (ret) {
4378                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4379                 return ret;
4380         }
4381
4382         /*
4383          * In current version VFs are not supported when PF is driven by DPDK
4384          * driver. After PF has been taken over by DPDK, the original VF will
4385          * be invalid. So, there is a possibility of entry residues. It should
4386          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4387          * during init.
4388          */
4389         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4390                 hns3_promisc_param_init(&param, false, false, false, func_id);
4391                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4392                 if (ret) {
4393                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4394                                         " ret = %d", func_id, ret);
4395                         return ret;
4396                 }
4397         }
4398
4399         return 0;
4400 }
4401
4402 static void
4403 hns3_promisc_uninit(struct hns3_hw *hw)
4404 {
4405         struct hns3_promisc_param param;
4406         uint16_t func_id;
4407         int ret;
4408
4409         func_id = HNS3_PF_FUNC_ID;
4410
4411         /*
4412          * In current version VFs are not supported when PF is driven by
4413          * DPDK driver, and VFs' promisc mode status has been cleared during
4414          * init and their status will not change. So just clear PF's promisc
4415          * mode status during uninit.
4416          */
4417         hns3_promisc_param_init(&param, false, false, false, func_id);
4418         ret = hns3_cmd_set_promisc_mode(hw, &param);
4419         if (ret)
4420                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4421                                 " uninit, ret = %d", ret);
4422 }
4423
4424 static int
4425 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4426 {
4427         bool allmulti = dev->data->all_multicast ? true : false;
4428         struct hns3_adapter *hns = dev->data->dev_private;
4429         struct hns3_hw *hw = &hns->hw;
4430         uint64_t offloads;
4431         int err;
4432         int ret;
4433
4434         rte_spinlock_lock(&hw->lock);
4435         ret = hns3_set_promisc_mode(hw, true, true);
4436         if (ret) {
4437                 rte_spinlock_unlock(&hw->lock);
4438                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4439                          ret);
4440                 return ret;
4441         }
4442
4443         /*
4444          * When promiscuous mode was enabled, disable the vlan filter to let
4445          * all packets coming in in the receiving direction.
4446          */
4447         offloads = dev->data->dev_conf.rxmode.offloads;
4448         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4449                 ret = hns3_enable_vlan_filter(hns, false);
4450                 if (ret) {
4451                         hns3_err(hw, "failed to enable promiscuous mode due to "
4452                                      "failure to disable vlan filter, ret = %d",
4453                                  ret);
4454                         err = hns3_set_promisc_mode(hw, false, allmulti);
4455                         if (err)
4456                                 hns3_err(hw, "failed to restore promiscuous "
4457                                          "status after disable vlan filter "
4458                                          "failed during enabling promiscuous "
4459                                          "mode, ret = %d", ret);
4460                 }
4461         }
4462
4463         rte_spinlock_unlock(&hw->lock);
4464
4465         return ret;
4466 }
4467
4468 static int
4469 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4470 {
4471         bool allmulti = dev->data->all_multicast ? true : false;
4472         struct hns3_adapter *hns = dev->data->dev_private;
4473         struct hns3_hw *hw = &hns->hw;
4474         uint64_t offloads;
4475         int err;
4476         int ret;
4477
4478         /* If now in all_multicast mode, must remain in all_multicast mode. */
4479         rte_spinlock_lock(&hw->lock);
4480         ret = hns3_set_promisc_mode(hw, false, allmulti);
4481         if (ret) {
4482                 rte_spinlock_unlock(&hw->lock);
4483                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4484                          ret);
4485                 return ret;
4486         }
4487         /* when promiscuous mode was disabled, restore the vlan filter status */
4488         offloads = dev->data->dev_conf.rxmode.offloads;
4489         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4490                 ret = hns3_enable_vlan_filter(hns, true);
4491                 if (ret) {
4492                         hns3_err(hw, "failed to disable promiscuous mode due to"
4493                                  " failure to restore vlan filter, ret = %d",
4494                                  ret);
4495                         err = hns3_set_promisc_mode(hw, true, true);
4496                         if (err)
4497                                 hns3_err(hw, "failed to restore promiscuous "
4498                                          "status after enabling vlan filter "
4499                                          "failed during disabling promiscuous "
4500                                          "mode, ret = %d", ret);
4501                 }
4502         }
4503         rte_spinlock_unlock(&hw->lock);
4504
4505         return ret;
4506 }
4507
4508 static int
4509 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4510 {
4511         struct hns3_adapter *hns = dev->data->dev_private;
4512         struct hns3_hw *hw = &hns->hw;
4513         int ret;
4514
4515         if (dev->data->promiscuous)
4516                 return 0;
4517
4518         rte_spinlock_lock(&hw->lock);
4519         ret = hns3_set_promisc_mode(hw, false, true);
4520         rte_spinlock_unlock(&hw->lock);
4521         if (ret)
4522                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4523                          ret);
4524
4525         return ret;
4526 }
4527
4528 static int
4529 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4530 {
4531         struct hns3_adapter *hns = dev->data->dev_private;
4532         struct hns3_hw *hw = &hns->hw;
4533         int ret;
4534
4535         /* If now in promiscuous mode, must remain in all_multicast mode. */
4536         if (dev->data->promiscuous)
4537                 return 0;
4538
4539         rte_spinlock_lock(&hw->lock);
4540         ret = hns3_set_promisc_mode(hw, false, false);
4541         rte_spinlock_unlock(&hw->lock);
4542         if (ret)
4543                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4544                          ret);
4545
4546         return ret;
4547 }
4548
4549 static int
4550 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4551 {
4552         struct hns3_hw *hw = &hns->hw;
4553         bool allmulti = hw->data->all_multicast ? true : false;
4554         int ret;
4555
4556         if (hw->data->promiscuous) {
4557                 ret = hns3_set_promisc_mode(hw, true, true);
4558                 if (ret)
4559                         hns3_err(hw, "failed to restore promiscuous mode, "
4560                                  "ret = %d", ret);
4561                 return ret;
4562         }
4563
4564         ret = hns3_set_promisc_mode(hw, false, allmulti);
4565         if (ret)
4566                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4567                          ret);
4568         return ret;
4569 }
4570
4571 static int
4572 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4573 {
4574         struct hns3_sfp_info_cmd *resp;
4575         struct hns3_cmd_desc desc;
4576         int ret;
4577
4578         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4579         resp = (struct hns3_sfp_info_cmd *)desc.data;
4580         resp->query_type = HNS3_ACTIVE_QUERY;
4581
4582         ret = hns3_cmd_send(hw, &desc, 1);
4583         if (ret == -EOPNOTSUPP) {
4584                 hns3_warn(hw, "firmware does not support get SFP info,"
4585                           " ret = %d.", ret);
4586                 return ret;
4587         } else if (ret) {
4588                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4589                 return ret;
4590         }
4591
4592         /*
4593          * In some case, the speed of MAC obtained from firmware may be 0, it
4594          * shouldn't be set to mac->speed.
4595          */
4596         if (!rte_le_to_cpu_32(resp->sfp_speed))
4597                 return 0;
4598
4599         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4600         /*
4601          * if resp->supported_speed is 0, it means it's an old version
4602          * firmware, do not update these params.
4603          */
4604         if (resp->supported_speed) {
4605                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4606                 mac_info->supported_speed =
4607                                         rte_le_to_cpu_32(resp->supported_speed);
4608         } else {
4609                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4610         }
4611
4612         return 0;
4613 }
4614
4615 static uint8_t
4616 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4617 {
4618         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4619                 duplex = ETH_LINK_FULL_DUPLEX;
4620
4621         return duplex;
4622 }
4623
4624 static int
4625 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4626 {
4627         struct hns3_mac *mac = &hw->mac;
4628         int ret;
4629
4630         duplex = hns3_check_speed_dup(duplex, speed);
4631         if (mac->link_speed == speed && mac->link_duplex == duplex)
4632                 return 0;
4633
4634         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4635         if (ret)
4636                 return ret;
4637
4638         ret = hns3_port_shaper_update(hw, speed);
4639         if (ret)
4640                 return ret;
4641
4642         mac->link_speed = speed;
4643         mac->link_duplex = duplex;
4644
4645         return 0;
4646 }
4647
4648 static int
4649 hns3_update_fiber_link_info(struct hns3_hw *hw)
4650 {
4651         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4652         struct hns3_mac *mac = &hw->mac;
4653         struct hns3_mac mac_info;
4654         int ret;
4655
4656         /* If firmware do not support get SFP/qSFP speed, return directly */
4657         if (!pf->support_sfp_query)
4658                 return 0;
4659
4660         memset(&mac_info, 0, sizeof(struct hns3_mac));
4661         ret = hns3_get_sfp_info(hw, &mac_info);
4662         if (ret == -EOPNOTSUPP) {
4663                 pf->support_sfp_query = false;
4664                 return ret;
4665         } else if (ret)
4666                 return ret;
4667
4668         /* Do nothing if no SFP */
4669         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4670                 return 0;
4671
4672         /*
4673          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4674          * to reconfigure the speed of MAC. Otherwise, it indicates
4675          * that the current firmware only supports to obtain the
4676          * speed of the SFP, and the speed of MAC needs to reconfigure.
4677          */
4678         mac->query_type = mac_info.query_type;
4679         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4680                 if (mac_info.link_speed != mac->link_speed) {
4681                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4682                         if (ret)
4683                                 return ret;
4684                 }
4685
4686                 mac->link_speed = mac_info.link_speed;
4687                 mac->supported_speed = mac_info.supported_speed;
4688
4689                 return 0;
4690         }
4691
4692         /* Config full duplex for SFP */
4693         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4694                                       ETH_LINK_FULL_DUPLEX);
4695 }
4696
4697 static void
4698 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4699 {
4700 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4701
4702         struct hns3_phy_params_bd0_cmd *req;
4703         uint32_t supported;
4704
4705         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4706         mac->link_speed = rte_le_to_cpu_32(req->speed);
4707         mac->link_duplex = hns3_get_bit(req->duplex,
4708                                            HNS3_PHY_DUPLEX_CFG_B);
4709         mac->link_autoneg = hns3_get_bit(req->autoneg,
4710                                            HNS3_PHY_AUTONEG_CFG_B);
4711         mac->advertising = rte_le_to_cpu_32(req->advertising);
4712         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4713         supported = rte_le_to_cpu_32(req->supported);
4714         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4715         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4716 }
4717
4718 static int
4719 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4720 {
4721         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4722         uint16_t i;
4723         int ret;
4724
4725         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4726                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4727                                           true);
4728                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4729         }
4730         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4731
4732         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4733         if (ret) {
4734                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4735                 return ret;
4736         }
4737
4738         hns3_parse_copper_phy_params(desc, mac);
4739
4740         return 0;
4741 }
4742
4743 static int
4744 hns3_update_copper_link_info(struct hns3_hw *hw)
4745 {
4746         struct hns3_mac *mac = &hw->mac;
4747         struct hns3_mac mac_info;
4748         int ret;
4749
4750         memset(&mac_info, 0, sizeof(struct hns3_mac));
4751         ret = hns3_get_copper_phy_params(hw, &mac_info);
4752         if (ret)
4753                 return ret;
4754
4755         if (mac_info.link_speed != mac->link_speed) {
4756                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4757                 if (ret)
4758                         return ret;
4759         }
4760
4761         mac->link_speed = mac_info.link_speed;
4762         mac->link_duplex = mac_info.link_duplex;
4763         mac->link_autoneg = mac_info.link_autoneg;
4764         mac->supported_speed = mac_info.supported_speed;
4765         mac->advertising = mac_info.advertising;
4766         mac->lp_advertising = mac_info.lp_advertising;
4767         mac->support_autoneg = mac_info.support_autoneg;
4768
4769         return 0;
4770 }
4771
4772 static int
4773 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4774 {
4775         struct hns3_adapter *hns = eth_dev->data->dev_private;
4776         struct hns3_hw *hw = &hns->hw;
4777         int ret = 0;
4778
4779         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4780                 ret = hns3_update_copper_link_info(hw);
4781         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4782                 ret = hns3_update_fiber_link_info(hw);
4783
4784         return ret;
4785 }
4786
4787 static int
4788 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4789 {
4790         struct hns3_config_mac_mode_cmd *req;
4791         struct hns3_cmd_desc desc;
4792         uint32_t loop_en = 0;
4793         uint8_t val = 0;
4794         int ret;
4795
4796         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4797
4798         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4799         if (enable)
4800                 val = 1;
4801         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4802         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4803         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4804         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4805         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4806         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4807         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4808         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4809         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4810         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4811
4812         /*
4813          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4814          * when receiving frames. Otherwise, CRC will be stripped.
4815          */
4816         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4817                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4818         else
4819                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4820         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4821         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4822         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4823         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4824
4825         ret = hns3_cmd_send(hw, &desc, 1);
4826         if (ret)
4827                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4828
4829         return ret;
4830 }
4831
4832 static int
4833 hns3_get_mac_link_status(struct hns3_hw *hw)
4834 {
4835         struct hns3_link_status_cmd *req;
4836         struct hns3_cmd_desc desc;
4837         int link_status;
4838         int ret;
4839
4840         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4841         ret = hns3_cmd_send(hw, &desc, 1);
4842         if (ret) {
4843                 hns3_err(hw, "get link status cmd failed %d", ret);
4844                 return ETH_LINK_DOWN;
4845         }
4846
4847         req = (struct hns3_link_status_cmd *)desc.data;
4848         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4849
4850         return !!link_status;
4851 }
4852
4853 static bool
4854 hns3_update_link_status(struct hns3_hw *hw)
4855 {
4856         int state;
4857
4858         state = hns3_get_mac_link_status(hw);
4859         if (state != hw->mac.link_status) {
4860                 hw->mac.link_status = state;
4861                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4862                 hns3_config_mac_tnl_int(hw,
4863                                         state == ETH_LINK_UP ? true : false);
4864                 return true;
4865         }
4866
4867         return false;
4868 }
4869
4870 void
4871 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4872 {
4873         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4874         struct rte_eth_link new_link;
4875         int ret;
4876
4877         if (query)
4878                 hns3_update_port_link_info(dev);
4879
4880         memset(&new_link, 0, sizeof(new_link));
4881         hns3_setup_linkstatus(dev, &new_link);
4882
4883         ret = rte_eth_linkstatus_set(dev, &new_link);
4884         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4885                 hns3_start_report_lse(dev);
4886 }
4887
4888 static void
4889 hns3_service_handler(void *param)
4890 {
4891         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4892         struct hns3_adapter *hns = eth_dev->data->dev_private;
4893         struct hns3_hw *hw = &hns->hw;
4894
4895         if (!hns3_is_reset_pending(hns))
4896                 hns3_update_linkstatus_and_event(hw, true);
4897         else
4898                 hns3_warn(hw, "Cancel the query when reset is pending");
4899
4900         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4901 }
4902
4903 static int
4904 hns3_init_hardware(struct hns3_adapter *hns)
4905 {
4906         struct hns3_hw *hw = &hns->hw;
4907         int ret;
4908
4909         ret = hns3_map_tqp(hw);
4910         if (ret) {
4911                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4912                 return ret;
4913         }
4914
4915         ret = hns3_init_umv_space(hw);
4916         if (ret) {
4917                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4918                 return ret;
4919         }
4920
4921         ret = hns3_mac_init(hw);
4922         if (ret) {
4923                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4924                 goto err_mac_init;
4925         }
4926
4927         ret = hns3_init_mgr_tbl(hw);
4928         if (ret) {
4929                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4930                 goto err_mac_init;
4931         }
4932
4933         ret = hns3_promisc_init(hw);
4934         if (ret) {
4935                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4936                              ret);
4937                 goto err_mac_init;
4938         }
4939
4940         ret = hns3_init_vlan_config(hns);
4941         if (ret) {
4942                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4943                 goto err_mac_init;
4944         }
4945
4946         ret = hns3_dcb_init(hw);
4947         if (ret) {
4948                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4949                 goto err_mac_init;
4950         }
4951
4952         ret = hns3_init_fd_config(hns);
4953         if (ret) {
4954                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4955                 goto err_mac_init;
4956         }
4957
4958         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4959         if (ret) {
4960                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4961                 goto err_mac_init;
4962         }
4963
4964         ret = hns3_config_gro(hw, false);
4965         if (ret) {
4966                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4967                 goto err_mac_init;
4968         }
4969
4970         /*
4971          * In the initialization clearing the all hardware mapping relationship
4972          * configurations between queues and interrupt vectors is needed, so
4973          * some error caused by the residual configurations, such as the
4974          * unexpected interrupt, can be avoid.
4975          */
4976         ret = hns3_init_ring_with_vector(hw);
4977         if (ret) {
4978                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4979                 goto err_mac_init;
4980         }
4981
4982         return 0;
4983
4984 err_mac_init:
4985         hns3_uninit_umv_space(hw);
4986         return ret;
4987 }
4988
4989 static int
4990 hns3_clear_hw(struct hns3_hw *hw)
4991 {
4992         struct hns3_cmd_desc desc;
4993         int ret;
4994
4995         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4996
4997         ret = hns3_cmd_send(hw, &desc, 1);
4998         if (ret && ret != -EOPNOTSUPP)
4999                 return ret;
5000
5001         return 0;
5002 }
5003
5004 static void
5005 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5006 {
5007         uint32_t val;
5008
5009         /*
5010          * The new firmware support report more hardware error types by
5011          * msix mode. These errors are defined as RAS errors in hardware
5012          * and belong to a different type from the MSI-x errors processed
5013          * by the network driver.
5014          *
5015          * Network driver should open the new error report on initialition
5016          */
5017         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5018         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5019         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5020 }
5021
5022 static uint32_t
5023 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5024 {
5025         struct hns3_mac *mac = &hw->mac;
5026
5027         switch (mac->link_speed) {
5028         case ETH_SPEED_NUM_1G:
5029                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5030         case ETH_SPEED_NUM_10G:
5031                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5032         case ETH_SPEED_NUM_25G:
5033                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5034         case ETH_SPEED_NUM_40G:
5035                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5036         case ETH_SPEED_NUM_50G:
5037                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5038         case ETH_SPEED_NUM_100G:
5039                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5040         case ETH_SPEED_NUM_200G:
5041                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5042         default:
5043                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5044                 return 0;
5045         }
5046 }
5047
5048 /*
5049  * Validity of supported_speed for firber and copper media type can be
5050  * guaranteed by the following policy:
5051  * Copper:
5052  *       Although the initialization of the phy in the firmware may not be
5053  *       completed, the firmware can guarantees that the supported_speed is
5054  *       an valid value.
5055  * Firber:
5056  *       If the version of firmware supports the acitive query way of the
5057  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5058  *       through it. If unsupported, use the SFP's speed as the value of the
5059  *       supported_speed.
5060  */
5061 static int
5062 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5063 {
5064         struct hns3_adapter *hns = eth_dev->data->dev_private;
5065         struct hns3_hw *hw = &hns->hw;
5066         struct hns3_mac *mac = &hw->mac;
5067         int ret;
5068
5069         ret = hns3_update_link_info(eth_dev);
5070         if (ret)
5071                 return ret;
5072
5073         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5074                 /*
5075                  * Some firmware does not support the report of supported_speed,
5076                  * and only report the effective speed of SFP. In this case, it
5077                  * is necessary to use the SFP's speed as the supported_speed.
5078                  */
5079                 if (mac->supported_speed == 0)
5080                         mac->supported_speed =
5081                                 hns3_set_firber_default_support_speed(hw);
5082         }
5083
5084         return 0;
5085 }
5086
5087 static int
5088 hns3_init_pf(struct rte_eth_dev *eth_dev)
5089 {
5090         struct rte_device *dev = eth_dev->device;
5091         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5092         struct hns3_adapter *hns = eth_dev->data->dev_private;
5093         struct hns3_hw *hw = &hns->hw;
5094         int ret;
5095
5096         PMD_INIT_FUNC_TRACE();
5097
5098         /* Get hardware io base address from pcie BAR2 IO space */
5099         hw->io_base = pci_dev->mem_resource[2].addr;
5100
5101         /* Firmware command queue initialize */
5102         ret = hns3_cmd_init_queue(hw);
5103         if (ret) {
5104                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5105                 goto err_cmd_init_queue;
5106         }
5107
5108         hns3_clear_all_event_cause(hw);
5109
5110         /* Firmware command initialize */
5111         ret = hns3_cmd_init(hw);
5112         if (ret) {
5113                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5114                 goto err_cmd_init;
5115         }
5116
5117         /*
5118          * To ensure that the hardware environment is clean during
5119          * initialization, the driver actively clear the hardware environment
5120          * during initialization, including PF and corresponding VFs' vlan, mac,
5121          * flow table configurations, etc.
5122          */
5123         ret = hns3_clear_hw(hw);
5124         if (ret) {
5125                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5126                 goto err_cmd_init;
5127         }
5128
5129         /* Hardware statistics of imissed registers cleared. */
5130         ret = hns3_update_imissed_stats(hw, true);
5131         if (ret) {
5132                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5133                 goto err_cmd_init;
5134         }
5135
5136         hns3_config_all_msix_error(hw, true);
5137
5138         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5139                                          hns3_interrupt_handler,
5140                                          eth_dev);
5141         if (ret) {
5142                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5143                 goto err_intr_callback_register;
5144         }
5145
5146         ret = hns3_ptp_init(hw);
5147         if (ret)
5148                 goto err_get_config;
5149
5150         /* Enable interrupt */
5151         rte_intr_enable(&pci_dev->intr_handle);
5152         hns3_pf_enable_irq0(hw);
5153
5154         /* Get configuration */
5155         ret = hns3_get_configuration(hw);
5156         if (ret) {
5157                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5158                 goto err_get_config;
5159         }
5160
5161         ret = hns3_tqp_stats_init(hw);
5162         if (ret)
5163                 goto err_get_config;
5164
5165         ret = hns3_init_hardware(hns);
5166         if (ret) {
5167                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5168                 goto err_init_hw;
5169         }
5170
5171         /* Initialize flow director filter list & hash */
5172         ret = hns3_fdir_filter_init(hns);
5173         if (ret) {
5174                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5175                 goto err_fdir;
5176         }
5177
5178         hns3_rss_set_default_args(hw);
5179
5180         ret = hns3_enable_hw_error_intr(hns, true);
5181         if (ret) {
5182                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5183                              ret);
5184                 goto err_enable_intr;
5185         }
5186
5187         ret = hns3_get_port_supported_speed(eth_dev);
5188         if (ret) {
5189                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5190                              "by device, ret = %d.", ret);
5191                 goto err_supported_speed;
5192         }
5193
5194         hns3_tm_conf_init(eth_dev);
5195
5196         return 0;
5197
5198 err_supported_speed:
5199         (void)hns3_enable_hw_error_intr(hns, false);
5200 err_enable_intr:
5201         hns3_fdir_filter_uninit(hns);
5202 err_fdir:
5203         hns3_uninit_umv_space(hw);
5204 err_init_hw:
5205         hns3_tqp_stats_uninit(hw);
5206 err_get_config:
5207         hns3_pf_disable_irq0(hw);
5208         rte_intr_disable(&pci_dev->intr_handle);
5209         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5210                              eth_dev);
5211 err_intr_callback_register:
5212 err_cmd_init:
5213         hns3_cmd_uninit(hw);
5214         hns3_cmd_destroy_queue(hw);
5215 err_cmd_init_queue:
5216         hw->io_base = NULL;
5217
5218         return ret;
5219 }
5220
5221 static void
5222 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5223 {
5224         struct hns3_adapter *hns = eth_dev->data->dev_private;
5225         struct rte_device *dev = eth_dev->device;
5226         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5227         struct hns3_hw *hw = &hns->hw;
5228
5229         PMD_INIT_FUNC_TRACE();
5230
5231         hns3_tm_conf_uninit(eth_dev);
5232         hns3_enable_hw_error_intr(hns, false);
5233         hns3_rss_uninit(hns);
5234         (void)hns3_config_gro(hw, false);
5235         hns3_promisc_uninit(hw);
5236         hns3_fdir_filter_uninit(hns);
5237         hns3_uninit_umv_space(hw);
5238         hns3_tqp_stats_uninit(hw);
5239         hns3_config_mac_tnl_int(hw, false);
5240         hns3_pf_disable_irq0(hw);
5241         rte_intr_disable(&pci_dev->intr_handle);
5242         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5243                              eth_dev);
5244         hns3_config_all_msix_error(hw, false);
5245         hns3_cmd_uninit(hw);
5246         hns3_cmd_destroy_queue(hw);
5247         hw->io_base = NULL;
5248 }
5249
5250 static int
5251 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5252 {
5253         struct hns3_hw *hw = &hns->hw;
5254         int ret;
5255
5256         ret = hns3_dcb_cfg_update(hns);
5257         if (ret)
5258                 return ret;
5259
5260         /*
5261          * The hns3_dcb_cfg_update may configure TM module, so
5262          * hns3_tm_conf_update must called later.
5263          */
5264         ret = hns3_tm_conf_update(hw);
5265         if (ret) {
5266                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5267                 return ret;
5268         }
5269
5270         hns3_enable_rxd_adv_layout(hw);
5271
5272         ret = hns3_init_queues(hns, reset_queue);
5273         if (ret) {
5274                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5275                 return ret;
5276         }
5277
5278         ret = hns3_cfg_mac_mode(hw, true);
5279         if (ret) {
5280                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5281                 goto err_config_mac_mode;
5282         }
5283         return 0;
5284
5285 err_config_mac_mode:
5286         hns3_dev_release_mbufs(hns);
5287         /*
5288          * Here is exception handling, hns3_reset_all_tqps will have the
5289          * corresponding error message if it is handled incorrectly, so it is
5290          * not necessary to check hns3_reset_all_tqps return value, here keep
5291          * ret as the error code causing the exception.
5292          */
5293         (void)hns3_reset_all_tqps(hns);
5294         return ret;
5295 }
5296
5297 static int
5298 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5299 {
5300         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5301         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5302         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5304         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5305         uint32_t intr_vector;
5306         uint16_t q_id;
5307         int ret;
5308
5309         /*
5310          * hns3 needs a separate interrupt to be used as event interrupt which
5311          * could not be shared with task queue pair, so KERNEL drivers need
5312          * support multiple interrupt vectors.
5313          */
5314         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5315             !rte_intr_cap_multiple(intr_handle))
5316                 return 0;
5317
5318         rte_intr_disable(intr_handle);
5319         intr_vector = hw->used_rx_queues;
5320         /* creates event fd for each intr vector when MSIX is used */
5321         if (rte_intr_efd_enable(intr_handle, intr_vector))
5322                 return -EINVAL;
5323
5324         if (intr_handle->intr_vec == NULL) {
5325                 intr_handle->intr_vec =
5326                         rte_zmalloc("intr_vec",
5327                                     hw->used_rx_queues * sizeof(int), 0);
5328                 if (intr_handle->intr_vec == NULL) {
5329                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5330                                         hw->used_rx_queues);
5331                         ret = -ENOMEM;
5332                         goto alloc_intr_vec_error;
5333                 }
5334         }
5335
5336         if (rte_intr_allow_others(intr_handle)) {
5337                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5338                 base = RTE_INTR_VEC_RXTX_OFFSET;
5339         }
5340
5341         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5342                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5343                                                  HNS3_RING_TYPE_RX, q_id);
5344                 if (ret)
5345                         goto bind_vector_error;
5346                 intr_handle->intr_vec[q_id] = vec;
5347                 /*
5348                  * If there are not enough efds (e.g. not enough interrupt),
5349                  * remaining queues will be bond to the last interrupt.
5350                  */
5351                 if (vec < base + intr_handle->nb_efd - 1)
5352                         vec++;
5353         }
5354         rte_intr_enable(intr_handle);
5355         return 0;
5356
5357 bind_vector_error:
5358         rte_free(intr_handle->intr_vec);
5359         intr_handle->intr_vec = NULL;
5360 alloc_intr_vec_error:
5361         rte_intr_efd_disable(intr_handle);
5362         return ret;
5363 }
5364
5365 static int
5366 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5367 {
5368         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5369         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5370         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5371         uint16_t q_id;
5372         int ret;
5373
5374         if (dev->data->dev_conf.intr_conf.rxq == 0)
5375                 return 0;
5376
5377         if (rte_intr_dp_is_en(intr_handle)) {
5378                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5379                         ret = hns3_bind_ring_with_vector(hw,
5380                                         intr_handle->intr_vec[q_id], true,
5381                                         HNS3_RING_TYPE_RX, q_id);
5382                         if (ret)
5383                                 return ret;
5384                 }
5385         }
5386
5387         return 0;
5388 }
5389
5390 static void
5391 hns3_restore_filter(struct rte_eth_dev *dev)
5392 {
5393         hns3_restore_rss_filter(dev);
5394 }
5395
5396 static int
5397 hns3_dev_start(struct rte_eth_dev *dev)
5398 {
5399         struct hns3_adapter *hns = dev->data->dev_private;
5400         struct hns3_hw *hw = &hns->hw;
5401         int ret;
5402
5403         PMD_INIT_FUNC_TRACE();
5404         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5405                 return -EBUSY;
5406
5407         rte_spinlock_lock(&hw->lock);
5408         hw->adapter_state = HNS3_NIC_STARTING;
5409
5410         ret = hns3_do_start(hns, true);
5411         if (ret) {
5412                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5413                 rte_spinlock_unlock(&hw->lock);
5414                 return ret;
5415         }
5416         ret = hns3_map_rx_interrupt(dev);
5417         if (ret)
5418                 goto map_rx_inter_err;
5419
5420         /*
5421          * There are three register used to control the status of a TQP
5422          * (contains a pair of Tx queue and Rx queue) in the new version network
5423          * engine. One is used to control the enabling of Tx queue, the other is
5424          * used to control the enabling of Rx queue, and the last is the master
5425          * switch used to control the enabling of the tqp. The Tx register and
5426          * TQP register must be enabled at the same time to enable a Tx queue.
5427          * The same applies to the Rx queue. For the older network engine, this
5428          * function only refresh the enabled flag, and it is used to update the
5429          * status of queue in the dpdk framework.
5430          */
5431         ret = hns3_start_all_txqs(dev);
5432         if (ret)
5433                 goto map_rx_inter_err;
5434
5435         ret = hns3_start_all_rxqs(dev);
5436         if (ret)
5437                 goto start_all_rxqs_fail;
5438
5439         hw->adapter_state = HNS3_NIC_STARTED;
5440         rte_spinlock_unlock(&hw->lock);
5441
5442         hns3_rx_scattered_calc(dev);
5443         hns3_set_rxtx_function(dev);
5444         hns3_mp_req_start_rxtx(dev);
5445
5446         hns3_restore_filter(dev);
5447
5448         /* Enable interrupt of all rx queues before enabling queues */
5449         hns3_dev_all_rx_queue_intr_enable(hw, true);
5450
5451         /*
5452          * After finished the initialization, enable tqps to receive/transmit
5453          * packets and refresh all queue status.
5454          */
5455         hns3_start_tqps(hw);
5456
5457         hns3_tm_dev_start_proc(hw);
5458
5459         if (dev->data->dev_conf.intr_conf.lsc != 0)
5460                 hns3_dev_link_update(dev, 0);
5461         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5462
5463         hns3_info(hw, "hns3 dev start successful!");
5464
5465         return 0;
5466
5467 start_all_rxqs_fail:
5468         hns3_stop_all_txqs(dev);
5469 map_rx_inter_err:
5470         (void)hns3_do_stop(hns);
5471         hw->adapter_state = HNS3_NIC_CONFIGURED;
5472         rte_spinlock_unlock(&hw->lock);
5473
5474         return ret;
5475 }
5476
5477 static int
5478 hns3_do_stop(struct hns3_adapter *hns)
5479 {
5480         struct hns3_hw *hw = &hns->hw;
5481         int ret;
5482
5483         /*
5484          * The "hns3_do_stop" function will also be called by .stop_service to
5485          * prepare reset. At the time of global or IMP reset, the command cannot
5486          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5487          * accessed during the reset process. So the mbuf can not be released
5488          * during reset and is required to be released after the reset is
5489          * completed.
5490          */
5491         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5492                 hns3_dev_release_mbufs(hns);
5493
5494         ret = hns3_cfg_mac_mode(hw, false);
5495         if (ret)
5496                 return ret;
5497         hw->mac.link_status = ETH_LINK_DOWN;
5498
5499         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5500                 hns3_configure_all_mac_addr(hns, true);
5501                 ret = hns3_reset_all_tqps(hns);
5502                 if (ret) {
5503                         hns3_err(hw, "failed to reset all queues ret = %d.",
5504                                  ret);
5505                         return ret;
5506                 }
5507         }
5508         hw->mac.default_addr_setted = false;
5509         return 0;
5510 }
5511
5512 static void
5513 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5514 {
5515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5517         struct hns3_adapter *hns = dev->data->dev_private;
5518         struct hns3_hw *hw = &hns->hw;
5519         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5520         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5521         uint16_t q_id;
5522
5523         if (dev->data->dev_conf.intr_conf.rxq == 0)
5524                 return;
5525
5526         /* unmap the ring with vector */
5527         if (rte_intr_allow_others(intr_handle)) {
5528                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5529                 base = RTE_INTR_VEC_RXTX_OFFSET;
5530         }
5531         if (rte_intr_dp_is_en(intr_handle)) {
5532                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5533                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5534                                                          HNS3_RING_TYPE_RX,
5535                                                          q_id);
5536                         if (vec < base + intr_handle->nb_efd - 1)
5537                                 vec++;
5538                 }
5539         }
5540         /* Clean datapath event and queue/vec mapping */
5541         rte_intr_efd_disable(intr_handle);
5542         if (intr_handle->intr_vec) {
5543                 rte_free(intr_handle->intr_vec);
5544                 intr_handle->intr_vec = NULL;
5545         }
5546 }
5547
5548 static int
5549 hns3_dev_stop(struct rte_eth_dev *dev)
5550 {
5551         struct hns3_adapter *hns = dev->data->dev_private;
5552         struct hns3_hw *hw = &hns->hw;
5553
5554         PMD_INIT_FUNC_TRACE();
5555         dev->data->dev_started = 0;
5556
5557         hw->adapter_state = HNS3_NIC_STOPPING;
5558         hns3_set_rxtx_function(dev);
5559         rte_wmb();
5560         /* Disable datapath on secondary process. */
5561         hns3_mp_req_stop_rxtx(dev);
5562         /* Prevent crashes when queues are still in use. */
5563         rte_delay_ms(hw->tqps_num);
5564
5565         rte_spinlock_lock(&hw->lock);
5566         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5567                 hns3_tm_dev_stop_proc(hw);
5568                 hns3_config_mac_tnl_int(hw, false);
5569                 hns3_stop_tqps(hw);
5570                 hns3_do_stop(hns);
5571                 hns3_unmap_rx_interrupt(dev);
5572                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5573         }
5574         hns3_rx_scattered_reset(dev);
5575         rte_eal_alarm_cancel(hns3_service_handler, dev);
5576         hns3_stop_report_lse(dev);
5577         rte_spinlock_unlock(&hw->lock);
5578
5579         return 0;
5580 }
5581
5582 static int
5583 hns3_dev_close(struct rte_eth_dev *eth_dev)
5584 {
5585         struct hns3_adapter *hns = eth_dev->data->dev_private;
5586         struct hns3_hw *hw = &hns->hw;
5587         int ret = 0;
5588
5589         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5590                 rte_free(eth_dev->process_private);
5591                 eth_dev->process_private = NULL;
5592                 return 0;
5593         }
5594
5595         if (hw->adapter_state == HNS3_NIC_STARTED)
5596                 ret = hns3_dev_stop(eth_dev);
5597
5598         hw->adapter_state = HNS3_NIC_CLOSING;
5599         hns3_reset_abort(hns);
5600         hw->adapter_state = HNS3_NIC_CLOSED;
5601
5602         hns3_configure_all_mc_mac_addr(hns, true);
5603         hns3_remove_all_vlan_table(hns);
5604         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5605         hns3_uninit_pf(eth_dev);
5606         hns3_free_all_queues(eth_dev);
5607         rte_free(hw->reset.wait_data);
5608         rte_free(eth_dev->process_private);
5609         eth_dev->process_private = NULL;
5610         hns3_mp_uninit_primary();
5611         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5612
5613         return ret;
5614 }
5615
5616 static int
5617 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5618 {
5619         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5620         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5621
5622         fc_conf->pause_time = pf->pause_time;
5623
5624         /*
5625          * If fc auto-negotiation is not supported, the configured fc mode
5626          * from user is the current fc mode.
5627          */
5628         switch (hw->requested_fc_mode) {
5629         case HNS3_FC_FULL:
5630                 fc_conf->mode = RTE_FC_FULL;
5631                 break;
5632         case HNS3_FC_TX_PAUSE:
5633                 fc_conf->mode = RTE_FC_TX_PAUSE;
5634                 break;
5635         case HNS3_FC_RX_PAUSE:
5636                 fc_conf->mode = RTE_FC_RX_PAUSE;
5637                 break;
5638         case HNS3_FC_NONE:
5639         default:
5640                 fc_conf->mode = RTE_FC_NONE;
5641                 break;
5642         }
5643
5644         return 0;
5645 }
5646
5647 static void
5648 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5649 {
5650         switch (mode) {
5651         case RTE_FC_NONE:
5652                 hw->requested_fc_mode = HNS3_FC_NONE;
5653                 break;
5654         case RTE_FC_RX_PAUSE:
5655                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
5656                 break;
5657         case RTE_FC_TX_PAUSE:
5658                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
5659                 break;
5660         case RTE_FC_FULL:
5661                 hw->requested_fc_mode = HNS3_FC_FULL;
5662                 break;
5663         default:
5664                 hw->requested_fc_mode = HNS3_FC_NONE;
5665                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5666                           "configured to RTE_FC_NONE", mode);
5667                 break;
5668         }
5669 }
5670
5671 static int
5672 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5673 {
5674         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5675         int ret;
5676
5677         if (fc_conf->high_water || fc_conf->low_water ||
5678             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5679                 hns3_err(hw, "Unsupported flow control settings specified, "
5680                          "high_water(%u), low_water(%u), send_xon(%u) and "
5681                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5682                          fc_conf->high_water, fc_conf->low_water,
5683                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5684                 return -EINVAL;
5685         }
5686         if (fc_conf->autoneg) {
5687                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5688                 return -EINVAL;
5689         }
5690         if (!fc_conf->pause_time) {
5691                 hns3_err(hw, "Invalid pause time %u setting.",
5692                          fc_conf->pause_time);
5693                 return -EINVAL;
5694         }
5695
5696         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5697             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5698                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5699                          "current_fc_status = %d", hw->current_fc_status);
5700                 return -EOPNOTSUPP;
5701         }
5702
5703         if (hw->num_tc > 1) {
5704                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5705                 return -EOPNOTSUPP;
5706         }
5707
5708         hns3_get_fc_mode(hw, fc_conf->mode);
5709
5710         rte_spinlock_lock(&hw->lock);
5711         ret = hns3_fc_enable(dev, fc_conf);
5712         rte_spinlock_unlock(&hw->lock);
5713
5714         return ret;
5715 }
5716
5717 static int
5718 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5719                             struct rte_eth_pfc_conf *pfc_conf)
5720 {
5721         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722         int ret;
5723
5724         if (!hns3_dev_dcb_supported(hw)) {
5725                 hns3_err(hw, "This port does not support dcb configurations.");
5726                 return -EOPNOTSUPP;
5727         }
5728
5729         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5730             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5731                 hns3_err(hw, "Unsupported flow control settings specified, "
5732                          "high_water(%u), low_water(%u), send_xon(%u) and "
5733                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5734                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5735                          pfc_conf->fc.send_xon,
5736                          pfc_conf->fc.mac_ctrl_frame_fwd);
5737                 return -EINVAL;
5738         }
5739         if (pfc_conf->fc.autoneg) {
5740                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5741                 return -EINVAL;
5742         }
5743         if (pfc_conf->fc.pause_time == 0) {
5744                 hns3_err(hw, "Invalid pause time %u setting.",
5745                          pfc_conf->fc.pause_time);
5746                 return -EINVAL;
5747         }
5748
5749         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5750             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5751                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5752                              "current_fc_status = %d", hw->current_fc_status);
5753                 return -EOPNOTSUPP;
5754         }
5755
5756         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5757
5758         rte_spinlock_lock(&hw->lock);
5759         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5760         rte_spinlock_unlock(&hw->lock);
5761
5762         return ret;
5763 }
5764
5765 static int
5766 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5767 {
5768         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5770         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5771         int i;
5772
5773         rte_spinlock_lock(&hw->lock);
5774         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5775                 dcb_info->nb_tcs = pf->local_max_tc;
5776         else
5777                 dcb_info->nb_tcs = 1;
5778
5779         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5780                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5781         for (i = 0; i < dcb_info->nb_tcs; i++)
5782                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5783
5784         for (i = 0; i < hw->num_tc; i++) {
5785                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5786                 dcb_info->tc_queue.tc_txq[0][i].base =
5787                                                 hw->tc_queue[i].tqp_offset;
5788                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5789                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5790                                                 hw->tc_queue[i].tqp_count;
5791         }
5792         rte_spinlock_unlock(&hw->lock);
5793
5794         return 0;
5795 }
5796
5797 static int
5798 hns3_reinit_dev(struct hns3_adapter *hns)
5799 {
5800         struct hns3_hw *hw = &hns->hw;
5801         int ret;
5802
5803         ret = hns3_cmd_init(hw);
5804         if (ret) {
5805                 hns3_err(hw, "Failed to init cmd: %d", ret);
5806                 return ret;
5807         }
5808
5809         ret = hns3_reset_all_tqps(hns);
5810         if (ret) {
5811                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5812                 return ret;
5813         }
5814
5815         ret = hns3_init_hardware(hns);
5816         if (ret) {
5817                 hns3_err(hw, "Failed to init hardware: %d", ret);
5818                 return ret;
5819         }
5820
5821         ret = hns3_enable_hw_error_intr(hns, true);
5822         if (ret) {
5823                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5824                              ret);
5825                 return ret;
5826         }
5827         hns3_info(hw, "Reset done, driver initialization finished.");
5828
5829         return 0;
5830 }
5831
5832 static bool
5833 is_pf_reset_done(struct hns3_hw *hw)
5834 {
5835         uint32_t val, reg, reg_bit;
5836
5837         switch (hw->reset.level) {
5838         case HNS3_IMP_RESET:
5839                 reg = HNS3_GLOBAL_RESET_REG;
5840                 reg_bit = HNS3_IMP_RESET_BIT;
5841                 break;
5842         case HNS3_GLOBAL_RESET:
5843                 reg = HNS3_GLOBAL_RESET_REG;
5844                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5845                 break;
5846         case HNS3_FUNC_RESET:
5847                 reg = HNS3_FUN_RST_ING;
5848                 reg_bit = HNS3_FUN_RST_ING_B;
5849                 break;
5850         case HNS3_FLR_RESET:
5851         default:
5852                 hns3_err(hw, "Wait for unsupported reset level: %d",
5853                          hw->reset.level);
5854                 return true;
5855         }
5856         val = hns3_read_dev(hw, reg);
5857         if (hns3_get_bit(val, reg_bit))
5858                 return false;
5859         else
5860                 return true;
5861 }
5862
5863 bool
5864 hns3_is_reset_pending(struct hns3_adapter *hns)
5865 {
5866         struct hns3_hw *hw = &hns->hw;
5867         enum hns3_reset_level reset;
5868
5869         hns3_check_event_cause(hns, NULL);
5870         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5871         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5872                 hns3_warn(hw, "High level reset %d is pending", reset);
5873                 return true;
5874         }
5875         reset = hns3_get_reset_level(hns, &hw->reset.request);
5876         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5877                 hns3_warn(hw, "High level reset %d is request", reset);
5878                 return true;
5879         }
5880         return false;
5881 }
5882
5883 static int
5884 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5885 {
5886         struct hns3_hw *hw = &hns->hw;
5887         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5888         struct timeval tv;
5889
5890         if (wait_data->result == HNS3_WAIT_SUCCESS)
5891                 return 0;
5892         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5893                 gettimeofday(&tv, NULL);
5894                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5895                           tv.tv_sec, tv.tv_usec);
5896                 return -ETIME;
5897         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5898                 return -EAGAIN;
5899
5900         wait_data->hns = hns;
5901         wait_data->check_completion = is_pf_reset_done;
5902         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5903                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5904         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5905         wait_data->count = HNS3_RESET_WAIT_CNT;
5906         wait_data->result = HNS3_WAIT_REQUEST;
5907         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5908         return -EAGAIN;
5909 }
5910
5911 static int
5912 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5913 {
5914         struct hns3_cmd_desc desc;
5915         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5916
5917         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5918         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5919         req->fun_reset_vfid = func_id;
5920
5921         return hns3_cmd_send(hw, &desc, 1);
5922 }
5923
5924 static int
5925 hns3_imp_reset_cmd(struct hns3_hw *hw)
5926 {
5927         struct hns3_cmd_desc desc;
5928
5929         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5930         desc.data[0] = 0xeedd;
5931
5932         return hns3_cmd_send(hw, &desc, 1);
5933 }
5934
5935 static void
5936 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5937 {
5938         struct hns3_hw *hw = &hns->hw;
5939         struct timeval tv;
5940         uint32_t val;
5941
5942         gettimeofday(&tv, NULL);
5943         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5944             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5945                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5946                           tv.tv_sec, tv.tv_usec);
5947                 return;
5948         }
5949
5950         switch (reset_level) {
5951         case HNS3_IMP_RESET:
5952                 hns3_imp_reset_cmd(hw);
5953                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5954                           tv.tv_sec, tv.tv_usec);
5955                 break;
5956         case HNS3_GLOBAL_RESET:
5957                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5958                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5959                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5960                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5961                           tv.tv_sec, tv.tv_usec);
5962                 break;
5963         case HNS3_FUNC_RESET:
5964                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5965                           tv.tv_sec, tv.tv_usec);
5966                 /* schedule again to check later */
5967                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5968                 hns3_schedule_reset(hns);
5969                 break;
5970         default:
5971                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5972                 return;
5973         }
5974         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5975 }
5976
5977 static enum hns3_reset_level
5978 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5979 {
5980         struct hns3_hw *hw = &hns->hw;
5981         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5982
5983         /* Return the highest priority reset level amongst all */
5984         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5985                 reset_level = HNS3_IMP_RESET;
5986         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5987                 reset_level = HNS3_GLOBAL_RESET;
5988         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5989                 reset_level = HNS3_FUNC_RESET;
5990         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5991                 reset_level = HNS3_FLR_RESET;
5992
5993         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5994                 return HNS3_NONE_RESET;
5995
5996         return reset_level;
5997 }
5998
5999 static void
6000 hns3_record_imp_error(struct hns3_adapter *hns)
6001 {
6002         struct hns3_hw *hw = &hns->hw;
6003         uint32_t reg_val;
6004
6005         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6006         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6007                 hns3_warn(hw, "Detected IMP RD poison!");
6008                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6009                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6010         }
6011
6012         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6013                 hns3_warn(hw, "Detected IMP CMDQ error!");
6014                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6015                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6016         }
6017 }
6018
6019 static int
6020 hns3_prepare_reset(struct hns3_adapter *hns)
6021 {
6022         struct hns3_hw *hw = &hns->hw;
6023         uint32_t reg_val;
6024         int ret;
6025
6026         switch (hw->reset.level) {
6027         case HNS3_FUNC_RESET:
6028                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6029                 if (ret)
6030                         return ret;
6031
6032                 /*
6033                  * After performaning pf reset, it is not necessary to do the
6034                  * mailbox handling or send any command to firmware, because
6035                  * any mailbox handling or command to firmware is only valid
6036                  * after hns3_cmd_init is called.
6037                  */
6038                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6039                 hw->reset.stats.request_cnt++;
6040                 break;
6041         case HNS3_IMP_RESET:
6042                 hns3_record_imp_error(hns);
6043                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6044                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6045                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6046                 break;
6047         default:
6048                 break;
6049         }
6050         return 0;
6051 }
6052
6053 static int
6054 hns3_set_rst_done(struct hns3_hw *hw)
6055 {
6056         struct hns3_pf_rst_done_cmd *req;
6057         struct hns3_cmd_desc desc;
6058
6059         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6060         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6061         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6062         return hns3_cmd_send(hw, &desc, 1);
6063 }
6064
6065 static int
6066 hns3_stop_service(struct hns3_adapter *hns)
6067 {
6068         struct hns3_hw *hw = &hns->hw;
6069         struct rte_eth_dev *eth_dev;
6070
6071         eth_dev = &rte_eth_devices[hw->data->port_id];
6072         hw->mac.link_status = ETH_LINK_DOWN;
6073         if (hw->adapter_state == HNS3_NIC_STARTED) {
6074                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6075                 hns3_update_linkstatus_and_event(hw, false);
6076         }
6077
6078         hns3_set_rxtx_function(eth_dev);
6079         rte_wmb();
6080         /* Disable datapath on secondary process. */
6081         hns3_mp_req_stop_rxtx(eth_dev);
6082         rte_delay_ms(hw->tqps_num);
6083
6084         rte_spinlock_lock(&hw->lock);
6085         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6086             hw->adapter_state == HNS3_NIC_STOPPING) {
6087                 hns3_enable_all_queues(hw, false);
6088                 hns3_do_stop(hns);
6089                 hw->reset.mbuf_deferred_free = true;
6090         } else
6091                 hw->reset.mbuf_deferred_free = false;
6092
6093         /*
6094          * It is cumbersome for hardware to pick-and-choose entries for deletion
6095          * from table space. Hence, for function reset software intervention is
6096          * required to delete the entries
6097          */
6098         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6099                 hns3_configure_all_mc_mac_addr(hns, true);
6100         rte_spinlock_unlock(&hw->lock);
6101
6102         return 0;
6103 }
6104
6105 static int
6106 hns3_start_service(struct hns3_adapter *hns)
6107 {
6108         struct hns3_hw *hw = &hns->hw;
6109         struct rte_eth_dev *eth_dev;
6110
6111         if (hw->reset.level == HNS3_IMP_RESET ||
6112             hw->reset.level == HNS3_GLOBAL_RESET)
6113                 hns3_set_rst_done(hw);
6114         eth_dev = &rte_eth_devices[hw->data->port_id];
6115         hns3_set_rxtx_function(eth_dev);
6116         hns3_mp_req_start_rxtx(eth_dev);
6117         if (hw->adapter_state == HNS3_NIC_STARTED) {
6118                 /*
6119                  * This API parent function already hold the hns3_hw.lock, the
6120                  * hns3_service_handler may report lse, in bonding application
6121                  * it will call driver's ops which may acquire the hns3_hw.lock
6122                  * again, thus lead to deadlock.
6123                  * We defer calls hns3_service_handler to avoid the deadlock.
6124                  */
6125                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6126                                   hns3_service_handler, eth_dev);
6127
6128                 /* Enable interrupt of all rx queues before enabling queues */
6129                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6130                 /*
6131                  * Enable state of each rxq and txq will be recovered after
6132                  * reset, so we need to restore them before enable all tqps;
6133                  */
6134                 hns3_restore_tqp_enable_state(hw);
6135                 /*
6136                  * When finished the initialization, enable queues to receive
6137                  * and transmit packets.
6138                  */
6139                 hns3_enable_all_queues(hw, true);
6140         }
6141
6142         return 0;
6143 }
6144
6145 static int
6146 hns3_restore_conf(struct hns3_adapter *hns)
6147 {
6148         struct hns3_hw *hw = &hns->hw;
6149         int ret;
6150
6151         ret = hns3_configure_all_mac_addr(hns, false);
6152         if (ret)
6153                 return ret;
6154
6155         ret = hns3_configure_all_mc_mac_addr(hns, false);
6156         if (ret)
6157                 goto err_mc_mac;
6158
6159         ret = hns3_dev_promisc_restore(hns);
6160         if (ret)
6161                 goto err_promisc;
6162
6163         ret = hns3_restore_vlan_table(hns);
6164         if (ret)
6165                 goto err_promisc;
6166
6167         ret = hns3_restore_vlan_conf(hns);
6168         if (ret)
6169                 goto err_promisc;
6170
6171         ret = hns3_restore_all_fdir_filter(hns);
6172         if (ret)
6173                 goto err_promisc;
6174
6175         ret = hns3_restore_ptp(hns);
6176         if (ret)
6177                 goto err_promisc;
6178
6179         ret = hns3_restore_rx_interrupt(hw);
6180         if (ret)
6181                 goto err_promisc;
6182
6183         ret = hns3_restore_gro_conf(hw);
6184         if (ret)
6185                 goto err_promisc;
6186
6187         ret = hns3_restore_fec(hw);
6188         if (ret)
6189                 goto err_promisc;
6190
6191         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6192                 ret = hns3_do_start(hns, false);
6193                 if (ret)
6194                         goto err_promisc;
6195                 hns3_info(hw, "hns3 dev restart successful!");
6196         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6197                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6198         return 0;
6199
6200 err_promisc:
6201         hns3_configure_all_mc_mac_addr(hns, true);
6202 err_mc_mac:
6203         hns3_configure_all_mac_addr(hns, true);
6204         return ret;
6205 }
6206
6207 static void
6208 hns3_reset_service(void *param)
6209 {
6210         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6211         struct hns3_hw *hw = &hns->hw;
6212         enum hns3_reset_level reset_level;
6213         struct timeval tv_delta;
6214         struct timeval tv_start;
6215         struct timeval tv;
6216         uint64_t msec;
6217         int ret;
6218
6219         /*
6220          * The interrupt is not triggered within the delay time.
6221          * The interrupt may have been lost. It is necessary to handle
6222          * the interrupt to recover from the error.
6223          */
6224         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6225                             SCHEDULE_DEFERRED) {
6226                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6227                                   __ATOMIC_RELAXED);
6228                 hns3_err(hw, "Handling interrupts in delayed tasks");
6229                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6230                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6231                 if (reset_level == HNS3_NONE_RESET) {
6232                         hns3_err(hw, "No reset level is set, try IMP reset");
6233                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6234                 }
6235         }
6236         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6237
6238         /*
6239          * Check if there is any ongoing reset in the hardware. This status can
6240          * be checked from reset_pending. If there is then, we need to wait for
6241          * hardware to complete reset.
6242          *    a. If we are able to figure out in reasonable time that hardware
6243          *       has fully resetted then, we can proceed with driver, client
6244          *       reset.
6245          *    b. else, we can come back later to check this status so re-sched
6246          *       now.
6247          */
6248         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6249         if (reset_level != HNS3_NONE_RESET) {
6250                 gettimeofday(&tv_start, NULL);
6251                 ret = hns3_reset_process(hns, reset_level);
6252                 gettimeofday(&tv, NULL);
6253                 timersub(&tv, &tv_start, &tv_delta);
6254                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6255                        tv_delta.tv_usec / USEC_PER_MSEC;
6256                 if (msec > HNS3_RESET_PROCESS_MS)
6257                         hns3_err(hw, "%d handle long time delta %" PRIx64
6258                                      " ms time=%ld.%.6ld",
6259                                  hw->reset.level, msec,
6260                                  tv.tv_sec, tv.tv_usec);
6261                 if (ret == -EAGAIN)
6262                         return;
6263         }
6264
6265         /* Check if we got any *new* reset requests to be honored */
6266         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6267         if (reset_level != HNS3_NONE_RESET)
6268                 hns3_msix_process(hns, reset_level);
6269 }
6270
6271 static unsigned int
6272 hns3_get_speed_capa_num(uint16_t device_id)
6273 {
6274         unsigned int num;
6275
6276         switch (device_id) {
6277         case HNS3_DEV_ID_25GE:
6278         case HNS3_DEV_ID_25GE_RDMA:
6279                 num = 2;
6280                 break;
6281         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6282         case HNS3_DEV_ID_200G_RDMA:
6283                 num = 1;
6284                 break;
6285         default:
6286                 num = 0;
6287                 break;
6288         }
6289
6290         return num;
6291 }
6292
6293 static int
6294 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6295                         uint16_t device_id)
6296 {
6297         switch (device_id) {
6298         case HNS3_DEV_ID_25GE:
6299         /* fallthrough */
6300         case HNS3_DEV_ID_25GE_RDMA:
6301                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6302                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6303
6304                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6305                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6306                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6307                 break;
6308         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6309                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6310                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6311                 break;
6312         case HNS3_DEV_ID_200G_RDMA:
6313                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6314                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6315                 break;
6316         default:
6317                 return -ENOTSUP;
6318         }
6319
6320         return 0;
6321 }
6322
6323 static int
6324 hns3_fec_get_capability(struct rte_eth_dev *dev,
6325                         struct rte_eth_fec_capa *speed_fec_capa,
6326                         unsigned int num)
6327 {
6328         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6330         uint16_t device_id = pci_dev->id.device_id;
6331         unsigned int capa_num;
6332         int ret;
6333
6334         capa_num = hns3_get_speed_capa_num(device_id);
6335         if (capa_num == 0) {
6336                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6337                          device_id);
6338                 return -ENOTSUP;
6339         }
6340
6341         if (speed_fec_capa == NULL || num < capa_num)
6342                 return capa_num;
6343
6344         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6345         if (ret)
6346                 return -ENOTSUP;
6347
6348         return capa_num;
6349 }
6350
6351 static int
6352 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6353 {
6354         struct hns3_config_fec_cmd *req;
6355         struct hns3_cmd_desc desc;
6356         int ret;
6357
6358         /*
6359          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6360          * in device of link speed
6361          * below 10 Gbps.
6362          */
6363         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6364                 *state = 0;
6365                 return 0;
6366         }
6367
6368         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6369         req = (struct hns3_config_fec_cmd *)desc.data;
6370         ret = hns3_cmd_send(hw, &desc, 1);
6371         if (ret) {
6372                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6373                          ret);
6374                 return ret;
6375         }
6376
6377         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6378         return 0;
6379 }
6380
6381 static int
6382 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6383 {
6384         struct hns3_sfp_info_cmd *resp;
6385         uint32_t tmp_fec_capa;
6386         uint8_t auto_state;
6387         struct hns3_cmd_desc desc;
6388         int ret;
6389
6390         /*
6391          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6392          * configured FEC mode is returned.
6393          * If link is up, current FEC mode is returned.
6394          */
6395         if (hw->mac.link_status == ETH_LINK_DOWN) {
6396                 ret = get_current_fec_auto_state(hw, &auto_state);
6397                 if (ret)
6398                         return ret;
6399
6400                 if (auto_state == 0x1) {
6401                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6402                         return 0;
6403                 }
6404         }
6405
6406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6407         resp = (struct hns3_sfp_info_cmd *)desc.data;
6408         resp->query_type = HNS3_ACTIVE_QUERY;
6409
6410         ret = hns3_cmd_send(hw, &desc, 1);
6411         if (ret == -EOPNOTSUPP) {
6412                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6413                 return ret;
6414         } else if (ret) {
6415                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6416                 return ret;
6417         }
6418
6419         /*
6420          * FEC mode order defined in hns3 hardware is inconsistend with
6421          * that defined in the ethdev library. So the sequence needs
6422          * to be converted.
6423          */
6424         switch (resp->active_fec) {
6425         case HNS3_HW_FEC_MODE_NOFEC:
6426                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6427                 break;
6428         case HNS3_HW_FEC_MODE_BASER:
6429                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6430                 break;
6431         case HNS3_HW_FEC_MODE_RS:
6432                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6433                 break;
6434         default:
6435                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6436                 break;
6437         }
6438
6439         *fec_capa = tmp_fec_capa;
6440         return 0;
6441 }
6442
6443 static int
6444 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6445 {
6446         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6447
6448         return hns3_fec_get_internal(hw, fec_capa);
6449 }
6450
6451 static int
6452 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6453 {
6454         struct hns3_config_fec_cmd *req;
6455         struct hns3_cmd_desc desc;
6456         int ret;
6457
6458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6459
6460         req = (struct hns3_config_fec_cmd *)desc.data;
6461         switch (mode) {
6462         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6463                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6464                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6465                 break;
6466         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6467                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6468                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6469                 break;
6470         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6471                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6472                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6473                 break;
6474         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6475                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6476                 break;
6477         default:
6478                 return 0;
6479         }
6480         ret = hns3_cmd_send(hw, &desc, 1);
6481         if (ret)
6482                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6483
6484         return ret;
6485 }
6486
6487 static uint32_t
6488 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6489 {
6490         struct hns3_mac *mac = &hw->mac;
6491         uint32_t cur_capa;
6492
6493         switch (mac->link_speed) {
6494         case ETH_SPEED_NUM_10G:
6495                 cur_capa = fec_capa[1].capa;
6496                 break;
6497         case ETH_SPEED_NUM_25G:
6498         case ETH_SPEED_NUM_100G:
6499         case ETH_SPEED_NUM_200G:
6500                 cur_capa = fec_capa[0].capa;
6501                 break;
6502         default:
6503                 cur_capa = 0;
6504                 break;
6505         }
6506
6507         return cur_capa;
6508 }
6509
6510 static bool
6511 is_fec_mode_one_bit_set(uint32_t mode)
6512 {
6513         int cnt = 0;
6514         uint8_t i;
6515
6516         for (i = 0; i < sizeof(mode); i++)
6517                 if (mode >> i & 0x1)
6518                         cnt++;
6519
6520         return cnt == 1 ? true : false;
6521 }
6522
6523 static int
6524 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6525 {
6526 #define FEC_CAPA_NUM 2
6527         struct hns3_adapter *hns = dev->data->dev_private;
6528         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6529         struct hns3_pf *pf = &hns->pf;
6530
6531         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6532         uint32_t cur_capa;
6533         uint32_t num = FEC_CAPA_NUM;
6534         int ret;
6535
6536         ret = hns3_fec_get_capability(dev, fec_capa, num);
6537         if (ret < 0)
6538                 return ret;
6539
6540         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6541         if (!is_fec_mode_one_bit_set(mode))
6542                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6543                              "FEC mode should be only one bit set", mode);
6544
6545         /*
6546          * Check whether the configured mode is within the FEC capability.
6547          * If not, the configured mode will not be supported.
6548          */
6549         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6550         if (!(cur_capa & mode)) {
6551                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6552                 return -EINVAL;
6553         }
6554
6555         rte_spinlock_lock(&hw->lock);
6556         ret = hns3_set_fec_hw(hw, mode);
6557         if (ret) {
6558                 rte_spinlock_unlock(&hw->lock);
6559                 return ret;
6560         }
6561
6562         pf->fec_mode = mode;
6563         rte_spinlock_unlock(&hw->lock);
6564
6565         return 0;
6566 }
6567
6568 static int
6569 hns3_restore_fec(struct hns3_hw *hw)
6570 {
6571         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6572         struct hns3_pf *pf = &hns->pf;
6573         uint32_t mode = pf->fec_mode;
6574         int ret;
6575
6576         ret = hns3_set_fec_hw(hw, mode);
6577         if (ret)
6578                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6579                          mode, ret);
6580
6581         return ret;
6582 }
6583
6584 static int
6585 hns3_query_dev_fec_info(struct hns3_hw *hw)
6586 {
6587         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6588         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6589         int ret;
6590
6591         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6592         if (ret)
6593                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6594
6595         return ret;
6596 }
6597
6598 static bool
6599 hns3_optical_module_existed(struct hns3_hw *hw)
6600 {
6601         struct hns3_cmd_desc desc;
6602         bool existed;
6603         int ret;
6604
6605         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6606         ret = hns3_cmd_send(hw, &desc, 1);
6607         if (ret) {
6608                 hns3_err(hw,
6609                          "fail to get optical module exist state, ret = %d.\n",
6610                          ret);
6611                 return false;
6612         }
6613         existed = !!desc.data[0];
6614
6615         return existed;
6616 }
6617
6618 static int
6619 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6620                                 uint32_t len, uint8_t *data)
6621 {
6622 #define HNS3_SFP_INFO_CMD_NUM 6
6623 #define HNS3_SFP_INFO_MAX_LEN \
6624         (HNS3_SFP_INFO_BD0_LEN + \
6625         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6626         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6627         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6628         uint16_t read_len;
6629         uint16_t copy_len;
6630         int ret;
6631         int i;
6632
6633         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6634                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6635                                           true);
6636                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6637                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6638         }
6639
6640         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6641         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6642         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6643         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6644
6645         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6646         if (ret) {
6647                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6648                                 ret);
6649                 return ret;
6650         }
6651
6652         /* The data format in BD0 is different with the others. */
6653         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6654         memcpy(data, sfp_info_bd0->data, copy_len);
6655         read_len = copy_len;
6656
6657         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6658                 if (read_len >= len)
6659                         break;
6660
6661                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6662                 memcpy(data + read_len, desc[i].data, copy_len);
6663                 read_len += copy_len;
6664         }
6665
6666         return (int)read_len;
6667 }
6668
6669 static int
6670 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6671                        struct rte_dev_eeprom_info *info)
6672 {
6673         struct hns3_adapter *hns = dev->data->dev_private;
6674         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6675         uint32_t offset = info->offset;
6676         uint32_t len = info->length;
6677         uint8_t *data = info->data;
6678         uint32_t read_len = 0;
6679
6680         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6681                 return -ENOTSUP;
6682
6683         if (!hns3_optical_module_existed(hw)) {
6684                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6685                 return -EIO;
6686         }
6687
6688         while (read_len < len) {
6689                 int ret;
6690                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6691                                                   len - read_len,
6692                                                   data + read_len);
6693                 if (ret < 0)
6694                         return -EIO;
6695                 read_len += ret;
6696         }
6697
6698         return 0;
6699 }
6700
6701 static int
6702 hns3_get_module_info(struct rte_eth_dev *dev,
6703                      struct rte_eth_dev_module_info *modinfo)
6704 {
6705 #define HNS3_SFF8024_ID_SFP             0x03
6706 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6707 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6708 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6709 #define HNS3_SFF_8636_V1_3              0x03
6710         struct hns3_adapter *hns = dev->data->dev_private;
6711         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6712         struct rte_dev_eeprom_info info;
6713         struct hns3_sfp_type sfp_type;
6714         int ret;
6715
6716         memset(&sfp_type, 0, sizeof(sfp_type));
6717         memset(&info, 0, sizeof(info));
6718         info.data = (uint8_t *)&sfp_type;
6719         info.length = sizeof(sfp_type);
6720         ret = hns3_get_module_eeprom(dev, &info);
6721         if (ret)
6722                 return ret;
6723
6724         switch (sfp_type.type) {
6725         case HNS3_SFF8024_ID_SFP:
6726                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6727                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6728                 break;
6729         case HNS3_SFF8024_ID_QSFP_8438:
6730                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6731                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6732                 break;
6733         case HNS3_SFF8024_ID_QSFP_8436_8636:
6734                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6735                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6736                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6737                 } else {
6738                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6739                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6740                 }
6741                 break;
6742         case HNS3_SFF8024_ID_QSFP28_8636:
6743                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6744                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6745                 break;
6746         default:
6747                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6748                          sfp_type.type, sfp_type.ext_type);
6749                 return -EINVAL;
6750         }
6751
6752         return 0;
6753 }
6754
6755 static int
6756 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6757 {
6758         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6759
6760         RTE_SET_USED(key);
6761
6762         if (strcmp(value, "vec") == 0)
6763                 hint = HNS3_IO_FUNC_HINT_VEC;
6764         else if (strcmp(value, "sve") == 0)
6765                 hint = HNS3_IO_FUNC_HINT_SVE;
6766         else if (strcmp(value, "simple") == 0)
6767                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6768         else if (strcmp(value, "common") == 0)
6769                 hint = HNS3_IO_FUNC_HINT_COMMON;
6770
6771         /* If the hint is valid then update output parameters */
6772         if (hint != HNS3_IO_FUNC_HINT_NONE)
6773                 *(uint32_t *)extra_args = hint;
6774
6775         return 0;
6776 }
6777
6778 static const char *
6779 hns3_get_io_hint_func_name(uint32_t hint)
6780 {
6781         switch (hint) {
6782         case HNS3_IO_FUNC_HINT_VEC:
6783                 return "vec";
6784         case HNS3_IO_FUNC_HINT_SVE:
6785                 return "sve";
6786         case HNS3_IO_FUNC_HINT_SIMPLE:
6787                 return "simple";
6788         case HNS3_IO_FUNC_HINT_COMMON:
6789                 return "common";
6790         default:
6791                 return "none";
6792         }
6793 }
6794
6795 void
6796 hns3_parse_devargs(struct rte_eth_dev *dev)
6797 {
6798         struct hns3_adapter *hns = dev->data->dev_private;
6799         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6800         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6801         struct hns3_hw *hw = &hns->hw;
6802         struct rte_kvargs *kvlist;
6803
6804         if (dev->device->devargs == NULL)
6805                 return;
6806
6807         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6808         if (!kvlist)
6809                 return;
6810
6811         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6812                            &hns3_parse_io_hint_func, &rx_func_hint);
6813         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6814                            &hns3_parse_io_hint_func, &tx_func_hint);
6815         rte_kvargs_free(kvlist);
6816
6817         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6818                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6819                           hns3_get_io_hint_func_name(rx_func_hint));
6820         hns->rx_func_hint = rx_func_hint;
6821         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6822                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6823                           hns3_get_io_hint_func_name(tx_func_hint));
6824         hns->tx_func_hint = tx_func_hint;
6825 }
6826
6827 static const struct eth_dev_ops hns3_eth_dev_ops = {
6828         .dev_configure      = hns3_dev_configure,
6829         .dev_start          = hns3_dev_start,
6830         .dev_stop           = hns3_dev_stop,
6831         .dev_close          = hns3_dev_close,
6832         .promiscuous_enable = hns3_dev_promiscuous_enable,
6833         .promiscuous_disable = hns3_dev_promiscuous_disable,
6834         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6835         .allmulticast_disable = hns3_dev_allmulticast_disable,
6836         .mtu_set            = hns3_dev_mtu_set,
6837         .stats_get          = hns3_stats_get,
6838         .stats_reset        = hns3_stats_reset,
6839         .xstats_get         = hns3_dev_xstats_get,
6840         .xstats_get_names   = hns3_dev_xstats_get_names,
6841         .xstats_reset       = hns3_dev_xstats_reset,
6842         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6843         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6844         .dev_infos_get          = hns3_dev_infos_get,
6845         .fw_version_get         = hns3_fw_version_get,
6846         .rx_queue_setup         = hns3_rx_queue_setup,
6847         .tx_queue_setup         = hns3_tx_queue_setup,
6848         .rx_queue_release       = hns3_dev_rx_queue_release,
6849         .tx_queue_release       = hns3_dev_tx_queue_release,
6850         .rx_queue_start         = hns3_dev_rx_queue_start,
6851         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6852         .tx_queue_start         = hns3_dev_tx_queue_start,
6853         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6854         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6855         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6856         .rxq_info_get           = hns3_rxq_info_get,
6857         .txq_info_get           = hns3_txq_info_get,
6858         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6859         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6860         .flow_ctrl_get          = hns3_flow_ctrl_get,
6861         .flow_ctrl_set          = hns3_flow_ctrl_set,
6862         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6863         .mac_addr_add           = hns3_add_mac_addr,
6864         .mac_addr_remove        = hns3_remove_mac_addr,
6865         .mac_addr_set           = hns3_set_default_mac_addr,
6866         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6867         .link_update            = hns3_dev_link_update,
6868         .rss_hash_update        = hns3_dev_rss_hash_update,
6869         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6870         .reta_update            = hns3_dev_rss_reta_update,
6871         .reta_query             = hns3_dev_rss_reta_query,
6872         .flow_ops_get           = hns3_dev_flow_ops_get,
6873         .vlan_filter_set        = hns3_vlan_filter_set,
6874         .vlan_tpid_set          = hns3_vlan_tpid_set,
6875         .vlan_offload_set       = hns3_vlan_offload_set,
6876         .vlan_pvid_set          = hns3_vlan_pvid_set,
6877         .get_reg                = hns3_get_regs,
6878         .get_module_info        = hns3_get_module_info,
6879         .get_module_eeprom      = hns3_get_module_eeprom,
6880         .get_dcb_info           = hns3_get_dcb_info,
6881         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6882         .fec_get_capability     = hns3_fec_get_capability,
6883         .fec_get                = hns3_fec_get,
6884         .fec_set                = hns3_fec_set,
6885         .tm_ops_get             = hns3_tm_ops_get,
6886         .tx_done_cleanup        = hns3_tx_done_cleanup,
6887         .timesync_enable            = hns3_timesync_enable,
6888         .timesync_disable           = hns3_timesync_disable,
6889         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6890         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6891         .timesync_adjust_time       = hns3_timesync_adjust_time,
6892         .timesync_read_time         = hns3_timesync_read_time,
6893         .timesync_write_time        = hns3_timesync_write_time,
6894 };
6895
6896 static const struct hns3_reset_ops hns3_reset_ops = {
6897         .reset_service       = hns3_reset_service,
6898         .stop_service        = hns3_stop_service,
6899         .prepare_reset       = hns3_prepare_reset,
6900         .wait_hardware_ready = hns3_wait_hardware_ready,
6901         .reinit_dev          = hns3_reinit_dev,
6902         .restore_conf        = hns3_restore_conf,
6903         .start_service       = hns3_start_service,
6904 };
6905
6906 static int
6907 hns3_dev_init(struct rte_eth_dev *eth_dev)
6908 {
6909         struct hns3_adapter *hns = eth_dev->data->dev_private;
6910         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6911         struct rte_ether_addr *eth_addr;
6912         struct hns3_hw *hw = &hns->hw;
6913         int ret;
6914
6915         PMD_INIT_FUNC_TRACE();
6916
6917         eth_dev->process_private = (struct hns3_process_private *)
6918             rte_zmalloc_socket("hns3_filter_list",
6919                                sizeof(struct hns3_process_private),
6920                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6921         if (eth_dev->process_private == NULL) {
6922                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6923                 return -ENOMEM;
6924         }
6925         /* initialize flow filter lists */
6926         hns3_filterlist_init(eth_dev);
6927
6928         hns3_set_rxtx_function(eth_dev);
6929         eth_dev->dev_ops = &hns3_eth_dev_ops;
6930         eth_dev->rx_queue_count = hns3_rx_queue_count;
6931         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6932                 ret = hns3_mp_init_secondary();
6933                 if (ret) {
6934                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6935                                      "process, ret = %d", ret);
6936                         goto err_mp_init_secondary;
6937                 }
6938
6939                 hw->secondary_cnt++;
6940                 return 0;
6941         }
6942
6943         ret = hns3_mp_init_primary();
6944         if (ret) {
6945                 PMD_INIT_LOG(ERR,
6946                              "Failed to init for primary process, ret = %d",
6947                              ret);
6948                 goto err_mp_init_primary;
6949         }
6950
6951         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6952         hns->is_vf = false;
6953         hw->data = eth_dev->data;
6954         hns3_parse_devargs(eth_dev);
6955
6956         /*
6957          * Set default max packet size according to the mtu
6958          * default vale in DPDK frame.
6959          */
6960         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6961
6962         ret = hns3_reset_init(hw);
6963         if (ret)
6964                 goto err_init_reset;
6965         hw->reset.ops = &hns3_reset_ops;
6966
6967         ret = hns3_init_pf(eth_dev);
6968         if (ret) {
6969                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6970                 goto err_init_pf;
6971         }
6972
6973         /* Allocate memory for storing MAC addresses */
6974         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6975                                                sizeof(struct rte_ether_addr) *
6976                                                HNS3_UC_MACADDR_NUM, 0);
6977         if (eth_dev->data->mac_addrs == NULL) {
6978                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6979                              "to store MAC addresses",
6980                              sizeof(struct rte_ether_addr) *
6981                              HNS3_UC_MACADDR_NUM);
6982                 ret = -ENOMEM;
6983                 goto err_rte_zmalloc;
6984         }
6985
6986         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6987         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6988                 rte_eth_random_addr(hw->mac.mac_addr);
6989                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6990                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6991                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6992                           "unicast address, using random MAC address %s",
6993                           mac_str);
6994         }
6995         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6996                             &eth_dev->data->mac_addrs[0]);
6997
6998         hw->adapter_state = HNS3_NIC_INITIALIZED;
6999
7000         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7001                             SCHEDULE_PENDING) {
7002                 hns3_err(hw, "Reschedule reset service after dev_init");
7003                 hns3_schedule_reset(hns);
7004         } else {
7005                 /* IMP will wait ready flag before reset */
7006                 hns3_notify_reset_ready(hw, false);
7007         }
7008
7009         hns3_info(hw, "hns3 dev initialization successful!");
7010         return 0;
7011
7012 err_rte_zmalloc:
7013         hns3_uninit_pf(eth_dev);
7014
7015 err_init_pf:
7016         rte_free(hw->reset.wait_data);
7017
7018 err_init_reset:
7019         hns3_mp_uninit_primary();
7020
7021 err_mp_init_primary:
7022 err_mp_init_secondary:
7023         eth_dev->dev_ops = NULL;
7024         eth_dev->rx_pkt_burst = NULL;
7025         eth_dev->rx_descriptor_status = NULL;
7026         eth_dev->tx_pkt_burst = NULL;
7027         eth_dev->tx_pkt_prepare = NULL;
7028         eth_dev->tx_descriptor_status = NULL;
7029         rte_free(eth_dev->process_private);
7030         eth_dev->process_private = NULL;
7031         return ret;
7032 }
7033
7034 static int
7035 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7036 {
7037         struct hns3_adapter *hns = eth_dev->data->dev_private;
7038         struct hns3_hw *hw = &hns->hw;
7039
7040         PMD_INIT_FUNC_TRACE();
7041
7042         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7043                 rte_free(eth_dev->process_private);
7044                 eth_dev->process_private = NULL;
7045                 return 0;
7046         }
7047
7048         if (hw->adapter_state < HNS3_NIC_CLOSING)
7049                 hns3_dev_close(eth_dev);
7050
7051         hw->adapter_state = HNS3_NIC_REMOVED;
7052         return 0;
7053 }
7054
7055 static int
7056 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7057                    struct rte_pci_device *pci_dev)
7058 {
7059         return rte_eth_dev_pci_generic_probe(pci_dev,
7060                                              sizeof(struct hns3_adapter),
7061                                              hns3_dev_init);
7062 }
7063
7064 static int
7065 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7066 {
7067         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7068 }
7069
7070 static const struct rte_pci_id pci_id_hns3_map[] = {
7071         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7072         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7073         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7074         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7075         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7076         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7077         { .vendor_id = 0, }, /* sentinel */
7078 };
7079
7080 static struct rte_pci_driver rte_hns3_pmd = {
7081         .id_table = pci_id_hns3_map,
7082         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7083         .probe = eth_hns3_pci_probe,
7084         .remove = eth_hns3_pci_remove,
7085 };
7086
7087 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7088 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7089 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7090 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7091                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7092                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
7093 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7094 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);