drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVLID_PVID                0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59
  60 #define HNS3_RESET_WAIT_MS      100
  61 #define HNS3_RESET_WAIT_CNT     200
  62
  63 enum hns3_evt_cause {
  64         HNS3_VECTOR0_EVENT_RST,
  65         HNS3_VECTOR0_EVENT_MBX,
  66         HNS3_VECTOR0_EVENT_ERR,
  67         HNS3_VECTOR0_EVENT_OTHER,
  68 };
  69
  70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  71                                                  uint64_t *levels);
  72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  74                                     int on);
  75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  76
  77 static int hns3_add_mc_addr(struct hns3_hw *hw,
  78                             struct rte_ether_addr *mac_addr);
  79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  80                             struct rte_ether_addr *mac_addr);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_hw *hw = &hns->hw;
 312         struct hns3_pf *pf = &hns->pf;
 313         uint16_t vlan_id;
 314         int ret = 0;
 315
 316         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 317                 return hns3_vlan_pvid_configure(hns,
 318                                                 hw->port_base_vlan_cfg.pvid, 1);
 319
 320         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 321                 if (vlan_entry->hd_tbl_status) {
 322                         vlan_id = vlan_entry->vlan_id;
 323                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 324                         if (ret)
 325                                 break;
 326                 }
 327         }
 328
 329         return ret;
 330 }
 331
 332 static int
 333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 334 {
 335         struct hns3_hw *hw = &hns->hw;
 336         bool writen_to_tbl = false;
 337         int ret = 0;
 338
 339         /*
 340          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 341          * for normal packet, deleting vlan id 0 is not allowed.
 342          */
 343         if (on == 0 && vlan_id == 0)
 344                 return 0;
 345
 346         /*
 347          * When port base vlan enabled, we use port base vlan as the vlan
 348          * filter condition. In this case, we don't update vlan filter table
 349          * when user add new vlan or remove exist vlan, just update the
 350          * vlan list. The vlan id in vlan list will be writen in vlan filter
 351          * table until port base vlan disabled
 352          */
 353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 354                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 355                 writen_to_tbl = true;
 356         }
 357
 358         if (ret == 0 && vlan_id) {
 359                 if (on)
 360                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 361                 else
 362                         hns3_rm_dev_vlan_table(hns, vlan_id);
 363         }
 364         return ret;
 365 }
 366
 367 static int
 368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 369 {
 370         struct hns3_adapter *hns = dev->data->dev_private;
 371         struct hns3_hw *hw = &hns->hw;
 372         int ret;
 373
 374         rte_spinlock_lock(&hw->lock);
 375         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 376         rte_spinlock_unlock(&hw->lock);
 377         return ret;
 378 }
 379
 380 static int
 381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 382                          uint16_t tpid)
 383 {
 384         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 385         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 386         struct hns3_hw *hw = &hns->hw;
 387         struct hns3_cmd_desc desc;
 388         int ret;
 389
 390         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 391              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 392                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 393                 return -EINVAL;
 394         }
 395
 396         if (tpid != RTE_ETHER_TYPE_VLAN) {
 397                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 398                 return -EINVAL;
 399         }
 400
 401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 402         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 403
 404         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 405                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 406                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 407         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 408                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 412         }
 413
 414         ret = hns3_cmd_send(hw, &desc, 1);
 415         if (ret) {
 416                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 417                          ret);
 418                 return ret;
 419         }
 420
 421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 422
 423         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 424         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 425         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 426
 427         ret = hns3_cmd_send(hw, &desc, 1);
 428         if (ret)
 429                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 430                          ret);
 431         return ret;
 432 }
 433
 434 static int
 435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 436                    uint16_t tpid)
 437 {
 438         struct hns3_adapter *hns = dev->data->dev_private;
 439         struct hns3_hw *hw = &hns->hw;
 440         int ret;
 441
 442         rte_spinlock_lock(&hw->lock);
 443         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 444         rte_spinlock_unlock(&hw->lock);
 445         return ret;
 446 }
 447
 448 static int
 449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 450                              struct hns3_rx_vtag_cfg *vcfg)
 451 {
 452         struct hns3_vport_vtag_rx_cfg_cmd *req;
 453         struct hns3_hw *hw = &hns->hw;
 454         struct hns3_cmd_desc desc;
 455         uint16_t vport_id;
 456         uint8_t bitmap;
 457         int ret;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 460
 461         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 462         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 463                      vcfg->strip_tag1_en ? 1 : 0);
 464         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 465                      vcfg->strip_tag2_en ? 1 : 0);
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 467                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 469                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 470
 471         /*
 472          * In current version VF is not supported when PF is driven by DPDK
 473          * driver, just need to configure parameters for PF vport.
 474          */
 475         vport_id = HNS3_PF_FUNC_ID;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_hw *hw = &hns->hw;
 507         int ret;
 508
 509         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 510                 rxvlan_cfg.strip_tag1_en = false;
 511                 rxvlan_cfg.strip_tag2_en = enable;
 512         } else {
 513                 rxvlan_cfg.strip_tag1_en = enable;
 514                 rxvlan_cfg.strip_tag2_en = true;
 515         }
 516
 517         rxvlan_cfg.vlan1_vlan_prionly = false;
 518         rxvlan_cfg.vlan2_vlan_prionly = false;
 519         rxvlan_cfg.rx_vlan_offload_en = enable;
 520
 521         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 522         if (ret) {
 523                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 524                 return ret;
 525         }
 526
 527         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 534                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 535 {
 536         struct hns3_vlan_filter_ctrl_cmd *req;
 537         struct hns3_cmd_desc desc;
 538         int ret;
 539
 540         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 541
 542         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 543         req->vlan_type = vlan_type;
 544         req->vlan_fe = filter_en ? fe_type : 0;
 545         req->vf_id = vf_id;
 546
 547         ret = hns3_cmd_send(hw, &desc, 1);
 548         if (ret)
 549                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 550
 551         return ret;
 552 }
 553
 554 static int
 555 hns3_vlan_filter_init(struct hns3_adapter *hns)
 556 {
 557         struct hns3_hw *hw = &hns->hw;
 558         int ret;
 559
 560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 561                                         HNS3_FILTER_FE_EGRESS, false,
 562                                         HNS3_PF_FUNC_ID);
 563         if (ret) {
 564                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, false,
 570                                         HNS3_PF_FUNC_ID);
 571         if (ret)
 572                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 573
 574         return ret;
 575 }
 576
 577 static int
 578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 579 {
 580         struct hns3_hw *hw = &hns->hw;
 581         int ret;
 582
 583         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 584                                         HNS3_FILTER_FE_INGRESS, enable,
 585                                         HNS3_PF_FUNC_ID);
 586         if (ret)
 587                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 588                          enable ? "enable" : "disable", ret);
 589
 590         return ret;
 591 }
 592
 593 static int
 594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 595 {
 596         struct hns3_adapter *hns = dev->data->dev_private;
 597         struct hns3_hw *hw = &hns->hw;
 598         struct rte_eth_rxmode *rxmode;
 599         unsigned int tmp_mask;
 600         bool enable;
 601         int ret = 0;
 602
 603         rte_spinlock_lock(&hw->lock);
 604         rxmode = &dev->data->dev_conf.rxmode;
 605         tmp_mask = (unsigned int)mask;
 606         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 607                 /* ignore vlan filter configuration during promiscuous mode */
 608                 if (!dev->data->promiscuous) {
 609                         /* Enable or disable VLAN filter */
 610                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 611                                  true : false;
 612
 613                         ret = hns3_enable_vlan_filter(hns, enable);
 614                         if (ret) {
 615                                 rte_spinlock_unlock(&hw->lock);
 616                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 617                                          enable ? "enable" : "disable", ret);
 618                                 return ret;
 619                         }
 620                 }
 621         }
 622
 623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 624                 /* Enable or disable VLAN stripping */
 625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 626                     true : false;
 627
 628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 629                 if (ret) {
 630                         rte_spinlock_unlock(&hw->lock);
 631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 632                                  enable ? "enable" : "disable", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         rte_spinlock_unlock(&hw->lock);
 638
 639         return ret;
 640 }
 641
 642 static int
 643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 644                              struct hns3_tx_vtag_cfg *vcfg)
 645 {
 646         struct hns3_vport_vtag_tx_cfg_cmd *req;
 647         struct hns3_cmd_desc desc;
 648         struct hns3_hw *hw = &hns->hw;
 649         uint16_t vport_id;
 650         uint8_t bitmap;
 651         int ret;
 652
 653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 654
 655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 656         req->def_vlan_tag1 = vcfg->default_tag1;
 657         req->def_vlan_tag2 = vcfg->default_tag2;
 658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 659                      vcfg->accept_tag1 ? 1 : 0);
 660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 661                      vcfg->accept_untag1 ? 1 : 0);
 662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 663                      vcfg->accept_tag2 ? 1 : 0);
 664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 665                      vcfg->accept_untag2 ? 1 : 0);
 666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 667                      vcfg->insert_tag1_en ? 1 : 0);
 668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 669                      vcfg->insert_tag2_en ? 1 : 0);
 670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 671
 672         /*
 673          * In current version VF is not supported when PF is driven by DPDK
 674          * driver, just need to configure parameters for PF vport.
 675          */
 676         vport_id = HNS3_PF_FUNC_ID;
 677         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 678         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 679         req->vf_bitmap[req->vf_offset] = bitmap;
 680
 681         ret = hns3_cmd_send(hw, &desc, 1);
 682         if (ret)
 683                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 684
 685         return ret;
 686 }
 687
 688 static int
 689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 690                      uint16_t pvid)
 691 {
 692         struct hns3_hw *hw = &hns->hw;
 693         struct hns3_tx_vtag_cfg txvlan_cfg;
 694         int ret;
 695
 696         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 697                 txvlan_cfg.accept_tag1 = true;
 698                 txvlan_cfg.insert_tag1_en = false;
 699                 txvlan_cfg.default_tag1 = 0;
 700         } else {
 701                 txvlan_cfg.accept_tag1 = false;
 702                 txvlan_cfg.insert_tag1_en = true;
 703                 txvlan_cfg.default_tag1 = pvid;
 704         }
 705
 706         txvlan_cfg.accept_untag1 = true;
 707         txvlan_cfg.accept_tag2 = true;
 708         txvlan_cfg.accept_untag2 = true;
 709         txvlan_cfg.insert_tag2_en = false;
 710         txvlan_cfg.default_tag2 = 0;
 711
 712         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 713         if (ret) {
 714                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 715                          ret);
 716                 return ret;
 717         }
 718
 719         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 720         return ret;
 721 }
 722
 723 static void
 724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 725 {
 726         struct hns3_hw *hw = &hns->hw;
 727
 728         hw->port_base_vlan_cfg.state = on ?
 729             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 730
 731         hw->port_base_vlan_cfg.pvid = pvid;
 732 }
 733
 734 static void
 735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 736 {
 737         struct hns3_user_vlan_table *vlan_entry;
 738         struct hns3_pf *pf = &hns->pf;
 739
 740         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 741                 if (vlan_entry->hd_tbl_status)
 742                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 743
 744                 vlan_entry->hd_tbl_status = false;
 745         }
 746
 747         if (is_del_list) {
 748                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 749                 while (vlan_entry) {
 750                         LIST_REMOVE(vlan_entry, next);
 751                         rte_free(vlan_entry);
 752                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 }
 754         }
 755 }
 756
 757 static void
 758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 759 {
 760         struct hns3_user_vlan_table *vlan_entry;
 761         struct hns3_pf *pf = &hns->pf;
 762
 763         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 764                 if (!vlan_entry->hd_tbl_status)
 765                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 766
 767                 vlan_entry->hd_tbl_status = true;
 768         }
 769 }
 770
 771 static void
 772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_hw *hw = &hns->hw;
 775         int ret;
 776
 777         hns3_rm_all_vlan_table(hns, true);
 778         if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 779                 ret = hns3_set_port_vlan_filter(hns,
 780                                                 hw->port_base_vlan_cfg.pvid, 0);
 781                 if (ret) {
 782                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 783                                  ret);
 784                         return;
 785                 }
 786         }
 787 }
 788
 789 static int
 790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 791                                 uint16_t port_base_vlan_state,
 792                                 uint16_t new_pvid, uint16_t old_pvid)
 793 {
 794         struct hns3_hw *hw = &hns->hw;
 795         int ret = 0;
 796
 797         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 798                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 799                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 800                         if (ret) {
 801                                 hns3_err(hw,
 802                                          "Failed to clear clear old pvid filter, ret =%d",
 803                                          ret);
 804                                 return ret;
 805                         }
 806                 }
 807
 808                 hns3_rm_all_vlan_table(hns, false);
 809                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 810         }
 811
 812         if (new_pvid != 0) {
 813                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 814                 if (ret) {
 815                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 816                                  ret);
 817                         return ret;
 818                 }
 819         }
 820
 821         if (new_pvid == hw->port_base_vlan_cfg.pvid)
 822                 hns3_add_all_vlan_table(hns);
 823
 824         return ret;
 825 }
 826
 827 static int
 828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 829 {
 830         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 831         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 832         bool rx_strip_en;
 833         int ret;
 834
 835         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
 836         if (on) {
 837                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 838                 rx_vlan_cfg.strip_tag2_en = true;
 839         } else {
 840                 rx_vlan_cfg.strip_tag1_en = false;
 841                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 842         }
 843         rx_vlan_cfg.vlan1_vlan_prionly = false;
 844         rx_vlan_cfg.vlan2_vlan_prionly = false;
 845         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 846
 847         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 848         if (ret)
 849                 return ret;
 850
 851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 852         return ret;
 853 }
 854
 855 static int
 856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 857 {
 858         struct hns3_hw *hw = &hns->hw;
 859         uint16_t port_base_vlan_state;
 860         uint16_t old_pvid;
 861         int ret;
 862
 863         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 864                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 865                         hns3_warn(hw, "Invalid operation! As current pvid set "
 866                                   "is %u, disable pvid %u is invalid",
 867                                   hw->port_base_vlan_cfg.pvid, pvid);
 868                 return 0;
 869         }
 870
 871         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 872                                     HNS3_PORT_BASE_VLAN_DISABLE;
 873         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 874         if (ret) {
 875                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 876                          ret);
 877                 return ret;
 878         }
 879
 880         ret = hns3_en_pvid_strip(hns, on);
 881         if (ret) {
 882                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 883                          "ret = %d", ret);
 884                 return ret;
 885         }
 886
 887         if (pvid == HNS3_INVLID_PVID)
 888                 goto out;
 889         old_pvid = hw->port_base_vlan_cfg.pvid;
 890         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 891                                               old_pvid);
 892         if (ret) {
 893                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 894                          ret);
 895                 return ret;
 896         }
 897
 898 out:
 899         hns3_store_port_base_vlan_info(hns, pvid, on);
 900         return ret;
 901 }
 902
 903 static int
 904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 905 {
 906         struct hns3_adapter *hns = dev->data->dev_private;
 907         struct hns3_hw *hw = &hns->hw;
 908         bool pvid_en_state_change;
 909         uint16_t pvid_state;
 910         int ret;
 911
 912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 914                          RTE_ETHER_MAX_VLAN_ID);
 915                 return -EINVAL;
 916         }
 917
 918         /*
 919          * If PVID configuration state change, should refresh the PVID
 920          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 921          */
 922         pvid_state = hw->port_base_vlan_cfg.state;
 923         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 924             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 925                 pvid_en_state_change = false;
 926         else
 927                 pvid_en_state_change = true;
 928
 929         rte_spinlock_lock(&hw->lock);
 930         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 931         rte_spinlock_unlock(&hw->lock);
 932         if (ret)
 933                 return ret;
 934
 935         if (pvid_en_state_change)
 936                 hns3_update_all_queues_pvid_state(hw);
 937
 938         return 0;
 939 }
 940
 941 static void
 942 init_port_base_vlan_info(struct hns3_hw *hw)
 943 {
 944         hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 945         hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 946 }
 947
 948 static int
 949 hns3_default_vlan_config(struct hns3_adapter *hns)
 950 {
 951         struct hns3_hw *hw = &hns->hw;
 952         int ret;
 953
 954         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 955         if (ret)
 956                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 957         return ret;
 958 }
 959
 960 static int
 961 hns3_init_vlan_config(struct hns3_adapter *hns)
 962 {
 963         struct hns3_hw *hw = &hns->hw;
 964         int ret;
 965
 966         /*
 967          * This function can be called in the initialization and reset process,
 968          * when in reset process, it means that hardware had been reseted
 969          * successfully and we need to restore the hardware configuration to
 970          * ensure that the hardware configuration remains unchanged before and
 971          * after reset.
 972          */
 973         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 974                 init_port_base_vlan_info(hw);
 975
 976         ret = hns3_vlan_filter_init(hns);
 977         if (ret) {
 978                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 979                 return ret;
 980         }
 981
 982         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 983                                        RTE_ETHER_TYPE_VLAN);
 984         if (ret) {
 985                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 986                 return ret;
 987         }
 988
 989         /*
 990          * When in the reinit dev stage of the reset process, the following
 991          * vlan-related configurations may differ from those at initialization,
 992          * we will restore configurations to hardware in hns3_restore_vlan_table
 993          * and hns3_restore_vlan_conf later.
 994          */
 995         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 996                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 997                 if (ret) {
 998                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 999                         return ret;
1000                 }
1001
1002                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1003                 if (ret) {
1004                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1005                                  ret);
1006                         return ret;
1007                 }
1008         }
1009
1010         return hns3_default_vlan_config(hns);
1011 }
1012
1013 static int
1014 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1015 {
1016         struct hns3_pf *pf = &hns->pf;
1017         struct hns3_hw *hw = &hns->hw;
1018         uint64_t offloads;
1019         bool enable;
1020         int ret;
1021
1022         if (!hw->data->promiscuous) {
1023                 /* restore vlan filter states */
1024                 offloads = hw->data->dev_conf.rxmode.offloads;
1025                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1026                 ret = hns3_enable_vlan_filter(hns, enable);
1027                 if (ret) {
1028                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1029                                  "ret = %d", ret);
1030                         return ret;
1031                 }
1032         }
1033
1034         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1035         if (ret) {
1036                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1037                 return ret;
1038         }
1039
1040         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1041         if (ret)
1042                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1043
1044         return ret;
1045 }
1046
1047 static int
1048 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1049 {
1050         struct hns3_adapter *hns = dev->data->dev_private;
1051         struct rte_eth_dev_data *data = dev->data;
1052         struct rte_eth_txmode *txmode;
1053         struct hns3_hw *hw = &hns->hw;
1054         int mask;
1055         int ret;
1056
1057         txmode = &data->dev_conf.txmode;
1058         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1059                 hns3_warn(hw,
1060                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1061                           "configuration is not supported! Ignore these two "
1062                           "parameters: hw_vlan_reject_tagged(%d), "
1063                           "hw_vlan_reject_untagged(%d)",
1064                           txmode->hw_vlan_reject_tagged,
1065                           txmode->hw_vlan_reject_untagged);
1066
1067         /* Apply vlan offload setting */
1068         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1069         ret = hns3_vlan_offload_set(dev, mask);
1070         if (ret) {
1071                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1072                          ret);
1073                 return ret;
1074         }
1075
1076         /*
1077          * If pvid config is not set in rte_eth_conf, driver needn't to set
1078          * VLAN pvid related configuration to hardware.
1079          */
1080         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1081                 return 0;
1082
1083         /* Apply pvid setting */
1084         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1085                                  txmode->hw_vlan_insert_pvid);
1086         if (ret)
1087                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1088                          txmode->pvid, ret);
1089
1090         return ret;
1091 }
1092
1093 static int
1094 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1095                 unsigned int tso_mss_max)
1096 {
1097         struct hns3_cfg_tso_status_cmd *req;
1098         struct hns3_cmd_desc desc;
1099         uint16_t tso_mss;
1100
1101         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1102
1103         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1104
1105         tso_mss = 0;
1106         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1107                        tso_mss_min);
1108         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1109
1110         tso_mss = 0;
1111         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1112                        tso_mss_max);
1113         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1114
1115         return hns3_cmd_send(hw, &desc, 1);
1116 }
1117
1118 static int
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120                    uint16_t *allocated_size, bool is_alloc)
1121 {
1122         struct hns3_umv_spc_alc_cmd *req;
1123         struct hns3_cmd_desc desc;
1124         int ret;
1125
1126         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129         req->space_size = rte_cpu_to_le_32(space_size);
1130
1131         ret = hns3_cmd_send(hw, &desc, 1);
1132         if (ret) {
1133                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134                              is_alloc ? "allocate" : "free", ret);
1135                 return ret;
1136         }
1137
1138         if (is_alloc && allocated_size)
1139                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1140
1141         return 0;
1142 }
1143
1144 static int
1145 hns3_init_umv_space(struct hns3_hw *hw)
1146 {
1147         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148         struct hns3_pf *pf = &hns->pf;
1149         uint16_t allocated_size = 0;
1150         int ret;
1151
1152         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1153                                  true);
1154         if (ret)
1155                 return ret;
1156
1157         if (allocated_size < pf->wanted_umv_size)
1158                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159                              pf->wanted_umv_size, allocated_size);
1160
1161         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162                                                 pf->wanted_umv_size;
1163         pf->used_umv_size = 0;
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         int ret;
1173
1174         if (pf->max_umv_size == 0)
1175                 return 0;
1176
1177         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1178         if (ret)
1179                 return ret;
1180
1181         pf->max_umv_size = 0;
1182
1183         return 0;
1184 }
1185
1186 static bool
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1188 {
1189         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190         struct hns3_pf *pf = &hns->pf;
1191         bool is_full;
1192
1193         is_full = (pf->used_umv_size >= pf->max_umv_size);
1194
1195         return is_full;
1196 }
1197
1198 static void
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1200 {
1201         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202         struct hns3_pf *pf = &hns->pf;
1203
1204         if (is_free) {
1205                 if (pf->used_umv_size > 0)
1206                         pf->used_umv_size--;
1207         } else
1208                 pf->used_umv_size++;
1209 }
1210
1211 static void
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213                       const uint8_t *addr, bool is_mc)
1214 {
1215         const unsigned char *mac_addr = addr;
1216         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217                             ((uint32_t)mac_addr[2] << 16) |
1218                             ((uint32_t)mac_addr[1] << 8) |
1219                             (uint32_t)mac_addr[0];
1220         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1221
1222         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1223         if (is_mc) {
1224                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1227         }
1228
1229         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1231 }
1232
1233 static int
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1235                              uint8_t resp_code,
1236                              enum hns3_mac_vlan_tbl_opcode op)
1237 {
1238         if (cmdq_resp) {
1239                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1240                          cmdq_resp);
1241                 return -EIO;
1242         }
1243
1244         if (op == HNS3_MAC_VLAN_ADD) {
1245                 if (resp_code == 0 || resp_code == 1) {
1246                         return 0;
1247                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248                         hns3_err(hw, "add mac addr failed for uc_overflow");
1249                         return -ENOSPC;
1250                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251                         hns3_err(hw, "add mac addr failed for mc_overflow");
1252                         return -ENOSPC;
1253                 }
1254
1255                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1256                          resp_code);
1257                 return -EIO;
1258         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259                 if (resp_code == 0) {
1260                         return 0;
1261                 } else if (resp_code == 1) {
1262                         hns3_dbg(hw, "remove mac addr failed for miss");
1263                         return -ENOENT;
1264                 }
1265
1266                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1267                          resp_code);
1268                 return -EIO;
1269         } else if (op == HNS3_MAC_VLAN_LKUP) {
1270                 if (resp_code == 0) {
1271                         return 0;
1272                 } else if (resp_code == 1) {
1273                         hns3_dbg(hw, "lookup mac addr failed for miss");
1274                         return -ENOENT;
1275                 }
1276
1277                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1278                          resp_code);
1279                 return -EIO;
1280         }
1281
1282         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1283                  op);
1284
1285         return -EINVAL;
1286 }
1287
1288 static int
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1291                          struct hns3_cmd_desc *desc, bool is_mc)
1292 {
1293         uint8_t resp_code;
1294         uint16_t retval;
1295         int ret;
1296
1297         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1298         if (is_mc) {
1299                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300                 memcpy(desc[0].data, req,
1301                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1303                                           true);
1304                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1306                                           true);
1307                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1308         } else {
1309                 memcpy(desc[0].data, req,
1310                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311                 ret = hns3_cmd_send(hw, desc, 1);
1312         }
1313         if (ret) {
1314                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1315                          ret);
1316                 return ret;
1317         }
1318         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319         retval = rte_le_to_cpu_16(desc[0].retval);
1320
1321         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322                                             HNS3_MAC_VLAN_LKUP);
1323 }
1324
1325 static int
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1328                       struct hns3_cmd_desc *mc_desc)
1329 {
1330         uint8_t resp_code;
1331         uint16_t retval;
1332         int cfg_status;
1333         int ret;
1334
1335         if (mc_desc == NULL) {
1336                 struct hns3_cmd_desc desc;
1337
1338                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339                 memcpy(desc.data, req,
1340                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341                 ret = hns3_cmd_send(hw, &desc, 1);
1342                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343                 retval = rte_le_to_cpu_16(desc.retval);
1344
1345                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1346                                                           HNS3_MAC_VLAN_ADD);
1347         } else {
1348                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354                 memcpy(mc_desc[0].data, req,
1355                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356                 mc_desc[0].retval = 0;
1357                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1360
1361                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1362                                                           HNS3_MAC_VLAN_ADD);
1363         }
1364
1365         if (ret) {
1366                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1367                 return ret;
1368         }
1369
1370         return cfg_status;
1371 }
1372
1373 static int
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1376 {
1377         struct hns3_cmd_desc desc;
1378         uint8_t resp_code;
1379         uint16_t retval;
1380         int ret;
1381
1382         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1383
1384         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1385
1386         ret = hns3_cmd_send(hw, &desc, 1);
1387         if (ret) {
1388                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1389                 return ret;
1390         }
1391         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392         retval = rte_le_to_cpu_16(desc.retval);
1393
1394         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395                                             HNS3_MAC_VLAN_REMOVE);
1396 }
1397
1398 static int
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1400 {
1401         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402         struct hns3_mac_vlan_tbl_entry_cmd req;
1403         struct hns3_pf *pf = &hns->pf;
1404         struct hns3_cmd_desc desc;
1405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406         uint16_t egress_port = 0;
1407         uint8_t vf_id;
1408         int ret;
1409
1410         /* check if mac addr is valid */
1411         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1413                                       mac_addr);
1414                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1415                          mac_str);
1416                 return -EINVAL;
1417         }
1418
1419         memset(&req, 0, sizeof(req));
1420
1421         /*
1422          * In current version VF is not supported when PF is driven by DPDK
1423          * driver, just need to configure parameters for PF vport.
1424          */
1425         vf_id = HNS3_PF_FUNC_ID;
1426         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427                        HNS3_MAC_EPORT_VFID_S, vf_id);
1428
1429         req.egress_port = rte_cpu_to_le_16(egress_port);
1430
1431         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1432
1433         /*
1434          * Lookup the mac address in the mac_vlan table, and add
1435          * it if the entry is inexistent. Repeated unicast entry
1436          * is not allowed in the mac vlan table.
1437          */
1438         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439         if (ret == -ENOENT) {
1440                 if (!hns3_is_umv_space_full(hw)) {
1441                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1442                         if (!ret)
1443                                 hns3_update_umv_space(hw, false);
1444                         return ret;
1445                 }
1446
1447                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1448
1449                 return -ENOSPC;
1450         }
1451
1452         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1453
1454         /* check if we just hit the duplicate */
1455         if (ret == 0) {
1456                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1457                 return 0;
1458         }
1459
1460         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1461                  mac_str);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1468 {
1469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470         struct rte_ether_addr *addr;
1471         int ret;
1472         int i;
1473
1474         for (i = 0; i < hw->mc_addrs_num; i++) {
1475                 addr = &hw->mc_addrs[i];
1476                 /* Check if there are duplicate addresses */
1477                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1479                                               addr);
1480                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1481                                  "(%s) is added by the set_mc_mac_addr_list "
1482                                  "API", mac_str);
1483                         return -EINVAL;
1484                 }
1485         }
1486
1487         ret = hns3_add_mc_addr(hw, mac_addr);
1488         if (ret) {
1489                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1490                                       mac_addr);
1491                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1492                          mac_str, ret);
1493         }
1494         return ret;
1495 }
1496
1497 static int
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1499 {
1500         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1501         int ret;
1502
1503         ret = hns3_remove_mc_addr(hw, mac_addr);
1504         if (ret) {
1505                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1506                                       mac_addr);
1507                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1508                          mac_str, ret);
1509         }
1510         return ret;
1511 }
1512
1513 static int
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515                   uint32_t idx, __rte_unused uint32_t pool)
1516 {
1517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1519         int ret;
1520
1521         rte_spinlock_lock(&hw->lock);
1522
1523         /*
1524          * In hns3 network engine adding UC and MC mac address with different
1525          * commands with firmware. We need to determine whether the input
1526          * address is a UC or a MC address to call different commands.
1527          * By the way, it is recommended calling the API function named
1528          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530          * may affect the specifications of UC mac addresses.
1531          */
1532         if (rte_is_multicast_ether_addr(mac_addr))
1533                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1534         else
1535                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1536
1537         if (ret) {
1538                 rte_spinlock_unlock(&hw->lock);
1539                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540                                       mac_addr);
1541                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1542                          ret);
1543                 return ret;
1544         }
1545
1546         if (idx == 0)
1547                 hw->mac.default_addr_setted = true;
1548         rte_spinlock_unlock(&hw->lock);
1549
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1555 {
1556         struct hns3_mac_vlan_tbl_entry_cmd req;
1557         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1558         int ret;
1559
1560         /* check if mac addr is valid */
1561         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1563                                       mac_addr);
1564                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1565                          mac_str);
1566                 return -EINVAL;
1567         }
1568
1569         memset(&req, 0, sizeof(req));
1570         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1574                 return 0;
1575         else if (ret == 0)
1576                 hns3_update_umv_space(hw, true);
1577
1578         return ret;
1579 }
1580
1581 static void
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1583 {
1584         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         /* index will be checked by upper level rte interface */
1586         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         if (rte_is_multicast_ether_addr(mac_addr))
1593                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1594         else
1595                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596         rte_spinlock_unlock(&hw->lock);
1597         if (ret) {
1598                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                       mac_addr);
1600                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1601                          ret);
1602         }
1603 }
1604
1605 static int
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607                           struct rte_ether_addr *mac_addr)
1608 {
1609         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct rte_ether_addr *oaddr;
1611         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612         bool default_addr_setted;
1613         bool rm_succes = false;
1614         int ret, ret_val;
1615
1616         /*
1617          * It has been guaranteed that input parameter named mac_addr is valid
1618          * address in the rte layer of DPDK framework.
1619          */
1620         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621         default_addr_setted = hw->mac.default_addr_setted;
1622         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1623                 return 0;
1624
1625         rte_spinlock_lock(&hw->lock);
1626         if (default_addr_setted) {
1627                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1628                 if (ret) {
1629                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                               oaddr);
1631                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1632                                   mac_str, ret);
1633                         rm_succes = false;
1634                 } else
1635                         rm_succes = true;
1636         }
1637
1638         ret = hns3_add_uc_addr_common(hw, mac_addr);
1639         if (ret) {
1640                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1641                                       mac_addr);
1642                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643                 goto err_add_uc_addr;
1644         }
1645
1646         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1647         if (ret) {
1648                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649                 goto err_pause_addr_cfg;
1650         }
1651
1652         rte_ether_addr_copy(mac_addr,
1653                             (struct rte_ether_addr *)hw->mac.mac_addr);
1654         hw->mac.default_addr_setted = true;
1655         rte_spinlock_unlock(&hw->lock);
1656
1657         return 0;
1658
1659 err_pause_addr_cfg:
1660         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1661         if (ret_val) {
1662                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663                                       mac_addr);
1664                 hns3_warn(hw,
1665                           "Failed to roll back to del setted mac addr(%s): %d",
1666                           mac_str, ret_val);
1667         }
1668
1669 err_add_uc_addr:
1670         if (rm_succes) {
1671                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1672                 if (ret_val) {
1673                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1674                                               oaddr);
1675                         hns3_warn(hw,
1676                                   "Failed to restore old uc mac addr(%s): %d",
1677                                   mac_str, ret_val);
1678                         hw->mac.default_addr_setted = false;
1679                 }
1680         }
1681         rte_spinlock_unlock(&hw->lock);
1682
1683         return ret;
1684 }
1685
1686 static int
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1688 {
1689         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690         struct hns3_hw *hw = &hns->hw;
1691         struct rte_ether_addr *addr;
1692         int err = 0;
1693         int ret;
1694         int i;
1695
1696         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697                 addr = &hw->data->mac_addrs[i];
1698                 if (rte_is_zero_ether_addr(addr))
1699                         continue;
1700                 if (rte_is_multicast_ether_addr(addr))
1701                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1702                               hns3_add_mc_addr(hw, addr);
1703                 else
1704                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705                               hns3_add_uc_addr_common(hw, addr);
1706
1707                 if (ret) {
1708                         err = ret;
1709                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                               addr);
1711                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712                                  "ret = %d.", del ? "remove" : "restore",
1713                                  mac_str, i, ret);
1714                 }
1715         }
1716         return err;
1717 }
1718
1719 static void
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1721 {
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1723         uint8_t word_num;
1724         uint8_t bit_num;
1725
1726         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727                 word_num = vfid / 32;
1728                 bit_num = vfid % 32;
1729                 if (clr)
1730                         desc[1].data[word_num] &=
1731                             rte_cpu_to_le_32(~(1UL << bit_num));
1732                 else
1733                         desc[1].data[word_num] |=
1734                             rte_cpu_to_le_32(1UL << bit_num);
1735         } else {
1736                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737                 bit_num = vfid % 32;
1738                 if (clr)
1739                         desc[2].data[word_num] &=
1740                             rte_cpu_to_le_32(~(1UL << bit_num));
1741                 else
1742                         desc[2].data[word_num] |=
1743                             rte_cpu_to_le_32(1UL << bit_num);
1744         }
1745 }
1746
1747 static int
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_mac_vlan_tbl_entry_cmd req;
1751         struct hns3_cmd_desc desc[3];
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         uint8_t vf_id;
1754         int ret;
1755
1756         /* Check if mac addr is valid */
1757         if (!rte_is_multicast_ether_addr(mac_addr)) {
1758                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1759                                       mac_addr);
1760                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1761                          mac_str);
1762                 return -EINVAL;
1763         }
1764
1765         memset(&req, 0, sizeof(req));
1766         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1769         if (ret) {
1770                 /* This mac addr do not exist, add new entry for it */
1771                 memset(desc[0].data, 0, sizeof(desc[0].data));
1772                 memset(desc[1].data, 0, sizeof(desc[0].data));
1773                 memset(desc[2].data, 0, sizeof(desc[0].data));
1774         }
1775
1776         /*
1777          * In current version VF is not supported when PF is driven by DPDK
1778          * driver, just need to configure parameters for PF vport.
1779          */
1780         vf_id = HNS3_PF_FUNC_ID;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, just need to configure parameters for PF vport.
1821                  */
1822                 vf_id = HNS3_PF_FUNC_ID;
1823                 hns3_update_desc_vfid(desc, vf_id, true);
1824
1825                 /* All the vfid is zero, so need to delete this entry */
1826                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827         } else if (ret == -ENOENT) {
1828                 /* This mac addr doesn't exist. */
1829                 return 0;
1830         }
1831
1832         if (ret) {
1833                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1834                                       mac_addr);
1835                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1836         }
1837
1838         return ret;
1839 }
1840
1841 static int
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843                            struct rte_ether_addr *mc_addr_set,
1844                            uint32_t nb_mc_addr)
1845 {
1846         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847         struct rte_ether_addr *addr;
1848         uint32_t i;
1849         uint32_t j;
1850
1851         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853                          "invalid. valid range: 0~%d",
1854                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1855                 return -EINVAL;
1856         }
1857
1858         /* Check if input mac addresses are valid */
1859         for (i = 0; i < nb_mc_addr; i++) {
1860                 addr = &mc_addr_set[i];
1861                 if (!rte_is_multicast_ether_addr(addr)) {
1862                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1863                                               addr);
1864                         hns3_err(hw,
1865                                  "failed to set mc mac addr, addr(%s) invalid.",
1866                                  mac_str);
1867                         return -EINVAL;
1868                 }
1869
1870                 /* Check if there are duplicate addresses */
1871                 for (j = i + 1; j < nb_mc_addr; j++) {
1872                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873                                 rte_ether_format_addr(mac_str,
1874                                                       RTE_ETHER_ADDR_FMT_SIZE,
1875                                                       addr);
1876                                 hns3_err(hw, "failed to set mc mac addr, "
1877                                          "addrs invalid. two same addrs(%s).",
1878                                          mac_str);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882
1883                 /*
1884                  * Check if there are duplicate addresses between mac_addrs
1885                  * and mc_addr_set
1886                  */
1887                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888                         if (rte_is_same_ether_addr(addr,
1889                                                    &hw->data->mac_addrs[j])) {
1890                                 rte_ether_format_addr(mac_str,
1891                                                       RTE_ETHER_ADDR_FMT_SIZE,
1892                                                       addr);
1893                                 hns3_err(hw, "failed to set mc mac addr, "
1894                                          "addrs invalid. addrs(%s) has already "
1895                                          "configured in mac_addr add API",
1896                                          mac_str);
1897                                 return -EINVAL;
1898                         }
1899                 }
1900         }
1901
1902         return 0;
1903 }
1904
1905 static void
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907                            struct rte_ether_addr *mc_addr_set,
1908                            int mc_addr_num,
1909                            struct rte_ether_addr *reserved_addr_list,
1910                            int *reserved_addr_num,
1911                            struct rte_ether_addr *add_addr_list,
1912                            int *add_addr_num,
1913                            struct rte_ether_addr *rm_addr_list,
1914                            int *rm_addr_num)
1915 {
1916         struct rte_ether_addr *addr;
1917         int current_addr_num;
1918         int reserved_num = 0;
1919         int add_num = 0;
1920         int rm_num = 0;
1921         int num;
1922         int i;
1923         int j;
1924         bool same_addr;
1925
1926         /* Calculate the mc mac address list that should be removed */
1927         current_addr_num = hw->mc_addrs_num;
1928         for (i = 0; i < current_addr_num; i++) {
1929                 addr = &hw->mc_addrs[i];
1930                 same_addr = false;
1931                 for (j = 0; j < mc_addr_num; j++) {
1932                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1933                                 same_addr = true;
1934                                 break;
1935                         }
1936                 }
1937
1938                 if (!same_addr) {
1939                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1940                         rm_num++;
1941                 } else {
1942                         rte_ether_addr_copy(addr,
1943                                             &reserved_addr_list[reserved_num]);
1944                         reserved_num++;
1945                 }
1946         }
1947
1948         /* Calculate the mc mac address list that should be added */
1949         for (i = 0; i < mc_addr_num; i++) {
1950                 addr = &mc_addr_set[i];
1951                 same_addr = false;
1952                 for (j = 0; j < current_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1961                         add_num++;
1962                 }
1963         }
1964
1965         /* Reorder the mc mac address list maintained by driver */
1966         for (i = 0; i < reserved_num; i++)
1967                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1968
1969         for (i = 0; i < rm_num; i++) {
1970                 num = reserved_num + i;
1971                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1972         }
1973
1974         *reserved_addr_num = reserved_num;
1975         *add_addr_num = add_num;
1976         *rm_addr_num = rm_num;
1977 }
1978
1979 static int
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981                           struct rte_ether_addr *mc_addr_set,
1982                           uint32_t nb_mc_addr)
1983 {
1984         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr *addr;
1989         int reserved_addr_num;
1990         int add_addr_num;
1991         int rm_addr_num;
1992         int mc_addr_num;
1993         int num;
1994         int ret;
1995         int i;
1996
1997         /* Check if input parameters are valid */
1998         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1999         if (ret)
2000                 return ret;
2001
2002         rte_spinlock_lock(&hw->lock);
2003
2004         /*
2005          * Calculate the mc mac address lists those should be removed and be
2006          * added, Reorder the mc mac address list maintained by driver.
2007          */
2008         mc_addr_num = (int)nb_mc_addr;
2009         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010                                    reserved_addr_list, &reserved_addr_num,
2011                                    add_addr_list, &add_addr_num,
2012                                    rm_addr_list, &rm_addr_num);
2013
2014         /* Remove mc mac addresses */
2015         for (i = 0; i < rm_addr_num; i++) {
2016                 num = rm_addr_num - i - 1;
2017                 addr = &rm_addr_list[num];
2018                 ret = hns3_remove_mc_addr(hw, addr);
2019                 if (ret) {
2020                         rte_spinlock_unlock(&hw->lock);
2021                         return ret;
2022                 }
2023                 hw->mc_addrs_num--;
2024         }
2025
2026         /* Add mc mac addresses */
2027         for (i = 0; i < add_addr_num; i++) {
2028                 addr = &add_addr_list[i];
2029                 ret = hns3_add_mc_addr(hw, addr);
2030                 if (ret) {
2031                         rte_spinlock_unlock(&hw->lock);
2032                         return ret;
2033                 }
2034
2035                 num = reserved_addr_num + i;
2036                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2037                 hw->mc_addrs_num++;
2038         }
2039         rte_spinlock_unlock(&hw->lock);
2040
2041         return 0;
2042 }
2043
2044 static int
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2046 {
2047         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048         struct hns3_hw *hw = &hns->hw;
2049         struct rte_ether_addr *addr;
2050         int err = 0;
2051         int ret;
2052         int i;
2053
2054         for (i = 0; i < hw->mc_addrs_num; i++) {
2055                 addr = &hw->mc_addrs[i];
2056                 if (!rte_is_multicast_ether_addr(addr))
2057                         continue;
2058                 if (del)
2059                         ret = hns3_remove_mc_addr(hw, addr);
2060                 else
2061                         ret = hns3_add_mc_addr(hw, addr);
2062                 if (ret) {
2063                         err = ret;
2064                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2065                                               addr);
2066                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067                                  del ? "Remove" : "Restore", mac_str, ret);
2068                 }
2069         }
2070         return err;
2071 }
2072
2073 static int
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2075 {
2076         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2082         uint8_t num_tc;
2083         int max_tc = 0;
2084         int i;
2085
2086         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2088
2089         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091                          "rx_mq_mode = %d", rx_mq_mode);
2092                 return -EINVAL;
2093         }
2094
2095         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099                          rx_mq_mode, tx_mq_mode);
2100                 return -EINVAL;
2101         }
2102
2103         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2107                         return -EINVAL;
2108                 }
2109
2110                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113                                  "nb_tcs(%d) != %d or %d in rx direction.",
2114                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2115                         return -EINVAL;
2116                 }
2117
2118                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2121                         return -EINVAL;
2122                 }
2123
2124                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127                                          "is not equal to one in tx direction.",
2128                                          i, dcb_rx_conf->dcb_tc[i]);
2129                                 return -EINVAL;
2130                         }
2131                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132                                 max_tc = dcb_rx_conf->dcb_tc[i];
2133                 }
2134
2135                 num_tc = max_tc + 1;
2136                 if (num_tc > dcb_rx_conf->nb_tcs) {
2137                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138                                  num_tc, dcb_rx_conf->nb_tcs);
2139                         return -EINVAL;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2148 {
2149         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         if (!hns3_dev_dcb_supported(hw)) {
2152                 hns3_err(hw, "this port does not support dcb configurations.");
2153                 return -EOPNOTSUPP;
2154         }
2155
2156         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2158                 return -EOPNOTSUPP;
2159         }
2160
2161         /* Check multiple queue mode */
2162         return hns3_check_mq_mode(dev);
2163 }
2164
2165 static int
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167                            enum hns3_ring_type queue_type, uint16_t queue_id)
2168 {
2169         struct hns3_cmd_desc desc;
2170         struct hns3_ctrl_vector_chain_cmd *req =
2171                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172         enum hns3_cmd_status status;
2173         enum hns3_opcode_type op;
2174         uint16_t tqp_type_and_id = 0;
2175         const char *op_str;
2176         uint16_t type;
2177         uint16_t gl;
2178
2179         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180         hns3_cmd_setup_basic_desc(&desc, op, false);
2181         req->int_vector_id = vector_id;
2182
2183         if (queue_type == HNS3_RING_TYPE_RX)
2184                 gl = HNS3_RING_GL_RX;
2185         else
2186                 gl = HNS3_RING_GL_TX;
2187
2188         type = queue_type;
2189
2190         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2191                        type);
2192         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2194                        gl);
2195         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196         req->int_cause_num = 1;
2197         op_str = mmap ? "Map" : "Unmap";
2198         status = hns3_cmd_send(hw, &desc, 1);
2199         if (status) {
2200                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201                          op_str, queue_id, req->int_vector_id, status);
2202                 return status;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2210 {
2211         uint16_t vec;
2212         int ret;
2213         int i;
2214
2215         /*
2216          * In hns3 network engine, vector 0 is always the misc interrupt of this
2217          * function, vector 1~N can be used respectively for the queues of the
2218          * function. Tx and Rx queues with the same number share the interrupt
2219          * vector. In the initialization clearing the all hardware mapping
2220          * relationship configurations between queues and interrupt vectors is
2221          * needed, so some error caused by the residual configurations, such as
2222          * the unexpected Tx interrupt, can be avoid.
2223          */
2224         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2225         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2226                 vec = vec - 1; /* the last interrupt is reserved */
2227         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2228         for (i = 0; i < hw->intr_tqps_num; i++) {
2229                 /*
2230                  * Set gap limiter/rate limiter/quanity limiter algorithm
2231                  * configuration for interrupt coalesce of queue's interrupt.
2232                  */
2233                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2234                                        HNS3_TQP_INTR_GL_DEFAULT);
2235                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2236                                        HNS3_TQP_INTR_GL_DEFAULT);
2237                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2238                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2239
2240                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2241                                                  HNS3_RING_TYPE_TX, i);
2242                 if (ret) {
2243                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2244                                           "vector: %d, ret=%d", i, vec, ret);
2245                         return ret;
2246                 }
2247
2248                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2249                                                  HNS3_RING_TYPE_RX, i);
2250                 if (ret) {
2251                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2252                                           "vector: %d, ret=%d", i, vec, ret);
2253                         return ret;
2254                 }
2255         }
2256
2257         return 0;
2258 }
2259
2260 static int
2261 hns3_dev_configure(struct rte_eth_dev *dev)
2262 {
2263         struct hns3_adapter *hns = dev->data->dev_private;
2264         struct rte_eth_conf *conf = &dev->data->dev_conf;
2265         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2266         struct hns3_hw *hw = &hns->hw;
2267         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2268         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2269         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2270         struct rte_eth_rss_conf rss_conf;
2271         uint16_t mtu;
2272         bool gro_en;
2273         int ret;
2274
2275         /*
2276          * Hardware does not support individually enable/disable/reset the Tx or
2277          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2278          * and Rx queues at the same time. When the numbers of Tx queues
2279          * allocated by upper applications are not equal to the numbers of Rx
2280          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2281          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2282          * these fake queues are imperceptible, and can not be used by upper
2283          * applications.
2284          */
2285         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2286         if (ret) {
2287                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2288                 return ret;
2289         }
2290
2291         hw->adapter_state = HNS3_NIC_CONFIGURING;
2292         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2293                 hns3_err(hw, "setting link speed/duplex not supported");
2294                 ret = -EINVAL;
2295                 goto cfg_err;
2296         }
2297
2298         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2299                 ret = hns3_check_dcb_cfg(dev);
2300                 if (ret)
2301                         goto cfg_err;
2302         }
2303
2304         /* When RSS is not configured, redirect the packet queue 0 */
2305         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2306                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2307                 rss_conf = conf->rx_adv_conf.rss_conf;
2308                 if (rss_conf.rss_key == NULL) {
2309                         rss_conf.rss_key = rss_cfg->key;
2310                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2311                 }
2312
2313                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2314                 if (ret)
2315                         goto cfg_err;
2316         }
2317
2318         /*
2319          * If jumbo frames are enabled, MTU needs to be refreshed
2320          * according to the maximum RX packet length.
2321          */
2322         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2323                 /*
2324                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2325                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2326                  * can safely assign to "uint16_t" type variable.
2327                  */
2328                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2329                 ret = hns3_dev_mtu_set(dev, mtu);
2330                 if (ret)
2331                         goto cfg_err;
2332                 dev->data->mtu = mtu;
2333         }
2334
2335         ret = hns3_dev_configure_vlan(dev);
2336         if (ret)
2337                 goto cfg_err;
2338
2339         /* config hardware GRO */
2340         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2341         ret = hns3_config_gro(hw, gro_en);
2342         if (ret)
2343                 goto cfg_err;
2344
2345         hw->adapter_state = HNS3_NIC_CONFIGURED;
2346
2347         return 0;
2348
2349 cfg_err:
2350         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2351         hw->adapter_state = HNS3_NIC_INITIALIZED;
2352
2353         return ret;
2354 }
2355
2356 static int
2357 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2358 {
2359         struct hns3_config_max_frm_size_cmd *req;
2360         struct hns3_cmd_desc desc;
2361
2362         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2363
2364         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2365         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2366         req->min_frm_size = RTE_ETHER_MIN_LEN;
2367
2368         return hns3_cmd_send(hw, &desc, 1);
2369 }
2370
2371 static int
2372 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2373 {
2374         int ret;
2375
2376         ret = hns3_set_mac_mtu(hw, mps);
2377         if (ret) {
2378                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2379                 return ret;
2380         }
2381
2382         ret = hns3_buffer_alloc(hw);
2383         if (ret)
2384                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2385
2386         return ret;
2387 }
2388
2389 static int
2390 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2391 {
2392         struct hns3_adapter *hns = dev->data->dev_private;
2393         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2394         struct hns3_hw *hw = &hns->hw;
2395         bool is_jumbo_frame;
2396         int ret;
2397
2398         if (dev->data->dev_started) {
2399                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2400                          "before configuration", dev->data->port_id);
2401                 return -EBUSY;
2402         }
2403
2404         rte_spinlock_lock(&hw->lock);
2405         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2406         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2407
2408         /*
2409          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2410          * assign to "uint16_t" type variable.
2411          */
2412         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2413         if (ret) {
2414                 rte_spinlock_unlock(&hw->lock);
2415                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2416                          dev->data->port_id, mtu, ret);
2417                 return ret;
2418         }
2419         hns->pf.mps = (uint16_t)frame_size;
2420         if (is_jumbo_frame)
2421                 dev->data->dev_conf.rxmode.offloads |=
2422                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2423         else
2424                 dev->data->dev_conf.rxmode.offloads &=
2425                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2426         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2427         rte_spinlock_unlock(&hw->lock);
2428
2429         return 0;
2430 }
2431
2432 static int
2433 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2434 {
2435         struct hns3_adapter *hns = eth_dev->data->dev_private;
2436         struct hns3_hw *hw = &hns->hw;
2437         uint16_t queue_num = hw->tqps_num;
2438
2439         /*
2440          * In interrupt mode, 'max_rx_queues' is set based on the number of
2441          * MSI-X interrupt resources of the hardware.
2442          */
2443         if (hw->data->dev_conf.intr_conf.rxq == 1)
2444                 queue_num = hw->intr_tqps_num;
2445
2446         info->max_rx_queues = queue_num;
2447         info->max_tx_queues = hw->tqps_num;
2448         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2449         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2450         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2451         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2452         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2453         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2454                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2455                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2456                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2457                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2458                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2459                                  DEV_RX_OFFLOAD_KEEP_CRC |
2460                                  DEV_RX_OFFLOAD_SCATTER |
2461                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2462                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2463                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2464                                  DEV_RX_OFFLOAD_RSS_HASH |
2465                                  DEV_RX_OFFLOAD_TCP_LRO);
2466         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2467         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2468                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2469                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2470                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2471                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2472                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2473                                  DEV_TX_OFFLOAD_TCP_TSO |
2474                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2475                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2476                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2477                                  info->tx_queue_offload_capa |
2478                                  hns3_txvlan_cap_get(hw));
2479
2480         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2481                 .nb_max = HNS3_MAX_RING_DESC,
2482                 .nb_min = HNS3_MIN_RING_DESC,
2483                 .nb_align = HNS3_ALIGN_RING_DESC,
2484         };
2485
2486         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2487                 .nb_max = HNS3_MAX_RING_DESC,
2488                 .nb_min = HNS3_MIN_RING_DESC,
2489                 .nb_align = HNS3_ALIGN_RING_DESC,
2490                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2491                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
2492         };
2493
2494         info->default_rxconf = (struct rte_eth_rxconf) {
2495                 /*
2496                  * If there are no available Rx buffer descriptors, incoming
2497                  * packets are always dropped by hardware based on hns3 network
2498                  * engine.
2499                  */
2500                 .rx_drop_en = 1,
2501         };
2502
2503         info->vmdq_queue_num = 0;
2504
2505         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2506         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2507         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2508
2509         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2510         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2511         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2512         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2513         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2514         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2515
2516         return 0;
2517 }
2518
2519 static int
2520 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2521                     size_t fw_size)
2522 {
2523         struct hns3_adapter *hns = eth_dev->data->dev_private;
2524         struct hns3_hw *hw = &hns->hw;
2525         uint32_t version = hw->fw_version;
2526         int ret;
2527
2528         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2529                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2530                                       HNS3_FW_VERSION_BYTE3_S),
2531                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2532                                       HNS3_FW_VERSION_BYTE2_S),
2533                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2534                                       HNS3_FW_VERSION_BYTE1_S),
2535                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2536                                       HNS3_FW_VERSION_BYTE0_S));
2537         ret += 1; /* add the size of '\0' */
2538         if (fw_size < (uint32_t)ret)
2539                 return ret;
2540         else
2541                 return 0;
2542 }
2543
2544 static int
2545 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2546                      __rte_unused int wait_to_complete)
2547 {
2548         struct hns3_adapter *hns = eth_dev->data->dev_private;
2549         struct hns3_hw *hw = &hns->hw;
2550         struct hns3_mac *mac = &hw->mac;
2551         struct rte_eth_link new_link;
2552
2553         if (!hns3_is_reset_pending(hns)) {
2554                 hns3_update_speed_duplex(eth_dev);
2555                 hns3_update_link_status(hw);
2556         }
2557
2558         memset(&new_link, 0, sizeof(new_link));
2559         switch (mac->link_speed) {
2560         case ETH_SPEED_NUM_10M:
2561         case ETH_SPEED_NUM_100M:
2562         case ETH_SPEED_NUM_1G:
2563         case ETH_SPEED_NUM_10G:
2564         case ETH_SPEED_NUM_25G:
2565         case ETH_SPEED_NUM_40G:
2566         case ETH_SPEED_NUM_50G:
2567         case ETH_SPEED_NUM_100G:
2568         case ETH_SPEED_NUM_200G:
2569                 new_link.link_speed = mac->link_speed;
2570                 break;
2571         default:
2572                 new_link.link_speed = ETH_SPEED_NUM_100M;
2573                 break;
2574         }
2575
2576         new_link.link_duplex = mac->link_duplex;
2577         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2578         new_link.link_autoneg =
2579             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2580
2581         return rte_eth_linkstatus_set(eth_dev, &new_link);
2582 }
2583
2584 static int
2585 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2586 {
2587         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2588         struct hns3_pf *pf = &hns->pf;
2589
2590         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2591                 return -EINVAL;
2592
2593         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2594
2595         return 0;
2596 }
2597
2598 static int
2599 hns3_query_function_status(struct hns3_hw *hw)
2600 {
2601 #define HNS3_QUERY_MAX_CNT              10
2602 #define HNS3_QUERY_SLEEP_MSCOEND        1
2603         struct hns3_func_status_cmd *req;
2604         struct hns3_cmd_desc desc;
2605         int timeout = 0;
2606         int ret;
2607
2608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2609         req = (struct hns3_func_status_cmd *)desc.data;
2610
2611         do {
2612                 ret = hns3_cmd_send(hw, &desc, 1);
2613                 if (ret) {
2614                         PMD_INIT_LOG(ERR, "query function status failed %d",
2615                                      ret);
2616                         return ret;
2617                 }
2618
2619                 /* Check pf reset is done */
2620                 if (req->pf_state)
2621                         break;
2622
2623                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2624         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2625
2626         return hns3_parse_func_status(hw, req);
2627 }
2628
2629 static int
2630 hns3_query_pf_resource(struct hns3_hw *hw)
2631 {
2632         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2633         struct hns3_pf *pf = &hns->pf;
2634         struct hns3_pf_res_cmd *req;
2635         struct hns3_cmd_desc desc;
2636         int ret;
2637
2638         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2639         ret = hns3_cmd_send(hw, &desc, 1);
2640         if (ret) {
2641                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2642                 return ret;
2643         }
2644
2645         req = (struct hns3_pf_res_cmd *)desc.data;
2646         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2647         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2648         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2649         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2650
2651         if (req->tx_buf_size)
2652                 pf->tx_buf_size =
2653                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2654         else
2655                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2656
2657         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2658
2659         if (req->dv_buf_size)
2660                 pf->dv_buf_size =
2661                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2662         else
2663                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2664
2665         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2666
2667         hw->num_msi =
2668                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2669                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2670
2671         return 0;
2672 }
2673
2674 static void
2675 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2676 {
2677         struct hns3_cfg_param_cmd *req;
2678         uint64_t mac_addr_tmp_high;
2679         uint64_t mac_addr_tmp;
2680         uint32_t i;
2681
2682         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2683
2684         /* get the configuration */
2685         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2686                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2687         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2688                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2689         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2690                                            HNS3_CFG_TQP_DESC_N_M,
2691                                            HNS3_CFG_TQP_DESC_N_S);
2692
2693         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2694                                        HNS3_CFG_PHY_ADDR_M,
2695                                        HNS3_CFG_PHY_ADDR_S);
2696         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2697                                          HNS3_CFG_MEDIA_TP_M,
2698                                          HNS3_CFG_MEDIA_TP_S);
2699         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2700                                          HNS3_CFG_RX_BUF_LEN_M,
2701                                          HNS3_CFG_RX_BUF_LEN_S);
2702         /* get mac address */
2703         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2704         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2705                                            HNS3_CFG_MAC_ADDR_H_M,
2706                                            HNS3_CFG_MAC_ADDR_H_S);
2707
2708         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2709
2710         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2711                                             HNS3_CFG_DEFAULT_SPEED_M,
2712                                             HNS3_CFG_DEFAULT_SPEED_S);
2713         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2714                                            HNS3_CFG_RSS_SIZE_M,
2715                                            HNS3_CFG_RSS_SIZE_S);
2716
2717         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2718                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2719
2720         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2721         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2722
2723         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2724                                             HNS3_CFG_SPEED_ABILITY_M,
2725                                             HNS3_CFG_SPEED_ABILITY_S);
2726         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2727                                         HNS3_CFG_UMV_TBL_SPACE_M,
2728                                         HNS3_CFG_UMV_TBL_SPACE_S);
2729         if (!cfg->umv_space)
2730                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2731 }
2732
2733 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2734  * @hw: pointer to struct hns3_hw
2735  * @hcfg: the config structure to be getted
2736  */
2737 static int
2738 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2739 {
2740         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2741         struct hns3_cfg_param_cmd *req;
2742         uint32_t offset;
2743         uint32_t i;
2744         int ret;
2745
2746         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2747                 offset = 0;
2748                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2749                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2750                                           true);
2751                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2752                                i * HNS3_CFG_RD_LEN_BYTES);
2753                 /* Len should be divided by 4 when send to hardware */
2754                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2755                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2756                 req->offset = rte_cpu_to_le_32(offset);
2757         }
2758
2759         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2760         if (ret) {
2761                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2762                 return ret;
2763         }
2764
2765         hns3_parse_cfg(hcfg, desc);
2766
2767         return 0;
2768 }
2769
2770 static int
2771 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2772 {
2773         switch (speed_cmd) {
2774         case HNS3_CFG_SPEED_10M:
2775                 *speed = ETH_SPEED_NUM_10M;
2776                 break;
2777         case HNS3_CFG_SPEED_100M:
2778                 *speed = ETH_SPEED_NUM_100M;
2779                 break;
2780         case HNS3_CFG_SPEED_1G:
2781                 *speed = ETH_SPEED_NUM_1G;
2782                 break;
2783         case HNS3_CFG_SPEED_10G:
2784                 *speed = ETH_SPEED_NUM_10G;
2785                 break;
2786         case HNS3_CFG_SPEED_25G:
2787                 *speed = ETH_SPEED_NUM_25G;
2788                 break;
2789         case HNS3_CFG_SPEED_40G:
2790                 *speed = ETH_SPEED_NUM_40G;
2791                 break;
2792         case HNS3_CFG_SPEED_50G:
2793                 *speed = ETH_SPEED_NUM_50G;
2794                 break;
2795         case HNS3_CFG_SPEED_100G:
2796                 *speed = ETH_SPEED_NUM_100G;
2797                 break;
2798         case HNS3_CFG_SPEED_200G:
2799                 *speed = ETH_SPEED_NUM_200G;
2800                 break;
2801         default:
2802                 return -EINVAL;
2803         }
2804
2805         return 0;
2806 }
2807
2808 static void
2809 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2810 {
2811         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2812         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2813         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2814         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2815 }
2816
2817 static void
2818 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2819 {
2820         struct hns3_dev_specs_0_cmd *req0;
2821
2822         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2823
2824         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2825         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2826         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2827         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2828 }
2829
2830 static int
2831 hns3_query_dev_specifications(struct hns3_hw *hw)
2832 {
2833         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2834         int ret;
2835         int i;
2836
2837         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2838                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2839                                           true);
2840                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2841         }
2842         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2843
2844         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2845         if (ret)
2846                 return ret;
2847
2848         hns3_parse_dev_specifications(hw, desc);
2849
2850         return 0;
2851 }
2852
2853 static int
2854 hns3_get_capability(struct hns3_hw *hw)
2855 {
2856         struct rte_pci_device *pci_dev;
2857         struct rte_eth_dev *eth_dev;
2858         uint16_t device_id;
2859         uint8_t revision;
2860         int ret;
2861
2862         eth_dev = &rte_eth_devices[hw->data->port_id];
2863         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2864         device_id = pci_dev->id.device_id;
2865
2866         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2867             device_id == HNS3_DEV_ID_50GE_RDMA ||
2868             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2869             device_id == HNS3_DEV_ID_200G_RDMA)
2870                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2871
2872         /* Get PCI revision id */
2873         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2874                                   HNS3_PCI_REVISION_ID);
2875         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2876                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2877                              ret);
2878                 return -EIO;
2879         }
2880         hw->revision = revision;
2881
2882         if (revision < PCI_REVISION_ID_HIP09_A) {
2883                 hns3_set_default_dev_specifications(hw);
2884                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2885                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2886                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2887                 return 0;
2888         }
2889
2890         ret = hns3_query_dev_specifications(hw);
2891         if (ret) {
2892                 PMD_INIT_LOG(ERR,
2893                              "failed to query dev specifications, ret = %d",
2894                              ret);
2895                 return ret;
2896         }
2897
2898         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2899         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
2900         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2901
2902         return 0;
2903 }
2904
2905 static int
2906 hns3_get_board_configuration(struct hns3_hw *hw)
2907 {
2908         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2909         struct hns3_pf *pf = &hns->pf;
2910         struct hns3_cfg cfg;
2911         int ret;
2912
2913         ret = hns3_get_board_cfg(hw, &cfg);
2914         if (ret) {
2915                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2916                 return ret;
2917         }
2918
2919         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
2920             !hns3_dev_copper_supported(hw)) {
2921                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2922                 return -EOPNOTSUPP;
2923         }
2924
2925         hw->mac.media_type = cfg.media_type;
2926         hw->rss_size_max = cfg.rss_size_max;
2927         hw->rss_dis_flag = false;
2928         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2929         hw->mac.phy_addr = cfg.phy_addr;
2930         hw->mac.default_addr_setted = false;
2931         hw->num_tx_desc = cfg.tqp_desc_num;
2932         hw->num_rx_desc = cfg.tqp_desc_num;
2933         hw->dcb_info.num_pg = 1;
2934         hw->dcb_info.hw_pfc_map = 0;
2935
2936         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2937         if (ret) {
2938                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2939                              cfg.default_speed, ret);
2940                 return ret;
2941         }
2942
2943         pf->tc_max = cfg.tc_num;
2944         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2945                 PMD_INIT_LOG(WARNING,
2946                              "Get TC num(%u) from flash, set TC num to 1",
2947                              pf->tc_max);
2948                 pf->tc_max = 1;
2949         }
2950
2951         /* Dev does not support DCB */
2952         if (!hns3_dev_dcb_supported(hw)) {
2953                 pf->tc_max = 1;
2954                 pf->pfc_max = 0;
2955         } else
2956                 pf->pfc_max = pf->tc_max;
2957
2958         hw->dcb_info.num_tc = 1;
2959         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2960                                      hw->tqps_num / hw->dcb_info.num_tc);
2961         hns3_set_bit(hw->hw_tc_map, 0, 1);
2962         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2963
2964         pf->wanted_umv_size = cfg.umv_space;
2965
2966         return ret;
2967 }
2968
2969 static int
2970 hns3_get_configuration(struct hns3_hw *hw)
2971 {
2972         int ret;
2973
2974         ret = hns3_query_function_status(hw);
2975         if (ret) {
2976                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2977                 return ret;
2978         }
2979
2980         /* Get device capability */
2981         ret = hns3_get_capability(hw);
2982         if (ret) {
2983                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2984                 return ret;
2985         }
2986
2987         /* Get pf resource */
2988         ret = hns3_query_pf_resource(hw);
2989         if (ret) {
2990                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2991                 return ret;
2992         }
2993
2994         ret = hns3_get_board_configuration(hw);
2995         if (ret)
2996                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2997
2998         return ret;
2999 }
3000
3001 static int
3002 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3003                       uint16_t tqp_vid, bool is_pf)
3004 {
3005         struct hns3_tqp_map_cmd *req;
3006         struct hns3_cmd_desc desc;
3007         int ret;
3008
3009         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3010
3011         req = (struct hns3_tqp_map_cmd *)desc.data;
3012         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3013         req->tqp_vf = func_id;
3014         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3015         if (!is_pf)
3016                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3017         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3018
3019         ret = hns3_cmd_send(hw, &desc, 1);
3020         if (ret)
3021                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3022
3023         return ret;
3024 }
3025
3026 static int
3027 hns3_map_tqp(struct hns3_hw *hw)
3028 {
3029         uint16_t tqps_num = hw->total_tqps_num;
3030         uint16_t func_id;
3031         uint16_t tqp_id;
3032         bool is_pf;
3033         int num;
3034         int ret;
3035         int i;
3036
3037         /*
3038          * In current version VF is not supported when PF is driven by DPDK
3039          * driver, so we allocate tqps to PF as much as possible.
3040          */
3041         tqp_id = 0;
3042         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
3043         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
3044                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
3045                 for (i = 0;
3046                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
3047                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
3048                                                     is_pf);
3049                         if (ret)
3050                                 return ret;
3051                 }
3052         }
3053
3054         return 0;
3055 }
3056
3057 static int
3058 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3059 {
3060         struct hns3_config_mac_speed_dup_cmd *req;
3061         struct hns3_cmd_desc desc;
3062         int ret;
3063
3064         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3065
3066         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3067
3068         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3069
3070         switch (speed) {
3071         case ETH_SPEED_NUM_10M:
3072                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3073                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3074                 break;
3075         case ETH_SPEED_NUM_100M:
3076                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3077                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3078                 break;
3079         case ETH_SPEED_NUM_1G:
3080                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3081                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3082                 break;
3083         case ETH_SPEED_NUM_10G:
3084                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3085                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3086                 break;
3087         case ETH_SPEED_NUM_25G:
3088                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3089                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3090                 break;
3091         case ETH_SPEED_NUM_40G:
3092                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3093                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3094                 break;
3095         case ETH_SPEED_NUM_50G:
3096                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3097                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3098                 break;
3099         case ETH_SPEED_NUM_100G:
3100                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3101                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3102                 break;
3103         case ETH_SPEED_NUM_200G:
3104                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3105                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3106                 break;
3107         default:
3108                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3109                 return -EINVAL;
3110         }
3111
3112         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3113
3114         ret = hns3_cmd_send(hw, &desc, 1);
3115         if (ret)
3116                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3117
3118         return ret;
3119 }
3120
3121 static int
3122 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3123 {
3124         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3125         struct hns3_pf *pf = &hns->pf;
3126         struct hns3_priv_buf *priv;
3127         uint32_t i, total_size;
3128
3129         total_size = pf->pkt_buf_size;
3130
3131         /* alloc tx buffer for all enabled tc */
3132         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3133                 priv = &buf_alloc->priv_buf[i];
3134
3135                 if (hw->hw_tc_map & BIT(i)) {
3136                         if (total_size < pf->tx_buf_size)
3137                                 return -ENOMEM;
3138
3139                         priv->tx_buf_size = pf->tx_buf_size;
3140                 } else
3141                         priv->tx_buf_size = 0;
3142
3143                 total_size -= priv->tx_buf_size;
3144         }
3145
3146         return 0;
3147 }
3148
3149 static int
3150 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3151 {
3152 /* TX buffer size is unit by 128 byte */
3153 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3154 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3155         struct hns3_tx_buff_alloc_cmd *req;
3156         struct hns3_cmd_desc desc;
3157         uint32_t buf_size;
3158         uint32_t i;
3159         int ret;
3160
3161         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3162
3163         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3164         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3165                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3166
3167                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3168                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3169                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3170         }
3171
3172         ret = hns3_cmd_send(hw, &desc, 1);
3173         if (ret)
3174                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3175
3176         return ret;
3177 }
3178
3179 static int
3180 hns3_get_tc_num(struct hns3_hw *hw)
3181 {
3182         int cnt = 0;
3183         uint8_t i;
3184
3185         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3186                 if (hw->hw_tc_map & BIT(i))
3187                         cnt++;
3188         return cnt;
3189 }
3190
3191 static uint32_t
3192 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3193 {
3194         struct hns3_priv_buf *priv;
3195         uint32_t rx_priv = 0;
3196         int i;
3197
3198         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3199                 priv = &buf_alloc->priv_buf[i];
3200                 if (priv->enable)
3201                         rx_priv += priv->buf_size;
3202         }
3203         return rx_priv;
3204 }
3205
3206 static uint32_t
3207 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3208 {
3209         uint32_t total_tx_size = 0;
3210         uint32_t i;
3211
3212         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3213                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3214
3215         return total_tx_size;
3216 }
3217
3218 /* Get the number of pfc enabled TCs, which have private buffer */
3219 static int
3220 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3221 {
3222         struct hns3_priv_buf *priv;
3223         int cnt = 0;
3224         uint8_t i;
3225
3226         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3227                 priv = &buf_alloc->priv_buf[i];
3228                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3229                         cnt++;
3230         }
3231
3232         return cnt;
3233 }
3234
3235 /* Get the number of pfc disabled TCs, which have private buffer */
3236 static int
3237 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3238                          struct hns3_pkt_buf_alloc *buf_alloc)
3239 {
3240         struct hns3_priv_buf *priv;
3241         int cnt = 0;
3242         uint8_t i;
3243
3244         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3245                 priv = &buf_alloc->priv_buf[i];
3246                 if (hw->hw_tc_map & BIT(i) &&
3247                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3248                         cnt++;
3249         }
3250
3251         return cnt;
3252 }
3253
3254 static bool
3255 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3256                   uint32_t rx_all)
3257 {
3258         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3259         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3260         struct hns3_pf *pf = &hns->pf;
3261         uint32_t shared_buf, aligned_mps;
3262         uint32_t rx_priv;
3263         uint8_t tc_num;
3264         uint8_t i;
3265
3266         tc_num = hns3_get_tc_num(hw);
3267         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3268
3269         if (hns3_dev_dcb_supported(hw))
3270                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3271                                         pf->dv_buf_size;
3272         else
3273                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3274                                         + pf->dv_buf_size;
3275
3276         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3277         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3278                              HNS3_BUF_SIZE_UNIT);
3279
3280         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3281         if (rx_all < rx_priv + shared_std)
3282                 return false;
3283
3284         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3285         buf_alloc->s_buf.buf_size = shared_buf;
3286         if (hns3_dev_dcb_supported(hw)) {
3287                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3288                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3289                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3290                                   HNS3_BUF_SIZE_UNIT);
3291         } else {
3292                 buf_alloc->s_buf.self.high =
3293                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3294                 buf_alloc->s_buf.self.low = aligned_mps;
3295         }
3296
3297         if (hns3_dev_dcb_supported(hw)) {
3298                 hi_thrd = shared_buf - pf->dv_buf_size;
3299
3300                 if (tc_num <= NEED_RESERVE_TC_NUM)
3301                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3302                                         / BUF_MAX_PERCENT;
3303
3304                 if (tc_num)
3305                         hi_thrd = hi_thrd / tc_num;
3306
3307                 hi_thrd = max_t(uint32_t, hi_thrd,
3308                                 HNS3_BUF_MUL_BY * aligned_mps);
3309                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3310                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3311         } else {
3312                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3313                 lo_thrd = aligned_mps;
3314         }
3315
3316         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3317                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3318                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3319         }
3320
3321         return true;
3322 }
3323
3324 static bool
3325 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3326                      struct hns3_pkt_buf_alloc *buf_alloc)
3327 {
3328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3329         struct hns3_pf *pf = &hns->pf;
3330         struct hns3_priv_buf *priv;
3331         uint32_t aligned_mps;
3332         uint32_t rx_all;
3333         uint8_t i;
3334
3335         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3336         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3337
3338         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3339                 priv = &buf_alloc->priv_buf[i];
3340
3341                 priv->enable = 0;
3342                 priv->wl.low = 0;
3343                 priv->wl.high = 0;
3344                 priv->buf_size = 0;
3345
3346                 if (!(hw->hw_tc_map & BIT(i)))
3347                         continue;
3348
3349                 priv->enable = 1;
3350                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3351                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3352                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3353                                                 HNS3_BUF_SIZE_UNIT);
3354                 } else {
3355                         priv->wl.low = 0;
3356                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3357                                         aligned_mps;
3358                 }
3359
3360                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3361         }
3362
3363         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3364 }
3365
3366 static bool
3367 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3368                              struct hns3_pkt_buf_alloc *buf_alloc)
3369 {
3370         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3371         struct hns3_pf *pf = &hns->pf;
3372         struct hns3_priv_buf *priv;
3373         int no_pfc_priv_num;
3374         uint32_t rx_all;
3375         uint8_t mask;
3376         int i;
3377
3378         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3379         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3380
3381         /* let the last to be cleared first */
3382         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3383                 priv = &buf_alloc->priv_buf[i];
3384                 mask = BIT((uint8_t)i);
3385
3386                 if (hw->hw_tc_map & mask &&
3387                     !(hw->dcb_info.hw_pfc_map & mask)) {
3388                         /* Clear the no pfc TC private buffer */
3389                         priv->wl.low = 0;
3390                         priv->wl.high = 0;
3391                         priv->buf_size = 0;
3392                         priv->enable = 0;
3393                         no_pfc_priv_num--;
3394                 }
3395
3396                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3397                     no_pfc_priv_num == 0)
3398                         break;
3399         }
3400
3401         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3402 }
3403
3404 static bool
3405 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3406                            struct hns3_pkt_buf_alloc *buf_alloc)
3407 {
3408         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3409         struct hns3_pf *pf = &hns->pf;
3410         struct hns3_priv_buf *priv;
3411         uint32_t rx_all;
3412         int pfc_priv_num;
3413         uint8_t mask;
3414         int i;
3415
3416         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3417         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3418
3419         /* let the last to be cleared first */
3420         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3421                 priv = &buf_alloc->priv_buf[i];
3422                 mask = BIT((uint8_t)i);
3423
3424                 if (hw->hw_tc_map & mask &&
3425                     hw->dcb_info.hw_pfc_map & mask) {
3426                         /* Reduce the number of pfc TC with private buffer */
3427                         priv->wl.low = 0;
3428                         priv->enable = 0;
3429                         priv->wl.high = 0;
3430                         priv->buf_size = 0;
3431                         pfc_priv_num--;
3432                 }
3433                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3434                     pfc_priv_num == 0)
3435                         break;
3436         }
3437
3438         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3439 }
3440
3441 static bool
3442 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3443                           struct hns3_pkt_buf_alloc *buf_alloc)
3444 {
3445 #define COMPENSATE_BUFFER       0x3C00
3446 #define COMPENSATE_HALF_MPS_NUM 5
3447 #define PRIV_WL_GAP             0x1800
3448         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3449         struct hns3_pf *pf = &hns->pf;
3450         uint32_t tc_num = hns3_get_tc_num(hw);
3451         uint32_t half_mps = pf->mps >> 1;
3452         struct hns3_priv_buf *priv;
3453         uint32_t min_rx_priv;
3454         uint32_t rx_priv;
3455         uint8_t i;
3456
3457         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3458         if (tc_num)
3459                 rx_priv = rx_priv / tc_num;
3460
3461         if (tc_num <= NEED_RESERVE_TC_NUM)
3462                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3463
3464         /*
3465          * Minimum value of private buffer in rx direction (min_rx_priv) is
3466          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3467          * buffer if rx_priv is greater than min_rx_priv.
3468          */
3469         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3470                         COMPENSATE_HALF_MPS_NUM * half_mps;
3471         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3472         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3473
3474         if (rx_priv < min_rx_priv)
3475                 return false;
3476
3477         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3478                 priv = &buf_alloc->priv_buf[i];
3479
3480                 priv->enable = 0;
3481                 priv->wl.low = 0;
3482                 priv->wl.high = 0;
3483                 priv->buf_size = 0;
3484
3485                 if (!(hw->hw_tc_map & BIT(i)))
3486                         continue;
3487
3488                 priv->enable = 1;
3489                 priv->buf_size = rx_priv;
3490                 priv->wl.high = rx_priv - pf->dv_buf_size;
3491                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3492         }
3493
3494         buf_alloc->s_buf.buf_size = 0;
3495
3496         return true;
3497 }
3498
3499 /*
3500  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3501  * @hw: pointer to struct hns3_hw
3502  * @buf_alloc: pointer to buffer calculation data
3503  * @return: 0: calculate sucessful, negative: fail
3504  */
3505 static int
3506 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3507 {
3508         /* When DCB is not supported, rx private buffer is not allocated. */
3509         if (!hns3_dev_dcb_supported(hw)) {
3510                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3511                 struct hns3_pf *pf = &hns->pf;
3512                 uint32_t rx_all = pf->pkt_buf_size;
3513
3514                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3515                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3516                         return -ENOMEM;
3517
3518                 return 0;
3519         }
3520
3521         /*
3522          * Try to allocate privated packet buffer for all TCs without share
3523          * buffer.
3524          */
3525         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3526                 return 0;
3527
3528         /*
3529          * Try to allocate privated packet buffer for all TCs with share
3530          * buffer.
3531          */
3532         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3533                 return 0;
3534
3535         /*
3536          * For different application scenes, the enabled port number, TC number
3537          * and no_drop TC number are different. In order to obtain the better
3538          * performance, software could allocate the buffer size and configure
3539          * the waterline by tring to decrease the private buffer size according
3540          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3541          * enabled tc.
3542          */
3543         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3544                 return 0;
3545
3546         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3547                 return 0;
3548
3549         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3550                 return 0;
3551
3552         return -ENOMEM;
3553 }
3554
3555 static int
3556 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3557 {
3558         struct hns3_rx_priv_buff_cmd *req;
3559         struct hns3_cmd_desc desc;
3560         uint32_t buf_size;
3561         int ret;
3562         int i;
3563
3564         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3565         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3566
3567         /* Alloc private buffer TCs */
3568         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3569                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3570
3571                 req->buf_num[i] =
3572                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3573                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3574         }
3575
3576         buf_size = buf_alloc->s_buf.buf_size;
3577         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3578                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3579
3580         ret = hns3_cmd_send(hw, &desc, 1);
3581         if (ret)
3582                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3583
3584         return ret;
3585 }
3586
3587 static int
3588 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3589 {
3590 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3591         struct hns3_rx_priv_wl_buf *req;
3592         struct hns3_priv_buf *priv;
3593         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3594         int i, j;
3595         int ret;
3596
3597         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3598                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3599                                           false);
3600                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3601
3602                 /* The first descriptor set the NEXT bit to 1 */
3603                 if (i == 0)
3604                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3605                 else
3606                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3607
3608                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3609                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3610
3611                         priv = &buf_alloc->priv_buf[idx];
3612                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3613                                                         HNS3_BUF_UNIT_S);
3614                         req->tc_wl[j].high |=
3615                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3616                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3617                                                         HNS3_BUF_UNIT_S);
3618                         req->tc_wl[j].low |=
3619                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3620                 }
3621         }
3622
3623         /* Send 2 descriptor at one time */
3624         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3625         if (ret)
3626                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3627                              ret);
3628         return ret;
3629 }
3630
3631 static int
3632 hns3_common_thrd_config(struct hns3_hw *hw,
3633                         struct hns3_pkt_buf_alloc *buf_alloc)
3634 {
3635 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3636         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3637         struct hns3_rx_com_thrd *req;
3638         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3639         struct hns3_tc_thrd *tc;
3640         int tc_idx;
3641         int i, j;
3642         int ret;
3643
3644         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3645                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3646                                           false);
3647                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3648
3649                 /* The first descriptor set the NEXT bit to 1 */
3650                 if (i == 0)
3651                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3652                 else
3653                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3654
3655                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3656                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3657                         tc = &s_buf->tc_thrd[tc_idx];
3658
3659                         req->com_thrd[j].high =
3660                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3661                         req->com_thrd[j].high |=
3662                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3663                         req->com_thrd[j].low =
3664                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3665                         req->com_thrd[j].low |=
3666                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3667                 }
3668         }
3669
3670         /* Send 2 descriptors at one time */
3671         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3672         if (ret)
3673                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3674
3675         return ret;
3676 }
3677
3678 static int
3679 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3680 {
3681         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3682         struct hns3_rx_com_wl *req;
3683         struct hns3_cmd_desc desc;
3684         int ret;
3685
3686         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3687
3688         req = (struct hns3_rx_com_wl *)desc.data;
3689         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3690         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3691
3692         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3693         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3694
3695         ret = hns3_cmd_send(hw, &desc, 1);
3696         if (ret)
3697                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3698
3699         return ret;
3700 }
3701
3702 int
3703 hns3_buffer_alloc(struct hns3_hw *hw)
3704 {
3705         struct hns3_pkt_buf_alloc pkt_buf;
3706         int ret;
3707
3708         memset(&pkt_buf, 0, sizeof(pkt_buf));
3709         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3710         if (ret) {
3711                 PMD_INIT_LOG(ERR,
3712                              "could not calc tx buffer size for all TCs %d",
3713                              ret);
3714                 return ret;
3715         }
3716
3717         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3718         if (ret) {
3719                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3720                 return ret;
3721         }
3722
3723         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3724         if (ret) {
3725                 PMD_INIT_LOG(ERR,
3726                              "could not calc rx priv buffer size for all TCs %d",
3727                              ret);
3728                 return ret;
3729         }
3730
3731         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3732         if (ret) {
3733                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3734                 return ret;
3735         }
3736
3737         if (hns3_dev_dcb_supported(hw)) {
3738                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3739                 if (ret) {
3740                         PMD_INIT_LOG(ERR,
3741                                      "could not configure rx private waterline %d",
3742                                      ret);
3743                         return ret;
3744                 }
3745
3746                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3747                 if (ret) {
3748                         PMD_INIT_LOG(ERR,
3749                                      "could not configure common threshold %d",
3750                                      ret);
3751                         return ret;
3752                 }
3753         }
3754
3755         ret = hns3_common_wl_config(hw, &pkt_buf);
3756         if (ret)
3757                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3758                              ret);
3759
3760         return ret;
3761 }
3762
3763 static int
3764 hns3_mac_init(struct hns3_hw *hw)
3765 {
3766         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3767         struct hns3_mac *mac = &hw->mac;
3768         struct hns3_pf *pf = &hns->pf;
3769         int ret;
3770
3771         pf->support_sfp_query = true;
3772         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3773         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3774         if (ret) {
3775                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3776                 return ret;
3777         }
3778
3779         mac->link_status = ETH_LINK_DOWN;
3780
3781         return hns3_config_mtu(hw, pf->mps);
3782 }
3783
3784 static int
3785 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3786 {
3787 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3788 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3789 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3790 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3791         int return_status;
3792
3793         if (cmdq_resp) {
3794                 PMD_INIT_LOG(ERR,
3795                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3796                              cmdq_resp);
3797                 return -EIO;
3798         }
3799
3800         switch (resp_code) {
3801         case HNS3_ETHERTYPE_SUCCESS_ADD:
3802         case HNS3_ETHERTYPE_ALREADY_ADD:
3803                 return_status = 0;
3804                 break;
3805         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3806                 PMD_INIT_LOG(ERR,
3807                              "add mac ethertype failed for manager table overflow.");
3808                 return_status = -EIO;
3809                 break;
3810         case HNS3_ETHERTYPE_KEY_CONFLICT:
3811                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3812                 return_status = -EIO;
3813                 break;
3814         default:
3815                 PMD_INIT_LOG(ERR,
3816                              "add mac ethertype failed for undefined, code=%d.",
3817                              resp_code);
3818                 return_status = -EIO;
3819                 break;
3820         }
3821
3822         return return_status;
3823 }
3824
3825 static int
3826 hns3_add_mgr_tbl(struct hns3_hw *hw,
3827                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3828 {
3829         struct hns3_cmd_desc desc;
3830         uint8_t resp_code;
3831         uint16_t retval;
3832         int ret;
3833
3834         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3835         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3836
3837         ret = hns3_cmd_send(hw, &desc, 1);
3838         if (ret) {
3839                 PMD_INIT_LOG(ERR,
3840                              "add mac ethertype failed for cmd_send, ret =%d.",
3841                              ret);
3842                 return ret;
3843         }
3844
3845         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3846         retval = rte_le_to_cpu_16(desc.retval);
3847
3848         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3849 }
3850
3851 static void
3852 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3853                      int *table_item_num)
3854 {
3855         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3856
3857         /*
3858          * In current version, we add one item in management table as below:
3859          * 0x0180C200000E -- LLDP MC address
3860          */
3861         tbl = mgr_table;
3862         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3863         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3864         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3865         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3866         tbl->i_port_bitmap = 0x1;
3867         *table_item_num = 1;
3868 }
3869
3870 static int
3871 hns3_init_mgr_tbl(struct hns3_hw *hw)
3872 {
3873 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3874         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3875         int table_item_num;
3876         int ret;
3877         int i;
3878
3879         memset(mgr_table, 0, sizeof(mgr_table));
3880         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3881         for (i = 0; i < table_item_num; i++) {
3882                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3883                 if (ret) {
3884                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3885                                      ret);
3886                         return ret;
3887                 }
3888         }
3889
3890         return 0;
3891 }
3892
3893 static void
3894 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3895                         bool en_mc, bool en_bc, int vport_id)
3896 {
3897         if (!param)
3898                 return;
3899
3900         memset(param, 0, sizeof(struct hns3_promisc_param));
3901         if (en_uc)
3902                 param->enable = HNS3_PROMISC_EN_UC;
3903         if (en_mc)
3904                 param->enable |= HNS3_PROMISC_EN_MC;
3905         if (en_bc)
3906                 param->enable |= HNS3_PROMISC_EN_BC;
3907         param->vf_id = vport_id;
3908 }
3909
3910 static int
3911 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3912 {
3913         struct hns3_promisc_cfg_cmd *req;
3914         struct hns3_cmd_desc desc;
3915         int ret;
3916
3917         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3918
3919         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3920         req->vf_id = param->vf_id;
3921         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3922             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3923
3924         ret = hns3_cmd_send(hw, &desc, 1);
3925         if (ret)
3926                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3927
3928         return ret;
3929 }
3930
3931 static int
3932 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3933 {
3934         struct hns3_promisc_param param;
3935         bool en_bc_pmc = true;
3936         uint8_t vf_id;
3937
3938         /*
3939          * In current version VF is not supported when PF is driven by DPDK
3940          * driver, just need to configure parameters for PF vport.
3941          */
3942         vf_id = HNS3_PF_FUNC_ID;
3943
3944         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3945         return hns3_cmd_set_promisc_mode(hw, &param);
3946 }
3947
3948 static int
3949 hns3_promisc_init(struct hns3_hw *hw)
3950 {
3951         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3952         struct hns3_pf *pf = &hns->pf;
3953         struct hns3_promisc_param param;
3954         uint16_t func_id;
3955         int ret;
3956
3957         ret = hns3_set_promisc_mode(hw, false, false);
3958         if (ret) {
3959                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3960                 return ret;
3961         }
3962
3963         /*
3964          * In current version VFs are not supported when PF is driven by DPDK
3965          * driver. After PF has been taken over by DPDK, the original VF will
3966          * be invalid. So, there is a possibility of entry residues. It should
3967          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3968          * during init.
3969          */
3970         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3971                 hns3_promisc_param_init(&param, false, false, false, func_id);
3972                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3973                 if (ret) {
3974                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3975                                         " ret = %d", func_id, ret);
3976                         return ret;
3977                 }
3978         }
3979
3980         return 0;
3981 }
3982
3983 static void
3984 hns3_promisc_uninit(struct hns3_hw *hw)
3985 {
3986         struct hns3_promisc_param param;
3987         uint16_t func_id;
3988         int ret;
3989
3990         func_id = HNS3_PF_FUNC_ID;
3991
3992         /*
3993          * In current version VFs are not supported when PF is driven by
3994          * DPDK driver, and VFs' promisc mode status has been cleared during
3995          * init and their status will not change. So just clear PF's promisc
3996          * mode status during uninit.
3997          */
3998         hns3_promisc_param_init(&param, false, false, false, func_id);
3999         ret = hns3_cmd_set_promisc_mode(hw, &param);
4000         if (ret)
4001                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4002                                 " uninit, ret = %d", ret);
4003 }
4004
4005 static int
4006 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4007 {
4008         bool allmulti = dev->data->all_multicast ? true : false;
4009         struct hns3_adapter *hns = dev->data->dev_private;
4010         struct hns3_hw *hw = &hns->hw;
4011         uint64_t offloads;
4012         int err;
4013         int ret;
4014
4015         rte_spinlock_lock(&hw->lock);
4016         ret = hns3_set_promisc_mode(hw, true, true);
4017         if (ret) {
4018                 rte_spinlock_unlock(&hw->lock);
4019                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4020                          ret);
4021                 return ret;
4022         }
4023
4024         /*
4025          * When promiscuous mode was enabled, disable the vlan filter to let
4026          * all packets coming in in the receiving direction.
4027          */
4028         offloads = dev->data->dev_conf.rxmode.offloads;
4029         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4030                 ret = hns3_enable_vlan_filter(hns, false);
4031                 if (ret) {
4032                         hns3_err(hw, "failed to enable promiscuous mode due to "
4033                                      "failure to disable vlan filter, ret = %d",
4034                                  ret);
4035                         err = hns3_set_promisc_mode(hw, false, allmulti);
4036                         if (err)
4037                                 hns3_err(hw, "failed to restore promiscuous "
4038                                          "status after disable vlan filter "
4039                                          "failed during enabling promiscuous "
4040                                          "mode, ret = %d", ret);
4041                 }
4042         }
4043
4044         rte_spinlock_unlock(&hw->lock);
4045
4046         return ret;
4047 }
4048
4049 static int
4050 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4051 {
4052         bool allmulti = dev->data->all_multicast ? true : false;
4053         struct hns3_adapter *hns = dev->data->dev_private;
4054         struct hns3_hw *hw = &hns->hw;
4055         uint64_t offloads;
4056         int err;
4057         int ret;
4058
4059         /* If now in all_multicast mode, must remain in all_multicast mode. */
4060         rte_spinlock_lock(&hw->lock);
4061         ret = hns3_set_promisc_mode(hw, false, allmulti);
4062         if (ret) {
4063                 rte_spinlock_unlock(&hw->lock);
4064                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4065                          ret);
4066                 return ret;
4067         }
4068         /* when promiscuous mode was disabled, restore the vlan filter status */
4069         offloads = dev->data->dev_conf.rxmode.offloads;
4070         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4071                 ret = hns3_enable_vlan_filter(hns, true);
4072                 if (ret) {
4073                         hns3_err(hw, "failed to disable promiscuous mode due to"
4074                                  " failure to restore vlan filter, ret = %d",
4075                                  ret);
4076                         err = hns3_set_promisc_mode(hw, true, true);
4077                         if (err)
4078                                 hns3_err(hw, "failed to restore promiscuous "
4079                                          "status after enabling vlan filter "
4080                                          "failed during disabling promiscuous "
4081                                          "mode, ret = %d", ret);
4082                 }
4083         }
4084         rte_spinlock_unlock(&hw->lock);
4085
4086         return ret;
4087 }
4088
4089 static int
4090 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4091 {
4092         struct hns3_adapter *hns = dev->data->dev_private;
4093         struct hns3_hw *hw = &hns->hw;
4094         int ret;
4095
4096         if (dev->data->promiscuous)
4097                 return 0;
4098
4099         rte_spinlock_lock(&hw->lock);
4100         ret = hns3_set_promisc_mode(hw, false, true);
4101         rte_spinlock_unlock(&hw->lock);
4102         if (ret)
4103                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4104                          ret);
4105
4106         return ret;
4107 }
4108
4109 static int
4110 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4111 {
4112         struct hns3_adapter *hns = dev->data->dev_private;
4113         struct hns3_hw *hw = &hns->hw;
4114         int ret;
4115
4116         /* If now in promiscuous mode, must remain in all_multicast mode. */
4117         if (dev->data->promiscuous)
4118                 return 0;
4119
4120         rte_spinlock_lock(&hw->lock);
4121         ret = hns3_set_promisc_mode(hw, false, false);
4122         rte_spinlock_unlock(&hw->lock);
4123         if (ret)
4124                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4125                          ret);
4126
4127         return ret;
4128 }
4129
4130 static int
4131 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4132 {
4133         struct hns3_hw *hw = &hns->hw;
4134         bool allmulti = hw->data->all_multicast ? true : false;
4135         int ret;
4136
4137         if (hw->data->promiscuous) {
4138                 ret = hns3_set_promisc_mode(hw, true, true);
4139                 if (ret)
4140                         hns3_err(hw, "failed to restore promiscuous mode, "
4141                                  "ret = %d", ret);
4142                 return ret;
4143         }
4144
4145         ret = hns3_set_promisc_mode(hw, false, allmulti);
4146         if (ret)
4147                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4148                          ret);
4149         return ret;
4150 }
4151
4152 static int
4153 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4154 {
4155         struct hns3_sfp_speed_cmd *resp;
4156         struct hns3_cmd_desc desc;
4157         int ret;
4158
4159         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4160         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4161         ret = hns3_cmd_send(hw, &desc, 1);
4162         if (ret == -EOPNOTSUPP) {
4163                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4164                 return ret;
4165         } else if (ret) {
4166                 hns3_err(hw, "get sfp speed failed %d", ret);
4167                 return ret;
4168         }
4169
4170         *speed = resp->sfp_speed;
4171
4172         return 0;
4173 }
4174
4175 static uint8_t
4176 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4177 {
4178         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4179                 duplex = ETH_LINK_FULL_DUPLEX;
4180
4181         return duplex;
4182 }
4183
4184 static int
4185 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4186 {
4187         struct hns3_mac *mac = &hw->mac;
4188         int ret;
4189
4190         duplex = hns3_check_speed_dup(duplex, speed);
4191         if (mac->link_speed == speed && mac->link_duplex == duplex)
4192                 return 0;
4193
4194         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4195         if (ret)
4196                 return ret;
4197
4198         mac->link_speed = speed;
4199         mac->link_duplex = duplex;
4200
4201         return 0;
4202 }
4203
4204 static int
4205 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4206 {
4207         struct hns3_adapter *hns = eth_dev->data->dev_private;
4208         struct hns3_hw *hw = &hns->hw;
4209         struct hns3_pf *pf = &hns->pf;
4210         uint32_t speed;
4211         int ret;
4212
4213         /* If IMP do not support get SFP/qSFP speed, return directly */
4214         if (!pf->support_sfp_query)
4215                 return 0;
4216
4217         ret = hns3_get_sfp_speed(hw, &speed);
4218         if (ret == -EOPNOTSUPP) {
4219                 pf->support_sfp_query = false;
4220                 return ret;
4221         } else if (ret)
4222                 return ret;
4223
4224         if (speed == ETH_SPEED_NUM_NONE)
4225                 return 0; /* do nothing if no SFP */
4226
4227         /* Config full duplex for SFP */
4228         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4229 }
4230
4231 static int
4232 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4233 {
4234         struct hns3_config_mac_mode_cmd *req;
4235         struct hns3_cmd_desc desc;
4236         uint32_t loop_en = 0;
4237         uint8_t val = 0;
4238         int ret;
4239
4240         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4241
4242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4243         if (enable)
4244                 val = 1;
4245         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4246         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4247         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4248         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4249         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4250         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4251         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4252         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4253         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4254         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4255
4256         /*
4257          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4258          * when receiving frames. Otherwise, CRC will be stripped.
4259          */
4260         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4261                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4262         else
4263                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4264         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4265         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4266         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4267         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4268
4269         ret = hns3_cmd_send(hw, &desc, 1);
4270         if (ret)
4271                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4272
4273         return ret;
4274 }
4275
4276 static int
4277 hns3_get_mac_link_status(struct hns3_hw *hw)
4278 {
4279         struct hns3_link_status_cmd *req;
4280         struct hns3_cmd_desc desc;
4281         int link_status;
4282         int ret;
4283
4284         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4285         ret = hns3_cmd_send(hw, &desc, 1);
4286         if (ret) {
4287                 hns3_err(hw, "get link status cmd failed %d", ret);
4288                 return ETH_LINK_DOWN;
4289         }
4290
4291         req = (struct hns3_link_status_cmd *)desc.data;
4292         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4293
4294         return !!link_status;
4295 }
4296
4297 void
4298 hns3_update_link_status(struct hns3_hw *hw)
4299 {
4300         int state;
4301
4302         state = hns3_get_mac_link_status(hw);
4303         if (state != hw->mac.link_status) {
4304                 hw->mac.link_status = state;
4305                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4306         }
4307 }
4308
4309 static void
4310 hns3_service_handler(void *param)
4311 {
4312         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4313         struct hns3_adapter *hns = eth_dev->data->dev_private;
4314         struct hns3_hw *hw = &hns->hw;
4315
4316         if (!hns3_is_reset_pending(hns)) {
4317                 hns3_update_speed_duplex(eth_dev);
4318                 hns3_update_link_status(hw);
4319         } else
4320                 hns3_warn(hw, "Cancel the query when reset is pending");
4321
4322         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4323 }
4324
4325 static int
4326 hns3_init_hardware(struct hns3_adapter *hns)
4327 {
4328         struct hns3_hw *hw = &hns->hw;
4329         int ret;
4330
4331         ret = hns3_map_tqp(hw);
4332         if (ret) {
4333                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4334                 return ret;
4335         }
4336
4337         ret = hns3_init_umv_space(hw);
4338         if (ret) {
4339                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4340                 return ret;
4341         }
4342
4343         ret = hns3_mac_init(hw);
4344         if (ret) {
4345                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4346                 goto err_mac_init;
4347         }
4348
4349         ret = hns3_init_mgr_tbl(hw);
4350         if (ret) {
4351                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4352                 goto err_mac_init;
4353         }
4354
4355         ret = hns3_promisc_init(hw);
4356         if (ret) {
4357                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4358                              ret);
4359                 goto err_mac_init;
4360         }
4361
4362         ret = hns3_init_vlan_config(hns);
4363         if (ret) {
4364                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4365                 goto err_mac_init;
4366         }
4367
4368         ret = hns3_dcb_init(hw);
4369         if (ret) {
4370                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4371                 goto err_mac_init;
4372         }
4373
4374         ret = hns3_init_fd_config(hns);
4375         if (ret) {
4376                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4377                 goto err_mac_init;
4378         }
4379
4380         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4381         if (ret) {
4382                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4383                 goto err_mac_init;
4384         }
4385
4386         ret = hns3_config_gro(hw, false);
4387         if (ret) {
4388                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4389                 goto err_mac_init;
4390         }
4391
4392         /*
4393          * In the initialization clearing the all hardware mapping relationship
4394          * configurations between queues and interrupt vectors is needed, so
4395          * some error caused by the residual configurations, such as the
4396          * unexpected interrupt, can be avoid.
4397          */
4398         ret = hns3_init_ring_with_vector(hw);
4399         if (ret) {
4400                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4401                 goto err_mac_init;
4402         }
4403
4404         return 0;
4405
4406 err_mac_init:
4407         hns3_uninit_umv_space(hw);
4408         return ret;
4409 }
4410
4411 static int
4412 hns3_clear_hw(struct hns3_hw *hw)
4413 {
4414         struct hns3_cmd_desc desc;
4415         int ret;
4416
4417         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4418
4419         ret = hns3_cmd_send(hw, &desc, 1);
4420         if (ret && ret != -EOPNOTSUPP)
4421                 return ret;
4422
4423         return 0;
4424 }
4425
4426 static int
4427 hns3_init_pf(struct rte_eth_dev *eth_dev)
4428 {
4429         struct rte_device *dev = eth_dev->device;
4430         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4431         struct hns3_adapter *hns = eth_dev->data->dev_private;
4432         struct hns3_hw *hw = &hns->hw;
4433         int ret;
4434
4435         PMD_INIT_FUNC_TRACE();
4436
4437         /* Get hardware io base address from pcie BAR2 IO space */
4438         hw->io_base = pci_dev->mem_resource[2].addr;
4439
4440         /* Firmware command queue initialize */
4441         ret = hns3_cmd_init_queue(hw);
4442         if (ret) {
4443                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4444                 goto err_cmd_init_queue;
4445         }
4446
4447         hns3_clear_all_event_cause(hw);
4448
4449         /* Firmware command initialize */
4450         ret = hns3_cmd_init(hw);
4451         if (ret) {
4452                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4453                 goto err_cmd_init;
4454         }
4455
4456         /*
4457          * To ensure that the hardware environment is clean during
4458          * initialization, the driver actively clear the hardware environment
4459          * during initialization, including PF and corresponding VFs' vlan, mac,
4460          * flow table configurations, etc.
4461          */
4462         ret = hns3_clear_hw(hw);
4463         if (ret) {
4464                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4465                 goto err_cmd_init;
4466         }
4467
4468         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4469                                          hns3_interrupt_handler,
4470                                          eth_dev);
4471         if (ret) {
4472                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4473                 goto err_intr_callback_register;
4474         }
4475
4476         /* Enable interrupt */
4477         rte_intr_enable(&pci_dev->intr_handle);
4478         hns3_pf_enable_irq0(hw);
4479
4480         /* Get configuration */
4481         ret = hns3_get_configuration(hw);
4482         if (ret) {
4483                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4484                 goto err_get_config;
4485         }
4486
4487         ret = hns3_init_hardware(hns);
4488         if (ret) {
4489                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4490                 goto err_get_config;
4491         }
4492
4493         /* Initialize flow director filter list & hash */
4494         ret = hns3_fdir_filter_init(hns);
4495         if (ret) {
4496                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4497                 goto err_hw_init;
4498         }
4499
4500         hns3_set_default_rss_args(hw);
4501
4502         ret = hns3_enable_hw_error_intr(hns, true);
4503         if (ret) {
4504                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4505                              ret);
4506                 goto err_fdir;
4507         }
4508
4509         return 0;
4510
4511 err_fdir:
4512         hns3_fdir_filter_uninit(hns);
4513 err_hw_init:
4514         hns3_uninit_umv_space(hw);
4515
4516 err_get_config:
4517         hns3_pf_disable_irq0(hw);
4518         rte_intr_disable(&pci_dev->intr_handle);
4519         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4520                              eth_dev);
4521 err_intr_callback_register:
4522 err_cmd_init:
4523         hns3_cmd_uninit(hw);
4524         hns3_cmd_destroy_queue(hw);
4525 err_cmd_init_queue:
4526         hw->io_base = NULL;
4527
4528         return ret;
4529 }
4530
4531 static void
4532 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4533 {
4534         struct hns3_adapter *hns = eth_dev->data->dev_private;
4535         struct rte_device *dev = eth_dev->device;
4536         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4537         struct hns3_hw *hw = &hns->hw;
4538
4539         PMD_INIT_FUNC_TRACE();
4540
4541         hns3_enable_hw_error_intr(hns, false);
4542         hns3_rss_uninit(hns);
4543         (void)hns3_config_gro(hw, false);
4544         hns3_promisc_uninit(hw);
4545         hns3_fdir_filter_uninit(hns);
4546         hns3_uninit_umv_space(hw);
4547         hns3_pf_disable_irq0(hw);
4548         rte_intr_disable(&pci_dev->intr_handle);
4549         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4550                              eth_dev);
4551         hns3_cmd_uninit(hw);
4552         hns3_cmd_destroy_queue(hw);
4553         hw->io_base = NULL;
4554 }
4555
4556 static int
4557 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4558 {
4559         struct hns3_hw *hw = &hns->hw;
4560         int ret;
4561
4562         ret = hns3_dcb_cfg_update(hns);
4563         if (ret)
4564                 return ret;
4565
4566         /* Enable queues */
4567         ret = hns3_start_queues(hns, reset_queue);
4568         if (ret) {
4569                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4570                 return ret;
4571         }
4572
4573         /* Enable MAC */
4574         ret = hns3_cfg_mac_mode(hw, true);
4575         if (ret) {
4576                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4577                 goto err_config_mac_mode;
4578         }
4579         return 0;
4580
4581 err_config_mac_mode:
4582         hns3_stop_queues(hns, true);
4583         return ret;
4584 }
4585
4586 static int
4587 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4588 {
4589         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4591         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4592         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4593         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4594         uint32_t intr_vector;
4595         uint16_t q_id;
4596         int ret;
4597
4598         if (dev->data->dev_conf.intr_conf.rxq == 0)
4599                 return 0;
4600
4601         /* disable uio/vfio intr/eventfd mapping */
4602         rte_intr_disable(intr_handle);
4603
4604         /* check and configure queue intr-vector mapping */
4605         if (rte_intr_cap_multiple(intr_handle) ||
4606             !RTE_ETH_DEV_SRIOV(dev).active) {
4607                 intr_vector = hw->used_rx_queues;
4608                 /* creates event fd for each intr vector when MSIX is used */
4609                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4610                         return -EINVAL;
4611         }
4612         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4613                 intr_handle->intr_vec =
4614                         rte_zmalloc("intr_vec",
4615                                     hw->used_rx_queues * sizeof(int), 0);
4616                 if (intr_handle->intr_vec == NULL) {
4617                         hns3_err(hw, "Failed to allocate %d rx_queues"
4618                                      " intr_vec", hw->used_rx_queues);
4619                         ret = -ENOMEM;
4620                         goto alloc_intr_vec_error;
4621                 }
4622         }
4623
4624         if (rte_intr_allow_others(intr_handle)) {
4625                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4626                 base = RTE_INTR_VEC_RXTX_OFFSET;
4627         }
4628         if (rte_intr_dp_is_en(intr_handle)) {
4629                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4630                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4631                                                          HNS3_RING_TYPE_RX,
4632                                                          q_id);
4633                         if (ret)
4634                                 goto bind_vector_error;
4635                         intr_handle->intr_vec[q_id] = vec;
4636                         if (vec < base + intr_handle->nb_efd - 1)
4637                                 vec++;
4638                 }
4639         }
4640         rte_intr_enable(intr_handle);
4641         return 0;
4642
4643 bind_vector_error:
4644         rte_intr_efd_disable(intr_handle);
4645         if (intr_handle->intr_vec) {
4646                 free(intr_handle->intr_vec);
4647                 intr_handle->intr_vec = NULL;
4648         }
4649         return ret;
4650 alloc_intr_vec_error:
4651         rte_intr_efd_disable(intr_handle);
4652         return ret;
4653 }
4654
4655 static int
4656 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4657 {
4658         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4659         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4660         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4661         uint16_t q_id;
4662         int ret;
4663
4664         if (dev->data->dev_conf.intr_conf.rxq == 0)
4665                 return 0;
4666
4667         if (rte_intr_dp_is_en(intr_handle)) {
4668                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4669                         ret = hns3_bind_ring_with_vector(hw,
4670                                         intr_handle->intr_vec[q_id], true,
4671                                         HNS3_RING_TYPE_RX, q_id);
4672                         if (ret)
4673                                 return ret;
4674                 }
4675         }
4676
4677         return 0;
4678 }
4679
4680 static void
4681 hns3_restore_filter(struct rte_eth_dev *dev)
4682 {
4683         hns3_restore_rss_filter(dev);
4684 }
4685
4686 static int
4687 hns3_dev_start(struct rte_eth_dev *dev)
4688 {
4689         struct hns3_adapter *hns = dev->data->dev_private;
4690         struct hns3_hw *hw = &hns->hw;
4691         int ret;
4692
4693         PMD_INIT_FUNC_TRACE();
4694         if (rte_atomic16_read(&hw->reset.resetting))
4695                 return -EBUSY;
4696
4697         rte_spinlock_lock(&hw->lock);
4698         hw->adapter_state = HNS3_NIC_STARTING;
4699
4700         ret = hns3_do_start(hns, true);
4701         if (ret) {
4702                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4703                 rte_spinlock_unlock(&hw->lock);
4704                 return ret;
4705         }
4706         ret = hns3_map_rx_interrupt(dev);
4707         if (ret) {
4708                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4709                 rte_spinlock_unlock(&hw->lock);
4710                 return ret;
4711         }
4712
4713         hw->adapter_state = HNS3_NIC_STARTED;
4714         rte_spinlock_unlock(&hw->lock);
4715
4716         hns3_set_rxtx_function(dev);
4717         hns3_mp_req_start_rxtx(dev);
4718         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4719
4720         hns3_restore_filter(dev);
4721
4722         /* Enable interrupt of all rx queues before enabling queues */
4723         hns3_dev_all_rx_queue_intr_enable(hw, true);
4724         /*
4725          * When finished the initialization, enable queues to receive/transmit
4726          * packets.
4727          */
4728         hns3_enable_all_queues(hw, true);
4729
4730         hns3_info(hw, "hns3 dev start successful!");
4731         return 0;
4732 }
4733
4734 static int
4735 hns3_do_stop(struct hns3_adapter *hns)
4736 {
4737         struct hns3_hw *hw = &hns->hw;
4738         bool reset_queue;
4739         int ret;
4740
4741         ret = hns3_cfg_mac_mode(hw, false);
4742         if (ret)
4743                 return ret;
4744         hw->mac.link_status = ETH_LINK_DOWN;
4745
4746         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4747                 hns3_configure_all_mac_addr(hns, true);
4748                 reset_queue = true;
4749         } else
4750                 reset_queue = false;
4751         hw->mac.default_addr_setted = false;
4752         return hns3_stop_queues(hns, reset_queue);
4753 }
4754
4755 static void
4756 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4757 {
4758         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4759         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4760         struct hns3_adapter *hns = dev->data->dev_private;
4761         struct hns3_hw *hw = &hns->hw;
4762         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4763         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4764         uint16_t q_id;
4765
4766         if (dev->data->dev_conf.intr_conf.rxq == 0)
4767                 return;
4768
4769         /* unmap the ring with vector */
4770         if (rte_intr_allow_others(intr_handle)) {
4771                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4772                 base = RTE_INTR_VEC_RXTX_OFFSET;
4773         }
4774         if (rte_intr_dp_is_en(intr_handle)) {
4775                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4776                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4777                                                          HNS3_RING_TYPE_RX,
4778                                                          q_id);
4779                         if (vec < base + intr_handle->nb_efd - 1)
4780                                 vec++;
4781                 }
4782         }
4783         /* Clean datapath event and queue/vec mapping */
4784         rte_intr_efd_disable(intr_handle);
4785         if (intr_handle->intr_vec) {
4786                 rte_free(intr_handle->intr_vec);
4787                 intr_handle->intr_vec = NULL;
4788         }
4789 }
4790
4791 static void
4792 hns3_dev_stop(struct rte_eth_dev *dev)
4793 {
4794         struct hns3_adapter *hns = dev->data->dev_private;
4795         struct hns3_hw *hw = &hns->hw;
4796
4797         PMD_INIT_FUNC_TRACE();
4798
4799         hw->adapter_state = HNS3_NIC_STOPPING;
4800         hns3_set_rxtx_function(dev);
4801         rte_wmb();
4802         /* Disable datapath on secondary process. */
4803         hns3_mp_req_stop_rxtx(dev);
4804         /* Prevent crashes when queues are still in use. */
4805         rte_delay_ms(hw->tqps_num);
4806
4807         rte_spinlock_lock(&hw->lock);
4808         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4809                 hns3_do_stop(hns);
4810                 hns3_unmap_rx_interrupt(dev);
4811                 hns3_dev_release_mbufs(hns);
4812                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4813         }
4814         rte_eal_alarm_cancel(hns3_service_handler, dev);
4815         rte_spinlock_unlock(&hw->lock);
4816 }
4817
4818 static void
4819 hns3_dev_close(struct rte_eth_dev *eth_dev)
4820 {
4821         struct hns3_adapter *hns = eth_dev->data->dev_private;
4822         struct hns3_hw *hw = &hns->hw;
4823
4824         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4825                 rte_free(eth_dev->process_private);
4826                 eth_dev->process_private = NULL;
4827                 return;
4828         }
4829
4830         if (hw->adapter_state == HNS3_NIC_STARTED)
4831                 hns3_dev_stop(eth_dev);
4832
4833         hw->adapter_state = HNS3_NIC_CLOSING;
4834         hns3_reset_abort(hns);
4835         hw->adapter_state = HNS3_NIC_CLOSED;
4836
4837         hns3_configure_all_mc_mac_addr(hns, true);
4838         hns3_remove_all_vlan_table(hns);
4839         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4840         hns3_uninit_pf(eth_dev);
4841         hns3_free_all_queues(eth_dev);
4842         rte_free(hw->reset.wait_data);
4843         rte_free(eth_dev->process_private);
4844         eth_dev->process_private = NULL;
4845         hns3_mp_uninit_primary();
4846         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4847 }
4848
4849 static int
4850 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4851 {
4852         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4854
4855         fc_conf->pause_time = pf->pause_time;
4856
4857         /* return fc current mode */
4858         switch (hw->current_mode) {
4859         case HNS3_FC_FULL:
4860                 fc_conf->mode = RTE_FC_FULL;
4861                 break;
4862         case HNS3_FC_TX_PAUSE:
4863                 fc_conf->mode = RTE_FC_TX_PAUSE;
4864                 break;
4865         case HNS3_FC_RX_PAUSE:
4866                 fc_conf->mode = RTE_FC_RX_PAUSE;
4867                 break;
4868         case HNS3_FC_NONE:
4869         default:
4870                 fc_conf->mode = RTE_FC_NONE;
4871                 break;
4872         }
4873
4874         return 0;
4875 }
4876
4877 static void
4878 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4879 {
4880         switch (mode) {
4881         case RTE_FC_NONE:
4882                 hw->requested_mode = HNS3_FC_NONE;
4883                 break;
4884         case RTE_FC_RX_PAUSE:
4885                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4886                 break;
4887         case RTE_FC_TX_PAUSE:
4888                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4889                 break;
4890         case RTE_FC_FULL:
4891                 hw->requested_mode = HNS3_FC_FULL;
4892                 break;
4893         default:
4894                 hw->requested_mode = HNS3_FC_NONE;
4895                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4896                           "configured to RTE_FC_NONE", mode);
4897                 break;
4898         }
4899 }
4900
4901 static int
4902 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4903 {
4904         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4905         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4906         int ret;
4907
4908         if (fc_conf->high_water || fc_conf->low_water ||
4909             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4910                 hns3_err(hw, "Unsupported flow control settings specified, "
4911                          "high_water(%u), low_water(%u), send_xon(%u) and "
4912                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4913                          fc_conf->high_water, fc_conf->low_water,
4914                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4915                 return -EINVAL;
4916         }
4917         if (fc_conf->autoneg) {
4918                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4919                 return -EINVAL;
4920         }
4921         if (!fc_conf->pause_time) {
4922                 hns3_err(hw, "Invalid pause time %d setting.",
4923                          fc_conf->pause_time);
4924                 return -EINVAL;
4925         }
4926
4927         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4928             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4929                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4930                          "current_fc_status = %d", hw->current_fc_status);
4931                 return -EOPNOTSUPP;
4932         }
4933
4934         hns3_get_fc_mode(hw, fc_conf->mode);
4935         if (hw->requested_mode == hw->current_mode &&
4936             pf->pause_time == fc_conf->pause_time)
4937                 return 0;
4938
4939         rte_spinlock_lock(&hw->lock);
4940         ret = hns3_fc_enable(dev, fc_conf);
4941         rte_spinlock_unlock(&hw->lock);
4942
4943         return ret;
4944 }
4945
4946 static int
4947 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4948                             struct rte_eth_pfc_conf *pfc_conf)
4949 {
4950         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4951         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4952         uint8_t priority;
4953         int ret;
4954
4955         if (!hns3_dev_dcb_supported(hw)) {
4956                 hns3_err(hw, "This port does not support dcb configurations.");
4957                 return -EOPNOTSUPP;
4958         }
4959
4960         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4961             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4962                 hns3_err(hw, "Unsupported flow control settings specified, "
4963                          "high_water(%u), low_water(%u), send_xon(%u) and "
4964                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4965                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4966                          pfc_conf->fc.send_xon,
4967                          pfc_conf->fc.mac_ctrl_frame_fwd);
4968                 return -EINVAL;
4969         }
4970         if (pfc_conf->fc.autoneg) {
4971                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4972                 return -EINVAL;
4973         }
4974         if (pfc_conf->fc.pause_time == 0) {
4975                 hns3_err(hw, "Invalid pause time %d setting.",
4976                          pfc_conf->fc.pause_time);
4977                 return -EINVAL;
4978         }
4979
4980         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4981             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4982                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4983                              "current_fc_status = %d", hw->current_fc_status);
4984                 return -EOPNOTSUPP;
4985         }
4986
4987         priority = pfc_conf->priority;
4988         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4989         if (hw->dcb_info.pfc_en & BIT(priority) &&
4990             hw->requested_mode == hw->current_mode &&
4991             pfc_conf->fc.pause_time == pf->pause_time)
4992                 return 0;
4993
4994         rte_spinlock_lock(&hw->lock);
4995         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4996         rte_spinlock_unlock(&hw->lock);
4997
4998         return ret;
4999 }
5000
5001 static int
5002 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5003 {
5004         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5005         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5006         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5007         int i;
5008
5009         rte_spinlock_lock(&hw->lock);
5010         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5011                 dcb_info->nb_tcs = pf->local_max_tc;
5012         else
5013                 dcb_info->nb_tcs = 1;
5014
5015         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5016                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5017         for (i = 0; i < dcb_info->nb_tcs; i++)
5018                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5019
5020         for (i = 0; i < hw->num_tc; i++) {
5021                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5022                 dcb_info->tc_queue.tc_txq[0][i].base =
5023                                                 hw->tc_queue[i].tqp_offset;
5024                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5025                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5026                                                 hw->tc_queue[i].tqp_count;
5027         }
5028         rte_spinlock_unlock(&hw->lock);
5029
5030         return 0;
5031 }
5032
5033 static int
5034 hns3_reinit_dev(struct hns3_adapter *hns)
5035 {
5036         struct hns3_hw *hw = &hns->hw;
5037         int ret;
5038
5039         ret = hns3_cmd_init(hw);
5040         if (ret) {
5041                 hns3_err(hw, "Failed to init cmd: %d", ret);
5042                 return ret;
5043         }
5044
5045         ret = hns3_reset_all_queues(hns);
5046         if (ret) {
5047                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5048                 return ret;
5049         }
5050
5051         ret = hns3_init_hardware(hns);
5052         if (ret) {
5053                 hns3_err(hw, "Failed to init hardware: %d", ret);
5054                 return ret;
5055         }
5056
5057         ret = hns3_enable_hw_error_intr(hns, true);
5058         if (ret) {
5059                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5060                              ret);
5061                 return ret;
5062         }
5063         hns3_info(hw, "Reset done, driver initialization finished.");
5064
5065         return 0;
5066 }
5067
5068 static bool
5069 is_pf_reset_done(struct hns3_hw *hw)
5070 {
5071         uint32_t val, reg, reg_bit;
5072
5073         switch (hw->reset.level) {
5074         case HNS3_IMP_RESET:
5075                 reg = HNS3_GLOBAL_RESET_REG;
5076                 reg_bit = HNS3_IMP_RESET_BIT;
5077                 break;
5078         case HNS3_GLOBAL_RESET:
5079                 reg = HNS3_GLOBAL_RESET_REG;
5080                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5081                 break;
5082         case HNS3_FUNC_RESET:
5083                 reg = HNS3_FUN_RST_ING;
5084                 reg_bit = HNS3_FUN_RST_ING_B;
5085                 break;
5086         case HNS3_FLR_RESET:
5087         default:
5088                 hns3_err(hw, "Wait for unsupported reset level: %d",
5089                          hw->reset.level);
5090                 return true;
5091         }
5092         val = hns3_read_dev(hw, reg);
5093         if (hns3_get_bit(val, reg_bit))
5094                 return false;
5095         else
5096                 return true;
5097 }
5098
5099 bool
5100 hns3_is_reset_pending(struct hns3_adapter *hns)
5101 {
5102         struct hns3_hw *hw = &hns->hw;
5103         enum hns3_reset_level reset;
5104
5105         hns3_check_event_cause(hns, NULL);
5106         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5107         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5108                 hns3_warn(hw, "High level reset %d is pending", reset);
5109                 return true;
5110         }
5111         reset = hns3_get_reset_level(hns, &hw->reset.request);
5112         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5113                 hns3_warn(hw, "High level reset %d is request", reset);
5114                 return true;
5115         }
5116         return false;
5117 }
5118
5119 static int
5120 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5121 {
5122         struct hns3_hw *hw = &hns->hw;
5123         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5124         struct timeval tv;
5125
5126         if (wait_data->result == HNS3_WAIT_SUCCESS)
5127                 return 0;
5128         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5129                 gettimeofday(&tv, NULL);
5130                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5131                           tv.tv_sec, tv.tv_usec);
5132                 return -ETIME;
5133         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5134                 return -EAGAIN;
5135
5136         wait_data->hns = hns;
5137         wait_data->check_completion = is_pf_reset_done;
5138         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5139                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5140         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5141         wait_data->count = HNS3_RESET_WAIT_CNT;
5142         wait_data->result = HNS3_WAIT_REQUEST;
5143         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5144         return -EAGAIN;
5145 }
5146
5147 static int
5148 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5149 {
5150         struct hns3_cmd_desc desc;
5151         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5152
5153         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5154         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5155         req->fun_reset_vfid = func_id;
5156
5157         return hns3_cmd_send(hw, &desc, 1);
5158 }
5159
5160 static int
5161 hns3_imp_reset_cmd(struct hns3_hw *hw)
5162 {
5163         struct hns3_cmd_desc desc;
5164
5165         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5166         desc.data[0] = 0xeedd;
5167
5168         return hns3_cmd_send(hw, &desc, 1);
5169 }
5170
5171 static void
5172 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5173 {
5174         struct hns3_hw *hw = &hns->hw;
5175         struct timeval tv;
5176         uint32_t val;
5177
5178         gettimeofday(&tv, NULL);
5179         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5180             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5181                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5182                           tv.tv_sec, tv.tv_usec);
5183                 return;
5184         }
5185
5186         switch (reset_level) {
5187         case HNS3_IMP_RESET:
5188                 hns3_imp_reset_cmd(hw);
5189                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5190                           tv.tv_sec, tv.tv_usec);
5191                 break;
5192         case HNS3_GLOBAL_RESET:
5193                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5194                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5195                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5196                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5197                           tv.tv_sec, tv.tv_usec);
5198                 break;
5199         case HNS3_FUNC_RESET:
5200                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5201                           tv.tv_sec, tv.tv_usec);
5202                 /* schedule again to check later */
5203                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5204                 hns3_schedule_reset(hns);
5205                 break;
5206         default:
5207                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5208                 return;
5209         }
5210         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5211 }
5212
5213 static enum hns3_reset_level
5214 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5215 {
5216         struct hns3_hw *hw = &hns->hw;
5217         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5218
5219         /* Return the highest priority reset level amongst all */
5220         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5221                 reset_level = HNS3_IMP_RESET;
5222         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5223                 reset_level = HNS3_GLOBAL_RESET;
5224         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5225                 reset_level = HNS3_FUNC_RESET;
5226         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5227                 reset_level = HNS3_FLR_RESET;
5228
5229         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5230                 return HNS3_NONE_RESET;
5231
5232         return reset_level;
5233 }
5234
5235 static int
5236 hns3_prepare_reset(struct hns3_adapter *hns)
5237 {
5238         struct hns3_hw *hw = &hns->hw;
5239         uint32_t reg_val;
5240         int ret;
5241
5242         switch (hw->reset.level) {
5243         case HNS3_FUNC_RESET:
5244                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5245                 if (ret)
5246                         return ret;
5247
5248                 /*
5249                  * After performaning pf reset, it is not necessary to do the
5250                  * mailbox handling or send any command to firmware, because
5251                  * any mailbox handling or command to firmware is only valid
5252                  * after hns3_cmd_init is called.
5253                  */
5254                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5255                 hw->reset.stats.request_cnt++;
5256                 break;
5257         case HNS3_IMP_RESET:
5258                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5259                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5260                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5261                 break;
5262         default:
5263                 break;
5264         }
5265         return 0;
5266 }
5267
5268 static int
5269 hns3_set_rst_done(struct hns3_hw *hw)
5270 {
5271         struct hns3_pf_rst_done_cmd *req;
5272         struct hns3_cmd_desc desc;
5273
5274         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5275         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5276         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5277         return hns3_cmd_send(hw, &desc, 1);
5278 }
5279
5280 static int
5281 hns3_stop_service(struct hns3_adapter *hns)
5282 {
5283         struct hns3_hw *hw = &hns->hw;
5284         struct rte_eth_dev *eth_dev;
5285
5286         eth_dev = &rte_eth_devices[hw->data->port_id];
5287         if (hw->adapter_state == HNS3_NIC_STARTED)
5288                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5289         hw->mac.link_status = ETH_LINK_DOWN;
5290
5291         hns3_set_rxtx_function(eth_dev);
5292         rte_wmb();
5293         /* Disable datapath on secondary process. */
5294         hns3_mp_req_stop_rxtx(eth_dev);
5295         rte_delay_ms(hw->tqps_num);
5296
5297         rte_spinlock_lock(&hw->lock);
5298         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5299             hw->adapter_state == HNS3_NIC_STOPPING) {
5300                 hns3_do_stop(hns);
5301                 hw->reset.mbuf_deferred_free = true;
5302         } else
5303                 hw->reset.mbuf_deferred_free = false;
5304
5305         /*
5306          * It is cumbersome for hardware to pick-and-choose entries for deletion
5307          * from table space. Hence, for function reset software intervention is
5308          * required to delete the entries
5309          */
5310         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5311                 hns3_configure_all_mc_mac_addr(hns, true);
5312         rte_spinlock_unlock(&hw->lock);
5313
5314         return 0;
5315 }
5316
5317 static int
5318 hns3_start_service(struct hns3_adapter *hns)
5319 {
5320         struct hns3_hw *hw = &hns->hw;
5321         struct rte_eth_dev *eth_dev;
5322
5323         if (hw->reset.level == HNS3_IMP_RESET ||
5324             hw->reset.level == HNS3_GLOBAL_RESET)
5325                 hns3_set_rst_done(hw);
5326         eth_dev = &rte_eth_devices[hw->data->port_id];
5327         hns3_set_rxtx_function(eth_dev);
5328         hns3_mp_req_start_rxtx(eth_dev);
5329         if (hw->adapter_state == HNS3_NIC_STARTED) {
5330                 hns3_service_handler(eth_dev);
5331
5332                 /* Enable interrupt of all rx queues before enabling queues */
5333                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5334                 /*
5335                  * When finished the initialization, enable queues to receive
5336                  * and transmit packets.
5337                  */
5338                 hns3_enable_all_queues(hw, true);
5339         }
5340
5341         return 0;
5342 }
5343
5344 static int
5345 hns3_restore_conf(struct hns3_adapter *hns)
5346 {
5347         struct hns3_hw *hw = &hns->hw;
5348         int ret;
5349
5350         ret = hns3_configure_all_mac_addr(hns, false);
5351         if (ret)
5352                 return ret;
5353
5354         ret = hns3_configure_all_mc_mac_addr(hns, false);
5355         if (ret)
5356                 goto err_mc_mac;
5357
5358         ret = hns3_dev_promisc_restore(hns);
5359         if (ret)
5360                 goto err_promisc;
5361
5362         ret = hns3_restore_vlan_table(hns);
5363         if (ret)
5364                 goto err_promisc;
5365
5366         ret = hns3_restore_vlan_conf(hns);
5367         if (ret)
5368                 goto err_promisc;
5369
5370         ret = hns3_restore_all_fdir_filter(hns);
5371         if (ret)
5372                 goto err_promisc;
5373
5374         ret = hns3_restore_rx_interrupt(hw);
5375         if (ret)
5376                 goto err_promisc;
5377
5378         ret = hns3_restore_gro_conf(hw);
5379         if (ret)
5380                 goto err_promisc;
5381
5382         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5383                 ret = hns3_do_start(hns, false);
5384                 if (ret)
5385                         goto err_promisc;
5386                 hns3_info(hw, "hns3 dev restart successful!");
5387         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5388                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5389         return 0;
5390
5391 err_promisc:
5392         hns3_configure_all_mc_mac_addr(hns, true);
5393 err_mc_mac:
5394         hns3_configure_all_mac_addr(hns, true);
5395         return ret;
5396 }
5397
5398 static void
5399 hns3_reset_service(void *param)
5400 {
5401         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5402         struct hns3_hw *hw = &hns->hw;
5403         enum hns3_reset_level reset_level;
5404         struct timeval tv_delta;
5405         struct timeval tv_start;
5406         struct timeval tv;
5407         uint64_t msec;
5408         int ret;
5409
5410         /*
5411          * The interrupt is not triggered within the delay time.
5412          * The interrupt may have been lost. It is necessary to handle
5413          * the interrupt to recover from the error.
5414          */
5415         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5416                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5417                 hns3_err(hw, "Handling interrupts in delayed tasks");
5418                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5419                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5420                 if (reset_level == HNS3_NONE_RESET) {
5421                         hns3_err(hw, "No reset level is set, try IMP reset");
5422                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5423                 }
5424         }
5425         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5426
5427         /*
5428          * Check if there is any ongoing reset in the hardware. This status can
5429          * be checked from reset_pending. If there is then, we need to wait for
5430          * hardware to complete reset.
5431          *    a. If we are able to figure out in reasonable time that hardware
5432          *       has fully resetted then, we can proceed with driver, client
5433          *       reset.
5434          *    b. else, we can come back later to check this status so re-sched
5435          *       now.
5436          */
5437         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5438         if (reset_level != HNS3_NONE_RESET) {
5439                 gettimeofday(&tv_start, NULL);
5440                 ret = hns3_reset_process(hns, reset_level);
5441                 gettimeofday(&tv, NULL);
5442                 timersub(&tv, &tv_start, &tv_delta);
5443                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5444                        tv_delta.tv_usec / USEC_PER_MSEC;
5445                 if (msec > HNS3_RESET_PROCESS_MS)
5446                         hns3_err(hw, "%d handle long time delta %" PRIx64
5447                                      " ms time=%ld.%.6ld",
5448                                  hw->reset.level, msec,
5449                                  tv.tv_sec, tv.tv_usec);
5450                 if (ret == -EAGAIN)
5451                         return;
5452         }
5453
5454         /* Check if we got any *new* reset requests to be honored */
5455         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5456         if (reset_level != HNS3_NONE_RESET)
5457                 hns3_msix_process(hns, reset_level);
5458 }
5459
5460 static const struct eth_dev_ops hns3_eth_dev_ops = {
5461         .dev_start          = hns3_dev_start,
5462         .dev_stop           = hns3_dev_stop,
5463         .dev_close          = hns3_dev_close,
5464         .promiscuous_enable = hns3_dev_promiscuous_enable,
5465         .promiscuous_disable = hns3_dev_promiscuous_disable,
5466         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5467         .allmulticast_disable = hns3_dev_allmulticast_disable,
5468         .mtu_set            = hns3_dev_mtu_set,
5469         .stats_get          = hns3_stats_get,
5470         .stats_reset        = hns3_stats_reset,
5471         .xstats_get         = hns3_dev_xstats_get,
5472         .xstats_get_names   = hns3_dev_xstats_get_names,
5473         .xstats_reset       = hns3_dev_xstats_reset,
5474         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5475         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5476         .dev_infos_get          = hns3_dev_infos_get,
5477         .fw_version_get         = hns3_fw_version_get,
5478         .rx_queue_setup         = hns3_rx_queue_setup,
5479         .tx_queue_setup         = hns3_tx_queue_setup,
5480         .rx_queue_release       = hns3_dev_rx_queue_release,
5481         .tx_queue_release       = hns3_dev_tx_queue_release,
5482         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5483         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5484         .rxq_info_get           = hns3_rxq_info_get,
5485         .txq_info_get           = hns3_txq_info_get,
5486         .dev_configure          = hns3_dev_configure,
5487         .flow_ctrl_get          = hns3_flow_ctrl_get,
5488         .flow_ctrl_set          = hns3_flow_ctrl_set,
5489         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5490         .mac_addr_add           = hns3_add_mac_addr,
5491         .mac_addr_remove        = hns3_remove_mac_addr,
5492         .mac_addr_set           = hns3_set_default_mac_addr,
5493         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5494         .link_update            = hns3_dev_link_update,
5495         .rss_hash_update        = hns3_dev_rss_hash_update,
5496         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5497         .reta_update            = hns3_dev_rss_reta_update,
5498         .reta_query             = hns3_dev_rss_reta_query,
5499         .filter_ctrl            = hns3_dev_filter_ctrl,
5500         .vlan_filter_set        = hns3_vlan_filter_set,
5501         .vlan_tpid_set          = hns3_vlan_tpid_set,
5502         .vlan_offload_set       = hns3_vlan_offload_set,
5503         .vlan_pvid_set          = hns3_vlan_pvid_set,
5504         .get_reg                = hns3_get_regs,
5505         .get_dcb_info           = hns3_get_dcb_info,
5506         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5507 };
5508
5509 static const struct hns3_reset_ops hns3_reset_ops = {
5510         .reset_service       = hns3_reset_service,
5511         .stop_service        = hns3_stop_service,
5512         .prepare_reset       = hns3_prepare_reset,
5513         .wait_hardware_ready = hns3_wait_hardware_ready,
5514         .reinit_dev          = hns3_reinit_dev,
5515         .restore_conf        = hns3_restore_conf,
5516         .start_service       = hns3_start_service,
5517 };
5518
5519 static int
5520 hns3_dev_init(struct rte_eth_dev *eth_dev)
5521 {
5522         struct hns3_adapter *hns = eth_dev->data->dev_private;
5523         struct hns3_hw *hw = &hns->hw;
5524         int ret;
5525
5526         PMD_INIT_FUNC_TRACE();
5527
5528         eth_dev->process_private = (struct hns3_process_private *)
5529             rte_zmalloc_socket("hns3_filter_list",
5530                                sizeof(struct hns3_process_private),
5531                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5532         if (eth_dev->process_private == NULL) {
5533                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5534                 return -ENOMEM;
5535         }
5536         /* initialize flow filter lists */
5537         hns3_filterlist_init(eth_dev);
5538
5539         hns3_set_rxtx_function(eth_dev);
5540         eth_dev->dev_ops = &hns3_eth_dev_ops;
5541         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5542                 ret = hns3_mp_init_secondary();
5543                 if (ret) {
5544                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
5545                                      "process, ret = %d", ret);
5546                         goto err_mp_init_secondary;
5547                 }
5548
5549                 hw->secondary_cnt++;
5550                 return 0;
5551         }
5552
5553         ret = hns3_mp_init_primary();
5554         if (ret) {
5555                 PMD_INIT_LOG(ERR,
5556                              "Failed to init for primary process, ret = %d",
5557                              ret);
5558                 goto err_mp_init_primary;
5559         }
5560
5561         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5562         hns->is_vf = false;
5563         hw->data = eth_dev->data;
5564
5565         /*
5566          * Set default max packet size according to the mtu
5567          * default vale in DPDK frame.
5568          */
5569         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5570
5571         ret = hns3_reset_init(hw);
5572         if (ret)
5573                 goto err_init_reset;
5574         hw->reset.ops = &hns3_reset_ops;
5575
5576         ret = hns3_init_pf(eth_dev);
5577         if (ret) {
5578                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5579                 goto err_init_pf;
5580         }
5581
5582         /* Allocate memory for storing MAC addresses */
5583         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5584                                                sizeof(struct rte_ether_addr) *
5585                                                HNS3_UC_MACADDR_NUM, 0);
5586         if (eth_dev->data->mac_addrs == NULL) {
5587                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5588                              "to store MAC addresses",
5589                              sizeof(struct rte_ether_addr) *
5590                              HNS3_UC_MACADDR_NUM);
5591                 ret = -ENOMEM;
5592                 goto err_rte_zmalloc;
5593         }
5594
5595         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5596                             &eth_dev->data->mac_addrs[0]);
5597
5598         hw->adapter_state = HNS3_NIC_INITIALIZED;
5599         /*
5600          * Pass the information to the rte_eth_dev_close() that it should also
5601          * release the private port resources.
5602          */
5603         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5604
5605         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5606                 hns3_err(hw, "Reschedule reset service after dev_init");
5607                 hns3_schedule_reset(hns);
5608         } else {
5609                 /* IMP will wait ready flag before reset */
5610                 hns3_notify_reset_ready(hw, false);
5611         }
5612
5613         hns3_info(hw, "hns3 dev initialization successful!");
5614         return 0;
5615
5616 err_rte_zmalloc:
5617         hns3_uninit_pf(eth_dev);
5618
5619 err_init_pf:
5620         rte_free(hw->reset.wait_data);
5621
5622 err_init_reset:
5623         hns3_mp_uninit_primary();
5624
5625 err_mp_init_primary:
5626 err_mp_init_secondary:
5627         eth_dev->dev_ops = NULL;
5628         eth_dev->rx_pkt_burst = NULL;
5629         eth_dev->tx_pkt_burst = NULL;
5630         eth_dev->tx_pkt_prepare = NULL;
5631         rte_free(eth_dev->process_private);
5632         eth_dev->process_private = NULL;
5633         return ret;
5634 }
5635
5636 static int
5637 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5638 {
5639         struct hns3_adapter *hns = eth_dev->data->dev_private;
5640         struct hns3_hw *hw = &hns->hw;
5641
5642         PMD_INIT_FUNC_TRACE();
5643
5644         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5645                 return -EPERM;
5646
5647         eth_dev->dev_ops = NULL;
5648         eth_dev->rx_pkt_burst = NULL;
5649         eth_dev->tx_pkt_burst = NULL;
5650         eth_dev->tx_pkt_prepare = NULL;
5651         if (hw->adapter_state < HNS3_NIC_CLOSING)
5652                 hns3_dev_close(eth_dev);
5653
5654         hw->adapter_state = HNS3_NIC_REMOVED;
5655         return 0;
5656 }
5657
5658 static int
5659 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5660                    struct rte_pci_device *pci_dev)
5661 {
5662         return rte_eth_dev_pci_generic_probe(pci_dev,
5663                                              sizeof(struct hns3_adapter),
5664                                              hns3_dev_init);
5665 }
5666
5667 static int
5668 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5669 {
5670         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5671 }
5672
5673 static const struct rte_pci_id pci_id_hns3_map[] = {
5674         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5675         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5676         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5677         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5678         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5679         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5680         { .vendor_id = 0, /* sentinel */ },
5681 };
5682
5683 static struct rte_pci_driver rte_hns3_pmd = {
5684         .id_table = pci_id_hns3_map,
5685         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5686         .probe = eth_hns3_pci_probe,
5687         .remove = eth_hns3_pci_remove,
5688 };
5689
5690 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5691 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5692 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5693 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5694 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);