drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_pf *pf = &hns->pf;
 312         uint16_t vlan_id;
 313         int ret = 0;
 314
 315         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 316                 return hns3_vlan_pvid_configure(hns,
 317                                                 pf->port_base_vlan_cfg.pvid, 1);
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 875                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 876                          RTE_ETHER_MAX_VLAN_ID);
 877                 return -EINVAL;
 878         }
 879
 880         rte_spinlock_lock(&hw->lock);
 881         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 882         rte_spinlock_unlock(&hw->lock);
 883         return ret;
 884 }
 885
 886 static void
 887 init_port_base_vlan_info(struct hns3_hw *hw)
 888 {
 889         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 890         struct hns3_pf *pf = &hns->pf;
 891
 892         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 893         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 894 }
 895
 896 static int
 897 hns3_default_vlan_config(struct hns3_adapter *hns)
 898 {
 899         struct hns3_hw *hw = &hns->hw;
 900         int ret;
 901
 902         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 903         if (ret)
 904                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 905         return ret;
 906 }
 907
 908 static int
 909 hns3_init_vlan_config(struct hns3_adapter *hns)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         int ret;
 913
 914         /*
 915          * This function can be called in the initialization and reset process,
 916          * when in reset process, it means that hardware had been reseted
 917          * successfully and we need to restore the hardware configuration to
 918          * ensure that the hardware configuration remains unchanged before and
 919          * after reset.
 920          */
 921         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 922                 init_port_base_vlan_info(hw);
 923
 924         ret = hns3_enable_vlan_filter(hns, true);
 925         if (ret) {
 926                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 927                 return ret;
 928         }
 929
 930         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 931                                        RTE_ETHER_TYPE_VLAN);
 932         if (ret) {
 933                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 934                 return ret;
 935         }
 936
 937         /*
 938          * When in the reinit dev stage of the reset process, the following
 939          * vlan-related configurations may differ from those at initialization,
 940          * we will restore configurations to hardware in hns3_restore_vlan_table
 941          * and hns3_restore_vlan_conf later.
 942          */
 943         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 944                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 945                 if (ret) {
 946                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 947                         return ret;
 948                 }
 949
 950                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 951                 if (ret) {
 952                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 953                                  ret);
 954                         return ret;
 955                 }
 956         }
 957
 958         return hns3_default_vlan_config(hns);
 959 }
 960
 961 static int
 962 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 963 {
 964         struct hns3_pf *pf = &hns->pf;
 965         struct hns3_hw *hw = &hns->hw;
 966         int ret;
 967
 968         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 969         if (ret) {
 970                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 971                 return ret;
 972         }
 973
 974         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 975         if (ret)
 976                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 977
 978         return ret;
 979 }
 980
 981 static int
 982 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 983 {
 984         struct hns3_adapter *hns = dev->data->dev_private;
 985         struct rte_eth_dev_data *data = dev->data;
 986         struct rte_eth_txmode *txmode;
 987         struct hns3_hw *hw = &hns->hw;
 988         int ret;
 989
 990         txmode = &data->dev_conf.txmode;
 991         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 992                 hns3_warn(hw,
 993                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 994                           "configuration is not supported! Ignore these two "
 995                           "parameters: hw_vlan_reject_tagged(%d), "
 996                           "hw_vlan_reject_untagged(%d)",
 997                           txmode->hw_vlan_reject_tagged,
 998                           txmode->hw_vlan_reject_untagged);
 999
1000         /* Apply vlan offload setting */
1001         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1002         if (ret) {
1003                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1004                 return ret;
1005         }
1006
1007         /* Apply pvid setting */
1008         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1009                                  txmode->hw_vlan_insert_pvid);
1010         if (ret)
1011                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1012                          txmode->pvid, ret);
1013
1014         return ret;
1015 }
1016
1017 static int
1018 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1019                 unsigned int tso_mss_max)
1020 {
1021         struct hns3_cfg_tso_status_cmd *req;
1022         struct hns3_cmd_desc desc;
1023         uint16_t tso_mss;
1024
1025         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1026
1027         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1028
1029         tso_mss = 0;
1030         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1031                        tso_mss_min);
1032         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1033
1034         tso_mss = 0;
1035         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1036                        tso_mss_max);
1037         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1038
1039         return hns3_cmd_send(hw, &desc, 1);
1040 }
1041
1042 int
1043 hns3_config_gro(struct hns3_hw *hw, bool en)
1044 {
1045         struct hns3_cfg_gro_status_cmd *req;
1046         struct hns3_cmd_desc desc;
1047         int ret;
1048
1049         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1050         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1051
1052         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1053
1054         ret = hns3_cmd_send(hw, &desc, 1);
1055         if (ret)
1056                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1057
1058         return ret;
1059 }
1060
1061 static int
1062 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1063                    uint16_t *allocated_size, bool is_alloc)
1064 {
1065         struct hns3_umv_spc_alc_cmd *req;
1066         struct hns3_cmd_desc desc;
1067         int ret;
1068
1069         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1070         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1071         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1072         req->space_size = rte_cpu_to_le_32(space_size);
1073
1074         ret = hns3_cmd_send(hw, &desc, 1);
1075         if (ret) {
1076                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1077                              is_alloc ? "allocate" : "free", ret);
1078                 return ret;
1079         }
1080
1081         if (is_alloc && allocated_size)
1082                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1083
1084         return 0;
1085 }
1086
1087 static int
1088 hns3_init_umv_space(struct hns3_hw *hw)
1089 {
1090         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1091         struct hns3_pf *pf = &hns->pf;
1092         uint16_t allocated_size = 0;
1093         int ret;
1094
1095         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1096                                  true);
1097         if (ret)
1098                 return ret;
1099
1100         if (allocated_size < pf->wanted_umv_size)
1101                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1102                              pf->wanted_umv_size, allocated_size);
1103
1104         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1105                                                 pf->wanted_umv_size;
1106         pf->used_umv_size = 0;
1107         return 0;
1108 }
1109
1110 static int
1111 hns3_uninit_umv_space(struct hns3_hw *hw)
1112 {
1113         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1114         struct hns3_pf *pf = &hns->pf;
1115         int ret;
1116
1117         if (pf->max_umv_size == 0)
1118                 return 0;
1119
1120         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1121         if (ret)
1122                 return ret;
1123
1124         pf->max_umv_size = 0;
1125
1126         return 0;
1127 }
1128
1129 static bool
1130 hns3_is_umv_space_full(struct hns3_hw *hw)
1131 {
1132         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1133         struct hns3_pf *pf = &hns->pf;
1134         bool is_full;
1135
1136         is_full = (pf->used_umv_size >= pf->max_umv_size);
1137
1138         return is_full;
1139 }
1140
1141 static void
1142 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1143 {
1144         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1145         struct hns3_pf *pf = &hns->pf;
1146
1147         if (is_free) {
1148                 if (pf->used_umv_size > 0)
1149                         pf->used_umv_size--;
1150         } else
1151                 pf->used_umv_size++;
1152 }
1153
1154 static void
1155 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1156                       const uint8_t *addr, bool is_mc)
1157 {
1158         const unsigned char *mac_addr = addr;
1159         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1160                             ((uint32_t)mac_addr[2] << 16) |
1161                             ((uint32_t)mac_addr[1] << 8) |
1162                             (uint32_t)mac_addr[0];
1163         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1164
1165         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1166         if (is_mc) {
1167                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1168                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1169                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1170         }
1171
1172         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1173         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1174 }
1175
1176 static int
1177 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1178                              uint8_t resp_code,
1179                              enum hns3_mac_vlan_tbl_opcode op)
1180 {
1181         if (cmdq_resp) {
1182                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1183                          cmdq_resp);
1184                 return -EIO;
1185         }
1186
1187         if (op == HNS3_MAC_VLAN_ADD) {
1188                 if (resp_code == 0 || resp_code == 1) {
1189                         return 0;
1190                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1191                         hns3_err(hw, "add mac addr failed for uc_overflow");
1192                         return -ENOSPC;
1193                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1194                         hns3_err(hw, "add mac addr failed for mc_overflow");
1195                         return -ENOSPC;
1196                 }
1197
1198                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1199                          resp_code);
1200                 return -EIO;
1201         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1202                 if (resp_code == 0) {
1203                         return 0;
1204                 } else if (resp_code == 1) {
1205                         hns3_dbg(hw, "remove mac addr failed for miss");
1206                         return -ENOENT;
1207                 }
1208
1209                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1210                          resp_code);
1211                 return -EIO;
1212         } else if (op == HNS3_MAC_VLAN_LKUP) {
1213                 if (resp_code == 0) {
1214                         return 0;
1215                 } else if (resp_code == 1) {
1216                         hns3_dbg(hw, "lookup mac addr failed for miss");
1217                         return -ENOENT;
1218                 }
1219
1220                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1221                          resp_code);
1222                 return -EIO;
1223         }
1224
1225         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1226                  op);
1227
1228         return -EINVAL;
1229 }
1230
1231 static int
1232 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1233                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1234                          struct hns3_cmd_desc *desc, bool is_mc)
1235 {
1236         uint8_t resp_code;
1237         uint16_t retval;
1238         int ret;
1239
1240         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1241         if (is_mc) {
1242                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1243                 memcpy(desc[0].data, req,
1244                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1245                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1246                                           true);
1247                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1248                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1249                                           true);
1250                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1251         } else {
1252                 memcpy(desc[0].data, req,
1253                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1254                 ret = hns3_cmd_send(hw, desc, 1);
1255         }
1256         if (ret) {
1257                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1258                          ret);
1259                 return ret;
1260         }
1261         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1262         retval = rte_le_to_cpu_16(desc[0].retval);
1263
1264         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1265                                             HNS3_MAC_VLAN_LKUP);
1266 }
1267
1268 static int
1269 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1270                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1271                       struct hns3_cmd_desc *mc_desc)
1272 {
1273         uint8_t resp_code;
1274         uint16_t retval;
1275         int cfg_status;
1276         int ret;
1277
1278         if (mc_desc == NULL) {
1279                 struct hns3_cmd_desc desc;
1280
1281                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1282                 memcpy(desc.data, req,
1283                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1284                 ret = hns3_cmd_send(hw, &desc, 1);
1285                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1286                 retval = rte_le_to_cpu_16(desc.retval);
1287
1288                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1289                                                           HNS3_MAC_VLAN_ADD);
1290         } else {
1291                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1292                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1293                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1294                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1295                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1296                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1297                 memcpy(mc_desc[0].data, req,
1298                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1299                 mc_desc[0].retval = 0;
1300                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1301                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1302                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1303
1304                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1305                                                           HNS3_MAC_VLAN_ADD);
1306         }
1307
1308         if (ret) {
1309                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1310                 return ret;
1311         }
1312
1313         return cfg_status;
1314 }
1315
1316 static int
1317 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1318                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1319 {
1320         struct hns3_cmd_desc desc;
1321         uint8_t resp_code;
1322         uint16_t retval;
1323         int ret;
1324
1325         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1326
1327         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1328
1329         ret = hns3_cmd_send(hw, &desc, 1);
1330         if (ret) {
1331                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1332                 return ret;
1333         }
1334         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1335         retval = rte_le_to_cpu_16(desc.retval);
1336
1337         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1338                                             HNS3_MAC_VLAN_REMOVE);
1339 }
1340
1341 static int
1342 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1343 {
1344         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1345         struct hns3_mac_vlan_tbl_entry_cmd req;
1346         struct hns3_pf *pf = &hns->pf;
1347         struct hns3_cmd_desc desc;
1348         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1349         uint16_t egress_port = 0;
1350         uint8_t vf_id;
1351         int ret;
1352
1353         /* check if mac addr is valid */
1354         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1355                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1356                                       mac_addr);
1357                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1358                          mac_str);
1359                 return -EINVAL;
1360         }
1361
1362         memset(&req, 0, sizeof(req));
1363
1364         /*
1365          * In current version VF is not supported when PF is driven by DPDK
1366          * driver, the PF-related vf_id is 0, just need to configure parameters
1367          * for vf_id 0.
1368          */
1369         vf_id = 0;
1370         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1371                        HNS3_MAC_EPORT_VFID_S, vf_id);
1372
1373         req.egress_port = rte_cpu_to_le_16(egress_port);
1374
1375         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1376
1377         /*
1378          * Lookup the mac address in the mac_vlan table, and add
1379          * it if the entry is inexistent. Repeated unicast entry
1380          * is not allowed in the mac vlan table.
1381          */
1382         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1383         if (ret == -ENOENT) {
1384                 if (!hns3_is_umv_space_full(hw)) {
1385                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1386                         if (!ret)
1387                                 hns3_update_umv_space(hw, false);
1388                         return ret;
1389                 }
1390
1391                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1392
1393                 return -ENOSPC;
1394         }
1395
1396         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1397
1398         /* check if we just hit the duplicate */
1399         if (ret == 0) {
1400                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1401                 return 0;
1402         }
1403
1404         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1405                  mac_str);
1406
1407         return ret;
1408 }
1409
1410 static int
1411 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1412                   uint32_t idx, __rte_unused uint32_t pool)
1413 {
1414         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1416         int ret;
1417
1418         rte_spinlock_lock(&hw->lock);
1419         ret = hns3_add_uc_addr_common(hw, mac_addr);
1420         if (ret) {
1421                 rte_spinlock_unlock(&hw->lock);
1422                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1423                                       mac_addr);
1424                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1425                 return ret;
1426         }
1427
1428         if (idx == 0)
1429                 hw->mac.default_addr_setted = true;
1430         rte_spinlock_unlock(&hw->lock);
1431
1432         return ret;
1433 }
1434
1435 static int
1436 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1437 {
1438         struct hns3_mac_vlan_tbl_entry_cmd req;
1439         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1440         int ret;
1441
1442         /* check if mac addr is valid */
1443         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1444                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1445                                       mac_addr);
1446                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1447                          mac_str);
1448                 return -EINVAL;
1449         }
1450
1451         memset(&req, 0, sizeof(req));
1452         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1453         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1454         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1455         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1456                 return 0;
1457         else if (ret == 0)
1458                 hns3_update_umv_space(hw, true);
1459
1460         return ret;
1461 }
1462
1463 static void
1464 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1465 {
1466         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467         /* index will be checked by upper level rte interface */
1468         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1469         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470         int ret;
1471
1472         rte_spinlock_lock(&hw->lock);
1473         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1474         if (ret) {
1475                 rte_spinlock_unlock(&hw->lock);
1476                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1477                                       mac_addr);
1478                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1479                 return;
1480         }
1481
1482         rte_spinlock_unlock(&hw->lock);
1483 }
1484
1485 static int
1486 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1487                           struct rte_ether_addr *mac_addr)
1488 {
1489         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490         struct rte_ether_addr *oaddr;
1491         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1492         bool default_addr_setted;
1493         bool rm_succes = false;
1494         int ret, ret_val;
1495
1496         /*
1497          * It has been guaranteed that input parameter named mac_addr is valid
1498          * address in the rte layer of DPDK framework.
1499          */
1500         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1501         default_addr_setted = hw->mac.default_addr_setted;
1502         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1503                 return 0;
1504
1505         rte_spinlock_lock(&hw->lock);
1506         if (default_addr_setted) {
1507                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1508                 if (ret) {
1509                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1510                                               oaddr);
1511                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1512                                   mac_str, ret);
1513                         rm_succes = false;
1514                 } else
1515                         rm_succes = true;
1516         }
1517
1518         ret = hns3_add_uc_addr_common(hw, mac_addr);
1519         if (ret) {
1520                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1521                                       mac_addr);
1522                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1523                 goto err_add_uc_addr;
1524         }
1525
1526         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1527         if (ret) {
1528                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1529                 goto err_pause_addr_cfg;
1530         }
1531
1532         rte_ether_addr_copy(mac_addr,
1533                             (struct rte_ether_addr *)hw->mac.mac_addr);
1534         hw->mac.default_addr_setted = true;
1535         rte_spinlock_unlock(&hw->lock);
1536
1537         return 0;
1538
1539 err_pause_addr_cfg:
1540         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1541         if (ret_val) {
1542                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1543                                       mac_addr);
1544                 hns3_warn(hw,
1545                           "Failed to roll back to del setted mac addr(%s): %d",
1546                           mac_str, ret_val);
1547         }
1548
1549 err_add_uc_addr:
1550         if (rm_succes) {
1551                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1552                 if (ret_val) {
1553                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                               oaddr);
1555                         hns3_warn(hw,
1556                                   "Failed to restore old uc mac addr(%s): %d",
1557                                   mac_str, ret_val);
1558                         hw->mac.default_addr_setted = false;
1559                 }
1560         }
1561         rte_spinlock_unlock(&hw->lock);
1562
1563         return ret;
1564 }
1565
1566 static int
1567 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1568 {
1569         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1570         struct hns3_hw *hw = &hns->hw;
1571         struct rte_ether_addr *addr;
1572         int err = 0;
1573         int ret;
1574         int i;
1575
1576         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1577                 addr = &hw->data->mac_addrs[i];
1578                 if (!rte_is_valid_assigned_ether_addr(addr))
1579                         continue;
1580                 if (del)
1581                         ret = hns3_remove_uc_addr_common(hw, addr);
1582                 else
1583                         ret = hns3_add_uc_addr_common(hw, addr);
1584                 if (ret) {
1585                         err = ret;
1586                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1587                                               addr);
1588                         hns3_dbg(hw,
1589                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1590                                  del ? "remove" : "restore", mac_str, ret, i);
1591                 }
1592         }
1593         return err;
1594 }
1595
1596 static void
1597 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1598 {
1599 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1600         uint8_t word_num;
1601         uint8_t bit_num;
1602
1603         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1604                 word_num = vfid / 32;
1605                 bit_num = vfid % 32;
1606                 if (clr)
1607                         desc[1].data[word_num] &=
1608                             rte_cpu_to_le_32(~(1UL << bit_num));
1609                 else
1610                         desc[1].data[word_num] |=
1611                             rte_cpu_to_le_32(1UL << bit_num);
1612         } else {
1613                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1614                 bit_num = vfid % 32;
1615                 if (clr)
1616                         desc[2].data[word_num] &=
1617                             rte_cpu_to_le_32(~(1UL << bit_num));
1618                 else
1619                         desc[2].data[word_num] |=
1620                             rte_cpu_to_le_32(1UL << bit_num);
1621         }
1622 }
1623
1624 static int
1625 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         struct hns3_mac_vlan_tbl_entry_cmd req;
1628         struct hns3_cmd_desc desc[3];
1629         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1630         uint8_t vf_id;
1631         int ret;
1632
1633         /* Check if mac addr is valid */
1634         if (!rte_is_multicast_ether_addr(mac_addr)) {
1635                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1636                                       mac_addr);
1637                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1638                          mac_str);
1639                 return -EINVAL;
1640         }
1641
1642         memset(&req, 0, sizeof(req));
1643         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1644         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1645         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1646         if (ret) {
1647                 /* This mac addr do not exist, add new entry for it */
1648                 memset(desc[0].data, 0, sizeof(desc[0].data));
1649                 memset(desc[1].data, 0, sizeof(desc[0].data));
1650                 memset(desc[2].data, 0, sizeof(desc[0].data));
1651         }
1652
1653         /*
1654          * In current version VF is not supported when PF is driven by DPDK
1655          * driver, the PF-related vf_id is 0, just need to configure parameters
1656          * for vf_id 0.
1657          */
1658         vf_id = 0;
1659         hns3_update_desc_vfid(desc, vf_id, false);
1660         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1661         if (ret) {
1662                 if (ret == -ENOSPC)
1663                         hns3_err(hw, "mc mac vlan table is full");
1664                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1665                                       mac_addr);
1666                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1667         }
1668
1669         return ret;
1670 }
1671
1672 static int
1673 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1674 {
1675         struct hns3_mac_vlan_tbl_entry_cmd req;
1676         struct hns3_cmd_desc desc[3];
1677         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1678         uint8_t vf_id;
1679         int ret;
1680
1681         /* Check if mac addr is valid */
1682         if (!rte_is_multicast_ether_addr(mac_addr)) {
1683                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1684                                       mac_addr);
1685                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1686                          mac_str);
1687                 return -EINVAL;
1688         }
1689
1690         memset(&req, 0, sizeof(req));
1691         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1692         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1693         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1694         if (ret == 0) {
1695                 /*
1696                  * This mac addr exist, remove this handle's VFID for it.
1697                  * In current version VF is not supported when PF is driven by
1698                  * DPDK driver, the PF-related vf_id is 0, just need to
1699                  * configure parameters for vf_id 0.
1700                  */
1701                 vf_id = 0;
1702                 hns3_update_desc_vfid(desc, vf_id, true);
1703
1704                 /* All the vfid is zero, so need to delete this entry */
1705                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1706         } else if (ret == -ENOENT) {
1707                 /* This mac addr doesn't exist. */
1708                 return 0;
1709         }
1710
1711         if (ret) {
1712                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1713                                       mac_addr);
1714                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1715         }
1716
1717         return ret;
1718 }
1719
1720 static int
1721 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1722                            struct rte_ether_addr *mc_addr_set,
1723                            uint32_t nb_mc_addr)
1724 {
1725         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1726         struct rte_ether_addr *addr;
1727         uint32_t i;
1728         uint32_t j;
1729
1730         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1731                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1732                          "invalid. valid range: 0~%d",
1733                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1734                 return -EINVAL;
1735         }
1736
1737         /* Check if input mac addresses are valid */
1738         for (i = 0; i < nb_mc_addr; i++) {
1739                 addr = &mc_addr_set[i];
1740                 if (!rte_is_multicast_ether_addr(addr)) {
1741                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1742                                               addr);
1743                         hns3_err(hw,
1744                                  "Failed to set mc mac addr, addr(%s) invalid.",
1745                                  mac_str);
1746                         return -EINVAL;
1747                 }
1748
1749                 /* Check if there are duplicate addresses */
1750                 for (j = i + 1; j < nb_mc_addr; j++) {
1751                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1752                                 rte_ether_format_addr(mac_str,
1753                                                       RTE_ETHER_ADDR_FMT_SIZE,
1754                                                       addr);
1755                                 hns3_err(hw, "Failed to set mc mac addr, "
1756                                          "addrs invalid. two same addrs(%s).",
1757                                          mac_str);
1758                                 return -EINVAL;
1759                         }
1760                 }
1761         }
1762
1763         return 0;
1764 }
1765
1766 static void
1767 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1768                            struct rte_ether_addr *mc_addr_set,
1769                            int mc_addr_num,
1770                            struct rte_ether_addr *reserved_addr_list,
1771                            int *reserved_addr_num,
1772                            struct rte_ether_addr *add_addr_list,
1773                            int *add_addr_num,
1774                            struct rte_ether_addr *rm_addr_list,
1775                            int *rm_addr_num)
1776 {
1777         struct rte_ether_addr *addr;
1778         int current_addr_num;
1779         int reserved_num = 0;
1780         int add_num = 0;
1781         int rm_num = 0;
1782         int num;
1783         int i;
1784         int j;
1785         bool same_addr;
1786
1787         /* Calculate the mc mac address list that should be removed */
1788         current_addr_num = hw->mc_addrs_num;
1789         for (i = 0; i < current_addr_num; i++) {
1790                 addr = &hw->mc_addrs[i];
1791                 same_addr = false;
1792                 for (j = 0; j < mc_addr_num; j++) {
1793                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1794                                 same_addr = true;
1795                                 break;
1796                         }
1797                 }
1798
1799                 if (!same_addr) {
1800                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1801                         rm_num++;
1802                 } else {
1803                         rte_ether_addr_copy(addr,
1804                                             &reserved_addr_list[reserved_num]);
1805                         reserved_num++;
1806                 }
1807         }
1808
1809         /* Calculate the mc mac address list that should be added */
1810         for (i = 0; i < mc_addr_num; i++) {
1811                 addr = &mc_addr_set[i];
1812                 same_addr = false;
1813                 for (j = 0; j < current_addr_num; j++) {
1814                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1815                                 same_addr = true;
1816                                 break;
1817                         }
1818                 }
1819
1820                 if (!same_addr) {
1821                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1822                         add_num++;
1823                 }
1824         }
1825
1826         /* Reorder the mc mac address list maintained by driver */
1827         for (i = 0; i < reserved_num; i++)
1828                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1829
1830         for (i = 0; i < rm_num; i++) {
1831                 num = reserved_num + i;
1832                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1833         }
1834
1835         *reserved_addr_num = reserved_num;
1836         *add_addr_num = add_num;
1837         *rm_addr_num = rm_num;
1838 }
1839
1840 static int
1841 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1842                           struct rte_ether_addr *mc_addr_set,
1843                           uint32_t nb_mc_addr)
1844 {
1845         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1847         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1848         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1849         struct rte_ether_addr *addr;
1850         int reserved_addr_num;
1851         int add_addr_num;
1852         int rm_addr_num;
1853         int mc_addr_num;
1854         int num;
1855         int ret;
1856         int i;
1857
1858         /* Check if input parameters are valid */
1859         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1860         if (ret)
1861                 return ret;
1862
1863         rte_spinlock_lock(&hw->lock);
1864
1865         /*
1866          * Calculate the mc mac address lists those should be removed and be
1867          * added, Reorder the mc mac address list maintained by driver.
1868          */
1869         mc_addr_num = (int)nb_mc_addr;
1870         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1871                                    reserved_addr_list, &reserved_addr_num,
1872                                    add_addr_list, &add_addr_num,
1873                                    rm_addr_list, &rm_addr_num);
1874
1875         /* Remove mc mac addresses */
1876         for (i = 0; i < rm_addr_num; i++) {
1877                 num = rm_addr_num - i - 1;
1878                 addr = &rm_addr_list[num];
1879                 ret = hns3_remove_mc_addr(hw, addr);
1880                 if (ret) {
1881                         rte_spinlock_unlock(&hw->lock);
1882                         return ret;
1883                 }
1884                 hw->mc_addrs_num--;
1885         }
1886
1887         /* Add mc mac addresses */
1888         for (i = 0; i < add_addr_num; i++) {
1889                 addr = &add_addr_list[i];
1890                 ret = hns3_add_mc_addr(hw, addr);
1891                 if (ret) {
1892                         rte_spinlock_unlock(&hw->lock);
1893                         return ret;
1894                 }
1895
1896                 num = reserved_addr_num + i;
1897                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1898                 hw->mc_addrs_num++;
1899         }
1900         rte_spinlock_unlock(&hw->lock);
1901
1902         return 0;
1903 }
1904
1905 static int
1906 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1907 {
1908         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1909         struct hns3_hw *hw = &hns->hw;
1910         struct rte_ether_addr *addr;
1911         int err = 0;
1912         int ret;
1913         int i;
1914
1915         for (i = 0; i < hw->mc_addrs_num; i++) {
1916                 addr = &hw->mc_addrs[i];
1917                 if (!rte_is_multicast_ether_addr(addr))
1918                         continue;
1919                 if (del)
1920                         ret = hns3_remove_mc_addr(hw, addr);
1921                 else
1922                         ret = hns3_add_mc_addr(hw, addr);
1923                 if (ret) {
1924                         err = ret;
1925                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1926                                               addr);
1927                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1928                                  del ? "Remove" : "Restore", mac_str);
1929                 }
1930         }
1931         return err;
1932 }
1933
1934 static int
1935 hns3_check_mq_mode(struct rte_eth_dev *dev)
1936 {
1937         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1938         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1939         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1942         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1943         uint8_t num_tc;
1944         int max_tc = 0;
1945         int i;
1946
1947         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1948         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1949
1950         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1951                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1952                          "rx_mq_mode = %d", rx_mq_mode);
1953                 return -EINVAL;
1954         }
1955
1956         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1957             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1958                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1959                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1960                          rx_mq_mode, tx_mq_mode);
1961                 return -EINVAL;
1962         }
1963
1964         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1965                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1966                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1967                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1968                         return -EINVAL;
1969                 }
1970
1971                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1972                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1973                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1974                                  "nb_tcs(%d) != %d or %d in rx direction.",
1975                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1976                         return -EINVAL;
1977                 }
1978
1979                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1980                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1981                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1982                         return -EINVAL;
1983                 }
1984
1985                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1986                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1987                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1988                                          "is not equal to one in tx direction.",
1989                                          i, dcb_rx_conf->dcb_tc[i]);
1990                                 return -EINVAL;
1991                         }
1992                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1993                                 max_tc = dcb_rx_conf->dcb_tc[i];
1994                 }
1995
1996                 num_tc = max_tc + 1;
1997                 if (num_tc > dcb_rx_conf->nb_tcs) {
1998                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1999                                  num_tc, dcb_rx_conf->nb_tcs);
2000                         return -EINVAL;
2001                 }
2002         }
2003
2004         return 0;
2005 }
2006
2007 static int
2008 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2009 {
2010         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011
2012         if (!hns3_dev_dcb_supported(hw)) {
2013                 hns3_err(hw, "this port does not support dcb configurations.");
2014                 return -EOPNOTSUPP;
2015         }
2016
2017         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2018                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2019                 return -EOPNOTSUPP;
2020         }
2021
2022         /* Check multiple queue mode */
2023         return hns3_check_mq_mode(dev);
2024 }
2025
2026 static int
2027 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2028                            enum hns3_ring_type queue_type, uint16_t queue_id)
2029 {
2030         struct hns3_cmd_desc desc;
2031         struct hns3_ctrl_vector_chain_cmd *req =
2032                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2033         enum hns3_cmd_status status;
2034         enum hns3_opcode_type op;
2035         uint16_t tqp_type_and_id = 0;
2036         const char *op_str;
2037         uint16_t type;
2038         uint16_t gl;
2039
2040         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2041         hns3_cmd_setup_basic_desc(&desc, op, false);
2042         req->int_vector_id = vector_id;
2043
2044         if (queue_type == HNS3_RING_TYPE_RX)
2045                 gl = HNS3_RING_GL_RX;
2046         else
2047                 gl = HNS3_RING_GL_TX;
2048
2049         type = queue_type;
2050
2051         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2052                        type);
2053         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2054         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2055                        gl);
2056         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2057         req->int_cause_num = 1;
2058         op_str = mmap ? "Map" : "Unmap";
2059         status = hns3_cmd_send(hw, &desc, 1);
2060         if (status) {
2061                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2062                          op_str, queue_id, req->int_vector_id, status);
2063                 return status;
2064         }
2065
2066         return 0;
2067 }
2068
2069 static int
2070 hns3_init_ring_with_vector(struct hns3_hw *hw)
2071 {
2072         uint8_t vec;
2073         int ret;
2074         int i;
2075
2076         /*
2077          * In hns3 network engine, vector 0 is always the misc interrupt of this
2078          * function, vector 1~N can be used respectively for the queues of the
2079          * function. Tx and Rx queues with the same number share the interrupt
2080          * vector. In the initialization clearing the all hardware mapping
2081          * relationship configurations between queues and interrupt vectors is
2082          * needed, so some error caused by the residual configurations, such as
2083          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2084          * constraints in hns3 hardware engine, we have to implement clearing
2085          * the mapping relationship configurations by binding all queues to the
2086          * last interrupt vector and reserving the last interrupt vector. This
2087          * method results in a decrease of the maximum queues when upper
2088          * applications call the rte_eth_dev_configure API function to enable
2089          * Rx interrupt.
2090          */
2091         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2092         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2093         for (i = 0; i < hw->intr_tqps_num; i++) {
2094                 /*
2095                  * Set gap limiter and rate limiter configuration of queue's
2096                  * interrupt.
2097                  */
2098                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2099                                        HNS3_TQP_INTR_GL_DEFAULT);
2100                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2101                                        HNS3_TQP_INTR_GL_DEFAULT);
2102                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2103
2104                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2105                                                  HNS3_RING_TYPE_TX, i);
2106                 if (ret) {
2107                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2108                                           "vector: %d, ret=%d", i, vec, ret);
2109                         return ret;
2110                 }
2111
2112                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2113                                                  HNS3_RING_TYPE_RX, i);
2114                 if (ret) {
2115                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2116                                           "vector: %d, ret=%d", i, vec, ret);
2117                         return ret;
2118                 }
2119         }
2120
2121         return 0;
2122 }
2123
2124 static int
2125 hns3_dev_configure(struct rte_eth_dev *dev)
2126 {
2127         struct hns3_adapter *hns = dev->data->dev_private;
2128         struct rte_eth_conf *conf = &dev->data->dev_conf;
2129         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2130         struct hns3_hw *hw = &hns->hw;
2131         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2132         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2133         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2134         struct rte_eth_rss_conf rss_conf;
2135         uint16_t mtu;
2136         int ret;
2137
2138         /*
2139          * Hardware does not support individually enable/disable/reset the Tx or
2140          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2141          * and Rx queues at the same time. When the numbers of Tx queues
2142          * allocated by upper applications are not equal to the numbers of Rx
2143          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2144          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2145          * these fake queues are imperceptible, and can not be used by upper
2146          * applications.
2147          */
2148         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2149         if (ret) {
2150                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2151                 return ret;
2152         }
2153
2154         hw->adapter_state = HNS3_NIC_CONFIGURING;
2155         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2156                 hns3_err(hw, "setting link speed/duplex not supported");
2157                 ret = -EINVAL;
2158                 goto cfg_err;
2159         }
2160
2161         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2162                 ret = hns3_check_dcb_cfg(dev);
2163                 if (ret)
2164                         goto cfg_err;
2165         }
2166
2167         /* When RSS is not configured, redirect the packet queue 0 */
2168         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2169                 rss_conf = conf->rx_adv_conf.rss_conf;
2170                 if (rss_conf.rss_key == NULL) {
2171                         rss_conf.rss_key = rss_cfg->key;
2172                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2173                 }
2174
2175                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2176                 if (ret)
2177                         goto cfg_err;
2178         }
2179
2180         /*
2181          * If jumbo frames are enabled, MTU needs to be refreshed
2182          * according to the maximum RX packet length.
2183          */
2184         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2185                 /*
2186                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2187                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2188                  * can safely assign to "uint16_t" type variable.
2189                  */
2190                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2191                 ret = hns3_dev_mtu_set(dev, mtu);
2192                 if (ret)
2193                         goto cfg_err;
2194                 dev->data->mtu = mtu;
2195         }
2196
2197         ret = hns3_dev_configure_vlan(dev);
2198         if (ret)
2199                 goto cfg_err;
2200
2201         hw->adapter_state = HNS3_NIC_CONFIGURED;
2202
2203         return 0;
2204
2205 cfg_err:
2206         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2207         hw->adapter_state = HNS3_NIC_INITIALIZED;
2208
2209         return ret;
2210 }
2211
2212 static int
2213 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2214 {
2215         struct hns3_config_max_frm_size_cmd *req;
2216         struct hns3_cmd_desc desc;
2217
2218         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2219
2220         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2221         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2222         req->min_frm_size = RTE_ETHER_MIN_LEN;
2223
2224         return hns3_cmd_send(hw, &desc, 1);
2225 }
2226
2227 static int
2228 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2229 {
2230         int ret;
2231
2232         ret = hns3_set_mac_mtu(hw, mps);
2233         if (ret) {
2234                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2235                 return ret;
2236         }
2237
2238         ret = hns3_buffer_alloc(hw);
2239         if (ret)
2240                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2241
2242         return ret;
2243 }
2244
2245 static int
2246 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2247 {
2248         struct hns3_adapter *hns = dev->data->dev_private;
2249         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2250         struct hns3_hw *hw = &hns->hw;
2251         bool is_jumbo_frame;
2252         int ret;
2253
2254         if (dev->data->dev_started) {
2255                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2256                          "before configuration", dev->data->port_id);
2257                 return -EBUSY;
2258         }
2259
2260         rte_spinlock_lock(&hw->lock);
2261         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2262         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2263
2264         /*
2265          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2266          * assign to "uint16_t" type variable.
2267          */
2268         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2269         if (ret) {
2270                 rte_spinlock_unlock(&hw->lock);
2271                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2272                          dev->data->port_id, mtu, ret);
2273                 return ret;
2274         }
2275         hns->pf.mps = (uint16_t)frame_size;
2276         if (is_jumbo_frame)
2277                 dev->data->dev_conf.rxmode.offloads |=
2278                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2279         else
2280                 dev->data->dev_conf.rxmode.offloads &=
2281                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2282         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2283         rte_spinlock_unlock(&hw->lock);
2284
2285         return 0;
2286 }
2287
2288 static int
2289 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2290 {
2291         struct hns3_adapter *hns = eth_dev->data->dev_private;
2292         struct hns3_hw *hw = &hns->hw;
2293         uint16_t queue_num = hw->tqps_num;
2294
2295         /*
2296          * In interrupt mode, 'max_rx_queues' is set based on the number of
2297          * MSI-X interrupt resources of the hardware.
2298          */
2299         if (hw->data->dev_conf.intr_conf.rxq == 1)
2300                 queue_num = hw->intr_tqps_num;
2301
2302         info->max_rx_queues = queue_num;
2303         info->max_tx_queues = hw->tqps_num;
2304         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2305         info->min_rx_bufsize = hw->rx_buf_len;
2306         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2307         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2308         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2309                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2310                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2311                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2312                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2313                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2314                                  DEV_RX_OFFLOAD_KEEP_CRC |
2315                                  DEV_RX_OFFLOAD_SCATTER |
2316                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2317                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2318                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2319                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2320                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2321         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2322         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2323                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2324                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2325                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2326                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2327                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2328                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2329                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2330                                  DEV_TX_OFFLOAD_TCP_TSO |
2331                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2332                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2333                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2334                                  info->tx_queue_offload_capa);
2335
2336         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2337                 .nb_max = HNS3_MAX_RING_DESC,
2338                 .nb_min = HNS3_MIN_RING_DESC,
2339                 .nb_align = HNS3_ALIGN_RING_DESC,
2340         };
2341
2342         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2343                 .nb_max = HNS3_MAX_RING_DESC,
2344                 .nb_min = HNS3_MIN_RING_DESC,
2345                 .nb_align = HNS3_ALIGN_RING_DESC,
2346         };
2347
2348         info->vmdq_queue_num = 0;
2349
2350         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2351         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2352         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2353
2354         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2355         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2356         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2357         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2358         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2359         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2360
2361         return 0;
2362 }
2363
2364 static int
2365 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2366                     size_t fw_size)
2367 {
2368         struct hns3_adapter *hns = eth_dev->data->dev_private;
2369         struct hns3_hw *hw = &hns->hw;
2370         int ret;
2371
2372         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2373         ret += 1; /* add the size of '\0' */
2374         if (fw_size < (uint32_t)ret)
2375                 return ret;
2376         else
2377                 return 0;
2378 }
2379
2380 static int
2381 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2382                      __rte_unused int wait_to_complete)
2383 {
2384         struct hns3_adapter *hns = eth_dev->data->dev_private;
2385         struct hns3_hw *hw = &hns->hw;
2386         struct hns3_mac *mac = &hw->mac;
2387         struct rte_eth_link new_link;
2388
2389         if (!hns3_is_reset_pending(hns)) {
2390                 hns3_update_speed_duplex(eth_dev);
2391                 hns3_update_link_status(hw);
2392         }
2393
2394         memset(&new_link, 0, sizeof(new_link));
2395         switch (mac->link_speed) {
2396         case ETH_SPEED_NUM_10M:
2397         case ETH_SPEED_NUM_100M:
2398         case ETH_SPEED_NUM_1G:
2399         case ETH_SPEED_NUM_10G:
2400         case ETH_SPEED_NUM_25G:
2401         case ETH_SPEED_NUM_40G:
2402         case ETH_SPEED_NUM_50G:
2403         case ETH_SPEED_NUM_100G:
2404                 new_link.link_speed = mac->link_speed;
2405                 break;
2406         default:
2407                 new_link.link_speed = ETH_SPEED_NUM_100M;
2408                 break;
2409         }
2410
2411         new_link.link_duplex = mac->link_duplex;
2412         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2413         new_link.link_autoneg =
2414             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2415
2416         return rte_eth_linkstatus_set(eth_dev, &new_link);
2417 }
2418
2419 static int
2420 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2421 {
2422         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2423         struct hns3_pf *pf = &hns->pf;
2424
2425         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2426                 return -EINVAL;
2427
2428         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2429
2430         return 0;
2431 }
2432
2433 static int
2434 hns3_query_function_status(struct hns3_hw *hw)
2435 {
2436 #define HNS3_QUERY_MAX_CNT              10
2437 #define HNS3_QUERY_SLEEP_MSCOEND        1
2438         struct hns3_func_status_cmd *req;
2439         struct hns3_cmd_desc desc;
2440         int timeout = 0;
2441         int ret;
2442
2443         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2444         req = (struct hns3_func_status_cmd *)desc.data;
2445
2446         do {
2447                 ret = hns3_cmd_send(hw, &desc, 1);
2448                 if (ret) {
2449                         PMD_INIT_LOG(ERR, "query function status failed %d",
2450                                      ret);
2451                         return ret;
2452                 }
2453
2454                 /* Check pf reset is done */
2455                 if (req->pf_state)
2456                         break;
2457
2458                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2459         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2460
2461         return hns3_parse_func_status(hw, req);
2462 }
2463
2464 static int
2465 hns3_query_pf_resource(struct hns3_hw *hw)
2466 {
2467         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2468         struct hns3_pf *pf = &hns->pf;
2469         struct hns3_pf_res_cmd *req;
2470         struct hns3_cmd_desc desc;
2471         uint16_t num_msi;
2472         int ret;
2473
2474         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2475         ret = hns3_cmd_send(hw, &desc, 1);
2476         if (ret) {
2477                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2478                 return ret;
2479         }
2480
2481         req = (struct hns3_pf_res_cmd *)desc.data;
2482         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2483         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2484         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2485         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2486
2487         if (req->tx_buf_size)
2488                 pf->tx_buf_size =
2489                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2490         else
2491                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2492
2493         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2494
2495         if (req->dv_buf_size)
2496                 pf->dv_buf_size =
2497                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2498         else
2499                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2500
2501         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2502
2503         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2504                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2505         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2506
2507         return 0;
2508 }
2509
2510 static void
2511 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2512 {
2513         struct hns3_cfg_param_cmd *req;
2514         uint64_t mac_addr_tmp_high;
2515         uint64_t mac_addr_tmp;
2516         uint32_t i;
2517
2518         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2519
2520         /* get the configuration */
2521         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2522                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2523         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2524                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2525         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2526                                            HNS3_CFG_TQP_DESC_N_M,
2527                                            HNS3_CFG_TQP_DESC_N_S);
2528
2529         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2530                                        HNS3_CFG_PHY_ADDR_M,
2531                                        HNS3_CFG_PHY_ADDR_S);
2532         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2533                                          HNS3_CFG_MEDIA_TP_M,
2534                                          HNS3_CFG_MEDIA_TP_S);
2535         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2536                                          HNS3_CFG_RX_BUF_LEN_M,
2537                                          HNS3_CFG_RX_BUF_LEN_S);
2538         /* get mac address */
2539         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2540         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2541                                            HNS3_CFG_MAC_ADDR_H_M,
2542                                            HNS3_CFG_MAC_ADDR_H_S);
2543
2544         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2545
2546         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2547                                             HNS3_CFG_DEFAULT_SPEED_M,
2548                                             HNS3_CFG_DEFAULT_SPEED_S);
2549         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2550                                            HNS3_CFG_RSS_SIZE_M,
2551                                            HNS3_CFG_RSS_SIZE_S);
2552
2553         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2554                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2555
2556         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2557         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2558
2559         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2560                                             HNS3_CFG_SPEED_ABILITY_M,
2561                                             HNS3_CFG_SPEED_ABILITY_S);
2562         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2563                                         HNS3_CFG_UMV_TBL_SPACE_M,
2564                                         HNS3_CFG_UMV_TBL_SPACE_S);
2565         if (!cfg->umv_space)
2566                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2567 }
2568
2569 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2570  * @hw: pointer to struct hns3_hw
2571  * @hcfg: the config structure to be getted
2572  */
2573 static int
2574 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2575 {
2576         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2577         struct hns3_cfg_param_cmd *req;
2578         uint32_t offset;
2579         uint32_t i;
2580         int ret;
2581
2582         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2583                 offset = 0;
2584                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2585                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2586                                           true);
2587                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2588                                i * HNS3_CFG_RD_LEN_BYTES);
2589                 /* Len should be divided by 4 when send to hardware */
2590                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2591                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2592                 req->offset = rte_cpu_to_le_32(offset);
2593         }
2594
2595         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2596         if (ret) {
2597                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2598                 return ret;
2599         }
2600
2601         hns3_parse_cfg(hcfg, desc);
2602
2603         return 0;
2604 }
2605
2606 static int
2607 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2608 {
2609         switch (speed_cmd) {
2610         case HNS3_CFG_SPEED_10M:
2611                 *speed = ETH_SPEED_NUM_10M;
2612                 break;
2613         case HNS3_CFG_SPEED_100M:
2614                 *speed = ETH_SPEED_NUM_100M;
2615                 break;
2616         case HNS3_CFG_SPEED_1G:
2617                 *speed = ETH_SPEED_NUM_1G;
2618                 break;
2619         case HNS3_CFG_SPEED_10G:
2620                 *speed = ETH_SPEED_NUM_10G;
2621                 break;
2622         case HNS3_CFG_SPEED_25G:
2623                 *speed = ETH_SPEED_NUM_25G;
2624                 break;
2625         case HNS3_CFG_SPEED_40G:
2626                 *speed = ETH_SPEED_NUM_40G;
2627                 break;
2628         case HNS3_CFG_SPEED_50G:
2629                 *speed = ETH_SPEED_NUM_50G;
2630                 break;
2631         case HNS3_CFG_SPEED_100G:
2632                 *speed = ETH_SPEED_NUM_100G;
2633                 break;
2634         default:
2635                 return -EINVAL;
2636         }
2637
2638         return 0;
2639 }
2640
2641 static int
2642 hns3_get_board_configuration(struct hns3_hw *hw)
2643 {
2644         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2645         struct hns3_pf *pf = &hns->pf;
2646         struct hns3_cfg cfg;
2647         int ret;
2648
2649         ret = hns3_get_board_cfg(hw, &cfg);
2650         if (ret) {
2651                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2652                 return ret;
2653         }
2654
2655         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2656                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2657                 return -EOPNOTSUPP;
2658         }
2659
2660         hw->mac.media_type = cfg.media_type;
2661         hw->rss_size_max = cfg.rss_size_max;
2662         hw->rss_dis_flag = false;
2663         hw->rx_buf_len = cfg.rx_buf_len;
2664         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2665         hw->mac.phy_addr = cfg.phy_addr;
2666         hw->mac.default_addr_setted = false;
2667         hw->num_tx_desc = cfg.tqp_desc_num;
2668         hw->num_rx_desc = cfg.tqp_desc_num;
2669         hw->dcb_info.num_pg = 1;
2670         hw->dcb_info.hw_pfc_map = 0;
2671
2672         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2673         if (ret) {
2674                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2675                              cfg.default_speed, ret);
2676                 return ret;
2677         }
2678
2679         pf->tc_max = cfg.tc_num;
2680         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2681                 PMD_INIT_LOG(WARNING,
2682                              "Get TC num(%u) from flash, set TC num to 1",
2683                              pf->tc_max);
2684                 pf->tc_max = 1;
2685         }
2686
2687         /* Dev does not support DCB */
2688         if (!hns3_dev_dcb_supported(hw)) {
2689                 pf->tc_max = 1;
2690                 pf->pfc_max = 0;
2691         } else
2692                 pf->pfc_max = pf->tc_max;
2693
2694         hw->dcb_info.num_tc = 1;
2695         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2696                                      hw->tqps_num / hw->dcb_info.num_tc);
2697         hns3_set_bit(hw->hw_tc_map, 0, 1);
2698         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2699
2700         pf->wanted_umv_size = cfg.umv_space;
2701
2702         return ret;
2703 }
2704
2705 static int
2706 hns3_get_configuration(struct hns3_hw *hw)
2707 {
2708         int ret;
2709
2710         ret = hns3_query_function_status(hw);
2711         if (ret) {
2712                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2713                 return ret;
2714         }
2715
2716         /* Get pf resource */
2717         ret = hns3_query_pf_resource(hw);
2718         if (ret) {
2719                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2720                 return ret;
2721         }
2722
2723         ret = hns3_get_board_configuration(hw);
2724         if (ret)
2725                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2726
2727         return ret;
2728 }
2729
2730 static int
2731 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2732                       uint16_t tqp_vid, bool is_pf)
2733 {
2734         struct hns3_tqp_map_cmd *req;
2735         struct hns3_cmd_desc desc;
2736         int ret;
2737
2738         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2739
2740         req = (struct hns3_tqp_map_cmd *)desc.data;
2741         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2742         req->tqp_vf = func_id;
2743         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2744         if (!is_pf)
2745                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2746         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2747
2748         ret = hns3_cmd_send(hw, &desc, 1);
2749         if (ret)
2750                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2751
2752         return ret;
2753 }
2754
2755 static int
2756 hns3_map_tqp(struct hns3_hw *hw)
2757 {
2758         uint16_t tqps_num = hw->total_tqps_num;
2759         uint16_t func_id;
2760         uint16_t tqp_id;
2761         bool is_pf;
2762         int num;
2763         int ret;
2764         int i;
2765
2766         /*
2767          * In current version VF is not supported when PF is driven by DPDK
2768          * driver, so we allocate tqps to PF as much as possible.
2769          */
2770         tqp_id = 0;
2771         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2772         for (func_id = 0; func_id < num; func_id++) {
2773                 is_pf = func_id == 0 ? true : false;
2774                 for (i = 0;
2775                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2776                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2777                                                     is_pf);
2778                         if (ret)
2779                                 return ret;
2780                 }
2781         }
2782
2783         return 0;
2784 }
2785
2786 static int
2787 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2788 {
2789         struct hns3_config_mac_speed_dup_cmd *req;
2790         struct hns3_cmd_desc desc;
2791         int ret;
2792
2793         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2794
2795         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2796
2797         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2798
2799         switch (speed) {
2800         case ETH_SPEED_NUM_10M:
2801                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2802                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2803                 break;
2804         case ETH_SPEED_NUM_100M:
2805                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2806                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2807                 break;
2808         case ETH_SPEED_NUM_1G:
2809                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2810                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2811                 break;
2812         case ETH_SPEED_NUM_10G:
2813                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2814                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2815                 break;
2816         case ETH_SPEED_NUM_25G:
2817                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2818                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2819                 break;
2820         case ETH_SPEED_NUM_40G:
2821                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2822                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2823                 break;
2824         case ETH_SPEED_NUM_50G:
2825                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2826                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2827                 break;
2828         case ETH_SPEED_NUM_100G:
2829                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2830                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2831                 break;
2832         default:
2833                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2834                 return -EINVAL;
2835         }
2836
2837         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2838
2839         ret = hns3_cmd_send(hw, &desc, 1);
2840         if (ret)
2841                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2842
2843         return ret;
2844 }
2845
2846 static int
2847 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2848 {
2849         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2850         struct hns3_pf *pf = &hns->pf;
2851         struct hns3_priv_buf *priv;
2852         uint32_t i, total_size;
2853
2854         total_size = pf->pkt_buf_size;
2855
2856         /* alloc tx buffer for all enabled tc */
2857         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2858                 priv = &buf_alloc->priv_buf[i];
2859
2860                 if (hw->hw_tc_map & BIT(i)) {
2861                         if (total_size < pf->tx_buf_size)
2862                                 return -ENOMEM;
2863
2864                         priv->tx_buf_size = pf->tx_buf_size;
2865                 } else
2866                         priv->tx_buf_size = 0;
2867
2868                 total_size -= priv->tx_buf_size;
2869         }
2870
2871         return 0;
2872 }
2873
2874 static int
2875 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2876 {
2877 /* TX buffer size is unit by 128 byte */
2878 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2879 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2880         struct hns3_tx_buff_alloc_cmd *req;
2881         struct hns3_cmd_desc desc;
2882         uint32_t buf_size;
2883         uint32_t i;
2884         int ret;
2885
2886         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2887
2888         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2889         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2890                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2891
2892                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2893                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2894                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2895         }
2896
2897         ret = hns3_cmd_send(hw, &desc, 1);
2898         if (ret)
2899                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2900
2901         return ret;
2902 }
2903
2904 static int
2905 hns3_get_tc_num(struct hns3_hw *hw)
2906 {
2907         int cnt = 0;
2908         uint8_t i;
2909
2910         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2911                 if (hw->hw_tc_map & BIT(i))
2912                         cnt++;
2913         return cnt;
2914 }
2915
2916 static uint32_t
2917 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2918 {
2919         struct hns3_priv_buf *priv;
2920         uint32_t rx_priv = 0;
2921         int i;
2922
2923         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2924                 priv = &buf_alloc->priv_buf[i];
2925                 if (priv->enable)
2926                         rx_priv += priv->buf_size;
2927         }
2928         return rx_priv;
2929 }
2930
2931 static uint32_t
2932 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2933 {
2934         uint32_t total_tx_size = 0;
2935         uint32_t i;
2936
2937         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2938                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2939
2940         return total_tx_size;
2941 }
2942
2943 /* Get the number of pfc enabled TCs, which have private buffer */
2944 static int
2945 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2946 {
2947         struct hns3_priv_buf *priv;
2948         int cnt = 0;
2949         uint8_t i;
2950
2951         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2952                 priv = &buf_alloc->priv_buf[i];
2953                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2954                         cnt++;
2955         }
2956
2957         return cnt;
2958 }
2959
2960 /* Get the number of pfc disabled TCs, which have private buffer */
2961 static int
2962 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2963                          struct hns3_pkt_buf_alloc *buf_alloc)
2964 {
2965         struct hns3_priv_buf *priv;
2966         int cnt = 0;
2967         uint8_t i;
2968
2969         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2970                 priv = &buf_alloc->priv_buf[i];
2971                 if (hw->hw_tc_map & BIT(i) &&
2972                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2973                         cnt++;
2974         }
2975
2976         return cnt;
2977 }
2978
2979 static bool
2980 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2981                   uint32_t rx_all)
2982 {
2983         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2984         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2985         struct hns3_pf *pf = &hns->pf;
2986         uint32_t shared_buf, aligned_mps;
2987         uint32_t rx_priv;
2988         uint8_t tc_num;
2989         uint8_t i;
2990
2991         tc_num = hns3_get_tc_num(hw);
2992         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2993
2994         if (hns3_dev_dcb_supported(hw))
2995                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2996                                         pf->dv_buf_size;
2997         else
2998                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2999                                         + pf->dv_buf_size;
3000
3001         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3002         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3003                              HNS3_BUF_SIZE_UNIT);
3004
3005         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3006         if (rx_all < rx_priv + shared_std)
3007                 return false;
3008
3009         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3010         buf_alloc->s_buf.buf_size = shared_buf;
3011         if (hns3_dev_dcb_supported(hw)) {
3012                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3013                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3014                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3015                                   HNS3_BUF_SIZE_UNIT);
3016         } else {
3017                 buf_alloc->s_buf.self.high =
3018                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3019                 buf_alloc->s_buf.self.low = aligned_mps;
3020         }
3021
3022         if (hns3_dev_dcb_supported(hw)) {
3023                 hi_thrd = shared_buf - pf->dv_buf_size;
3024
3025                 if (tc_num <= NEED_RESERVE_TC_NUM)
3026                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3027                                         / BUF_MAX_PERCENT;
3028
3029                 if (tc_num)
3030                         hi_thrd = hi_thrd / tc_num;
3031
3032                 hi_thrd = max_t(uint32_t, hi_thrd,
3033                                 HNS3_BUF_MUL_BY * aligned_mps);
3034                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3035                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3036         } else {
3037                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3038                 lo_thrd = aligned_mps;
3039         }
3040
3041         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3042                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3043                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3044         }
3045
3046         return true;
3047 }
3048
3049 static bool
3050 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3051                      struct hns3_pkt_buf_alloc *buf_alloc)
3052 {
3053         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3054         struct hns3_pf *pf = &hns->pf;
3055         struct hns3_priv_buf *priv;
3056         uint32_t aligned_mps;
3057         uint32_t rx_all;
3058         uint8_t i;
3059
3060         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3061         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3062
3063         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3064                 priv = &buf_alloc->priv_buf[i];
3065
3066                 priv->enable = 0;
3067                 priv->wl.low = 0;
3068                 priv->wl.high = 0;
3069                 priv->buf_size = 0;
3070
3071                 if (!(hw->hw_tc_map & BIT(i)))
3072                         continue;
3073
3074                 priv->enable = 1;
3075                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3076                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3077                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3078                                                 HNS3_BUF_SIZE_UNIT);
3079                 } else {
3080                         priv->wl.low = 0;
3081                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3082                                         aligned_mps;
3083                 }
3084
3085                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3086         }
3087
3088         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3089 }
3090
3091 static bool
3092 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3093                              struct hns3_pkt_buf_alloc *buf_alloc)
3094 {
3095         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3096         struct hns3_pf *pf = &hns->pf;
3097         struct hns3_priv_buf *priv;
3098         int no_pfc_priv_num;
3099         uint32_t rx_all;
3100         uint8_t mask;
3101         int i;
3102
3103         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3104         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3105
3106         /* let the last to be cleared first */
3107         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3108                 priv = &buf_alloc->priv_buf[i];
3109                 mask = BIT((uint8_t)i);
3110
3111                 if (hw->hw_tc_map & mask &&
3112                     !(hw->dcb_info.hw_pfc_map & mask)) {
3113                         /* Clear the no pfc TC private buffer */
3114                         priv->wl.low = 0;
3115                         priv->wl.high = 0;
3116                         priv->buf_size = 0;
3117                         priv->enable = 0;
3118                         no_pfc_priv_num--;
3119                 }
3120
3121                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3122                     no_pfc_priv_num == 0)
3123                         break;
3124         }
3125
3126         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3127 }
3128
3129 static bool
3130 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3131                            struct hns3_pkt_buf_alloc *buf_alloc)
3132 {
3133         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3134         struct hns3_pf *pf = &hns->pf;
3135         struct hns3_priv_buf *priv;
3136         uint32_t rx_all;
3137         int pfc_priv_num;
3138         uint8_t mask;
3139         int i;
3140
3141         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3142         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3143
3144         /* let the last to be cleared first */
3145         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3146                 priv = &buf_alloc->priv_buf[i];
3147                 mask = BIT((uint8_t)i);
3148
3149                 if (hw->hw_tc_map & mask &&
3150                     hw->dcb_info.hw_pfc_map & mask) {
3151                         /* Reduce the number of pfc TC with private buffer */
3152                         priv->wl.low = 0;
3153                         priv->enable = 0;
3154                         priv->wl.high = 0;
3155                         priv->buf_size = 0;
3156                         pfc_priv_num--;
3157                 }
3158                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3159                     pfc_priv_num == 0)
3160                         break;
3161         }
3162
3163         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3164 }
3165
3166 static bool
3167 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3168                           struct hns3_pkt_buf_alloc *buf_alloc)
3169 {
3170 #define COMPENSATE_BUFFER       0x3C00
3171 #define COMPENSATE_HALF_MPS_NUM 5
3172 #define PRIV_WL_GAP             0x1800
3173         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3174         struct hns3_pf *pf = &hns->pf;
3175         uint32_t tc_num = hns3_get_tc_num(hw);
3176         uint32_t half_mps = pf->mps >> 1;
3177         struct hns3_priv_buf *priv;
3178         uint32_t min_rx_priv;
3179         uint32_t rx_priv;
3180         uint8_t i;
3181
3182         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3183         if (tc_num)
3184                 rx_priv = rx_priv / tc_num;
3185
3186         if (tc_num <= NEED_RESERVE_TC_NUM)
3187                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3188
3189         /*
3190          * Minimum value of private buffer in rx direction (min_rx_priv) is
3191          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3192          * buffer if rx_priv is greater than min_rx_priv.
3193          */
3194         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3195                         COMPENSATE_HALF_MPS_NUM * half_mps;
3196         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3197         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3198
3199         if (rx_priv < min_rx_priv)
3200                 return false;
3201
3202         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3203                 priv = &buf_alloc->priv_buf[i];
3204
3205                 priv->enable = 0;
3206                 priv->wl.low = 0;
3207                 priv->wl.high = 0;
3208                 priv->buf_size = 0;
3209
3210                 if (!(hw->hw_tc_map & BIT(i)))
3211                         continue;
3212
3213                 priv->enable = 1;
3214                 priv->buf_size = rx_priv;
3215                 priv->wl.high = rx_priv - pf->dv_buf_size;
3216                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3217         }
3218
3219         buf_alloc->s_buf.buf_size = 0;
3220
3221         return true;
3222 }
3223
3224 /*
3225  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3226  * @hw: pointer to struct hns3_hw
3227  * @buf_alloc: pointer to buffer calculation data
3228  * @return: 0: calculate sucessful, negative: fail
3229  */
3230 static int
3231 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3232 {
3233         /* When DCB is not supported, rx private buffer is not allocated. */
3234         if (!hns3_dev_dcb_supported(hw)) {
3235                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3236                 struct hns3_pf *pf = &hns->pf;
3237                 uint32_t rx_all = pf->pkt_buf_size;
3238
3239                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3240                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3241                         return -ENOMEM;
3242
3243                 return 0;
3244         }
3245
3246         /*
3247          * Try to allocate privated packet buffer for all TCs without share
3248          * buffer.
3249          */
3250         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3251                 return 0;
3252
3253         /*
3254          * Try to allocate privated packet buffer for all TCs with share
3255          * buffer.
3256          */
3257         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3258                 return 0;
3259
3260         /*
3261          * For different application scenes, the enabled port number, TC number
3262          * and no_drop TC number are different. In order to obtain the better
3263          * performance, software could allocate the buffer size and configure
3264          * the waterline by tring to decrease the private buffer size according
3265          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3266          * enabled tc.
3267          */
3268         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3269                 return 0;
3270
3271         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3272                 return 0;
3273
3274         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3275                 return 0;
3276
3277         return -ENOMEM;
3278 }
3279
3280 static int
3281 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3282 {
3283         struct hns3_rx_priv_buff_cmd *req;
3284         struct hns3_cmd_desc desc;
3285         uint32_t buf_size;
3286         int ret;
3287         int i;
3288
3289         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3290         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3291
3292         /* Alloc private buffer TCs */
3293         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3294                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3295
3296                 req->buf_num[i] =
3297                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3298                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3299         }
3300
3301         buf_size = buf_alloc->s_buf.buf_size;
3302         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3303                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3304
3305         ret = hns3_cmd_send(hw, &desc, 1);
3306         if (ret)
3307                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3308
3309         return ret;
3310 }
3311
3312 static int
3313 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3314 {
3315 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3316         struct hns3_rx_priv_wl_buf *req;
3317         struct hns3_priv_buf *priv;
3318         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3319         int i, j;
3320         int ret;
3321
3322         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3323                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3324                                           false);
3325                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3326
3327                 /* The first descriptor set the NEXT bit to 1 */
3328                 if (i == 0)
3329                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3330                 else
3331                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3332
3333                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3334                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3335
3336                         priv = &buf_alloc->priv_buf[idx];
3337                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3338                                                         HNS3_BUF_UNIT_S);
3339                         req->tc_wl[j].high |=
3340                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3341                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3342                                                         HNS3_BUF_UNIT_S);
3343                         req->tc_wl[j].low |=
3344                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3345                 }
3346         }
3347
3348         /* Send 2 descriptor at one time */
3349         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3350         if (ret)
3351                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3352                              ret);
3353         return ret;
3354 }
3355
3356 static int
3357 hns3_common_thrd_config(struct hns3_hw *hw,
3358                         struct hns3_pkt_buf_alloc *buf_alloc)
3359 {
3360 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3361         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3362         struct hns3_rx_com_thrd *req;
3363         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3364         struct hns3_tc_thrd *tc;
3365         int tc_idx;
3366         int i, j;
3367         int ret;
3368
3369         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3370                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3371                                           false);
3372                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3373
3374                 /* The first descriptor set the NEXT bit to 1 */
3375                 if (i == 0)
3376                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3377                 else
3378                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3379
3380                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3381                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3382                         tc = &s_buf->tc_thrd[tc_idx];
3383
3384                         req->com_thrd[j].high =
3385                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3386                         req->com_thrd[j].high |=
3387                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3388                         req->com_thrd[j].low =
3389                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3390                         req->com_thrd[j].low |=
3391                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3392                 }
3393         }
3394
3395         /* Send 2 descriptors at one time */
3396         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3397         if (ret)
3398                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3399
3400         return ret;
3401 }
3402
3403 static int
3404 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3405 {
3406         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3407         struct hns3_rx_com_wl *req;
3408         struct hns3_cmd_desc desc;
3409         int ret;
3410
3411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3412
3413         req = (struct hns3_rx_com_wl *)desc.data;
3414         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3415         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3416
3417         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3418         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3419
3420         ret = hns3_cmd_send(hw, &desc, 1);
3421         if (ret)
3422                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3423
3424         return ret;
3425 }
3426
3427 int
3428 hns3_buffer_alloc(struct hns3_hw *hw)
3429 {
3430         struct hns3_pkt_buf_alloc pkt_buf;
3431         int ret;
3432
3433         memset(&pkt_buf, 0, sizeof(pkt_buf));
3434         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3435         if (ret) {
3436                 PMD_INIT_LOG(ERR,
3437                              "could not calc tx buffer size for all TCs %d",
3438                              ret);
3439                 return ret;
3440         }
3441
3442         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3443         if (ret) {
3444                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3445                 return ret;
3446         }
3447
3448         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3449         if (ret) {
3450                 PMD_INIT_LOG(ERR,
3451                              "could not calc rx priv buffer size for all TCs %d",
3452                              ret);
3453                 return ret;
3454         }
3455
3456         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3457         if (ret) {
3458                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3459                 return ret;
3460         }
3461
3462         if (hns3_dev_dcb_supported(hw)) {
3463                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3464                 if (ret) {
3465                         PMD_INIT_LOG(ERR,
3466                                      "could not configure rx private waterline %d",
3467                                      ret);
3468                         return ret;
3469                 }
3470
3471                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3472                 if (ret) {
3473                         PMD_INIT_LOG(ERR,
3474                                      "could not configure common threshold %d",
3475                                      ret);
3476                         return ret;
3477                 }
3478         }
3479
3480         ret = hns3_common_wl_config(hw, &pkt_buf);
3481         if (ret)
3482                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3483                              ret);
3484
3485         return ret;
3486 }
3487
3488 static int
3489 hns3_mac_init(struct hns3_hw *hw)
3490 {
3491         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3492         struct hns3_mac *mac = &hw->mac;
3493         struct hns3_pf *pf = &hns->pf;
3494         int ret;
3495
3496         pf->support_sfp_query = true;
3497         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3498         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3499         if (ret) {
3500                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3501                 return ret;
3502         }
3503
3504         mac->link_status = ETH_LINK_DOWN;
3505
3506         return hns3_config_mtu(hw, pf->mps);
3507 }
3508
3509 static int
3510 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3511 {
3512 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3513 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3514 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3515 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3516         int return_status;
3517
3518         if (cmdq_resp) {
3519                 PMD_INIT_LOG(ERR,
3520                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3521                              cmdq_resp);
3522                 return -EIO;
3523         }
3524
3525         switch (resp_code) {
3526         case HNS3_ETHERTYPE_SUCCESS_ADD:
3527         case HNS3_ETHERTYPE_ALREADY_ADD:
3528                 return_status = 0;
3529                 break;
3530         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3531                 PMD_INIT_LOG(ERR,
3532                              "add mac ethertype failed for manager table overflow.");
3533                 return_status = -EIO;
3534                 break;
3535         case HNS3_ETHERTYPE_KEY_CONFLICT:
3536                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3537                 return_status = -EIO;
3538                 break;
3539         default:
3540                 PMD_INIT_LOG(ERR,
3541                              "add mac ethertype failed for undefined, code=%d.",
3542                              resp_code);
3543                 return_status = -EIO;
3544         }
3545
3546         return return_status;
3547 }
3548
3549 static int
3550 hns3_add_mgr_tbl(struct hns3_hw *hw,
3551                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3552 {
3553         struct hns3_cmd_desc desc;
3554         uint8_t resp_code;
3555         uint16_t retval;
3556         int ret;
3557
3558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3559         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3560
3561         ret = hns3_cmd_send(hw, &desc, 1);
3562         if (ret) {
3563                 PMD_INIT_LOG(ERR,
3564                              "add mac ethertype failed for cmd_send, ret =%d.",
3565                              ret);
3566                 return ret;
3567         }
3568
3569         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3570         retval = rte_le_to_cpu_16(desc.retval);
3571
3572         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3573 }
3574
3575 static void
3576 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3577                      int *table_item_num)
3578 {
3579         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3580
3581         /*
3582          * In current version, we add one item in management table as below:
3583          * 0x0180C200000E -- LLDP MC address
3584          */
3585         tbl = mgr_table;
3586         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3587         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3588         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3589         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3590         tbl->i_port_bitmap = 0x1;
3591         *table_item_num = 1;
3592 }
3593
3594 static int
3595 hns3_init_mgr_tbl(struct hns3_hw *hw)
3596 {
3597 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3598         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3599         int table_item_num;
3600         int ret;
3601         int i;
3602
3603         memset(mgr_table, 0, sizeof(mgr_table));
3604         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3605         for (i = 0; i < table_item_num; i++) {
3606                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3607                 if (ret) {
3608                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3609                                      ret);
3610                         return ret;
3611                 }
3612         }
3613
3614         return 0;
3615 }
3616
3617 static void
3618 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3619                         bool en_mc, bool en_bc, int vport_id)
3620 {
3621         if (!param)
3622                 return;
3623
3624         memset(param, 0, sizeof(struct hns3_promisc_param));
3625         if (en_uc)
3626                 param->enable = HNS3_PROMISC_EN_UC;
3627         if (en_mc)
3628                 param->enable |= HNS3_PROMISC_EN_MC;
3629         if (en_bc)
3630                 param->enable |= HNS3_PROMISC_EN_BC;
3631         param->vf_id = vport_id;
3632 }
3633
3634 static int
3635 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3636 {
3637         struct hns3_promisc_cfg_cmd *req;
3638         struct hns3_cmd_desc desc;
3639         int ret;
3640
3641         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3642
3643         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3644         req->vf_id = param->vf_id;
3645         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3646             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3647
3648         ret = hns3_cmd_send(hw, &desc, 1);
3649         if (ret)
3650                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3651
3652         return ret;
3653 }
3654
3655 static int
3656 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3657 {
3658         struct hns3_promisc_param param;
3659         bool en_bc_pmc = true;
3660         uint8_t vf_id;
3661
3662         /*
3663          * In current version VF is not supported when PF is driven by DPDK
3664          * driver, the PF-related vf_id is 0, just need to configure parameters
3665          * for vf_id 0.
3666          */
3667         vf_id = 0;
3668
3669         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3670         return hns3_cmd_set_promisc_mode(hw, &param);
3671 }
3672
3673 static int
3674 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3675 {
3676         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3677         struct hns3_pf *pf = &hns->pf;
3678         struct hns3_promisc_param param;
3679         uint16_t func_id;
3680         int ret;
3681
3682         /* func_id 0 is denoted PF, the VFs start from 1 */
3683         for (func_id = 1; func_id < pf->func_num; func_id++) {
3684                 hns3_promisc_param_init(&param, false, false, false, func_id);
3685                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3686                 if (ret)
3687                         return ret;
3688         }
3689
3690         return 0;
3691 }
3692
3693 static int
3694 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3695 {
3696         struct hns3_adapter *hns = dev->data->dev_private;
3697         struct hns3_hw *hw = &hns->hw;
3698         int ret;
3699
3700         rte_spinlock_lock(&hw->lock);
3701         ret = hns3_set_promisc_mode(hw, true, true);
3702         rte_spinlock_unlock(&hw->lock);
3703         if (ret)
3704                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3705                          ret);
3706
3707         return ret;
3708 }
3709
3710 static int
3711 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3712 {
3713         bool allmulti = dev->data->all_multicast ? true : false;
3714         struct hns3_adapter *hns = dev->data->dev_private;
3715         struct hns3_hw *hw = &hns->hw;
3716         int ret;
3717
3718         /* If now in all_multicast mode, must remain in all_multicast mode. */
3719         rte_spinlock_lock(&hw->lock);
3720         ret = hns3_set_promisc_mode(hw, false, allmulti);
3721         rte_spinlock_unlock(&hw->lock);
3722         if (ret)
3723                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3724                          ret);
3725
3726         return ret;
3727 }
3728
3729 static int
3730 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3731 {
3732         struct hns3_adapter *hns = dev->data->dev_private;
3733         struct hns3_hw *hw = &hns->hw;
3734         int ret;
3735
3736         if (dev->data->promiscuous)
3737                 return 0;
3738
3739         rte_spinlock_lock(&hw->lock);
3740         ret = hns3_set_promisc_mode(hw, false, true);
3741         rte_spinlock_unlock(&hw->lock);
3742         if (ret)
3743                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3744                          ret);
3745
3746         return ret;
3747 }
3748
3749 static int
3750 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3751 {
3752         struct hns3_adapter *hns = dev->data->dev_private;
3753         struct hns3_hw *hw = &hns->hw;
3754         int ret;
3755
3756         /* If now in promiscuous mode, must remain in all_multicast mode. */
3757         if (dev->data->promiscuous)
3758                 return 0;
3759
3760         rte_spinlock_lock(&hw->lock);
3761         ret = hns3_set_promisc_mode(hw, false, false);
3762         rte_spinlock_unlock(&hw->lock);
3763         if (ret)
3764                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3765                          ret);
3766
3767         return ret;
3768 }
3769
3770 static int
3771 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3772 {
3773         struct hns3_hw *hw = &hns->hw;
3774         bool allmulti = hw->data->all_multicast ? true : false;
3775
3776         if (hw->data->promiscuous)
3777                 return hns3_set_promisc_mode(hw, true, true);
3778
3779         return hns3_set_promisc_mode(hw, false, allmulti);
3780 }
3781
3782 static int
3783 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3784 {
3785         struct hns3_sfp_speed_cmd *resp;
3786         struct hns3_cmd_desc desc;
3787         int ret;
3788
3789         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3790         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3791         ret = hns3_cmd_send(hw, &desc, 1);
3792         if (ret == -EOPNOTSUPP) {
3793                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3794                 return ret;
3795         } else if (ret) {
3796                 hns3_err(hw, "get sfp speed failed %d", ret);
3797                 return ret;
3798         }
3799
3800         *speed = resp->sfp_speed;
3801
3802         return 0;
3803 }
3804
3805 static uint8_t
3806 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3807 {
3808         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3809                 duplex = ETH_LINK_FULL_DUPLEX;
3810
3811         return duplex;
3812 }
3813
3814 static int
3815 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3816 {
3817         struct hns3_mac *mac = &hw->mac;
3818         int ret;
3819
3820         duplex = hns3_check_speed_dup(duplex, speed);
3821         if (mac->link_speed == speed && mac->link_duplex == duplex)
3822                 return 0;
3823
3824         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3825         if (ret)
3826                 return ret;
3827
3828         mac->link_speed = speed;
3829         mac->link_duplex = duplex;
3830
3831         return 0;
3832 }
3833
3834 static int
3835 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3836 {
3837         struct hns3_adapter *hns = eth_dev->data->dev_private;
3838         struct hns3_hw *hw = &hns->hw;
3839         struct hns3_pf *pf = &hns->pf;
3840         uint32_t speed;
3841         int ret;
3842
3843         /* If IMP do not support get SFP/qSFP speed, return directly */
3844         if (!pf->support_sfp_query)
3845                 return 0;
3846
3847         ret = hns3_get_sfp_speed(hw, &speed);
3848         if (ret == -EOPNOTSUPP) {
3849                 pf->support_sfp_query = false;
3850                 return ret;
3851         } else if (ret)
3852                 return ret;
3853
3854         if (speed == ETH_SPEED_NUM_NONE)
3855                 return 0; /* do nothing if no SFP */
3856
3857         /* Config full duplex for SFP */
3858         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3859 }
3860
3861 static int
3862 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3863 {
3864         struct hns3_config_mac_mode_cmd *req;
3865         struct hns3_cmd_desc desc;
3866         uint32_t loop_en = 0;
3867         uint8_t val = 0;
3868         int ret;
3869
3870         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3871
3872         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3873         if (enable)
3874                 val = 1;
3875         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3876         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3877         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3878         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3879         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3880         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3881         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3882         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3883         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3884         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3885         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3886         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3887         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3888         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3889         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3890
3891         ret = hns3_cmd_send(hw, &desc, 1);
3892         if (ret)
3893                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3894
3895         return ret;
3896 }
3897
3898 static int
3899 hns3_get_mac_link_status(struct hns3_hw *hw)
3900 {
3901         struct hns3_link_status_cmd *req;
3902         struct hns3_cmd_desc desc;
3903         int link_status;
3904         int ret;
3905
3906         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3907         ret = hns3_cmd_send(hw, &desc, 1);
3908         if (ret) {
3909                 hns3_err(hw, "get link status cmd failed %d", ret);
3910                 return ETH_LINK_DOWN;
3911         }
3912
3913         req = (struct hns3_link_status_cmd *)desc.data;
3914         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3915
3916         return !!link_status;
3917 }
3918
3919 void
3920 hns3_update_link_status(struct hns3_hw *hw)
3921 {
3922         int state;
3923
3924         state = hns3_get_mac_link_status(hw);
3925         if (state != hw->mac.link_status) {
3926                 hw->mac.link_status = state;
3927                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3928         }
3929 }
3930
3931 static void
3932 hns3_service_handler(void *param)
3933 {
3934         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3935         struct hns3_adapter *hns = eth_dev->data->dev_private;
3936         struct hns3_hw *hw = &hns->hw;
3937
3938         if (!hns3_is_reset_pending(hns)) {
3939                 hns3_update_speed_duplex(eth_dev);
3940                 hns3_update_link_status(hw);
3941         } else
3942                 hns3_warn(hw, "Cancel the query when reset is pending");
3943
3944         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3945 }
3946
3947 static int
3948 hns3_init_hardware(struct hns3_adapter *hns)
3949 {
3950         struct hns3_hw *hw = &hns->hw;
3951         int ret;
3952
3953         ret = hns3_map_tqp(hw);
3954         if (ret) {
3955                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3956                 return ret;
3957         }
3958
3959         ret = hns3_init_umv_space(hw);
3960         if (ret) {
3961                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3962                 return ret;
3963         }
3964
3965         ret = hns3_mac_init(hw);
3966         if (ret) {
3967                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3968                 goto err_mac_init;
3969         }
3970
3971         ret = hns3_init_mgr_tbl(hw);
3972         if (ret) {
3973                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3974                 goto err_mac_init;
3975         }
3976
3977         ret = hns3_set_promisc_mode(hw, false, false);
3978         if (ret) {
3979                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3980                 goto err_mac_init;
3981         }
3982
3983         ret = hns3_clear_all_vfs_promisc_mode(hw);
3984         if (ret) {
3985                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3986                              ret);
3987                 goto err_mac_init;
3988         }
3989
3990         ret = hns3_init_vlan_config(hns);
3991         if (ret) {
3992                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3993                 goto err_mac_init;
3994         }
3995
3996         ret = hns3_dcb_init(hw);
3997         if (ret) {
3998                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3999                 goto err_mac_init;
4000         }
4001
4002         ret = hns3_init_fd_config(hns);
4003         if (ret) {
4004                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4005                 goto err_mac_init;
4006         }
4007
4008         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4009         if (ret) {
4010                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4011                 goto err_mac_init;
4012         }
4013
4014         ret = hns3_config_gro(hw, false);
4015         if (ret) {
4016                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4017                 goto err_mac_init;
4018         }
4019         return 0;
4020
4021 err_mac_init:
4022         hns3_uninit_umv_space(hw);
4023         return ret;
4024 }
4025
4026 static int
4027 hns3_init_pf(struct rte_eth_dev *eth_dev)
4028 {
4029         struct rte_device *dev = eth_dev->device;
4030         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4031         struct hns3_adapter *hns = eth_dev->data->dev_private;
4032         struct hns3_hw *hw = &hns->hw;
4033         int ret;
4034
4035         PMD_INIT_FUNC_TRACE();
4036
4037         /* Get hardware io base address from pcie BAR2 IO space */
4038         hw->io_base = pci_dev->mem_resource[2].addr;
4039
4040         /* Firmware command queue initialize */
4041         ret = hns3_cmd_init_queue(hw);
4042         if (ret) {
4043                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4044                 goto err_cmd_init_queue;
4045         }
4046
4047         hns3_clear_all_event_cause(hw);
4048
4049         /* Firmware command initialize */
4050         ret = hns3_cmd_init(hw);
4051         if (ret) {
4052                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4053                 goto err_cmd_init;
4054         }
4055
4056         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4057                                          hns3_interrupt_handler,
4058                                          eth_dev);
4059         if (ret) {
4060                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4061                 goto err_intr_callback_register;
4062         }
4063
4064         /* Enable interrupt */
4065         rte_intr_enable(&pci_dev->intr_handle);
4066         hns3_pf_enable_irq0(hw);
4067
4068         /* Get configuration */
4069         ret = hns3_get_configuration(hw);
4070         if (ret) {
4071                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4072                 goto err_get_config;
4073         }
4074
4075         ret = hns3_init_hardware(hns);
4076         if (ret) {
4077                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4078                 goto err_get_config;
4079         }
4080
4081         /* Initialize flow director filter list & hash */
4082         ret = hns3_fdir_filter_init(hns);
4083         if (ret) {
4084                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4085                 goto err_hw_init;
4086         }
4087
4088         hns3_set_default_rss_args(hw);
4089
4090         ret = hns3_enable_hw_error_intr(hns, true);
4091         if (ret) {
4092                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4093                              ret);
4094                 goto err_fdir;
4095         }
4096
4097         /*
4098          * In the initialization clearing the all hardware mapping relationship
4099          * configurations between queues and interrupt vectors is needed, so
4100          * some error caused by the residual configurations, such as the
4101          * unexpected interrupt, can be avoid.
4102          */
4103         ret = hns3_init_ring_with_vector(hw);
4104         if (ret)
4105                 goto err_fdir;
4106
4107         return 0;
4108
4109 err_fdir:
4110         hns3_fdir_filter_uninit(hns);
4111 err_hw_init:
4112         hns3_uninit_umv_space(hw);
4113
4114 err_get_config:
4115         hns3_pf_disable_irq0(hw);
4116         rte_intr_disable(&pci_dev->intr_handle);
4117         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4118                              eth_dev);
4119 err_intr_callback_register:
4120 err_cmd_init:
4121         hns3_cmd_uninit(hw);
4122         hns3_cmd_destroy_queue(hw);
4123 err_cmd_init_queue:
4124         hw->io_base = NULL;
4125
4126         return ret;
4127 }
4128
4129 static void
4130 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4131 {
4132         struct hns3_adapter *hns = eth_dev->data->dev_private;
4133         struct rte_device *dev = eth_dev->device;
4134         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4135         struct hns3_hw *hw = &hns->hw;
4136
4137         PMD_INIT_FUNC_TRACE();
4138
4139         hns3_enable_hw_error_intr(hns, false);
4140         hns3_rss_uninit(hns);
4141         hns3_fdir_filter_uninit(hns);
4142         hns3_uninit_umv_space(hw);
4143         hns3_pf_disable_irq0(hw);
4144         rte_intr_disable(&pci_dev->intr_handle);
4145         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4146                              eth_dev);
4147         hns3_cmd_uninit(hw);
4148         hns3_cmd_destroy_queue(hw);
4149         hw->io_base = NULL;
4150 }
4151
4152 static int
4153 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4154 {
4155         struct hns3_hw *hw = &hns->hw;
4156         int ret;
4157
4158         ret = hns3_dcb_cfg_update(hns);
4159         if (ret)
4160                 return ret;
4161
4162         /* Enable queues */
4163         ret = hns3_start_queues(hns, reset_queue);
4164         if (ret) {
4165                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4166                 return ret;
4167         }
4168
4169         /* Enable MAC */
4170         ret = hns3_cfg_mac_mode(hw, true);
4171         if (ret) {
4172                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4173                 goto err_config_mac_mode;
4174         }
4175         return 0;
4176
4177 err_config_mac_mode:
4178         hns3_stop_queues(hns, true);
4179         return ret;
4180 }
4181
4182 static int
4183 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4184 {
4185         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4187         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4189         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4190         uint32_t intr_vector;
4191         uint16_t q_id;
4192         int ret;
4193
4194         if (dev->data->dev_conf.intr_conf.rxq == 0)
4195                 return 0;
4196
4197         /* disable uio/vfio intr/eventfd mapping */
4198         rte_intr_disable(intr_handle);
4199
4200         /* check and configure queue intr-vector mapping */
4201         if (rte_intr_cap_multiple(intr_handle) ||
4202             !RTE_ETH_DEV_SRIOV(dev).active) {
4203                 intr_vector = hw->used_rx_queues;
4204                 /* creates event fd for each intr vector when MSIX is used */
4205                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4206                         return -EINVAL;
4207         }
4208         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4209                 intr_handle->intr_vec =
4210                         rte_zmalloc("intr_vec",
4211                                     hw->used_rx_queues * sizeof(int), 0);
4212                 if (intr_handle->intr_vec == NULL) {
4213                         hns3_err(hw, "Failed to allocate %d rx_queues"
4214                                      " intr_vec", hw->used_rx_queues);
4215                         ret = -ENOMEM;
4216                         goto alloc_intr_vec_error;
4217                 }
4218         }
4219
4220         if (rte_intr_allow_others(intr_handle)) {
4221                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4222                 base = RTE_INTR_VEC_RXTX_OFFSET;
4223         }
4224         if (rte_intr_dp_is_en(intr_handle)) {
4225                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4226                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4227                                                          HNS3_RING_TYPE_RX,
4228                                                          q_id);
4229                         if (ret)
4230                                 goto bind_vector_error;
4231                         intr_handle->intr_vec[q_id] = vec;
4232                         if (vec < base + intr_handle->nb_efd - 1)
4233                                 vec++;
4234                 }
4235         }
4236         rte_intr_enable(intr_handle);
4237         return 0;
4238
4239 bind_vector_error:
4240         rte_intr_efd_disable(intr_handle);
4241         if (intr_handle->intr_vec) {
4242                 free(intr_handle->intr_vec);
4243                 intr_handle->intr_vec = NULL;
4244         }
4245         return ret;
4246 alloc_intr_vec_error:
4247         rte_intr_efd_disable(intr_handle);
4248         return ret;
4249 }
4250
4251 static void
4252 hns3_restore_filter(struct rte_eth_dev *dev)
4253 {
4254         hns3_restore_rss_filter(dev);
4255 }
4256
4257 static int
4258 hns3_dev_start(struct rte_eth_dev *dev)
4259 {
4260         struct hns3_adapter *hns = dev->data->dev_private;
4261         struct hns3_hw *hw = &hns->hw;
4262         int ret;
4263
4264         PMD_INIT_FUNC_TRACE();
4265         if (rte_atomic16_read(&hw->reset.resetting))
4266                 return -EBUSY;
4267
4268         rte_spinlock_lock(&hw->lock);
4269         hw->adapter_state = HNS3_NIC_STARTING;
4270
4271         ret = hns3_do_start(hns, true);
4272         if (ret) {
4273                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4274                 rte_spinlock_unlock(&hw->lock);
4275                 return ret;
4276         }
4277
4278         hw->adapter_state = HNS3_NIC_STARTED;
4279         rte_spinlock_unlock(&hw->lock);
4280
4281         ret = hns3_map_rx_interrupt(dev);
4282         if (ret)
4283                 return ret;
4284         hns3_set_rxtx_function(dev);
4285         hns3_mp_req_start_rxtx(dev);
4286         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4287
4288         hns3_restore_filter(dev);
4289
4290         hns3_info(hw, "hns3 dev start successful!");
4291         return 0;
4292 }
4293
4294 static int
4295 hns3_do_stop(struct hns3_adapter *hns)
4296 {
4297         struct hns3_hw *hw = &hns->hw;
4298         bool reset_queue;
4299         int ret;
4300
4301         ret = hns3_cfg_mac_mode(hw, false);
4302         if (ret)
4303                 return ret;
4304         hw->mac.link_status = ETH_LINK_DOWN;
4305
4306         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4307                 hns3_configure_all_mac_addr(hns, true);
4308                 reset_queue = true;
4309         } else
4310                 reset_queue = false;
4311         hw->mac.default_addr_setted = false;
4312         return hns3_stop_queues(hns, reset_queue);
4313 }
4314
4315 static void
4316 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4317 {
4318         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4320         struct hns3_adapter *hns = dev->data->dev_private;
4321         struct hns3_hw *hw = &hns->hw;
4322         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4323         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4324         uint16_t q_id;
4325
4326         if (dev->data->dev_conf.intr_conf.rxq == 0)
4327                 return;
4328
4329         /* unmap the ring with vector */
4330         if (rte_intr_allow_others(intr_handle)) {
4331                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4332                 base = RTE_INTR_VEC_RXTX_OFFSET;
4333         }
4334         if (rte_intr_dp_is_en(intr_handle)) {
4335                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4336                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4337                                                          HNS3_RING_TYPE_RX,
4338                                                          q_id);
4339                         if (vec < base + intr_handle->nb_efd - 1)
4340                                 vec++;
4341                 }
4342         }
4343         /* Clean datapath event and queue/vec mapping */
4344         rte_intr_efd_disable(intr_handle);
4345         if (intr_handle->intr_vec) {
4346                 rte_free(intr_handle->intr_vec);
4347                 intr_handle->intr_vec = NULL;
4348         }
4349 }
4350
4351 static void
4352 hns3_dev_stop(struct rte_eth_dev *dev)
4353 {
4354         struct hns3_adapter *hns = dev->data->dev_private;
4355         struct hns3_hw *hw = &hns->hw;
4356
4357         PMD_INIT_FUNC_TRACE();
4358
4359         hw->adapter_state = HNS3_NIC_STOPPING;
4360         hns3_set_rxtx_function(dev);
4361         rte_wmb();
4362         /* Disable datapath on secondary process. */
4363         hns3_mp_req_stop_rxtx(dev);
4364         /* Prevent crashes when queues are still in use. */
4365         rte_delay_ms(hw->tqps_num);
4366
4367         rte_spinlock_lock(&hw->lock);
4368         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4369                 hns3_do_stop(hns);
4370                 hns3_dev_release_mbufs(hns);
4371                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4372         }
4373         rte_eal_alarm_cancel(hns3_service_handler, dev);
4374         rte_spinlock_unlock(&hw->lock);
4375         hns3_unmap_rx_interrupt(dev);
4376 }
4377
4378 static void
4379 hns3_dev_close(struct rte_eth_dev *eth_dev)
4380 {
4381         struct hns3_adapter *hns = eth_dev->data->dev_private;
4382         struct hns3_hw *hw = &hns->hw;
4383
4384         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4385                 rte_free(eth_dev->process_private);
4386                 eth_dev->process_private = NULL;
4387                 return;
4388         }
4389
4390         if (hw->adapter_state == HNS3_NIC_STARTED)
4391                 hns3_dev_stop(eth_dev);
4392
4393         hw->adapter_state = HNS3_NIC_CLOSING;
4394         hns3_reset_abort(hns);
4395         hw->adapter_state = HNS3_NIC_CLOSED;
4396
4397         hns3_configure_all_mc_mac_addr(hns, true);
4398         hns3_remove_all_vlan_table(hns);
4399         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4400         hns3_uninit_pf(eth_dev);
4401         hns3_free_all_queues(eth_dev);
4402         rte_free(hw->reset.wait_data);
4403         rte_free(eth_dev->process_private);
4404         eth_dev->process_private = NULL;
4405         hns3_mp_uninit_primary();
4406         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4407 }
4408
4409 static int
4410 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4411 {
4412         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4414
4415         fc_conf->pause_time = pf->pause_time;
4416
4417         /* return fc current mode */
4418         switch (hw->current_mode) {
4419         case HNS3_FC_FULL:
4420                 fc_conf->mode = RTE_FC_FULL;
4421                 break;
4422         case HNS3_FC_TX_PAUSE:
4423                 fc_conf->mode = RTE_FC_TX_PAUSE;
4424                 break;
4425         case HNS3_FC_RX_PAUSE:
4426                 fc_conf->mode = RTE_FC_RX_PAUSE;
4427                 break;
4428         case HNS3_FC_NONE:
4429         default:
4430                 fc_conf->mode = RTE_FC_NONE;
4431                 break;
4432         }
4433
4434         return 0;
4435 }
4436
4437 static void
4438 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4439 {
4440         switch (mode) {
4441         case RTE_FC_NONE:
4442                 hw->requested_mode = HNS3_FC_NONE;
4443                 break;
4444         case RTE_FC_RX_PAUSE:
4445                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4446                 break;
4447         case RTE_FC_TX_PAUSE:
4448                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4449                 break;
4450         case RTE_FC_FULL:
4451                 hw->requested_mode = HNS3_FC_FULL;
4452                 break;
4453         default:
4454                 hw->requested_mode = HNS3_FC_NONE;
4455                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4456                           "configured to RTE_FC_NONE", mode);
4457                 break;
4458         }
4459 }
4460
4461 static int
4462 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4463 {
4464         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4465         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4466         int ret;
4467
4468         if (fc_conf->high_water || fc_conf->low_water ||
4469             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4470                 hns3_err(hw, "Unsupported flow control settings specified, "
4471                          "high_water(%u), low_water(%u), send_xon(%u) and "
4472                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4473                          fc_conf->high_water, fc_conf->low_water,
4474                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4475                 return -EINVAL;
4476         }
4477         if (fc_conf->autoneg) {
4478                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4479                 return -EINVAL;
4480         }
4481         if (!fc_conf->pause_time) {
4482                 hns3_err(hw, "Invalid pause time %d setting.",
4483                          fc_conf->pause_time);
4484                 return -EINVAL;
4485         }
4486
4487         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4488             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4489                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4490                          "current_fc_status = %d", hw->current_fc_status);
4491                 return -EOPNOTSUPP;
4492         }
4493
4494         hns3_get_fc_mode(hw, fc_conf->mode);
4495         if (hw->requested_mode == hw->current_mode &&
4496             pf->pause_time == fc_conf->pause_time)
4497                 return 0;
4498
4499         rte_spinlock_lock(&hw->lock);
4500         ret = hns3_fc_enable(dev, fc_conf);
4501         rte_spinlock_unlock(&hw->lock);
4502
4503         return ret;
4504 }
4505
4506 static int
4507 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4508                             struct rte_eth_pfc_conf *pfc_conf)
4509 {
4510         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4512         uint8_t priority;
4513         int ret;
4514
4515         if (!hns3_dev_dcb_supported(hw)) {
4516                 hns3_err(hw, "This port does not support dcb configurations.");
4517                 return -EOPNOTSUPP;
4518         }
4519
4520         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4521             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4522                 hns3_err(hw, "Unsupported flow control settings specified, "
4523                          "high_water(%u), low_water(%u), send_xon(%u) and "
4524                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4525                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4526                          pfc_conf->fc.send_xon,
4527                          pfc_conf->fc.mac_ctrl_frame_fwd);
4528                 return -EINVAL;
4529         }
4530         if (pfc_conf->fc.autoneg) {
4531                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4532                 return -EINVAL;
4533         }
4534         if (pfc_conf->fc.pause_time == 0) {
4535                 hns3_err(hw, "Invalid pause time %d setting.",
4536                          pfc_conf->fc.pause_time);
4537                 return -EINVAL;
4538         }
4539
4540         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4541             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4542                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4543                              "current_fc_status = %d", hw->current_fc_status);
4544                 return -EOPNOTSUPP;
4545         }
4546
4547         priority = pfc_conf->priority;
4548         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4549         if (hw->dcb_info.pfc_en & BIT(priority) &&
4550             hw->requested_mode == hw->current_mode &&
4551             pfc_conf->fc.pause_time == pf->pause_time)
4552                 return 0;
4553
4554         rte_spinlock_lock(&hw->lock);
4555         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4556         rte_spinlock_unlock(&hw->lock);
4557
4558         return ret;
4559 }
4560
4561 static int
4562 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4563 {
4564         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4566         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4567         int i;
4568
4569         rte_spinlock_lock(&hw->lock);
4570         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4571                 dcb_info->nb_tcs = pf->local_max_tc;
4572         else
4573                 dcb_info->nb_tcs = 1;
4574
4575         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4576                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4577         for (i = 0; i < dcb_info->nb_tcs; i++)
4578                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4579
4580         for (i = 0; i < hw->num_tc; i++) {
4581                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4582                 dcb_info->tc_queue.tc_txq[0][i].base =
4583                                                 hw->tc_queue[i].tqp_offset;
4584                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4585                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4586                                                 hw->tc_queue[i].tqp_count;
4587         }
4588         rte_spinlock_unlock(&hw->lock);
4589
4590         return 0;
4591 }
4592
4593 static int
4594 hns3_reinit_dev(struct hns3_adapter *hns)
4595 {
4596         struct hns3_hw *hw = &hns->hw;
4597         int ret;
4598
4599         ret = hns3_cmd_init(hw);
4600         if (ret) {
4601                 hns3_err(hw, "Failed to init cmd: %d", ret);
4602                 return ret;
4603         }
4604
4605         ret = hns3_reset_all_queues(hns);
4606         if (ret) {
4607                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4608                 return ret;
4609         }
4610
4611         ret = hns3_init_hardware(hns);
4612         if (ret) {
4613                 hns3_err(hw, "Failed to init hardware: %d", ret);
4614                 return ret;
4615         }
4616
4617         ret = hns3_enable_hw_error_intr(hns, true);
4618         if (ret) {
4619                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4620                              ret);
4621                 return ret;
4622         }
4623         hns3_info(hw, "Reset done, driver initialization finished.");
4624
4625         return 0;
4626 }
4627
4628 static bool
4629 is_pf_reset_done(struct hns3_hw *hw)
4630 {
4631         uint32_t val, reg, reg_bit;
4632
4633         switch (hw->reset.level) {
4634         case HNS3_IMP_RESET:
4635                 reg = HNS3_GLOBAL_RESET_REG;
4636                 reg_bit = HNS3_IMP_RESET_BIT;
4637                 break;
4638         case HNS3_GLOBAL_RESET:
4639                 reg = HNS3_GLOBAL_RESET_REG;
4640                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4641                 break;
4642         case HNS3_FUNC_RESET:
4643                 reg = HNS3_FUN_RST_ING;
4644                 reg_bit = HNS3_FUN_RST_ING_B;
4645                 break;
4646         case HNS3_FLR_RESET:
4647         default:
4648                 hns3_err(hw, "Wait for unsupported reset level: %d",
4649                          hw->reset.level);
4650                 return true;
4651         }
4652         val = hns3_read_dev(hw, reg);
4653         if (hns3_get_bit(val, reg_bit))
4654                 return false;
4655         else
4656                 return true;
4657 }
4658
4659 bool
4660 hns3_is_reset_pending(struct hns3_adapter *hns)
4661 {
4662         struct hns3_hw *hw = &hns->hw;
4663         enum hns3_reset_level reset;
4664
4665         hns3_check_event_cause(hns, NULL);
4666         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4667         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4668                 hns3_warn(hw, "High level reset %d is pending", reset);
4669                 return true;
4670         }
4671         reset = hns3_get_reset_level(hns, &hw->reset.request);
4672         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4673                 hns3_warn(hw, "High level reset %d is request", reset);
4674                 return true;
4675         }
4676         return false;
4677 }
4678
4679 static int
4680 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4681 {
4682         struct hns3_hw *hw = &hns->hw;
4683         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4684         struct timeval tv;
4685
4686         if (wait_data->result == HNS3_WAIT_SUCCESS)
4687                 return 0;
4688         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4689                 gettimeofday(&tv, NULL);
4690                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4691                           tv.tv_sec, tv.tv_usec);
4692                 return -ETIME;
4693         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4694                 return -EAGAIN;
4695
4696         wait_data->hns = hns;
4697         wait_data->check_completion = is_pf_reset_done;
4698         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4699                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4700         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4701         wait_data->count = HNS3_RESET_WAIT_CNT;
4702         wait_data->result = HNS3_WAIT_REQUEST;
4703         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4704         return -EAGAIN;
4705 }
4706
4707 static int
4708 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4709 {
4710         struct hns3_cmd_desc desc;
4711         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4712
4713         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4714         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4715         req->fun_reset_vfid = func_id;
4716
4717         return hns3_cmd_send(hw, &desc, 1);
4718 }
4719
4720 static int
4721 hns3_imp_reset_cmd(struct hns3_hw *hw)
4722 {
4723         struct hns3_cmd_desc desc;
4724
4725         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4726         desc.data[0] = 0xeedd;
4727
4728         return hns3_cmd_send(hw, &desc, 1);
4729 }
4730
4731 static void
4732 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4733 {
4734         struct hns3_hw *hw = &hns->hw;
4735         struct timeval tv;
4736         uint32_t val;
4737
4738         gettimeofday(&tv, NULL);
4739         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4740             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4741                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4742                           tv.tv_sec, tv.tv_usec);
4743                 return;
4744         }
4745
4746         switch (reset_level) {
4747         case HNS3_IMP_RESET:
4748                 hns3_imp_reset_cmd(hw);
4749                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4750                           tv.tv_sec, tv.tv_usec);
4751                 break;
4752         case HNS3_GLOBAL_RESET:
4753                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4754                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4755                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4756                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4757                           tv.tv_sec, tv.tv_usec);
4758                 break;
4759         case HNS3_FUNC_RESET:
4760                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4761                           tv.tv_sec, tv.tv_usec);
4762                 /* schedule again to check later */
4763                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4764                 hns3_schedule_reset(hns);
4765                 break;
4766         default:
4767                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4768                 return;
4769         }
4770         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4771 }
4772
4773 static enum hns3_reset_level
4774 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4775 {
4776         struct hns3_hw *hw = &hns->hw;
4777         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4778
4779         /* Return the highest priority reset level amongst all */
4780         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4781                 reset_level = HNS3_IMP_RESET;
4782         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4783                 reset_level = HNS3_GLOBAL_RESET;
4784         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4785                 reset_level = HNS3_FUNC_RESET;
4786         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4787                 reset_level = HNS3_FLR_RESET;
4788
4789         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4790                 return HNS3_NONE_RESET;
4791
4792         return reset_level;
4793 }
4794
4795 static int
4796 hns3_prepare_reset(struct hns3_adapter *hns)
4797 {
4798         struct hns3_hw *hw = &hns->hw;
4799         uint32_t reg_val;
4800         int ret;
4801
4802         switch (hw->reset.level) {
4803         case HNS3_FUNC_RESET:
4804                 ret = hns3_func_reset_cmd(hw, 0);
4805                 if (ret)
4806                         return ret;
4807
4808                 /*
4809                  * After performaning pf reset, it is not necessary to do the
4810                  * mailbox handling or send any command to firmware, because
4811                  * any mailbox handling or command to firmware is only valid
4812                  * after hns3_cmd_init is called.
4813                  */
4814                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4815                 hw->reset.stats.request_cnt++;
4816                 break;
4817         case HNS3_IMP_RESET:
4818                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4819                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4820                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4821                 break;
4822         default:
4823                 break;
4824         }
4825         return 0;
4826 }
4827
4828 static int
4829 hns3_set_rst_done(struct hns3_hw *hw)
4830 {
4831         struct hns3_pf_rst_done_cmd *req;
4832         struct hns3_cmd_desc desc;
4833
4834         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4835         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4836         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4837         return hns3_cmd_send(hw, &desc, 1);
4838 }
4839
4840 static int
4841 hns3_stop_service(struct hns3_adapter *hns)
4842 {
4843         struct hns3_hw *hw = &hns->hw;
4844         struct rte_eth_dev *eth_dev;
4845
4846         eth_dev = &rte_eth_devices[hw->data->port_id];
4847         if (hw->adapter_state == HNS3_NIC_STARTED)
4848                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4849         hw->mac.link_status = ETH_LINK_DOWN;
4850
4851         hns3_set_rxtx_function(eth_dev);
4852         rte_wmb();
4853         /* Disable datapath on secondary process. */
4854         hns3_mp_req_stop_rxtx(eth_dev);
4855         rte_delay_ms(hw->tqps_num);
4856
4857         rte_spinlock_lock(&hw->lock);
4858         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4859             hw->adapter_state == HNS3_NIC_STOPPING) {
4860                 hns3_do_stop(hns);
4861                 hw->reset.mbuf_deferred_free = true;
4862         } else
4863                 hw->reset.mbuf_deferred_free = false;
4864
4865         /*
4866          * It is cumbersome for hardware to pick-and-choose entries for deletion
4867          * from table space. Hence, for function reset software intervention is
4868          * required to delete the entries
4869          */
4870         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4871                 hns3_configure_all_mc_mac_addr(hns, true);
4872         rte_spinlock_unlock(&hw->lock);
4873
4874         return 0;
4875 }
4876
4877 static int
4878 hns3_start_service(struct hns3_adapter *hns)
4879 {
4880         struct hns3_hw *hw = &hns->hw;
4881         struct rte_eth_dev *eth_dev;
4882
4883         if (hw->reset.level == HNS3_IMP_RESET ||
4884             hw->reset.level == HNS3_GLOBAL_RESET)
4885                 hns3_set_rst_done(hw);
4886         eth_dev = &rte_eth_devices[hw->data->port_id];
4887         hns3_set_rxtx_function(eth_dev);
4888         hns3_mp_req_start_rxtx(eth_dev);
4889         if (hw->adapter_state == HNS3_NIC_STARTED)
4890                 hns3_service_handler(eth_dev);
4891
4892         return 0;
4893 }
4894
4895 static int
4896 hns3_restore_conf(struct hns3_adapter *hns)
4897 {
4898         struct hns3_hw *hw = &hns->hw;
4899         int ret;
4900
4901         ret = hns3_configure_all_mac_addr(hns, false);
4902         if (ret)
4903                 return ret;
4904
4905         ret = hns3_configure_all_mc_mac_addr(hns, false);
4906         if (ret)
4907                 goto err_mc_mac;
4908
4909         ret = hns3_dev_promisc_restore(hns);
4910         if (ret)
4911                 goto err_promisc;
4912
4913         ret = hns3_restore_vlan_table(hns);
4914         if (ret)
4915                 goto err_promisc;
4916
4917         ret = hns3_restore_vlan_conf(hns);
4918         if (ret)
4919                 goto err_promisc;
4920
4921         ret = hns3_restore_all_fdir_filter(hns);
4922         if (ret)
4923                 goto err_promisc;
4924
4925         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4926                 ret = hns3_do_start(hns, false);
4927                 if (ret)
4928                         goto err_promisc;
4929                 hns3_info(hw, "hns3 dev restart successful!");
4930         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4931                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4932         return 0;
4933
4934 err_promisc:
4935         hns3_configure_all_mc_mac_addr(hns, true);
4936 err_mc_mac:
4937         hns3_configure_all_mac_addr(hns, true);
4938         return ret;
4939 }
4940
4941 static void
4942 hns3_reset_service(void *param)
4943 {
4944         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4945         struct hns3_hw *hw = &hns->hw;
4946         enum hns3_reset_level reset_level;
4947         struct timeval tv_delta;
4948         struct timeval tv_start;
4949         struct timeval tv;
4950         uint64_t msec;
4951         int ret;
4952
4953         /*
4954          * The interrupt is not triggered within the delay time.
4955          * The interrupt may have been lost. It is necessary to handle
4956          * the interrupt to recover from the error.
4957          */
4958         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4959                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4960                 hns3_err(hw, "Handling interrupts in delayed tasks");
4961                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4962                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4963                 if (reset_level == HNS3_NONE_RESET) {
4964                         hns3_err(hw, "No reset level is set, try IMP reset");
4965                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4966                 }
4967         }
4968         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4969
4970         /*
4971          * Check if there is any ongoing reset in the hardware. This status can
4972          * be checked from reset_pending. If there is then, we need to wait for
4973          * hardware to complete reset.
4974          *    a. If we are able to figure out in reasonable time that hardware
4975          *       has fully resetted then, we can proceed with driver, client
4976          *       reset.
4977          *    b. else, we can come back later to check this status so re-sched
4978          *       now.
4979          */
4980         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4981         if (reset_level != HNS3_NONE_RESET) {
4982                 gettimeofday(&tv_start, NULL);
4983                 ret = hns3_reset_process(hns, reset_level);
4984                 gettimeofday(&tv, NULL);
4985                 timersub(&tv, &tv_start, &tv_delta);
4986                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4987                        tv_delta.tv_usec / USEC_PER_MSEC;
4988                 if (msec > HNS3_RESET_PROCESS_MS)
4989                         hns3_err(hw, "%d handle long time delta %" PRIx64
4990                                      " ms time=%ld.%.6ld",
4991                                  hw->reset.level, msec,
4992                                  tv.tv_sec, tv.tv_usec);
4993                 if (ret == -EAGAIN)
4994                         return;
4995         }
4996
4997         /* Check if we got any *new* reset requests to be honored */
4998         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4999         if (reset_level != HNS3_NONE_RESET)
5000                 hns3_msix_process(hns, reset_level);
5001 }
5002
5003 static const struct eth_dev_ops hns3_eth_dev_ops = {
5004         .dev_start          = hns3_dev_start,
5005         .dev_stop           = hns3_dev_stop,
5006         .dev_close          = hns3_dev_close,
5007         .promiscuous_enable = hns3_dev_promiscuous_enable,
5008         .promiscuous_disable = hns3_dev_promiscuous_disable,
5009         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5010         .allmulticast_disable = hns3_dev_allmulticast_disable,
5011         .mtu_set            = hns3_dev_mtu_set,
5012         .stats_get          = hns3_stats_get,
5013         .stats_reset        = hns3_stats_reset,
5014         .xstats_get         = hns3_dev_xstats_get,
5015         .xstats_get_names   = hns3_dev_xstats_get_names,
5016         .xstats_reset       = hns3_dev_xstats_reset,
5017         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5018         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5019         .dev_infos_get          = hns3_dev_infos_get,
5020         .fw_version_get         = hns3_fw_version_get,
5021         .rx_queue_setup         = hns3_rx_queue_setup,
5022         .tx_queue_setup         = hns3_tx_queue_setup,
5023         .rx_queue_release       = hns3_dev_rx_queue_release,
5024         .tx_queue_release       = hns3_dev_tx_queue_release,
5025         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5026         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5027         .dev_configure          = hns3_dev_configure,
5028         .flow_ctrl_get          = hns3_flow_ctrl_get,
5029         .flow_ctrl_set          = hns3_flow_ctrl_set,
5030         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5031         .mac_addr_add           = hns3_add_mac_addr,
5032         .mac_addr_remove        = hns3_remove_mac_addr,
5033         .mac_addr_set           = hns3_set_default_mac_addr,
5034         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5035         .link_update            = hns3_dev_link_update,
5036         .rss_hash_update        = hns3_dev_rss_hash_update,
5037         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5038         .reta_update            = hns3_dev_rss_reta_update,
5039         .reta_query             = hns3_dev_rss_reta_query,
5040         .filter_ctrl            = hns3_dev_filter_ctrl,
5041         .vlan_filter_set        = hns3_vlan_filter_set,
5042         .vlan_tpid_set          = hns3_vlan_tpid_set,
5043         .vlan_offload_set       = hns3_vlan_offload_set,
5044         .vlan_pvid_set          = hns3_vlan_pvid_set,
5045         .get_reg                = hns3_get_regs,
5046         .get_dcb_info           = hns3_get_dcb_info,
5047         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5048 };
5049
5050 static const struct hns3_reset_ops hns3_reset_ops = {
5051         .reset_service       = hns3_reset_service,
5052         .stop_service        = hns3_stop_service,
5053         .prepare_reset       = hns3_prepare_reset,
5054         .wait_hardware_ready = hns3_wait_hardware_ready,
5055         .reinit_dev          = hns3_reinit_dev,
5056         .restore_conf        = hns3_restore_conf,
5057         .start_service       = hns3_start_service,
5058 };
5059
5060 static int
5061 hns3_dev_init(struct rte_eth_dev *eth_dev)
5062 {
5063         struct rte_device *dev = eth_dev->device;
5064         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5065         struct hns3_adapter *hns = eth_dev->data->dev_private;
5066         struct hns3_hw *hw = &hns->hw;
5067         uint16_t device_id = pci_dev->id.device_id;
5068         int ret;
5069
5070         PMD_INIT_FUNC_TRACE();
5071         eth_dev->process_private = (struct hns3_process_private *)
5072             rte_zmalloc_socket("hns3_filter_list",
5073                                sizeof(struct hns3_process_private),
5074                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5075         if (eth_dev->process_private == NULL) {
5076                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5077                 return -ENOMEM;
5078         }
5079         /* initialize flow filter lists */
5080         hns3_filterlist_init(eth_dev);
5081
5082         hns3_set_rxtx_function(eth_dev);
5083         eth_dev->dev_ops = &hns3_eth_dev_ops;
5084         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5085                 hns3_mp_init_secondary();
5086                 hw->secondary_cnt++;
5087                 return 0;
5088         }
5089
5090         hns3_mp_init_primary();
5091         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5092
5093         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5094             device_id == HNS3_DEV_ID_50GE_RDMA ||
5095             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5096                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5097
5098         hns->is_vf = false;
5099         hw->data = eth_dev->data;
5100
5101         /*
5102          * Set default max packet size according to the mtu
5103          * default vale in DPDK frame.
5104          */
5105         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5106
5107         ret = hns3_reset_init(hw);
5108         if (ret)
5109                 goto err_init_reset;
5110         hw->reset.ops = &hns3_reset_ops;
5111
5112         ret = hns3_init_pf(eth_dev);
5113         if (ret) {
5114                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5115                 goto err_init_pf;
5116         }
5117
5118         /* Allocate memory for storing MAC addresses */
5119         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5120                                                sizeof(struct rte_ether_addr) *
5121                                                HNS3_UC_MACADDR_NUM, 0);
5122         if (eth_dev->data->mac_addrs == NULL) {
5123                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5124                              "to store MAC addresses",
5125                              sizeof(struct rte_ether_addr) *
5126                              HNS3_UC_MACADDR_NUM);
5127                 ret = -ENOMEM;
5128                 goto err_rte_zmalloc;
5129         }
5130
5131         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5132                             &eth_dev->data->mac_addrs[0]);
5133
5134         hw->adapter_state = HNS3_NIC_INITIALIZED;
5135         /*
5136          * Pass the information to the rte_eth_dev_close() that it should also
5137          * release the private port resources.
5138          */
5139         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5140
5141         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5142                 hns3_err(hw, "Reschedule reset service after dev_init");
5143                 hns3_schedule_reset(hns);
5144         } else {
5145                 /* IMP will wait ready flag before reset */
5146                 hns3_notify_reset_ready(hw, false);
5147         }
5148
5149         hns3_info(hw, "hns3 dev initialization successful!");
5150         return 0;
5151
5152 err_rte_zmalloc:
5153         hns3_uninit_pf(eth_dev);
5154
5155 err_init_pf:
5156         rte_free(hw->reset.wait_data);
5157 err_init_reset:
5158         eth_dev->dev_ops = NULL;
5159         eth_dev->rx_pkt_burst = NULL;
5160         eth_dev->tx_pkt_burst = NULL;
5161         eth_dev->tx_pkt_prepare = NULL;
5162         rte_free(eth_dev->process_private);
5163         eth_dev->process_private = NULL;
5164         return ret;
5165 }
5166
5167 static int
5168 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5169 {
5170         struct hns3_adapter *hns = eth_dev->data->dev_private;
5171         struct hns3_hw *hw = &hns->hw;
5172
5173         PMD_INIT_FUNC_TRACE();
5174
5175         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5176                 return -EPERM;
5177
5178         eth_dev->dev_ops = NULL;
5179         eth_dev->rx_pkt_burst = NULL;
5180         eth_dev->tx_pkt_burst = NULL;
5181         eth_dev->tx_pkt_prepare = NULL;
5182         if (hw->adapter_state < HNS3_NIC_CLOSING)
5183                 hns3_dev_close(eth_dev);
5184
5185         hw->adapter_state = HNS3_NIC_REMOVED;
5186         return 0;
5187 }
5188
5189 static int
5190 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5191                    struct rte_pci_device *pci_dev)
5192 {
5193         return rte_eth_dev_pci_generic_probe(pci_dev,
5194                                              sizeof(struct hns3_adapter),
5195                                              hns3_dev_init);
5196 }
5197
5198 static int
5199 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5200 {
5201         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5202 }
5203
5204 static const struct rte_pci_id pci_id_hns3_map[] = {
5205         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5206         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5208         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5209         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5210         { .vendor_id = 0, /* sentinel */ },
5211 };
5212
5213 static struct rte_pci_driver rte_hns3_pmd = {
5214         .id_table = pci_id_hns3_map,
5215         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5216         .probe = eth_hns3_pci_probe,
5217         .remove = eth_hns3_pci_remove,
5218 };
5219
5220 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5221 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5222 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5223
5224 RTE_INIT(hns3_init_log)
5225 {
5226         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5227         if (hns3_logtype_init >= 0)
5228                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5229         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5230         if (hns3_logtype_driver >= 0)
5231                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5232 }