drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108
 109 void hns3_ether_format_addr(char *buf, uint16_t size,
 110                             const struct rte_ether_addr *ether_addr)
 111 {
 112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 113                 ether_addr->addr_bytes[0],
 114                 ether_addr->addr_bytes[4],
 115                 ether_addr->addr_bytes[5]);
 116 }
 117
 118 static void
 119 hns3_pf_disable_irq0(struct hns3_hw *hw)
 120 {
 121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 122 }
 123
 124 static void
 125 hns3_pf_enable_irq0(struct hns3_hw *hw)
 126 {
 127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 128 }
 129
 130 static enum hns3_evt_cause
 131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 132                           uint32_t *vec_val)
 133 {
 134         struct hns3_hw *hw = &hns->hw;
 135
 136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 139         if (!is_delay) {
 140                 hw->reset.stats.imp_cnt++;
 141                 hns3_warn(hw, "IMP reset detected, clear reset status");
 142         } else {
 143                 hns3_schedule_delayed_reset(hns);
 144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 145         }
 146
 147         return HNS3_VECTOR0_EVENT_RST;
 148 }
 149
 150 static enum hns3_evt_cause
 151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 152                              uint32_t *vec_val)
 153 {
 154         struct hns3_hw *hw = &hns->hw;
 155
 156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 159         if (!is_delay) {
 160                 hw->reset.stats.global_cnt++;
 161                 hns3_warn(hw, "Global reset detected, clear reset status");
 162         } else {
 163                 hns3_schedule_delayed_reset(hns);
 164                 hns3_warn(hw,
 165                           "Global reset detected, don't clear reset status");
 166         }
 167
 168         return HNS3_VECTOR0_EVENT_RST;
 169 }
 170
 171 static enum hns3_evt_cause
 172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 173 {
 174         struct hns3_hw *hw = &hns->hw;
 175         uint32_t vector0_int_stats;
 176         uint32_t cmdq_src_val;
 177         uint32_t hw_err_src_reg;
 178         uint32_t val;
 179         enum hns3_evt_cause ret;
 180         bool is_delay;
 181
 182         /* fetch the events from their corresponding regs */
 183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 186
 187         is_delay = clearval == NULL ? true : false;
 188         /*
 189          * Assumption: If by any chance reset and mailbox events are reported
 190          * together then we will only process reset event and defer the
 191          * processing of the mailbox events. Since, we would have not cleared
 192          * RX CMDQ event this time we would receive again another interrupt
 193          * from H/W just for the mailbox.
 194          */
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 197                 goto out;
 198         }
 199
 200         /* Global reset */
 201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 203                 goto out;
 204         }
 205
 206         /* Check for vector0 1588 event source */
 207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 209                 ret = HNS3_VECTOR0_EVENT_PTP;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 msix event source */
 214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 216                 val = vector0_int_stats | hw_err_src_reg;
 217                 ret = HNS3_VECTOR0_EVENT_ERR;
 218                 goto out;
 219         }
 220
 221         /* check for vector0 mailbox(=CMDQ RX) event source */
 222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 224                 val = cmdq_src_val;
 225                 ret = HNS3_VECTOR0_EVENT_MBX;
 226                 goto out;
 227         }
 228
 229         val = vector0_int_stats;
 230         ret = HNS3_VECTOR0_EVENT_OTHER;
 231 out:
 232
 233         if (clearval)
 234                 *clearval = val;
 235         return ret;
 236 }
 237
 238 static bool
 239 hns3_is_1588_event_type(uint32_t event_type)
 240 {
 241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 242 }
 243
 244 static void
 245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 246 {
 247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 248             hns3_is_1588_event_type(event_type))
 249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 252 }
 253
 254 static void
 255 hns3_clear_all_event_cause(struct hns3_hw *hw)
 256 {
 257         uint32_t vector0_int_stats;
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259
 260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 261                 hns3_warn(hw, "Probe during IMP reset interrupt");
 262
 263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 264                 hns3_warn(hw, "Probe during Global reset interrupt");
 265
 266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 272                                 BIT(HNS3_VECTOR0_1588_INT_B));
 273 }
 274
 275 static void
 276 hns3_handle_mac_tnl(struct hns3_hw *hw)
 277 {
 278         struct hns3_cmd_desc desc;
 279         uint32_t status;
 280         int ret;
 281
 282         /* query and clear mac tnl interruptions */
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 284         ret = hns3_cmd_send(hw, &desc, 1);
 285         if (ret) {
 286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 287                 return;
 288         }
 289
 290         status = rte_le_to_cpu_32(desc.data[0]);
 291         if (status) {
 292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 294                                           false);
 295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 296                 ret = hns3_cmd_send(hw, &desc, 1);
 297                 if (ret)
 298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 299                                  ret);
 300         }
 301 }
 302
 303 static void
 304 hns3_interrupt_handler(void *param)
 305 {
 306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 307         struct hns3_adapter *hns = dev->data->dev_private;
 308         struct hns3_hw *hw = &hns->hw;
 309         enum hns3_evt_cause event_cause;
 310         uint32_t clearval = 0;
 311         uint32_t vector0_int;
 312         uint32_t ras_int;
 313         uint32_t cmdq_int;
 314
 315         /* Disable interrupt */
 316         hns3_pf_disable_irq0(hw);
 317
 318         event_cause = hns3_check_event_cause(hns, &clearval);
 319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_msix_error(hns, &hw->reset.request);
 328                 hns3_handle_ras_error(hns, &hw->reset.request);
 329                 hns3_handle_mac_tnl(hw);
 330                 hns3_schedule_reset(hns);
 331         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 332                 hns3_warn(hw, "received reset interrupt");
 333                 hns3_schedule_reset(hns);
 334         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 335                 hns3_dev_handle_mbx_msg(hw);
 336         } else {
 337                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 338                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 339                           vector0_int, ras_int, cmdq_int);
 340         }
 341
 342         hns3_clear_event_cause(hw, event_cause, clearval);
 343         /* Enable interrupt if it is not cause by reset */
 344         hns3_pf_enable_irq0(hw);
 345 }
 346
 347 static int
 348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 349 {
 350 #define HNS3_VLAN_ID_OFFSET_STEP        160
 351 #define HNS3_VLAN_BYTE_SIZE             8
 352         struct hns3_vlan_filter_pf_cfg_cmd *req;
 353         struct hns3_hw *hw = &hns->hw;
 354         uint8_t vlan_offset_byte_val;
 355         struct hns3_cmd_desc desc;
 356         uint8_t vlan_offset_byte;
 357         uint8_t vlan_offset_base;
 358         int ret;
 359
 360         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 361
 362         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 363         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 364                            HNS3_VLAN_BYTE_SIZE;
 365         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 366
 367         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 368         req->vlan_offset = vlan_offset_base;
 369         req->vlan_cfg = on ? 0 : 1;
 370         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 371
 372         ret = hns3_cmd_send(hw, &desc, 1);
 373         if (ret)
 374                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 375                          vlan_id, ret);
 376
 377         return ret;
 378 }
 379
 380 static void
 381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 382 {
 383         struct hns3_user_vlan_table *vlan_entry;
 384         struct hns3_pf *pf = &hns->pf;
 385
 386         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 387                 if (vlan_entry->vlan_id == vlan_id) {
 388                         if (vlan_entry->hd_tbl_status)
 389                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 390                         LIST_REMOVE(vlan_entry, next);
 391                         rte_free(vlan_entry);
 392                         break;
 393                 }
 394         }
 395 }
 396
 397 static void
 398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 399                         bool writen_to_tbl)
 400 {
 401         struct hns3_user_vlan_table *vlan_entry;
 402         struct hns3_hw *hw = &hns->hw;
 403         struct hns3_pf *pf = &hns->pf;
 404
 405         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 406                 if (vlan_entry->vlan_id == vlan_id)
 407                         return;
 408         }
 409
 410         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 411         if (vlan_entry == NULL) {
 412                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 413                 return;
 414         }
 415
 416         vlan_entry->hd_tbl_status = writen_to_tbl;
 417         vlan_entry->vlan_id = vlan_id;
 418
 419         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 420 }
 421
 422 static int
 423 hns3_restore_vlan_table(struct hns3_adapter *hns)
 424 {
 425         struct hns3_user_vlan_table *vlan_entry;
 426         struct hns3_hw *hw = &hns->hw;
 427         struct hns3_pf *pf = &hns->pf;
 428         uint16_t vlan_id;
 429         int ret = 0;
 430
 431         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 432                 return hns3_vlan_pvid_configure(hns,
 433                                                 hw->port_base_vlan_cfg.pvid, 1);
 434
 435         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 436                 if (vlan_entry->hd_tbl_status) {
 437                         vlan_id = vlan_entry->vlan_id;
 438                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 439                         if (ret)
 440                                 break;
 441                 }
 442         }
 443
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 449 {
 450         struct hns3_hw *hw = &hns->hw;
 451         bool writen_to_tbl = false;
 452         int ret = 0;
 453
 454         /*
 455          * When vlan filter is enabled, hardware regards packets without vlan
 456          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 457          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 458          */
 459         if (on == 0 && vlan_id == 0)
 460                 return 0;
 461
 462         /*
 463          * When port base vlan enabled, we use port base vlan as the vlan
 464          * filter condition. In this case, we don't update vlan filter table
 465          * when user add new vlan or remove exist vlan, just update the
 466          * vlan list. The vlan id in vlan list will be writen in vlan filter
 467          * table until port base vlan disabled
 468          */
 469         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 470                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 471                 writen_to_tbl = true;
 472         }
 473
 474         if (ret == 0) {
 475                 if (on)
 476                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 477                 else
 478                         hns3_rm_dev_vlan_table(hns, vlan_id);
 479         }
 480         return ret;
 481 }
 482
 483 static int
 484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 485 {
 486         struct hns3_adapter *hns = dev->data->dev_private;
 487         struct hns3_hw *hw = &hns->hw;
 488         int ret;
 489
 490         rte_spinlock_lock(&hw->lock);
 491         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 492         rte_spinlock_unlock(&hw->lock);
 493         return ret;
 494 }
 495
 496 static int
 497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 498                          uint16_t tpid)
 499 {
 500         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 501         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 502         struct hns3_hw *hw = &hns->hw;
 503         struct hns3_cmd_desc desc;
 504         int ret;
 505
 506         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 507              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 508                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 509                 return -EINVAL;
 510         }
 511
 512         if (tpid != RTE_ETHER_TYPE_VLAN) {
 513                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 514                 return -EINVAL;
 515         }
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 518         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 519
 520         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 524                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 527                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 528         }
 529
 530         ret = hns3_cmd_send(hw, &desc, 1);
 531         if (ret) {
 532                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 533                          ret);
 534                 return ret;
 535         }
 536
 537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 538
 539         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 540         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 541         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 546                          ret);
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 552                    uint16_t tpid)
 553 {
 554         struct hns3_adapter *hns = dev->data->dev_private;
 555         struct hns3_hw *hw = &hns->hw;
 556         int ret;
 557
 558         rte_spinlock_lock(&hw->lock);
 559         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 560         rte_spinlock_unlock(&hw->lock);
 561         return ret;
 562 }
 563
 564 static int
 565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 566                              struct hns3_rx_vtag_cfg *vcfg)
 567 {
 568         struct hns3_vport_vtag_rx_cfg_cmd *req;
 569         struct hns3_hw *hw = &hns->hw;
 570         struct hns3_cmd_desc desc;
 571         uint16_t vport_id;
 572         uint8_t bitmap;
 573         int ret;
 574
 575         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 576
 577         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 579                      vcfg->strip_tag1_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 581                      vcfg->strip_tag2_en ? 1 : 0);
 582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 583                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 584         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 585                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 586
 587         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 589                      vcfg->strip_tag1_discard_en ? 1 : 0);
 590         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 591                      vcfg->strip_tag2_discard_en ? 1 : 0);
 592         /*
 593          * In current version VF is not supported when PF is driven by DPDK
 594          * driver, just need to configure parameters for PF vport.
 595          */
 596         vport_id = HNS3_PF_FUNC_ID;
 597         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 598         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 599         req->vf_bitmap[req->vf_offset] = bitmap;
 600
 601         ret = hns3_cmd_send(hw, &desc, 1);
 602         if (ret)
 603                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 604         return ret;
 605 }
 606
 607 static void
 608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 609                            struct hns3_rx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_pf *pf = &hns->pf;
 612         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 613 }
 614
 615 static void
 616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 617                            struct hns3_tx_vtag_cfg *vcfg)
 618 {
 619         struct hns3_pf *pf = &hns->pf;
 620         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 621 }
 622
 623 static int
 624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 625 {
 626         struct hns3_rx_vtag_cfg rxvlan_cfg;
 627         struct hns3_hw *hw = &hns->hw;
 628         int ret;
 629
 630         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 631                 rxvlan_cfg.strip_tag1_en = false;
 632                 rxvlan_cfg.strip_tag2_en = enable;
 633                 rxvlan_cfg.strip_tag2_discard_en = false;
 634         } else {
 635                 rxvlan_cfg.strip_tag1_en = enable;
 636                 rxvlan_cfg.strip_tag2_en = true;
 637                 rxvlan_cfg.strip_tag2_discard_en = true;
 638         }
 639
 640         rxvlan_cfg.strip_tag1_discard_en = false;
 641         rxvlan_cfg.vlan1_vlan_prionly = false;
 642         rxvlan_cfg.vlan2_vlan_prionly = false;
 643         rxvlan_cfg.rx_vlan_offload_en = enable;
 644
 645         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 646         if (ret) {
 647                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 648                 return ret;
 649         }
 650
 651         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 658                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 659 {
 660         struct hns3_vlan_filter_ctrl_cmd *req;
 661         struct hns3_cmd_desc desc;
 662         int ret;
 663
 664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 665
 666         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 667         req->vlan_type = vlan_type;
 668         req->vlan_fe = filter_en ? fe_type : 0;
 669         req->vf_id = vf_id;
 670
 671         ret = hns3_cmd_send(hw, &desc, 1);
 672         if (ret)
 673                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 674
 675         return ret;
 676 }
 677
 678 static int
 679 hns3_vlan_filter_init(struct hns3_adapter *hns)
 680 {
 681         struct hns3_hw *hw = &hns->hw;
 682         int ret;
 683
 684         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 685                                         HNS3_FILTER_FE_EGRESS, false,
 686                                         HNS3_PF_FUNC_ID);
 687         if (ret) {
 688                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 689                 return ret;
 690         }
 691
 692         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 693                                         HNS3_FILTER_FE_INGRESS, false,
 694                                         HNS3_PF_FUNC_ID);
 695         if (ret)
 696                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 697
 698         return ret;
 699 }
 700
 701 static int
 702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 703 {
 704         struct hns3_hw *hw = &hns->hw;
 705         int ret;
 706
 707         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 708                                         HNS3_FILTER_FE_INGRESS, enable,
 709                                         HNS3_PF_FUNC_ID);
 710         if (ret)
 711                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 712                          enable ? "enable" : "disable", ret);
 713
 714         return ret;
 715 }
 716
 717 static int
 718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 719 {
 720         struct hns3_adapter *hns = dev->data->dev_private;
 721         struct hns3_hw *hw = &hns->hw;
 722         struct rte_eth_rxmode *rxmode;
 723         unsigned int tmp_mask;
 724         bool enable;
 725         int ret = 0;
 726
 727         rte_spinlock_lock(&hw->lock);
 728         rxmode = &dev->data->dev_conf.rxmode;
 729         tmp_mask = (unsigned int)mask;
 730         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 731                 /* ignore vlan filter configuration during promiscuous mode */
 732                 if (!dev->data->promiscuous) {
 733                         /* Enable or disable VLAN filter */
 734                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 735                                  true : false;
 736
 737                         ret = hns3_enable_vlan_filter(hns, enable);
 738                         if (ret) {
 739                                 rte_spinlock_unlock(&hw->lock);
 740                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 741                                          enable ? "enable" : "disable", ret);
 742                                 return ret;
 743                         }
 744                 }
 745         }
 746
 747         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 748                 /* Enable or disable VLAN stripping */
 749                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 750                     true : false;
 751
 752                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 753                 if (ret) {
 754                         rte_spinlock_unlock(&hw->lock);
 755                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 756                                  enable ? "enable" : "disable", ret);
 757                         return ret;
 758                 }
 759         }
 760
 761         rte_spinlock_unlock(&hw->lock);
 762
 763         return ret;
 764 }
 765
 766 static int
 767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 768                              struct hns3_tx_vtag_cfg *vcfg)
 769 {
 770         struct hns3_vport_vtag_tx_cfg_cmd *req;
 771         struct hns3_cmd_desc desc;
 772         struct hns3_hw *hw = &hns->hw;
 773         uint16_t vport_id;
 774         uint8_t bitmap;
 775         int ret;
 776
 777         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 778
 779         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 780         req->def_vlan_tag1 = vcfg->default_tag1;
 781         req->def_vlan_tag2 = vcfg->default_tag2;
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 783                      vcfg->accept_tag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 785                      vcfg->accept_untag1 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 787                      vcfg->accept_tag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 789                      vcfg->accept_untag2 ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 791                      vcfg->insert_tag1_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 793                      vcfg->insert_tag2_en ? 1 : 0);
 794         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 795
 796         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 797         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 798                      vcfg->tag_shift_mode_en ? 1 : 0);
 799
 800         /*
 801          * In current version VF is not supported when PF is driven by DPDK
 802          * driver, just need to configure parameters for PF vport.
 803          */
 804         vport_id = HNS3_PF_FUNC_ID;
 805         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 806         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 807         req->vf_bitmap[req->vf_offset] = bitmap;
 808
 809         ret = hns3_cmd_send(hw, &desc, 1);
 810         if (ret)
 811                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 812
 813         return ret;
 814 }
 815
 816 static int
 817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 818                      uint16_t pvid)
 819 {
 820         struct hns3_hw *hw = &hns->hw;
 821         struct hns3_tx_vtag_cfg txvlan_cfg;
 822         int ret;
 823
 824         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 825                 txvlan_cfg.accept_tag1 = true;
 826                 txvlan_cfg.insert_tag1_en = false;
 827                 txvlan_cfg.default_tag1 = 0;
 828         } else {
 829                 txvlan_cfg.accept_tag1 =
 830                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 831                 txvlan_cfg.insert_tag1_en = true;
 832                 txvlan_cfg.default_tag1 = pvid;
 833         }
 834
 835         txvlan_cfg.accept_untag1 = true;
 836         txvlan_cfg.accept_tag2 = true;
 837         txvlan_cfg.accept_untag2 = true;
 838         txvlan_cfg.insert_tag2_en = false;
 839         txvlan_cfg.default_tag2 = 0;
 840         txvlan_cfg.tag_shift_mode_en = true;
 841
 842         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 843         if (ret) {
 844                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 845                          ret);
 846                 return ret;
 847         }
 848
 849         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 850         return ret;
 851 }
 852
 853
 854 static void
 855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 856 {
 857         struct hns3_user_vlan_table *vlan_entry;
 858         struct hns3_pf *pf = &hns->pf;
 859
 860         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 861                 if (vlan_entry->hd_tbl_status) {
 862                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 863                         vlan_entry->hd_tbl_status = false;
 864                 }
 865         }
 866
 867         if (is_del_list) {
 868                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 869                 while (vlan_entry) {
 870                         LIST_REMOVE(vlan_entry, next);
 871                         rte_free(vlan_entry);
 872                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 873                 }
 874         }
 875 }
 876
 877 static void
 878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 879 {
 880         struct hns3_user_vlan_table *vlan_entry;
 881         struct hns3_pf *pf = &hns->pf;
 882
 883         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 884                 if (!vlan_entry->hd_tbl_status) {
 885                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 886                         vlan_entry->hd_tbl_status = true;
 887                 }
 888         }
 889 }
 890
 891 static void
 892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 893 {
 894         struct hns3_hw *hw = &hns->hw;
 895         int ret;
 896
 897         hns3_rm_all_vlan_table(hns, true);
 898         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 899                 ret = hns3_set_port_vlan_filter(hns,
 900                                                 hw->port_base_vlan_cfg.pvid, 0);
 901                 if (ret) {
 902                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 903                                  ret);
 904                         return;
 905                 }
 906         }
 907 }
 908
 909 static int
 910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 911                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         uint16_t old_pvid;
 915         int ret;
 916
 917         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 918                 old_pvid = hw->port_base_vlan_cfg.pvid;
 919                 if (old_pvid != HNS3_INVALID_PVID) {
 920                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 921                         if (ret) {
 922                                 hns3_err(hw, "failed to remove old pvid %u, "
 923                                                 "ret = %d", old_pvid, ret);
 924                                 return ret;
 925                         }
 926                 }
 927
 928                 hns3_rm_all_vlan_table(hns, false);
 929                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 930                 if (ret) {
 931                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 932                                         new_pvid, ret);
 933                         return ret;
 934                 }
 935         } else {
 936                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 937                 if (ret) {
 938                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 939                                         new_pvid, ret);
 940                         return ret;
 941                 }
 942
 943                 hns3_add_all_vlan_table(hns);
 944         }
 945         return 0;
 946 }
 947
 948 static int
 949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 950 {
 951         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 952         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 953         bool rx_strip_en;
 954         int ret;
 955
 956         rx_strip_en = old_cfg->rx_vlan_offload_en;
 957         if (on) {
 958                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 959                 rx_vlan_cfg.strip_tag2_en = true;
 960                 rx_vlan_cfg.strip_tag2_discard_en = true;
 961         } else {
 962                 rx_vlan_cfg.strip_tag1_en = false;
 963                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 964                 rx_vlan_cfg.strip_tag2_discard_en = false;
 965         }
 966         rx_vlan_cfg.strip_tag1_discard_en = false;
 967         rx_vlan_cfg.vlan1_vlan_prionly = false;
 968         rx_vlan_cfg.vlan2_vlan_prionly = false;
 969         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 970
 971         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 972         if (ret)
 973                 return ret;
 974
 975         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         uint16_t port_base_vlan_state;
 984         int ret;
 985
 986         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 987                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 988                         hns3_warn(hw, "Invalid operation! As current pvid set "
 989                                   "is %u, disable pvid %u is invalid",
 990                                   hw->port_base_vlan_cfg.pvid, pvid);
 991                 return 0;
 992         }
 993
 994         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 995                                     HNS3_PORT_BASE_VLAN_DISABLE;
 996         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 997         if (ret) {
 998                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 999                          ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_en_pvid_strip(hns, on);
1004         if (ret) {
1005                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006                          "ret = %d", ret);
1007                 return ret;
1008         }
1009
1010         if (pvid == HNS3_INVALID_PVID)
1011                 goto out;
1012         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013         if (ret) {
1014                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015                          ret);
1016                 return ret;
1017         }
1018
1019 out:
1020         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022         return ret;
1023 }
1024
1025 static int
1026 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1027 {
1028         struct hns3_adapter *hns = dev->data->dev_private;
1029         struct hns3_hw *hw = &hns->hw;
1030         bool pvid_en_state_change;
1031         uint16_t pvid_state;
1032         int ret;
1033
1034         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1035                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1036                          RTE_ETHER_MAX_VLAN_ID);
1037                 return -EINVAL;
1038         }
1039
1040         /*
1041          * If PVID configuration state change, should refresh the PVID
1042          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1043          */
1044         pvid_state = hw->port_base_vlan_cfg.state;
1045         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1046             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1047                 pvid_en_state_change = false;
1048         else
1049                 pvid_en_state_change = true;
1050
1051         rte_spinlock_lock(&hw->lock);
1052         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1053         rte_spinlock_unlock(&hw->lock);
1054         if (ret)
1055                 return ret;
1056         /*
1057          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1058          * need be processed by PMD driver.
1059          */
1060         if (pvid_en_state_change &&
1061             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1062                 hns3_update_all_queues_pvid_proc_en(hw);
1063
1064         return 0;
1065 }
1066
1067 static int
1068 hns3_default_vlan_config(struct hns3_adapter *hns)
1069 {
1070         struct hns3_hw *hw = &hns->hw;
1071         int ret;
1072
1073         /*
1074          * When vlan filter is enabled, hardware regards packets without vlan
1075          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1076          * table, packets without vlan won't be received. So, add vlan 0 as
1077          * the default vlan.
1078          */
1079         ret = hns3_vlan_filter_configure(hns, 0, 1);
1080         if (ret)
1081                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1082         return ret;
1083 }
1084
1085 static int
1086 hns3_init_vlan_config(struct hns3_adapter *hns)
1087 {
1088         struct hns3_hw *hw = &hns->hw;
1089         int ret;
1090
1091         /*
1092          * This function can be called in the initialization and reset process,
1093          * when in reset process, it means that hardware had been reseted
1094          * successfully and we need to restore the hardware configuration to
1095          * ensure that the hardware configuration remains unchanged before and
1096          * after reset.
1097          */
1098         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1099                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1100                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1101         }
1102
1103         ret = hns3_vlan_filter_init(hns);
1104         if (ret) {
1105                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1106                 return ret;
1107         }
1108
1109         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1110                                        RTE_ETHER_TYPE_VLAN);
1111         if (ret) {
1112                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1113                 return ret;
1114         }
1115
1116         /*
1117          * When in the reinit dev stage of the reset process, the following
1118          * vlan-related configurations may differ from those at initialization,
1119          * we will restore configurations to hardware in hns3_restore_vlan_table
1120          * and hns3_restore_vlan_conf later.
1121          */
1122         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1123                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1124                 if (ret) {
1125                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1126                         return ret;
1127                 }
1128
1129                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1130                 if (ret) {
1131                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1132                                  ret);
1133                         return ret;
1134                 }
1135         }
1136
1137         return hns3_default_vlan_config(hns);
1138 }
1139
1140 static int
1141 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1142 {
1143         struct hns3_pf *pf = &hns->pf;
1144         struct hns3_hw *hw = &hns->hw;
1145         uint64_t offloads;
1146         bool enable;
1147         int ret;
1148
1149         if (!hw->data->promiscuous) {
1150                 /* restore vlan filter states */
1151                 offloads = hw->data->dev_conf.rxmode.offloads;
1152                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1153                 ret = hns3_enable_vlan_filter(hns, enable);
1154                 if (ret) {
1155                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1156                                  "ret = %d", ret);
1157                         return ret;
1158                 }
1159         }
1160
1161         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1162         if (ret) {
1163                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1164                 return ret;
1165         }
1166
1167         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1168         if (ret)
1169                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1170
1171         return ret;
1172 }
1173
1174 static int
1175 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1176 {
1177         struct hns3_adapter *hns = dev->data->dev_private;
1178         struct rte_eth_dev_data *data = dev->data;
1179         struct rte_eth_txmode *txmode;
1180         struct hns3_hw *hw = &hns->hw;
1181         int mask;
1182         int ret;
1183
1184         txmode = &data->dev_conf.txmode;
1185         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1186                 hns3_warn(hw,
1187                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1188                           "configuration is not supported! Ignore these two "
1189                           "parameters: hw_vlan_reject_tagged(%u), "
1190                           "hw_vlan_reject_untagged(%u)",
1191                           txmode->hw_vlan_reject_tagged,
1192                           txmode->hw_vlan_reject_untagged);
1193
1194         /* Apply vlan offload setting */
1195         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1196         ret = hns3_vlan_offload_set(dev, mask);
1197         if (ret) {
1198                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1199                          ret);
1200                 return ret;
1201         }
1202
1203         /*
1204          * If pvid config is not set in rte_eth_conf, driver needn't to set
1205          * VLAN pvid related configuration to hardware.
1206          */
1207         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1208                 return 0;
1209
1210         /* Apply pvid setting */
1211         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1212                                  txmode->hw_vlan_insert_pvid);
1213         if (ret)
1214                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1215                          txmode->pvid, ret);
1216
1217         return ret;
1218 }
1219
1220 static int
1221 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1222                 unsigned int tso_mss_max)
1223 {
1224         struct hns3_cfg_tso_status_cmd *req;
1225         struct hns3_cmd_desc desc;
1226         uint16_t tso_mss;
1227
1228         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1229
1230         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1231
1232         tso_mss = 0;
1233         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1234                        tso_mss_min);
1235         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1236
1237         tso_mss = 0;
1238         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1239                        tso_mss_max);
1240         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1241
1242         return hns3_cmd_send(hw, &desc, 1);
1243 }
1244
1245 static int
1246 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1247                    uint16_t *allocated_size, bool is_alloc)
1248 {
1249         struct hns3_umv_spc_alc_cmd *req;
1250         struct hns3_cmd_desc desc;
1251         int ret;
1252
1253         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1254         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1255         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1256         req->space_size = rte_cpu_to_le_32(space_size);
1257
1258         ret = hns3_cmd_send(hw, &desc, 1);
1259         if (ret) {
1260                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1261                              is_alloc ? "allocate" : "free", ret);
1262                 return ret;
1263         }
1264
1265         if (is_alloc && allocated_size)
1266                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1267
1268         return 0;
1269 }
1270
1271 static int
1272 hns3_init_umv_space(struct hns3_hw *hw)
1273 {
1274         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1275         struct hns3_pf *pf = &hns->pf;
1276         uint16_t allocated_size = 0;
1277         int ret;
1278
1279         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1280                                  true);
1281         if (ret)
1282                 return ret;
1283
1284         if (allocated_size < pf->wanted_umv_size)
1285                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1286                              pf->wanted_umv_size, allocated_size);
1287
1288         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1289                                                 pf->wanted_umv_size;
1290         pf->used_umv_size = 0;
1291         return 0;
1292 }
1293
1294 static int
1295 hns3_uninit_umv_space(struct hns3_hw *hw)
1296 {
1297         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1298         struct hns3_pf *pf = &hns->pf;
1299         int ret;
1300
1301         if (pf->max_umv_size == 0)
1302                 return 0;
1303
1304         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1305         if (ret)
1306                 return ret;
1307
1308         pf->max_umv_size = 0;
1309
1310         return 0;
1311 }
1312
1313 static bool
1314 hns3_is_umv_space_full(struct hns3_hw *hw)
1315 {
1316         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1317         struct hns3_pf *pf = &hns->pf;
1318         bool is_full;
1319
1320         is_full = (pf->used_umv_size >= pf->max_umv_size);
1321
1322         return is_full;
1323 }
1324
1325 static void
1326 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1327 {
1328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329         struct hns3_pf *pf = &hns->pf;
1330
1331         if (is_free) {
1332                 if (pf->used_umv_size > 0)
1333                         pf->used_umv_size--;
1334         } else
1335                 pf->used_umv_size++;
1336 }
1337
1338 static void
1339 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1340                       const uint8_t *addr, bool is_mc)
1341 {
1342         const unsigned char *mac_addr = addr;
1343         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1344                             ((uint32_t)mac_addr[2] << 16) |
1345                             ((uint32_t)mac_addr[1] << 8) |
1346                             (uint32_t)mac_addr[0];
1347         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1348
1349         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1350         if (is_mc) {
1351                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1352                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1353                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1354         }
1355
1356         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1357         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1358 }
1359
1360 static int
1361 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1362                              uint8_t resp_code,
1363                              enum hns3_mac_vlan_tbl_opcode op)
1364 {
1365         if (cmdq_resp) {
1366                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1367                          cmdq_resp);
1368                 return -EIO;
1369         }
1370
1371         if (op == HNS3_MAC_VLAN_ADD) {
1372                 if (resp_code == 0 || resp_code == 1) {
1373                         return 0;
1374                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1375                         hns3_err(hw, "add mac addr failed for uc_overflow");
1376                         return -ENOSPC;
1377                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1378                         hns3_err(hw, "add mac addr failed for mc_overflow");
1379                         return -ENOSPC;
1380                 }
1381
1382                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1383                          resp_code);
1384                 return -EIO;
1385         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1386                 if (resp_code == 0) {
1387                         return 0;
1388                 } else if (resp_code == 1) {
1389                         hns3_dbg(hw, "remove mac addr failed for miss");
1390                         return -ENOENT;
1391                 }
1392
1393                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1394                          resp_code);
1395                 return -EIO;
1396         } else if (op == HNS3_MAC_VLAN_LKUP) {
1397                 if (resp_code == 0) {
1398                         return 0;
1399                 } else if (resp_code == 1) {
1400                         hns3_dbg(hw, "lookup mac addr failed for miss");
1401                         return -ENOENT;
1402                 }
1403
1404                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1405                          resp_code);
1406                 return -EIO;
1407         }
1408
1409         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1410                  op);
1411
1412         return -EINVAL;
1413 }
1414
1415 static int
1416 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1417                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1418                          struct hns3_cmd_desc *desc, bool is_mc)
1419 {
1420         uint8_t resp_code;
1421         uint16_t retval;
1422         int ret;
1423
1424         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1425         if (is_mc) {
1426                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1427                 memcpy(desc[0].data, req,
1428                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1429                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1430                                           true);
1431                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1432                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1433                                           true);
1434                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1435         } else {
1436                 memcpy(desc[0].data, req,
1437                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1438                 ret = hns3_cmd_send(hw, desc, 1);
1439         }
1440         if (ret) {
1441                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1442                          ret);
1443                 return ret;
1444         }
1445         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1446         retval = rte_le_to_cpu_16(desc[0].retval);
1447
1448         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1449                                             HNS3_MAC_VLAN_LKUP);
1450 }
1451
1452 static int
1453 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1454                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1455                       struct hns3_cmd_desc *mc_desc)
1456 {
1457         uint8_t resp_code;
1458         uint16_t retval;
1459         int cfg_status;
1460         int ret;
1461
1462         if (mc_desc == NULL) {
1463                 struct hns3_cmd_desc desc;
1464
1465                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1466                 memcpy(desc.data, req,
1467                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1468                 ret = hns3_cmd_send(hw, &desc, 1);
1469                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1470                 retval = rte_le_to_cpu_16(desc.retval);
1471
1472                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1473                                                           HNS3_MAC_VLAN_ADD);
1474         } else {
1475                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1476                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1477                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1478                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1479                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1480                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1481                 memcpy(mc_desc[0].data, req,
1482                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1483                 mc_desc[0].retval = 0;
1484                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1485                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1486                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1487
1488                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1489                                                           HNS3_MAC_VLAN_ADD);
1490         }
1491
1492         if (ret) {
1493                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1494                 return ret;
1495         }
1496
1497         return cfg_status;
1498 }
1499
1500 static int
1501 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1502                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1503 {
1504         struct hns3_cmd_desc desc;
1505         uint8_t resp_code;
1506         uint16_t retval;
1507         int ret;
1508
1509         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1510
1511         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1512
1513         ret = hns3_cmd_send(hw, &desc, 1);
1514         if (ret) {
1515                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1516                 return ret;
1517         }
1518         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1519         retval = rte_le_to_cpu_16(desc.retval);
1520
1521         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1522                                             HNS3_MAC_VLAN_REMOVE);
1523 }
1524
1525 static int
1526 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1527 {
1528         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1529         struct hns3_mac_vlan_tbl_entry_cmd req;
1530         struct hns3_pf *pf = &hns->pf;
1531         struct hns3_cmd_desc desc[3];
1532         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1533         uint16_t egress_port = 0;
1534         uint8_t vf_id;
1535         int ret;
1536
1537         /* check if mac addr is valid */
1538         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1539                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1540                                       mac_addr);
1541                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1542                          mac_str);
1543                 return -EINVAL;
1544         }
1545
1546         memset(&req, 0, sizeof(req));
1547
1548         /*
1549          * In current version VF is not supported when PF is driven by DPDK
1550          * driver, just need to configure parameters for PF vport.
1551          */
1552         vf_id = HNS3_PF_FUNC_ID;
1553         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1554                        HNS3_MAC_EPORT_VFID_S, vf_id);
1555
1556         req.egress_port = rte_cpu_to_le_16(egress_port);
1557
1558         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1559
1560         /*
1561          * Lookup the mac address in the mac_vlan table, and add
1562          * it if the entry is inexistent. Repeated unicast entry
1563          * is not allowed in the mac vlan table.
1564          */
1565         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1566         if (ret == -ENOENT) {
1567                 if (!hns3_is_umv_space_full(hw)) {
1568                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1569                         if (!ret)
1570                                 hns3_update_umv_space(hw, false);
1571                         return ret;
1572                 }
1573
1574                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1575
1576                 return -ENOSPC;
1577         }
1578
1579         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1580
1581         /* check if we just hit the duplicate */
1582         if (ret == 0) {
1583                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1584                 return 0;
1585         }
1586
1587         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1588                  mac_str);
1589
1590         return ret;
1591 }
1592
1593 static int
1594 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1595 {
1596         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1597         struct rte_ether_addr *addr;
1598         int ret;
1599         int i;
1600
1601         for (i = 0; i < hw->mc_addrs_num; i++) {
1602                 addr = &hw->mc_addrs[i];
1603                 /* Check if there are duplicate addresses */
1604                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1605                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1606                                               addr);
1607                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1608                                  "(%s) is added by the set_mc_mac_addr_list "
1609                                  "API", mac_str);
1610                         return -EINVAL;
1611                 }
1612         }
1613
1614         ret = hns3_add_mc_addr(hw, mac_addr);
1615         if (ret) {
1616                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1617                                       mac_addr);
1618                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1619                          mac_str, ret);
1620         }
1621         return ret;
1622 }
1623
1624 static int
1625 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1626 {
1627         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1628         int ret;
1629
1630         ret = hns3_remove_mc_addr(hw, mac_addr);
1631         if (ret) {
1632                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1633                                       mac_addr);
1634                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1635                          mac_str, ret);
1636         }
1637         return ret;
1638 }
1639
1640 static int
1641 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1642                   uint32_t idx, __rte_unused uint32_t pool)
1643 {
1644         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1646         int ret;
1647
1648         rte_spinlock_lock(&hw->lock);
1649
1650         /*
1651          * In hns3 network engine adding UC and MC mac address with different
1652          * commands with firmware. We need to determine whether the input
1653          * address is a UC or a MC address to call different commands.
1654          * By the way, it is recommended calling the API function named
1655          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1656          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1657          * may affect the specifications of UC mac addresses.
1658          */
1659         if (rte_is_multicast_ether_addr(mac_addr))
1660                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1661         else
1662                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1663
1664         if (ret) {
1665                 rte_spinlock_unlock(&hw->lock);
1666                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1667                                       mac_addr);
1668                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1669                          ret);
1670                 return ret;
1671         }
1672
1673         if (idx == 0)
1674                 hw->mac.default_addr_setted = true;
1675         rte_spinlock_unlock(&hw->lock);
1676
1677         return ret;
1678 }
1679
1680 static int
1681 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1682 {
1683         struct hns3_mac_vlan_tbl_entry_cmd req;
1684         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1685         int ret;
1686
1687         /* check if mac addr is valid */
1688         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1689                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1690                                       mac_addr);
1691                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1692                          mac_str);
1693                 return -EINVAL;
1694         }
1695
1696         memset(&req, 0, sizeof(req));
1697         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1698         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1699         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1700         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1701                 return 0;
1702         else if (ret == 0)
1703                 hns3_update_umv_space(hw, true);
1704
1705         return ret;
1706 }
1707
1708 static void
1709 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1710 {
1711         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         /* index will be checked by upper level rte interface */
1713         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1714         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1715         int ret;
1716
1717         rte_spinlock_lock(&hw->lock);
1718
1719         if (rte_is_multicast_ether_addr(mac_addr))
1720                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1721         else
1722                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1723         rte_spinlock_unlock(&hw->lock);
1724         if (ret) {
1725                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1726                                       mac_addr);
1727                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1728                          ret);
1729         }
1730 }
1731
1732 static int
1733 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1734                           struct rte_ether_addr *mac_addr)
1735 {
1736         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         struct rte_ether_addr *oaddr;
1738         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1739         bool default_addr_setted;
1740         bool rm_succes = false;
1741         int ret, ret_val;
1742
1743         /*
1744          * It has been guaranteed that input parameter named mac_addr is valid
1745          * address in the rte layer of DPDK framework.
1746          */
1747         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1748         default_addr_setted = hw->mac.default_addr_setted;
1749         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1750                 return 0;
1751
1752         rte_spinlock_lock(&hw->lock);
1753         if (default_addr_setted) {
1754                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1755                 if (ret) {
1756                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1757                                               oaddr);
1758                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1759                                   mac_str, ret);
1760                         rm_succes = false;
1761                 } else
1762                         rm_succes = true;
1763         }
1764
1765         ret = hns3_add_uc_addr_common(hw, mac_addr);
1766         if (ret) {
1767                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768                                       mac_addr);
1769                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1770                 goto err_add_uc_addr;
1771         }
1772
1773         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1774         if (ret) {
1775                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1776                 goto err_pause_addr_cfg;
1777         }
1778
1779         rte_ether_addr_copy(mac_addr,
1780                             (struct rte_ether_addr *)hw->mac.mac_addr);
1781         hw->mac.default_addr_setted = true;
1782         rte_spinlock_unlock(&hw->lock);
1783
1784         return 0;
1785
1786 err_pause_addr_cfg:
1787         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1788         if (ret_val) {
1789                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1790                                       mac_addr);
1791                 hns3_warn(hw,
1792                           "Failed to roll back to del setted mac addr(%s): %d",
1793                           mac_str, ret_val);
1794         }
1795
1796 err_add_uc_addr:
1797         if (rm_succes) {
1798                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1799                 if (ret_val) {
1800                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1801                                               oaddr);
1802                         hns3_warn(hw,
1803                                   "Failed to restore old uc mac addr(%s): %d",
1804                                   mac_str, ret_val);
1805                         hw->mac.default_addr_setted = false;
1806                 }
1807         }
1808         rte_spinlock_unlock(&hw->lock);
1809
1810         return ret;
1811 }
1812
1813 static int
1814 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1815 {
1816         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1817         struct hns3_hw *hw = &hns->hw;
1818         struct rte_ether_addr *addr;
1819         int err = 0;
1820         int ret;
1821         int i;
1822
1823         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1824                 addr = &hw->data->mac_addrs[i];
1825                 if (rte_is_zero_ether_addr(addr))
1826                         continue;
1827                 if (rte_is_multicast_ether_addr(addr))
1828                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1829                               hns3_add_mc_addr(hw, addr);
1830                 else
1831                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1832                               hns3_add_uc_addr_common(hw, addr);
1833
1834                 if (ret) {
1835                         err = ret;
1836                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1837                                               addr);
1838                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1839                                  "ret = %d.", del ? "remove" : "restore",
1840                                  mac_str, i, ret);
1841                 }
1842         }
1843         return err;
1844 }
1845
1846 static void
1847 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1848 {
1849 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1850         uint8_t word_num;
1851         uint8_t bit_num;
1852
1853         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1854                 word_num = vfid / 32;
1855                 bit_num = vfid % 32;
1856                 if (clr)
1857                         desc[1].data[word_num] &=
1858                             rte_cpu_to_le_32(~(1UL << bit_num));
1859                 else
1860                         desc[1].data[word_num] |=
1861                             rte_cpu_to_le_32(1UL << bit_num);
1862         } else {
1863                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1864                 bit_num = vfid % 32;
1865                 if (clr)
1866                         desc[2].data[word_num] &=
1867                             rte_cpu_to_le_32(~(1UL << bit_num));
1868                 else
1869                         desc[2].data[word_num] |=
1870                             rte_cpu_to_le_32(1UL << bit_num);
1871         }
1872 }
1873
1874 static int
1875 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1876 {
1877         struct hns3_mac_vlan_tbl_entry_cmd req;
1878         struct hns3_cmd_desc desc[3];
1879         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1880         uint8_t vf_id;
1881         int ret;
1882
1883         /* Check if mac addr is valid */
1884         if (!rte_is_multicast_ether_addr(mac_addr)) {
1885                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1886                                       mac_addr);
1887                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1888                          mac_str);
1889                 return -EINVAL;
1890         }
1891
1892         memset(&req, 0, sizeof(req));
1893         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1894         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1895         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1896         if (ret) {
1897                 /* This mac addr do not exist, add new entry for it */
1898                 memset(desc[0].data, 0, sizeof(desc[0].data));
1899                 memset(desc[1].data, 0, sizeof(desc[0].data));
1900                 memset(desc[2].data, 0, sizeof(desc[0].data));
1901         }
1902
1903         /*
1904          * In current version VF is not supported when PF is driven by DPDK
1905          * driver, just need to configure parameters for PF vport.
1906          */
1907         vf_id = HNS3_PF_FUNC_ID;
1908         hns3_update_desc_vfid(desc, vf_id, false);
1909         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1910         if (ret) {
1911                 if (ret == -ENOSPC)
1912                         hns3_err(hw, "mc mac vlan table is full");
1913                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1914                                       mac_addr);
1915                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1916         }
1917
1918         return ret;
1919 }
1920
1921 static int
1922 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1923 {
1924         struct hns3_mac_vlan_tbl_entry_cmd req;
1925         struct hns3_cmd_desc desc[3];
1926         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1927         uint8_t vf_id;
1928         int ret;
1929
1930         /* Check if mac addr is valid */
1931         if (!rte_is_multicast_ether_addr(mac_addr)) {
1932                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1933                                       mac_addr);
1934                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1935                          mac_str);
1936                 return -EINVAL;
1937         }
1938
1939         memset(&req, 0, sizeof(req));
1940         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1941         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1942         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1943         if (ret == 0) {
1944                 /*
1945                  * This mac addr exist, remove this handle's VFID for it.
1946                  * In current version VF is not supported when PF is driven by
1947                  * DPDK driver, just need to configure parameters for PF vport.
1948                  */
1949                 vf_id = HNS3_PF_FUNC_ID;
1950                 hns3_update_desc_vfid(desc, vf_id, true);
1951
1952                 /* All the vfid is zero, so need to delete this entry */
1953                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1954         } else if (ret == -ENOENT) {
1955                 /* This mac addr doesn't exist. */
1956                 return 0;
1957         }
1958
1959         if (ret) {
1960                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1961                                       mac_addr);
1962                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1963         }
1964
1965         return ret;
1966 }
1967
1968 static int
1969 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1970                            struct rte_ether_addr *mc_addr_set,
1971                            uint32_t nb_mc_addr)
1972 {
1973         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1974         struct rte_ether_addr *addr;
1975         uint32_t i;
1976         uint32_t j;
1977
1978         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1979                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1980                          "invalid. valid range: 0~%d",
1981                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1982                 return -EINVAL;
1983         }
1984
1985         /* Check if input mac addresses are valid */
1986         for (i = 0; i < nb_mc_addr; i++) {
1987                 addr = &mc_addr_set[i];
1988                 if (!rte_is_multicast_ether_addr(addr)) {
1989                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1990                                               addr);
1991                         hns3_err(hw,
1992                                  "failed to set mc mac addr, addr(%s) invalid.",
1993                                  mac_str);
1994                         return -EINVAL;
1995                 }
1996
1997                 /* Check if there are duplicate addresses */
1998                 for (j = i + 1; j < nb_mc_addr; j++) {
1999                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2000                                 hns3_ether_format_addr(mac_str,
2001                                                       RTE_ETHER_ADDR_FMT_SIZE,
2002                                                       addr);
2003                                 hns3_err(hw, "failed to set mc mac addr, "
2004                                          "addrs invalid. two same addrs(%s).",
2005                                          mac_str);
2006                                 return -EINVAL;
2007                         }
2008                 }
2009
2010                 /*
2011                  * Check if there are duplicate addresses between mac_addrs
2012                  * and mc_addr_set
2013                  */
2014                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2015                         if (rte_is_same_ether_addr(addr,
2016                                                    &hw->data->mac_addrs[j])) {
2017                                 hns3_ether_format_addr(mac_str,
2018                                                       RTE_ETHER_ADDR_FMT_SIZE,
2019                                                       addr);
2020                                 hns3_err(hw, "failed to set mc mac addr, "
2021                                          "addrs invalid. addrs(%s) has already "
2022                                          "configured in mac_addr add API",
2023                                          mac_str);
2024                                 return -EINVAL;
2025                         }
2026                 }
2027         }
2028
2029         return 0;
2030 }
2031
2032 static void
2033 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2034                            struct rte_ether_addr *mc_addr_set,
2035                            int mc_addr_num,
2036                            struct rte_ether_addr *reserved_addr_list,
2037                            int *reserved_addr_num,
2038                            struct rte_ether_addr *add_addr_list,
2039                            int *add_addr_num,
2040                            struct rte_ether_addr *rm_addr_list,
2041                            int *rm_addr_num)
2042 {
2043         struct rte_ether_addr *addr;
2044         int current_addr_num;
2045         int reserved_num = 0;
2046         int add_num = 0;
2047         int rm_num = 0;
2048         int num;
2049         int i;
2050         int j;
2051         bool same_addr;
2052
2053         /* Calculate the mc mac address list that should be removed */
2054         current_addr_num = hw->mc_addrs_num;
2055         for (i = 0; i < current_addr_num; i++) {
2056                 addr = &hw->mc_addrs[i];
2057                 same_addr = false;
2058                 for (j = 0; j < mc_addr_num; j++) {
2059                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2060                                 same_addr = true;
2061                                 break;
2062                         }
2063                 }
2064
2065                 if (!same_addr) {
2066                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2067                         rm_num++;
2068                 } else {
2069                         rte_ether_addr_copy(addr,
2070                                             &reserved_addr_list[reserved_num]);
2071                         reserved_num++;
2072                 }
2073         }
2074
2075         /* Calculate the mc mac address list that should be added */
2076         for (i = 0; i < mc_addr_num; i++) {
2077                 addr = &mc_addr_set[i];
2078                 same_addr = false;
2079                 for (j = 0; j < current_addr_num; j++) {
2080                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2081                                 same_addr = true;
2082                                 break;
2083                         }
2084                 }
2085
2086                 if (!same_addr) {
2087                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2088                         add_num++;
2089                 }
2090         }
2091
2092         /* Reorder the mc mac address list maintained by driver */
2093         for (i = 0; i < reserved_num; i++)
2094                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2095
2096         for (i = 0; i < rm_num; i++) {
2097                 num = reserved_num + i;
2098                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2099         }
2100
2101         *reserved_addr_num = reserved_num;
2102         *add_addr_num = add_num;
2103         *rm_addr_num = rm_num;
2104 }
2105
2106 static int
2107 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2108                           struct rte_ether_addr *mc_addr_set,
2109                           uint32_t nb_mc_addr)
2110 {
2111         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2113         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2114         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2115         struct rte_ether_addr *addr;
2116         int reserved_addr_num;
2117         int add_addr_num;
2118         int rm_addr_num;
2119         int mc_addr_num;
2120         int num;
2121         int ret;
2122         int i;
2123
2124         /* Check if input parameters are valid */
2125         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2126         if (ret)
2127                 return ret;
2128
2129         rte_spinlock_lock(&hw->lock);
2130
2131         /*
2132          * Calculate the mc mac address lists those should be removed and be
2133          * added, Reorder the mc mac address list maintained by driver.
2134          */
2135         mc_addr_num = (int)nb_mc_addr;
2136         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2137                                    reserved_addr_list, &reserved_addr_num,
2138                                    add_addr_list, &add_addr_num,
2139                                    rm_addr_list, &rm_addr_num);
2140
2141         /* Remove mc mac addresses */
2142         for (i = 0; i < rm_addr_num; i++) {
2143                 num = rm_addr_num - i - 1;
2144                 addr = &rm_addr_list[num];
2145                 ret = hns3_remove_mc_addr(hw, addr);
2146                 if (ret) {
2147                         rte_spinlock_unlock(&hw->lock);
2148                         return ret;
2149                 }
2150                 hw->mc_addrs_num--;
2151         }
2152
2153         /* Add mc mac addresses */
2154         for (i = 0; i < add_addr_num; i++) {
2155                 addr = &add_addr_list[i];
2156                 ret = hns3_add_mc_addr(hw, addr);
2157                 if (ret) {
2158                         rte_spinlock_unlock(&hw->lock);
2159                         return ret;
2160                 }
2161
2162                 num = reserved_addr_num + i;
2163                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2164                 hw->mc_addrs_num++;
2165         }
2166         rte_spinlock_unlock(&hw->lock);
2167
2168         return 0;
2169 }
2170
2171 static int
2172 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2173 {
2174         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2175         struct hns3_hw *hw = &hns->hw;
2176         struct rte_ether_addr *addr;
2177         int err = 0;
2178         int ret;
2179         int i;
2180
2181         for (i = 0; i < hw->mc_addrs_num; i++) {
2182                 addr = &hw->mc_addrs[i];
2183                 if (!rte_is_multicast_ether_addr(addr))
2184                         continue;
2185                 if (del)
2186                         ret = hns3_remove_mc_addr(hw, addr);
2187                 else
2188                         ret = hns3_add_mc_addr(hw, addr);
2189                 if (ret) {
2190                         err = ret;
2191                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2192                                               addr);
2193                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2194                                  del ? "Remove" : "Restore", mac_str, ret);
2195                 }
2196         }
2197         return err;
2198 }
2199
2200 static int
2201 hns3_check_mq_mode(struct rte_eth_dev *dev)
2202 {
2203         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2204         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2205         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2207         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2208         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2209         uint8_t num_tc;
2210         int max_tc = 0;
2211         int i;
2212
2213         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2214         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2215
2216         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2217                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2218                          "rx_mq_mode = %d", rx_mq_mode);
2219                 return -EINVAL;
2220         }
2221
2222         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2223             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2224                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2225                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2226                          rx_mq_mode, tx_mq_mode);
2227                 return -EINVAL;
2228         }
2229
2230         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2231                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2232                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2233                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2234                         return -EINVAL;
2235                 }
2236
2237                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2238                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2239                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2240                                  "nb_tcs(%d) != %d or %d in rx direction.",
2241                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2242                         return -EINVAL;
2243                 }
2244
2245                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2246                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2247                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2248                         return -EINVAL;
2249                 }
2250
2251                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2252                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2253                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2254                                          "is not equal to one in tx direction.",
2255                                          i, dcb_rx_conf->dcb_tc[i]);
2256                                 return -EINVAL;
2257                         }
2258                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2259                                 max_tc = dcb_rx_conf->dcb_tc[i];
2260                 }
2261
2262                 num_tc = max_tc + 1;
2263                 if (num_tc > dcb_rx_conf->nb_tcs) {
2264                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2265                                  num_tc, dcb_rx_conf->nb_tcs);
2266                         return -EINVAL;
2267                 }
2268         }
2269
2270         return 0;
2271 }
2272
2273 static int
2274 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2275 {
2276         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277
2278         if (!hns3_dev_dcb_supported(hw)) {
2279                 hns3_err(hw, "this port does not support dcb configurations.");
2280                 return -EOPNOTSUPP;
2281         }
2282
2283         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2284                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2285                 return -EOPNOTSUPP;
2286         }
2287
2288         /* Check multiple queue mode */
2289         return hns3_check_mq_mode(dev);
2290 }
2291
2292 static int
2293 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2294                            enum hns3_ring_type queue_type, uint16_t queue_id)
2295 {
2296         struct hns3_cmd_desc desc;
2297         struct hns3_ctrl_vector_chain_cmd *req =
2298                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2299         enum hns3_cmd_status status;
2300         enum hns3_opcode_type op;
2301         uint16_t tqp_type_and_id = 0;
2302         uint16_t type;
2303         uint16_t gl;
2304
2305         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2306         hns3_cmd_setup_basic_desc(&desc, op, false);
2307         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2308                                               HNS3_TQP_INT_ID_L_S);
2309         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2310                                               HNS3_TQP_INT_ID_H_S);
2311
2312         if (queue_type == HNS3_RING_TYPE_RX)
2313                 gl = HNS3_RING_GL_RX;
2314         else
2315                 gl = HNS3_RING_GL_TX;
2316
2317         type = queue_type;
2318
2319         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2320                        type);
2321         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2322         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2323                        gl);
2324         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2325         req->int_cause_num = 1;
2326         status = hns3_cmd_send(hw, &desc, 1);
2327         if (status) {
2328                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2329                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2330                 return status;
2331         }
2332
2333         return 0;
2334 }
2335
2336 static int
2337 hns3_init_ring_with_vector(struct hns3_hw *hw)
2338 {
2339         uint16_t vec;
2340         int ret;
2341         int i;
2342
2343         /*
2344          * In hns3 network engine, vector 0 is always the misc interrupt of this
2345          * function, vector 1~N can be used respectively for the queues of the
2346          * function. Tx and Rx queues with the same number share the interrupt
2347          * vector. In the initialization clearing the all hardware mapping
2348          * relationship configurations between queues and interrupt vectors is
2349          * needed, so some error caused by the residual configurations, such as
2350          * the unexpected Tx interrupt, can be avoid.
2351          */
2352         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2353         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2354                 vec = vec - 1; /* the last interrupt is reserved */
2355         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2356         for (i = 0; i < hw->intr_tqps_num; i++) {
2357                 /*
2358                  * Set gap limiter/rate limiter/quanity limiter algorithm
2359                  * configuration for interrupt coalesce of queue's interrupt.
2360                  */
2361                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2362                                        HNS3_TQP_INTR_GL_DEFAULT);
2363                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2364                                        HNS3_TQP_INTR_GL_DEFAULT);
2365                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2366                 /*
2367                  * QL(quantity limiter) is not used currently, just set 0 to
2368                  * close it.
2369                  */
2370                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2371
2372                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2373                                                  HNS3_RING_TYPE_TX, i);
2374                 if (ret) {
2375                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2376                                           "vector: %u, ret=%d", i, vec, ret);
2377                         return ret;
2378                 }
2379
2380                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2381                                                  HNS3_RING_TYPE_RX, i);
2382                 if (ret) {
2383                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2384                                           "vector: %u, ret=%d", i, vec, ret);
2385                         return ret;
2386                 }
2387         }
2388
2389         return 0;
2390 }
2391
2392 static int
2393 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2394 {
2395         struct hns3_adapter *hns = dev->data->dev_private;
2396         struct hns3_hw *hw = &hns->hw;
2397         uint32_t max_rx_pkt_len;
2398         uint16_t mtu;
2399         int ret;
2400
2401         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2402                 return 0;
2403
2404         /*
2405          * If jumbo frames are enabled, MTU needs to be refreshed
2406          * according to the maximum RX packet length.
2407          */
2408         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2409         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2410             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2411                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2412                          "and no more than %u when jumbo frame enabled.",
2413                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2414                          (uint16_t)HNS3_MAX_FRAME_LEN);
2415                 return -EINVAL;
2416         }
2417
2418         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2419         ret = hns3_dev_mtu_set(dev, mtu);
2420         if (ret)
2421                 return ret;
2422         dev->data->mtu = mtu;
2423
2424         return 0;
2425 }
2426
2427 static int
2428 hns3_dev_configure(struct rte_eth_dev *dev)
2429 {
2430         struct hns3_adapter *hns = dev->data->dev_private;
2431         struct rte_eth_conf *conf = &dev->data->dev_conf;
2432         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2433         struct hns3_hw *hw = &hns->hw;
2434         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2435         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2436         struct rte_eth_rss_conf rss_conf;
2437         bool gro_en;
2438         int ret;
2439
2440         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2441
2442         /*
2443          * Some versions of hardware network engine does not support
2444          * individually enable/disable/reset the Tx or Rx queue. These devices
2445          * must enable/disable/reset Tx and Rx queues at the same time. When the
2446          * numbers of Tx queues allocated by upper applications are not equal to
2447          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2448          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2449          * work as usual. But these fake queues are imperceptible, and can not
2450          * be used by upper applications.
2451          */
2452         if (!hns3_dev_indep_txrx_supported(hw)) {
2453                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2454                 if (ret) {
2455                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2456                                  ret);
2457                         return ret;
2458                 }
2459         }
2460
2461         hw->adapter_state = HNS3_NIC_CONFIGURING;
2462         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2463                 hns3_err(hw, "setting link speed/duplex not supported");
2464                 ret = -EINVAL;
2465                 goto cfg_err;
2466         }
2467
2468         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2469                 ret = hns3_check_dcb_cfg(dev);
2470                 if (ret)
2471                         goto cfg_err;
2472         }
2473
2474         /* When RSS is not configured, redirect the packet queue 0 */
2475         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2476                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2477                 rss_conf = conf->rx_adv_conf.rss_conf;
2478                 hw->rss_dis_flag = false;
2479                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2480                 if (ret)
2481                         goto cfg_err;
2482         }
2483
2484         ret = hns3_refresh_mtu(dev, conf);
2485         if (ret)
2486                 goto cfg_err;
2487
2488         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2489         if (ret)
2490                 goto cfg_err;
2491
2492         ret = hns3_dev_configure_vlan(dev);
2493         if (ret)
2494                 goto cfg_err;
2495
2496         /* config hardware GRO */
2497         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2498         ret = hns3_config_gro(hw, gro_en);
2499         if (ret)
2500                 goto cfg_err;
2501
2502         hns->rx_simple_allowed = true;
2503         hns->rx_vec_allowed = true;
2504         hns->tx_simple_allowed = true;
2505         hns->tx_vec_allowed = true;
2506
2507         hns3_init_rx_ptype_tble(dev);
2508         hw->adapter_state = HNS3_NIC_CONFIGURED;
2509
2510         return 0;
2511
2512 cfg_err:
2513         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2514         hw->adapter_state = HNS3_NIC_INITIALIZED;
2515
2516         return ret;
2517 }
2518
2519 static int
2520 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2521 {
2522         struct hns3_config_max_frm_size_cmd *req;
2523         struct hns3_cmd_desc desc;
2524
2525         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2526
2527         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2528         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2529         req->min_frm_size = RTE_ETHER_MIN_LEN;
2530
2531         return hns3_cmd_send(hw, &desc, 1);
2532 }
2533
2534 static int
2535 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2536 {
2537         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2538         uint16_t original_mps = hns->pf.mps;
2539         int err;
2540         int ret;
2541
2542         ret = hns3_set_mac_mtu(hw, mps);
2543         if (ret) {
2544                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2545                 return ret;
2546         }
2547
2548         hns->pf.mps = mps;
2549         ret = hns3_buffer_alloc(hw);
2550         if (ret) {
2551                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2552                 goto rollback;
2553         }
2554
2555         return 0;
2556
2557 rollback:
2558         err = hns3_set_mac_mtu(hw, original_mps);
2559         if (err) {
2560                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2561                 return ret;
2562         }
2563         hns->pf.mps = original_mps;
2564
2565         return ret;
2566 }
2567
2568 static int
2569 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2570 {
2571         struct hns3_adapter *hns = dev->data->dev_private;
2572         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2573         struct hns3_hw *hw = &hns->hw;
2574         bool is_jumbo_frame;
2575         int ret;
2576
2577         if (dev->data->dev_started) {
2578                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2579                          "before configuration", dev->data->port_id);
2580                 return -EBUSY;
2581         }
2582
2583         rte_spinlock_lock(&hw->lock);
2584         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2585         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2586
2587         /*
2588          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2589          * assign to "uint16_t" type variable.
2590          */
2591         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2592         if (ret) {
2593                 rte_spinlock_unlock(&hw->lock);
2594                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2595                          dev->data->port_id, mtu, ret);
2596                 return ret;
2597         }
2598
2599         if (is_jumbo_frame)
2600                 dev->data->dev_conf.rxmode.offloads |=
2601                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2602         else
2603                 dev->data->dev_conf.rxmode.offloads &=
2604                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2605         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2606         rte_spinlock_unlock(&hw->lock);
2607
2608         return 0;
2609 }
2610
2611 int
2612 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2613 {
2614         struct hns3_adapter *hns = eth_dev->data->dev_private;
2615         struct hns3_hw *hw = &hns->hw;
2616         uint16_t queue_num = hw->tqps_num;
2617
2618         /*
2619          * In interrupt mode, 'max_rx_queues' is set based on the number of
2620          * MSI-X interrupt resources of the hardware.
2621          */
2622         if (hw->data->dev_conf.intr_conf.rxq == 1)
2623                 queue_num = hw->intr_tqps_num;
2624
2625         info->max_rx_queues = queue_num;
2626         info->max_tx_queues = hw->tqps_num;
2627         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2628         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2629         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2630         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2631         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2632         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2633                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2634                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2635                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2636                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2637                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2638                                  DEV_RX_OFFLOAD_KEEP_CRC |
2639                                  DEV_RX_OFFLOAD_SCATTER |
2640                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2641                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2642                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2643                                  DEV_RX_OFFLOAD_RSS_HASH |
2644                                  DEV_RX_OFFLOAD_TCP_LRO);
2645         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2646                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2647                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2648                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2649                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2650                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2651                                  DEV_TX_OFFLOAD_TCP_TSO |
2652                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2653                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2654                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2655                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2656                                  hns3_txvlan_cap_get(hw));
2657
2658         if (hns3_dev_outer_udp_cksum_supported(hw))
2659                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2660
2661         if (hns3_dev_indep_txrx_supported(hw))
2662                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2663                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2664
2665         if (hns3_dev_ptp_supported(hw))
2666                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2667
2668         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2669                 .nb_max = HNS3_MAX_RING_DESC,
2670                 .nb_min = HNS3_MIN_RING_DESC,
2671                 .nb_align = HNS3_ALIGN_RING_DESC,
2672         };
2673
2674         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2675                 .nb_max = HNS3_MAX_RING_DESC,
2676                 .nb_min = HNS3_MIN_RING_DESC,
2677                 .nb_align = HNS3_ALIGN_RING_DESC,
2678                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2679                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2680         };
2681
2682         info->default_rxconf = (struct rte_eth_rxconf) {
2683                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2684                 /*
2685                  * If there are no available Rx buffer descriptors, incoming
2686                  * packets are always dropped by hardware based on hns3 network
2687                  * engine.
2688                  */
2689                 .rx_drop_en = 1,
2690                 .offloads = 0,
2691         };
2692         info->default_txconf = (struct rte_eth_txconf) {
2693                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2694                 .offloads = 0,
2695         };
2696
2697         info->vmdq_queue_num = 0;
2698
2699         info->reta_size = hw->rss_ind_tbl_size;
2700         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2701         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2702
2703         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2704         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2705         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2706         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2707         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2708         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2709
2710         return 0;
2711 }
2712
2713 static int
2714 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2715                     size_t fw_size)
2716 {
2717         struct hns3_adapter *hns = eth_dev->data->dev_private;
2718         struct hns3_hw *hw = &hns->hw;
2719         uint32_t version = hw->fw_version;
2720         int ret;
2721
2722         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2723                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2724                                       HNS3_FW_VERSION_BYTE3_S),
2725                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2726                                       HNS3_FW_VERSION_BYTE2_S),
2727                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2728                                       HNS3_FW_VERSION_BYTE1_S),
2729                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2730                                       HNS3_FW_VERSION_BYTE0_S));
2731         ret += 1; /* add the size of '\0' */
2732         if (fw_size < (uint32_t)ret)
2733                 return ret;
2734         else
2735                 return 0;
2736 }
2737
2738 static int
2739 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2740 {
2741         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2742
2743         (void)hns3_update_link_status(hw);
2744
2745         return hns3_update_link_info(eth_dev);
2746 }
2747
2748 static void
2749 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2750                       struct rte_eth_link *new_link)
2751 {
2752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2753         struct hns3_mac *mac = &hw->mac;
2754
2755         switch (mac->link_speed) {
2756         case ETH_SPEED_NUM_10M:
2757         case ETH_SPEED_NUM_100M:
2758         case ETH_SPEED_NUM_1G:
2759         case ETH_SPEED_NUM_10G:
2760         case ETH_SPEED_NUM_25G:
2761         case ETH_SPEED_NUM_40G:
2762         case ETH_SPEED_NUM_50G:
2763         case ETH_SPEED_NUM_100G:
2764         case ETH_SPEED_NUM_200G:
2765                 new_link->link_speed = mac->link_speed;
2766                 break;
2767         default:
2768                 if (mac->link_status)
2769                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2770                 else
2771                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2772                 break;
2773         }
2774
2775         new_link->link_duplex = mac->link_duplex;
2776         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2777         new_link->link_autoneg =
2778             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2779 }
2780
2781 static int
2782 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2783                      __rte_unused int wait_to_complete)
2784 {
2785         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2786         struct hns3_mac *mac = &hw->mac;
2787         struct rte_eth_link new_link;
2788         int ret;
2789
2790         ret = hns3_update_port_link_info(eth_dev);
2791         if (ret) {
2792                 mac->link_status = ETH_LINK_DOWN;
2793                 hns3_err(hw, "failed to get port link info, ret = %d.", ret);
2794         }
2795
2796         memset(&new_link, 0, sizeof(new_link));
2797         hns3_setup_linkstatus(eth_dev, &new_link);
2798
2799         return rte_eth_linkstatus_set(eth_dev, &new_link);
2800 }
2801
2802 static int
2803 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2804 {
2805         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2806         struct hns3_pf *pf = &hns->pf;
2807
2808         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2809                 return -EINVAL;
2810
2811         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2812
2813         return 0;
2814 }
2815
2816 static int
2817 hns3_query_function_status(struct hns3_hw *hw)
2818 {
2819 #define HNS3_QUERY_MAX_CNT              10
2820 #define HNS3_QUERY_SLEEP_MSCOEND        1
2821         struct hns3_func_status_cmd *req;
2822         struct hns3_cmd_desc desc;
2823         int timeout = 0;
2824         int ret;
2825
2826         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2827         req = (struct hns3_func_status_cmd *)desc.data;
2828
2829         do {
2830                 ret = hns3_cmd_send(hw, &desc, 1);
2831                 if (ret) {
2832                         PMD_INIT_LOG(ERR, "query function status failed %d",
2833                                      ret);
2834                         return ret;
2835                 }
2836
2837                 /* Check pf reset is done */
2838                 if (req->pf_state)
2839                         break;
2840
2841                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2842         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2843
2844         return hns3_parse_func_status(hw, req);
2845 }
2846
2847 static int
2848 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2849 {
2850         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2851         struct hns3_pf *pf = &hns->pf;
2852
2853         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2854                 /*
2855                  * The total_tqps_num obtained from firmware is maximum tqp
2856                  * numbers of this port, which should be used for PF and VFs.
2857                  * There is no need for pf to have so many tqp numbers in
2858                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2859                  * coming from config file, is assigned to maximum queue number
2860                  * for the PF of this port by user. So users can modify the
2861                  * maximum queue number of PF according to their own application
2862                  * scenarios, which is more flexible to use. In addition, many
2863                  * memories can be saved due to allocating queue statistics
2864                  * room according to the actual number of queues required. The
2865                  * maximum queue number of PF for network engine with
2866                  * revision_id greater than 0x30 is assigned by config file.
2867                  */
2868                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2869                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2870                                  "must be greater than 0.",
2871                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2872                         return -EINVAL;
2873                 }
2874
2875                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2876                                        hw->total_tqps_num);
2877         } else {
2878                 /*
2879                  * Due to the limitation on the number of PF interrupts
2880                  * available, the maximum queue number assigned to PF on
2881                  * the network engine with revision_id 0x21 is 64.
2882                  */
2883                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2884                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int
2891 hns3_query_pf_resource(struct hns3_hw *hw)
2892 {
2893         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2894         struct hns3_pf *pf = &hns->pf;
2895         struct hns3_pf_res_cmd *req;
2896         struct hns3_cmd_desc desc;
2897         int ret;
2898
2899         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2900         ret = hns3_cmd_send(hw, &desc, 1);
2901         if (ret) {
2902                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2903                 return ret;
2904         }
2905
2906         req = (struct hns3_pf_res_cmd *)desc.data;
2907         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2908                              rte_le_to_cpu_16(req->ext_tqp_num);
2909         ret = hns3_get_pf_max_tqp_num(hw);
2910         if (ret)
2911                 return ret;
2912
2913         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2914         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2915
2916         if (req->tx_buf_size)
2917                 pf->tx_buf_size =
2918                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2919         else
2920                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2921
2922         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2923
2924         if (req->dv_buf_size)
2925                 pf->dv_buf_size =
2926                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2927         else
2928                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2929
2930         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2931
2932         hw->num_msi =
2933                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2934                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2935
2936         return 0;
2937 }
2938
2939 static void
2940 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2941 {
2942         struct hns3_cfg_param_cmd *req;
2943         uint64_t mac_addr_tmp_high;
2944         uint8_t ext_rss_size_max;
2945         uint64_t mac_addr_tmp;
2946         uint32_t i;
2947
2948         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2949
2950         /* get the configuration */
2951         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2952                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2953         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2954                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2955         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2956                                            HNS3_CFG_TQP_DESC_N_M,
2957                                            HNS3_CFG_TQP_DESC_N_S);
2958
2959         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2960                                        HNS3_CFG_PHY_ADDR_M,
2961                                        HNS3_CFG_PHY_ADDR_S);
2962         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2963                                          HNS3_CFG_MEDIA_TP_M,
2964                                          HNS3_CFG_MEDIA_TP_S);
2965         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2966                                          HNS3_CFG_RX_BUF_LEN_M,
2967                                          HNS3_CFG_RX_BUF_LEN_S);
2968         /* get mac address */
2969         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2970         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2971                                            HNS3_CFG_MAC_ADDR_H_M,
2972                                            HNS3_CFG_MAC_ADDR_H_S);
2973
2974         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2975
2976         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2977                                             HNS3_CFG_DEFAULT_SPEED_M,
2978                                             HNS3_CFG_DEFAULT_SPEED_S);
2979         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2980                                            HNS3_CFG_RSS_SIZE_M,
2981                                            HNS3_CFG_RSS_SIZE_S);
2982
2983         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2984                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2985
2986         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2987         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2988
2989         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2990                                             HNS3_CFG_SPEED_ABILITY_M,
2991                                             HNS3_CFG_SPEED_ABILITY_S);
2992         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2993                                         HNS3_CFG_UMV_TBL_SPACE_M,
2994                                         HNS3_CFG_UMV_TBL_SPACE_S);
2995         if (!cfg->umv_space)
2996                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2997
2998         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2999                                                HNS3_CFG_EXT_RSS_SIZE_M,
3000                                                HNS3_CFG_EXT_RSS_SIZE_S);
3001
3002         /*
3003          * Field ext_rss_size_max obtained from firmware will be more flexible
3004          * for future changes and expansions, which is an exponent of 2, instead
3005          * of reading out directly. If this field is not zero, hns3 PF PMD
3006          * driver uses it as rss_size_max under one TC. Device, whose revision
3007          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3008          * maximum number of queues supported under a TC through this field.
3009          */
3010         if (ext_rss_size_max)
3011                 cfg->rss_size_max = 1U << ext_rss_size_max;
3012 }
3013
3014 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3015  * @hw: pointer to struct hns3_hw
3016  * @hcfg: the config structure to be getted
3017  */
3018 static int
3019 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3020 {
3021         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3022         struct hns3_cfg_param_cmd *req;
3023         uint32_t offset;
3024         uint32_t i;
3025         int ret;
3026
3027         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3028                 offset = 0;
3029                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3030                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3031                                           true);
3032                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3033                                i * HNS3_CFG_RD_LEN_BYTES);
3034                 /* Len should be divided by 4 when send to hardware */
3035                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3036                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3037                 req->offset = rte_cpu_to_le_32(offset);
3038         }
3039
3040         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3041         if (ret) {
3042                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3043                 return ret;
3044         }
3045
3046         hns3_parse_cfg(hcfg, desc);
3047
3048         return 0;
3049 }
3050
3051 static int
3052 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3053 {
3054         switch (speed_cmd) {
3055         case HNS3_CFG_SPEED_10M:
3056                 *speed = ETH_SPEED_NUM_10M;
3057                 break;
3058         case HNS3_CFG_SPEED_100M:
3059                 *speed = ETH_SPEED_NUM_100M;
3060                 break;
3061         case HNS3_CFG_SPEED_1G:
3062                 *speed = ETH_SPEED_NUM_1G;
3063                 break;
3064         case HNS3_CFG_SPEED_10G:
3065                 *speed = ETH_SPEED_NUM_10G;
3066                 break;
3067         case HNS3_CFG_SPEED_25G:
3068                 *speed = ETH_SPEED_NUM_25G;
3069                 break;
3070         case HNS3_CFG_SPEED_40G:
3071                 *speed = ETH_SPEED_NUM_40G;
3072                 break;
3073         case HNS3_CFG_SPEED_50G:
3074                 *speed = ETH_SPEED_NUM_50G;
3075                 break;
3076         case HNS3_CFG_SPEED_100G:
3077                 *speed = ETH_SPEED_NUM_100G;
3078                 break;
3079         case HNS3_CFG_SPEED_200G:
3080                 *speed = ETH_SPEED_NUM_200G;
3081                 break;
3082         default:
3083                 return -EINVAL;
3084         }
3085
3086         return 0;
3087 }
3088
3089 static void
3090 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3091 {
3092         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3093         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3094         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3095         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3096         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3097 }
3098
3099 static void
3100 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3101 {
3102         struct hns3_dev_specs_0_cmd *req0;
3103
3104         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3105
3106         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3107         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3108         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3109         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3110         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3111 }
3112
3113 static int
3114 hns3_check_dev_specifications(struct hns3_hw *hw)
3115 {
3116         if (hw->rss_ind_tbl_size == 0 ||
3117             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3118                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3119                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3120                               HNS3_RSS_IND_TBL_SIZE_MAX);
3121                 return -EINVAL;
3122         }
3123
3124         return 0;
3125 }
3126
3127 static int
3128 hns3_query_dev_specifications(struct hns3_hw *hw)
3129 {
3130         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3131         int ret;
3132         int i;
3133
3134         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3135                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3136                                           true);
3137                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3138         }
3139         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3140
3141         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3142         if (ret)
3143                 return ret;
3144
3145         hns3_parse_dev_specifications(hw, desc);
3146
3147         return hns3_check_dev_specifications(hw);
3148 }
3149
3150 static int
3151 hns3_get_capability(struct hns3_hw *hw)
3152 {
3153         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3154         struct rte_pci_device *pci_dev;
3155         struct hns3_pf *pf = &hns->pf;
3156         struct rte_eth_dev *eth_dev;
3157         uint16_t device_id;
3158         uint8_t revision;
3159         int ret;
3160
3161         eth_dev = &rte_eth_devices[hw->data->port_id];
3162         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3163         device_id = pci_dev->id.device_id;
3164
3165         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3166             device_id == HNS3_DEV_ID_50GE_RDMA ||
3167             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3168             device_id == HNS3_DEV_ID_200G_RDMA)
3169                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3170
3171         /* Get PCI revision id */
3172         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3173                                   HNS3_PCI_REVISION_ID);
3174         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3175                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3176                              ret);
3177                 return -EIO;
3178         }
3179         hw->revision = revision;
3180
3181         if (revision < PCI_REVISION_ID_HIP09_A) {
3182                 hns3_set_default_dev_specifications(hw);
3183                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3184                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3185                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3186                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3187                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3188                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3189                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3190                 hw->rss_info.ipv6_sctp_offload_supported = false;
3191                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3192                 return 0;
3193         }
3194
3195         ret = hns3_query_dev_specifications(hw);
3196         if (ret) {
3197                 PMD_INIT_LOG(ERR,
3198                              "failed to query dev specifications, ret = %d",
3199                              ret);
3200                 return ret;
3201         }
3202
3203         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3204         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3205         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3206         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3207         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3208         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3209         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3210         hw->rss_info.ipv6_sctp_offload_supported = true;
3211         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3212
3213         return 0;
3214 }
3215
3216 static int
3217 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3218 {
3219         int ret;
3220
3221         switch (media_type) {
3222         case HNS3_MEDIA_TYPE_COPPER:
3223                 if (!hns3_dev_copper_supported(hw)) {
3224                         PMD_INIT_LOG(ERR,
3225                                      "Media type is copper, not supported.");
3226                         ret = -EOPNOTSUPP;
3227                 } else {
3228                         ret = 0;
3229                 }
3230                 break;
3231         case HNS3_MEDIA_TYPE_FIBER:
3232                 ret = 0;
3233                 break;
3234         case HNS3_MEDIA_TYPE_BACKPLANE:
3235                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3236                 ret = -EOPNOTSUPP;
3237                 break;
3238         default:
3239                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3240                 ret = -EINVAL;
3241                 break;
3242         }
3243
3244         return ret;
3245 }
3246
3247 static int
3248 hns3_get_board_configuration(struct hns3_hw *hw)
3249 {
3250         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3251         struct hns3_pf *pf = &hns->pf;
3252         struct hns3_cfg cfg;
3253         int ret;
3254
3255         ret = hns3_get_board_cfg(hw, &cfg);
3256         if (ret) {
3257                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3258                 return ret;
3259         }
3260
3261         ret = hns3_check_media_type(hw, cfg.media_type);
3262         if (ret)
3263                 return ret;
3264
3265         hw->mac.media_type = cfg.media_type;
3266         hw->rss_size_max = cfg.rss_size_max;
3267         hw->rss_dis_flag = false;
3268         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3269         hw->mac.phy_addr = cfg.phy_addr;
3270         hw->mac.default_addr_setted = false;
3271         hw->num_tx_desc = cfg.tqp_desc_num;
3272         hw->num_rx_desc = cfg.tqp_desc_num;
3273         hw->dcb_info.num_pg = 1;
3274         hw->dcb_info.hw_pfc_map = 0;
3275
3276         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3277         if (ret) {
3278                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3279                              cfg.default_speed, ret);
3280                 return ret;
3281         }
3282
3283         pf->tc_max = cfg.tc_num;
3284         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3285                 PMD_INIT_LOG(WARNING,
3286                              "Get TC num(%u) from flash, set TC num to 1",
3287                              pf->tc_max);
3288                 pf->tc_max = 1;
3289         }
3290
3291         /* Dev does not support DCB */
3292         if (!hns3_dev_dcb_supported(hw)) {
3293                 pf->tc_max = 1;
3294                 pf->pfc_max = 0;
3295         } else
3296                 pf->pfc_max = pf->tc_max;
3297
3298         hw->dcb_info.num_tc = 1;
3299         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3300                                      hw->tqps_num / hw->dcb_info.num_tc);
3301         hns3_set_bit(hw->hw_tc_map, 0, 1);
3302         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3303
3304         pf->wanted_umv_size = cfg.umv_space;
3305
3306         return ret;
3307 }
3308
3309 static int
3310 hns3_get_configuration(struct hns3_hw *hw)
3311 {
3312         int ret;
3313
3314         ret = hns3_query_function_status(hw);
3315         if (ret) {
3316                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3317                 return ret;
3318         }
3319
3320         /* Get device capability */
3321         ret = hns3_get_capability(hw);
3322         if (ret) {
3323                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3324                 return ret;
3325         }
3326
3327         /* Get pf resource */
3328         ret = hns3_query_pf_resource(hw);
3329         if (ret) {
3330                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3331                 return ret;
3332         }
3333
3334         ret = hns3_get_board_configuration(hw);
3335         if (ret) {
3336                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3337                 return ret;
3338         }
3339
3340         ret = hns3_query_dev_fec_info(hw);
3341         if (ret)
3342                 PMD_INIT_LOG(ERR,
3343                              "failed to query FEC information, ret = %d", ret);
3344
3345         return ret;
3346 }
3347
3348 static int
3349 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3350                       uint16_t tqp_vid, bool is_pf)
3351 {
3352         struct hns3_tqp_map_cmd *req;
3353         struct hns3_cmd_desc desc;
3354         int ret;
3355
3356         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3357
3358         req = (struct hns3_tqp_map_cmd *)desc.data;
3359         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3360         req->tqp_vf = func_id;
3361         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3362         if (!is_pf)
3363                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3364         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3365
3366         ret = hns3_cmd_send(hw, &desc, 1);
3367         if (ret)
3368                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3369
3370         return ret;
3371 }
3372
3373 static int
3374 hns3_map_tqp(struct hns3_hw *hw)
3375 {
3376         int ret;
3377         int i;
3378
3379         /*
3380          * In current version, VF is not supported when PF is driven by DPDK
3381          * driver, so we assign total tqps_num tqps allocated to this port
3382          * to PF.
3383          */
3384         for (i = 0; i < hw->total_tqps_num; i++) {
3385                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3386                 if (ret)
3387                         return ret;
3388         }
3389
3390         return 0;
3391 }
3392
3393 static int
3394 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3395 {
3396         struct hns3_config_mac_speed_dup_cmd *req;
3397         struct hns3_cmd_desc desc;
3398         int ret;
3399
3400         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3401
3402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3403
3404         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3405
3406         switch (speed) {
3407         case ETH_SPEED_NUM_10M:
3408                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3409                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3410                 break;
3411         case ETH_SPEED_NUM_100M:
3412                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3413                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3414                 break;
3415         case ETH_SPEED_NUM_1G:
3416                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3417                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3418                 break;
3419         case ETH_SPEED_NUM_10G:
3420                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3421                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3422                 break;
3423         case ETH_SPEED_NUM_25G:
3424                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3425                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3426                 break;
3427         case ETH_SPEED_NUM_40G:
3428                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3429                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3430                 break;
3431         case ETH_SPEED_NUM_50G:
3432                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3433                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3434                 break;
3435         case ETH_SPEED_NUM_100G:
3436                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3437                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3438                 break;
3439         case ETH_SPEED_NUM_200G:
3440                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3441                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3442                 break;
3443         default:
3444                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3445                 return -EINVAL;
3446         }
3447
3448         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3449
3450         ret = hns3_cmd_send(hw, &desc, 1);
3451         if (ret)
3452                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3453
3454         return ret;
3455 }
3456
3457 static int
3458 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3459 {
3460         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3461         struct hns3_pf *pf = &hns->pf;
3462         struct hns3_priv_buf *priv;
3463         uint32_t i, total_size;
3464
3465         total_size = pf->pkt_buf_size;
3466
3467         /* alloc tx buffer for all enabled tc */
3468         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3469                 priv = &buf_alloc->priv_buf[i];
3470
3471                 if (hw->hw_tc_map & BIT(i)) {
3472                         if (total_size < pf->tx_buf_size)
3473                                 return -ENOMEM;
3474
3475                         priv->tx_buf_size = pf->tx_buf_size;
3476                 } else
3477                         priv->tx_buf_size = 0;
3478
3479                 total_size -= priv->tx_buf_size;
3480         }
3481
3482         return 0;
3483 }
3484
3485 static int
3486 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3487 {
3488 /* TX buffer size is unit by 128 byte */
3489 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3490 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3491         struct hns3_tx_buff_alloc_cmd *req;
3492         struct hns3_cmd_desc desc;
3493         uint32_t buf_size;
3494         uint32_t i;
3495         int ret;
3496
3497         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3498
3499         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3500         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3501                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3502
3503                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3504                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3505                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3506         }
3507
3508         ret = hns3_cmd_send(hw, &desc, 1);
3509         if (ret)
3510                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3511
3512         return ret;
3513 }
3514
3515 static int
3516 hns3_get_tc_num(struct hns3_hw *hw)
3517 {
3518         int cnt = 0;
3519         uint8_t i;
3520
3521         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3522                 if (hw->hw_tc_map & BIT(i))
3523                         cnt++;
3524         return cnt;
3525 }
3526
3527 static uint32_t
3528 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3529 {
3530         struct hns3_priv_buf *priv;
3531         uint32_t rx_priv = 0;
3532         int i;
3533
3534         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3535                 priv = &buf_alloc->priv_buf[i];
3536                 if (priv->enable)
3537                         rx_priv += priv->buf_size;
3538         }
3539         return rx_priv;
3540 }
3541
3542 static uint32_t
3543 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3544 {
3545         uint32_t total_tx_size = 0;
3546         uint32_t i;
3547
3548         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3549                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3550
3551         return total_tx_size;
3552 }
3553
3554 /* Get the number of pfc enabled TCs, which have private buffer */
3555 static int
3556 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3557 {
3558         struct hns3_priv_buf *priv;
3559         int cnt = 0;
3560         uint8_t i;
3561
3562         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3563                 priv = &buf_alloc->priv_buf[i];
3564                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3565                         cnt++;
3566         }
3567
3568         return cnt;
3569 }
3570
3571 /* Get the number of pfc disabled TCs, which have private buffer */
3572 static int
3573 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3574                          struct hns3_pkt_buf_alloc *buf_alloc)
3575 {
3576         struct hns3_priv_buf *priv;
3577         int cnt = 0;
3578         uint8_t i;
3579
3580         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3581                 priv = &buf_alloc->priv_buf[i];
3582                 if (hw->hw_tc_map & BIT(i) &&
3583                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3584                         cnt++;
3585         }
3586
3587         return cnt;
3588 }
3589
3590 static bool
3591 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3592                   uint32_t rx_all)
3593 {
3594         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3595         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3596         struct hns3_pf *pf = &hns->pf;
3597         uint32_t shared_buf, aligned_mps;
3598         uint32_t rx_priv;
3599         uint8_t tc_num;
3600         uint8_t i;
3601
3602         tc_num = hns3_get_tc_num(hw);
3603         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3604
3605         if (hns3_dev_dcb_supported(hw))
3606                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3607                                         pf->dv_buf_size;
3608         else
3609                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3610                                         + pf->dv_buf_size;
3611
3612         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3613         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3614                              HNS3_BUF_SIZE_UNIT);
3615
3616         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3617         if (rx_all < rx_priv + shared_std)
3618                 return false;
3619
3620         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3621         buf_alloc->s_buf.buf_size = shared_buf;
3622         if (hns3_dev_dcb_supported(hw)) {
3623                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3624                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3625                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3626                                   HNS3_BUF_SIZE_UNIT);
3627         } else {
3628                 buf_alloc->s_buf.self.high =
3629                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3630                 buf_alloc->s_buf.self.low = aligned_mps;
3631         }
3632
3633         if (hns3_dev_dcb_supported(hw)) {
3634                 hi_thrd = shared_buf - pf->dv_buf_size;
3635
3636                 if (tc_num <= NEED_RESERVE_TC_NUM)
3637                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3638                                   BUF_MAX_PERCENT;
3639
3640                 if (tc_num)
3641                         hi_thrd = hi_thrd / tc_num;
3642
3643                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3644                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3645                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3646         } else {
3647                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3648                 lo_thrd = aligned_mps;
3649         }
3650
3651         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3652                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3653                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3654         }
3655
3656         return true;
3657 }
3658
3659 static bool
3660 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3661                      struct hns3_pkt_buf_alloc *buf_alloc)
3662 {
3663         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3664         struct hns3_pf *pf = &hns->pf;
3665         struct hns3_priv_buf *priv;
3666         uint32_t aligned_mps;
3667         uint32_t rx_all;
3668         uint8_t i;
3669
3670         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3671         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3672
3673         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3674                 priv = &buf_alloc->priv_buf[i];
3675
3676                 priv->enable = 0;
3677                 priv->wl.low = 0;
3678                 priv->wl.high = 0;
3679                 priv->buf_size = 0;
3680
3681                 if (!(hw->hw_tc_map & BIT(i)))
3682                         continue;
3683
3684                 priv->enable = 1;
3685                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3686                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3687                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3688                                                 HNS3_BUF_SIZE_UNIT);
3689                 } else {
3690                         priv->wl.low = 0;
3691                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3692                                         aligned_mps;
3693                 }
3694
3695                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3696         }
3697
3698         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3699 }
3700
3701 static bool
3702 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3703                              struct hns3_pkt_buf_alloc *buf_alloc)
3704 {
3705         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3706         struct hns3_pf *pf = &hns->pf;
3707         struct hns3_priv_buf *priv;
3708         int no_pfc_priv_num;
3709         uint32_t rx_all;
3710         uint8_t mask;
3711         int i;
3712
3713         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3714         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3715
3716         /* let the last to be cleared first */
3717         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3718                 priv = &buf_alloc->priv_buf[i];
3719                 mask = BIT((uint8_t)i);
3720
3721                 if (hw->hw_tc_map & mask &&
3722                     !(hw->dcb_info.hw_pfc_map & mask)) {
3723                         /* Clear the no pfc TC private buffer */
3724                         priv->wl.low = 0;
3725                         priv->wl.high = 0;
3726                         priv->buf_size = 0;
3727                         priv->enable = 0;
3728                         no_pfc_priv_num--;
3729                 }
3730
3731                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3732                     no_pfc_priv_num == 0)
3733                         break;
3734         }
3735
3736         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3737 }
3738
3739 static bool
3740 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3741                            struct hns3_pkt_buf_alloc *buf_alloc)
3742 {
3743         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3744         struct hns3_pf *pf = &hns->pf;
3745         struct hns3_priv_buf *priv;
3746         uint32_t rx_all;
3747         int pfc_priv_num;
3748         uint8_t mask;
3749         int i;
3750
3751         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3752         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3753
3754         /* let the last to be cleared first */
3755         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3756                 priv = &buf_alloc->priv_buf[i];
3757                 mask = BIT((uint8_t)i);
3758                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3759                         /* Reduce the number of pfc TC with private buffer */
3760                         priv->wl.low = 0;
3761                         priv->enable = 0;
3762                         priv->wl.high = 0;
3763                         priv->buf_size = 0;
3764                         pfc_priv_num--;
3765                 }
3766                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3767                     pfc_priv_num == 0)
3768                         break;
3769         }
3770
3771         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3772 }
3773
3774 static bool
3775 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3776                           struct hns3_pkt_buf_alloc *buf_alloc)
3777 {
3778 #define COMPENSATE_BUFFER       0x3C00
3779 #define COMPENSATE_HALF_MPS_NUM 5
3780 #define PRIV_WL_GAP             0x1800
3781         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3782         struct hns3_pf *pf = &hns->pf;
3783         uint32_t tc_num = hns3_get_tc_num(hw);
3784         uint32_t half_mps = pf->mps >> 1;
3785         struct hns3_priv_buf *priv;
3786         uint32_t min_rx_priv;
3787         uint32_t rx_priv;
3788         uint8_t i;
3789
3790         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3791         if (tc_num)
3792                 rx_priv = rx_priv / tc_num;
3793
3794         if (tc_num <= NEED_RESERVE_TC_NUM)
3795                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3796
3797         /*
3798          * Minimum value of private buffer in rx direction (min_rx_priv) is
3799          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3800          * buffer if rx_priv is greater than min_rx_priv.
3801          */
3802         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3803                         COMPENSATE_HALF_MPS_NUM * half_mps;
3804         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3805         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3806
3807         if (rx_priv < min_rx_priv)
3808                 return false;
3809
3810         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3811                 priv = &buf_alloc->priv_buf[i];
3812                 priv->enable = 0;
3813                 priv->wl.low = 0;
3814                 priv->wl.high = 0;
3815                 priv->buf_size = 0;
3816
3817                 if (!(hw->hw_tc_map & BIT(i)))
3818                         continue;
3819
3820                 priv->enable = 1;
3821                 priv->buf_size = rx_priv;
3822                 priv->wl.high = rx_priv - pf->dv_buf_size;
3823                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3824         }
3825
3826         buf_alloc->s_buf.buf_size = 0;
3827
3828         return true;
3829 }
3830
3831 /*
3832  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3833  * @hw: pointer to struct hns3_hw
3834  * @buf_alloc: pointer to buffer calculation data
3835  * @return: 0: calculate sucessful, negative: fail
3836  */
3837 static int
3838 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3839 {
3840         /* When DCB is not supported, rx private buffer is not allocated. */
3841         if (!hns3_dev_dcb_supported(hw)) {
3842                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3843                 struct hns3_pf *pf = &hns->pf;
3844                 uint32_t rx_all = pf->pkt_buf_size;
3845
3846                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3847                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3848                         return -ENOMEM;
3849
3850                 return 0;
3851         }
3852
3853         /*
3854          * Try to allocate privated packet buffer for all TCs without share
3855          * buffer.
3856          */
3857         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3858                 return 0;
3859
3860         /*
3861          * Try to allocate privated packet buffer for all TCs with share
3862          * buffer.
3863          */
3864         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3865                 return 0;
3866
3867         /*
3868          * For different application scenes, the enabled port number, TC number
3869          * and no_drop TC number are different. In order to obtain the better
3870          * performance, software could allocate the buffer size and configure
3871          * the waterline by tring to decrease the private buffer size according
3872          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3873          * enabled tc.
3874          */
3875         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3876                 return 0;
3877
3878         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3879                 return 0;
3880
3881         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3882                 return 0;
3883
3884         return -ENOMEM;
3885 }
3886
3887 static int
3888 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3889 {
3890         struct hns3_rx_priv_buff_cmd *req;
3891         struct hns3_cmd_desc desc;
3892         uint32_t buf_size;
3893         int ret;
3894         int i;
3895
3896         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3897         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3898
3899         /* Alloc private buffer TCs */
3900         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3901                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3902
3903                 req->buf_num[i] =
3904                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3905                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3906         }
3907
3908         buf_size = buf_alloc->s_buf.buf_size;
3909         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3910                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3911
3912         ret = hns3_cmd_send(hw, &desc, 1);
3913         if (ret)
3914                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3915
3916         return ret;
3917 }
3918
3919 static int
3920 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3921 {
3922 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3923         struct hns3_rx_priv_wl_buf *req;
3924         struct hns3_priv_buf *priv;
3925         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3926         int i, j;
3927         int ret;
3928
3929         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3930                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3931                                           false);
3932                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3933
3934                 /* The first descriptor set the NEXT bit to 1 */
3935                 if (i == 0)
3936                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3937                 else
3938                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3939
3940                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3941                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3942
3943                         priv = &buf_alloc->priv_buf[idx];
3944                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3945                                                         HNS3_BUF_UNIT_S);
3946                         req->tc_wl[j].high |=
3947                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3948                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3949                                                         HNS3_BUF_UNIT_S);
3950                         req->tc_wl[j].low |=
3951                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3952                 }
3953         }
3954
3955         /* Send 2 descriptor at one time */
3956         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3957         if (ret)
3958                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3959                              ret);
3960         return ret;
3961 }
3962
3963 static int
3964 hns3_common_thrd_config(struct hns3_hw *hw,
3965                         struct hns3_pkt_buf_alloc *buf_alloc)
3966 {
3967 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3968         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3969         struct hns3_rx_com_thrd *req;
3970         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3971         struct hns3_tc_thrd *tc;
3972         int tc_idx;
3973         int i, j;
3974         int ret;
3975
3976         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3977                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3978                                           false);
3979                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3980
3981                 /* The first descriptor set the NEXT bit to 1 */
3982                 if (i == 0)
3983                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3984                 else
3985                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3986
3987                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3988                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3989                         tc = &s_buf->tc_thrd[tc_idx];
3990
3991                         req->com_thrd[j].high =
3992                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3993                         req->com_thrd[j].high |=
3994                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3995                         req->com_thrd[j].low =
3996                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3997                         req->com_thrd[j].low |=
3998                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3999                 }
4000         }
4001
4002         /* Send 2 descriptors at one time */
4003         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4004         if (ret)
4005                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4006
4007         return ret;
4008 }
4009
4010 static int
4011 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4012 {
4013         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4014         struct hns3_rx_com_wl *req;
4015         struct hns3_cmd_desc desc;
4016         int ret;
4017
4018         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4019
4020         req = (struct hns3_rx_com_wl *)desc.data;
4021         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4022         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4023
4024         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4025         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4026
4027         ret = hns3_cmd_send(hw, &desc, 1);
4028         if (ret)
4029                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4030
4031         return ret;
4032 }
4033
4034 int
4035 hns3_buffer_alloc(struct hns3_hw *hw)
4036 {
4037         struct hns3_pkt_buf_alloc pkt_buf;
4038         int ret;
4039
4040         memset(&pkt_buf, 0, sizeof(pkt_buf));
4041         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4042         if (ret) {
4043                 PMD_INIT_LOG(ERR,
4044                              "could not calc tx buffer size for all TCs %d",
4045                              ret);
4046                 return ret;
4047         }
4048
4049         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4050         if (ret) {
4051                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4052                 return ret;
4053         }
4054
4055         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4056         if (ret) {
4057                 PMD_INIT_LOG(ERR,
4058                              "could not calc rx priv buffer size for all TCs %d",
4059                              ret);
4060                 return ret;
4061         }
4062
4063         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4064         if (ret) {
4065                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4066                 return ret;
4067         }
4068
4069         if (hns3_dev_dcb_supported(hw)) {
4070                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4071                 if (ret) {
4072                         PMD_INIT_LOG(ERR,
4073                                      "could not configure rx private waterline %d",
4074                                      ret);
4075                         return ret;
4076                 }
4077
4078                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4079                 if (ret) {
4080                         PMD_INIT_LOG(ERR,
4081                                      "could not configure common threshold %d",
4082                                      ret);
4083                         return ret;
4084                 }
4085         }
4086
4087         ret = hns3_common_wl_config(hw, &pkt_buf);
4088         if (ret)
4089                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4090                              ret);
4091
4092         return ret;
4093 }
4094
4095 static int
4096 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4097 {
4098         struct hns3_firmware_compat_cmd *req;
4099         struct hns3_cmd_desc desc;
4100         uint32_t compat = 0;
4101
4102         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4103         req = (struct hns3_firmware_compat_cmd *)desc.data;
4104
4105         if (is_init) {
4106                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4107                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4108                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4109                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4110         }
4111
4112         req->compat = rte_cpu_to_le_32(compat);
4113
4114         return hns3_cmd_send(hw, &desc, 1);
4115 }
4116
4117 static int
4118 hns3_mac_init(struct hns3_hw *hw)
4119 {
4120         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4121         struct hns3_mac *mac = &hw->mac;
4122         struct hns3_pf *pf = &hns->pf;
4123         int ret;
4124
4125         pf->support_sfp_query = true;
4126         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4127         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4128         if (ret) {
4129                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4130                 return ret;
4131         }
4132
4133         mac->link_status = ETH_LINK_DOWN;
4134
4135         return hns3_config_mtu(hw, pf->mps);
4136 }
4137
4138 static int
4139 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4140 {
4141 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4142 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4143 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4144 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4145         int return_status;
4146
4147         if (cmdq_resp) {
4148                 PMD_INIT_LOG(ERR,
4149                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4150                              cmdq_resp);
4151                 return -EIO;
4152         }
4153
4154         switch (resp_code) {
4155         case HNS3_ETHERTYPE_SUCCESS_ADD:
4156         case HNS3_ETHERTYPE_ALREADY_ADD:
4157                 return_status = 0;
4158                 break;
4159         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4160                 PMD_INIT_LOG(ERR,
4161                              "add mac ethertype failed for manager table overflow.");
4162                 return_status = -EIO;
4163                 break;
4164         case HNS3_ETHERTYPE_KEY_CONFLICT:
4165                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4166                 return_status = -EIO;
4167                 break;
4168         default:
4169                 PMD_INIT_LOG(ERR,
4170                              "add mac ethertype failed for undefined, code=%u.",
4171                              resp_code);
4172                 return_status = -EIO;
4173                 break;
4174         }
4175
4176         return return_status;
4177 }
4178
4179 static int
4180 hns3_add_mgr_tbl(struct hns3_hw *hw,
4181                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4182 {
4183         struct hns3_cmd_desc desc;
4184         uint8_t resp_code;
4185         uint16_t retval;
4186         int ret;
4187
4188         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4189         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4190
4191         ret = hns3_cmd_send(hw, &desc, 1);
4192         if (ret) {
4193                 PMD_INIT_LOG(ERR,
4194                              "add mac ethertype failed for cmd_send, ret =%d.",
4195                              ret);
4196                 return ret;
4197         }
4198
4199         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4200         retval = rte_le_to_cpu_16(desc.retval);
4201
4202         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4203 }
4204
4205 static void
4206 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4207                      int *table_item_num)
4208 {
4209         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4210
4211         /*
4212          * In current version, we add one item in management table as below:
4213          * 0x0180C200000E -- LLDP MC address
4214          */
4215         tbl = mgr_table;
4216         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4217         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4218         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4219         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4220         tbl->i_port_bitmap = 0x1;
4221         *table_item_num = 1;
4222 }
4223
4224 static int
4225 hns3_init_mgr_tbl(struct hns3_hw *hw)
4226 {
4227 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4228         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4229         int table_item_num;
4230         int ret;
4231         int i;
4232
4233         memset(mgr_table, 0, sizeof(mgr_table));
4234         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4235         for (i = 0; i < table_item_num; i++) {
4236                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4237                 if (ret) {
4238                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4239                                      ret);
4240                         return ret;
4241                 }
4242         }
4243
4244         return 0;
4245 }
4246
4247 static void
4248 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4249                         bool en_mc, bool en_bc, int vport_id)
4250 {
4251         if (!param)
4252                 return;
4253
4254         memset(param, 0, sizeof(struct hns3_promisc_param));
4255         if (en_uc)
4256                 param->enable = HNS3_PROMISC_EN_UC;
4257         if (en_mc)
4258                 param->enable |= HNS3_PROMISC_EN_MC;
4259         if (en_bc)
4260                 param->enable |= HNS3_PROMISC_EN_BC;
4261         param->vf_id = vport_id;
4262 }
4263
4264 static int
4265 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4266 {
4267         struct hns3_promisc_cfg_cmd *req;
4268         struct hns3_cmd_desc desc;
4269         int ret;
4270
4271         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4272
4273         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4274         req->vf_id = param->vf_id;
4275         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4276             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4277
4278         ret = hns3_cmd_send(hw, &desc, 1);
4279         if (ret)
4280                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4281
4282         return ret;
4283 }
4284
4285 static int
4286 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4287 {
4288         struct hns3_promisc_param param;
4289         bool en_bc_pmc = true;
4290         uint8_t vf_id;
4291
4292         /*
4293          * In current version VF is not supported when PF is driven by DPDK
4294          * driver, just need to configure parameters for PF vport.
4295          */
4296         vf_id = HNS3_PF_FUNC_ID;
4297
4298         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4299         return hns3_cmd_set_promisc_mode(hw, &param);
4300 }
4301
4302 static int
4303 hns3_promisc_init(struct hns3_hw *hw)
4304 {
4305         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4306         struct hns3_pf *pf = &hns->pf;
4307         struct hns3_promisc_param param;
4308         uint16_t func_id;
4309         int ret;
4310
4311         ret = hns3_set_promisc_mode(hw, false, false);
4312         if (ret) {
4313                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4314                 return ret;
4315         }
4316
4317         /*
4318          * In current version VFs are not supported when PF is driven by DPDK
4319          * driver. After PF has been taken over by DPDK, the original VF will
4320          * be invalid. So, there is a possibility of entry residues. It should
4321          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4322          * during init.
4323          */
4324         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4325                 hns3_promisc_param_init(&param, false, false, false, func_id);
4326                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4327                 if (ret) {
4328                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4329                                         " ret = %d", func_id, ret);
4330                         return ret;
4331                 }
4332         }
4333
4334         return 0;
4335 }
4336
4337 static void
4338 hns3_promisc_uninit(struct hns3_hw *hw)
4339 {
4340         struct hns3_promisc_param param;
4341         uint16_t func_id;
4342         int ret;
4343
4344         func_id = HNS3_PF_FUNC_ID;
4345
4346         /*
4347          * In current version VFs are not supported when PF is driven by
4348          * DPDK driver, and VFs' promisc mode status has been cleared during
4349          * init and their status will not change. So just clear PF's promisc
4350          * mode status during uninit.
4351          */
4352         hns3_promisc_param_init(&param, false, false, false, func_id);
4353         ret = hns3_cmd_set_promisc_mode(hw, &param);
4354         if (ret)
4355                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4356                                 " uninit, ret = %d", ret);
4357 }
4358
4359 static int
4360 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4361 {
4362         bool allmulti = dev->data->all_multicast ? true : false;
4363         struct hns3_adapter *hns = dev->data->dev_private;
4364         struct hns3_hw *hw = &hns->hw;
4365         uint64_t offloads;
4366         int err;
4367         int ret;
4368
4369         rte_spinlock_lock(&hw->lock);
4370         ret = hns3_set_promisc_mode(hw, true, true);
4371         if (ret) {
4372                 rte_spinlock_unlock(&hw->lock);
4373                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4374                          ret);
4375                 return ret;
4376         }
4377
4378         /*
4379          * When promiscuous mode was enabled, disable the vlan filter to let
4380          * all packets coming in in the receiving direction.
4381          */
4382         offloads = dev->data->dev_conf.rxmode.offloads;
4383         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4384                 ret = hns3_enable_vlan_filter(hns, false);
4385                 if (ret) {
4386                         hns3_err(hw, "failed to enable promiscuous mode due to "
4387                                      "failure to disable vlan filter, ret = %d",
4388                                  ret);
4389                         err = hns3_set_promisc_mode(hw, false, allmulti);
4390                         if (err)
4391                                 hns3_err(hw, "failed to restore promiscuous "
4392                                          "status after disable vlan filter "
4393                                          "failed during enabling promiscuous "
4394                                          "mode, ret = %d", ret);
4395                 }
4396         }
4397
4398         rte_spinlock_unlock(&hw->lock);
4399
4400         return ret;
4401 }
4402
4403 static int
4404 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4405 {
4406         bool allmulti = dev->data->all_multicast ? true : false;
4407         struct hns3_adapter *hns = dev->data->dev_private;
4408         struct hns3_hw *hw = &hns->hw;
4409         uint64_t offloads;
4410         int err;
4411         int ret;
4412
4413         /* If now in all_multicast mode, must remain in all_multicast mode. */
4414         rte_spinlock_lock(&hw->lock);
4415         ret = hns3_set_promisc_mode(hw, false, allmulti);
4416         if (ret) {
4417                 rte_spinlock_unlock(&hw->lock);
4418                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4419                          ret);
4420                 return ret;
4421         }
4422         /* when promiscuous mode was disabled, restore the vlan filter status */
4423         offloads = dev->data->dev_conf.rxmode.offloads;
4424         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4425                 ret = hns3_enable_vlan_filter(hns, true);
4426                 if (ret) {
4427                         hns3_err(hw, "failed to disable promiscuous mode due to"
4428                                  " failure to restore vlan filter, ret = %d",
4429                                  ret);
4430                         err = hns3_set_promisc_mode(hw, true, true);
4431                         if (err)
4432                                 hns3_err(hw, "failed to restore promiscuous "
4433                                          "status after enabling vlan filter "
4434                                          "failed during disabling promiscuous "
4435                                          "mode, ret = %d", ret);
4436                 }
4437         }
4438         rte_spinlock_unlock(&hw->lock);
4439
4440         return ret;
4441 }
4442
4443 static int
4444 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4445 {
4446         struct hns3_adapter *hns = dev->data->dev_private;
4447         struct hns3_hw *hw = &hns->hw;
4448         int ret;
4449
4450         if (dev->data->promiscuous)
4451                 return 0;
4452
4453         rte_spinlock_lock(&hw->lock);
4454         ret = hns3_set_promisc_mode(hw, false, true);
4455         rte_spinlock_unlock(&hw->lock);
4456         if (ret)
4457                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4458                          ret);
4459
4460         return ret;
4461 }
4462
4463 static int
4464 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4465 {
4466         struct hns3_adapter *hns = dev->data->dev_private;
4467         struct hns3_hw *hw = &hns->hw;
4468         int ret;
4469
4470         /* If now in promiscuous mode, must remain in all_multicast mode. */
4471         if (dev->data->promiscuous)
4472                 return 0;
4473
4474         rte_spinlock_lock(&hw->lock);
4475         ret = hns3_set_promisc_mode(hw, false, false);
4476         rte_spinlock_unlock(&hw->lock);
4477         if (ret)
4478                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4479                          ret);
4480
4481         return ret;
4482 }
4483
4484 static int
4485 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4486 {
4487         struct hns3_hw *hw = &hns->hw;
4488         bool allmulti = hw->data->all_multicast ? true : false;
4489         int ret;
4490
4491         if (hw->data->promiscuous) {
4492                 ret = hns3_set_promisc_mode(hw, true, true);
4493                 if (ret)
4494                         hns3_err(hw, "failed to restore promiscuous mode, "
4495                                  "ret = %d", ret);
4496                 return ret;
4497         }
4498
4499         ret = hns3_set_promisc_mode(hw, false, allmulti);
4500         if (ret)
4501                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4502                          ret);
4503         return ret;
4504 }
4505
4506 static int
4507 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4508 {
4509         struct hns3_sfp_speed_cmd *resp;
4510         struct hns3_cmd_desc desc;
4511         int ret;
4512
4513         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4514         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4515         ret = hns3_cmd_send(hw, &desc, 1);
4516         if (ret == -EOPNOTSUPP) {
4517                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4518                 return ret;
4519         } else if (ret) {
4520                 hns3_err(hw, "get sfp speed failed %d", ret);
4521                 return ret;
4522         }
4523
4524         *speed = resp->sfp_speed;
4525
4526         return 0;
4527 }
4528
4529 static uint8_t
4530 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4531 {
4532         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4533                 duplex = ETH_LINK_FULL_DUPLEX;
4534
4535         return duplex;
4536 }
4537
4538 static int
4539 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4540 {
4541         struct hns3_mac *mac = &hw->mac;
4542         int ret;
4543
4544         duplex = hns3_check_speed_dup(duplex, speed);
4545         if (mac->link_speed == speed && mac->link_duplex == duplex)
4546                 return 0;
4547
4548         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4549         if (ret)
4550                 return ret;
4551
4552         ret = hns3_port_shaper_update(hw, speed);
4553         if (ret)
4554                 return ret;
4555
4556         mac->link_speed = speed;
4557         mac->link_duplex = duplex;
4558
4559         return 0;
4560 }
4561
4562 static int
4563 hns3_update_fiber_link_info(struct hns3_hw *hw)
4564 {
4565         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4566         uint32_t speed;
4567         int ret;
4568
4569         /* If IMP do not support get SFP/qSFP speed, return directly */
4570         if (!pf->support_sfp_query)
4571                 return 0;
4572
4573         ret = hns3_get_sfp_speed(hw, &speed);
4574         if (ret == -EOPNOTSUPP) {
4575                 pf->support_sfp_query = false;
4576                 return ret;
4577         } else if (ret)
4578                 return ret;
4579
4580         if (speed == ETH_SPEED_NUM_NONE)
4581                 return 0; /* do nothing if no SFP */
4582
4583         /* Config full duplex for SFP */
4584         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4585 }
4586
4587 static void
4588 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4589 {
4590         struct hns3_phy_params_bd0_cmd *req;
4591
4592         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4593         mac->link_speed = rte_le_to_cpu_32(req->speed);
4594         mac->link_duplex = hns3_get_bit(req->duplex,
4595                                            HNS3_PHY_DUPLEX_CFG_B);
4596         mac->link_autoneg = hns3_get_bit(req->autoneg,
4597                                            HNS3_PHY_AUTONEG_CFG_B);
4598         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4599         mac->advertising = rte_le_to_cpu_32(req->advertising);
4600         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4601         mac->support_autoneg = !!(mac->supported_capa &
4602                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4603 }
4604
4605 static int
4606 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4607 {
4608         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4609         uint16_t i;
4610         int ret;
4611
4612         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4613                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4614                                           true);
4615                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4616         }
4617         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4618
4619         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4620         if (ret) {
4621                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4622                 return ret;
4623         }
4624
4625         hns3_parse_phy_params(desc, mac);
4626
4627         return 0;
4628 }
4629
4630 static int
4631 hns3_update_phy_link_info(struct hns3_hw *hw)
4632 {
4633         struct hns3_mac *mac = &hw->mac;
4634         struct hns3_mac mac_info;
4635         int ret;
4636
4637         memset(&mac_info, 0, sizeof(struct hns3_mac));
4638         ret = hns3_get_phy_params(hw, &mac_info);
4639         if (ret)
4640                 return ret;
4641
4642         if (mac_info.link_speed != mac->link_speed) {
4643                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4644                 if (ret)
4645                         return ret;
4646         }
4647
4648         mac->link_speed = mac_info.link_speed;
4649         mac->link_duplex = mac_info.link_duplex;
4650         mac->link_autoneg = mac_info.link_autoneg;
4651         mac->supported_capa = mac_info.supported_capa;
4652         mac->advertising = mac_info.advertising;
4653         mac->lp_advertising = mac_info.lp_advertising;
4654         mac->support_autoneg = mac_info.support_autoneg;
4655
4656         return 0;
4657 }
4658
4659 static int
4660 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4661 {
4662         struct hns3_adapter *hns = eth_dev->data->dev_private;
4663         struct hns3_hw *hw = &hns->hw;
4664         int ret = 0;
4665
4666         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4667                 ret = hns3_update_phy_link_info(hw);
4668         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4669                 ret = hns3_update_fiber_link_info(hw);
4670
4671         return ret;
4672 }
4673
4674 static int
4675 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4676 {
4677         struct hns3_config_mac_mode_cmd *req;
4678         struct hns3_cmd_desc desc;
4679         uint32_t loop_en = 0;
4680         uint8_t val = 0;
4681         int ret;
4682
4683         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4684
4685         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4686         if (enable)
4687                 val = 1;
4688         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4689         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4690         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4691         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4692         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4693         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4694         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4695         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4696         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4697         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4698
4699         /*
4700          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4701          * when receiving frames. Otherwise, CRC will be stripped.
4702          */
4703         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4704                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4705         else
4706                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4707         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4708         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4709         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4710         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4711
4712         ret = hns3_cmd_send(hw, &desc, 1);
4713         if (ret)
4714                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4715
4716         return ret;
4717 }
4718
4719 static int
4720 hns3_get_mac_link_status(struct hns3_hw *hw)
4721 {
4722         struct hns3_link_status_cmd *req;
4723         struct hns3_cmd_desc desc;
4724         int link_status;
4725         int ret;
4726
4727         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4728         ret = hns3_cmd_send(hw, &desc, 1);
4729         if (ret) {
4730                 hns3_err(hw, "get link status cmd failed %d", ret);
4731                 return ETH_LINK_DOWN;
4732         }
4733
4734         req = (struct hns3_link_status_cmd *)desc.data;
4735         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4736
4737         return !!link_status;
4738 }
4739
4740 static bool
4741 hns3_update_link_status(struct hns3_hw *hw)
4742 {
4743         int state;
4744
4745         state = hns3_get_mac_link_status(hw);
4746         if (state != hw->mac.link_status) {
4747                 hw->mac.link_status = state;
4748                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4749                 hns3_config_mac_tnl_int(hw,
4750                                         state == ETH_LINK_UP ? true : false);
4751                 return true;
4752         }
4753
4754         return false;
4755 }
4756
4757 /*
4758  * Current, the PF driver get link status by two ways:
4759  * 1) Periodic polling in the intr thread context, driver call
4760  *    hns3_update_link_status to update link status.
4761  * 2) Firmware report async interrupt, driver process the event in the intr
4762  *    thread context, and call hns3_update_link_status to update link status.
4763  *
4764  * If detect link status changed, driver need report LSE. One method is add the
4765  * report LSE logic in hns3_update_link_status.
4766  *
4767  * But the PF driver ops(link_update) also call hns3_update_link_status to
4768  * update link status.
4769  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4770  * bonding application.
4771  *
4772  * So add the one new API which used only in intr thread context.
4773  */
4774 void
4775 hns3_update_link_status_and_event(struct hns3_hw *hw)
4776 {
4777         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4778         bool changed = hns3_update_link_status(hw);
4779         if (changed)
4780                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4781 }
4782
4783 static void
4784 hns3_service_handler(void *param)
4785 {
4786         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4787         struct hns3_adapter *hns = eth_dev->data->dev_private;
4788         struct hns3_hw *hw = &hns->hw;
4789
4790         if (!hns3_is_reset_pending(hns)) {
4791                 hns3_update_link_status_and_event(hw);
4792                 hns3_update_link_info(eth_dev);
4793         } else {
4794                 hns3_warn(hw, "Cancel the query when reset is pending");
4795         }
4796
4797         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4798 }
4799
4800 static int
4801 hns3_init_hardware(struct hns3_adapter *hns)
4802 {
4803         struct hns3_hw *hw = &hns->hw;
4804         int ret;
4805
4806         ret = hns3_map_tqp(hw);
4807         if (ret) {
4808                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4809                 return ret;
4810         }
4811
4812         ret = hns3_init_umv_space(hw);
4813         if (ret) {
4814                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4815                 return ret;
4816         }
4817
4818         ret = hns3_mac_init(hw);
4819         if (ret) {
4820                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4821                 goto err_mac_init;
4822         }
4823
4824         ret = hns3_init_mgr_tbl(hw);
4825         if (ret) {
4826                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4827                 goto err_mac_init;
4828         }
4829
4830         ret = hns3_promisc_init(hw);
4831         if (ret) {
4832                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4833                              ret);
4834                 goto err_mac_init;
4835         }
4836
4837         ret = hns3_init_vlan_config(hns);
4838         if (ret) {
4839                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4840                 goto err_mac_init;
4841         }
4842
4843         ret = hns3_dcb_init(hw);
4844         if (ret) {
4845                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4846                 goto err_mac_init;
4847         }
4848
4849         ret = hns3_init_fd_config(hns);
4850         if (ret) {
4851                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4852                 goto err_mac_init;
4853         }
4854
4855         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4856         if (ret) {
4857                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4858                 goto err_mac_init;
4859         }
4860
4861         ret = hns3_config_gro(hw, false);
4862         if (ret) {
4863                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4864                 goto err_mac_init;
4865         }
4866
4867         /*
4868          * In the initialization clearing the all hardware mapping relationship
4869          * configurations between queues and interrupt vectors is needed, so
4870          * some error caused by the residual configurations, such as the
4871          * unexpected interrupt, can be avoid.
4872          */
4873         ret = hns3_init_ring_with_vector(hw);
4874         if (ret) {
4875                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4876                 goto err_mac_init;
4877         }
4878
4879         /*
4880          * Requiring firmware to enable some features, driver can
4881          * still work without it.
4882          */
4883         ret = hns3_firmware_compat_config(hw, true);
4884         if (ret)
4885                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4886                              "supported, ret = %d.", ret);
4887
4888         return 0;
4889
4890 err_mac_init:
4891         hns3_uninit_umv_space(hw);
4892         return ret;
4893 }
4894
4895 static int
4896 hns3_clear_hw(struct hns3_hw *hw)
4897 {
4898         struct hns3_cmd_desc desc;
4899         int ret;
4900
4901         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4902
4903         ret = hns3_cmd_send(hw, &desc, 1);
4904         if (ret && ret != -EOPNOTSUPP)
4905                 return ret;
4906
4907         return 0;
4908 }
4909
4910 static void
4911 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4912 {
4913         uint32_t val;
4914
4915         /*
4916          * The new firmware support report more hardware error types by
4917          * msix mode. These errors are defined as RAS errors in hardware
4918          * and belong to a different type from the MSI-x errors processed
4919          * by the network driver.
4920          *
4921          * Network driver should open the new error report on initialition
4922          */
4923         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4924         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4925         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4926 }
4927
4928 static int
4929 hns3_init_pf(struct rte_eth_dev *eth_dev)
4930 {
4931         struct rte_device *dev = eth_dev->device;
4932         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4933         struct hns3_adapter *hns = eth_dev->data->dev_private;
4934         struct hns3_hw *hw = &hns->hw;
4935         int ret;
4936
4937         PMD_INIT_FUNC_TRACE();
4938
4939         /* Get hardware io base address from pcie BAR2 IO space */
4940         hw->io_base = pci_dev->mem_resource[2].addr;
4941
4942         /* Firmware command queue initialize */
4943         ret = hns3_cmd_init_queue(hw);
4944         if (ret) {
4945                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4946                 goto err_cmd_init_queue;
4947         }
4948
4949         hns3_clear_all_event_cause(hw);
4950
4951         /* Firmware command initialize */
4952         ret = hns3_cmd_init(hw);
4953         if (ret) {
4954                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4955                 goto err_cmd_init;
4956         }
4957
4958         /*
4959          * To ensure that the hardware environment is clean during
4960          * initialization, the driver actively clear the hardware environment
4961          * during initialization, including PF and corresponding VFs' vlan, mac,
4962          * flow table configurations, etc.
4963          */
4964         ret = hns3_clear_hw(hw);
4965         if (ret) {
4966                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4967                 goto err_cmd_init;
4968         }
4969
4970         /* Hardware statistics of imissed registers cleared. */
4971         ret = hns3_update_imissed_stats(hw, true);
4972         if (ret) {
4973                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4974                 return ret;
4975         }
4976
4977         hns3_config_all_msix_error(hw, true);
4978
4979         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4980                                          hns3_interrupt_handler,
4981                                          eth_dev);
4982         if (ret) {
4983                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4984                 goto err_intr_callback_register;
4985         }
4986
4987         ret = hns3_ptp_init(hw);
4988         if (ret)
4989                 goto err_get_config;
4990
4991         /* Enable interrupt */
4992         rte_intr_enable(&pci_dev->intr_handle);
4993         hns3_pf_enable_irq0(hw);
4994
4995         /* Get configuration */
4996         ret = hns3_get_configuration(hw);
4997         if (ret) {
4998                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4999                 goto err_get_config;
5000         }
5001
5002         ret = hns3_tqp_stats_init(hw);
5003         if (ret)
5004                 goto err_get_config;
5005
5006         ret = hns3_init_hardware(hns);
5007         if (ret) {
5008                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5009                 goto err_init_hw;
5010         }
5011
5012         /* Initialize flow director filter list & hash */
5013         ret = hns3_fdir_filter_init(hns);
5014         if (ret) {
5015                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5016                 goto err_fdir;
5017         }
5018
5019         hns3_rss_set_default_args(hw);
5020
5021         ret = hns3_enable_hw_error_intr(hns, true);
5022         if (ret) {
5023                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5024                              ret);
5025                 goto err_enable_intr;
5026         }
5027
5028         hns3_tm_conf_init(eth_dev);
5029
5030         return 0;
5031
5032 err_enable_intr:
5033         hns3_fdir_filter_uninit(hns);
5034 err_fdir:
5035         (void)hns3_firmware_compat_config(hw, false);
5036         hns3_uninit_umv_space(hw);
5037 err_init_hw:
5038         hns3_tqp_stats_uninit(hw);
5039 err_get_config:
5040         hns3_pf_disable_irq0(hw);
5041         rte_intr_disable(&pci_dev->intr_handle);
5042         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5043                              eth_dev);
5044 err_intr_callback_register:
5045 err_cmd_init:
5046         hns3_cmd_uninit(hw);
5047         hns3_cmd_destroy_queue(hw);
5048 err_cmd_init_queue:
5049         hw->io_base = NULL;
5050
5051         return ret;
5052 }
5053
5054 static void
5055 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5056 {
5057         struct hns3_adapter *hns = eth_dev->data->dev_private;
5058         struct rte_device *dev = eth_dev->device;
5059         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5060         struct hns3_hw *hw = &hns->hw;
5061
5062         PMD_INIT_FUNC_TRACE();
5063
5064         hns3_tm_conf_uninit(eth_dev);
5065         hns3_enable_hw_error_intr(hns, false);
5066         hns3_rss_uninit(hns);
5067         (void)hns3_config_gro(hw, false);
5068         hns3_promisc_uninit(hw);
5069         hns3_fdir_filter_uninit(hns);
5070         (void)hns3_firmware_compat_config(hw, false);
5071         hns3_uninit_umv_space(hw);
5072         hns3_tqp_stats_uninit(hw);
5073         hns3_config_mac_tnl_int(hw, false);
5074         hns3_pf_disable_irq0(hw);
5075         rte_intr_disable(&pci_dev->intr_handle);
5076         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5077                              eth_dev);
5078         hns3_config_all_msix_error(hw, false);
5079         hns3_cmd_uninit(hw);
5080         hns3_cmd_destroy_queue(hw);
5081         hw->io_base = NULL;
5082 }
5083
5084 static int
5085 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5086 {
5087         struct hns3_hw *hw = &hns->hw;
5088         int ret;
5089
5090         ret = hns3_dcb_cfg_update(hns);
5091         if (ret)
5092                 return ret;
5093
5094         /*
5095          * The hns3_dcb_cfg_update may configure TM module, so
5096          * hns3_tm_conf_update must called later.
5097          */
5098         ret = hns3_tm_conf_update(hw);
5099         if (ret) {
5100                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5101                 return ret;
5102         }
5103
5104         hns3_enable_rxd_adv_layout(hw);
5105
5106         ret = hns3_init_queues(hns, reset_queue);
5107         if (ret) {
5108                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5109                 return ret;
5110         }
5111
5112         ret = hns3_cfg_mac_mode(hw, true);
5113         if (ret) {
5114                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5115                 goto err_config_mac_mode;
5116         }
5117         return 0;
5118
5119 err_config_mac_mode:
5120         hns3_dev_release_mbufs(hns);
5121         /*
5122          * Here is exception handling, hns3_reset_all_tqps will have the
5123          * corresponding error message if it is handled incorrectly, so it is
5124          * not necessary to check hns3_reset_all_tqps return value, here keep
5125          * ret as the error code causing the exception.
5126          */
5127         (void)hns3_reset_all_tqps(hns);
5128         return ret;
5129 }
5130
5131 static int
5132 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5133 {
5134         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5136         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5138         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5139         uint32_t intr_vector;
5140         uint16_t q_id;
5141         int ret;
5142
5143         /*
5144          * hns3 needs a separate interrupt to be used as event interrupt which
5145          * could not be shared with task queue pair, so KERNEL drivers need
5146          * support multiple interrupt vectors.
5147          */
5148         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5149             !rte_intr_cap_multiple(intr_handle))
5150                 return 0;
5151
5152         rte_intr_disable(intr_handle);
5153         intr_vector = hw->used_rx_queues;
5154         /* creates event fd for each intr vector when MSIX is used */
5155         if (rte_intr_efd_enable(intr_handle, intr_vector))
5156                 return -EINVAL;
5157
5158         if (intr_handle->intr_vec == NULL) {
5159                 intr_handle->intr_vec =
5160                         rte_zmalloc("intr_vec",
5161                                     hw->used_rx_queues * sizeof(int), 0);
5162                 if (intr_handle->intr_vec == NULL) {
5163                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5164                                         hw->used_rx_queues);
5165                         ret = -ENOMEM;
5166                         goto alloc_intr_vec_error;
5167                 }
5168         }
5169
5170         if (rte_intr_allow_others(intr_handle)) {
5171                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5172                 base = RTE_INTR_VEC_RXTX_OFFSET;
5173         }
5174
5175         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5176                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5177                                                  HNS3_RING_TYPE_RX, q_id);
5178                 if (ret)
5179                         goto bind_vector_error;
5180                 intr_handle->intr_vec[q_id] = vec;
5181                 /*
5182                  * If there are not enough efds (e.g. not enough interrupt),
5183                  * remaining queues will be bond to the last interrupt.
5184                  */
5185                 if (vec < base + intr_handle->nb_efd - 1)
5186                         vec++;
5187         }
5188         rte_intr_enable(intr_handle);
5189         return 0;
5190
5191 bind_vector_error:
5192         rte_free(intr_handle->intr_vec);
5193         intr_handle->intr_vec = NULL;
5194 alloc_intr_vec_error:
5195         rte_intr_efd_disable(intr_handle);
5196         return ret;
5197 }
5198
5199 static int
5200 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5201 {
5202         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5203         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5204         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5205         uint16_t q_id;
5206         int ret;
5207
5208         if (dev->data->dev_conf.intr_conf.rxq == 0)
5209                 return 0;
5210
5211         if (rte_intr_dp_is_en(intr_handle)) {
5212                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5213                         ret = hns3_bind_ring_with_vector(hw,
5214                                         intr_handle->intr_vec[q_id], true,
5215                                         HNS3_RING_TYPE_RX, q_id);
5216                         if (ret)
5217                                 return ret;
5218                 }
5219         }
5220
5221         return 0;
5222 }
5223
5224 static void
5225 hns3_restore_filter(struct rte_eth_dev *dev)
5226 {
5227         hns3_restore_rss_filter(dev);
5228 }
5229
5230 static int
5231 hns3_dev_start(struct rte_eth_dev *dev)
5232 {
5233         struct hns3_adapter *hns = dev->data->dev_private;
5234         struct hns3_hw *hw = &hns->hw;
5235         int ret;
5236
5237         PMD_INIT_FUNC_TRACE();
5238         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5239                 return -EBUSY;
5240
5241         rte_spinlock_lock(&hw->lock);
5242         hw->adapter_state = HNS3_NIC_STARTING;
5243
5244         ret = hns3_do_start(hns, true);
5245         if (ret) {
5246                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5247                 rte_spinlock_unlock(&hw->lock);
5248                 return ret;
5249         }
5250         ret = hns3_map_rx_interrupt(dev);
5251         if (ret)
5252                 goto map_rx_inter_err;
5253
5254         /*
5255          * There are three register used to control the status of a TQP
5256          * (contains a pair of Tx queue and Rx queue) in the new version network
5257          * engine. One is used to control the enabling of Tx queue, the other is
5258          * used to control the enabling of Rx queue, and the last is the master
5259          * switch used to control the enabling of the tqp. The Tx register and
5260          * TQP register must be enabled at the same time to enable a Tx queue.
5261          * The same applies to the Rx queue. For the older network engine, this
5262          * function only refresh the enabled flag, and it is used to update the
5263          * status of queue in the dpdk framework.
5264          */
5265         ret = hns3_start_all_txqs(dev);
5266         if (ret)
5267                 goto map_rx_inter_err;
5268
5269         ret = hns3_start_all_rxqs(dev);
5270         if (ret)
5271                 goto start_all_rxqs_fail;
5272
5273         hw->adapter_state = HNS3_NIC_STARTED;
5274         rte_spinlock_unlock(&hw->lock);
5275
5276         hns3_rx_scattered_calc(dev);
5277         hns3_set_rxtx_function(dev);
5278         hns3_mp_req_start_rxtx(dev);
5279         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5280
5281         hns3_restore_filter(dev);
5282
5283         /* Enable interrupt of all rx queues before enabling queues */
5284         hns3_dev_all_rx_queue_intr_enable(hw, true);
5285
5286         /*
5287          * After finished the initialization, enable tqps to receive/transmit
5288          * packets and refresh all queue status.
5289          */
5290         hns3_start_tqps(hw);
5291
5292         hns3_tm_dev_start_proc(hw);
5293
5294         hns3_info(hw, "hns3 dev start successful!");
5295
5296         return 0;
5297
5298 start_all_rxqs_fail:
5299         hns3_stop_all_txqs(dev);
5300 map_rx_inter_err:
5301         (void)hns3_do_stop(hns);
5302         hw->adapter_state = HNS3_NIC_CONFIGURED;
5303         rte_spinlock_unlock(&hw->lock);
5304
5305         return ret;
5306 }
5307
5308 static int
5309 hns3_do_stop(struct hns3_adapter *hns)
5310 {
5311         struct hns3_hw *hw = &hns->hw;
5312         int ret;
5313
5314         /*
5315          * The "hns3_do_stop" function will also be called by .stop_service to
5316          * prepare reset. At the time of global or IMP reset, the command cannot
5317          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5318          * accessed during the reset process. So the mbuf can not be released
5319          * during reset and is required to be released after the reset is
5320          * completed.
5321          */
5322         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5323                 hns3_dev_release_mbufs(hns);
5324
5325         ret = hns3_cfg_mac_mode(hw, false);
5326         if (ret)
5327                 return ret;
5328         hw->mac.link_status = ETH_LINK_DOWN;
5329
5330         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5331                 hns3_configure_all_mac_addr(hns, true);
5332                 ret = hns3_reset_all_tqps(hns);
5333                 if (ret) {
5334                         hns3_err(hw, "failed to reset all queues ret = %d.",
5335                                  ret);
5336                         return ret;
5337                 }
5338         }
5339         hw->mac.default_addr_setted = false;
5340         return 0;
5341 }
5342
5343 static void
5344 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5345 {
5346         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5347         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5348         struct hns3_adapter *hns = dev->data->dev_private;
5349         struct hns3_hw *hw = &hns->hw;
5350         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5351         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5352         uint16_t q_id;
5353
5354         if (dev->data->dev_conf.intr_conf.rxq == 0)
5355                 return;
5356
5357         /* unmap the ring with vector */
5358         if (rte_intr_allow_others(intr_handle)) {
5359                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5360                 base = RTE_INTR_VEC_RXTX_OFFSET;
5361         }
5362         if (rte_intr_dp_is_en(intr_handle)) {
5363                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5364                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5365                                                          HNS3_RING_TYPE_RX,
5366                                                          q_id);
5367                         if (vec < base + intr_handle->nb_efd - 1)
5368                                 vec++;
5369                 }
5370         }
5371         /* Clean datapath event and queue/vec mapping */
5372         rte_intr_efd_disable(intr_handle);
5373         if (intr_handle->intr_vec) {
5374                 rte_free(intr_handle->intr_vec);
5375                 intr_handle->intr_vec = NULL;
5376         }
5377 }
5378
5379 static int
5380 hns3_dev_stop(struct rte_eth_dev *dev)
5381 {
5382         struct hns3_adapter *hns = dev->data->dev_private;
5383         struct hns3_hw *hw = &hns->hw;
5384
5385         PMD_INIT_FUNC_TRACE();
5386         dev->data->dev_started = 0;
5387
5388         hw->adapter_state = HNS3_NIC_STOPPING;
5389         hns3_set_rxtx_function(dev);
5390         rte_wmb();
5391         /* Disable datapath on secondary process. */
5392         hns3_mp_req_stop_rxtx(dev);
5393         /* Prevent crashes when queues are still in use. */
5394         rte_delay_ms(hw->tqps_num);
5395
5396         rte_spinlock_lock(&hw->lock);
5397         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5398                 hns3_tm_dev_stop_proc(hw);
5399                 hns3_config_mac_tnl_int(hw, false);
5400                 hns3_stop_tqps(hw);
5401                 hns3_do_stop(hns);
5402                 hns3_unmap_rx_interrupt(dev);
5403                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5404         }
5405         hns3_rx_scattered_reset(dev);
5406         rte_eal_alarm_cancel(hns3_service_handler, dev);
5407         rte_spinlock_unlock(&hw->lock);
5408
5409         return 0;
5410 }
5411
5412 static int
5413 hns3_dev_close(struct rte_eth_dev *eth_dev)
5414 {
5415         struct hns3_adapter *hns = eth_dev->data->dev_private;
5416         struct hns3_hw *hw = &hns->hw;
5417         int ret = 0;
5418
5419         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5420                 rte_free(eth_dev->process_private);
5421                 eth_dev->process_private = NULL;
5422                 return 0;
5423         }
5424
5425         if (hw->adapter_state == HNS3_NIC_STARTED)
5426                 ret = hns3_dev_stop(eth_dev);
5427
5428         hw->adapter_state = HNS3_NIC_CLOSING;
5429         hns3_reset_abort(hns);
5430         hw->adapter_state = HNS3_NIC_CLOSED;
5431
5432         hns3_configure_all_mc_mac_addr(hns, true);
5433         hns3_remove_all_vlan_table(hns);
5434         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5435         hns3_uninit_pf(eth_dev);
5436         hns3_free_all_queues(eth_dev);
5437         rte_free(hw->reset.wait_data);
5438         rte_free(eth_dev->process_private);
5439         eth_dev->process_private = NULL;
5440         hns3_mp_uninit_primary();
5441         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5442
5443         return ret;
5444 }
5445
5446 static int
5447 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5448 {
5449         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5451
5452         fc_conf->pause_time = pf->pause_time;
5453
5454         /* return fc current mode */
5455         switch (hw->current_mode) {
5456         case HNS3_FC_FULL:
5457                 fc_conf->mode = RTE_FC_FULL;
5458                 break;
5459         case HNS3_FC_TX_PAUSE:
5460                 fc_conf->mode = RTE_FC_TX_PAUSE;
5461                 break;
5462         case HNS3_FC_RX_PAUSE:
5463                 fc_conf->mode = RTE_FC_RX_PAUSE;
5464                 break;
5465         case HNS3_FC_NONE:
5466         default:
5467                 fc_conf->mode = RTE_FC_NONE;
5468                 break;
5469         }
5470
5471         return 0;
5472 }
5473
5474 static void
5475 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5476 {
5477         switch (mode) {
5478         case RTE_FC_NONE:
5479                 hw->requested_mode = HNS3_FC_NONE;
5480                 break;
5481         case RTE_FC_RX_PAUSE:
5482                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5483                 break;
5484         case RTE_FC_TX_PAUSE:
5485                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5486                 break;
5487         case RTE_FC_FULL:
5488                 hw->requested_mode = HNS3_FC_FULL;
5489                 break;
5490         default:
5491                 hw->requested_mode = HNS3_FC_NONE;
5492                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5493                           "configured to RTE_FC_NONE", mode);
5494                 break;
5495         }
5496 }
5497
5498 static int
5499 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5500 {
5501         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5502         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5503         int ret;
5504
5505         if (fc_conf->high_water || fc_conf->low_water ||
5506             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5507                 hns3_err(hw, "Unsupported flow control settings specified, "
5508                          "high_water(%u), low_water(%u), send_xon(%u) and "
5509                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5510                          fc_conf->high_water, fc_conf->low_water,
5511                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5512                 return -EINVAL;
5513         }
5514         if (fc_conf->autoneg) {
5515                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5516                 return -EINVAL;
5517         }
5518         if (!fc_conf->pause_time) {
5519                 hns3_err(hw, "Invalid pause time %u setting.",
5520                          fc_conf->pause_time);
5521                 return -EINVAL;
5522         }
5523
5524         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5525             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5526                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5527                          "current_fc_status = %d", hw->current_fc_status);
5528                 return -EOPNOTSUPP;
5529         }
5530
5531         hns3_get_fc_mode(hw, fc_conf->mode);
5532         if (hw->requested_mode == hw->current_mode &&
5533             pf->pause_time == fc_conf->pause_time)
5534                 return 0;
5535
5536         rte_spinlock_lock(&hw->lock);
5537         ret = hns3_fc_enable(dev, fc_conf);
5538         rte_spinlock_unlock(&hw->lock);
5539
5540         return ret;
5541 }
5542
5543 static int
5544 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5545                             struct rte_eth_pfc_conf *pfc_conf)
5546 {
5547         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5549         uint8_t priority;
5550         int ret;
5551
5552         if (!hns3_dev_dcb_supported(hw)) {
5553                 hns3_err(hw, "This port does not support dcb configurations.");
5554                 return -EOPNOTSUPP;
5555         }
5556
5557         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5558             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5559                 hns3_err(hw, "Unsupported flow control settings specified, "
5560                          "high_water(%u), low_water(%u), send_xon(%u) and "
5561                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5562                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5563                          pfc_conf->fc.send_xon,
5564                          pfc_conf->fc.mac_ctrl_frame_fwd);
5565                 return -EINVAL;
5566         }
5567         if (pfc_conf->fc.autoneg) {
5568                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5569                 return -EINVAL;
5570         }
5571         if (pfc_conf->fc.pause_time == 0) {
5572                 hns3_err(hw, "Invalid pause time %u setting.",
5573                          pfc_conf->fc.pause_time);
5574                 return -EINVAL;
5575         }
5576
5577         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5578             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5579                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5580                              "current_fc_status = %d", hw->current_fc_status);
5581                 return -EOPNOTSUPP;
5582         }
5583
5584         priority = pfc_conf->priority;
5585         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5586         if (hw->dcb_info.pfc_en & BIT(priority) &&
5587             hw->requested_mode == hw->current_mode &&
5588             pfc_conf->fc.pause_time == pf->pause_time)
5589                 return 0;
5590
5591         rte_spinlock_lock(&hw->lock);
5592         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5593         rte_spinlock_unlock(&hw->lock);
5594
5595         return ret;
5596 }
5597
5598 static int
5599 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5600 {
5601         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5602         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5603         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5604         int i;
5605
5606         rte_spinlock_lock(&hw->lock);
5607         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5608                 dcb_info->nb_tcs = pf->local_max_tc;
5609         else
5610                 dcb_info->nb_tcs = 1;
5611
5612         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5613                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5614         for (i = 0; i < dcb_info->nb_tcs; i++)
5615                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5616
5617         for (i = 0; i < hw->num_tc; i++) {
5618                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5619                 dcb_info->tc_queue.tc_txq[0][i].base =
5620                                                 hw->tc_queue[i].tqp_offset;
5621                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5622                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5623                                                 hw->tc_queue[i].tqp_count;
5624         }
5625         rte_spinlock_unlock(&hw->lock);
5626
5627         return 0;
5628 }
5629
5630 static int
5631 hns3_reinit_dev(struct hns3_adapter *hns)
5632 {
5633         struct hns3_hw *hw = &hns->hw;
5634         int ret;
5635
5636         ret = hns3_cmd_init(hw);
5637         if (ret) {
5638                 hns3_err(hw, "Failed to init cmd: %d", ret);
5639                 return ret;
5640         }
5641
5642         ret = hns3_reset_all_tqps(hns);
5643         if (ret) {
5644                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5645                 return ret;
5646         }
5647
5648         ret = hns3_init_hardware(hns);
5649         if (ret) {
5650                 hns3_err(hw, "Failed to init hardware: %d", ret);
5651                 return ret;
5652         }
5653
5654         ret = hns3_enable_hw_error_intr(hns, true);
5655         if (ret) {
5656                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5657                              ret);
5658                 return ret;
5659         }
5660         hns3_info(hw, "Reset done, driver initialization finished.");
5661
5662         return 0;
5663 }
5664
5665 static bool
5666 is_pf_reset_done(struct hns3_hw *hw)
5667 {
5668         uint32_t val, reg, reg_bit;
5669
5670         switch (hw->reset.level) {
5671         case HNS3_IMP_RESET:
5672                 reg = HNS3_GLOBAL_RESET_REG;
5673                 reg_bit = HNS3_IMP_RESET_BIT;
5674                 break;
5675         case HNS3_GLOBAL_RESET:
5676                 reg = HNS3_GLOBAL_RESET_REG;
5677                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5678                 break;
5679         case HNS3_FUNC_RESET:
5680                 reg = HNS3_FUN_RST_ING;
5681                 reg_bit = HNS3_FUN_RST_ING_B;
5682                 break;
5683         case HNS3_FLR_RESET:
5684         default:
5685                 hns3_err(hw, "Wait for unsupported reset level: %d",
5686                          hw->reset.level);
5687                 return true;
5688         }
5689         val = hns3_read_dev(hw, reg);
5690         if (hns3_get_bit(val, reg_bit))
5691                 return false;
5692         else
5693                 return true;
5694 }
5695
5696 bool
5697 hns3_is_reset_pending(struct hns3_adapter *hns)
5698 {
5699         struct hns3_hw *hw = &hns->hw;
5700         enum hns3_reset_level reset;
5701
5702         hns3_check_event_cause(hns, NULL);
5703         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5704         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5705                 hns3_warn(hw, "High level reset %d is pending", reset);
5706                 return true;
5707         }
5708         reset = hns3_get_reset_level(hns, &hw->reset.request);
5709         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5710                 hns3_warn(hw, "High level reset %d is request", reset);
5711                 return true;
5712         }
5713         return false;
5714 }
5715
5716 static int
5717 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5718 {
5719         struct hns3_hw *hw = &hns->hw;
5720         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5721         struct timeval tv;
5722
5723         if (wait_data->result == HNS3_WAIT_SUCCESS)
5724                 return 0;
5725         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5726                 gettimeofday(&tv, NULL);
5727                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5728                           tv.tv_sec, tv.tv_usec);
5729                 return -ETIME;
5730         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5731                 return -EAGAIN;
5732
5733         wait_data->hns = hns;
5734         wait_data->check_completion = is_pf_reset_done;
5735         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5736                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5737         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5738         wait_data->count = HNS3_RESET_WAIT_CNT;
5739         wait_data->result = HNS3_WAIT_REQUEST;
5740         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5741         return -EAGAIN;
5742 }
5743
5744 static int
5745 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5746 {
5747         struct hns3_cmd_desc desc;
5748         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5749
5750         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5751         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5752         req->fun_reset_vfid = func_id;
5753
5754         return hns3_cmd_send(hw, &desc, 1);
5755 }
5756
5757 static int
5758 hns3_imp_reset_cmd(struct hns3_hw *hw)
5759 {
5760         struct hns3_cmd_desc desc;
5761
5762         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5763         desc.data[0] = 0xeedd;
5764
5765         return hns3_cmd_send(hw, &desc, 1);
5766 }
5767
5768 static void
5769 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5770 {
5771         struct hns3_hw *hw = &hns->hw;
5772         struct timeval tv;
5773         uint32_t val;
5774
5775         gettimeofday(&tv, NULL);
5776         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5777             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5778                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5779                           tv.tv_sec, tv.tv_usec);
5780                 return;
5781         }
5782
5783         switch (reset_level) {
5784         case HNS3_IMP_RESET:
5785                 hns3_imp_reset_cmd(hw);
5786                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5787                           tv.tv_sec, tv.tv_usec);
5788                 break;
5789         case HNS3_GLOBAL_RESET:
5790                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5791                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5792                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5793                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5794                           tv.tv_sec, tv.tv_usec);
5795                 break;
5796         case HNS3_FUNC_RESET:
5797                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5798                           tv.tv_sec, tv.tv_usec);
5799                 /* schedule again to check later */
5800                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5801                 hns3_schedule_reset(hns);
5802                 break;
5803         default:
5804                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5805                 return;
5806         }
5807         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5808 }
5809
5810 static enum hns3_reset_level
5811 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5812 {
5813         struct hns3_hw *hw = &hns->hw;
5814         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5815
5816         /* Return the highest priority reset level amongst all */
5817         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5818                 reset_level = HNS3_IMP_RESET;
5819         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5820                 reset_level = HNS3_GLOBAL_RESET;
5821         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5822                 reset_level = HNS3_FUNC_RESET;
5823         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5824                 reset_level = HNS3_FLR_RESET;
5825
5826         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5827                 return HNS3_NONE_RESET;
5828
5829         return reset_level;
5830 }
5831
5832 static void
5833 hns3_record_imp_error(struct hns3_adapter *hns)
5834 {
5835         struct hns3_hw *hw = &hns->hw;
5836         uint32_t reg_val;
5837
5838         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5839         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5840                 hns3_warn(hw, "Detected IMP RD poison!");
5841                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5842                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5843         }
5844
5845         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5846                 hns3_warn(hw, "Detected IMP CMDQ error!");
5847                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5848                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5849         }
5850 }
5851
5852 static int
5853 hns3_prepare_reset(struct hns3_adapter *hns)
5854 {
5855         struct hns3_hw *hw = &hns->hw;
5856         uint32_t reg_val;
5857         int ret;
5858
5859         switch (hw->reset.level) {
5860         case HNS3_FUNC_RESET:
5861                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5862                 if (ret)
5863                         return ret;
5864
5865                 /*
5866                  * After performaning pf reset, it is not necessary to do the
5867                  * mailbox handling or send any command to firmware, because
5868                  * any mailbox handling or command to firmware is only valid
5869                  * after hns3_cmd_init is called.
5870                  */
5871                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5872                 hw->reset.stats.request_cnt++;
5873                 break;
5874         case HNS3_IMP_RESET:
5875                 hns3_record_imp_error(hns);
5876                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5877                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5878                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5879                 break;
5880         default:
5881                 break;
5882         }
5883         return 0;
5884 }
5885
5886 static int
5887 hns3_set_rst_done(struct hns3_hw *hw)
5888 {
5889         struct hns3_pf_rst_done_cmd *req;
5890         struct hns3_cmd_desc desc;
5891
5892         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5893         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5894         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5895         return hns3_cmd_send(hw, &desc, 1);
5896 }
5897
5898 static int
5899 hns3_stop_service(struct hns3_adapter *hns)
5900 {
5901         struct hns3_hw *hw = &hns->hw;
5902         struct rte_eth_dev *eth_dev;
5903
5904         eth_dev = &rte_eth_devices[hw->data->port_id];
5905         if (hw->adapter_state == HNS3_NIC_STARTED) {
5906                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5907                 hns3_update_link_status_and_event(hw);
5908         }
5909         hw->mac.link_status = ETH_LINK_DOWN;
5910
5911         hns3_set_rxtx_function(eth_dev);
5912         rte_wmb();
5913         /* Disable datapath on secondary process. */
5914         hns3_mp_req_stop_rxtx(eth_dev);
5915         rte_delay_ms(hw->tqps_num);
5916
5917         rte_spinlock_lock(&hw->lock);
5918         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5919             hw->adapter_state == HNS3_NIC_STOPPING) {
5920                 hns3_enable_all_queues(hw, false);
5921                 hns3_do_stop(hns);
5922                 hw->reset.mbuf_deferred_free = true;
5923         } else
5924                 hw->reset.mbuf_deferred_free = false;
5925
5926         /*
5927          * It is cumbersome for hardware to pick-and-choose entries for deletion
5928          * from table space. Hence, for function reset software intervention is
5929          * required to delete the entries
5930          */
5931         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5932                 hns3_configure_all_mc_mac_addr(hns, true);
5933         rte_spinlock_unlock(&hw->lock);
5934
5935         return 0;
5936 }
5937
5938 static int
5939 hns3_start_service(struct hns3_adapter *hns)
5940 {
5941         struct hns3_hw *hw = &hns->hw;
5942         struct rte_eth_dev *eth_dev;
5943
5944         if (hw->reset.level == HNS3_IMP_RESET ||
5945             hw->reset.level == HNS3_GLOBAL_RESET)
5946                 hns3_set_rst_done(hw);
5947         eth_dev = &rte_eth_devices[hw->data->port_id];
5948         hns3_set_rxtx_function(eth_dev);
5949         hns3_mp_req_start_rxtx(eth_dev);
5950         if (hw->adapter_state == HNS3_NIC_STARTED) {
5951                 /*
5952                  * This API parent function already hold the hns3_hw.lock, the
5953                  * hns3_service_handler may report lse, in bonding application
5954                  * it will call driver's ops which may acquire the hns3_hw.lock
5955                  * again, thus lead to deadlock.
5956                  * We defer calls hns3_service_handler to avoid the deadlock.
5957                  */
5958                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5959                                   hns3_service_handler, eth_dev);
5960
5961                 /* Enable interrupt of all rx queues before enabling queues */
5962                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5963                 /*
5964                  * Enable state of each rxq and txq will be recovered after
5965                  * reset, so we need to restore them before enable all tqps;
5966                  */
5967                 hns3_restore_tqp_enable_state(hw);
5968                 /*
5969                  * When finished the initialization, enable queues to receive
5970                  * and transmit packets.
5971                  */
5972                 hns3_enable_all_queues(hw, true);
5973         }
5974
5975         return 0;
5976 }
5977
5978 static int
5979 hns3_restore_conf(struct hns3_adapter *hns)
5980 {
5981         struct hns3_hw *hw = &hns->hw;
5982         int ret;
5983
5984         ret = hns3_configure_all_mac_addr(hns, false);
5985         if (ret)
5986                 return ret;
5987
5988         ret = hns3_configure_all_mc_mac_addr(hns, false);
5989         if (ret)
5990                 goto err_mc_mac;
5991
5992         ret = hns3_dev_promisc_restore(hns);
5993         if (ret)
5994                 goto err_promisc;
5995
5996         ret = hns3_restore_vlan_table(hns);
5997         if (ret)
5998                 goto err_promisc;
5999
6000         ret = hns3_restore_vlan_conf(hns);
6001         if (ret)
6002                 goto err_promisc;
6003
6004         ret = hns3_restore_all_fdir_filter(hns);
6005         if (ret)
6006                 goto err_promisc;
6007
6008         ret = hns3_restore_ptp(hns);
6009         if (ret)
6010                 goto err_promisc;
6011
6012         ret = hns3_restore_rx_interrupt(hw);
6013         if (ret)
6014                 goto err_promisc;
6015
6016         ret = hns3_restore_gro_conf(hw);
6017         if (ret)
6018                 goto err_promisc;
6019
6020         ret = hns3_restore_fec(hw);
6021         if (ret)
6022                 goto err_promisc;
6023
6024         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6025                 ret = hns3_do_start(hns, false);
6026                 if (ret)
6027                         goto err_promisc;
6028                 hns3_info(hw, "hns3 dev restart successful!");
6029         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6030                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6031         return 0;
6032
6033 err_promisc:
6034         hns3_configure_all_mc_mac_addr(hns, true);
6035 err_mc_mac:
6036         hns3_configure_all_mac_addr(hns, true);
6037         return ret;
6038 }
6039
6040 static void
6041 hns3_reset_service(void *param)
6042 {
6043         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6044         struct hns3_hw *hw = &hns->hw;
6045         enum hns3_reset_level reset_level;
6046         struct timeval tv_delta;
6047         struct timeval tv_start;
6048         struct timeval tv;
6049         uint64_t msec;
6050         int ret;
6051
6052         /*
6053          * The interrupt is not triggered within the delay time.
6054          * The interrupt may have been lost. It is necessary to handle
6055          * the interrupt to recover from the error.
6056          */
6057         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6058                             SCHEDULE_DEFERRED) {
6059                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6060                                   __ATOMIC_RELAXED);
6061                 hns3_err(hw, "Handling interrupts in delayed tasks");
6062                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6063                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6064                 if (reset_level == HNS3_NONE_RESET) {
6065                         hns3_err(hw, "No reset level is set, try IMP reset");
6066                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6067                 }
6068         }
6069         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6070
6071         /*
6072          * Check if there is any ongoing reset in the hardware. This status can
6073          * be checked from reset_pending. If there is then, we need to wait for
6074          * hardware to complete reset.
6075          *    a. If we are able to figure out in reasonable time that hardware
6076          *       has fully resetted then, we can proceed with driver, client
6077          *       reset.
6078          *    b. else, we can come back later to check this status so re-sched
6079          *       now.
6080          */
6081         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6082         if (reset_level != HNS3_NONE_RESET) {
6083                 gettimeofday(&tv_start, NULL);
6084                 ret = hns3_reset_process(hns, reset_level);
6085                 gettimeofday(&tv, NULL);
6086                 timersub(&tv, &tv_start, &tv_delta);
6087                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6088                        tv_delta.tv_usec / USEC_PER_MSEC;
6089                 if (msec > HNS3_RESET_PROCESS_MS)
6090                         hns3_err(hw, "%d handle long time delta %" PRIx64
6091                                      " ms time=%ld.%.6ld",
6092                                  hw->reset.level, msec,
6093                                  tv.tv_sec, tv.tv_usec);
6094                 if (ret == -EAGAIN)
6095                         return;
6096         }
6097
6098         /* Check if we got any *new* reset requests to be honored */
6099         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6100         if (reset_level != HNS3_NONE_RESET)
6101                 hns3_msix_process(hns, reset_level);
6102 }
6103
6104 static unsigned int
6105 hns3_get_speed_capa_num(uint16_t device_id)
6106 {
6107         unsigned int num;
6108
6109         switch (device_id) {
6110         case HNS3_DEV_ID_25GE:
6111         case HNS3_DEV_ID_25GE_RDMA:
6112                 num = 2;
6113                 break;
6114         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6115         case HNS3_DEV_ID_200G_RDMA:
6116                 num = 1;
6117                 break;
6118         default:
6119                 num = 0;
6120                 break;
6121         }
6122
6123         return num;
6124 }
6125
6126 static int
6127 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6128                         uint16_t device_id)
6129 {
6130         switch (device_id) {
6131         case HNS3_DEV_ID_25GE:
6132         /* fallthrough */
6133         case HNS3_DEV_ID_25GE_RDMA:
6134                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6135                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6136
6137                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6138                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6139                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6140                 break;
6141         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6142                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6143                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6144                 break;
6145         case HNS3_DEV_ID_200G_RDMA:
6146                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6147                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6148                 break;
6149         default:
6150                 return -ENOTSUP;
6151         }
6152
6153         return 0;
6154 }
6155
6156 static int
6157 hns3_fec_get_capability(struct rte_eth_dev *dev,
6158                         struct rte_eth_fec_capa *speed_fec_capa,
6159                         unsigned int num)
6160 {
6161         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6163         uint16_t device_id = pci_dev->id.device_id;
6164         unsigned int capa_num;
6165         int ret;
6166
6167         capa_num = hns3_get_speed_capa_num(device_id);
6168         if (capa_num == 0) {
6169                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6170                          device_id);
6171                 return -ENOTSUP;
6172         }
6173
6174         if (speed_fec_capa == NULL || num < capa_num)
6175                 return capa_num;
6176
6177         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6178         if (ret)
6179                 return -ENOTSUP;
6180
6181         return capa_num;
6182 }
6183
6184 static int
6185 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6186 {
6187         struct hns3_config_fec_cmd *req;
6188         struct hns3_cmd_desc desc;
6189         int ret;
6190
6191         /*
6192          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6193          * in device of link speed
6194          * below 10 Gbps.
6195          */
6196         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6197                 *state = 0;
6198                 return 0;
6199         }
6200
6201         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6202         req = (struct hns3_config_fec_cmd *)desc.data;
6203         ret = hns3_cmd_send(hw, &desc, 1);
6204         if (ret) {
6205                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6206                          ret);
6207                 return ret;
6208         }
6209
6210         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6211         return 0;
6212 }
6213
6214 static int
6215 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6216 {
6217 #define QUERY_ACTIVE_SPEED      1
6218         struct hns3_sfp_speed_cmd *resp;
6219         uint32_t tmp_fec_capa;
6220         uint8_t auto_state;
6221         struct hns3_cmd_desc desc;
6222         int ret;
6223
6224         /*
6225          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6226          * configured FEC mode is returned.
6227          * If link is up, current FEC mode is returned.
6228          */
6229         if (hw->mac.link_status == ETH_LINK_DOWN) {
6230                 ret = get_current_fec_auto_state(hw, &auto_state);
6231                 if (ret)
6232                         return ret;
6233
6234                 if (auto_state == 0x1) {
6235                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6236                         return 0;
6237                 }
6238         }
6239
6240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6241         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6242         resp->query_type = QUERY_ACTIVE_SPEED;
6243
6244         ret = hns3_cmd_send(hw, &desc, 1);
6245         if (ret == -EOPNOTSUPP) {
6246                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6247                 return ret;
6248         } else if (ret) {
6249                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6250                 return ret;
6251         }
6252
6253         /*
6254          * FEC mode order defined in hns3 hardware is inconsistend with
6255          * that defined in the ethdev library. So the sequence needs
6256          * to be converted.
6257          */
6258         switch (resp->active_fec) {
6259         case HNS3_HW_FEC_MODE_NOFEC:
6260                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6261                 break;
6262         case HNS3_HW_FEC_MODE_BASER:
6263                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6264                 break;
6265         case HNS3_HW_FEC_MODE_RS:
6266                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6267                 break;
6268         default:
6269                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6270                 break;
6271         }
6272
6273         *fec_capa = tmp_fec_capa;
6274         return 0;
6275 }
6276
6277 static int
6278 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6279 {
6280         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6281
6282         return hns3_fec_get_internal(hw, fec_capa);
6283 }
6284
6285 static int
6286 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6287 {
6288         struct hns3_config_fec_cmd *req;
6289         struct hns3_cmd_desc desc;
6290         int ret;
6291
6292         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6293
6294         req = (struct hns3_config_fec_cmd *)desc.data;
6295         switch (mode) {
6296         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6297                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6298                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6299                 break;
6300         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6301                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6302                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6303                 break;
6304         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6305                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6306                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6307                 break;
6308         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6309                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6310                 break;
6311         default:
6312                 return 0;
6313         }
6314         ret = hns3_cmd_send(hw, &desc, 1);
6315         if (ret)
6316                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6317
6318         return ret;
6319 }
6320
6321 static uint32_t
6322 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6323 {
6324         struct hns3_mac *mac = &hw->mac;
6325         uint32_t cur_capa;
6326
6327         switch (mac->link_speed) {
6328         case ETH_SPEED_NUM_10G:
6329                 cur_capa = fec_capa[1].capa;
6330                 break;
6331         case ETH_SPEED_NUM_25G:
6332         case ETH_SPEED_NUM_100G:
6333         case ETH_SPEED_NUM_200G:
6334                 cur_capa = fec_capa[0].capa;
6335                 break;
6336         default:
6337                 cur_capa = 0;
6338                 break;
6339         }
6340
6341         return cur_capa;
6342 }
6343
6344 static bool
6345 is_fec_mode_one_bit_set(uint32_t mode)
6346 {
6347         int cnt = 0;
6348         uint8_t i;
6349
6350         for (i = 0; i < sizeof(mode); i++)
6351                 if (mode >> i & 0x1)
6352                         cnt++;
6353
6354         return cnt == 1 ? true : false;
6355 }
6356
6357 static int
6358 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6359 {
6360 #define FEC_CAPA_NUM 2
6361         struct hns3_adapter *hns = dev->data->dev_private;
6362         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6363         struct hns3_pf *pf = &hns->pf;
6364
6365         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6366         uint32_t cur_capa;
6367         uint32_t num = FEC_CAPA_NUM;
6368         int ret;
6369
6370         ret = hns3_fec_get_capability(dev, fec_capa, num);
6371         if (ret < 0)
6372                 return ret;
6373
6374         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6375         if (!is_fec_mode_one_bit_set(mode))
6376                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6377                              "FEC mode should be only one bit set", mode);
6378
6379         /*
6380          * Check whether the configured mode is within the FEC capability.
6381          * If not, the configured mode will not be supported.
6382          */
6383         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6384         if (!(cur_capa & mode)) {
6385                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6386                 return -EINVAL;
6387         }
6388
6389         ret = hns3_set_fec_hw(hw, mode);
6390         if (ret)
6391                 return ret;
6392
6393         pf->fec_mode = mode;
6394         return 0;
6395 }
6396
6397 static int
6398 hns3_restore_fec(struct hns3_hw *hw)
6399 {
6400         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6401         struct hns3_pf *pf = &hns->pf;
6402         uint32_t mode = pf->fec_mode;
6403         int ret;
6404
6405         ret = hns3_set_fec_hw(hw, mode);
6406         if (ret)
6407                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6408                          mode, ret);
6409
6410         return ret;
6411 }
6412
6413 static int
6414 hns3_query_dev_fec_info(struct hns3_hw *hw)
6415 {
6416         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6417         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6418         int ret;
6419
6420         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6421         if (ret)
6422                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6423
6424         return ret;
6425 }
6426
6427 static bool
6428 hns3_optical_module_existed(struct hns3_hw *hw)
6429 {
6430         struct hns3_cmd_desc desc;
6431         bool existed;
6432         int ret;
6433
6434         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6435         ret = hns3_cmd_send(hw, &desc, 1);
6436         if (ret) {
6437                 hns3_err(hw,
6438                          "fail to get optical module exist state, ret = %d.\n",
6439                          ret);
6440                 return false;
6441         }
6442         existed = !!desc.data[0];
6443
6444         return existed;
6445 }
6446
6447 static int
6448 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6449                                 uint32_t len, uint8_t *data)
6450 {
6451 #define HNS3_SFP_INFO_CMD_NUM 6
6452 #define HNS3_SFP_INFO_MAX_LEN \
6453         (HNS3_SFP_INFO_BD0_LEN + \
6454         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6455         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6456         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6457         uint16_t read_len;
6458         uint16_t copy_len;
6459         int ret;
6460         int i;
6461
6462         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6463                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6464                                           true);
6465                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6466                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6467         }
6468
6469         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6470         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6471         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6472         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6473
6474         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6475         if (ret) {
6476                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6477                                 ret);
6478                 return ret;
6479         }
6480
6481         /* The data format in BD0 is different with the others. */
6482         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6483         memcpy(data, sfp_info_bd0->data, copy_len);
6484         read_len = copy_len;
6485
6486         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6487                 if (read_len >= len)
6488                         break;
6489
6490                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6491                 memcpy(data + read_len, desc[i].data, copy_len);
6492                 read_len += copy_len;
6493         }
6494
6495         return (int)read_len;
6496 }
6497
6498 static int
6499 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6500                        struct rte_dev_eeprom_info *info)
6501 {
6502         struct hns3_adapter *hns = dev->data->dev_private;
6503         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6504         uint32_t offset = info->offset;
6505         uint32_t len = info->length;
6506         uint8_t *data = info->data;
6507         uint32_t read_len = 0;
6508
6509         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6510                 return -ENOTSUP;
6511
6512         if (!hns3_optical_module_existed(hw)) {
6513                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6514                 return -EIO;
6515         }
6516
6517         while (read_len < len) {
6518                 int ret;
6519                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6520                                                   len - read_len,
6521                                                   data + read_len);
6522                 if (ret < 0)
6523                         return -EIO;
6524                 read_len += ret;
6525         }
6526
6527         return 0;
6528 }
6529
6530 static int
6531 hns3_get_module_info(struct rte_eth_dev *dev,
6532                      struct rte_eth_dev_module_info *modinfo)
6533 {
6534 #define HNS3_SFF8024_ID_SFP             0x03
6535 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6536 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6537 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6538 #define HNS3_SFF_8636_V1_3              0x03
6539         struct hns3_adapter *hns = dev->data->dev_private;
6540         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6541         struct rte_dev_eeprom_info info;
6542         struct hns3_sfp_type sfp_type;
6543         int ret;
6544
6545         memset(&sfp_type, 0, sizeof(sfp_type));
6546         memset(&info, 0, sizeof(info));
6547         info.data = (uint8_t *)&sfp_type;
6548         info.length = sizeof(sfp_type);
6549         ret = hns3_get_module_eeprom(dev, &info);
6550         if (ret)
6551                 return ret;
6552
6553         switch (sfp_type.type) {
6554         case HNS3_SFF8024_ID_SFP:
6555                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6556                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6557                 break;
6558         case HNS3_SFF8024_ID_QSFP_8438:
6559                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6560                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6561                 break;
6562         case HNS3_SFF8024_ID_QSFP_8436_8636:
6563                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6564                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6565                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6566                 } else {
6567                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6568                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6569                 }
6570                 break;
6571         case HNS3_SFF8024_ID_QSFP28_8636:
6572                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6573                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6574                 break;
6575         default:
6576                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6577                          sfp_type.type, sfp_type.ext_type);
6578                 return -EINVAL;
6579         }
6580
6581         return 0;
6582 }
6583
6584 static int
6585 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6586 {
6587         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6588
6589         RTE_SET_USED(key);
6590
6591         if (strcmp(value, "vec") == 0)
6592                 hint = HNS3_IO_FUNC_HINT_VEC;
6593         else if (strcmp(value, "sve") == 0)
6594                 hint = HNS3_IO_FUNC_HINT_SVE;
6595         else if (strcmp(value, "simple") == 0)
6596                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6597         else if (strcmp(value, "common") == 0)
6598                 hint = HNS3_IO_FUNC_HINT_COMMON;
6599
6600         /* If the hint is valid then update output parameters */
6601         if (hint != HNS3_IO_FUNC_HINT_NONE)
6602                 *(uint32_t *)extra_args = hint;
6603
6604         return 0;
6605 }
6606
6607 static const char *
6608 hns3_get_io_hint_func_name(uint32_t hint)
6609 {
6610         switch (hint) {
6611         case HNS3_IO_FUNC_HINT_VEC:
6612                 return "vec";
6613         case HNS3_IO_FUNC_HINT_SVE:
6614                 return "sve";
6615         case HNS3_IO_FUNC_HINT_SIMPLE:
6616                 return "simple";
6617         case HNS3_IO_FUNC_HINT_COMMON:
6618                 return "common";
6619         default:
6620                 return "none";
6621         }
6622 }
6623
6624 void
6625 hns3_parse_devargs(struct rte_eth_dev *dev)
6626 {
6627         struct hns3_adapter *hns = dev->data->dev_private;
6628         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6629         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6630         struct hns3_hw *hw = &hns->hw;
6631         struct rte_kvargs *kvlist;
6632
6633         if (dev->device->devargs == NULL)
6634                 return;
6635
6636         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6637         if (!kvlist)
6638                 return;
6639
6640         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6641                            &hns3_parse_io_hint_func, &rx_func_hint);
6642         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6643                            &hns3_parse_io_hint_func, &tx_func_hint);
6644         rte_kvargs_free(kvlist);
6645
6646         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6647                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6648                           hns3_get_io_hint_func_name(rx_func_hint));
6649         hns->rx_func_hint = rx_func_hint;
6650         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6651                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6652                           hns3_get_io_hint_func_name(tx_func_hint));
6653         hns->tx_func_hint = tx_func_hint;
6654 }
6655
6656 static const struct eth_dev_ops hns3_eth_dev_ops = {
6657         .dev_configure      = hns3_dev_configure,
6658         .dev_start          = hns3_dev_start,
6659         .dev_stop           = hns3_dev_stop,
6660         .dev_close          = hns3_dev_close,
6661         .promiscuous_enable = hns3_dev_promiscuous_enable,
6662         .promiscuous_disable = hns3_dev_promiscuous_disable,
6663         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6664         .allmulticast_disable = hns3_dev_allmulticast_disable,
6665         .mtu_set            = hns3_dev_mtu_set,
6666         .stats_get          = hns3_stats_get,
6667         .stats_reset        = hns3_stats_reset,
6668         .xstats_get         = hns3_dev_xstats_get,
6669         .xstats_get_names   = hns3_dev_xstats_get_names,
6670         .xstats_reset       = hns3_dev_xstats_reset,
6671         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6672         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6673         .dev_infos_get          = hns3_dev_infos_get,
6674         .fw_version_get         = hns3_fw_version_get,
6675         .rx_queue_setup         = hns3_rx_queue_setup,
6676         .tx_queue_setup         = hns3_tx_queue_setup,
6677         .rx_queue_release       = hns3_dev_rx_queue_release,
6678         .tx_queue_release       = hns3_dev_tx_queue_release,
6679         .rx_queue_start         = hns3_dev_rx_queue_start,
6680         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6681         .tx_queue_start         = hns3_dev_tx_queue_start,
6682         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6683         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6684         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6685         .rxq_info_get           = hns3_rxq_info_get,
6686         .txq_info_get           = hns3_txq_info_get,
6687         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6688         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6689         .flow_ctrl_get          = hns3_flow_ctrl_get,
6690         .flow_ctrl_set          = hns3_flow_ctrl_set,
6691         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6692         .mac_addr_add           = hns3_add_mac_addr,
6693         .mac_addr_remove        = hns3_remove_mac_addr,
6694         .mac_addr_set           = hns3_set_default_mac_addr,
6695         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6696         .link_update            = hns3_dev_link_update,
6697         .rss_hash_update        = hns3_dev_rss_hash_update,
6698         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6699         .reta_update            = hns3_dev_rss_reta_update,
6700         .reta_query             = hns3_dev_rss_reta_query,
6701         .flow_ops_get           = hns3_dev_flow_ops_get,
6702         .vlan_filter_set        = hns3_vlan_filter_set,
6703         .vlan_tpid_set          = hns3_vlan_tpid_set,
6704         .vlan_offload_set       = hns3_vlan_offload_set,
6705         .vlan_pvid_set          = hns3_vlan_pvid_set,
6706         .get_reg                = hns3_get_regs,
6707         .get_module_info        = hns3_get_module_info,
6708         .get_module_eeprom      = hns3_get_module_eeprom,
6709         .get_dcb_info           = hns3_get_dcb_info,
6710         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6711         .fec_get_capability     = hns3_fec_get_capability,
6712         .fec_get                = hns3_fec_get,
6713         .fec_set                = hns3_fec_set,
6714         .tm_ops_get             = hns3_tm_ops_get,
6715         .tx_done_cleanup        = hns3_tx_done_cleanup,
6716         .timesync_enable            = hns3_timesync_enable,
6717         .timesync_disable           = hns3_timesync_disable,
6718         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6719         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6720         .timesync_adjust_time       = hns3_timesync_adjust_time,
6721         .timesync_read_time         = hns3_timesync_read_time,
6722         .timesync_write_time        = hns3_timesync_write_time,
6723 };
6724
6725 static const struct hns3_reset_ops hns3_reset_ops = {
6726         .reset_service       = hns3_reset_service,
6727         .stop_service        = hns3_stop_service,
6728         .prepare_reset       = hns3_prepare_reset,
6729         .wait_hardware_ready = hns3_wait_hardware_ready,
6730         .reinit_dev          = hns3_reinit_dev,
6731         .restore_conf        = hns3_restore_conf,
6732         .start_service       = hns3_start_service,
6733 };
6734
6735 static int
6736 hns3_dev_init(struct rte_eth_dev *eth_dev)
6737 {
6738         struct hns3_adapter *hns = eth_dev->data->dev_private;
6739         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6740         struct rte_ether_addr *eth_addr;
6741         struct hns3_hw *hw = &hns->hw;
6742         int ret;
6743
6744         PMD_INIT_FUNC_TRACE();
6745
6746         eth_dev->process_private = (struct hns3_process_private *)
6747             rte_zmalloc_socket("hns3_filter_list",
6748                                sizeof(struct hns3_process_private),
6749                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6750         if (eth_dev->process_private == NULL) {
6751                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6752                 return -ENOMEM;
6753         }
6754         /* initialize flow filter lists */
6755         hns3_filterlist_init(eth_dev);
6756
6757         hns3_set_rxtx_function(eth_dev);
6758         eth_dev->dev_ops = &hns3_eth_dev_ops;
6759         eth_dev->rx_queue_count = hns3_rx_queue_count;
6760         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6761                 ret = hns3_mp_init_secondary();
6762                 if (ret) {
6763                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6764                                      "process, ret = %d", ret);
6765                         goto err_mp_init_secondary;
6766                 }
6767
6768                 hw->secondary_cnt++;
6769                 return 0;
6770         }
6771
6772         ret = hns3_mp_init_primary();
6773         if (ret) {
6774                 PMD_INIT_LOG(ERR,
6775                              "Failed to init for primary process, ret = %d",
6776                              ret);
6777                 goto err_mp_init_primary;
6778         }
6779
6780         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6781         hns->is_vf = false;
6782         hw->data = eth_dev->data;
6783         hns3_parse_devargs(eth_dev);
6784
6785         /*
6786          * Set default max packet size according to the mtu
6787          * default vale in DPDK frame.
6788          */
6789         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6790
6791         ret = hns3_reset_init(hw);
6792         if (ret)
6793                 goto err_init_reset;
6794         hw->reset.ops = &hns3_reset_ops;
6795
6796         ret = hns3_init_pf(eth_dev);
6797         if (ret) {
6798                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6799                 goto err_init_pf;
6800         }
6801
6802         /* Allocate memory for storing MAC addresses */
6803         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6804                                                sizeof(struct rte_ether_addr) *
6805                                                HNS3_UC_MACADDR_NUM, 0);
6806         if (eth_dev->data->mac_addrs == NULL) {
6807                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6808                              "to store MAC addresses",
6809                              sizeof(struct rte_ether_addr) *
6810                              HNS3_UC_MACADDR_NUM);
6811                 ret = -ENOMEM;
6812                 goto err_rte_zmalloc;
6813         }
6814
6815         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6816         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6817                 rte_eth_random_addr(hw->mac.mac_addr);
6818                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6819                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6820                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6821                           "unicast address, using random MAC address %s",
6822                           mac_str);
6823         }
6824         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6825                             &eth_dev->data->mac_addrs[0]);
6826
6827         hw->adapter_state = HNS3_NIC_INITIALIZED;
6828
6829         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6830                             SCHEDULE_PENDING) {
6831                 hns3_err(hw, "Reschedule reset service after dev_init");
6832                 hns3_schedule_reset(hns);
6833         } else {
6834                 /* IMP will wait ready flag before reset */
6835                 hns3_notify_reset_ready(hw, false);
6836         }
6837
6838         hns3_info(hw, "hns3 dev initialization successful!");
6839         return 0;
6840
6841 err_rte_zmalloc:
6842         hns3_uninit_pf(eth_dev);
6843
6844 err_init_pf:
6845         rte_free(hw->reset.wait_data);
6846
6847 err_init_reset:
6848         hns3_mp_uninit_primary();
6849
6850 err_mp_init_primary:
6851 err_mp_init_secondary:
6852         eth_dev->dev_ops = NULL;
6853         eth_dev->rx_pkt_burst = NULL;
6854         eth_dev->rx_descriptor_status = NULL;
6855         eth_dev->tx_pkt_burst = NULL;
6856         eth_dev->tx_pkt_prepare = NULL;
6857         eth_dev->tx_descriptor_status = NULL;
6858         rte_free(eth_dev->process_private);
6859         eth_dev->process_private = NULL;
6860         return ret;
6861 }
6862
6863 static int
6864 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6865 {
6866         struct hns3_adapter *hns = eth_dev->data->dev_private;
6867         struct hns3_hw *hw = &hns->hw;
6868
6869         PMD_INIT_FUNC_TRACE();
6870
6871         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6872                 rte_free(eth_dev->process_private);
6873                 eth_dev->process_private = NULL;
6874                 return 0;
6875         }
6876
6877         if (hw->adapter_state < HNS3_NIC_CLOSING)
6878                 hns3_dev_close(eth_dev);
6879
6880         hw->adapter_state = HNS3_NIC_REMOVED;
6881         return 0;
6882 }
6883
6884 static int
6885 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6886                    struct rte_pci_device *pci_dev)
6887 {
6888         return rte_eth_dev_pci_generic_probe(pci_dev,
6889                                              sizeof(struct hns3_adapter),
6890                                              hns3_dev_init);
6891 }
6892
6893 static int
6894 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6895 {
6896         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6897 }
6898
6899 static const struct rte_pci_id pci_id_hns3_map[] = {
6900         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6901         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6902         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6903         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6904         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6905         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6906         { .vendor_id = 0, }, /* sentinel */
6907 };
6908
6909 static struct rte_pci_driver rte_hns3_pmd = {
6910         .id_table = pci_id_hns3_map,
6911         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6912         .probe = eth_hns3_pci_probe,
6913         .remove = eth_hns3_pci_remove,
6914 };
6915
6916 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6917 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6918 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6919 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6920                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6921                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6922 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6923 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);