1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
12 #include <rte_atomic.h>
13 #include <rte_bus_pci.h>
14 #include <rte_common.h>
15 #include <rte_cycles.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_interrupts.h>
26 #include "hns3_ethdev.h"
27 #include "hns3_logs.h"
28 #include "hns3_rxtx.h"
29 #include "hns3_intr.h"
30 #include "hns3_regs.h"
34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
38 #define HNS3_INVLID_PVID 0xFFFF
40 #define HNS3_FILTER_TYPE_VF 0
41 #define HNS3_FILTER_TYPE_PORT 1
42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
48 | HNS3_FILTER_FE_ROCE_EGRESS_B)
49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
50 | HNS3_FILTER_FE_ROCE_INGRESS_B)
52 /* Reset related Registers */
53 #define HNS3_GLOBAL_RESET_BIT 0
54 #define HNS3_CORE_RESET_BIT 1
55 #define HNS3_IMP_RESET_BIT 2
56 #define HNS3_FUN_RST_ING_B 0
58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
60 #define HNS3_RESET_WAIT_MS 100
61 #define HNS3_RESET_WAIT_CNT 200
64 HNS3_VECTOR0_EVENT_RST,
65 HNS3_VECTOR0_EVENT_MBX,
66 HNS3_VECTOR0_EVENT_ERR,
67 HNS3_VECTOR0_EVENT_OTHER,
70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
77 static int hns3_add_mc_addr(struct hns3_hw *hw,
78 struct rte_ether_addr *mac_addr);
79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
80 struct rte_ether_addr *mac_addr);
83 hns3_pf_disable_irq0(struct hns3_hw *hw)
85 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
89 hns3_pf_enable_irq0(struct hns3_hw *hw)
91 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
94 static enum hns3_evt_cause
95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
97 struct hns3_hw *hw = &hns->hw;
98 uint32_t vector0_int_stats;
99 uint32_t cmdq_src_val;
101 enum hns3_evt_cause ret;
103 /* fetch the events from their corresponding regs */
104 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
105 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
108 * Assumption: If by any chance reset and mailbox events are reported
109 * together then we will only process reset event and defer the
110 * processing of the mailbox events. Since, we would have not cleared
111 * RX CMDQ event this time we would receive again another interrupt
112 * from H/W just for the mailbox.
114 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
115 rte_atomic16_set(&hw->reset.disable_cmd, 1);
116 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
117 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
119 hw->reset.stats.imp_cnt++;
120 hns3_warn(hw, "IMP reset detected, clear reset status");
122 hns3_schedule_delayed_reset(hns);
123 hns3_warn(hw, "IMP reset detected, don't clear reset status");
126 ret = HNS3_VECTOR0_EVENT_RST;
131 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
132 rte_atomic16_set(&hw->reset.disable_cmd, 1);
133 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
134 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
136 hw->reset.stats.global_cnt++;
137 hns3_warn(hw, "Global reset detected, clear reset status");
139 hns3_schedule_delayed_reset(hns);
140 hns3_warn(hw, "Global reset detected, don't clear reset status");
143 ret = HNS3_VECTOR0_EVENT_RST;
147 /* check for vector0 msix event source */
148 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
149 val = vector0_int_stats;
150 ret = HNS3_VECTOR0_EVENT_ERR;
154 /* check for vector0 mailbox(=CMDQ RX) event source */
155 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
156 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
158 ret = HNS3_VECTOR0_EVENT_MBX;
162 if (clearval && (vector0_int_stats || cmdq_src_val))
163 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
164 vector0_int_stats, cmdq_src_val);
165 val = vector0_int_stats;
166 ret = HNS3_VECTOR0_EVENT_OTHER;
175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
177 if (event_type == HNS3_VECTOR0_EVENT_RST)
178 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
179 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
180 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
184 hns3_clear_all_event_cause(struct hns3_hw *hw)
186 uint32_t vector0_int_stats;
187 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
189 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
190 hns3_warn(hw, "Probe during IMP reset interrupt");
192 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
193 hns3_warn(hw, "Probe during Global reset interrupt");
195 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
196 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
197 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
198 BIT(HNS3_VECTOR0_CORERESET_INT_B));
199 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
203 hns3_interrupt_handler(void *param)
205 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
206 struct hns3_adapter *hns = dev->data->dev_private;
207 struct hns3_hw *hw = &hns->hw;
208 enum hns3_evt_cause event_cause;
209 uint32_t clearval = 0;
211 /* Disable interrupt */
212 hns3_pf_disable_irq0(hw);
214 event_cause = hns3_check_event_cause(hns, &clearval);
216 /* vector 0 interrupt is shared with reset and mailbox source events. */
217 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
218 hns3_handle_msix_error(hns, &hw->reset.request);
219 hns3_schedule_reset(hns);
220 } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
221 hns3_schedule_reset(hns);
222 else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
223 hns3_dev_handle_mbx_msg(hw);
225 hns3_err(hw, "Received unknown event");
227 hns3_clear_event_cause(hw, event_cause, clearval);
228 /* Enable interrupt if it is not cause by reset */
229 hns3_pf_enable_irq0(hw);
233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
235 #define HNS3_VLAN_ID_OFFSET_STEP 160
236 #define HNS3_VLAN_BYTE_SIZE 8
237 struct hns3_vlan_filter_pf_cfg_cmd *req;
238 struct hns3_hw *hw = &hns->hw;
239 uint8_t vlan_offset_byte_val;
240 struct hns3_cmd_desc desc;
241 uint8_t vlan_offset_byte;
242 uint8_t vlan_offset_base;
245 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
247 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
248 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
250 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
252 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
253 req->vlan_offset = vlan_offset_base;
254 req->vlan_cfg = on ? 0 : 1;
255 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
257 ret = hns3_cmd_send(hw, &desc, 1);
259 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
268 struct hns3_user_vlan_table *vlan_entry;
269 struct hns3_pf *pf = &hns->pf;
271 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
272 if (vlan_entry->vlan_id == vlan_id) {
273 if (vlan_entry->hd_tbl_status)
274 hns3_set_port_vlan_filter(hns, vlan_id, 0);
275 LIST_REMOVE(vlan_entry, next);
276 rte_free(vlan_entry);
283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
286 struct hns3_user_vlan_table *vlan_entry;
287 struct hns3_hw *hw = &hns->hw;
288 struct hns3_pf *pf = &hns->pf;
290 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
291 if (vlan_entry->vlan_id == vlan_id)
295 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
296 if (vlan_entry == NULL) {
297 hns3_err(hw, "Failed to malloc hns3 vlan table");
301 vlan_entry->hd_tbl_status = writen_to_tbl;
302 vlan_entry->vlan_id = vlan_id;
304 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
308 hns3_restore_vlan_table(struct hns3_adapter *hns)
310 struct hns3_user_vlan_table *vlan_entry;
311 struct hns3_hw *hw = &hns->hw;
312 struct hns3_pf *pf = &hns->pf;
316 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
317 return hns3_vlan_pvid_configure(hns,
318 hw->port_base_vlan_cfg.pvid, 1);
320 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
321 if (vlan_entry->hd_tbl_status) {
322 vlan_id = vlan_entry->vlan_id;
323 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
335 struct hns3_hw *hw = &hns->hw;
336 bool writen_to_tbl = false;
340 * When vlan filter is enabled, hardware regards vlan id 0 as the entry
341 * for normal packet, deleting vlan id 0 is not allowed.
343 if (on == 0 && vlan_id == 0)
347 * When port base vlan enabled, we use port base vlan as the vlan
348 * filter condition. In this case, we don't update vlan filter table
349 * when user add new vlan or remove exist vlan, just update the
350 * vlan list. The vlan id in vlan list will be writen in vlan filter
351 * table until port base vlan disabled
353 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
354 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
355 writen_to_tbl = true;
358 if (ret == 0 && vlan_id) {
360 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
362 hns3_rm_dev_vlan_table(hns, vlan_id);
368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
370 struct hns3_adapter *hns = dev->data->dev_private;
371 struct hns3_hw *hw = &hns->hw;
374 rte_spinlock_lock(&hw->lock);
375 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
376 rte_spinlock_unlock(&hw->lock);
381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
384 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
385 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
386 struct hns3_hw *hw = &hns->hw;
387 struct hns3_cmd_desc desc;
390 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
391 vlan_type != ETH_VLAN_TYPE_OUTER)) {
392 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
396 if (tpid != RTE_ETHER_TYPE_VLAN) {
397 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
401 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
402 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
404 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
405 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
406 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
407 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
408 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
409 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
410 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
411 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
414 ret = hns3_cmd_send(hw, &desc, 1);
416 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
421 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
423 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
424 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
425 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
427 ret = hns3_cmd_send(hw, &desc, 1);
429 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
438 struct hns3_adapter *hns = dev->data->dev_private;
439 struct hns3_hw *hw = &hns->hw;
442 rte_spinlock_lock(&hw->lock);
443 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
444 rte_spinlock_unlock(&hw->lock);
449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
450 struct hns3_rx_vtag_cfg *vcfg)
452 struct hns3_vport_vtag_rx_cfg_cmd *req;
453 struct hns3_hw *hw = &hns->hw;
454 struct hns3_cmd_desc desc;
459 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
461 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
462 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
463 vcfg->strip_tag1_en ? 1 : 0);
464 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
465 vcfg->strip_tag2_en ? 1 : 0);
466 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
467 vcfg->vlan1_vlan_prionly ? 1 : 0);
468 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
469 vcfg->vlan2_vlan_prionly ? 1 : 0);
472 * In current version VF is not supported when PF is driven by DPDK
473 * driver, just need to configure parameters for PF vport.
475 vport_id = HNS3_PF_FUNC_ID;
476 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
477 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
478 req->vf_bitmap[req->vf_offset] = bitmap;
480 ret = hns3_cmd_send(hw, &desc, 1);
482 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
488 struct hns3_rx_vtag_cfg *vcfg)
490 struct hns3_pf *pf = &hns->pf;
491 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
496 struct hns3_tx_vtag_cfg *vcfg)
498 struct hns3_pf *pf = &hns->pf;
499 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
505 struct hns3_rx_vtag_cfg rxvlan_cfg;
506 struct hns3_hw *hw = &hns->hw;
509 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
510 rxvlan_cfg.strip_tag1_en = false;
511 rxvlan_cfg.strip_tag2_en = enable;
513 rxvlan_cfg.strip_tag1_en = enable;
514 rxvlan_cfg.strip_tag2_en = true;
517 rxvlan_cfg.vlan1_vlan_prionly = false;
518 rxvlan_cfg.vlan2_vlan_prionly = false;
519 rxvlan_cfg.rx_vlan_offload_en = enable;
521 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
523 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
527 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
534 uint8_t fe_type, bool filter_en, uint8_t vf_id)
536 struct hns3_vlan_filter_ctrl_cmd *req;
537 struct hns3_cmd_desc desc;
540 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
542 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
543 req->vlan_type = vlan_type;
544 req->vlan_fe = filter_en ? fe_type : 0;
547 ret = hns3_cmd_send(hw, &desc, 1);
549 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
555 hns3_vlan_filter_init(struct hns3_adapter *hns)
557 struct hns3_hw *hw = &hns->hw;
560 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
561 HNS3_FILTER_FE_EGRESS, false,
564 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
568 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
569 HNS3_FILTER_FE_INGRESS, false,
572 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
580 struct hns3_hw *hw = &hns->hw;
583 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
584 HNS3_FILTER_FE_INGRESS, enable,
587 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
588 enable ? "enable" : "disable", ret);
594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
596 struct hns3_adapter *hns = dev->data->dev_private;
597 struct hns3_hw *hw = &hns->hw;
598 struct rte_eth_rxmode *rxmode;
599 unsigned int tmp_mask;
603 rte_spinlock_lock(&hw->lock);
604 rxmode = &dev->data->dev_conf.rxmode;
605 tmp_mask = (unsigned int)mask;
606 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
607 /* ignore vlan filter configuration during promiscuous mode */
608 if (!dev->data->promiscuous) {
609 /* Enable or disable VLAN filter */
610 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
613 ret = hns3_enable_vlan_filter(hns, enable);
615 rte_spinlock_unlock(&hw->lock);
616 hns3_err(hw, "failed to %s rx filter, ret = %d",
617 enable ? "enable" : "disable", ret);
623 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
624 /* Enable or disable VLAN stripping */
625 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
628 ret = hns3_en_hw_strip_rxvtag(hns, enable);
630 rte_spinlock_unlock(&hw->lock);
631 hns3_err(hw, "failed to %s rx strip, ret = %d",
632 enable ? "enable" : "disable", ret);
637 rte_spinlock_unlock(&hw->lock);
643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
644 struct hns3_tx_vtag_cfg *vcfg)
646 struct hns3_vport_vtag_tx_cfg_cmd *req;
647 struct hns3_cmd_desc desc;
648 struct hns3_hw *hw = &hns->hw;
653 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
655 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
656 req->def_vlan_tag1 = vcfg->default_tag1;
657 req->def_vlan_tag2 = vcfg->default_tag2;
658 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
659 vcfg->accept_tag1 ? 1 : 0);
660 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
661 vcfg->accept_untag1 ? 1 : 0);
662 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
663 vcfg->accept_tag2 ? 1 : 0);
664 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
665 vcfg->accept_untag2 ? 1 : 0);
666 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
667 vcfg->insert_tag1_en ? 1 : 0);
668 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
669 vcfg->insert_tag2_en ? 1 : 0);
670 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
673 * In current version VF is not supported when PF is driven by DPDK
674 * driver, just need to configure parameters for PF vport.
676 vport_id = HNS3_PF_FUNC_ID;
677 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
678 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
679 req->vf_bitmap[req->vf_offset] = bitmap;
681 ret = hns3_cmd_send(hw, &desc, 1);
683 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
692 struct hns3_hw *hw = &hns->hw;
693 struct hns3_tx_vtag_cfg txvlan_cfg;
696 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
697 txvlan_cfg.accept_tag1 = true;
698 txvlan_cfg.insert_tag1_en = false;
699 txvlan_cfg.default_tag1 = 0;
701 txvlan_cfg.accept_tag1 = false;
702 txvlan_cfg.insert_tag1_en = true;
703 txvlan_cfg.default_tag1 = pvid;
706 txvlan_cfg.accept_untag1 = true;
707 txvlan_cfg.accept_tag2 = true;
708 txvlan_cfg.accept_untag2 = true;
709 txvlan_cfg.insert_tag2_en = false;
710 txvlan_cfg.default_tag2 = 0;
712 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
714 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
719 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
726 struct hns3_hw *hw = &hns->hw;
728 hw->port_base_vlan_cfg.state = on ?
729 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
731 hw->port_base_vlan_cfg.pvid = pvid;
735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
737 struct hns3_user_vlan_table *vlan_entry;
738 struct hns3_pf *pf = &hns->pf;
740 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
741 if (vlan_entry->hd_tbl_status)
742 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
744 vlan_entry->hd_tbl_status = false;
748 vlan_entry = LIST_FIRST(&pf->vlan_list);
750 LIST_REMOVE(vlan_entry, next);
751 rte_free(vlan_entry);
752 vlan_entry = LIST_FIRST(&pf->vlan_list);
758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
760 struct hns3_user_vlan_table *vlan_entry;
761 struct hns3_pf *pf = &hns->pf;
763 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
764 if (!vlan_entry->hd_tbl_status)
765 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
767 vlan_entry->hd_tbl_status = true;
772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
774 struct hns3_hw *hw = &hns->hw;
777 hns3_rm_all_vlan_table(hns, true);
778 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
779 ret = hns3_set_port_vlan_filter(hns,
780 hw->port_base_vlan_cfg.pvid, 0);
782 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
791 uint16_t port_base_vlan_state,
792 uint16_t new_pvid, uint16_t old_pvid)
794 struct hns3_hw *hw = &hns->hw;
797 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
798 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
799 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
802 "Failed to clear clear old pvid filter, ret =%d",
808 hns3_rm_all_vlan_table(hns, false);
809 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
813 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
815 hns3_err(hw, "Failed to set port vlan filter, ret =%d",
821 if (new_pvid == hw->port_base_vlan_cfg.pvid)
822 hns3_add_all_vlan_table(hns);
828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
830 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
831 struct hns3_rx_vtag_cfg rx_vlan_cfg;
835 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
837 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
838 rx_vlan_cfg.strip_tag2_en = true;
840 rx_vlan_cfg.strip_tag1_en = false;
841 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
843 rx_vlan_cfg.vlan1_vlan_prionly = false;
844 rx_vlan_cfg.vlan2_vlan_prionly = false;
845 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
847 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
851 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
858 struct hns3_hw *hw = &hns->hw;
859 uint16_t port_base_vlan_state;
863 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
864 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
865 hns3_warn(hw, "Invalid operation! As current pvid set "
866 "is %u, disable pvid %u is invalid",
867 hw->port_base_vlan_cfg.pvid, pvid);
871 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
872 HNS3_PORT_BASE_VLAN_DISABLE;
873 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
875 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
880 ret = hns3_en_pvid_strip(hns, on);
882 hns3_err(hw, "failed to config rx vlan strip for pvid, "
887 if (pvid == HNS3_INVLID_PVID)
889 old_pvid = hw->port_base_vlan_cfg.pvid;
890 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
893 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
899 hns3_store_port_base_vlan_info(hns, pvid, on);
904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
906 struct hns3_adapter *hns = dev->data->dev_private;
907 struct hns3_hw *hw = &hns->hw;
908 bool pvid_en_state_change;
912 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
913 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
914 RTE_ETHER_MAX_VLAN_ID);
919 * If PVID configuration state change, should refresh the PVID
920 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
922 pvid_state = hw->port_base_vlan_cfg.state;
923 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
924 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
925 pvid_en_state_change = false;
927 pvid_en_state_change = true;
929 rte_spinlock_lock(&hw->lock);
930 ret = hns3_vlan_pvid_configure(hns, pvid, on);
931 rte_spinlock_unlock(&hw->lock);
935 if (pvid_en_state_change)
936 hns3_update_all_queues_pvid_state(hw);
942 init_port_base_vlan_info(struct hns3_hw *hw)
944 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
945 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
949 hns3_default_vlan_config(struct hns3_adapter *hns)
951 struct hns3_hw *hw = &hns->hw;
954 ret = hns3_set_port_vlan_filter(hns, 0, 1);
956 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
961 hns3_init_vlan_config(struct hns3_adapter *hns)
963 struct hns3_hw *hw = &hns->hw;
967 * This function can be called in the initialization and reset process,
968 * when in reset process, it means that hardware had been reseted
969 * successfully and we need to restore the hardware configuration to
970 * ensure that the hardware configuration remains unchanged before and
973 if (rte_atomic16_read(&hw->reset.resetting) == 0)
974 init_port_base_vlan_info(hw);
976 ret = hns3_vlan_filter_init(hns);
978 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
982 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
983 RTE_ETHER_TYPE_VLAN);
985 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
990 * When in the reinit dev stage of the reset process, the following
991 * vlan-related configurations may differ from those at initialization,
992 * we will restore configurations to hardware in hns3_restore_vlan_table
993 * and hns3_restore_vlan_conf later.
995 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
996 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
998 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1002 ret = hns3_en_hw_strip_rxvtag(hns, false);
1004 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1010 return hns3_default_vlan_config(hns);
1014 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1016 struct hns3_pf *pf = &hns->pf;
1017 struct hns3_hw *hw = &hns->hw;
1022 if (!hw->data->promiscuous) {
1023 /* restore vlan filter states */
1024 offloads = hw->data->dev_conf.rxmode.offloads;
1025 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1026 ret = hns3_enable_vlan_filter(hns, enable);
1028 hns3_err(hw, "failed to restore vlan rx filter conf, "
1034 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1036 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1040 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1042 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1048 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1050 struct hns3_adapter *hns = dev->data->dev_private;
1051 struct rte_eth_dev_data *data = dev->data;
1052 struct rte_eth_txmode *txmode;
1053 struct hns3_hw *hw = &hns->hw;
1057 txmode = &data->dev_conf.txmode;
1058 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1060 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1061 "configuration is not supported! Ignore these two "
1062 "parameters: hw_vlan_reject_tagged(%d), "
1063 "hw_vlan_reject_untagged(%d)",
1064 txmode->hw_vlan_reject_tagged,
1065 txmode->hw_vlan_reject_untagged);
1067 /* Apply vlan offload setting */
1068 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1069 ret = hns3_vlan_offload_set(dev, mask);
1071 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1077 * If pvid config is not set in rte_eth_conf, driver needn't to set
1078 * VLAN pvid related configuration to hardware.
1080 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1083 /* Apply pvid setting */
1084 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1085 txmode->hw_vlan_insert_pvid);
1087 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1094 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1095 unsigned int tso_mss_max)
1097 struct hns3_cfg_tso_status_cmd *req;
1098 struct hns3_cmd_desc desc;
1101 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1103 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1106 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1108 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1111 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1113 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1115 return hns3_cmd_send(hw, &desc, 1);
1119 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1120 uint16_t *allocated_size, bool is_alloc)
1122 struct hns3_umv_spc_alc_cmd *req;
1123 struct hns3_cmd_desc desc;
1126 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1127 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1128 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1129 req->space_size = rte_cpu_to_le_32(space_size);
1131 ret = hns3_cmd_send(hw, &desc, 1);
1133 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1134 is_alloc ? "allocate" : "free", ret);
1138 if (is_alloc && allocated_size)
1139 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1145 hns3_init_umv_space(struct hns3_hw *hw)
1147 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1148 struct hns3_pf *pf = &hns->pf;
1149 uint16_t allocated_size = 0;
1152 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1157 if (allocated_size < pf->wanted_umv_size)
1158 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1159 pf->wanted_umv_size, allocated_size);
1161 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1162 pf->wanted_umv_size;
1163 pf->used_umv_size = 0;
1168 hns3_uninit_umv_space(struct hns3_hw *hw)
1170 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171 struct hns3_pf *pf = &hns->pf;
1174 if (pf->max_umv_size == 0)
1177 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1181 pf->max_umv_size = 0;
1187 hns3_is_umv_space_full(struct hns3_hw *hw)
1189 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1190 struct hns3_pf *pf = &hns->pf;
1193 is_full = (pf->used_umv_size >= pf->max_umv_size);
1199 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1201 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1202 struct hns3_pf *pf = &hns->pf;
1205 if (pf->used_umv_size > 0)
1206 pf->used_umv_size--;
1208 pf->used_umv_size++;
1212 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1213 const uint8_t *addr, bool is_mc)
1215 const unsigned char *mac_addr = addr;
1216 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1217 ((uint32_t)mac_addr[2] << 16) |
1218 ((uint32_t)mac_addr[1] << 8) |
1219 (uint32_t)mac_addr[0];
1220 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1222 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1224 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1225 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1226 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1229 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1230 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1234 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1236 enum hns3_mac_vlan_tbl_opcode op)
1239 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1244 if (op == HNS3_MAC_VLAN_ADD) {
1245 if (resp_code == 0 || resp_code == 1) {
1247 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1248 hns3_err(hw, "add mac addr failed for uc_overflow");
1250 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1251 hns3_err(hw, "add mac addr failed for mc_overflow");
1255 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1258 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1259 if (resp_code == 0) {
1261 } else if (resp_code == 1) {
1262 hns3_dbg(hw, "remove mac addr failed for miss");
1266 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1269 } else if (op == HNS3_MAC_VLAN_LKUP) {
1270 if (resp_code == 0) {
1272 } else if (resp_code == 1) {
1273 hns3_dbg(hw, "lookup mac addr failed for miss");
1277 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1282 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1289 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1290 struct hns3_mac_vlan_tbl_entry_cmd *req,
1291 struct hns3_cmd_desc *desc, bool is_mc)
1297 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1299 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1300 memcpy(desc[0].data, req,
1301 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1302 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1304 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1305 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1307 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1309 memcpy(desc[0].data, req,
1310 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1311 ret = hns3_cmd_send(hw, desc, 1);
1314 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1318 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1319 retval = rte_le_to_cpu_16(desc[0].retval);
1321 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1322 HNS3_MAC_VLAN_LKUP);
1326 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1327 struct hns3_mac_vlan_tbl_entry_cmd *req,
1328 struct hns3_cmd_desc *mc_desc)
1335 if (mc_desc == NULL) {
1336 struct hns3_cmd_desc desc;
1338 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1339 memcpy(desc.data, req,
1340 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1341 ret = hns3_cmd_send(hw, &desc, 1);
1342 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1343 retval = rte_le_to_cpu_16(desc.retval);
1345 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1348 hns3_cmd_reuse_desc(&mc_desc[0], false);
1349 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350 hns3_cmd_reuse_desc(&mc_desc[1], false);
1351 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1352 hns3_cmd_reuse_desc(&mc_desc[2], false);
1353 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1354 memcpy(mc_desc[0].data, req,
1355 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1356 mc_desc[0].retval = 0;
1357 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1358 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1359 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1361 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1366 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1374 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1375 struct hns3_mac_vlan_tbl_entry_cmd *req)
1377 struct hns3_cmd_desc desc;
1382 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1384 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1386 ret = hns3_cmd_send(hw, &desc, 1);
1388 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1391 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1392 retval = rte_le_to_cpu_16(desc.retval);
1394 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1395 HNS3_MAC_VLAN_REMOVE);
1399 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1401 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1402 struct hns3_mac_vlan_tbl_entry_cmd req;
1403 struct hns3_pf *pf = &hns->pf;
1404 struct hns3_cmd_desc desc;
1405 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1406 uint16_t egress_port = 0;
1410 /* check if mac addr is valid */
1411 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1412 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1414 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1419 memset(&req, 0, sizeof(req));
1422 * In current version VF is not supported when PF is driven by DPDK
1423 * driver, just need to configure parameters for PF vport.
1425 vf_id = HNS3_PF_FUNC_ID;
1426 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1427 HNS3_MAC_EPORT_VFID_S, vf_id);
1429 req.egress_port = rte_cpu_to_le_16(egress_port);
1431 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1434 * Lookup the mac address in the mac_vlan table, and add
1435 * it if the entry is inexistent. Repeated unicast entry
1436 * is not allowed in the mac vlan table.
1438 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1439 if (ret == -ENOENT) {
1440 if (!hns3_is_umv_space_full(hw)) {
1441 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1443 hns3_update_umv_space(hw, false);
1447 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1452 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1454 /* check if we just hit the duplicate */
1456 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1460 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1467 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1469 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1470 struct rte_ether_addr *addr;
1474 for (i = 0; i < hw->mc_addrs_num; i++) {
1475 addr = &hw->mc_addrs[i];
1476 /* Check if there are duplicate addresses */
1477 if (rte_is_same_ether_addr(addr, mac_addr)) {
1478 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1480 hns3_err(hw, "failed to add mc mac addr, same addrs"
1481 "(%s) is added by the set_mc_mac_addr_list "
1487 ret = hns3_add_mc_addr(hw, mac_addr);
1489 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1491 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1498 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1500 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1503 ret = hns3_remove_mc_addr(hw, mac_addr);
1505 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1507 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1514 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1515 uint32_t idx, __rte_unused uint32_t pool)
1517 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1521 rte_spinlock_lock(&hw->lock);
1524 * In hns3 network engine adding UC and MC mac address with different
1525 * commands with firmware. We need to determine whether the input
1526 * address is a UC or a MC address to call different commands.
1527 * By the way, it is recommended calling the API function named
1528 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1529 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1530 * may affect the specifications of UC mac addresses.
1532 if (rte_is_multicast_ether_addr(mac_addr))
1533 ret = hns3_add_mc_addr_common(hw, mac_addr);
1535 ret = hns3_add_uc_addr_common(hw, mac_addr);
1538 rte_spinlock_unlock(&hw->lock);
1539 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1541 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1547 hw->mac.default_addr_setted = true;
1548 rte_spinlock_unlock(&hw->lock);
1554 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1556 struct hns3_mac_vlan_tbl_entry_cmd req;
1557 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1560 /* check if mac addr is valid */
1561 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1562 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1564 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1569 memset(&req, 0, sizeof(req));
1570 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1571 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1573 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1576 hns3_update_umv_space(hw, true);
1582 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1584 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585 /* index will be checked by upper level rte interface */
1586 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1587 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1590 rte_spinlock_lock(&hw->lock);
1592 if (rte_is_multicast_ether_addr(mac_addr))
1593 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1595 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1596 rte_spinlock_unlock(&hw->lock);
1598 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1600 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1606 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1607 struct rte_ether_addr *mac_addr)
1609 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610 struct rte_ether_addr *oaddr;
1611 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1612 bool default_addr_setted;
1613 bool rm_succes = false;
1617 * It has been guaranteed that input parameter named mac_addr is valid
1618 * address in the rte layer of DPDK framework.
1620 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1621 default_addr_setted = hw->mac.default_addr_setted;
1622 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1625 rte_spinlock_lock(&hw->lock);
1626 if (default_addr_setted) {
1627 ret = hns3_remove_uc_addr_common(hw, oaddr);
1629 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1638 ret = hns3_add_uc_addr_common(hw, mac_addr);
1640 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1642 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1643 goto err_add_uc_addr;
1646 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1648 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1649 goto err_pause_addr_cfg;
1652 rte_ether_addr_copy(mac_addr,
1653 (struct rte_ether_addr *)hw->mac.mac_addr);
1654 hw->mac.default_addr_setted = true;
1655 rte_spinlock_unlock(&hw->lock);
1660 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1662 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1665 "Failed to roll back to del setted mac addr(%s): %d",
1671 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1673 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1676 "Failed to restore old uc mac addr(%s): %d",
1678 hw->mac.default_addr_setted = false;
1681 rte_spinlock_unlock(&hw->lock);
1687 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1689 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1690 struct hns3_hw *hw = &hns->hw;
1691 struct rte_ether_addr *addr;
1696 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1697 addr = &hw->data->mac_addrs[i];
1698 if (rte_is_zero_ether_addr(addr))
1700 if (rte_is_multicast_ether_addr(addr))
1701 ret = del ? hns3_remove_mc_addr(hw, addr) :
1702 hns3_add_mc_addr(hw, addr);
1704 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1705 hns3_add_uc_addr_common(hw, addr);
1709 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1711 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1712 "ret = %d.", del ? "remove" : "restore",
1720 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1722 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1726 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1727 word_num = vfid / 32;
1728 bit_num = vfid % 32;
1730 desc[1].data[word_num] &=
1731 rte_cpu_to_le_32(~(1UL << bit_num));
1733 desc[1].data[word_num] |=
1734 rte_cpu_to_le_32(1UL << bit_num);
1736 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1737 bit_num = vfid % 32;
1739 desc[2].data[word_num] &=
1740 rte_cpu_to_le_32(~(1UL << bit_num));
1742 desc[2].data[word_num] |=
1743 rte_cpu_to_le_32(1UL << bit_num);
1748 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1750 struct hns3_mac_vlan_tbl_entry_cmd req;
1751 struct hns3_cmd_desc desc[3];
1752 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1756 /* Check if mac addr is valid */
1757 if (!rte_is_multicast_ether_addr(mac_addr)) {
1758 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1760 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1765 memset(&req, 0, sizeof(req));
1766 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1767 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1768 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1770 /* This mac addr do not exist, add new entry for it */
1771 memset(desc[0].data, 0, sizeof(desc[0].data));
1772 memset(desc[1].data, 0, sizeof(desc[0].data));
1773 memset(desc[2].data, 0, sizeof(desc[0].data));
1777 * In current version VF is not supported when PF is driven by DPDK
1778 * driver, just need to configure parameters for PF vport.
1780 vf_id = HNS3_PF_FUNC_ID;
1781 hns3_update_desc_vfid(desc, vf_id, false);
1782 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1785 hns3_err(hw, "mc mac vlan table is full");
1786 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1788 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1797 struct hns3_mac_vlan_tbl_entry_cmd req;
1798 struct hns3_cmd_desc desc[3];
1799 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1803 /* Check if mac addr is valid */
1804 if (!rte_is_multicast_ether_addr(mac_addr)) {
1805 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1807 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1812 memset(&req, 0, sizeof(req));
1813 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1818 * This mac addr exist, remove this handle's VFID for it.
1819 * In current version VF is not supported when PF is driven by
1820 * DPDK driver, just need to configure parameters for PF vport.
1822 vf_id = HNS3_PF_FUNC_ID;
1823 hns3_update_desc_vfid(desc, vf_id, true);
1825 /* All the vfid is zero, so need to delete this entry */
1826 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1827 } else if (ret == -ENOENT) {
1828 /* This mac addr doesn't exist. */
1833 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1835 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1842 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1843 struct rte_ether_addr *mc_addr_set,
1844 uint32_t nb_mc_addr)
1846 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1847 struct rte_ether_addr *addr;
1851 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1852 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1853 "invalid. valid range: 0~%d",
1854 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1858 /* Check if input mac addresses are valid */
1859 for (i = 0; i < nb_mc_addr; i++) {
1860 addr = &mc_addr_set[i];
1861 if (!rte_is_multicast_ether_addr(addr)) {
1862 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1865 "failed to set mc mac addr, addr(%s) invalid.",
1870 /* Check if there are duplicate addresses */
1871 for (j = i + 1; j < nb_mc_addr; j++) {
1872 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1873 rte_ether_format_addr(mac_str,
1874 RTE_ETHER_ADDR_FMT_SIZE,
1876 hns3_err(hw, "failed to set mc mac addr, "
1877 "addrs invalid. two same addrs(%s).",
1884 * Check if there are duplicate addresses between mac_addrs
1887 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1888 if (rte_is_same_ether_addr(addr,
1889 &hw->data->mac_addrs[j])) {
1890 rte_ether_format_addr(mac_str,
1891 RTE_ETHER_ADDR_FMT_SIZE,
1893 hns3_err(hw, "failed to set mc mac addr, "
1894 "addrs invalid. addrs(%s) has already "
1895 "configured in mac_addr add API",
1906 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1907 struct rte_ether_addr *mc_addr_set,
1909 struct rte_ether_addr *reserved_addr_list,
1910 int *reserved_addr_num,
1911 struct rte_ether_addr *add_addr_list,
1913 struct rte_ether_addr *rm_addr_list,
1916 struct rte_ether_addr *addr;
1917 int current_addr_num;
1918 int reserved_num = 0;
1926 /* Calculate the mc mac address list that should be removed */
1927 current_addr_num = hw->mc_addrs_num;
1928 for (i = 0; i < current_addr_num; i++) {
1929 addr = &hw->mc_addrs[i];
1931 for (j = 0; j < mc_addr_num; j++) {
1932 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1939 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1942 rte_ether_addr_copy(addr,
1943 &reserved_addr_list[reserved_num]);
1948 /* Calculate the mc mac address list that should be added */
1949 for (i = 0; i < mc_addr_num; i++) {
1950 addr = &mc_addr_set[i];
1952 for (j = 0; j < current_addr_num; j++) {
1953 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1960 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1965 /* Reorder the mc mac address list maintained by driver */
1966 for (i = 0; i < reserved_num; i++)
1967 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1969 for (i = 0; i < rm_num; i++) {
1970 num = reserved_num + i;
1971 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1974 *reserved_addr_num = reserved_num;
1975 *add_addr_num = add_num;
1976 *rm_addr_num = rm_num;
1980 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1981 struct rte_ether_addr *mc_addr_set,
1982 uint32_t nb_mc_addr)
1984 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1986 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1987 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1988 struct rte_ether_addr *addr;
1989 int reserved_addr_num;
1997 /* Check if input parameters are valid */
1998 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2002 rte_spinlock_lock(&hw->lock);
2005 * Calculate the mc mac address lists those should be removed and be
2006 * added, Reorder the mc mac address list maintained by driver.
2008 mc_addr_num = (int)nb_mc_addr;
2009 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2010 reserved_addr_list, &reserved_addr_num,
2011 add_addr_list, &add_addr_num,
2012 rm_addr_list, &rm_addr_num);
2014 /* Remove mc mac addresses */
2015 for (i = 0; i < rm_addr_num; i++) {
2016 num = rm_addr_num - i - 1;
2017 addr = &rm_addr_list[num];
2018 ret = hns3_remove_mc_addr(hw, addr);
2020 rte_spinlock_unlock(&hw->lock);
2026 /* Add mc mac addresses */
2027 for (i = 0; i < add_addr_num; i++) {
2028 addr = &add_addr_list[i];
2029 ret = hns3_add_mc_addr(hw, addr);
2031 rte_spinlock_unlock(&hw->lock);
2035 num = reserved_addr_num + i;
2036 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2039 rte_spinlock_unlock(&hw->lock);
2045 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2047 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2048 struct hns3_hw *hw = &hns->hw;
2049 struct rte_ether_addr *addr;
2054 for (i = 0; i < hw->mc_addrs_num; i++) {
2055 addr = &hw->mc_addrs[i];
2056 if (!rte_is_multicast_ether_addr(addr))
2059 ret = hns3_remove_mc_addr(hw, addr);
2061 ret = hns3_add_mc_addr(hw, addr);
2064 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2066 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2067 del ? "Remove" : "Restore", mac_str, ret);
2074 hns3_check_mq_mode(struct rte_eth_dev *dev)
2076 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2077 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2078 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2080 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2081 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2086 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2087 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2089 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2091 "rx_mq_mode = %d", rx_mq_mode);
2095 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2096 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2097 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2098 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2099 rx_mq_mode, tx_mq_mode);
2103 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2104 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2105 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2106 dcb_rx_conf->nb_tcs, pf->tc_max);
2110 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2111 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2112 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2113 "nb_tcs(%d) != %d or %d in rx direction.",
2114 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2118 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2119 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2120 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2124 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2125 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2126 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2127 "is not equal to one in tx direction.",
2128 i, dcb_rx_conf->dcb_tc[i]);
2131 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2132 max_tc = dcb_rx_conf->dcb_tc[i];
2135 num_tc = max_tc + 1;
2136 if (num_tc > dcb_rx_conf->nb_tcs) {
2137 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2138 num_tc, dcb_rx_conf->nb_tcs);
2147 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2149 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151 if (!hns3_dev_dcb_supported(hw)) {
2152 hns3_err(hw, "this port does not support dcb configurations.");
2156 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2157 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2161 /* Check multiple queue mode */
2162 return hns3_check_mq_mode(dev);
2166 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2167 enum hns3_ring_type queue_type, uint16_t queue_id)
2169 struct hns3_cmd_desc desc;
2170 struct hns3_ctrl_vector_chain_cmd *req =
2171 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2172 enum hns3_cmd_status status;
2173 enum hns3_opcode_type op;
2174 uint16_t tqp_type_and_id = 0;
2179 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2180 hns3_cmd_setup_basic_desc(&desc, op, false);
2181 req->int_vector_id = vector_id;
2183 if (queue_type == HNS3_RING_TYPE_RX)
2184 gl = HNS3_RING_GL_RX;
2186 gl = HNS3_RING_GL_TX;
2190 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2192 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2193 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2195 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2196 req->int_cause_num = 1;
2197 op_str = mmap ? "Map" : "Unmap";
2198 status = hns3_cmd_send(hw, &desc, 1);
2200 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2201 op_str, queue_id, req->int_vector_id, status);
2209 hns3_init_ring_with_vector(struct hns3_hw *hw)
2216 * In hns3 network engine, vector 0 is always the misc interrupt of this
2217 * function, vector 1~N can be used respectively for the queues of the
2218 * function. Tx and Rx queues with the same number share the interrupt
2219 * vector. In the initialization clearing the all hardware mapping
2220 * relationship configurations between queues and interrupt vectors is
2221 * needed, so some error caused by the residual configurations, such as
2222 * the unexpected Tx interrupt, can be avoid.
2224 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2225 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2226 vec = vec - 1; /* the last interrupt is reserved */
2227 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2228 for (i = 0; i < hw->intr_tqps_num; i++) {
2230 * Set gap limiter/rate limiter/quanity limiter algorithm
2231 * configuration for interrupt coalesce of queue's interrupt.
2233 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2234 HNS3_TQP_INTR_GL_DEFAULT);
2235 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2236 HNS3_TQP_INTR_GL_DEFAULT);
2237 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2238 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2240 ret = hns3_bind_ring_with_vector(hw, vec, false,
2241 HNS3_RING_TYPE_TX, i);
2243 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2244 "vector: %d, ret=%d", i, vec, ret);
2248 ret = hns3_bind_ring_with_vector(hw, vec, false,
2249 HNS3_RING_TYPE_RX, i);
2251 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2252 "vector: %d, ret=%d", i, vec, ret);
2261 hns3_dev_configure(struct rte_eth_dev *dev)
2263 struct hns3_adapter *hns = dev->data->dev_private;
2264 struct rte_eth_conf *conf = &dev->data->dev_conf;
2265 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2266 struct hns3_hw *hw = &hns->hw;
2267 struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2268 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2269 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2270 struct rte_eth_rss_conf rss_conf;
2276 * Hardware does not support individually enable/disable/reset the Tx or
2277 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2278 * and Rx queues at the same time. When the numbers of Tx queues
2279 * allocated by upper applications are not equal to the numbers of Rx
2280 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2281 * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2282 * these fake queues are imperceptible, and can not be used by upper
2285 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2287 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2291 hw->adapter_state = HNS3_NIC_CONFIGURING;
2292 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2293 hns3_err(hw, "setting link speed/duplex not supported");
2298 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2299 ret = hns3_check_dcb_cfg(dev);
2304 /* When RSS is not configured, redirect the packet queue 0 */
2305 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2306 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2307 rss_conf = conf->rx_adv_conf.rss_conf;
2308 if (rss_conf.rss_key == NULL) {
2309 rss_conf.rss_key = rss_cfg->key;
2310 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2313 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2319 * If jumbo frames are enabled, MTU needs to be refreshed
2320 * according to the maximum RX packet length.
2322 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2324 * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2325 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2326 * can safely assign to "uint16_t" type variable.
2328 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2329 ret = hns3_dev_mtu_set(dev, mtu);
2332 dev->data->mtu = mtu;
2335 ret = hns3_dev_configure_vlan(dev);
2339 /* config hardware GRO */
2340 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2341 ret = hns3_config_gro(hw, gro_en);
2345 hw->adapter_state = HNS3_NIC_CONFIGURED;
2350 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2351 hw->adapter_state = HNS3_NIC_INITIALIZED;
2357 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2359 struct hns3_config_max_frm_size_cmd *req;
2360 struct hns3_cmd_desc desc;
2362 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2364 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2365 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2366 req->min_frm_size = RTE_ETHER_MIN_LEN;
2368 return hns3_cmd_send(hw, &desc, 1);
2372 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2376 ret = hns3_set_mac_mtu(hw, mps);
2378 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2382 ret = hns3_buffer_alloc(hw);
2384 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2390 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2392 struct hns3_adapter *hns = dev->data->dev_private;
2393 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2394 struct hns3_hw *hw = &hns->hw;
2395 bool is_jumbo_frame;
2398 if (dev->data->dev_started) {
2399 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2400 "before configuration", dev->data->port_id);
2404 rte_spinlock_lock(&hw->lock);
2405 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2406 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2409 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2410 * assign to "uint16_t" type variable.
2412 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2414 rte_spinlock_unlock(&hw->lock);
2415 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2416 dev->data->port_id, mtu, ret);
2419 hns->pf.mps = (uint16_t)frame_size;
2421 dev->data->dev_conf.rxmode.offloads |=
2422 DEV_RX_OFFLOAD_JUMBO_FRAME;
2424 dev->data->dev_conf.rxmode.offloads &=
2425 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2426 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2427 rte_spinlock_unlock(&hw->lock);
2433 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2435 struct hns3_adapter *hns = eth_dev->data->dev_private;
2436 struct hns3_hw *hw = &hns->hw;
2437 uint16_t queue_num = hw->tqps_num;
2440 * In interrupt mode, 'max_rx_queues' is set based on the number of
2441 * MSI-X interrupt resources of the hardware.
2443 if (hw->data->dev_conf.intr_conf.rxq == 1)
2444 queue_num = hw->intr_tqps_num;
2446 info->max_rx_queues = queue_num;
2447 info->max_tx_queues = hw->tqps_num;
2448 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2449 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2450 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2451 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2452 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2453 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2454 DEV_RX_OFFLOAD_TCP_CKSUM |
2455 DEV_RX_OFFLOAD_UDP_CKSUM |
2456 DEV_RX_OFFLOAD_SCTP_CKSUM |
2457 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2458 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2459 DEV_RX_OFFLOAD_KEEP_CRC |
2460 DEV_RX_OFFLOAD_SCATTER |
2461 DEV_RX_OFFLOAD_VLAN_STRIP |
2462 DEV_RX_OFFLOAD_VLAN_FILTER |
2463 DEV_RX_OFFLOAD_JUMBO_FRAME |
2464 DEV_RX_OFFLOAD_RSS_HASH |
2465 DEV_RX_OFFLOAD_TCP_LRO);
2466 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2467 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2468 DEV_TX_OFFLOAD_IPV4_CKSUM |
2469 DEV_TX_OFFLOAD_TCP_CKSUM |
2470 DEV_TX_OFFLOAD_UDP_CKSUM |
2471 DEV_TX_OFFLOAD_SCTP_CKSUM |
2472 DEV_TX_OFFLOAD_MULTI_SEGS |
2473 DEV_TX_OFFLOAD_TCP_TSO |
2474 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2475 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2476 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2477 info->tx_queue_offload_capa |
2478 hns3_txvlan_cap_get(hw));
2480 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2481 .nb_max = HNS3_MAX_RING_DESC,
2482 .nb_min = HNS3_MIN_RING_DESC,
2483 .nb_align = HNS3_ALIGN_RING_DESC,
2486 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2487 .nb_max = HNS3_MAX_RING_DESC,
2488 .nb_min = HNS3_MIN_RING_DESC,
2489 .nb_align = HNS3_ALIGN_RING_DESC,
2490 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2491 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
2494 info->default_rxconf = (struct rte_eth_rxconf) {
2496 * If there are no available Rx buffer descriptors, incoming
2497 * packets are always dropped by hardware based on hns3 network
2503 info->vmdq_queue_num = 0;
2505 info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2506 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2507 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2509 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2510 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2511 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2512 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2513 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2514 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2520 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2523 struct hns3_adapter *hns = eth_dev->data->dev_private;
2524 struct hns3_hw *hw = &hns->hw;
2525 uint32_t version = hw->fw_version;
2528 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2529 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2530 HNS3_FW_VERSION_BYTE3_S),
2531 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2532 HNS3_FW_VERSION_BYTE2_S),
2533 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2534 HNS3_FW_VERSION_BYTE1_S),
2535 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2536 HNS3_FW_VERSION_BYTE0_S));
2537 ret += 1; /* add the size of '\0' */
2538 if (fw_size < (uint32_t)ret)
2545 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2546 __rte_unused int wait_to_complete)
2548 struct hns3_adapter *hns = eth_dev->data->dev_private;
2549 struct hns3_hw *hw = &hns->hw;
2550 struct hns3_mac *mac = &hw->mac;
2551 struct rte_eth_link new_link;
2553 if (!hns3_is_reset_pending(hns)) {
2554 hns3_update_speed_duplex(eth_dev);
2555 hns3_update_link_status(hw);
2558 memset(&new_link, 0, sizeof(new_link));
2559 switch (mac->link_speed) {
2560 case ETH_SPEED_NUM_10M:
2561 case ETH_SPEED_NUM_100M:
2562 case ETH_SPEED_NUM_1G:
2563 case ETH_SPEED_NUM_10G:
2564 case ETH_SPEED_NUM_25G:
2565 case ETH_SPEED_NUM_40G:
2566 case ETH_SPEED_NUM_50G:
2567 case ETH_SPEED_NUM_100G:
2568 case ETH_SPEED_NUM_200G:
2569 new_link.link_speed = mac->link_speed;
2572 new_link.link_speed = ETH_SPEED_NUM_100M;
2576 new_link.link_duplex = mac->link_duplex;
2577 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2578 new_link.link_autoneg =
2579 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2581 return rte_eth_linkstatus_set(eth_dev, &new_link);
2585 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2587 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2588 struct hns3_pf *pf = &hns->pf;
2590 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2593 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2599 hns3_query_function_status(struct hns3_hw *hw)
2601 #define HNS3_QUERY_MAX_CNT 10
2602 #define HNS3_QUERY_SLEEP_MSCOEND 1
2603 struct hns3_func_status_cmd *req;
2604 struct hns3_cmd_desc desc;
2608 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2609 req = (struct hns3_func_status_cmd *)desc.data;
2612 ret = hns3_cmd_send(hw, &desc, 1);
2614 PMD_INIT_LOG(ERR, "query function status failed %d",
2619 /* Check pf reset is done */
2623 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2624 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2626 return hns3_parse_func_status(hw, req);
2630 hns3_query_pf_resource(struct hns3_hw *hw)
2632 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2633 struct hns3_pf *pf = &hns->pf;
2634 struct hns3_pf_res_cmd *req;
2635 struct hns3_cmd_desc desc;
2638 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2639 ret = hns3_cmd_send(hw, &desc, 1);
2641 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2645 req = (struct hns3_pf_res_cmd *)desc.data;
2646 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2647 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2648 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2649 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2651 if (req->tx_buf_size)
2653 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2655 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2657 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2659 if (req->dv_buf_size)
2661 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2663 pf->dv_buf_size = HNS3_DEFAULT_DV;
2665 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2668 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2669 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2675 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2677 struct hns3_cfg_param_cmd *req;
2678 uint64_t mac_addr_tmp_high;
2679 uint64_t mac_addr_tmp;
2682 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2684 /* get the configuration */
2685 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2686 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2687 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2688 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2689 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2690 HNS3_CFG_TQP_DESC_N_M,
2691 HNS3_CFG_TQP_DESC_N_S);
2693 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2694 HNS3_CFG_PHY_ADDR_M,
2695 HNS3_CFG_PHY_ADDR_S);
2696 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2697 HNS3_CFG_MEDIA_TP_M,
2698 HNS3_CFG_MEDIA_TP_S);
2699 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2700 HNS3_CFG_RX_BUF_LEN_M,
2701 HNS3_CFG_RX_BUF_LEN_S);
2702 /* get mac address */
2703 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2704 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2705 HNS3_CFG_MAC_ADDR_H_M,
2706 HNS3_CFG_MAC_ADDR_H_S);
2708 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2710 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2711 HNS3_CFG_DEFAULT_SPEED_M,
2712 HNS3_CFG_DEFAULT_SPEED_S);
2713 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2714 HNS3_CFG_RSS_SIZE_M,
2715 HNS3_CFG_RSS_SIZE_S);
2717 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2718 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2720 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2721 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2723 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2724 HNS3_CFG_SPEED_ABILITY_M,
2725 HNS3_CFG_SPEED_ABILITY_S);
2726 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2727 HNS3_CFG_UMV_TBL_SPACE_M,
2728 HNS3_CFG_UMV_TBL_SPACE_S);
2729 if (!cfg->umv_space)
2730 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2733 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2734 * @hw: pointer to struct hns3_hw
2735 * @hcfg: the config structure to be getted
2738 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2740 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2741 struct hns3_cfg_param_cmd *req;
2746 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2748 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2749 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2751 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2752 i * HNS3_CFG_RD_LEN_BYTES);
2753 /* Len should be divided by 4 when send to hardware */
2754 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2755 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2756 req->offset = rte_cpu_to_le_32(offset);
2759 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2761 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2765 hns3_parse_cfg(hcfg, desc);
2771 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2773 switch (speed_cmd) {
2774 case HNS3_CFG_SPEED_10M:
2775 *speed = ETH_SPEED_NUM_10M;
2777 case HNS3_CFG_SPEED_100M:
2778 *speed = ETH_SPEED_NUM_100M;
2780 case HNS3_CFG_SPEED_1G:
2781 *speed = ETH_SPEED_NUM_1G;
2783 case HNS3_CFG_SPEED_10G:
2784 *speed = ETH_SPEED_NUM_10G;
2786 case HNS3_CFG_SPEED_25G:
2787 *speed = ETH_SPEED_NUM_25G;
2789 case HNS3_CFG_SPEED_40G:
2790 *speed = ETH_SPEED_NUM_40G;
2792 case HNS3_CFG_SPEED_50G:
2793 *speed = ETH_SPEED_NUM_50G;
2795 case HNS3_CFG_SPEED_100G:
2796 *speed = ETH_SPEED_NUM_100G;
2798 case HNS3_CFG_SPEED_200G:
2799 *speed = ETH_SPEED_NUM_200G;
2809 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2811 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2812 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2813 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2814 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2818 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2820 struct hns3_dev_specs_0_cmd *req0;
2822 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2824 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2825 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2826 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2827 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2831 hns3_query_dev_specifications(struct hns3_hw *hw)
2833 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2837 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2838 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2840 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2842 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2844 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2848 hns3_parse_dev_specifications(hw, desc);
2854 hns3_get_capability(struct hns3_hw *hw)
2856 struct rte_pci_device *pci_dev;
2857 struct rte_eth_dev *eth_dev;
2862 eth_dev = &rte_eth_devices[hw->data->port_id];
2863 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2864 device_id = pci_dev->id.device_id;
2866 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2867 device_id == HNS3_DEV_ID_50GE_RDMA ||
2868 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2869 device_id == HNS3_DEV_ID_200G_RDMA)
2870 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2872 /* Get PCI revision id */
2873 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2874 HNS3_PCI_REVISION_ID);
2875 if (ret != HNS3_PCI_REVISION_ID_LEN) {
2876 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2880 hw->revision = revision;
2882 if (revision < PCI_REVISION_ID_HIP09_A) {
2883 hns3_set_default_dev_specifications(hw);
2884 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2885 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2886 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2887 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2891 ret = hns3_query_dev_specifications(hw);
2894 "failed to query dev specifications, ret = %d",
2899 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2900 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
2901 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2902 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2908 hns3_get_board_configuration(struct hns3_hw *hw)
2910 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2911 struct hns3_pf *pf = &hns->pf;
2912 struct hns3_cfg cfg;
2915 ret = hns3_get_board_cfg(hw, &cfg);
2917 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2921 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
2922 !hns3_dev_copper_supported(hw)) {
2923 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2927 hw->mac.media_type = cfg.media_type;
2928 hw->rss_size_max = cfg.rss_size_max;
2929 hw->rss_dis_flag = false;
2930 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2931 hw->mac.phy_addr = cfg.phy_addr;
2932 hw->mac.default_addr_setted = false;
2933 hw->num_tx_desc = cfg.tqp_desc_num;
2934 hw->num_rx_desc = cfg.tqp_desc_num;
2935 hw->dcb_info.num_pg = 1;
2936 hw->dcb_info.hw_pfc_map = 0;
2938 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2940 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2941 cfg.default_speed, ret);
2945 pf->tc_max = cfg.tc_num;
2946 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2947 PMD_INIT_LOG(WARNING,
2948 "Get TC num(%u) from flash, set TC num to 1",
2953 /* Dev does not support DCB */
2954 if (!hns3_dev_dcb_supported(hw)) {
2958 pf->pfc_max = pf->tc_max;
2960 hw->dcb_info.num_tc = 1;
2961 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2962 hw->tqps_num / hw->dcb_info.num_tc);
2963 hns3_set_bit(hw->hw_tc_map, 0, 1);
2964 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2966 pf->wanted_umv_size = cfg.umv_space;
2972 hns3_get_configuration(struct hns3_hw *hw)
2976 ret = hns3_query_function_status(hw);
2978 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2982 /* Get device capability */
2983 ret = hns3_get_capability(hw);
2985 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2989 /* Get pf resource */
2990 ret = hns3_query_pf_resource(hw);
2992 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2996 ret = hns3_get_board_configuration(hw);
2998 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
3004 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3005 uint16_t tqp_vid, bool is_pf)
3007 struct hns3_tqp_map_cmd *req;
3008 struct hns3_cmd_desc desc;
3011 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3013 req = (struct hns3_tqp_map_cmd *)desc.data;
3014 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3015 req->tqp_vf = func_id;
3016 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3018 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3019 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3021 ret = hns3_cmd_send(hw, &desc, 1);
3023 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3029 hns3_map_tqp(struct hns3_hw *hw)
3031 uint16_t tqps_num = hw->total_tqps_num;
3040 * In current version VF is not supported when PF is driven by DPDK
3041 * driver, so we allocate tqps to PF as much as possible.
3044 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
3045 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
3046 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
3048 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
3049 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
3060 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3062 struct hns3_config_mac_speed_dup_cmd *req;
3063 struct hns3_cmd_desc desc;
3066 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3068 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3070 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3073 case ETH_SPEED_NUM_10M:
3074 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3075 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3077 case ETH_SPEED_NUM_100M:
3078 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3079 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3081 case ETH_SPEED_NUM_1G:
3082 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3083 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3085 case ETH_SPEED_NUM_10G:
3086 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3087 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3089 case ETH_SPEED_NUM_25G:
3090 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3091 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3093 case ETH_SPEED_NUM_40G:
3094 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3095 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3097 case ETH_SPEED_NUM_50G:
3098 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3099 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3101 case ETH_SPEED_NUM_100G:
3102 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3103 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3105 case ETH_SPEED_NUM_200G:
3106 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3107 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3110 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3114 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3116 ret = hns3_cmd_send(hw, &desc, 1);
3118 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3124 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3126 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3127 struct hns3_pf *pf = &hns->pf;
3128 struct hns3_priv_buf *priv;
3129 uint32_t i, total_size;
3131 total_size = pf->pkt_buf_size;
3133 /* alloc tx buffer for all enabled tc */
3134 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3135 priv = &buf_alloc->priv_buf[i];
3137 if (hw->hw_tc_map & BIT(i)) {
3138 if (total_size < pf->tx_buf_size)
3141 priv->tx_buf_size = pf->tx_buf_size;
3143 priv->tx_buf_size = 0;
3145 total_size -= priv->tx_buf_size;
3152 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3154 /* TX buffer size is unit by 128 byte */
3155 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3156 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3157 struct hns3_tx_buff_alloc_cmd *req;
3158 struct hns3_cmd_desc desc;
3163 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3165 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3166 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3167 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3169 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3170 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3171 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3174 ret = hns3_cmd_send(hw, &desc, 1);
3176 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3182 hns3_get_tc_num(struct hns3_hw *hw)
3187 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3188 if (hw->hw_tc_map & BIT(i))
3194 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3196 struct hns3_priv_buf *priv;
3197 uint32_t rx_priv = 0;
3200 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3201 priv = &buf_alloc->priv_buf[i];
3203 rx_priv += priv->buf_size;
3209 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3211 uint32_t total_tx_size = 0;
3214 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3215 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3217 return total_tx_size;
3220 /* Get the number of pfc enabled TCs, which have private buffer */
3222 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3224 struct hns3_priv_buf *priv;
3228 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3229 priv = &buf_alloc->priv_buf[i];
3230 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3237 /* Get the number of pfc disabled TCs, which have private buffer */
3239 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3240 struct hns3_pkt_buf_alloc *buf_alloc)
3242 struct hns3_priv_buf *priv;
3246 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3247 priv = &buf_alloc->priv_buf[i];
3248 if (hw->hw_tc_map & BIT(i) &&
3249 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3257 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3260 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3261 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3262 struct hns3_pf *pf = &hns->pf;
3263 uint32_t shared_buf, aligned_mps;
3268 tc_num = hns3_get_tc_num(hw);
3269 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3271 if (hns3_dev_dcb_supported(hw))
3272 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3275 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3278 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3279 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3280 HNS3_BUF_SIZE_UNIT);
3282 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3283 if (rx_all < rx_priv + shared_std)
3286 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3287 buf_alloc->s_buf.buf_size = shared_buf;
3288 if (hns3_dev_dcb_supported(hw)) {
3289 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3290 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3291 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3292 HNS3_BUF_SIZE_UNIT);
3294 buf_alloc->s_buf.self.high =
3295 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3296 buf_alloc->s_buf.self.low = aligned_mps;
3299 if (hns3_dev_dcb_supported(hw)) {
3300 hi_thrd = shared_buf - pf->dv_buf_size;
3302 if (tc_num <= NEED_RESERVE_TC_NUM)
3303 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3307 hi_thrd = hi_thrd / tc_num;
3309 hi_thrd = max_t(uint32_t, hi_thrd,
3310 HNS3_BUF_MUL_BY * aligned_mps);
3311 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3312 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3314 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3315 lo_thrd = aligned_mps;
3318 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3319 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3320 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3327 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3328 struct hns3_pkt_buf_alloc *buf_alloc)
3330 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3331 struct hns3_pf *pf = &hns->pf;
3332 struct hns3_priv_buf *priv;
3333 uint32_t aligned_mps;
3337 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3338 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3340 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3341 priv = &buf_alloc->priv_buf[i];
3348 if (!(hw->hw_tc_map & BIT(i)))
3352 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3353 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3354 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3355 HNS3_BUF_SIZE_UNIT);
3358 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3362 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3365 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3369 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3370 struct hns3_pkt_buf_alloc *buf_alloc)
3372 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3373 struct hns3_pf *pf = &hns->pf;
3374 struct hns3_priv_buf *priv;
3375 int no_pfc_priv_num;
3380 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3381 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3383 /* let the last to be cleared first */
3384 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3385 priv = &buf_alloc->priv_buf[i];
3386 mask = BIT((uint8_t)i);
3388 if (hw->hw_tc_map & mask &&
3389 !(hw->dcb_info.hw_pfc_map & mask)) {
3390 /* Clear the no pfc TC private buffer */
3398 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3399 no_pfc_priv_num == 0)
3403 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3407 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3408 struct hns3_pkt_buf_alloc *buf_alloc)
3410 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3411 struct hns3_pf *pf = &hns->pf;
3412 struct hns3_priv_buf *priv;
3418 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3419 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3421 /* let the last to be cleared first */
3422 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3423 priv = &buf_alloc->priv_buf[i];
3424 mask = BIT((uint8_t)i);
3426 if (hw->hw_tc_map & mask &&
3427 hw->dcb_info.hw_pfc_map & mask) {
3428 /* Reduce the number of pfc TC with private buffer */
3435 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3440 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3444 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3445 struct hns3_pkt_buf_alloc *buf_alloc)
3447 #define COMPENSATE_BUFFER 0x3C00
3448 #define COMPENSATE_HALF_MPS_NUM 5
3449 #define PRIV_WL_GAP 0x1800
3450 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3451 struct hns3_pf *pf = &hns->pf;
3452 uint32_t tc_num = hns3_get_tc_num(hw);
3453 uint32_t half_mps = pf->mps >> 1;
3454 struct hns3_priv_buf *priv;
3455 uint32_t min_rx_priv;
3459 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3461 rx_priv = rx_priv / tc_num;
3463 if (tc_num <= NEED_RESERVE_TC_NUM)
3464 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3467 * Minimum value of private buffer in rx direction (min_rx_priv) is
3468 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3469 * buffer if rx_priv is greater than min_rx_priv.
3471 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3472 COMPENSATE_HALF_MPS_NUM * half_mps;
3473 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3474 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3476 if (rx_priv < min_rx_priv)
3479 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3480 priv = &buf_alloc->priv_buf[i];
3487 if (!(hw->hw_tc_map & BIT(i)))
3491 priv->buf_size = rx_priv;
3492 priv->wl.high = rx_priv - pf->dv_buf_size;
3493 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3496 buf_alloc->s_buf.buf_size = 0;
3502 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3503 * @hw: pointer to struct hns3_hw
3504 * @buf_alloc: pointer to buffer calculation data
3505 * @return: 0: calculate sucessful, negative: fail
3508 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3510 /* When DCB is not supported, rx private buffer is not allocated. */
3511 if (!hns3_dev_dcb_supported(hw)) {
3512 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3513 struct hns3_pf *pf = &hns->pf;
3514 uint32_t rx_all = pf->pkt_buf_size;
3516 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3517 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3524 * Try to allocate privated packet buffer for all TCs without share
3527 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3531 * Try to allocate privated packet buffer for all TCs with share
3534 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3538 * For different application scenes, the enabled port number, TC number
3539 * and no_drop TC number are different. In order to obtain the better
3540 * performance, software could allocate the buffer size and configure
3541 * the waterline by tring to decrease the private buffer size according
3542 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3545 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3548 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3551 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3558 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3560 struct hns3_rx_priv_buff_cmd *req;
3561 struct hns3_cmd_desc desc;
3566 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3567 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3569 /* Alloc private buffer TCs */
3570 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3571 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3574 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3575 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3578 buf_size = buf_alloc->s_buf.buf_size;
3579 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3580 (1 << HNS3_TC0_PRI_BUF_EN_B));
3582 ret = hns3_cmd_send(hw, &desc, 1);
3584 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3590 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3592 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3593 struct hns3_rx_priv_wl_buf *req;
3594 struct hns3_priv_buf *priv;
3595 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3599 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3600 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3602 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3604 /* The first descriptor set the NEXT bit to 1 */
3606 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3608 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3610 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3611 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3613 priv = &buf_alloc->priv_buf[idx];
3614 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3616 req->tc_wl[j].high |=
3617 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3618 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3620 req->tc_wl[j].low |=
3621 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3625 /* Send 2 descriptor at one time */
3626 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3628 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3634 hns3_common_thrd_config(struct hns3_hw *hw,
3635 struct hns3_pkt_buf_alloc *buf_alloc)
3637 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3638 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3639 struct hns3_rx_com_thrd *req;
3640 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3641 struct hns3_tc_thrd *tc;
3646 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3647 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3649 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3651 /* The first descriptor set the NEXT bit to 1 */
3653 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3655 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3657 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3658 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3659 tc = &s_buf->tc_thrd[tc_idx];
3661 req->com_thrd[j].high =
3662 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3663 req->com_thrd[j].high |=
3664 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3665 req->com_thrd[j].low =
3666 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3667 req->com_thrd[j].low |=
3668 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3672 /* Send 2 descriptors at one time */
3673 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3675 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3681 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3683 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3684 struct hns3_rx_com_wl *req;
3685 struct hns3_cmd_desc desc;
3688 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3690 req = (struct hns3_rx_com_wl *)desc.data;
3691 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3692 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3694 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3695 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3697 ret = hns3_cmd_send(hw, &desc, 1);
3699 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3705 hns3_buffer_alloc(struct hns3_hw *hw)
3707 struct hns3_pkt_buf_alloc pkt_buf;
3710 memset(&pkt_buf, 0, sizeof(pkt_buf));
3711 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3714 "could not calc tx buffer size for all TCs %d",
3719 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3721 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3725 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3728 "could not calc rx priv buffer size for all TCs %d",
3733 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3735 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3739 if (hns3_dev_dcb_supported(hw)) {
3740 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3743 "could not configure rx private waterline %d",
3748 ret = hns3_common_thrd_config(hw, &pkt_buf);
3751 "could not configure common threshold %d",
3757 ret = hns3_common_wl_config(hw, &pkt_buf);
3759 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3766 hns3_mac_init(struct hns3_hw *hw)
3768 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3769 struct hns3_mac *mac = &hw->mac;
3770 struct hns3_pf *pf = &hns->pf;
3773 pf->support_sfp_query = true;
3774 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3775 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3777 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3781 mac->link_status = ETH_LINK_DOWN;
3783 return hns3_config_mtu(hw, pf->mps);
3787 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3789 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
3790 #define HNS3_ETHERTYPE_ALREADY_ADD 1
3791 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
3792 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
3797 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3802 switch (resp_code) {
3803 case HNS3_ETHERTYPE_SUCCESS_ADD:
3804 case HNS3_ETHERTYPE_ALREADY_ADD:
3807 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3809 "add mac ethertype failed for manager table overflow.");
3810 return_status = -EIO;
3812 case HNS3_ETHERTYPE_KEY_CONFLICT:
3813 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3814 return_status = -EIO;
3818 "add mac ethertype failed for undefined, code=%d.",
3820 return_status = -EIO;
3824 return return_status;
3828 hns3_add_mgr_tbl(struct hns3_hw *hw,
3829 const struct hns3_mac_mgr_tbl_entry_cmd *req)
3831 struct hns3_cmd_desc desc;
3836 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3837 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3839 ret = hns3_cmd_send(hw, &desc, 1);
3842 "add mac ethertype failed for cmd_send, ret =%d.",
3847 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3848 retval = rte_le_to_cpu_16(desc.retval);
3850 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3854 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3855 int *table_item_num)
3857 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3860 * In current version, we add one item in management table as below:
3861 * 0x0180C200000E -- LLDP MC address
3864 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3865 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3866 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3867 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3868 tbl->i_port_bitmap = 0x1;
3869 *table_item_num = 1;
3873 hns3_init_mgr_tbl(struct hns3_hw *hw)
3875 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
3876 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3881 memset(mgr_table, 0, sizeof(mgr_table));
3882 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3883 for (i = 0; i < table_item_num; i++) {
3884 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3886 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3896 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3897 bool en_mc, bool en_bc, int vport_id)
3902 memset(param, 0, sizeof(struct hns3_promisc_param));
3904 param->enable = HNS3_PROMISC_EN_UC;
3906 param->enable |= HNS3_PROMISC_EN_MC;
3908 param->enable |= HNS3_PROMISC_EN_BC;
3909 param->vf_id = vport_id;
3913 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3915 struct hns3_promisc_cfg_cmd *req;
3916 struct hns3_cmd_desc desc;
3919 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3921 req = (struct hns3_promisc_cfg_cmd *)desc.data;
3922 req->vf_id = param->vf_id;
3923 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3924 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3926 ret = hns3_cmd_send(hw, &desc, 1);
3928 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3934 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3936 struct hns3_promisc_param param;
3937 bool en_bc_pmc = true;
3941 * In current version VF is not supported when PF is driven by DPDK
3942 * driver, just need to configure parameters for PF vport.
3944 vf_id = HNS3_PF_FUNC_ID;
3946 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3947 return hns3_cmd_set_promisc_mode(hw, ¶m);
3951 hns3_promisc_init(struct hns3_hw *hw)
3953 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3954 struct hns3_pf *pf = &hns->pf;
3955 struct hns3_promisc_param param;
3959 ret = hns3_set_promisc_mode(hw, false, false);
3961 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3966 * In current version VFs are not supported when PF is driven by DPDK
3967 * driver. After PF has been taken over by DPDK, the original VF will
3968 * be invalid. So, there is a possibility of entry residues. It should
3969 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3972 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3973 hns3_promisc_param_init(¶m, false, false, false, func_id);
3974 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
3976 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3977 " ret = %d", func_id, ret);
3986 hns3_promisc_uninit(struct hns3_hw *hw)
3988 struct hns3_promisc_param param;
3992 func_id = HNS3_PF_FUNC_ID;
3995 * In current version VFs are not supported when PF is driven by
3996 * DPDK driver, and VFs' promisc mode status has been cleared during
3997 * init and their status will not change. So just clear PF's promisc
3998 * mode status during uninit.
4000 hns3_promisc_param_init(¶m, false, false, false, func_id);
4001 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4003 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4004 " uninit, ret = %d", ret);
4008 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4010 bool allmulti = dev->data->all_multicast ? true : false;
4011 struct hns3_adapter *hns = dev->data->dev_private;
4012 struct hns3_hw *hw = &hns->hw;
4017 rte_spinlock_lock(&hw->lock);
4018 ret = hns3_set_promisc_mode(hw, true, true);
4020 rte_spinlock_unlock(&hw->lock);
4021 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4027 * When promiscuous mode was enabled, disable the vlan filter to let
4028 * all packets coming in in the receiving direction.
4030 offloads = dev->data->dev_conf.rxmode.offloads;
4031 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4032 ret = hns3_enable_vlan_filter(hns, false);
4034 hns3_err(hw, "failed to enable promiscuous mode due to "
4035 "failure to disable vlan filter, ret = %d",
4037 err = hns3_set_promisc_mode(hw, false, allmulti);
4039 hns3_err(hw, "failed to restore promiscuous "
4040 "status after disable vlan filter "
4041 "failed during enabling promiscuous "
4042 "mode, ret = %d", ret);
4046 rte_spinlock_unlock(&hw->lock);
4052 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4054 bool allmulti = dev->data->all_multicast ? true : false;
4055 struct hns3_adapter *hns = dev->data->dev_private;
4056 struct hns3_hw *hw = &hns->hw;
4061 /* If now in all_multicast mode, must remain in all_multicast mode. */
4062 rte_spinlock_lock(&hw->lock);
4063 ret = hns3_set_promisc_mode(hw, false, allmulti);
4065 rte_spinlock_unlock(&hw->lock);
4066 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4070 /* when promiscuous mode was disabled, restore the vlan filter status */
4071 offloads = dev->data->dev_conf.rxmode.offloads;
4072 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4073 ret = hns3_enable_vlan_filter(hns, true);
4075 hns3_err(hw, "failed to disable promiscuous mode due to"
4076 " failure to restore vlan filter, ret = %d",
4078 err = hns3_set_promisc_mode(hw, true, true);
4080 hns3_err(hw, "failed to restore promiscuous "
4081 "status after enabling vlan filter "
4082 "failed during disabling promiscuous "
4083 "mode, ret = %d", ret);
4086 rte_spinlock_unlock(&hw->lock);
4092 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4094 struct hns3_adapter *hns = dev->data->dev_private;
4095 struct hns3_hw *hw = &hns->hw;
4098 if (dev->data->promiscuous)
4101 rte_spinlock_lock(&hw->lock);
4102 ret = hns3_set_promisc_mode(hw, false, true);
4103 rte_spinlock_unlock(&hw->lock);
4105 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4112 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4114 struct hns3_adapter *hns = dev->data->dev_private;
4115 struct hns3_hw *hw = &hns->hw;
4118 /* If now in promiscuous mode, must remain in all_multicast mode. */
4119 if (dev->data->promiscuous)
4122 rte_spinlock_lock(&hw->lock);
4123 ret = hns3_set_promisc_mode(hw, false, false);
4124 rte_spinlock_unlock(&hw->lock);
4126 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4133 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4135 struct hns3_hw *hw = &hns->hw;
4136 bool allmulti = hw->data->all_multicast ? true : false;
4139 if (hw->data->promiscuous) {
4140 ret = hns3_set_promisc_mode(hw, true, true);
4142 hns3_err(hw, "failed to restore promiscuous mode, "
4147 ret = hns3_set_promisc_mode(hw, false, allmulti);
4149 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4155 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4157 struct hns3_sfp_speed_cmd *resp;
4158 struct hns3_cmd_desc desc;
4161 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4162 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4163 ret = hns3_cmd_send(hw, &desc, 1);
4164 if (ret == -EOPNOTSUPP) {
4165 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4168 hns3_err(hw, "get sfp speed failed %d", ret);
4172 *speed = resp->sfp_speed;
4178 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4180 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4181 duplex = ETH_LINK_FULL_DUPLEX;
4187 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4189 struct hns3_mac *mac = &hw->mac;
4192 duplex = hns3_check_speed_dup(duplex, speed);
4193 if (mac->link_speed == speed && mac->link_duplex == duplex)
4196 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4200 mac->link_speed = speed;
4201 mac->link_duplex = duplex;
4207 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4209 struct hns3_adapter *hns = eth_dev->data->dev_private;
4210 struct hns3_hw *hw = &hns->hw;
4211 struct hns3_pf *pf = &hns->pf;
4215 /* If IMP do not support get SFP/qSFP speed, return directly */
4216 if (!pf->support_sfp_query)
4219 ret = hns3_get_sfp_speed(hw, &speed);
4220 if (ret == -EOPNOTSUPP) {
4221 pf->support_sfp_query = false;
4226 if (speed == ETH_SPEED_NUM_NONE)
4227 return 0; /* do nothing if no SFP */
4229 /* Config full duplex for SFP */
4230 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4234 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4236 struct hns3_config_mac_mode_cmd *req;
4237 struct hns3_cmd_desc desc;
4238 uint32_t loop_en = 0;
4242 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4244 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4247 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4248 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4249 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4250 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4251 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4252 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4253 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4254 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4255 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4256 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4259 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4260 * when receiving frames. Otherwise, CRC will be stripped.
4262 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4263 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4265 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4266 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4267 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4268 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4269 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4271 ret = hns3_cmd_send(hw, &desc, 1);
4273 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4279 hns3_get_mac_link_status(struct hns3_hw *hw)
4281 struct hns3_link_status_cmd *req;
4282 struct hns3_cmd_desc desc;
4286 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4287 ret = hns3_cmd_send(hw, &desc, 1);
4289 hns3_err(hw, "get link status cmd failed %d", ret);
4290 return ETH_LINK_DOWN;
4293 req = (struct hns3_link_status_cmd *)desc.data;
4294 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4296 return !!link_status;
4300 hns3_update_link_status(struct hns3_hw *hw)
4304 state = hns3_get_mac_link_status(hw);
4305 if (state != hw->mac.link_status) {
4306 hw->mac.link_status = state;
4307 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4312 hns3_service_handler(void *param)
4314 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4315 struct hns3_adapter *hns = eth_dev->data->dev_private;
4316 struct hns3_hw *hw = &hns->hw;
4318 if (!hns3_is_reset_pending(hns)) {
4319 hns3_update_speed_duplex(eth_dev);
4320 hns3_update_link_status(hw);
4322 hns3_warn(hw, "Cancel the query when reset is pending");
4324 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4328 hns3_init_hardware(struct hns3_adapter *hns)
4330 struct hns3_hw *hw = &hns->hw;
4333 ret = hns3_map_tqp(hw);
4335 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4339 ret = hns3_init_umv_space(hw);
4341 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4345 ret = hns3_mac_init(hw);
4347 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4351 ret = hns3_init_mgr_tbl(hw);
4353 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4357 ret = hns3_promisc_init(hw);
4359 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4364 ret = hns3_init_vlan_config(hns);
4366 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4370 ret = hns3_dcb_init(hw);
4372 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4376 ret = hns3_init_fd_config(hns);
4378 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4382 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4384 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4388 ret = hns3_config_gro(hw, false);
4390 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4395 * In the initialization clearing the all hardware mapping relationship
4396 * configurations between queues and interrupt vectors is needed, so
4397 * some error caused by the residual configurations, such as the
4398 * unexpected interrupt, can be avoid.
4400 ret = hns3_init_ring_with_vector(hw);
4402 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4409 hns3_uninit_umv_space(hw);
4414 hns3_clear_hw(struct hns3_hw *hw)
4416 struct hns3_cmd_desc desc;
4419 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4421 ret = hns3_cmd_send(hw, &desc, 1);
4422 if (ret && ret != -EOPNOTSUPP)
4429 hns3_init_pf(struct rte_eth_dev *eth_dev)
4431 struct rte_device *dev = eth_dev->device;
4432 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4433 struct hns3_adapter *hns = eth_dev->data->dev_private;
4434 struct hns3_hw *hw = &hns->hw;
4437 PMD_INIT_FUNC_TRACE();
4439 /* Get hardware io base address from pcie BAR2 IO space */
4440 hw->io_base = pci_dev->mem_resource[2].addr;
4442 /* Firmware command queue initialize */
4443 ret = hns3_cmd_init_queue(hw);
4445 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4446 goto err_cmd_init_queue;
4449 hns3_clear_all_event_cause(hw);
4451 /* Firmware command initialize */
4452 ret = hns3_cmd_init(hw);
4454 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4459 * To ensure that the hardware environment is clean during
4460 * initialization, the driver actively clear the hardware environment
4461 * during initialization, including PF and corresponding VFs' vlan, mac,
4462 * flow table configurations, etc.
4464 ret = hns3_clear_hw(hw);
4466 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4470 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4471 hns3_interrupt_handler,
4474 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4475 goto err_intr_callback_register;
4478 /* Enable interrupt */
4479 rte_intr_enable(&pci_dev->intr_handle);
4480 hns3_pf_enable_irq0(hw);
4482 /* Get configuration */
4483 ret = hns3_get_configuration(hw);
4485 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4486 goto err_get_config;
4489 ret = hns3_init_hardware(hns);
4491 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4492 goto err_get_config;
4495 /* Initialize flow director filter list & hash */
4496 ret = hns3_fdir_filter_init(hns);
4498 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4502 hns3_set_default_rss_args(hw);
4504 ret = hns3_enable_hw_error_intr(hns, true);
4506 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4514 hns3_fdir_filter_uninit(hns);
4516 hns3_uninit_umv_space(hw);
4519 hns3_pf_disable_irq0(hw);
4520 rte_intr_disable(&pci_dev->intr_handle);
4521 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4523 err_intr_callback_register:
4525 hns3_cmd_uninit(hw);
4526 hns3_cmd_destroy_queue(hw);
4534 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4536 struct hns3_adapter *hns = eth_dev->data->dev_private;
4537 struct rte_device *dev = eth_dev->device;
4538 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4539 struct hns3_hw *hw = &hns->hw;
4541 PMD_INIT_FUNC_TRACE();
4543 hns3_enable_hw_error_intr(hns, false);
4544 hns3_rss_uninit(hns);
4545 (void)hns3_config_gro(hw, false);
4546 hns3_promisc_uninit(hw);
4547 hns3_fdir_filter_uninit(hns);
4548 hns3_uninit_umv_space(hw);
4549 hns3_pf_disable_irq0(hw);
4550 rte_intr_disable(&pci_dev->intr_handle);
4551 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4553 hns3_cmd_uninit(hw);
4554 hns3_cmd_destroy_queue(hw);
4559 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4561 struct hns3_hw *hw = &hns->hw;
4564 ret = hns3_dcb_cfg_update(hns);
4569 ret = hns3_start_queues(hns, reset_queue);
4571 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4576 ret = hns3_cfg_mac_mode(hw, true);
4578 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4579 goto err_config_mac_mode;
4583 err_config_mac_mode:
4584 hns3_stop_queues(hns, true);
4589 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4591 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4592 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4593 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4594 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4595 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4596 uint32_t intr_vector;
4600 if (dev->data->dev_conf.intr_conf.rxq == 0)
4603 /* disable uio/vfio intr/eventfd mapping */
4604 rte_intr_disable(intr_handle);
4606 /* check and configure queue intr-vector mapping */
4607 if (rte_intr_cap_multiple(intr_handle) ||
4608 !RTE_ETH_DEV_SRIOV(dev).active) {
4609 intr_vector = hw->used_rx_queues;
4610 /* creates event fd for each intr vector when MSIX is used */
4611 if (rte_intr_efd_enable(intr_handle, intr_vector))
4614 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4615 intr_handle->intr_vec =
4616 rte_zmalloc("intr_vec",
4617 hw->used_rx_queues * sizeof(int), 0);
4618 if (intr_handle->intr_vec == NULL) {
4619 hns3_err(hw, "Failed to allocate %d rx_queues"
4620 " intr_vec", hw->used_rx_queues);
4622 goto alloc_intr_vec_error;
4626 if (rte_intr_allow_others(intr_handle)) {
4627 vec = RTE_INTR_VEC_RXTX_OFFSET;
4628 base = RTE_INTR_VEC_RXTX_OFFSET;
4630 if (rte_intr_dp_is_en(intr_handle)) {
4631 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4632 ret = hns3_bind_ring_with_vector(hw, vec, true,
4636 goto bind_vector_error;
4637 intr_handle->intr_vec[q_id] = vec;
4638 if (vec < base + intr_handle->nb_efd - 1)
4642 rte_intr_enable(intr_handle);
4646 rte_intr_efd_disable(intr_handle);
4647 if (intr_handle->intr_vec) {
4648 free(intr_handle->intr_vec);
4649 intr_handle->intr_vec = NULL;
4652 alloc_intr_vec_error:
4653 rte_intr_efd_disable(intr_handle);
4658 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4660 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4661 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4662 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4666 if (dev->data->dev_conf.intr_conf.rxq == 0)
4669 if (rte_intr_dp_is_en(intr_handle)) {
4670 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4671 ret = hns3_bind_ring_with_vector(hw,
4672 intr_handle->intr_vec[q_id], true,
4673 HNS3_RING_TYPE_RX, q_id);
4683 hns3_restore_filter(struct rte_eth_dev *dev)
4685 hns3_restore_rss_filter(dev);
4689 hns3_dev_start(struct rte_eth_dev *dev)
4691 struct hns3_adapter *hns = dev->data->dev_private;
4692 struct hns3_hw *hw = &hns->hw;
4695 PMD_INIT_FUNC_TRACE();
4696 if (rte_atomic16_read(&hw->reset.resetting))
4699 rte_spinlock_lock(&hw->lock);
4700 hw->adapter_state = HNS3_NIC_STARTING;
4702 ret = hns3_do_start(hns, true);
4704 hw->adapter_state = HNS3_NIC_CONFIGURED;
4705 rte_spinlock_unlock(&hw->lock);
4708 ret = hns3_map_rx_interrupt(dev);
4710 hw->adapter_state = HNS3_NIC_CONFIGURED;
4711 rte_spinlock_unlock(&hw->lock);
4715 hw->adapter_state = HNS3_NIC_STARTED;
4716 rte_spinlock_unlock(&hw->lock);
4718 hns3_set_rxtx_function(dev);
4719 hns3_mp_req_start_rxtx(dev);
4720 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4722 hns3_restore_filter(dev);
4724 /* Enable interrupt of all rx queues before enabling queues */
4725 hns3_dev_all_rx_queue_intr_enable(hw, true);
4727 * When finished the initialization, enable queues to receive/transmit
4730 hns3_enable_all_queues(hw, true);
4732 hns3_info(hw, "hns3 dev start successful!");
4737 hns3_do_stop(struct hns3_adapter *hns)
4739 struct hns3_hw *hw = &hns->hw;
4743 ret = hns3_cfg_mac_mode(hw, false);
4746 hw->mac.link_status = ETH_LINK_DOWN;
4748 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4749 hns3_configure_all_mac_addr(hns, true);
4752 reset_queue = false;
4753 hw->mac.default_addr_setted = false;
4754 return hns3_stop_queues(hns, reset_queue);
4758 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4760 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4761 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4762 struct hns3_adapter *hns = dev->data->dev_private;
4763 struct hns3_hw *hw = &hns->hw;
4764 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4765 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4768 if (dev->data->dev_conf.intr_conf.rxq == 0)
4771 /* unmap the ring with vector */
4772 if (rte_intr_allow_others(intr_handle)) {
4773 vec = RTE_INTR_VEC_RXTX_OFFSET;
4774 base = RTE_INTR_VEC_RXTX_OFFSET;
4776 if (rte_intr_dp_is_en(intr_handle)) {
4777 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4778 (void)hns3_bind_ring_with_vector(hw, vec, false,
4781 if (vec < base + intr_handle->nb_efd - 1)
4785 /* Clean datapath event and queue/vec mapping */
4786 rte_intr_efd_disable(intr_handle);
4787 if (intr_handle->intr_vec) {
4788 rte_free(intr_handle->intr_vec);
4789 intr_handle->intr_vec = NULL;
4794 hns3_dev_stop(struct rte_eth_dev *dev)
4796 struct hns3_adapter *hns = dev->data->dev_private;
4797 struct hns3_hw *hw = &hns->hw;
4799 PMD_INIT_FUNC_TRACE();
4801 hw->adapter_state = HNS3_NIC_STOPPING;
4802 hns3_set_rxtx_function(dev);
4804 /* Disable datapath on secondary process. */
4805 hns3_mp_req_stop_rxtx(dev);
4806 /* Prevent crashes when queues are still in use. */
4807 rte_delay_ms(hw->tqps_num);
4809 rte_spinlock_lock(&hw->lock);
4810 if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4812 hns3_unmap_rx_interrupt(dev);
4813 hns3_dev_release_mbufs(hns);
4814 hw->adapter_state = HNS3_NIC_CONFIGURED;
4816 rte_eal_alarm_cancel(hns3_service_handler, dev);
4817 rte_spinlock_unlock(&hw->lock);
4821 hns3_dev_close(struct rte_eth_dev *eth_dev)
4823 struct hns3_adapter *hns = eth_dev->data->dev_private;
4824 struct hns3_hw *hw = &hns->hw;
4826 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4827 rte_free(eth_dev->process_private);
4828 eth_dev->process_private = NULL;
4832 if (hw->adapter_state == HNS3_NIC_STARTED)
4833 hns3_dev_stop(eth_dev);
4835 hw->adapter_state = HNS3_NIC_CLOSING;
4836 hns3_reset_abort(hns);
4837 hw->adapter_state = HNS3_NIC_CLOSED;
4839 hns3_configure_all_mc_mac_addr(hns, true);
4840 hns3_remove_all_vlan_table(hns);
4841 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4842 hns3_uninit_pf(eth_dev);
4843 hns3_free_all_queues(eth_dev);
4844 rte_free(hw->reset.wait_data);
4845 rte_free(eth_dev->process_private);
4846 eth_dev->process_private = NULL;
4847 hns3_mp_uninit_primary();
4848 hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4852 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4854 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4857 fc_conf->pause_time = pf->pause_time;
4859 /* return fc current mode */
4860 switch (hw->current_mode) {
4862 fc_conf->mode = RTE_FC_FULL;
4864 case HNS3_FC_TX_PAUSE:
4865 fc_conf->mode = RTE_FC_TX_PAUSE;
4867 case HNS3_FC_RX_PAUSE:
4868 fc_conf->mode = RTE_FC_RX_PAUSE;
4872 fc_conf->mode = RTE_FC_NONE;
4880 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4884 hw->requested_mode = HNS3_FC_NONE;
4886 case RTE_FC_RX_PAUSE:
4887 hw->requested_mode = HNS3_FC_RX_PAUSE;
4889 case RTE_FC_TX_PAUSE:
4890 hw->requested_mode = HNS3_FC_TX_PAUSE;
4893 hw->requested_mode = HNS3_FC_FULL;
4896 hw->requested_mode = HNS3_FC_NONE;
4897 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4898 "configured to RTE_FC_NONE", mode);
4904 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4906 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4910 if (fc_conf->high_water || fc_conf->low_water ||
4911 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4912 hns3_err(hw, "Unsupported flow control settings specified, "
4913 "high_water(%u), low_water(%u), send_xon(%u) and "
4914 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4915 fc_conf->high_water, fc_conf->low_water,
4916 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4919 if (fc_conf->autoneg) {
4920 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4923 if (!fc_conf->pause_time) {
4924 hns3_err(hw, "Invalid pause time %d setting.",
4925 fc_conf->pause_time);
4929 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4930 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4931 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4932 "current_fc_status = %d", hw->current_fc_status);
4936 hns3_get_fc_mode(hw, fc_conf->mode);
4937 if (hw->requested_mode == hw->current_mode &&
4938 pf->pause_time == fc_conf->pause_time)
4941 rte_spinlock_lock(&hw->lock);
4942 ret = hns3_fc_enable(dev, fc_conf);
4943 rte_spinlock_unlock(&hw->lock);
4949 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4950 struct rte_eth_pfc_conf *pfc_conf)
4952 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4953 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4957 if (!hns3_dev_dcb_supported(hw)) {
4958 hns3_err(hw, "This port does not support dcb configurations.");
4962 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4963 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4964 hns3_err(hw, "Unsupported flow control settings specified, "
4965 "high_water(%u), low_water(%u), send_xon(%u) and "
4966 "mac_ctrl_frame_fwd(%u) must be set to '0'",
4967 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4968 pfc_conf->fc.send_xon,
4969 pfc_conf->fc.mac_ctrl_frame_fwd);
4972 if (pfc_conf->fc.autoneg) {
4973 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4976 if (pfc_conf->fc.pause_time == 0) {
4977 hns3_err(hw, "Invalid pause time %d setting.",
4978 pfc_conf->fc.pause_time);
4982 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4983 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4984 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4985 "current_fc_status = %d", hw->current_fc_status);
4989 priority = pfc_conf->priority;
4990 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4991 if (hw->dcb_info.pfc_en & BIT(priority) &&
4992 hw->requested_mode == hw->current_mode &&
4993 pfc_conf->fc.pause_time == pf->pause_time)
4996 rte_spinlock_lock(&hw->lock);
4997 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4998 rte_spinlock_unlock(&hw->lock);
5004 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5006 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5007 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5008 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5011 rte_spinlock_lock(&hw->lock);
5012 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5013 dcb_info->nb_tcs = pf->local_max_tc;
5015 dcb_info->nb_tcs = 1;
5017 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5018 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5019 for (i = 0; i < dcb_info->nb_tcs; i++)
5020 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5022 for (i = 0; i < hw->num_tc; i++) {
5023 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5024 dcb_info->tc_queue.tc_txq[0][i].base =
5025 hw->tc_queue[i].tqp_offset;
5026 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5027 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5028 hw->tc_queue[i].tqp_count;
5030 rte_spinlock_unlock(&hw->lock);
5036 hns3_reinit_dev(struct hns3_adapter *hns)
5038 struct hns3_hw *hw = &hns->hw;
5041 ret = hns3_cmd_init(hw);
5043 hns3_err(hw, "Failed to init cmd: %d", ret);
5047 ret = hns3_reset_all_queues(hns);
5049 hns3_err(hw, "Failed to reset all queues: %d", ret);
5053 ret = hns3_init_hardware(hns);
5055 hns3_err(hw, "Failed to init hardware: %d", ret);
5059 ret = hns3_enable_hw_error_intr(hns, true);
5061 hns3_err(hw, "fail to enable hw error interrupts: %d",
5065 hns3_info(hw, "Reset done, driver initialization finished.");
5071 is_pf_reset_done(struct hns3_hw *hw)
5073 uint32_t val, reg, reg_bit;
5075 switch (hw->reset.level) {
5076 case HNS3_IMP_RESET:
5077 reg = HNS3_GLOBAL_RESET_REG;
5078 reg_bit = HNS3_IMP_RESET_BIT;
5080 case HNS3_GLOBAL_RESET:
5081 reg = HNS3_GLOBAL_RESET_REG;
5082 reg_bit = HNS3_GLOBAL_RESET_BIT;
5084 case HNS3_FUNC_RESET:
5085 reg = HNS3_FUN_RST_ING;
5086 reg_bit = HNS3_FUN_RST_ING_B;
5088 case HNS3_FLR_RESET:
5090 hns3_err(hw, "Wait for unsupported reset level: %d",
5094 val = hns3_read_dev(hw, reg);
5095 if (hns3_get_bit(val, reg_bit))
5102 hns3_is_reset_pending(struct hns3_adapter *hns)
5104 struct hns3_hw *hw = &hns->hw;
5105 enum hns3_reset_level reset;
5107 hns3_check_event_cause(hns, NULL);
5108 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5109 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5110 hns3_warn(hw, "High level reset %d is pending", reset);
5113 reset = hns3_get_reset_level(hns, &hw->reset.request);
5114 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5115 hns3_warn(hw, "High level reset %d is request", reset);
5122 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5124 struct hns3_hw *hw = &hns->hw;
5125 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5128 if (wait_data->result == HNS3_WAIT_SUCCESS)
5130 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5131 gettimeofday(&tv, NULL);
5132 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5133 tv.tv_sec, tv.tv_usec);
5135 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5138 wait_data->hns = hns;
5139 wait_data->check_completion = is_pf_reset_done;
5140 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5141 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5142 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5143 wait_data->count = HNS3_RESET_WAIT_CNT;
5144 wait_data->result = HNS3_WAIT_REQUEST;
5145 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5150 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5152 struct hns3_cmd_desc desc;
5153 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5155 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5156 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5157 req->fun_reset_vfid = func_id;
5159 return hns3_cmd_send(hw, &desc, 1);
5163 hns3_imp_reset_cmd(struct hns3_hw *hw)
5165 struct hns3_cmd_desc desc;
5167 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5168 desc.data[0] = 0xeedd;
5170 return hns3_cmd_send(hw, &desc, 1);
5174 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5176 struct hns3_hw *hw = &hns->hw;
5180 gettimeofday(&tv, NULL);
5181 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5182 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5183 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5184 tv.tv_sec, tv.tv_usec);
5188 switch (reset_level) {
5189 case HNS3_IMP_RESET:
5190 hns3_imp_reset_cmd(hw);
5191 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5192 tv.tv_sec, tv.tv_usec);
5194 case HNS3_GLOBAL_RESET:
5195 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5196 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5197 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5198 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5199 tv.tv_sec, tv.tv_usec);
5201 case HNS3_FUNC_RESET:
5202 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5203 tv.tv_sec, tv.tv_usec);
5204 /* schedule again to check later */
5205 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5206 hns3_schedule_reset(hns);
5209 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5212 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5215 static enum hns3_reset_level
5216 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5218 struct hns3_hw *hw = &hns->hw;
5219 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5221 /* Return the highest priority reset level amongst all */
5222 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5223 reset_level = HNS3_IMP_RESET;
5224 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5225 reset_level = HNS3_GLOBAL_RESET;
5226 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5227 reset_level = HNS3_FUNC_RESET;
5228 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5229 reset_level = HNS3_FLR_RESET;
5231 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5232 return HNS3_NONE_RESET;
5238 hns3_prepare_reset(struct hns3_adapter *hns)
5240 struct hns3_hw *hw = &hns->hw;
5244 switch (hw->reset.level) {
5245 case HNS3_FUNC_RESET:
5246 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5251 * After performaning pf reset, it is not necessary to do the
5252 * mailbox handling or send any command to firmware, because
5253 * any mailbox handling or command to firmware is only valid
5254 * after hns3_cmd_init is called.
5256 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5257 hw->reset.stats.request_cnt++;
5259 case HNS3_IMP_RESET:
5260 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5261 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5262 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5271 hns3_set_rst_done(struct hns3_hw *hw)
5273 struct hns3_pf_rst_done_cmd *req;
5274 struct hns3_cmd_desc desc;
5276 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5277 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5278 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5279 return hns3_cmd_send(hw, &desc, 1);
5283 hns3_stop_service(struct hns3_adapter *hns)
5285 struct hns3_hw *hw = &hns->hw;
5286 struct rte_eth_dev *eth_dev;
5288 eth_dev = &rte_eth_devices[hw->data->port_id];
5289 if (hw->adapter_state == HNS3_NIC_STARTED)
5290 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5291 hw->mac.link_status = ETH_LINK_DOWN;
5293 hns3_set_rxtx_function(eth_dev);
5295 /* Disable datapath on secondary process. */
5296 hns3_mp_req_stop_rxtx(eth_dev);
5297 rte_delay_ms(hw->tqps_num);
5299 rte_spinlock_lock(&hw->lock);
5300 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5301 hw->adapter_state == HNS3_NIC_STOPPING) {
5303 hw->reset.mbuf_deferred_free = true;
5305 hw->reset.mbuf_deferred_free = false;
5308 * It is cumbersome for hardware to pick-and-choose entries for deletion
5309 * from table space. Hence, for function reset software intervention is
5310 * required to delete the entries
5312 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5313 hns3_configure_all_mc_mac_addr(hns, true);
5314 rte_spinlock_unlock(&hw->lock);
5320 hns3_start_service(struct hns3_adapter *hns)
5322 struct hns3_hw *hw = &hns->hw;
5323 struct rte_eth_dev *eth_dev;
5325 if (hw->reset.level == HNS3_IMP_RESET ||
5326 hw->reset.level == HNS3_GLOBAL_RESET)
5327 hns3_set_rst_done(hw);
5328 eth_dev = &rte_eth_devices[hw->data->port_id];
5329 hns3_set_rxtx_function(eth_dev);
5330 hns3_mp_req_start_rxtx(eth_dev);
5331 if (hw->adapter_state == HNS3_NIC_STARTED) {
5332 hns3_service_handler(eth_dev);
5334 /* Enable interrupt of all rx queues before enabling queues */
5335 hns3_dev_all_rx_queue_intr_enable(hw, true);
5337 * When finished the initialization, enable queues to receive
5338 * and transmit packets.
5340 hns3_enable_all_queues(hw, true);
5347 hns3_restore_conf(struct hns3_adapter *hns)
5349 struct hns3_hw *hw = &hns->hw;
5352 ret = hns3_configure_all_mac_addr(hns, false);
5356 ret = hns3_configure_all_mc_mac_addr(hns, false);
5360 ret = hns3_dev_promisc_restore(hns);
5364 ret = hns3_restore_vlan_table(hns);
5368 ret = hns3_restore_vlan_conf(hns);
5372 ret = hns3_restore_all_fdir_filter(hns);
5376 ret = hns3_restore_rx_interrupt(hw);
5380 ret = hns3_restore_gro_conf(hw);
5384 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5385 ret = hns3_do_start(hns, false);
5388 hns3_info(hw, "hns3 dev restart successful!");
5389 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5390 hw->adapter_state = HNS3_NIC_CONFIGURED;
5394 hns3_configure_all_mc_mac_addr(hns, true);
5396 hns3_configure_all_mac_addr(hns, true);
5401 hns3_reset_service(void *param)
5403 struct hns3_adapter *hns = (struct hns3_adapter *)param;
5404 struct hns3_hw *hw = &hns->hw;
5405 enum hns3_reset_level reset_level;
5406 struct timeval tv_delta;
5407 struct timeval tv_start;
5413 * The interrupt is not triggered within the delay time.
5414 * The interrupt may have been lost. It is necessary to handle
5415 * the interrupt to recover from the error.
5417 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5418 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5419 hns3_err(hw, "Handling interrupts in delayed tasks");
5420 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5421 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5422 if (reset_level == HNS3_NONE_RESET) {
5423 hns3_err(hw, "No reset level is set, try IMP reset");
5424 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5427 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5430 * Check if there is any ongoing reset in the hardware. This status can
5431 * be checked from reset_pending. If there is then, we need to wait for
5432 * hardware to complete reset.
5433 * a. If we are able to figure out in reasonable time that hardware
5434 * has fully resetted then, we can proceed with driver, client
5436 * b. else, we can come back later to check this status so re-sched
5439 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5440 if (reset_level != HNS3_NONE_RESET) {
5441 gettimeofday(&tv_start, NULL);
5442 ret = hns3_reset_process(hns, reset_level);
5443 gettimeofday(&tv, NULL);
5444 timersub(&tv, &tv_start, &tv_delta);
5445 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5446 tv_delta.tv_usec / USEC_PER_MSEC;
5447 if (msec > HNS3_RESET_PROCESS_MS)
5448 hns3_err(hw, "%d handle long time delta %" PRIx64
5449 " ms time=%ld.%.6ld",
5450 hw->reset.level, msec,
5451 tv.tv_sec, tv.tv_usec);
5456 /* Check if we got any *new* reset requests to be honored */
5457 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5458 if (reset_level != HNS3_NONE_RESET)
5459 hns3_msix_process(hns, reset_level);
5462 static const struct eth_dev_ops hns3_eth_dev_ops = {
5463 .dev_start = hns3_dev_start,
5464 .dev_stop = hns3_dev_stop,
5465 .dev_close = hns3_dev_close,
5466 .promiscuous_enable = hns3_dev_promiscuous_enable,
5467 .promiscuous_disable = hns3_dev_promiscuous_disable,
5468 .allmulticast_enable = hns3_dev_allmulticast_enable,
5469 .allmulticast_disable = hns3_dev_allmulticast_disable,
5470 .mtu_set = hns3_dev_mtu_set,
5471 .stats_get = hns3_stats_get,
5472 .stats_reset = hns3_stats_reset,
5473 .xstats_get = hns3_dev_xstats_get,
5474 .xstats_get_names = hns3_dev_xstats_get_names,
5475 .xstats_reset = hns3_dev_xstats_reset,
5476 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
5477 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5478 .dev_infos_get = hns3_dev_infos_get,
5479 .fw_version_get = hns3_fw_version_get,
5480 .rx_queue_setup = hns3_rx_queue_setup,
5481 .tx_queue_setup = hns3_tx_queue_setup,
5482 .rx_queue_release = hns3_dev_rx_queue_release,
5483 .tx_queue_release = hns3_dev_tx_queue_release,
5484 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
5485 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
5486 .rxq_info_get = hns3_rxq_info_get,
5487 .txq_info_get = hns3_txq_info_get,
5488 .dev_configure = hns3_dev_configure,
5489 .flow_ctrl_get = hns3_flow_ctrl_get,
5490 .flow_ctrl_set = hns3_flow_ctrl_set,
5491 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5492 .mac_addr_add = hns3_add_mac_addr,
5493 .mac_addr_remove = hns3_remove_mac_addr,
5494 .mac_addr_set = hns3_set_default_mac_addr,
5495 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
5496 .link_update = hns3_dev_link_update,
5497 .rss_hash_update = hns3_dev_rss_hash_update,
5498 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
5499 .reta_update = hns3_dev_rss_reta_update,
5500 .reta_query = hns3_dev_rss_reta_query,
5501 .filter_ctrl = hns3_dev_filter_ctrl,
5502 .vlan_filter_set = hns3_vlan_filter_set,
5503 .vlan_tpid_set = hns3_vlan_tpid_set,
5504 .vlan_offload_set = hns3_vlan_offload_set,
5505 .vlan_pvid_set = hns3_vlan_pvid_set,
5506 .get_reg = hns3_get_regs,
5507 .get_dcb_info = hns3_get_dcb_info,
5508 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5511 static const struct hns3_reset_ops hns3_reset_ops = {
5512 .reset_service = hns3_reset_service,
5513 .stop_service = hns3_stop_service,
5514 .prepare_reset = hns3_prepare_reset,
5515 .wait_hardware_ready = hns3_wait_hardware_ready,
5516 .reinit_dev = hns3_reinit_dev,
5517 .restore_conf = hns3_restore_conf,
5518 .start_service = hns3_start_service,
5522 hns3_dev_init(struct rte_eth_dev *eth_dev)
5524 struct hns3_adapter *hns = eth_dev->data->dev_private;
5525 struct hns3_hw *hw = &hns->hw;
5528 PMD_INIT_FUNC_TRACE();
5530 eth_dev->process_private = (struct hns3_process_private *)
5531 rte_zmalloc_socket("hns3_filter_list",
5532 sizeof(struct hns3_process_private),
5533 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5534 if (eth_dev->process_private == NULL) {
5535 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5538 /* initialize flow filter lists */
5539 hns3_filterlist_init(eth_dev);
5541 hns3_set_rxtx_function(eth_dev);
5542 eth_dev->dev_ops = &hns3_eth_dev_ops;
5543 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5544 ret = hns3_mp_init_secondary();
5546 PMD_INIT_LOG(ERR, "Failed to init for secondary "
5547 "process, ret = %d", ret);
5548 goto err_mp_init_secondary;
5551 hw->secondary_cnt++;
5555 ret = hns3_mp_init_primary();
5558 "Failed to init for primary process, ret = %d",
5560 goto err_mp_init_primary;
5563 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5565 hw->data = eth_dev->data;
5568 * Set default max packet size according to the mtu
5569 * default vale in DPDK frame.
5571 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5573 ret = hns3_reset_init(hw);
5575 goto err_init_reset;
5576 hw->reset.ops = &hns3_reset_ops;
5578 ret = hns3_init_pf(eth_dev);
5580 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5584 /* Allocate memory for storing MAC addresses */
5585 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5586 sizeof(struct rte_ether_addr) *
5587 HNS3_UC_MACADDR_NUM, 0);
5588 if (eth_dev->data->mac_addrs == NULL) {
5589 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5590 "to store MAC addresses",
5591 sizeof(struct rte_ether_addr) *
5592 HNS3_UC_MACADDR_NUM);
5594 goto err_rte_zmalloc;
5597 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5598 ð_dev->data->mac_addrs[0]);
5600 hw->adapter_state = HNS3_NIC_INITIALIZED;
5602 * Pass the information to the rte_eth_dev_close() that it should also
5603 * release the private port resources.
5605 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5607 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5608 hns3_err(hw, "Reschedule reset service after dev_init");
5609 hns3_schedule_reset(hns);
5611 /* IMP will wait ready flag before reset */
5612 hns3_notify_reset_ready(hw, false);
5615 hns3_info(hw, "hns3 dev initialization successful!");
5619 hns3_uninit_pf(eth_dev);
5622 rte_free(hw->reset.wait_data);
5625 hns3_mp_uninit_primary();
5627 err_mp_init_primary:
5628 err_mp_init_secondary:
5629 eth_dev->dev_ops = NULL;
5630 eth_dev->rx_pkt_burst = NULL;
5631 eth_dev->tx_pkt_burst = NULL;
5632 eth_dev->tx_pkt_prepare = NULL;
5633 rte_free(eth_dev->process_private);
5634 eth_dev->process_private = NULL;
5639 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5641 struct hns3_adapter *hns = eth_dev->data->dev_private;
5642 struct hns3_hw *hw = &hns->hw;
5644 PMD_INIT_FUNC_TRACE();
5646 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5649 eth_dev->dev_ops = NULL;
5650 eth_dev->rx_pkt_burst = NULL;
5651 eth_dev->tx_pkt_burst = NULL;
5652 eth_dev->tx_pkt_prepare = NULL;
5653 if (hw->adapter_state < HNS3_NIC_CLOSING)
5654 hns3_dev_close(eth_dev);
5656 hw->adapter_state = HNS3_NIC_REMOVED;
5661 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5662 struct rte_pci_device *pci_dev)
5664 return rte_eth_dev_pci_generic_probe(pci_dev,
5665 sizeof(struct hns3_adapter),
5670 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5672 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5675 static const struct rte_pci_id pci_id_hns3_map[] = {
5676 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5677 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5678 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5679 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5680 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5681 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5682 { .vendor_id = 0, /* sentinel */ },
5685 static struct rte_pci_driver rte_hns3_pmd = {
5686 .id_table = pci_id_hns3_map,
5687 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5688 .probe = eth_hns3_pci_probe,
5689 .remove = eth_hns3_pci_remove,
5692 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5693 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5694 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5695 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5696 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);