drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, the PF-related vf_id is 0, just need to configure parameters
 478          * for vport_id 0.
 479          */
 480         vport_id = 0;
 481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 483         req->vf_bitmap[req->vf_offset] = bitmap;
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 488         return ret;
 489 }
 490
 491 static void
 492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_rx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 497 }
 498
 499 static void
 500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 501                            struct hns3_tx_vtag_cfg *vcfg)
 502 {
 503         struct hns3_pf *pf = &hns->pf;
 504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 505 }
 506
 507 static int
 508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 509 {
 510         struct hns3_rx_vtag_cfg rxvlan_cfg;
 511         struct hns3_pf *pf = &hns->pf;
 512         struct hns3_hw *hw = &hns->hw;
 513         int ret;
 514
 515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 516                 rxvlan_cfg.strip_tag1_en = false;
 517                 rxvlan_cfg.strip_tag2_en = enable;
 518         } else {
 519                 rxvlan_cfg.strip_tag1_en = enable;
 520                 rxvlan_cfg.strip_tag2_en = true;
 521         }
 522
 523         rxvlan_cfg.vlan1_vlan_prionly = false;
 524         rxvlan_cfg.vlan2_vlan_prionly = false;
 525         rxvlan_cfg.rx_vlan_offload_en = enable;
 526
 527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 528         if (ret) {
 529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 530                 return ret;
 531         }
 532
 533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 541 {
 542         struct hns3_vlan_filter_ctrl_cmd *req;
 543         struct hns3_cmd_desc desc;
 544         int ret;
 545
 546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 547
 548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 549         req->vlan_type = vlan_type;
 550         req->vlan_fe = filter_en ? fe_type : 0;
 551         req->vf_id = vf_id;
 552
 553         ret = hns3_cmd_send(hw, &desc, 1);
 554         if (ret)
 555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 556
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_vlan_filter_init(struct hns3_adapter *hns)
 562 {
 563         struct hns3_hw *hw = &hns->hw;
 564         int ret;
 565
 566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 567                                         HNS3_FILTER_FE_EGRESS, false, 0);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false, 0);
 575         if (ret)
 576                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 577
 578         return ret;
 579 }
 580
 581 static int
 582 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 583 {
 584         struct hns3_hw *hw = &hns->hw;
 585         int ret;
 586
 587         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 588                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 589         if (ret)
 590                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 591                          enable ? "enable" : "disable", ret);
 592
 593         return ret;
 594 }
 595
 596 static int
 597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 598 {
 599         struct hns3_adapter *hns = dev->data->dev_private;
 600         struct hns3_hw *hw = &hns->hw;
 601         struct rte_eth_rxmode *rxmode;
 602         unsigned int tmp_mask;
 603         bool enable;
 604         int ret = 0;
 605
 606         rte_spinlock_lock(&hw->lock);
 607         rxmode = &dev->data->dev_conf.rxmode;
 608         tmp_mask = (unsigned int)mask;
 609         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 610                 /* ignore vlan filter configuration during promiscuous mode */
 611                 if (!dev->data->promiscuous) {
 612                         /* Enable or disable VLAN filter */
 613                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 614                                  true : false;
 615
 616                         ret = hns3_enable_vlan_filter(hns, enable);
 617                         if (ret) {
 618                                 rte_spinlock_unlock(&hw->lock);
 619                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 620                                          enable ? "enable" : "disable", ret);
 621                                 return ret;
 622                         }
 623                 }
 624         }
 625
 626         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 627                 /* Enable or disable VLAN stripping */
 628                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 629                     true : false;
 630
 631                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 632                 if (ret) {
 633                         rte_spinlock_unlock(&hw->lock);
 634                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 635                                  enable ? "enable" : "disable", ret);
 636                         return ret;
 637                 }
 638         }
 639
 640         rte_spinlock_unlock(&hw->lock);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 647                              struct hns3_tx_vtag_cfg *vcfg)
 648 {
 649         struct hns3_vport_vtag_tx_cfg_cmd *req;
 650         struct hns3_cmd_desc desc;
 651         struct hns3_hw *hw = &hns->hw;
 652         uint16_t vport_id;
 653         uint8_t bitmap;
 654         int ret;
 655
 656         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 657
 658         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 659         req->def_vlan_tag1 = vcfg->default_tag1;
 660         req->def_vlan_tag2 = vcfg->default_tag2;
 661         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 662                      vcfg->accept_tag1 ? 1 : 0);
 663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 664                      vcfg->accept_untag1 ? 1 : 0);
 665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 666                      vcfg->accept_tag2 ? 1 : 0);
 667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 668                      vcfg->accept_untag2 ? 1 : 0);
 669         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 670                      vcfg->insert_tag1_en ? 1 : 0);
 671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 672                      vcfg->insert_tag2_en ? 1 : 0);
 673         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 674
 675         /*
 676          * In current version VF is not supported when PF is driven by DPDK
 677          * driver, the PF-related vf_id is 0, just need to configure parameters
 678          * for vport_id 0.
 679          */
 680         vport_id = 0;
 681         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 682         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 683         req->vf_bitmap[req->vf_offset] = bitmap;
 684
 685         ret = hns3_cmd_send(hw, &desc, 1);
 686         if (ret)
 687                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 688
 689         return ret;
 690 }
 691
 692 static int
 693 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 694                      uint16_t pvid)
 695 {
 696         struct hns3_hw *hw = &hns->hw;
 697         struct hns3_tx_vtag_cfg txvlan_cfg;
 698         int ret;
 699
 700         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 701                 txvlan_cfg.accept_tag1 = true;
 702                 txvlan_cfg.insert_tag1_en = false;
 703                 txvlan_cfg.default_tag1 = 0;
 704         } else {
 705                 txvlan_cfg.accept_tag1 = false;
 706                 txvlan_cfg.insert_tag1_en = true;
 707                 txvlan_cfg.default_tag1 = pvid;
 708         }
 709
 710         txvlan_cfg.accept_untag1 = true;
 711         txvlan_cfg.accept_tag2 = true;
 712         txvlan_cfg.accept_untag2 = true;
 713         txvlan_cfg.insert_tag2_en = false;
 714         txvlan_cfg.default_tag2 = 0;
 715
 716         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 717         if (ret) {
 718                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 719                          ret);
 720                 return ret;
 721         }
 722
 723         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 724         return ret;
 725 }
 726
 727 static void
 728 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 729 {
 730         struct hns3_pf *pf = &hns->pf;
 731
 732         pf->port_base_vlan_cfg.state = on ?
 733             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 734
 735         pf->port_base_vlan_cfg.pvid = pvid;
 736 }
 737
 738 static void
 739 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 740 {
 741         struct hns3_user_vlan_table *vlan_entry;
 742         struct hns3_pf *pf = &hns->pf;
 743
 744         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 745                 if (vlan_entry->hd_tbl_status)
 746                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 747
 748                 vlan_entry->hd_tbl_status = false;
 749         }
 750
 751         if (is_del_list) {
 752                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 while (vlan_entry) {
 754                         LIST_REMOVE(vlan_entry, next);
 755                         rte_free(vlan_entry);
 756                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 757                 }
 758         }
 759 }
 760
 761 static void
 762 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 763 {
 764         struct hns3_user_vlan_table *vlan_entry;
 765         struct hns3_pf *pf = &hns->pf;
 766
 767         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 768                 if (!vlan_entry->hd_tbl_status)
 769                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 770
 771                 vlan_entry->hd_tbl_status = true;
 772         }
 773 }
 774
 775 static void
 776 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 777 {
 778         struct hns3_hw *hw = &hns->hw;
 779         struct hns3_pf *pf = &hns->pf;
 780         int ret;
 781
 782         hns3_rm_all_vlan_table(hns, true);
 783         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 784                 ret = hns3_set_port_vlan_filter(hns,
 785                                                 pf->port_base_vlan_cfg.pvid, 0);
 786                 if (ret) {
 787                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 788                                  ret);
 789                         return;
 790                 }
 791         }
 792 }
 793
 794 static int
 795 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 796                                 uint16_t port_base_vlan_state,
 797                                 uint16_t new_pvid, uint16_t old_pvid)
 798 {
 799         struct hns3_pf *pf = &hns->pf;
 800         struct hns3_hw *hw = &hns->hw;
 801         int ret = 0;
 802
 803         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 804                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 805                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 806                         if (ret) {
 807                                 hns3_err(hw,
 808                                          "Failed to clear clear old pvid filter, ret =%d",
 809                                          ret);
 810                                 return ret;
 811                         }
 812                 }
 813
 814                 hns3_rm_all_vlan_table(hns, false);
 815                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 816         }
 817
 818         if (new_pvid != 0) {
 819                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 820                 if (ret) {
 821                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 822                                  ret);
 823                         return ret;
 824                 }
 825         }
 826
 827         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 828                 hns3_add_all_vlan_table(hns);
 829
 830         return ret;
 831 }
 832
 833 static int
 834 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 835 {
 836         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 837         struct hns3_hw *hw = &hns->hw;
 838         bool rx_strip_en;
 839         int ret;
 840
 841         rx_strip_en = on ? true : false;
 842         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 843         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 844         rx_vlan_cfg.vlan1_vlan_prionly = false;
 845         rx_vlan_cfg.vlan2_vlan_prionly = false;
 846         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 847
 848         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 849         if (ret) {
 850                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 851                 return ret;
 852         }
 853
 854         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 855         return ret;
 856 }
 857
 858 static int
 859 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 860 {
 861         struct hns3_pf *pf = &hns->pf;
 862         struct hns3_hw *hw = &hns->hw;
 863         uint16_t port_base_vlan_state;
 864         uint16_t old_pvid;
 865         int ret;
 866
 867         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 868                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 869                         hns3_warn(hw, "Invalid operation! As current pvid set "
 870                                   "is %u, disable pvid %u is invalid",
 871                                   pf->port_base_vlan_cfg.pvid, pvid);
 872                 return 0;
 873         }
 874
 875         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 876                                     HNS3_PORT_BASE_VLAN_DISABLE;
 877         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 878         if (ret) {
 879                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 880                 return ret;
 881         }
 882
 883         ret = hns3_en_rx_strip_all(hns, on);
 884         if (ret) {
 885                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 886                 return ret;
 887         }
 888
 889         if (pvid == HNS3_INVLID_PVID)
 890                 goto out;
 891         old_pvid = pf->port_base_vlan_cfg.pvid;
 892         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 893                                               old_pvid);
 894         if (ret) {
 895                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 896                          ret);
 897                 return ret;
 898         }
 899
 900 out:
 901         hns3_store_port_base_vlan_info(hns, pvid, on);
 902         return ret;
 903 }
 904
 905 static int
 906 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 907 {
 908         struct hns3_adapter *hns = dev->data->dev_private;
 909         struct hns3_hw *hw = &hns->hw;
 910         int ret;
 911
 912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 914                          RTE_ETHER_MAX_VLAN_ID);
 915                 return -EINVAL;
 916         }
 917
 918         rte_spinlock_lock(&hw->lock);
 919         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 920         rte_spinlock_unlock(&hw->lock);
 921         return ret;
 922 }
 923
 924 static void
 925 init_port_base_vlan_info(struct hns3_hw *hw)
 926 {
 927         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 928         struct hns3_pf *pf = &hns->pf;
 929
 930         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 931         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 932 }
 933
 934 static int
 935 hns3_default_vlan_config(struct hns3_adapter *hns)
 936 {
 937         struct hns3_hw *hw = &hns->hw;
 938         int ret;
 939
 940         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 941         if (ret)
 942                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 943         return ret;
 944 }
 945
 946 static int
 947 hns3_init_vlan_config(struct hns3_adapter *hns)
 948 {
 949         struct hns3_hw *hw = &hns->hw;
 950         int ret;
 951
 952         /*
 953          * This function can be called in the initialization and reset process,
 954          * when in reset process, it means that hardware had been reseted
 955          * successfully and we need to restore the hardware configuration to
 956          * ensure that the hardware configuration remains unchanged before and
 957          * after reset.
 958          */
 959         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 960                 init_port_base_vlan_info(hw);
 961
 962         ret = hns3_vlan_filter_init(hns);
 963         if (ret) {
 964                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 969                                        RTE_ETHER_TYPE_VLAN);
 970         if (ret) {
 971                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 972                 return ret;
 973         }
 974
 975         /*
 976          * When in the reinit dev stage of the reset process, the following
 977          * vlan-related configurations may differ from those at initialization,
 978          * we will restore configurations to hardware in hns3_restore_vlan_table
 979          * and hns3_restore_vlan_conf later.
 980          */
 981         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 982                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 983                 if (ret) {
 984                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 985                         return ret;
 986                 }
 987
 988                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 989                 if (ret) {
 990                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 991                                  ret);
 992                         return ret;
 993                 }
 994         }
 995
 996         return hns3_default_vlan_config(hns);
 997 }
 998
 999 static int
1000 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1001 {
1002         struct hns3_pf *pf = &hns->pf;
1003         struct hns3_hw *hw = &hns->hw;
1004         uint64_t offloads;
1005         bool enable;
1006         int ret;
1007
1008         if (!hw->data->promiscuous) {
1009                 /* restore vlan filter states */
1010                 offloads = hw->data->dev_conf.rxmode.offloads;
1011                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1012                 ret = hns3_enable_vlan_filter(hns, enable);
1013                 if (ret) {
1014                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1015                                  "ret = %d", ret);
1016                         return ret;
1017                 }
1018         }
1019
1020         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1021         if (ret) {
1022                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1023                 return ret;
1024         }
1025
1026         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1027         if (ret)
1028                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1029
1030         return ret;
1031 }
1032
1033 static int
1034 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1035 {
1036         struct hns3_adapter *hns = dev->data->dev_private;
1037         struct rte_eth_dev_data *data = dev->data;
1038         struct rte_eth_txmode *txmode;
1039         struct hns3_hw *hw = &hns->hw;
1040         int mask;
1041         int ret;
1042
1043         txmode = &data->dev_conf.txmode;
1044         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1045                 hns3_warn(hw,
1046                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1047                           "configuration is not supported! Ignore these two "
1048                           "parameters: hw_vlan_reject_tagged(%d), "
1049                           "hw_vlan_reject_untagged(%d)",
1050                           txmode->hw_vlan_reject_tagged,
1051                           txmode->hw_vlan_reject_untagged);
1052
1053         /* Apply vlan offload setting */
1054         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1055         ret = hns3_vlan_offload_set(dev, mask);
1056         if (ret) {
1057                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1058                          ret);
1059                 return ret;
1060         }
1061
1062         /* Apply pvid setting */
1063         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1064                                  txmode->hw_vlan_insert_pvid);
1065         if (ret)
1066                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1067                          txmode->pvid, ret);
1068
1069         return ret;
1070 }
1071
1072 static int
1073 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1074                 unsigned int tso_mss_max)
1075 {
1076         struct hns3_cfg_tso_status_cmd *req;
1077         struct hns3_cmd_desc desc;
1078         uint16_t tso_mss;
1079
1080         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1081
1082         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1083
1084         tso_mss = 0;
1085         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1086                        tso_mss_min);
1087         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1088
1089         tso_mss = 0;
1090         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1091                        tso_mss_max);
1092         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1093
1094         return hns3_cmd_send(hw, &desc, 1);
1095 }
1096
1097 int
1098 hns3_config_gro(struct hns3_hw *hw, bool en)
1099 {
1100         struct hns3_cfg_gro_status_cmd *req;
1101         struct hns3_cmd_desc desc;
1102         int ret;
1103
1104         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1105         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1106
1107         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1108
1109         ret = hns3_cmd_send(hw, &desc, 1);
1110         if (ret)
1111                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1112
1113         return ret;
1114 }
1115
1116 static int
1117 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1118                    uint16_t *allocated_size, bool is_alloc)
1119 {
1120         struct hns3_umv_spc_alc_cmd *req;
1121         struct hns3_cmd_desc desc;
1122         int ret;
1123
1124         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1125         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1126         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1127         req->space_size = rte_cpu_to_le_32(space_size);
1128
1129         ret = hns3_cmd_send(hw, &desc, 1);
1130         if (ret) {
1131                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1132                              is_alloc ? "allocate" : "free", ret);
1133                 return ret;
1134         }
1135
1136         if (is_alloc && allocated_size)
1137                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1138
1139         return 0;
1140 }
1141
1142 static int
1143 hns3_init_umv_space(struct hns3_hw *hw)
1144 {
1145         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1146         struct hns3_pf *pf = &hns->pf;
1147         uint16_t allocated_size = 0;
1148         int ret;
1149
1150         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1151                                  true);
1152         if (ret)
1153                 return ret;
1154
1155         if (allocated_size < pf->wanted_umv_size)
1156                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1157                              pf->wanted_umv_size, allocated_size);
1158
1159         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1160                                                 pf->wanted_umv_size;
1161         pf->used_umv_size = 0;
1162         return 0;
1163 }
1164
1165 static int
1166 hns3_uninit_umv_space(struct hns3_hw *hw)
1167 {
1168         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169         struct hns3_pf *pf = &hns->pf;
1170         int ret;
1171
1172         if (pf->max_umv_size == 0)
1173                 return 0;
1174
1175         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1176         if (ret)
1177                 return ret;
1178
1179         pf->max_umv_size = 0;
1180
1181         return 0;
1182 }
1183
1184 static bool
1185 hns3_is_umv_space_full(struct hns3_hw *hw)
1186 {
1187         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1188         struct hns3_pf *pf = &hns->pf;
1189         bool is_full;
1190
1191         is_full = (pf->used_umv_size >= pf->max_umv_size);
1192
1193         return is_full;
1194 }
1195
1196 static void
1197 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1198 {
1199         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1200         struct hns3_pf *pf = &hns->pf;
1201
1202         if (is_free) {
1203                 if (pf->used_umv_size > 0)
1204                         pf->used_umv_size--;
1205         } else
1206                 pf->used_umv_size++;
1207 }
1208
1209 static void
1210 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1211                       const uint8_t *addr, bool is_mc)
1212 {
1213         const unsigned char *mac_addr = addr;
1214         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1215                             ((uint32_t)mac_addr[2] << 16) |
1216                             ((uint32_t)mac_addr[1] << 8) |
1217                             (uint32_t)mac_addr[0];
1218         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1219
1220         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1221         if (is_mc) {
1222                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1223                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1224                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1225         }
1226
1227         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1228         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1229 }
1230
1231 static int
1232 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1233                              uint8_t resp_code,
1234                              enum hns3_mac_vlan_tbl_opcode op)
1235 {
1236         if (cmdq_resp) {
1237                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1238                          cmdq_resp);
1239                 return -EIO;
1240         }
1241
1242         if (op == HNS3_MAC_VLAN_ADD) {
1243                 if (resp_code == 0 || resp_code == 1) {
1244                         return 0;
1245                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1246                         hns3_err(hw, "add mac addr failed for uc_overflow");
1247                         return -ENOSPC;
1248                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1249                         hns3_err(hw, "add mac addr failed for mc_overflow");
1250                         return -ENOSPC;
1251                 }
1252
1253                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1254                          resp_code);
1255                 return -EIO;
1256         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1257                 if (resp_code == 0) {
1258                         return 0;
1259                 } else if (resp_code == 1) {
1260                         hns3_dbg(hw, "remove mac addr failed for miss");
1261                         return -ENOENT;
1262                 }
1263
1264                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1265                          resp_code);
1266                 return -EIO;
1267         } else if (op == HNS3_MAC_VLAN_LKUP) {
1268                 if (resp_code == 0) {
1269                         return 0;
1270                 } else if (resp_code == 1) {
1271                         hns3_dbg(hw, "lookup mac addr failed for miss");
1272                         return -ENOENT;
1273                 }
1274
1275                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1276                          resp_code);
1277                 return -EIO;
1278         }
1279
1280         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1281                  op);
1282
1283         return -EINVAL;
1284 }
1285
1286 static int
1287 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1288                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1289                          struct hns3_cmd_desc *desc, bool is_mc)
1290 {
1291         uint8_t resp_code;
1292         uint16_t retval;
1293         int ret;
1294
1295         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1296         if (is_mc) {
1297                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298                 memcpy(desc[0].data, req,
1299                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1300                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1301                                           true);
1302                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1303                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1304                                           true);
1305                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1306         } else {
1307                 memcpy(desc[0].data, req,
1308                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1309                 ret = hns3_cmd_send(hw, desc, 1);
1310         }
1311         if (ret) {
1312                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1313                          ret);
1314                 return ret;
1315         }
1316         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1317         retval = rte_le_to_cpu_16(desc[0].retval);
1318
1319         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1320                                             HNS3_MAC_VLAN_LKUP);
1321 }
1322
1323 static int
1324 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1325                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1326                       struct hns3_cmd_desc *mc_desc)
1327 {
1328         uint8_t resp_code;
1329         uint16_t retval;
1330         int cfg_status;
1331         int ret;
1332
1333         if (mc_desc == NULL) {
1334                 struct hns3_cmd_desc desc;
1335
1336                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1337                 memcpy(desc.data, req,
1338                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1339                 ret = hns3_cmd_send(hw, &desc, 1);
1340                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1341                 retval = rte_le_to_cpu_16(desc.retval);
1342
1343                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1344                                                           HNS3_MAC_VLAN_ADD);
1345         } else {
1346                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1347                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1348                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1349                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1351                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1352                 memcpy(mc_desc[0].data, req,
1353                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1354                 mc_desc[0].retval = 0;
1355                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1356                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1357                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1358
1359                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1360                                                           HNS3_MAC_VLAN_ADD);
1361         }
1362
1363         if (ret) {
1364                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1365                 return ret;
1366         }
1367
1368         return cfg_status;
1369 }
1370
1371 static int
1372 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1373                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1374 {
1375         struct hns3_cmd_desc desc;
1376         uint8_t resp_code;
1377         uint16_t retval;
1378         int ret;
1379
1380         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1381
1382         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1383
1384         ret = hns3_cmd_send(hw, &desc, 1);
1385         if (ret) {
1386                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc.retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_REMOVE);
1394 }
1395
1396 static int
1397 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1398 {
1399         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1400         struct hns3_mac_vlan_tbl_entry_cmd req;
1401         struct hns3_pf *pf = &hns->pf;
1402         struct hns3_cmd_desc desc;
1403         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1404         uint16_t egress_port = 0;
1405         uint8_t vf_id;
1406         int ret;
1407
1408         /* check if mac addr is valid */
1409         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1410                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1411                                       mac_addr);
1412                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1413                          mac_str);
1414                 return -EINVAL;
1415         }
1416
1417         memset(&req, 0, sizeof(req));
1418
1419         /*
1420          * In current version VF is not supported when PF is driven by DPDK
1421          * driver, the PF-related vf_id is 0, just need to configure parameters
1422          * for vf_id 0.
1423          */
1424         vf_id = 0;
1425         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1426                        HNS3_MAC_EPORT_VFID_S, vf_id);
1427
1428         req.egress_port = rte_cpu_to_le_16(egress_port);
1429
1430         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1431
1432         /*
1433          * Lookup the mac address in the mac_vlan table, and add
1434          * it if the entry is inexistent. Repeated unicast entry
1435          * is not allowed in the mac vlan table.
1436          */
1437         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1438         if (ret == -ENOENT) {
1439                 if (!hns3_is_umv_space_full(hw)) {
1440                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1441                         if (!ret)
1442                                 hns3_update_umv_space(hw, false);
1443                         return ret;
1444                 }
1445
1446                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1447
1448                 return -ENOSPC;
1449         }
1450
1451         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1452
1453         /* check if we just hit the duplicate */
1454         if (ret == 0) {
1455                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1456                 return 0;
1457         }
1458
1459         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1460                  mac_str);
1461
1462         return ret;
1463 }
1464
1465 static int
1466 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1467 {
1468         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1469         struct rte_ether_addr *addr;
1470         int ret;
1471         int i;
1472
1473         for (i = 0; i < hw->mc_addrs_num; i++) {
1474                 addr = &hw->mc_addrs[i];
1475                 /* Check if there are duplicate addresses */
1476                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1477                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1478                                               addr);
1479                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1480                                  "(%s) is added by the set_mc_mac_addr_list "
1481                                  "API", mac_str);
1482                         return -EINVAL;
1483                 }
1484         }
1485
1486         ret = hns3_add_mc_addr(hw, mac_addr);
1487         if (ret) {
1488                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1489                                       mac_addr);
1490                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1491                          mac_str, ret);
1492         }
1493         return ret;
1494 }
1495
1496 static int
1497 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1498 {
1499         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1500         int ret;
1501
1502         ret = hns3_remove_mc_addr(hw, mac_addr);
1503         if (ret) {
1504                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1505                                       mac_addr);
1506                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1507                          mac_str, ret);
1508         }
1509         return ret;
1510 }
1511
1512 static int
1513 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1514                   uint32_t idx, __rte_unused uint32_t pool)
1515 {
1516         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1518         int ret;
1519
1520         rte_spinlock_lock(&hw->lock);
1521
1522         /*
1523          * In hns3 network engine adding UC and MC mac address with different
1524          * commands with firmware. We need to determine whether the input
1525          * address is a UC or a MC address to call different commands.
1526          * By the way, it is recommended calling the API function named
1527          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1528          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1529          * may affect the specifications of UC mac addresses.
1530          */
1531         if (rte_is_multicast_ether_addr(mac_addr))
1532                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1533         else
1534                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1535
1536         if (ret) {
1537                 rte_spinlock_unlock(&hw->lock);
1538                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1539                                       mac_addr);
1540                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1541                          ret);
1542                 return ret;
1543         }
1544
1545         if (idx == 0)
1546                 hw->mac.default_addr_setted = true;
1547         rte_spinlock_unlock(&hw->lock);
1548
1549         return ret;
1550 }
1551
1552 static int
1553 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1554 {
1555         struct hns3_mac_vlan_tbl_entry_cmd req;
1556         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1557         int ret;
1558
1559         /* check if mac addr is valid */
1560         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1561                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562                                       mac_addr);
1563                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1564                          mac_str);
1565                 return -EINVAL;
1566         }
1567
1568         memset(&req, 0, sizeof(req));
1569         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1570         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1571         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1572         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1573                 return 0;
1574         else if (ret == 0)
1575                 hns3_update_umv_space(hw, true);
1576
1577         return ret;
1578 }
1579
1580 static void
1581 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1582 {
1583         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         /* index will be checked by upper level rte interface */
1585         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1586         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1587         int ret;
1588
1589         rte_spinlock_lock(&hw->lock);
1590
1591         if (rte_is_multicast_ether_addr(mac_addr))
1592                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1593         else
1594                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1595         rte_spinlock_unlock(&hw->lock);
1596         if (ret) {
1597                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1598                                       mac_addr);
1599                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1600                          ret);
1601         }
1602 }
1603
1604 static int
1605 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1606                           struct rte_ether_addr *mac_addr)
1607 {
1608         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct rte_ether_addr *oaddr;
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         bool default_addr_setted;
1612         bool rm_succes = false;
1613         int ret, ret_val;
1614
1615         /*
1616          * It has been guaranteed that input parameter named mac_addr is valid
1617          * address in the rte layer of DPDK framework.
1618          */
1619         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1620         default_addr_setted = hw->mac.default_addr_setted;
1621         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1622                 return 0;
1623
1624         rte_spinlock_lock(&hw->lock);
1625         if (default_addr_setted) {
1626                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1627                 if (ret) {
1628                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                               oaddr);
1630                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1631                                   mac_str, ret);
1632                         rm_succes = false;
1633                 } else
1634                         rm_succes = true;
1635         }
1636
1637         ret = hns3_add_uc_addr_common(hw, mac_addr);
1638         if (ret) {
1639                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1640                                       mac_addr);
1641                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1642                 goto err_add_uc_addr;
1643         }
1644
1645         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1646         if (ret) {
1647                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1648                 goto err_pause_addr_cfg;
1649         }
1650
1651         rte_ether_addr_copy(mac_addr,
1652                             (struct rte_ether_addr *)hw->mac.mac_addr);
1653         hw->mac.default_addr_setted = true;
1654         rte_spinlock_unlock(&hw->lock);
1655
1656         return 0;
1657
1658 err_pause_addr_cfg:
1659         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1660         if (ret_val) {
1661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1662                                       mac_addr);
1663                 hns3_warn(hw,
1664                           "Failed to roll back to del setted mac addr(%s): %d",
1665                           mac_str, ret_val);
1666         }
1667
1668 err_add_uc_addr:
1669         if (rm_succes) {
1670                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1671                 if (ret_val) {
1672                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1673                                               oaddr);
1674                         hns3_warn(hw,
1675                                   "Failed to restore old uc mac addr(%s): %d",
1676                                   mac_str, ret_val);
1677                         hw->mac.default_addr_setted = false;
1678                 }
1679         }
1680         rte_spinlock_unlock(&hw->lock);
1681
1682         return ret;
1683 }
1684
1685 static int
1686 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1687 {
1688         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1689         struct hns3_hw *hw = &hns->hw;
1690         struct rte_ether_addr *addr;
1691         int err = 0;
1692         int ret;
1693         int i;
1694
1695         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1696                 addr = &hw->data->mac_addrs[i];
1697                 if (rte_is_zero_ether_addr(addr))
1698                         continue;
1699                 if (rte_is_multicast_ether_addr(addr))
1700                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1701                               hns3_add_mc_addr(hw, addr);
1702                 else
1703                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1704                               hns3_add_uc_addr_common(hw, addr);
1705
1706                 if (ret) {
1707                         err = ret;
1708                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1709                                               addr);
1710                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1711                                  "ret = %d.", del ? "remove" : "restore",
1712                                  mac_str, i, ret);
1713                 }
1714         }
1715         return err;
1716 }
1717
1718 static void
1719 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1720 {
1721 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1722         uint8_t word_num;
1723         uint8_t bit_num;
1724
1725         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1726                 word_num = vfid / 32;
1727                 bit_num = vfid % 32;
1728                 if (clr)
1729                         desc[1].data[word_num] &=
1730                             rte_cpu_to_le_32(~(1UL << bit_num));
1731                 else
1732                         desc[1].data[word_num] |=
1733                             rte_cpu_to_le_32(1UL << bit_num);
1734         } else {
1735                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1736                 bit_num = vfid % 32;
1737                 if (clr)
1738                         desc[2].data[word_num] &=
1739                             rte_cpu_to_le_32(~(1UL << bit_num));
1740                 else
1741                         desc[2].data[word_num] |=
1742                             rte_cpu_to_le_32(1UL << bit_num);
1743         }
1744 }
1745
1746 static int
1747 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1748 {
1749         struct hns3_mac_vlan_tbl_entry_cmd req;
1750         struct hns3_cmd_desc desc[3];
1751         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752         uint8_t vf_id;
1753         int ret;
1754
1755         /* Check if mac addr is valid */
1756         if (!rte_is_multicast_ether_addr(mac_addr)) {
1757                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1758                                       mac_addr);
1759                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1760                          mac_str);
1761                 return -EINVAL;
1762         }
1763
1764         memset(&req, 0, sizeof(req));
1765         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1766         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1767         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1768         if (ret) {
1769                 /* This mac addr do not exist, add new entry for it */
1770                 memset(desc[0].data, 0, sizeof(desc[0].data));
1771                 memset(desc[1].data, 0, sizeof(desc[0].data));
1772                 memset(desc[2].data, 0, sizeof(desc[0].data));
1773         }
1774
1775         /*
1776          * In current version VF is not supported when PF is driven by DPDK
1777          * driver, the PF-related vf_id is 0, just need to configure parameters
1778          * for vf_id 0.
1779          */
1780         vf_id = 0;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, the PF-related vf_id is 0, just need to
1821                  * configure parameters for vf_id 0.
1822                  */
1823                 vf_id = 0;
1824                 hns3_update_desc_vfid(desc, vf_id, true);
1825
1826                 /* All the vfid is zero, so need to delete this entry */
1827                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1828         } else if (ret == -ENOENT) {
1829                 /* This mac addr doesn't exist. */
1830                 return 0;
1831         }
1832
1833         if (ret) {
1834                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1835                                       mac_addr);
1836                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1837         }
1838
1839         return ret;
1840 }
1841
1842 static int
1843 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1844                            struct rte_ether_addr *mc_addr_set,
1845                            uint32_t nb_mc_addr)
1846 {
1847         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1848         struct rte_ether_addr *addr;
1849         uint32_t i;
1850         uint32_t j;
1851
1852         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1853                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1854                          "invalid. valid range: 0~%d",
1855                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1856                 return -EINVAL;
1857         }
1858
1859         /* Check if input mac addresses are valid */
1860         for (i = 0; i < nb_mc_addr; i++) {
1861                 addr = &mc_addr_set[i];
1862                 if (!rte_is_multicast_ether_addr(addr)) {
1863                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1864                                               addr);
1865                         hns3_err(hw,
1866                                  "failed to set mc mac addr, addr(%s) invalid.",
1867                                  mac_str);
1868                         return -EINVAL;
1869                 }
1870
1871                 /* Check if there are duplicate addresses */
1872                 for (j = i + 1; j < nb_mc_addr; j++) {
1873                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1874                                 rte_ether_format_addr(mac_str,
1875                                                       RTE_ETHER_ADDR_FMT_SIZE,
1876                                                       addr);
1877                                 hns3_err(hw, "failed to set mc mac addr, "
1878                                          "addrs invalid. two same addrs(%s).",
1879                                          mac_str);
1880                                 return -EINVAL;
1881                         }
1882                 }
1883
1884                 /*
1885                  * Check if there are duplicate addresses between mac_addrs
1886                  * and mc_addr_set
1887                  */
1888                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1889                         if (rte_is_same_ether_addr(addr,
1890                                                    &hw->data->mac_addrs[j])) {
1891                                 rte_ether_format_addr(mac_str,
1892                                                       RTE_ETHER_ADDR_FMT_SIZE,
1893                                                       addr);
1894                                 hns3_err(hw, "failed to set mc mac addr, "
1895                                          "addrs invalid. addrs(%s) has already "
1896                                          "configured in mac_addr add API",
1897                                          mac_str);
1898                                 return -EINVAL;
1899                         }
1900                 }
1901         }
1902
1903         return 0;
1904 }
1905
1906 static void
1907 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1908                            struct rte_ether_addr *mc_addr_set,
1909                            int mc_addr_num,
1910                            struct rte_ether_addr *reserved_addr_list,
1911                            int *reserved_addr_num,
1912                            struct rte_ether_addr *add_addr_list,
1913                            int *add_addr_num,
1914                            struct rte_ether_addr *rm_addr_list,
1915                            int *rm_addr_num)
1916 {
1917         struct rte_ether_addr *addr;
1918         int current_addr_num;
1919         int reserved_num = 0;
1920         int add_num = 0;
1921         int rm_num = 0;
1922         int num;
1923         int i;
1924         int j;
1925         bool same_addr;
1926
1927         /* Calculate the mc mac address list that should be removed */
1928         current_addr_num = hw->mc_addrs_num;
1929         for (i = 0; i < current_addr_num; i++) {
1930                 addr = &hw->mc_addrs[i];
1931                 same_addr = false;
1932                 for (j = 0; j < mc_addr_num; j++) {
1933                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1934                                 same_addr = true;
1935                                 break;
1936                         }
1937                 }
1938
1939                 if (!same_addr) {
1940                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1941                         rm_num++;
1942                 } else {
1943                         rte_ether_addr_copy(addr,
1944                                             &reserved_addr_list[reserved_num]);
1945                         reserved_num++;
1946                 }
1947         }
1948
1949         /* Calculate the mc mac address list that should be added */
1950         for (i = 0; i < mc_addr_num; i++) {
1951                 addr = &mc_addr_set[i];
1952                 same_addr = false;
1953                 for (j = 0; j < current_addr_num; j++) {
1954                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1955                                 same_addr = true;
1956                                 break;
1957                         }
1958                 }
1959
1960                 if (!same_addr) {
1961                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1962                         add_num++;
1963                 }
1964         }
1965
1966         /* Reorder the mc mac address list maintained by driver */
1967         for (i = 0; i < reserved_num; i++)
1968                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1969
1970         for (i = 0; i < rm_num; i++) {
1971                 num = reserved_num + i;
1972                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1973         }
1974
1975         *reserved_addr_num = reserved_num;
1976         *add_addr_num = add_num;
1977         *rm_addr_num = rm_num;
1978 }
1979
1980 static int
1981 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1982                           struct rte_ether_addr *mc_addr_set,
1983                           uint32_t nb_mc_addr)
1984 {
1985         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1989         struct rte_ether_addr *addr;
1990         int reserved_addr_num;
1991         int add_addr_num;
1992         int rm_addr_num;
1993         int mc_addr_num;
1994         int num;
1995         int ret;
1996         int i;
1997
1998         /* Check if input parameters are valid */
1999         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2000         if (ret)
2001                 return ret;
2002
2003         rte_spinlock_lock(&hw->lock);
2004
2005         /*
2006          * Calculate the mc mac address lists those should be removed and be
2007          * added, Reorder the mc mac address list maintained by driver.
2008          */
2009         mc_addr_num = (int)nb_mc_addr;
2010         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2011                                    reserved_addr_list, &reserved_addr_num,
2012                                    add_addr_list, &add_addr_num,
2013                                    rm_addr_list, &rm_addr_num);
2014
2015         /* Remove mc mac addresses */
2016         for (i = 0; i < rm_addr_num; i++) {
2017                 num = rm_addr_num - i - 1;
2018                 addr = &rm_addr_list[num];
2019                 ret = hns3_remove_mc_addr(hw, addr);
2020                 if (ret) {
2021                         rte_spinlock_unlock(&hw->lock);
2022                         return ret;
2023                 }
2024                 hw->mc_addrs_num--;
2025         }
2026
2027         /* Add mc mac addresses */
2028         for (i = 0; i < add_addr_num; i++) {
2029                 addr = &add_addr_list[i];
2030                 ret = hns3_add_mc_addr(hw, addr);
2031                 if (ret) {
2032                         rte_spinlock_unlock(&hw->lock);
2033                         return ret;
2034                 }
2035
2036                 num = reserved_addr_num + i;
2037                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2038                 hw->mc_addrs_num++;
2039         }
2040         rte_spinlock_unlock(&hw->lock);
2041
2042         return 0;
2043 }
2044
2045 static int
2046 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2047 {
2048         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2049         struct hns3_hw *hw = &hns->hw;
2050         struct rte_ether_addr *addr;
2051         int err = 0;
2052         int ret;
2053         int i;
2054
2055         for (i = 0; i < hw->mc_addrs_num; i++) {
2056                 addr = &hw->mc_addrs[i];
2057                 if (!rte_is_multicast_ether_addr(addr))
2058                         continue;
2059                 if (del)
2060                         ret = hns3_remove_mc_addr(hw, addr);
2061                 else
2062                         ret = hns3_add_mc_addr(hw, addr);
2063                 if (ret) {
2064                         err = ret;
2065                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2066                                               addr);
2067                         hns3_dbg(hw, "%s mc mac addr: %s failed",
2068                                  del ? "Remove" : "Restore", mac_str);
2069                 }
2070         }
2071         return err;
2072 }
2073
2074 static int
2075 hns3_check_mq_mode(struct rte_eth_dev *dev)
2076 {
2077         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2078         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2079         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2081         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2082         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2083         uint8_t num_tc;
2084         int max_tc = 0;
2085         int i;
2086
2087         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2088         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2089
2090         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2091                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2092                          "rx_mq_mode = %d", rx_mq_mode);
2093                 return -EINVAL;
2094         }
2095
2096         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2097             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2098                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2099                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2100                          rx_mq_mode, tx_mq_mode);
2101                 return -EINVAL;
2102         }
2103
2104         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2105                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2106                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2107                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2108                         return -EINVAL;
2109                 }
2110
2111                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2112                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2113                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2114                                  "nb_tcs(%d) != %d or %d in rx direction.",
2115                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2116                         return -EINVAL;
2117                 }
2118
2119                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2120                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2121                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2122                         return -EINVAL;
2123                 }
2124
2125                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2126                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2127                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2128                                          "is not equal to one in tx direction.",
2129                                          i, dcb_rx_conf->dcb_tc[i]);
2130                                 return -EINVAL;
2131                         }
2132                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2133                                 max_tc = dcb_rx_conf->dcb_tc[i];
2134                 }
2135
2136                 num_tc = max_tc + 1;
2137                 if (num_tc > dcb_rx_conf->nb_tcs) {
2138                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2139                                  num_tc, dcb_rx_conf->nb_tcs);
2140                         return -EINVAL;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147 static int
2148 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2149 {
2150         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151
2152         if (!hns3_dev_dcb_supported(hw)) {
2153                 hns3_err(hw, "this port does not support dcb configurations.");
2154                 return -EOPNOTSUPP;
2155         }
2156
2157         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2158                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2159                 return -EOPNOTSUPP;
2160         }
2161
2162         /* Check multiple queue mode */
2163         return hns3_check_mq_mode(dev);
2164 }
2165
2166 static int
2167 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2168                            enum hns3_ring_type queue_type, uint16_t queue_id)
2169 {
2170         struct hns3_cmd_desc desc;
2171         struct hns3_ctrl_vector_chain_cmd *req =
2172                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2173         enum hns3_cmd_status status;
2174         enum hns3_opcode_type op;
2175         uint16_t tqp_type_and_id = 0;
2176         const char *op_str;
2177         uint16_t type;
2178         uint16_t gl;
2179
2180         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2181         hns3_cmd_setup_basic_desc(&desc, op, false);
2182         req->int_vector_id = vector_id;
2183
2184         if (queue_type == HNS3_RING_TYPE_RX)
2185                 gl = HNS3_RING_GL_RX;
2186         else
2187                 gl = HNS3_RING_GL_TX;
2188
2189         type = queue_type;
2190
2191         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2192                        type);
2193         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2194         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2195                        gl);
2196         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2197         req->int_cause_num = 1;
2198         op_str = mmap ? "Map" : "Unmap";
2199         status = hns3_cmd_send(hw, &desc, 1);
2200         if (status) {
2201                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2202                          op_str, queue_id, req->int_vector_id, status);
2203                 return status;
2204         }
2205
2206         return 0;
2207 }
2208
2209 static int
2210 hns3_init_ring_with_vector(struct hns3_hw *hw)
2211 {
2212         uint8_t vec;
2213         int ret;
2214         int i;
2215
2216         /*
2217          * In hns3 network engine, vector 0 is always the misc interrupt of this
2218          * function, vector 1~N can be used respectively for the queues of the
2219          * function. Tx and Rx queues with the same number share the interrupt
2220          * vector. In the initialization clearing the all hardware mapping
2221          * relationship configurations between queues and interrupt vectors is
2222          * needed, so some error caused by the residual configurations, such as
2223          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2224          * constraints in hns3 hardware engine, we have to implement clearing
2225          * the mapping relationship configurations by binding all queues to the
2226          * last interrupt vector and reserving the last interrupt vector. This
2227          * method results in a decrease of the maximum queues when upper
2228          * applications call the rte_eth_dev_configure API function to enable
2229          * Rx interrupt.
2230          */
2231         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2232         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2233         for (i = 0; i < hw->intr_tqps_num; i++) {
2234                 /*
2235                  * Set gap limiter and rate limiter configuration of queue's
2236                  * interrupt.
2237                  */
2238                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239                                        HNS3_TQP_INTR_GL_DEFAULT);
2240                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241                                        HNS3_TQP_INTR_GL_DEFAULT);
2242                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2243
2244                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245                                                  HNS3_RING_TYPE_TX, i);
2246                 if (ret) {
2247                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248                                           "vector: %d, ret=%d", i, vec, ret);
2249                         return ret;
2250                 }
2251
2252                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253                                                  HNS3_RING_TYPE_RX, i);
2254                 if (ret) {
2255                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256                                           "vector: %d, ret=%d", i, vec, ret);
2257                         return ret;
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2266 {
2267         struct hns3_adapter *hns = dev->data->dev_private;
2268         struct rte_eth_conf *conf = &dev->data->dev_conf;
2269         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270         struct hns3_hw *hw = &hns->hw;
2271         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274         struct rte_eth_rss_conf rss_conf;
2275         uint16_t mtu;
2276         int ret;
2277
2278         /*
2279          * Hardware does not support individually enable/disable/reset the Tx or
2280          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2281          * and Rx queues at the same time. When the numbers of Tx queues
2282          * allocated by upper applications are not equal to the numbers of Rx
2283          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2284          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2285          * these fake queues are imperceptible, and can not be used by upper
2286          * applications.
2287          */
2288         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2289         if (ret) {
2290                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2291                 return ret;
2292         }
2293
2294         hw->adapter_state = HNS3_NIC_CONFIGURING;
2295         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2296                 hns3_err(hw, "setting link speed/duplex not supported");
2297                 ret = -EINVAL;
2298                 goto cfg_err;
2299         }
2300
2301         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2302                 ret = hns3_check_dcb_cfg(dev);
2303                 if (ret)
2304                         goto cfg_err;
2305         }
2306
2307         /* When RSS is not configured, redirect the packet queue 0 */
2308         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2309                 rss_conf = conf->rx_adv_conf.rss_conf;
2310                 if (rss_conf.rss_key == NULL) {
2311                         rss_conf.rss_key = rss_cfg->key;
2312                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2313                 }
2314
2315                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2316                 if (ret)
2317                         goto cfg_err;
2318         }
2319
2320         /*
2321          * If jumbo frames are enabled, MTU needs to be refreshed
2322          * according to the maximum RX packet length.
2323          */
2324         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2325                 /*
2326                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2327                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2328                  * can safely assign to "uint16_t" type variable.
2329                  */
2330                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2331                 ret = hns3_dev_mtu_set(dev, mtu);
2332                 if (ret)
2333                         goto cfg_err;
2334                 dev->data->mtu = mtu;
2335         }
2336
2337         ret = hns3_dev_configure_vlan(dev);
2338         if (ret)
2339                 goto cfg_err;
2340
2341         hw->adapter_state = HNS3_NIC_CONFIGURED;
2342
2343         return 0;
2344
2345 cfg_err:
2346         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2347         hw->adapter_state = HNS3_NIC_INITIALIZED;
2348
2349         return ret;
2350 }
2351
2352 static int
2353 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2354 {
2355         struct hns3_config_max_frm_size_cmd *req;
2356         struct hns3_cmd_desc desc;
2357
2358         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2359
2360         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2361         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2362         req->min_frm_size = RTE_ETHER_MIN_LEN;
2363
2364         return hns3_cmd_send(hw, &desc, 1);
2365 }
2366
2367 static int
2368 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2369 {
2370         int ret;
2371
2372         ret = hns3_set_mac_mtu(hw, mps);
2373         if (ret) {
2374                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2375                 return ret;
2376         }
2377
2378         ret = hns3_buffer_alloc(hw);
2379         if (ret)
2380                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2381
2382         return ret;
2383 }
2384
2385 static int
2386 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2387 {
2388         struct hns3_adapter *hns = dev->data->dev_private;
2389         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2390         struct hns3_hw *hw = &hns->hw;
2391         bool is_jumbo_frame;
2392         int ret;
2393
2394         if (dev->data->dev_started) {
2395                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2396                          "before configuration", dev->data->port_id);
2397                 return -EBUSY;
2398         }
2399
2400         rte_spinlock_lock(&hw->lock);
2401         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2402         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2403
2404         /*
2405          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2406          * assign to "uint16_t" type variable.
2407          */
2408         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2409         if (ret) {
2410                 rte_spinlock_unlock(&hw->lock);
2411                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2412                          dev->data->port_id, mtu, ret);
2413                 return ret;
2414         }
2415         hns->pf.mps = (uint16_t)frame_size;
2416         if (is_jumbo_frame)
2417                 dev->data->dev_conf.rxmode.offloads |=
2418                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2419         else
2420                 dev->data->dev_conf.rxmode.offloads &=
2421                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2422         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2423         rte_spinlock_unlock(&hw->lock);
2424
2425         return 0;
2426 }
2427
2428 static int
2429 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2430 {
2431         struct hns3_adapter *hns = eth_dev->data->dev_private;
2432         struct hns3_hw *hw = &hns->hw;
2433         uint16_t queue_num = hw->tqps_num;
2434
2435         /*
2436          * In interrupt mode, 'max_rx_queues' is set based on the number of
2437          * MSI-X interrupt resources of the hardware.
2438          */
2439         if (hw->data->dev_conf.intr_conf.rxq == 1)
2440                 queue_num = hw->intr_tqps_num;
2441
2442         info->max_rx_queues = queue_num;
2443         info->max_tx_queues = hw->tqps_num;
2444         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2445         info->min_rx_bufsize = hw->rx_buf_len;
2446         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2447         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2448         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2449                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2450                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2451                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2452                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2453                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2454                                  DEV_RX_OFFLOAD_KEEP_CRC |
2455                                  DEV_RX_OFFLOAD_SCATTER |
2456                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2457                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2458                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2459                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2460                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2461                                  DEV_RX_OFFLOAD_RSS_HASH);
2462         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2463         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2464                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2465                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2466                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2467                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2468                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2469                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2470                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2471                                  DEV_TX_OFFLOAD_TCP_TSO |
2472                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2473                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2474                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2475                                  info->tx_queue_offload_capa);
2476
2477         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2478                 .nb_max = HNS3_MAX_RING_DESC,
2479                 .nb_min = HNS3_MIN_RING_DESC,
2480                 .nb_align = HNS3_ALIGN_RING_DESC,
2481         };
2482
2483         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2484                 .nb_max = HNS3_MAX_RING_DESC,
2485                 .nb_min = HNS3_MIN_RING_DESC,
2486                 .nb_align = HNS3_ALIGN_RING_DESC,
2487         };
2488
2489         info->vmdq_queue_num = 0;
2490
2491         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2492         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2493         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2494
2495         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2496         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2497         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2498         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2499         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2500         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2501
2502         return 0;
2503 }
2504
2505 static int
2506 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2507                     size_t fw_size)
2508 {
2509         struct hns3_adapter *hns = eth_dev->data->dev_private;
2510         struct hns3_hw *hw = &hns->hw;
2511         int ret;
2512
2513         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2514         ret += 1; /* add the size of '\0' */
2515         if (fw_size < (uint32_t)ret)
2516                 return ret;
2517         else
2518                 return 0;
2519 }
2520
2521 static int
2522 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2523                      __rte_unused int wait_to_complete)
2524 {
2525         struct hns3_adapter *hns = eth_dev->data->dev_private;
2526         struct hns3_hw *hw = &hns->hw;
2527         struct hns3_mac *mac = &hw->mac;
2528         struct rte_eth_link new_link;
2529
2530         if (!hns3_is_reset_pending(hns)) {
2531                 hns3_update_speed_duplex(eth_dev);
2532                 hns3_update_link_status(hw);
2533         }
2534
2535         memset(&new_link, 0, sizeof(new_link));
2536         switch (mac->link_speed) {
2537         case ETH_SPEED_NUM_10M:
2538         case ETH_SPEED_NUM_100M:
2539         case ETH_SPEED_NUM_1G:
2540         case ETH_SPEED_NUM_10G:
2541         case ETH_SPEED_NUM_25G:
2542         case ETH_SPEED_NUM_40G:
2543         case ETH_SPEED_NUM_50G:
2544         case ETH_SPEED_NUM_100G:
2545                 new_link.link_speed = mac->link_speed;
2546                 break;
2547         default:
2548                 new_link.link_speed = ETH_SPEED_NUM_100M;
2549                 break;
2550         }
2551
2552         new_link.link_duplex = mac->link_duplex;
2553         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2554         new_link.link_autoneg =
2555             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2556
2557         return rte_eth_linkstatus_set(eth_dev, &new_link);
2558 }
2559
2560 static int
2561 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2562 {
2563         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2564         struct hns3_pf *pf = &hns->pf;
2565
2566         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2567                 return -EINVAL;
2568
2569         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2570
2571         return 0;
2572 }
2573
2574 static int
2575 hns3_query_function_status(struct hns3_hw *hw)
2576 {
2577 #define HNS3_QUERY_MAX_CNT              10
2578 #define HNS3_QUERY_SLEEP_MSCOEND        1
2579         struct hns3_func_status_cmd *req;
2580         struct hns3_cmd_desc desc;
2581         int timeout = 0;
2582         int ret;
2583
2584         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2585         req = (struct hns3_func_status_cmd *)desc.data;
2586
2587         do {
2588                 ret = hns3_cmd_send(hw, &desc, 1);
2589                 if (ret) {
2590                         PMD_INIT_LOG(ERR, "query function status failed %d",
2591                                      ret);
2592                         return ret;
2593                 }
2594
2595                 /* Check pf reset is done */
2596                 if (req->pf_state)
2597                         break;
2598
2599                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2600         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2601
2602         return hns3_parse_func_status(hw, req);
2603 }
2604
2605 static int
2606 hns3_query_pf_resource(struct hns3_hw *hw)
2607 {
2608         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2609         struct hns3_pf *pf = &hns->pf;
2610         struct hns3_pf_res_cmd *req;
2611         struct hns3_cmd_desc desc;
2612         uint16_t num_msi;
2613         int ret;
2614
2615         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2616         ret = hns3_cmd_send(hw, &desc, 1);
2617         if (ret) {
2618                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2619                 return ret;
2620         }
2621
2622         req = (struct hns3_pf_res_cmd *)desc.data;
2623         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2624         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2625         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2626         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2627
2628         if (req->tx_buf_size)
2629                 pf->tx_buf_size =
2630                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2631         else
2632                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2633
2634         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2635
2636         if (req->dv_buf_size)
2637                 pf->dv_buf_size =
2638                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2639         else
2640                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2641
2642         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2643
2644         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2645                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2646         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2647
2648         return 0;
2649 }
2650
2651 static void
2652 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2653 {
2654         struct hns3_cfg_param_cmd *req;
2655         uint64_t mac_addr_tmp_high;
2656         uint64_t mac_addr_tmp;
2657         uint32_t i;
2658
2659         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2660
2661         /* get the configuration */
2662         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2663                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2664         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2665                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2666         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2667                                            HNS3_CFG_TQP_DESC_N_M,
2668                                            HNS3_CFG_TQP_DESC_N_S);
2669
2670         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2671                                        HNS3_CFG_PHY_ADDR_M,
2672                                        HNS3_CFG_PHY_ADDR_S);
2673         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2674                                          HNS3_CFG_MEDIA_TP_M,
2675                                          HNS3_CFG_MEDIA_TP_S);
2676         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2677                                          HNS3_CFG_RX_BUF_LEN_M,
2678                                          HNS3_CFG_RX_BUF_LEN_S);
2679         /* get mac address */
2680         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2681         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2682                                            HNS3_CFG_MAC_ADDR_H_M,
2683                                            HNS3_CFG_MAC_ADDR_H_S);
2684
2685         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2686
2687         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2688                                             HNS3_CFG_DEFAULT_SPEED_M,
2689                                             HNS3_CFG_DEFAULT_SPEED_S);
2690         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2691                                            HNS3_CFG_RSS_SIZE_M,
2692                                            HNS3_CFG_RSS_SIZE_S);
2693
2694         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2695                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2696
2697         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2698         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2699
2700         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2701                                             HNS3_CFG_SPEED_ABILITY_M,
2702                                             HNS3_CFG_SPEED_ABILITY_S);
2703         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2704                                         HNS3_CFG_UMV_TBL_SPACE_M,
2705                                         HNS3_CFG_UMV_TBL_SPACE_S);
2706         if (!cfg->umv_space)
2707                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2708 }
2709
2710 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2711  * @hw: pointer to struct hns3_hw
2712  * @hcfg: the config structure to be getted
2713  */
2714 static int
2715 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2716 {
2717         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2718         struct hns3_cfg_param_cmd *req;
2719         uint32_t offset;
2720         uint32_t i;
2721         int ret;
2722
2723         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2724                 offset = 0;
2725                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2726                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2727                                           true);
2728                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2729                                i * HNS3_CFG_RD_LEN_BYTES);
2730                 /* Len should be divided by 4 when send to hardware */
2731                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2732                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2733                 req->offset = rte_cpu_to_le_32(offset);
2734         }
2735
2736         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2737         if (ret) {
2738                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2739                 return ret;
2740         }
2741
2742         hns3_parse_cfg(hcfg, desc);
2743
2744         return 0;
2745 }
2746
2747 static int
2748 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2749 {
2750         switch (speed_cmd) {
2751         case HNS3_CFG_SPEED_10M:
2752                 *speed = ETH_SPEED_NUM_10M;
2753                 break;
2754         case HNS3_CFG_SPEED_100M:
2755                 *speed = ETH_SPEED_NUM_100M;
2756                 break;
2757         case HNS3_CFG_SPEED_1G:
2758                 *speed = ETH_SPEED_NUM_1G;
2759                 break;
2760         case HNS3_CFG_SPEED_10G:
2761                 *speed = ETH_SPEED_NUM_10G;
2762                 break;
2763         case HNS3_CFG_SPEED_25G:
2764                 *speed = ETH_SPEED_NUM_25G;
2765                 break;
2766         case HNS3_CFG_SPEED_40G:
2767                 *speed = ETH_SPEED_NUM_40G;
2768                 break;
2769         case HNS3_CFG_SPEED_50G:
2770                 *speed = ETH_SPEED_NUM_50G;
2771                 break;
2772         case HNS3_CFG_SPEED_100G:
2773                 *speed = ETH_SPEED_NUM_100G;
2774                 break;
2775         default:
2776                 return -EINVAL;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static int
2783 hns3_get_board_configuration(struct hns3_hw *hw)
2784 {
2785         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2786         struct hns3_pf *pf = &hns->pf;
2787         struct hns3_cfg cfg;
2788         int ret;
2789
2790         ret = hns3_get_board_cfg(hw, &cfg);
2791         if (ret) {
2792                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2793                 return ret;
2794         }
2795
2796         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2797                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2798                 return -EOPNOTSUPP;
2799         }
2800
2801         hw->mac.media_type = cfg.media_type;
2802         hw->rss_size_max = cfg.rss_size_max;
2803         hw->rss_dis_flag = false;
2804         hw->rx_buf_len = cfg.rx_buf_len;
2805         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2806         hw->mac.phy_addr = cfg.phy_addr;
2807         hw->mac.default_addr_setted = false;
2808         hw->num_tx_desc = cfg.tqp_desc_num;
2809         hw->num_rx_desc = cfg.tqp_desc_num;
2810         hw->dcb_info.num_pg = 1;
2811         hw->dcb_info.hw_pfc_map = 0;
2812
2813         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2814         if (ret) {
2815                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2816                              cfg.default_speed, ret);
2817                 return ret;
2818         }
2819
2820         pf->tc_max = cfg.tc_num;
2821         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2822                 PMD_INIT_LOG(WARNING,
2823                              "Get TC num(%u) from flash, set TC num to 1",
2824                              pf->tc_max);
2825                 pf->tc_max = 1;
2826         }
2827
2828         /* Dev does not support DCB */
2829         if (!hns3_dev_dcb_supported(hw)) {
2830                 pf->tc_max = 1;
2831                 pf->pfc_max = 0;
2832         } else
2833                 pf->pfc_max = pf->tc_max;
2834
2835         hw->dcb_info.num_tc = 1;
2836         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2837                                      hw->tqps_num / hw->dcb_info.num_tc);
2838         hns3_set_bit(hw->hw_tc_map, 0, 1);
2839         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2840
2841         pf->wanted_umv_size = cfg.umv_space;
2842
2843         return ret;
2844 }
2845
2846 static int
2847 hns3_get_configuration(struct hns3_hw *hw)
2848 {
2849         int ret;
2850
2851         ret = hns3_query_function_status(hw);
2852         if (ret) {
2853                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2854                 return ret;
2855         }
2856
2857         /* Get pf resource */
2858         ret = hns3_query_pf_resource(hw);
2859         if (ret) {
2860                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2861                 return ret;
2862         }
2863
2864         ret = hns3_get_board_configuration(hw);
2865         if (ret)
2866                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2867
2868         return ret;
2869 }
2870
2871 static int
2872 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2873                       uint16_t tqp_vid, bool is_pf)
2874 {
2875         struct hns3_tqp_map_cmd *req;
2876         struct hns3_cmd_desc desc;
2877         int ret;
2878
2879         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2880
2881         req = (struct hns3_tqp_map_cmd *)desc.data;
2882         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2883         req->tqp_vf = func_id;
2884         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2885         if (!is_pf)
2886                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2887         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2888
2889         ret = hns3_cmd_send(hw, &desc, 1);
2890         if (ret)
2891                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2892
2893         return ret;
2894 }
2895
2896 static int
2897 hns3_map_tqp(struct hns3_hw *hw)
2898 {
2899         uint16_t tqps_num = hw->total_tqps_num;
2900         uint16_t func_id;
2901         uint16_t tqp_id;
2902         bool is_pf;
2903         int num;
2904         int ret;
2905         int i;
2906
2907         /*
2908          * In current version VF is not supported when PF is driven by DPDK
2909          * driver, so we allocate tqps to PF as much as possible.
2910          */
2911         tqp_id = 0;
2912         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2913         for (func_id = 0; func_id < num; func_id++) {
2914                 is_pf = func_id == 0 ? true : false;
2915                 for (i = 0;
2916                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2917                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2918                                                     is_pf);
2919                         if (ret)
2920                                 return ret;
2921                 }
2922         }
2923
2924         return 0;
2925 }
2926
2927 static int
2928 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2929 {
2930         struct hns3_config_mac_speed_dup_cmd *req;
2931         struct hns3_cmd_desc desc;
2932         int ret;
2933
2934         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2935
2936         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2937
2938         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2939
2940         switch (speed) {
2941         case ETH_SPEED_NUM_10M:
2942                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2943                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2944                 break;
2945         case ETH_SPEED_NUM_100M:
2946                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2947                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2948                 break;
2949         case ETH_SPEED_NUM_1G:
2950                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2951                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2952                 break;
2953         case ETH_SPEED_NUM_10G:
2954                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2955                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2956                 break;
2957         case ETH_SPEED_NUM_25G:
2958                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2959                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2960                 break;
2961         case ETH_SPEED_NUM_40G:
2962                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2963                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2964                 break;
2965         case ETH_SPEED_NUM_50G:
2966                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2967                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2968                 break;
2969         case ETH_SPEED_NUM_100G:
2970                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2971                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2972                 break;
2973         default:
2974                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2975                 return -EINVAL;
2976         }
2977
2978         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2979
2980         ret = hns3_cmd_send(hw, &desc, 1);
2981         if (ret)
2982                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2983
2984         return ret;
2985 }
2986
2987 static int
2988 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2989 {
2990         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2991         struct hns3_pf *pf = &hns->pf;
2992         struct hns3_priv_buf *priv;
2993         uint32_t i, total_size;
2994
2995         total_size = pf->pkt_buf_size;
2996
2997         /* alloc tx buffer for all enabled tc */
2998         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2999                 priv = &buf_alloc->priv_buf[i];
3000
3001                 if (hw->hw_tc_map & BIT(i)) {
3002                         if (total_size < pf->tx_buf_size)
3003                                 return -ENOMEM;
3004
3005                         priv->tx_buf_size = pf->tx_buf_size;
3006                 } else
3007                         priv->tx_buf_size = 0;
3008
3009                 total_size -= priv->tx_buf_size;
3010         }
3011
3012         return 0;
3013 }
3014
3015 static int
3016 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3017 {
3018 /* TX buffer size is unit by 128 byte */
3019 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3020 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3021         struct hns3_tx_buff_alloc_cmd *req;
3022         struct hns3_cmd_desc desc;
3023         uint32_t buf_size;
3024         uint32_t i;
3025         int ret;
3026
3027         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3028
3029         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3030         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3031                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3032
3033                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3034                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3035                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3036         }
3037
3038         ret = hns3_cmd_send(hw, &desc, 1);
3039         if (ret)
3040                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3041
3042         return ret;
3043 }
3044
3045 static int
3046 hns3_get_tc_num(struct hns3_hw *hw)
3047 {
3048         int cnt = 0;
3049         uint8_t i;
3050
3051         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3052                 if (hw->hw_tc_map & BIT(i))
3053                         cnt++;
3054         return cnt;
3055 }
3056
3057 static uint32_t
3058 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3059 {
3060         struct hns3_priv_buf *priv;
3061         uint32_t rx_priv = 0;
3062         int i;
3063
3064         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3065                 priv = &buf_alloc->priv_buf[i];
3066                 if (priv->enable)
3067                         rx_priv += priv->buf_size;
3068         }
3069         return rx_priv;
3070 }
3071
3072 static uint32_t
3073 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3074 {
3075         uint32_t total_tx_size = 0;
3076         uint32_t i;
3077
3078         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3079                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3080
3081         return total_tx_size;
3082 }
3083
3084 /* Get the number of pfc enabled TCs, which have private buffer */
3085 static int
3086 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3087 {
3088         struct hns3_priv_buf *priv;
3089         int cnt = 0;
3090         uint8_t i;
3091
3092         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3093                 priv = &buf_alloc->priv_buf[i];
3094                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3095                         cnt++;
3096         }
3097
3098         return cnt;
3099 }
3100
3101 /* Get the number of pfc disabled TCs, which have private buffer */
3102 static int
3103 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3104                          struct hns3_pkt_buf_alloc *buf_alloc)
3105 {
3106         struct hns3_priv_buf *priv;
3107         int cnt = 0;
3108         uint8_t i;
3109
3110         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3111                 priv = &buf_alloc->priv_buf[i];
3112                 if (hw->hw_tc_map & BIT(i) &&
3113                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3114                         cnt++;
3115         }
3116
3117         return cnt;
3118 }
3119
3120 static bool
3121 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3122                   uint32_t rx_all)
3123 {
3124         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3125         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3126         struct hns3_pf *pf = &hns->pf;
3127         uint32_t shared_buf, aligned_mps;
3128         uint32_t rx_priv;
3129         uint8_t tc_num;
3130         uint8_t i;
3131
3132         tc_num = hns3_get_tc_num(hw);
3133         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3134
3135         if (hns3_dev_dcb_supported(hw))
3136                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3137                                         pf->dv_buf_size;
3138         else
3139                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3140                                         + pf->dv_buf_size;
3141
3142         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3143         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3144                              HNS3_BUF_SIZE_UNIT);
3145
3146         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3147         if (rx_all < rx_priv + shared_std)
3148                 return false;
3149
3150         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3151         buf_alloc->s_buf.buf_size = shared_buf;
3152         if (hns3_dev_dcb_supported(hw)) {
3153                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3154                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3155                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3156                                   HNS3_BUF_SIZE_UNIT);
3157         } else {
3158                 buf_alloc->s_buf.self.high =
3159                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3160                 buf_alloc->s_buf.self.low = aligned_mps;
3161         }
3162
3163         if (hns3_dev_dcb_supported(hw)) {
3164                 hi_thrd = shared_buf - pf->dv_buf_size;
3165
3166                 if (tc_num <= NEED_RESERVE_TC_NUM)
3167                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3168                                         / BUF_MAX_PERCENT;
3169
3170                 if (tc_num)
3171                         hi_thrd = hi_thrd / tc_num;
3172
3173                 hi_thrd = max_t(uint32_t, hi_thrd,
3174                                 HNS3_BUF_MUL_BY * aligned_mps);
3175                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3176                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3177         } else {
3178                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3179                 lo_thrd = aligned_mps;
3180         }
3181
3182         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3183                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3184                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3185         }
3186
3187         return true;
3188 }
3189
3190 static bool
3191 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3192                      struct hns3_pkt_buf_alloc *buf_alloc)
3193 {
3194         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3195         struct hns3_pf *pf = &hns->pf;
3196         struct hns3_priv_buf *priv;
3197         uint32_t aligned_mps;
3198         uint32_t rx_all;
3199         uint8_t i;
3200
3201         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3202         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3203
3204         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3205                 priv = &buf_alloc->priv_buf[i];
3206
3207                 priv->enable = 0;
3208                 priv->wl.low = 0;
3209                 priv->wl.high = 0;
3210                 priv->buf_size = 0;
3211
3212                 if (!(hw->hw_tc_map & BIT(i)))
3213                         continue;
3214
3215                 priv->enable = 1;
3216                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3217                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3218                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3219                                                 HNS3_BUF_SIZE_UNIT);
3220                 } else {
3221                         priv->wl.low = 0;
3222                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3223                                         aligned_mps;
3224                 }
3225
3226                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3227         }
3228
3229         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3230 }
3231
3232 static bool
3233 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3234                              struct hns3_pkt_buf_alloc *buf_alloc)
3235 {
3236         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3237         struct hns3_pf *pf = &hns->pf;
3238         struct hns3_priv_buf *priv;
3239         int no_pfc_priv_num;
3240         uint32_t rx_all;
3241         uint8_t mask;
3242         int i;
3243
3244         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3245         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3246
3247         /* let the last to be cleared first */
3248         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3249                 priv = &buf_alloc->priv_buf[i];
3250                 mask = BIT((uint8_t)i);
3251
3252                 if (hw->hw_tc_map & mask &&
3253                     !(hw->dcb_info.hw_pfc_map & mask)) {
3254                         /* Clear the no pfc TC private buffer */
3255                         priv->wl.low = 0;
3256                         priv->wl.high = 0;
3257                         priv->buf_size = 0;
3258                         priv->enable = 0;
3259                         no_pfc_priv_num--;
3260                 }
3261
3262                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3263                     no_pfc_priv_num == 0)
3264                         break;
3265         }
3266
3267         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3268 }
3269
3270 static bool
3271 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3272                            struct hns3_pkt_buf_alloc *buf_alloc)
3273 {
3274         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3275         struct hns3_pf *pf = &hns->pf;
3276         struct hns3_priv_buf *priv;
3277         uint32_t rx_all;
3278         int pfc_priv_num;
3279         uint8_t mask;
3280         int i;
3281
3282         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3283         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3284
3285         /* let the last to be cleared first */
3286         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3287                 priv = &buf_alloc->priv_buf[i];
3288                 mask = BIT((uint8_t)i);
3289
3290                 if (hw->hw_tc_map & mask &&
3291                     hw->dcb_info.hw_pfc_map & mask) {
3292                         /* Reduce the number of pfc TC with private buffer */
3293                         priv->wl.low = 0;
3294                         priv->enable = 0;
3295                         priv->wl.high = 0;
3296                         priv->buf_size = 0;
3297                         pfc_priv_num--;
3298                 }
3299                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3300                     pfc_priv_num == 0)
3301                         break;
3302         }
3303
3304         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3305 }
3306
3307 static bool
3308 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3309                           struct hns3_pkt_buf_alloc *buf_alloc)
3310 {
3311 #define COMPENSATE_BUFFER       0x3C00
3312 #define COMPENSATE_HALF_MPS_NUM 5
3313 #define PRIV_WL_GAP             0x1800
3314         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3315         struct hns3_pf *pf = &hns->pf;
3316         uint32_t tc_num = hns3_get_tc_num(hw);
3317         uint32_t half_mps = pf->mps >> 1;
3318         struct hns3_priv_buf *priv;
3319         uint32_t min_rx_priv;
3320         uint32_t rx_priv;
3321         uint8_t i;
3322
3323         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3324         if (tc_num)
3325                 rx_priv = rx_priv / tc_num;
3326
3327         if (tc_num <= NEED_RESERVE_TC_NUM)
3328                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3329
3330         /*
3331          * Minimum value of private buffer in rx direction (min_rx_priv) is
3332          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3333          * buffer if rx_priv is greater than min_rx_priv.
3334          */
3335         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3336                         COMPENSATE_HALF_MPS_NUM * half_mps;
3337         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3338         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3339
3340         if (rx_priv < min_rx_priv)
3341                 return false;
3342
3343         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3344                 priv = &buf_alloc->priv_buf[i];
3345
3346                 priv->enable = 0;
3347                 priv->wl.low = 0;
3348                 priv->wl.high = 0;
3349                 priv->buf_size = 0;
3350
3351                 if (!(hw->hw_tc_map & BIT(i)))
3352                         continue;
3353
3354                 priv->enable = 1;
3355                 priv->buf_size = rx_priv;
3356                 priv->wl.high = rx_priv - pf->dv_buf_size;
3357                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3358         }
3359
3360         buf_alloc->s_buf.buf_size = 0;
3361
3362         return true;
3363 }
3364
3365 /*
3366  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3367  * @hw: pointer to struct hns3_hw
3368  * @buf_alloc: pointer to buffer calculation data
3369  * @return: 0: calculate sucessful, negative: fail
3370  */
3371 static int
3372 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3373 {
3374         /* When DCB is not supported, rx private buffer is not allocated. */
3375         if (!hns3_dev_dcb_supported(hw)) {
3376                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3377                 struct hns3_pf *pf = &hns->pf;
3378                 uint32_t rx_all = pf->pkt_buf_size;
3379
3380                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3381                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3382                         return -ENOMEM;
3383
3384                 return 0;
3385         }
3386
3387         /*
3388          * Try to allocate privated packet buffer for all TCs without share
3389          * buffer.
3390          */
3391         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3392                 return 0;
3393
3394         /*
3395          * Try to allocate privated packet buffer for all TCs with share
3396          * buffer.
3397          */
3398         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3399                 return 0;
3400
3401         /*
3402          * For different application scenes, the enabled port number, TC number
3403          * and no_drop TC number are different. In order to obtain the better
3404          * performance, software could allocate the buffer size and configure
3405          * the waterline by tring to decrease the private buffer size according
3406          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3407          * enabled tc.
3408          */
3409         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3410                 return 0;
3411
3412         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3413                 return 0;
3414
3415         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3416                 return 0;
3417
3418         return -ENOMEM;
3419 }
3420
3421 static int
3422 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3423 {
3424         struct hns3_rx_priv_buff_cmd *req;
3425         struct hns3_cmd_desc desc;
3426         uint32_t buf_size;
3427         int ret;
3428         int i;
3429
3430         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3431         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3432
3433         /* Alloc private buffer TCs */
3434         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3435                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3436
3437                 req->buf_num[i] =
3438                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3439                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3440         }
3441
3442         buf_size = buf_alloc->s_buf.buf_size;
3443         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3444                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3445
3446         ret = hns3_cmd_send(hw, &desc, 1);
3447         if (ret)
3448                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3449
3450         return ret;
3451 }
3452
3453 static int
3454 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3455 {
3456 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3457         struct hns3_rx_priv_wl_buf *req;
3458         struct hns3_priv_buf *priv;
3459         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3460         int i, j;
3461         int ret;
3462
3463         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3464                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3465                                           false);
3466                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3467
3468                 /* The first descriptor set the NEXT bit to 1 */
3469                 if (i == 0)
3470                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3471                 else
3472                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3473
3474                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3475                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3476
3477                         priv = &buf_alloc->priv_buf[idx];
3478                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3479                                                         HNS3_BUF_UNIT_S);
3480                         req->tc_wl[j].high |=
3481                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3482                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3483                                                         HNS3_BUF_UNIT_S);
3484                         req->tc_wl[j].low |=
3485                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3486                 }
3487         }
3488
3489         /* Send 2 descriptor at one time */
3490         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3491         if (ret)
3492                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3493                              ret);
3494         return ret;
3495 }
3496
3497 static int
3498 hns3_common_thrd_config(struct hns3_hw *hw,
3499                         struct hns3_pkt_buf_alloc *buf_alloc)
3500 {
3501 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3502         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3503         struct hns3_rx_com_thrd *req;
3504         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3505         struct hns3_tc_thrd *tc;
3506         int tc_idx;
3507         int i, j;
3508         int ret;
3509
3510         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3511                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3512                                           false);
3513                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3514
3515                 /* The first descriptor set the NEXT bit to 1 */
3516                 if (i == 0)
3517                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3518                 else
3519                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3520
3521                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3522                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3523                         tc = &s_buf->tc_thrd[tc_idx];
3524
3525                         req->com_thrd[j].high =
3526                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3527                         req->com_thrd[j].high |=
3528                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3529                         req->com_thrd[j].low =
3530                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3531                         req->com_thrd[j].low |=
3532                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3533                 }
3534         }
3535
3536         /* Send 2 descriptors at one time */
3537         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3538         if (ret)
3539                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3540
3541         return ret;
3542 }
3543
3544 static int
3545 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3546 {
3547         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3548         struct hns3_rx_com_wl *req;
3549         struct hns3_cmd_desc desc;
3550         int ret;
3551
3552         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3553
3554         req = (struct hns3_rx_com_wl *)desc.data;
3555         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3556         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3557
3558         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3559         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3560
3561         ret = hns3_cmd_send(hw, &desc, 1);
3562         if (ret)
3563                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3564
3565         return ret;
3566 }
3567
3568 int
3569 hns3_buffer_alloc(struct hns3_hw *hw)
3570 {
3571         struct hns3_pkt_buf_alloc pkt_buf;
3572         int ret;
3573
3574         memset(&pkt_buf, 0, sizeof(pkt_buf));
3575         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3576         if (ret) {
3577                 PMD_INIT_LOG(ERR,
3578                              "could not calc tx buffer size for all TCs %d",
3579                              ret);
3580                 return ret;
3581         }
3582
3583         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3584         if (ret) {
3585                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3586                 return ret;
3587         }
3588
3589         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3590         if (ret) {
3591                 PMD_INIT_LOG(ERR,
3592                              "could not calc rx priv buffer size for all TCs %d",
3593                              ret);
3594                 return ret;
3595         }
3596
3597         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3598         if (ret) {
3599                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3600                 return ret;
3601         }
3602
3603         if (hns3_dev_dcb_supported(hw)) {
3604                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3605                 if (ret) {
3606                         PMD_INIT_LOG(ERR,
3607                                      "could not configure rx private waterline %d",
3608                                      ret);
3609                         return ret;
3610                 }
3611
3612                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3613                 if (ret) {
3614                         PMD_INIT_LOG(ERR,
3615                                      "could not configure common threshold %d",
3616                                      ret);
3617                         return ret;
3618                 }
3619         }
3620
3621         ret = hns3_common_wl_config(hw, &pkt_buf);
3622         if (ret)
3623                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3624                              ret);
3625
3626         return ret;
3627 }
3628
3629 static int
3630 hns3_mac_init(struct hns3_hw *hw)
3631 {
3632         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3633         struct hns3_mac *mac = &hw->mac;
3634         struct hns3_pf *pf = &hns->pf;
3635         int ret;
3636
3637         pf->support_sfp_query = true;
3638         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3639         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3640         if (ret) {
3641                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3642                 return ret;
3643         }
3644
3645         mac->link_status = ETH_LINK_DOWN;
3646
3647         return hns3_config_mtu(hw, pf->mps);
3648 }
3649
3650 static int
3651 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3652 {
3653 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3654 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3655 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3656 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3657         int return_status;
3658
3659         if (cmdq_resp) {
3660                 PMD_INIT_LOG(ERR,
3661                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3662                              cmdq_resp);
3663                 return -EIO;
3664         }
3665
3666         switch (resp_code) {
3667         case HNS3_ETHERTYPE_SUCCESS_ADD:
3668         case HNS3_ETHERTYPE_ALREADY_ADD:
3669                 return_status = 0;
3670                 break;
3671         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3672                 PMD_INIT_LOG(ERR,
3673                              "add mac ethertype failed for manager table overflow.");
3674                 return_status = -EIO;
3675                 break;
3676         case HNS3_ETHERTYPE_KEY_CONFLICT:
3677                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3678                 return_status = -EIO;
3679                 break;
3680         default:
3681                 PMD_INIT_LOG(ERR,
3682                              "add mac ethertype failed for undefined, code=%d.",
3683                              resp_code);
3684                 return_status = -EIO;
3685                 break;
3686         }
3687
3688         return return_status;
3689 }
3690
3691 static int
3692 hns3_add_mgr_tbl(struct hns3_hw *hw,
3693                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3694 {
3695         struct hns3_cmd_desc desc;
3696         uint8_t resp_code;
3697         uint16_t retval;
3698         int ret;
3699
3700         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3701         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3702
3703         ret = hns3_cmd_send(hw, &desc, 1);
3704         if (ret) {
3705                 PMD_INIT_LOG(ERR,
3706                              "add mac ethertype failed for cmd_send, ret =%d.",
3707                              ret);
3708                 return ret;
3709         }
3710
3711         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3712         retval = rte_le_to_cpu_16(desc.retval);
3713
3714         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3715 }
3716
3717 static void
3718 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3719                      int *table_item_num)
3720 {
3721         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3722
3723         /*
3724          * In current version, we add one item in management table as below:
3725          * 0x0180C200000E -- LLDP MC address
3726          */
3727         tbl = mgr_table;
3728         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3729         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3730         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3731         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3732         tbl->i_port_bitmap = 0x1;
3733         *table_item_num = 1;
3734 }
3735
3736 static int
3737 hns3_init_mgr_tbl(struct hns3_hw *hw)
3738 {
3739 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3740         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3741         int table_item_num;
3742         int ret;
3743         int i;
3744
3745         memset(mgr_table, 0, sizeof(mgr_table));
3746         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3747         for (i = 0; i < table_item_num; i++) {
3748                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3749                 if (ret) {
3750                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3751                                      ret);
3752                         return ret;
3753                 }
3754         }
3755
3756         return 0;
3757 }
3758
3759 static void
3760 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3761                         bool en_mc, bool en_bc, int vport_id)
3762 {
3763         if (!param)
3764                 return;
3765
3766         memset(param, 0, sizeof(struct hns3_promisc_param));
3767         if (en_uc)
3768                 param->enable = HNS3_PROMISC_EN_UC;
3769         if (en_mc)
3770                 param->enable |= HNS3_PROMISC_EN_MC;
3771         if (en_bc)
3772                 param->enable |= HNS3_PROMISC_EN_BC;
3773         param->vf_id = vport_id;
3774 }
3775
3776 static int
3777 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3778 {
3779         struct hns3_promisc_cfg_cmd *req;
3780         struct hns3_cmd_desc desc;
3781         int ret;
3782
3783         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3784
3785         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3786         req->vf_id = param->vf_id;
3787         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3788             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3789
3790         ret = hns3_cmd_send(hw, &desc, 1);
3791         if (ret)
3792                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3793
3794         return ret;
3795 }
3796
3797 static int
3798 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3799 {
3800         struct hns3_promisc_param param;
3801         bool en_bc_pmc = true;
3802         uint8_t vf_id;
3803
3804         /*
3805          * In current version VF is not supported when PF is driven by DPDK
3806          * driver, the PF-related vf_id is 0, just need to configure parameters
3807          * for vf_id 0.
3808          */
3809         vf_id = 0;
3810
3811         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3812         return hns3_cmd_set_promisc_mode(hw, &param);
3813 }
3814
3815 static int
3816 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3817 {
3818         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3819         struct hns3_pf *pf = &hns->pf;
3820         struct hns3_promisc_param param;
3821         uint16_t func_id;
3822         int ret;
3823
3824         /* func_id 0 is denoted PF, the VFs start from 1 */
3825         for (func_id = 1; func_id < pf->func_num; func_id++) {
3826                 hns3_promisc_param_init(&param, false, false, false, func_id);
3827                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3828                 if (ret)
3829                         return ret;
3830         }
3831
3832         return 0;
3833 }
3834
3835 static int
3836 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3837 {
3838         bool allmulti = dev->data->all_multicast ? true : false;
3839         struct hns3_adapter *hns = dev->data->dev_private;
3840         struct hns3_hw *hw = &hns->hw;
3841         uint64_t offloads;
3842         int err;
3843         int ret;
3844
3845         rte_spinlock_lock(&hw->lock);
3846         ret = hns3_set_promisc_mode(hw, true, true);
3847         if (ret) {
3848                 rte_spinlock_unlock(&hw->lock);
3849                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3850                          ret);
3851                 return ret;
3852         }
3853
3854         /*
3855          * When promiscuous mode was enabled, disable the vlan filter to let
3856          * all packets coming in in the receiving direction.
3857          */
3858         offloads = dev->data->dev_conf.rxmode.offloads;
3859         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3860                 ret = hns3_enable_vlan_filter(hns, false);
3861                 if (ret) {
3862                         hns3_err(hw, "failed to enable promiscuous mode due to "
3863                                      "failure to disable vlan filter, ret = %d",
3864                                  ret);
3865                         err = hns3_set_promisc_mode(hw, false, allmulti);
3866                         if (err)
3867                                 hns3_err(hw, "failed to restore promiscuous "
3868                                          "status after disable vlan filter "
3869                                          "failed during enabling promiscuous "
3870                                          "mode, ret = %d", ret);
3871                 }
3872         }
3873
3874         rte_spinlock_unlock(&hw->lock);
3875
3876         return ret;
3877 }
3878
3879 static int
3880 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3881 {
3882         bool allmulti = dev->data->all_multicast ? true : false;
3883         struct hns3_adapter *hns = dev->data->dev_private;
3884         struct hns3_hw *hw = &hns->hw;
3885         uint64_t offloads;
3886         int err;
3887         int ret;
3888
3889         /* If now in all_multicast mode, must remain in all_multicast mode. */
3890         rte_spinlock_lock(&hw->lock);
3891         ret = hns3_set_promisc_mode(hw, false, allmulti);
3892         if (ret) {
3893                 rte_spinlock_unlock(&hw->lock);
3894                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3895                          ret);
3896                 return ret;
3897         }
3898         /* when promiscuous mode was disabled, restore the vlan filter status */
3899         offloads = dev->data->dev_conf.rxmode.offloads;
3900         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3901                 ret = hns3_enable_vlan_filter(hns, true);
3902                 if (ret) {
3903                         hns3_err(hw, "failed to disable promiscuous mode due to"
3904                                  " failure to restore vlan filter, ret = %d",
3905                                  ret);
3906                         err = hns3_set_promisc_mode(hw, true, true);
3907                         if (err)
3908                                 hns3_err(hw, "failed to restore promiscuous "
3909                                          "status after enabling vlan filter "
3910                                          "failed during disabling promiscuous "
3911                                          "mode, ret = %d", ret);
3912                 }
3913         }
3914         rte_spinlock_unlock(&hw->lock);
3915
3916         return ret;
3917 }
3918
3919 static int
3920 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3921 {
3922         struct hns3_adapter *hns = dev->data->dev_private;
3923         struct hns3_hw *hw = &hns->hw;
3924         int ret;
3925
3926         if (dev->data->promiscuous)
3927                 return 0;
3928
3929         rte_spinlock_lock(&hw->lock);
3930         ret = hns3_set_promisc_mode(hw, false, true);
3931         rte_spinlock_unlock(&hw->lock);
3932         if (ret)
3933                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3934                          ret);
3935
3936         return ret;
3937 }
3938
3939 static int
3940 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3941 {
3942         struct hns3_adapter *hns = dev->data->dev_private;
3943         struct hns3_hw *hw = &hns->hw;
3944         int ret;
3945
3946         /* If now in promiscuous mode, must remain in all_multicast mode. */
3947         if (dev->data->promiscuous)
3948                 return 0;
3949
3950         rte_spinlock_lock(&hw->lock);
3951         ret = hns3_set_promisc_mode(hw, false, false);
3952         rte_spinlock_unlock(&hw->lock);
3953         if (ret)
3954                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
3955                          ret);
3956
3957         return ret;
3958 }
3959
3960 static int
3961 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3962 {
3963         struct hns3_hw *hw = &hns->hw;
3964         bool allmulti = hw->data->all_multicast ? true : false;
3965         int ret;
3966
3967         if (hw->data->promiscuous) {
3968                 ret = hns3_set_promisc_mode(hw, true, true);
3969                 if (ret)
3970                         hns3_err(hw, "failed to restore promiscuous mode, "
3971                                  "ret = %d", ret);
3972                 return ret;
3973         }
3974
3975         ret = hns3_set_promisc_mode(hw, false, allmulti);
3976         if (ret)
3977                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
3978                          ret);
3979         return ret;
3980 }
3981
3982 static int
3983 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3984 {
3985         struct hns3_sfp_speed_cmd *resp;
3986         struct hns3_cmd_desc desc;
3987         int ret;
3988
3989         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3990         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3991         ret = hns3_cmd_send(hw, &desc, 1);
3992         if (ret == -EOPNOTSUPP) {
3993                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3994                 return ret;
3995         } else if (ret) {
3996                 hns3_err(hw, "get sfp speed failed %d", ret);
3997                 return ret;
3998         }
3999
4000         *speed = resp->sfp_speed;
4001
4002         return 0;
4003 }
4004
4005 static uint8_t
4006 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4007 {
4008         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4009                 duplex = ETH_LINK_FULL_DUPLEX;
4010
4011         return duplex;
4012 }
4013
4014 static int
4015 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4016 {
4017         struct hns3_mac *mac = &hw->mac;
4018         int ret;
4019
4020         duplex = hns3_check_speed_dup(duplex, speed);
4021         if (mac->link_speed == speed && mac->link_duplex == duplex)
4022                 return 0;
4023
4024         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4025         if (ret)
4026                 return ret;
4027
4028         mac->link_speed = speed;
4029         mac->link_duplex = duplex;
4030
4031         return 0;
4032 }
4033
4034 static int
4035 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4036 {
4037         struct hns3_adapter *hns = eth_dev->data->dev_private;
4038         struct hns3_hw *hw = &hns->hw;
4039         struct hns3_pf *pf = &hns->pf;
4040         uint32_t speed;
4041         int ret;
4042
4043         /* If IMP do not support get SFP/qSFP speed, return directly */
4044         if (!pf->support_sfp_query)
4045                 return 0;
4046
4047         ret = hns3_get_sfp_speed(hw, &speed);
4048         if (ret == -EOPNOTSUPP) {
4049                 pf->support_sfp_query = false;
4050                 return ret;
4051         } else if (ret)
4052                 return ret;
4053
4054         if (speed == ETH_SPEED_NUM_NONE)
4055                 return 0; /* do nothing if no SFP */
4056
4057         /* Config full duplex for SFP */
4058         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4059 }
4060
4061 static int
4062 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4063 {
4064         struct hns3_config_mac_mode_cmd *req;
4065         struct hns3_cmd_desc desc;
4066         uint32_t loop_en = 0;
4067         uint8_t val = 0;
4068         int ret;
4069
4070         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4071
4072         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4073         if (enable)
4074                 val = 1;
4075         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4076         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4077         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4078         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4079         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4080         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4081         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4082         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4083         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4084         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4085         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4086         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4087         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4088         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4089         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4090
4091         ret = hns3_cmd_send(hw, &desc, 1);
4092         if (ret)
4093                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4094
4095         return ret;
4096 }
4097
4098 static int
4099 hns3_get_mac_link_status(struct hns3_hw *hw)
4100 {
4101         struct hns3_link_status_cmd *req;
4102         struct hns3_cmd_desc desc;
4103         int link_status;
4104         int ret;
4105
4106         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4107         ret = hns3_cmd_send(hw, &desc, 1);
4108         if (ret) {
4109                 hns3_err(hw, "get link status cmd failed %d", ret);
4110                 return ETH_LINK_DOWN;
4111         }
4112
4113         req = (struct hns3_link_status_cmd *)desc.data;
4114         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4115
4116         return !!link_status;
4117 }
4118
4119 void
4120 hns3_update_link_status(struct hns3_hw *hw)
4121 {
4122         int state;
4123
4124         state = hns3_get_mac_link_status(hw);
4125         if (state != hw->mac.link_status) {
4126                 hw->mac.link_status = state;
4127                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4128         }
4129 }
4130
4131 static void
4132 hns3_service_handler(void *param)
4133 {
4134         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4135         struct hns3_adapter *hns = eth_dev->data->dev_private;
4136         struct hns3_hw *hw = &hns->hw;
4137
4138         if (!hns3_is_reset_pending(hns)) {
4139                 hns3_update_speed_duplex(eth_dev);
4140                 hns3_update_link_status(hw);
4141         } else
4142                 hns3_warn(hw, "Cancel the query when reset is pending");
4143
4144         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4145 }
4146
4147 static int
4148 hns3_init_hardware(struct hns3_adapter *hns)
4149 {
4150         struct hns3_hw *hw = &hns->hw;
4151         int ret;
4152
4153         ret = hns3_map_tqp(hw);
4154         if (ret) {
4155                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4156                 return ret;
4157         }
4158
4159         ret = hns3_init_umv_space(hw);
4160         if (ret) {
4161                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4162                 return ret;
4163         }
4164
4165         ret = hns3_mac_init(hw);
4166         if (ret) {
4167                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4168                 goto err_mac_init;
4169         }
4170
4171         ret = hns3_init_mgr_tbl(hw);
4172         if (ret) {
4173                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4174                 goto err_mac_init;
4175         }
4176
4177         ret = hns3_set_promisc_mode(hw, false, false);
4178         if (ret) {
4179                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4180                 goto err_mac_init;
4181         }
4182
4183         ret = hns3_clear_all_vfs_promisc_mode(hw);
4184         if (ret) {
4185                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4186                              ret);
4187                 goto err_mac_init;
4188         }
4189
4190         ret = hns3_init_vlan_config(hns);
4191         if (ret) {
4192                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4193                 goto err_mac_init;
4194         }
4195
4196         ret = hns3_dcb_init(hw);
4197         if (ret) {
4198                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4199                 goto err_mac_init;
4200         }
4201
4202         ret = hns3_init_fd_config(hns);
4203         if (ret) {
4204                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4205                 goto err_mac_init;
4206         }
4207
4208         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4209         if (ret) {
4210                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4211                 goto err_mac_init;
4212         }
4213
4214         ret = hns3_config_gro(hw, false);
4215         if (ret) {
4216                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4217                 goto err_mac_init;
4218         }
4219
4220         /*
4221          * In the initialization clearing the all hardware mapping relationship
4222          * configurations between queues and interrupt vectors is needed, so
4223          * some error caused by the residual configurations, such as the
4224          * unexpected interrupt, can be avoid.
4225          */
4226         ret = hns3_init_ring_with_vector(hw);
4227         if (ret) {
4228                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4229                 goto err_mac_init;
4230         }
4231
4232         return 0;
4233
4234 err_mac_init:
4235         hns3_uninit_umv_space(hw);
4236         return ret;
4237 }
4238
4239 static int
4240 hns3_init_pf(struct rte_eth_dev *eth_dev)
4241 {
4242         struct rte_device *dev = eth_dev->device;
4243         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4244         struct hns3_adapter *hns = eth_dev->data->dev_private;
4245         struct hns3_hw *hw = &hns->hw;
4246         int ret;
4247
4248         PMD_INIT_FUNC_TRACE();
4249
4250         /* Get hardware io base address from pcie BAR2 IO space */
4251         hw->io_base = pci_dev->mem_resource[2].addr;
4252
4253         /* Firmware command queue initialize */
4254         ret = hns3_cmd_init_queue(hw);
4255         if (ret) {
4256                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4257                 goto err_cmd_init_queue;
4258         }
4259
4260         hns3_clear_all_event_cause(hw);
4261
4262         /* Firmware command initialize */
4263         ret = hns3_cmd_init(hw);
4264         if (ret) {
4265                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4266                 goto err_cmd_init;
4267         }
4268
4269         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4270                                          hns3_interrupt_handler,
4271                                          eth_dev);
4272         if (ret) {
4273                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4274                 goto err_intr_callback_register;
4275         }
4276
4277         /* Enable interrupt */
4278         rte_intr_enable(&pci_dev->intr_handle);
4279         hns3_pf_enable_irq0(hw);
4280
4281         /* Get configuration */
4282         ret = hns3_get_configuration(hw);
4283         if (ret) {
4284                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4285                 goto err_get_config;
4286         }
4287
4288         ret = hns3_init_hardware(hns);
4289         if (ret) {
4290                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4291                 goto err_get_config;
4292         }
4293
4294         /* Initialize flow director filter list & hash */
4295         ret = hns3_fdir_filter_init(hns);
4296         if (ret) {
4297                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4298                 goto err_hw_init;
4299         }
4300
4301         hns3_set_default_rss_args(hw);
4302
4303         ret = hns3_enable_hw_error_intr(hns, true);
4304         if (ret) {
4305                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4306                              ret);
4307                 goto err_fdir;
4308         }
4309
4310         return 0;
4311
4312 err_fdir:
4313         hns3_fdir_filter_uninit(hns);
4314 err_hw_init:
4315         hns3_uninit_umv_space(hw);
4316
4317 err_get_config:
4318         hns3_pf_disable_irq0(hw);
4319         rte_intr_disable(&pci_dev->intr_handle);
4320         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4321                              eth_dev);
4322 err_intr_callback_register:
4323 err_cmd_init:
4324         hns3_cmd_uninit(hw);
4325         hns3_cmd_destroy_queue(hw);
4326 err_cmd_init_queue:
4327         hw->io_base = NULL;
4328
4329         return ret;
4330 }
4331
4332 static void
4333 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4334 {
4335         struct hns3_adapter *hns = eth_dev->data->dev_private;
4336         struct rte_device *dev = eth_dev->device;
4337         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4338         struct hns3_hw *hw = &hns->hw;
4339
4340         PMD_INIT_FUNC_TRACE();
4341
4342         hns3_enable_hw_error_intr(hns, false);
4343         hns3_rss_uninit(hns);
4344         hns3_fdir_filter_uninit(hns);
4345         hns3_uninit_umv_space(hw);
4346         hns3_pf_disable_irq0(hw);
4347         rte_intr_disable(&pci_dev->intr_handle);
4348         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4349                              eth_dev);
4350         hns3_cmd_uninit(hw);
4351         hns3_cmd_destroy_queue(hw);
4352         hw->io_base = NULL;
4353 }
4354
4355 static int
4356 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4357 {
4358         struct hns3_hw *hw = &hns->hw;
4359         int ret;
4360
4361         ret = hns3_dcb_cfg_update(hns);
4362         if (ret)
4363                 return ret;
4364
4365         /* Enable queues */
4366         ret = hns3_start_queues(hns, reset_queue);
4367         if (ret) {
4368                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4369                 return ret;
4370         }
4371
4372         /* Enable MAC */
4373         ret = hns3_cfg_mac_mode(hw, true);
4374         if (ret) {
4375                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4376                 goto err_config_mac_mode;
4377         }
4378         return 0;
4379
4380 err_config_mac_mode:
4381         hns3_stop_queues(hns, true);
4382         return ret;
4383 }
4384
4385 static int
4386 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4387 {
4388         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4389         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4390         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4392         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4393         uint32_t intr_vector;
4394         uint16_t q_id;
4395         int ret;
4396
4397         if (dev->data->dev_conf.intr_conf.rxq == 0)
4398                 return 0;
4399
4400         /* disable uio/vfio intr/eventfd mapping */
4401         rte_intr_disable(intr_handle);
4402
4403         /* check and configure queue intr-vector mapping */
4404         if (rte_intr_cap_multiple(intr_handle) ||
4405             !RTE_ETH_DEV_SRIOV(dev).active) {
4406                 intr_vector = hw->used_rx_queues;
4407                 /* creates event fd for each intr vector when MSIX is used */
4408                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4409                         return -EINVAL;
4410         }
4411         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4412                 intr_handle->intr_vec =
4413                         rte_zmalloc("intr_vec",
4414                                     hw->used_rx_queues * sizeof(int), 0);
4415                 if (intr_handle->intr_vec == NULL) {
4416                         hns3_err(hw, "Failed to allocate %d rx_queues"
4417                                      " intr_vec", hw->used_rx_queues);
4418                         ret = -ENOMEM;
4419                         goto alloc_intr_vec_error;
4420                 }
4421         }
4422
4423         if (rte_intr_allow_others(intr_handle)) {
4424                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4425                 base = RTE_INTR_VEC_RXTX_OFFSET;
4426         }
4427         if (rte_intr_dp_is_en(intr_handle)) {
4428                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4429                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4430                                                          HNS3_RING_TYPE_RX,
4431                                                          q_id);
4432                         if (ret)
4433                                 goto bind_vector_error;
4434                         intr_handle->intr_vec[q_id] = vec;
4435                         if (vec < base + intr_handle->nb_efd - 1)
4436                                 vec++;
4437                 }
4438         }
4439         rte_intr_enable(intr_handle);
4440         return 0;
4441
4442 bind_vector_error:
4443         rte_intr_efd_disable(intr_handle);
4444         if (intr_handle->intr_vec) {
4445                 free(intr_handle->intr_vec);
4446                 intr_handle->intr_vec = NULL;
4447         }
4448         return ret;
4449 alloc_intr_vec_error:
4450         rte_intr_efd_disable(intr_handle);
4451         return ret;
4452 }
4453
4454 static int
4455 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4456 {
4457         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4458         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4459         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4460         uint16_t q_id;
4461         int ret;
4462
4463         if (dev->data->dev_conf.intr_conf.rxq == 0)
4464                 return 0;
4465
4466         if (rte_intr_dp_is_en(intr_handle)) {
4467                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4468                         ret = hns3_bind_ring_with_vector(hw,
4469                                         intr_handle->intr_vec[q_id], true,
4470                                         HNS3_RING_TYPE_RX, q_id);
4471                         if (ret)
4472                                 return ret;
4473                 }
4474         }
4475
4476         return 0;
4477 }
4478
4479 static void
4480 hns3_restore_filter(struct rte_eth_dev *dev)
4481 {
4482         hns3_restore_rss_filter(dev);
4483 }
4484
4485 static int
4486 hns3_dev_start(struct rte_eth_dev *dev)
4487 {
4488         struct hns3_adapter *hns = dev->data->dev_private;
4489         struct hns3_hw *hw = &hns->hw;
4490         int ret;
4491
4492         PMD_INIT_FUNC_TRACE();
4493         if (rte_atomic16_read(&hw->reset.resetting))
4494                 return -EBUSY;
4495
4496         rte_spinlock_lock(&hw->lock);
4497         hw->adapter_state = HNS3_NIC_STARTING;
4498
4499         ret = hns3_do_start(hns, true);
4500         if (ret) {
4501                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4502                 rte_spinlock_unlock(&hw->lock);
4503                 return ret;
4504         }
4505         ret = hns3_map_rx_interrupt(dev);
4506         if (ret) {
4507                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4508                 rte_spinlock_unlock(&hw->lock);
4509                 return ret;
4510         }
4511
4512         hw->adapter_state = HNS3_NIC_STARTED;
4513         rte_spinlock_unlock(&hw->lock);
4514
4515         hns3_set_rxtx_function(dev);
4516         hns3_mp_req_start_rxtx(dev);
4517         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4518
4519         hns3_restore_filter(dev);
4520
4521         /* Enable interrupt of all rx queues before enabling queues */
4522         hns3_dev_all_rx_queue_intr_enable(hw, true);
4523         /*
4524          * When finished the initialization, enable queues to receive/transmit
4525          * packets.
4526          */
4527         hns3_enable_all_queues(hw, true);
4528
4529         hns3_info(hw, "hns3 dev start successful!");
4530         return 0;
4531 }
4532
4533 static int
4534 hns3_do_stop(struct hns3_adapter *hns)
4535 {
4536         struct hns3_hw *hw = &hns->hw;
4537         bool reset_queue;
4538         int ret;
4539
4540         ret = hns3_cfg_mac_mode(hw, false);
4541         if (ret)
4542                 return ret;
4543         hw->mac.link_status = ETH_LINK_DOWN;
4544
4545         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4546                 hns3_configure_all_mac_addr(hns, true);
4547                 reset_queue = true;
4548         } else
4549                 reset_queue = false;
4550         hw->mac.default_addr_setted = false;
4551         return hns3_stop_queues(hns, reset_queue);
4552 }
4553
4554 static void
4555 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4556 {
4557         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4558         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4559         struct hns3_adapter *hns = dev->data->dev_private;
4560         struct hns3_hw *hw = &hns->hw;
4561         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4562         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4563         uint16_t q_id;
4564
4565         if (dev->data->dev_conf.intr_conf.rxq == 0)
4566                 return;
4567
4568         /* unmap the ring with vector */
4569         if (rte_intr_allow_others(intr_handle)) {
4570                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4571                 base = RTE_INTR_VEC_RXTX_OFFSET;
4572         }
4573         if (rte_intr_dp_is_en(intr_handle)) {
4574                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4575                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4576                                                          HNS3_RING_TYPE_RX,
4577                                                          q_id);
4578                         if (vec < base + intr_handle->nb_efd - 1)
4579                                 vec++;
4580                 }
4581         }
4582         /* Clean datapath event and queue/vec mapping */
4583         rte_intr_efd_disable(intr_handle);
4584         if (intr_handle->intr_vec) {
4585                 rte_free(intr_handle->intr_vec);
4586                 intr_handle->intr_vec = NULL;
4587         }
4588 }
4589
4590 static void
4591 hns3_dev_stop(struct rte_eth_dev *dev)
4592 {
4593         struct hns3_adapter *hns = dev->data->dev_private;
4594         struct hns3_hw *hw = &hns->hw;
4595
4596         PMD_INIT_FUNC_TRACE();
4597
4598         hw->adapter_state = HNS3_NIC_STOPPING;
4599         hns3_set_rxtx_function(dev);
4600         rte_wmb();
4601         /* Disable datapath on secondary process. */
4602         hns3_mp_req_stop_rxtx(dev);
4603         /* Prevent crashes when queues are still in use. */
4604         rte_delay_ms(hw->tqps_num);
4605
4606         rte_spinlock_lock(&hw->lock);
4607         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4608                 hns3_do_stop(hns);
4609                 hns3_unmap_rx_interrupt(dev);
4610                 hns3_dev_release_mbufs(hns);
4611                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4612         }
4613         rte_eal_alarm_cancel(hns3_service_handler, dev);
4614         rte_spinlock_unlock(&hw->lock);
4615 }
4616
4617 static void
4618 hns3_dev_close(struct rte_eth_dev *eth_dev)
4619 {
4620         struct hns3_adapter *hns = eth_dev->data->dev_private;
4621         struct hns3_hw *hw = &hns->hw;
4622
4623         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4624                 rte_free(eth_dev->process_private);
4625                 eth_dev->process_private = NULL;
4626                 return;
4627         }
4628
4629         if (hw->adapter_state == HNS3_NIC_STARTED)
4630                 hns3_dev_stop(eth_dev);
4631
4632         hw->adapter_state = HNS3_NIC_CLOSING;
4633         hns3_reset_abort(hns);
4634         hw->adapter_state = HNS3_NIC_CLOSED;
4635
4636         hns3_configure_all_mc_mac_addr(hns, true);
4637         hns3_remove_all_vlan_table(hns);
4638         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4639         hns3_uninit_pf(eth_dev);
4640         hns3_free_all_queues(eth_dev);
4641         rte_free(hw->reset.wait_data);
4642         rte_free(eth_dev->process_private);
4643         eth_dev->process_private = NULL;
4644         hns3_mp_uninit_primary();
4645         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4646 }
4647
4648 static int
4649 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4650 {
4651         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4652         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4653
4654         fc_conf->pause_time = pf->pause_time;
4655
4656         /* return fc current mode */
4657         switch (hw->current_mode) {
4658         case HNS3_FC_FULL:
4659                 fc_conf->mode = RTE_FC_FULL;
4660                 break;
4661         case HNS3_FC_TX_PAUSE:
4662                 fc_conf->mode = RTE_FC_TX_PAUSE;
4663                 break;
4664         case HNS3_FC_RX_PAUSE:
4665                 fc_conf->mode = RTE_FC_RX_PAUSE;
4666                 break;
4667         case HNS3_FC_NONE:
4668         default:
4669                 fc_conf->mode = RTE_FC_NONE;
4670                 break;
4671         }
4672
4673         return 0;
4674 }
4675
4676 static void
4677 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4678 {
4679         switch (mode) {
4680         case RTE_FC_NONE:
4681                 hw->requested_mode = HNS3_FC_NONE;
4682                 break;
4683         case RTE_FC_RX_PAUSE:
4684                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4685                 break;
4686         case RTE_FC_TX_PAUSE:
4687                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4688                 break;
4689         case RTE_FC_FULL:
4690                 hw->requested_mode = HNS3_FC_FULL;
4691                 break;
4692         default:
4693                 hw->requested_mode = HNS3_FC_NONE;
4694                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4695                           "configured to RTE_FC_NONE", mode);
4696                 break;
4697         }
4698 }
4699
4700 static int
4701 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4702 {
4703         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4705         int ret;
4706
4707         if (fc_conf->high_water || fc_conf->low_water ||
4708             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4709                 hns3_err(hw, "Unsupported flow control settings specified, "
4710                          "high_water(%u), low_water(%u), send_xon(%u) and "
4711                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4712                          fc_conf->high_water, fc_conf->low_water,
4713                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4714                 return -EINVAL;
4715         }
4716         if (fc_conf->autoneg) {
4717                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4718                 return -EINVAL;
4719         }
4720         if (!fc_conf->pause_time) {
4721                 hns3_err(hw, "Invalid pause time %d setting.",
4722                          fc_conf->pause_time);
4723                 return -EINVAL;
4724         }
4725
4726         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4727             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4728                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4729                          "current_fc_status = %d", hw->current_fc_status);
4730                 return -EOPNOTSUPP;
4731         }
4732
4733         hns3_get_fc_mode(hw, fc_conf->mode);
4734         if (hw->requested_mode == hw->current_mode &&
4735             pf->pause_time == fc_conf->pause_time)
4736                 return 0;
4737
4738         rte_spinlock_lock(&hw->lock);
4739         ret = hns3_fc_enable(dev, fc_conf);
4740         rte_spinlock_unlock(&hw->lock);
4741
4742         return ret;
4743 }
4744
4745 static int
4746 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4747                             struct rte_eth_pfc_conf *pfc_conf)
4748 {
4749         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4751         uint8_t priority;
4752         int ret;
4753
4754         if (!hns3_dev_dcb_supported(hw)) {
4755                 hns3_err(hw, "This port does not support dcb configurations.");
4756                 return -EOPNOTSUPP;
4757         }
4758
4759         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4760             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4761                 hns3_err(hw, "Unsupported flow control settings specified, "
4762                          "high_water(%u), low_water(%u), send_xon(%u) and "
4763                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4764                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4765                          pfc_conf->fc.send_xon,
4766                          pfc_conf->fc.mac_ctrl_frame_fwd);
4767                 return -EINVAL;
4768         }
4769         if (pfc_conf->fc.autoneg) {
4770                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4771                 return -EINVAL;
4772         }
4773         if (pfc_conf->fc.pause_time == 0) {
4774                 hns3_err(hw, "Invalid pause time %d setting.",
4775                          pfc_conf->fc.pause_time);
4776                 return -EINVAL;
4777         }
4778
4779         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4780             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4781                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4782                              "current_fc_status = %d", hw->current_fc_status);
4783                 return -EOPNOTSUPP;
4784         }
4785
4786         priority = pfc_conf->priority;
4787         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4788         if (hw->dcb_info.pfc_en & BIT(priority) &&
4789             hw->requested_mode == hw->current_mode &&
4790             pfc_conf->fc.pause_time == pf->pause_time)
4791                 return 0;
4792
4793         rte_spinlock_lock(&hw->lock);
4794         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4795         rte_spinlock_unlock(&hw->lock);
4796
4797         return ret;
4798 }
4799
4800 static int
4801 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4802 {
4803         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4805         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4806         int i;
4807
4808         rte_spinlock_lock(&hw->lock);
4809         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4810                 dcb_info->nb_tcs = pf->local_max_tc;
4811         else
4812                 dcb_info->nb_tcs = 1;
4813
4814         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4815                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4816         for (i = 0; i < dcb_info->nb_tcs; i++)
4817                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4818
4819         for (i = 0; i < hw->num_tc; i++) {
4820                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4821                 dcb_info->tc_queue.tc_txq[0][i].base =
4822                                                 hw->tc_queue[i].tqp_offset;
4823                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4824                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4825                                                 hw->tc_queue[i].tqp_count;
4826         }
4827         rte_spinlock_unlock(&hw->lock);
4828
4829         return 0;
4830 }
4831
4832 static int
4833 hns3_reinit_dev(struct hns3_adapter *hns)
4834 {
4835         struct hns3_hw *hw = &hns->hw;
4836         int ret;
4837
4838         ret = hns3_cmd_init(hw);
4839         if (ret) {
4840                 hns3_err(hw, "Failed to init cmd: %d", ret);
4841                 return ret;
4842         }
4843
4844         ret = hns3_reset_all_queues(hns);
4845         if (ret) {
4846                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4847                 return ret;
4848         }
4849
4850         ret = hns3_init_hardware(hns);
4851         if (ret) {
4852                 hns3_err(hw, "Failed to init hardware: %d", ret);
4853                 return ret;
4854         }
4855
4856         ret = hns3_enable_hw_error_intr(hns, true);
4857         if (ret) {
4858                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4859                              ret);
4860                 return ret;
4861         }
4862         hns3_info(hw, "Reset done, driver initialization finished.");
4863
4864         return 0;
4865 }
4866
4867 static bool
4868 is_pf_reset_done(struct hns3_hw *hw)
4869 {
4870         uint32_t val, reg, reg_bit;
4871
4872         switch (hw->reset.level) {
4873         case HNS3_IMP_RESET:
4874                 reg = HNS3_GLOBAL_RESET_REG;
4875                 reg_bit = HNS3_IMP_RESET_BIT;
4876                 break;
4877         case HNS3_GLOBAL_RESET:
4878                 reg = HNS3_GLOBAL_RESET_REG;
4879                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4880                 break;
4881         case HNS3_FUNC_RESET:
4882                 reg = HNS3_FUN_RST_ING;
4883                 reg_bit = HNS3_FUN_RST_ING_B;
4884                 break;
4885         case HNS3_FLR_RESET:
4886         default:
4887                 hns3_err(hw, "Wait for unsupported reset level: %d",
4888                          hw->reset.level);
4889                 return true;
4890         }
4891         val = hns3_read_dev(hw, reg);
4892         if (hns3_get_bit(val, reg_bit))
4893                 return false;
4894         else
4895                 return true;
4896 }
4897
4898 bool
4899 hns3_is_reset_pending(struct hns3_adapter *hns)
4900 {
4901         struct hns3_hw *hw = &hns->hw;
4902         enum hns3_reset_level reset;
4903
4904         hns3_check_event_cause(hns, NULL);
4905         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4906         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4907                 hns3_warn(hw, "High level reset %d is pending", reset);
4908                 return true;
4909         }
4910         reset = hns3_get_reset_level(hns, &hw->reset.request);
4911         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4912                 hns3_warn(hw, "High level reset %d is request", reset);
4913                 return true;
4914         }
4915         return false;
4916 }
4917
4918 static int
4919 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4920 {
4921         struct hns3_hw *hw = &hns->hw;
4922         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4923         struct timeval tv;
4924
4925         if (wait_data->result == HNS3_WAIT_SUCCESS)
4926                 return 0;
4927         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4928                 gettimeofday(&tv, NULL);
4929                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4930                           tv.tv_sec, tv.tv_usec);
4931                 return -ETIME;
4932         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4933                 return -EAGAIN;
4934
4935         wait_data->hns = hns;
4936         wait_data->check_completion = is_pf_reset_done;
4937         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4938                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4939         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4940         wait_data->count = HNS3_RESET_WAIT_CNT;
4941         wait_data->result = HNS3_WAIT_REQUEST;
4942         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4943         return -EAGAIN;
4944 }
4945
4946 static int
4947 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4948 {
4949         struct hns3_cmd_desc desc;
4950         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4951
4952         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4953         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4954         req->fun_reset_vfid = func_id;
4955
4956         return hns3_cmd_send(hw, &desc, 1);
4957 }
4958
4959 static int
4960 hns3_imp_reset_cmd(struct hns3_hw *hw)
4961 {
4962         struct hns3_cmd_desc desc;
4963
4964         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4965         desc.data[0] = 0xeedd;
4966
4967         return hns3_cmd_send(hw, &desc, 1);
4968 }
4969
4970 static void
4971 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4972 {
4973         struct hns3_hw *hw = &hns->hw;
4974         struct timeval tv;
4975         uint32_t val;
4976
4977         gettimeofday(&tv, NULL);
4978         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4979             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4980                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4981                           tv.tv_sec, tv.tv_usec);
4982                 return;
4983         }
4984
4985         switch (reset_level) {
4986         case HNS3_IMP_RESET:
4987                 hns3_imp_reset_cmd(hw);
4988                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4989                           tv.tv_sec, tv.tv_usec);
4990                 break;
4991         case HNS3_GLOBAL_RESET:
4992                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4993                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4994                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4995                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4996                           tv.tv_sec, tv.tv_usec);
4997                 break;
4998         case HNS3_FUNC_RESET:
4999                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5000                           tv.tv_sec, tv.tv_usec);
5001                 /* schedule again to check later */
5002                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5003                 hns3_schedule_reset(hns);
5004                 break;
5005         default:
5006                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5007                 return;
5008         }
5009         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5010 }
5011
5012 static enum hns3_reset_level
5013 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5014 {
5015         struct hns3_hw *hw = &hns->hw;
5016         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5017
5018         /* Return the highest priority reset level amongst all */
5019         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5020                 reset_level = HNS3_IMP_RESET;
5021         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5022                 reset_level = HNS3_GLOBAL_RESET;
5023         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5024                 reset_level = HNS3_FUNC_RESET;
5025         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5026                 reset_level = HNS3_FLR_RESET;
5027
5028         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5029                 return HNS3_NONE_RESET;
5030
5031         return reset_level;
5032 }
5033
5034 static int
5035 hns3_prepare_reset(struct hns3_adapter *hns)
5036 {
5037         struct hns3_hw *hw = &hns->hw;
5038         uint32_t reg_val;
5039         int ret;
5040
5041         switch (hw->reset.level) {
5042         case HNS3_FUNC_RESET:
5043                 ret = hns3_func_reset_cmd(hw, 0);
5044                 if (ret)
5045                         return ret;
5046
5047                 /*
5048                  * After performaning pf reset, it is not necessary to do the
5049                  * mailbox handling or send any command to firmware, because
5050                  * any mailbox handling or command to firmware is only valid
5051                  * after hns3_cmd_init is called.
5052                  */
5053                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5054                 hw->reset.stats.request_cnt++;
5055                 break;
5056         case HNS3_IMP_RESET:
5057                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5058                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5059                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5060                 break;
5061         default:
5062                 break;
5063         }
5064         return 0;
5065 }
5066
5067 static int
5068 hns3_set_rst_done(struct hns3_hw *hw)
5069 {
5070         struct hns3_pf_rst_done_cmd *req;
5071         struct hns3_cmd_desc desc;
5072
5073         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5074         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5075         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5076         return hns3_cmd_send(hw, &desc, 1);
5077 }
5078
5079 static int
5080 hns3_stop_service(struct hns3_adapter *hns)
5081 {
5082         struct hns3_hw *hw = &hns->hw;
5083         struct rte_eth_dev *eth_dev;
5084
5085         eth_dev = &rte_eth_devices[hw->data->port_id];
5086         if (hw->adapter_state == HNS3_NIC_STARTED)
5087                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5088         hw->mac.link_status = ETH_LINK_DOWN;
5089
5090         hns3_set_rxtx_function(eth_dev);
5091         rte_wmb();
5092         /* Disable datapath on secondary process. */
5093         hns3_mp_req_stop_rxtx(eth_dev);
5094         rte_delay_ms(hw->tqps_num);
5095
5096         rte_spinlock_lock(&hw->lock);
5097         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5098             hw->adapter_state == HNS3_NIC_STOPPING) {
5099                 hns3_do_stop(hns);
5100                 hw->reset.mbuf_deferred_free = true;
5101         } else
5102                 hw->reset.mbuf_deferred_free = false;
5103
5104         /*
5105          * It is cumbersome for hardware to pick-and-choose entries for deletion
5106          * from table space. Hence, for function reset software intervention is
5107          * required to delete the entries
5108          */
5109         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5110                 hns3_configure_all_mc_mac_addr(hns, true);
5111         rte_spinlock_unlock(&hw->lock);
5112
5113         return 0;
5114 }
5115
5116 static int
5117 hns3_start_service(struct hns3_adapter *hns)
5118 {
5119         struct hns3_hw *hw = &hns->hw;
5120         struct rte_eth_dev *eth_dev;
5121
5122         if (hw->reset.level == HNS3_IMP_RESET ||
5123             hw->reset.level == HNS3_GLOBAL_RESET)
5124                 hns3_set_rst_done(hw);
5125         eth_dev = &rte_eth_devices[hw->data->port_id];
5126         hns3_set_rxtx_function(eth_dev);
5127         hns3_mp_req_start_rxtx(eth_dev);
5128         if (hw->adapter_state == HNS3_NIC_STARTED) {
5129                 hns3_service_handler(eth_dev);
5130
5131                 /* Enable interrupt of all rx queues before enabling queues */
5132                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5133                 /*
5134                  * When finished the initialization, enable queues to receive
5135                  * and transmit packets.
5136                  */
5137                 hns3_enable_all_queues(hw, true);
5138         }
5139
5140         return 0;
5141 }
5142
5143 static int
5144 hns3_restore_conf(struct hns3_adapter *hns)
5145 {
5146         struct hns3_hw *hw = &hns->hw;
5147         int ret;
5148
5149         ret = hns3_configure_all_mac_addr(hns, false);
5150         if (ret)
5151                 return ret;
5152
5153         ret = hns3_configure_all_mc_mac_addr(hns, false);
5154         if (ret)
5155                 goto err_mc_mac;
5156
5157         ret = hns3_dev_promisc_restore(hns);
5158         if (ret)
5159                 goto err_promisc;
5160
5161         ret = hns3_restore_vlan_table(hns);
5162         if (ret)
5163                 goto err_promisc;
5164
5165         ret = hns3_restore_vlan_conf(hns);
5166         if (ret)
5167                 goto err_promisc;
5168
5169         ret = hns3_restore_all_fdir_filter(hns);
5170         if (ret)
5171                 goto err_promisc;
5172
5173         ret = hns3_restore_rx_interrupt(hw);
5174         if (ret)
5175                 goto err_promisc;
5176
5177         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5178                 ret = hns3_do_start(hns, false);
5179                 if (ret)
5180                         goto err_promisc;
5181                 hns3_info(hw, "hns3 dev restart successful!");
5182         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5183                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5184         return 0;
5185
5186 err_promisc:
5187         hns3_configure_all_mc_mac_addr(hns, true);
5188 err_mc_mac:
5189         hns3_configure_all_mac_addr(hns, true);
5190         return ret;
5191 }
5192
5193 static void
5194 hns3_reset_service(void *param)
5195 {
5196         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5197         struct hns3_hw *hw = &hns->hw;
5198         enum hns3_reset_level reset_level;
5199         struct timeval tv_delta;
5200         struct timeval tv_start;
5201         struct timeval tv;
5202         uint64_t msec;
5203         int ret;
5204
5205         /*
5206          * The interrupt is not triggered within the delay time.
5207          * The interrupt may have been lost. It is necessary to handle
5208          * the interrupt to recover from the error.
5209          */
5210         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5211                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5212                 hns3_err(hw, "Handling interrupts in delayed tasks");
5213                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5214                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5215                 if (reset_level == HNS3_NONE_RESET) {
5216                         hns3_err(hw, "No reset level is set, try IMP reset");
5217                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5218                 }
5219         }
5220         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5221
5222         /*
5223          * Check if there is any ongoing reset in the hardware. This status can
5224          * be checked from reset_pending. If there is then, we need to wait for
5225          * hardware to complete reset.
5226          *    a. If we are able to figure out in reasonable time that hardware
5227          *       has fully resetted then, we can proceed with driver, client
5228          *       reset.
5229          *    b. else, we can come back later to check this status so re-sched
5230          *       now.
5231          */
5232         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5233         if (reset_level != HNS3_NONE_RESET) {
5234                 gettimeofday(&tv_start, NULL);
5235                 ret = hns3_reset_process(hns, reset_level);
5236                 gettimeofday(&tv, NULL);
5237                 timersub(&tv, &tv_start, &tv_delta);
5238                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5239                        tv_delta.tv_usec / USEC_PER_MSEC;
5240                 if (msec > HNS3_RESET_PROCESS_MS)
5241                         hns3_err(hw, "%d handle long time delta %" PRIx64
5242                                      " ms time=%ld.%.6ld",
5243                                  hw->reset.level, msec,
5244                                  tv.tv_sec, tv.tv_usec);
5245                 if (ret == -EAGAIN)
5246                         return;
5247         }
5248
5249         /* Check if we got any *new* reset requests to be honored */
5250         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5251         if (reset_level != HNS3_NONE_RESET)
5252                 hns3_msix_process(hns, reset_level);
5253 }
5254
5255 static const struct eth_dev_ops hns3_eth_dev_ops = {
5256         .dev_start          = hns3_dev_start,
5257         .dev_stop           = hns3_dev_stop,
5258         .dev_close          = hns3_dev_close,
5259         .promiscuous_enable = hns3_dev_promiscuous_enable,
5260         .promiscuous_disable = hns3_dev_promiscuous_disable,
5261         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5262         .allmulticast_disable = hns3_dev_allmulticast_disable,
5263         .mtu_set            = hns3_dev_mtu_set,
5264         .stats_get          = hns3_stats_get,
5265         .stats_reset        = hns3_stats_reset,
5266         .xstats_get         = hns3_dev_xstats_get,
5267         .xstats_get_names   = hns3_dev_xstats_get_names,
5268         .xstats_reset       = hns3_dev_xstats_reset,
5269         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5270         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5271         .dev_infos_get          = hns3_dev_infos_get,
5272         .fw_version_get         = hns3_fw_version_get,
5273         .rx_queue_setup         = hns3_rx_queue_setup,
5274         .tx_queue_setup         = hns3_tx_queue_setup,
5275         .rx_queue_release       = hns3_dev_rx_queue_release,
5276         .tx_queue_release       = hns3_dev_tx_queue_release,
5277         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5278         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5279         .dev_configure          = hns3_dev_configure,
5280         .flow_ctrl_get          = hns3_flow_ctrl_get,
5281         .flow_ctrl_set          = hns3_flow_ctrl_set,
5282         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5283         .mac_addr_add           = hns3_add_mac_addr,
5284         .mac_addr_remove        = hns3_remove_mac_addr,
5285         .mac_addr_set           = hns3_set_default_mac_addr,
5286         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5287         .link_update            = hns3_dev_link_update,
5288         .rss_hash_update        = hns3_dev_rss_hash_update,
5289         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5290         .reta_update            = hns3_dev_rss_reta_update,
5291         .reta_query             = hns3_dev_rss_reta_query,
5292         .filter_ctrl            = hns3_dev_filter_ctrl,
5293         .vlan_filter_set        = hns3_vlan_filter_set,
5294         .vlan_tpid_set          = hns3_vlan_tpid_set,
5295         .vlan_offload_set       = hns3_vlan_offload_set,
5296         .vlan_pvid_set          = hns3_vlan_pvid_set,
5297         .get_reg                = hns3_get_regs,
5298         .get_dcb_info           = hns3_get_dcb_info,
5299         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5300 };
5301
5302 static const struct hns3_reset_ops hns3_reset_ops = {
5303         .reset_service       = hns3_reset_service,
5304         .stop_service        = hns3_stop_service,
5305         .prepare_reset       = hns3_prepare_reset,
5306         .wait_hardware_ready = hns3_wait_hardware_ready,
5307         .reinit_dev          = hns3_reinit_dev,
5308         .restore_conf        = hns3_restore_conf,
5309         .start_service       = hns3_start_service,
5310 };
5311
5312 static int
5313 hns3_dev_init(struct rte_eth_dev *eth_dev)
5314 {
5315         struct rte_device *dev = eth_dev->device;
5316         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5317         struct hns3_adapter *hns = eth_dev->data->dev_private;
5318         struct hns3_hw *hw = &hns->hw;
5319         uint16_t device_id = pci_dev->id.device_id;
5320         int ret;
5321
5322         PMD_INIT_FUNC_TRACE();
5323         eth_dev->process_private = (struct hns3_process_private *)
5324             rte_zmalloc_socket("hns3_filter_list",
5325                                sizeof(struct hns3_process_private),
5326                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5327         if (eth_dev->process_private == NULL) {
5328                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5329                 return -ENOMEM;
5330         }
5331         /* initialize flow filter lists */
5332         hns3_filterlist_init(eth_dev);
5333
5334         hns3_set_rxtx_function(eth_dev);
5335         eth_dev->dev_ops = &hns3_eth_dev_ops;
5336         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5337                 hns3_mp_init_secondary();
5338                 hw->secondary_cnt++;
5339                 return 0;
5340         }
5341
5342         hns3_mp_init_primary();
5343         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5344
5345         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5346             device_id == HNS3_DEV_ID_50GE_RDMA ||
5347             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5348                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5349
5350         hns->is_vf = false;
5351         hw->data = eth_dev->data;
5352
5353         /*
5354          * Set default max packet size according to the mtu
5355          * default vale in DPDK frame.
5356          */
5357         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5358
5359         ret = hns3_reset_init(hw);
5360         if (ret)
5361                 goto err_init_reset;
5362         hw->reset.ops = &hns3_reset_ops;
5363
5364         ret = hns3_init_pf(eth_dev);
5365         if (ret) {
5366                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5367                 goto err_init_pf;
5368         }
5369
5370         /* Allocate memory for storing MAC addresses */
5371         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5372                                                sizeof(struct rte_ether_addr) *
5373                                                HNS3_UC_MACADDR_NUM, 0);
5374         if (eth_dev->data->mac_addrs == NULL) {
5375                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5376                              "to store MAC addresses",
5377                              sizeof(struct rte_ether_addr) *
5378                              HNS3_UC_MACADDR_NUM);
5379                 ret = -ENOMEM;
5380                 goto err_rte_zmalloc;
5381         }
5382
5383         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5384                             &eth_dev->data->mac_addrs[0]);
5385
5386         hw->adapter_state = HNS3_NIC_INITIALIZED;
5387         /*
5388          * Pass the information to the rte_eth_dev_close() that it should also
5389          * release the private port resources.
5390          */
5391         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5392
5393         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5394                 hns3_err(hw, "Reschedule reset service after dev_init");
5395                 hns3_schedule_reset(hns);
5396         } else {
5397                 /* IMP will wait ready flag before reset */
5398                 hns3_notify_reset_ready(hw, false);
5399         }
5400
5401         hns3_info(hw, "hns3 dev initialization successful!");
5402         return 0;
5403
5404 err_rte_zmalloc:
5405         hns3_uninit_pf(eth_dev);
5406
5407 err_init_pf:
5408         rte_free(hw->reset.wait_data);
5409 err_init_reset:
5410         eth_dev->dev_ops = NULL;
5411         eth_dev->rx_pkt_burst = NULL;
5412         eth_dev->tx_pkt_burst = NULL;
5413         eth_dev->tx_pkt_prepare = NULL;
5414         rte_free(eth_dev->process_private);
5415         eth_dev->process_private = NULL;
5416         return ret;
5417 }
5418
5419 static int
5420 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5421 {
5422         struct hns3_adapter *hns = eth_dev->data->dev_private;
5423         struct hns3_hw *hw = &hns->hw;
5424
5425         PMD_INIT_FUNC_TRACE();
5426
5427         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5428                 return -EPERM;
5429
5430         eth_dev->dev_ops = NULL;
5431         eth_dev->rx_pkt_burst = NULL;
5432         eth_dev->tx_pkt_burst = NULL;
5433         eth_dev->tx_pkt_prepare = NULL;
5434         if (hw->adapter_state < HNS3_NIC_CLOSING)
5435                 hns3_dev_close(eth_dev);
5436
5437         hw->adapter_state = HNS3_NIC_REMOVED;
5438         return 0;
5439 }
5440
5441 static int
5442 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5443                    struct rte_pci_device *pci_dev)
5444 {
5445         return rte_eth_dev_pci_generic_probe(pci_dev,
5446                                              sizeof(struct hns3_adapter),
5447                                              hns3_dev_init);
5448 }
5449
5450 static int
5451 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5452 {
5453         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5454 }
5455
5456 static const struct rte_pci_id pci_id_hns3_map[] = {
5457         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5458         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5459         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5460         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5461         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5462         { .vendor_id = 0, /* sentinel */ },
5463 };
5464
5465 static struct rte_pci_driver rte_hns3_pmd = {
5466         .id_table = pci_id_hns3_map,
5467         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5468         .probe = eth_hns3_pci_probe,
5469         .remove = eth_hns3_pci_remove,
5470 };
5471
5472 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5473 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5474 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5475
5476 RTE_INIT(hns3_init_log)
5477 {
5478         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5479         if (hns3_logtype_init >= 0)
5480                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5481         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5482         if (hns3_logtype_driver >= 0)
5483                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5484 }