drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27 #include "hns3_dcb.h"
  28
  29 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  30 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  31
  32 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  33 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  34 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  35 #define HNS3_INVLID_PVID                0xFFFF
  36
  37 #define HNS3_FILTER_TYPE_VF             0
  38 #define HNS3_FILTER_TYPE_PORT           1
  39 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  40 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  41 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  42 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  43 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  44 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  45                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  46 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  47                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  48
  49 int hns3_logtype_init;
  50 int hns3_logtype_driver;
  51
  52 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  53                                     int on);
  54
  55 static int
  56 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
  57 {
  58 #define HNS3_VLAN_OFFSET_160            160
  59         struct hns3_vlan_filter_pf_cfg_cmd *req;
  60         struct hns3_hw *hw = &hns->hw;
  61         uint8_t vlan_offset_byte_val;
  62         struct hns3_cmd_desc desc;
  63         uint8_t vlan_offset_byte;
  64         uint8_t vlan_offset_160;
  65         int ret;
  66
  67         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
  68
  69         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
  70         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
  71         vlan_offset_byte_val = 1 << (vlan_id % 8);
  72
  73         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
  74         req->vlan_offset = vlan_offset_160;
  75         req->vlan_cfg = on ? 0 : 1;
  76         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
  77
  78         ret = hns3_cmd_send(hw, &desc, 1);
  79         if (ret)
  80                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
  81                          vlan_id, ret);
  82
  83         return ret;
  84 }
  85
  86 static void
  87 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
  88 {
  89         struct hns3_user_vlan_table *vlan_entry;
  90         struct hns3_pf *pf = &hns->pf;
  91
  92         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
  93                 if (vlan_entry->vlan_id == vlan_id) {
  94                         if (vlan_entry->hd_tbl_status)
  95                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
  96                         LIST_REMOVE(vlan_entry, next);
  97                         rte_free(vlan_entry);
  98                         break;
  99                 }
 100         }
 101 }
 102
 103 static void
 104 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 105                         bool writen_to_tbl)
 106 {
 107         struct hns3_user_vlan_table *vlan_entry;
 108         struct hns3_hw *hw = &hns->hw;
 109         struct hns3_pf *pf = &hns->pf;
 110
 111         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 112         if (vlan_entry == NULL) {
 113                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 114                 return;
 115         }
 116
 117         vlan_entry->hd_tbl_status = writen_to_tbl;
 118         vlan_entry->vlan_id = vlan_id;
 119
 120         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 121 }
 122
 123 static int
 124 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 125 {
 126         struct hns3_pf *pf = &hns->pf;
 127         bool writen_to_tbl = false;
 128         int ret = 0;
 129
 130         /*
 131          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 132          * for normal packet, deleting vlan id 0 is not allowed.
 133          */
 134         if (on == 0 && vlan_id == 0)
 135                 return 0;
 136
 137         /*
 138          * When port base vlan enabled, we use port base vlan as the vlan
 139          * filter condition. In this case, we don't update vlan filter table
 140          * when user add new vlan or remove exist vlan, just update the
 141          * vlan list. The vlan id in vlan list will be writen in vlan filter
 142          * table until port base vlan disabled
 143          */
 144         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 145                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 146                 writen_to_tbl = true;
 147         }
 148
 149         if (ret == 0 && vlan_id) {
 150                 if (on)
 151                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 152                 else
 153                         hns3_rm_dev_vlan_table(hns, vlan_id);
 154         }
 155         return ret;
 156 }
 157
 158 static int
 159 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 160 {
 161         struct hns3_adapter *hns = dev->data->dev_private;
 162         struct hns3_hw *hw = &hns->hw;
 163         int ret;
 164
 165         rte_spinlock_lock(&hw->lock);
 166         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 167         rte_spinlock_unlock(&hw->lock);
 168         return ret;
 169 }
 170
 171 static int
 172 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 173                          uint16_t tpid)
 174 {
 175         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 176         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 177         struct hns3_hw *hw = &hns->hw;
 178         struct hns3_cmd_desc desc;
 179         int ret;
 180
 181         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 182              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 183                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 184                 return -EINVAL;
 185         }
 186
 187         if (tpid != RTE_ETHER_TYPE_VLAN) {
 188                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 189                 return -EINVAL;
 190         }
 191
 192         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 193         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 194
 195         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 196                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 197                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 198         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 199                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 200                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 201                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 202                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 203         }
 204
 205         ret = hns3_cmd_send(hw, &desc, 1);
 206         if (ret) {
 207                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 208                          ret);
 209                 return ret;
 210         }
 211
 212         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 213
 214         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 215         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 216         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 217
 218         ret = hns3_cmd_send(hw, &desc, 1);
 219         if (ret)
 220                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 221                          ret);
 222         return ret;
 223 }
 224
 225 static int
 226 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 227                    uint16_t tpid)
 228 {
 229         struct hns3_adapter *hns = dev->data->dev_private;
 230         struct hns3_hw *hw = &hns->hw;
 231         int ret;
 232
 233         rte_spinlock_lock(&hw->lock);
 234         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 235         rte_spinlock_unlock(&hw->lock);
 236         return ret;
 237 }
 238
 239 static int
 240 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 241                              struct hns3_rx_vtag_cfg *vcfg)
 242 {
 243         struct hns3_vport_vtag_rx_cfg_cmd *req;
 244         struct hns3_hw *hw = &hns->hw;
 245         struct hns3_cmd_desc desc;
 246         uint16_t vport_id;
 247         uint8_t bitmap;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 251
 252         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 253         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 254                      vcfg->strip_tag1_en ? 1 : 0);
 255         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 256                      vcfg->strip_tag2_en ? 1 : 0);
 257         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 258                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 259         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 260                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 261
 262         /*
 263          * In current version VF is not supported when PF is driven by DPDK
 264          * driver, the PF-related vf_id is 0, just need to configure parameters
 265          * for vport_id 0.
 266          */
 267         vport_id = 0;
 268         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 269         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 270         req->vf_bitmap[req->vf_offset] = bitmap;
 271
 272         ret = hns3_cmd_send(hw, &desc, 1);
 273         if (ret)
 274                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 275         return ret;
 276 }
 277
 278 static void
 279 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 280                            struct hns3_rx_vtag_cfg *vcfg)
 281 {
 282         struct hns3_pf *pf = &hns->pf;
 283         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 284 }
 285
 286 static void
 287 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 288                            struct hns3_tx_vtag_cfg *vcfg)
 289 {
 290         struct hns3_pf *pf = &hns->pf;
 291         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 292 }
 293
 294 static int
 295 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 296 {
 297         struct hns3_rx_vtag_cfg rxvlan_cfg;
 298         struct hns3_pf *pf = &hns->pf;
 299         struct hns3_hw *hw = &hns->hw;
 300         int ret;
 301
 302         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 303                 rxvlan_cfg.strip_tag1_en = false;
 304                 rxvlan_cfg.strip_tag2_en = enable;
 305         } else {
 306                 rxvlan_cfg.strip_tag1_en = enable;
 307                 rxvlan_cfg.strip_tag2_en = true;
 308         }
 309
 310         rxvlan_cfg.vlan1_vlan_prionly = false;
 311         rxvlan_cfg.vlan2_vlan_prionly = false;
 312         rxvlan_cfg.rx_vlan_offload_en = enable;
 313
 314         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 315         if (ret) {
 316                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 317                 return ret;
 318         }
 319
 320         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 327                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 328 {
 329         struct hns3_vlan_filter_ctrl_cmd *req;
 330         struct hns3_cmd_desc desc;
 331         int ret;
 332
 333         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 334
 335         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 336         req->vlan_type = vlan_type;
 337         req->vlan_fe = filter_en ? fe_type : 0;
 338         req->vf_id = vf_id;
 339
 340         ret = hns3_cmd_send(hw, &desc, 1);
 341         if (ret)
 342                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 343
 344         return ret;
 345 }
 346
 347 static int
 348 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 349 {
 350         struct hns3_hw *hw = &hns->hw;
 351         int ret;
 352
 353         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 354                                         HNS3_FILTER_FE_EGRESS, false, 0);
 355         if (ret) {
 356                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 357                 return ret;
 358         }
 359
 360         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 361                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 362         if (ret)
 363                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 364
 365         return ret;
 366 }
 367
 368 static int
 369 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 370 {
 371         struct hns3_adapter *hns = dev->data->dev_private;
 372         struct hns3_hw *hw = &hns->hw;
 373         struct rte_eth_rxmode *rxmode;
 374         unsigned int tmp_mask;
 375         bool enable;
 376         int ret = 0;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         rxmode = &dev->data->dev_conf.rxmode;
 380         tmp_mask = (unsigned int)mask;
 381         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 382                 /* Enable or disable VLAN stripping */
 383                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 384                     true : false;
 385
 386                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 387                 if (ret) {
 388                         rte_spinlock_unlock(&hw->lock);
 389                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 390                         return ret;
 391                 }
 392         }
 393
 394         rte_spinlock_unlock(&hw->lock);
 395
 396         return ret;
 397 }
 398
 399 static int
 400 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 401                              struct hns3_tx_vtag_cfg *vcfg)
 402 {
 403         struct hns3_vport_vtag_tx_cfg_cmd *req;
 404         struct hns3_cmd_desc desc;
 405         struct hns3_hw *hw = &hns->hw;
 406         uint16_t vport_id;
 407         uint8_t bitmap;
 408         int ret;
 409
 410         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 411
 412         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 413         req->def_vlan_tag1 = vcfg->default_tag1;
 414         req->def_vlan_tag2 = vcfg->default_tag2;
 415         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 416                      vcfg->accept_tag1 ? 1 : 0);
 417         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 418                      vcfg->accept_untag1 ? 1 : 0);
 419         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 420                      vcfg->accept_tag2 ? 1 : 0);
 421         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 422                      vcfg->accept_untag2 ? 1 : 0);
 423         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 424                      vcfg->insert_tag1_en ? 1 : 0);
 425         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 426                      vcfg->insert_tag2_en ? 1 : 0);
 427         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 428
 429         /*
 430          * In current version VF is not supported when PF is driven by DPDK
 431          * driver, the PF-related vf_id is 0, just need to configure parameters
 432          * for vport_id 0.
 433          */
 434         vport_id = 0;
 435         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 436         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 437         req->vf_bitmap[req->vf_offset] = bitmap;
 438
 439         ret = hns3_cmd_send(hw, &desc, 1);
 440         if (ret)
 441                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 442
 443         return ret;
 444 }
 445
 446 static int
 447 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 448                      uint16_t pvid)
 449 {
 450         struct hns3_hw *hw = &hns->hw;
 451         struct hns3_tx_vtag_cfg txvlan_cfg;
 452         int ret;
 453
 454         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 455                 txvlan_cfg.accept_tag1 = true;
 456                 txvlan_cfg.insert_tag1_en = false;
 457                 txvlan_cfg.default_tag1 = 0;
 458         } else {
 459                 txvlan_cfg.accept_tag1 = false;
 460                 txvlan_cfg.insert_tag1_en = true;
 461                 txvlan_cfg.default_tag1 = pvid;
 462         }
 463
 464         txvlan_cfg.accept_untag1 = true;
 465         txvlan_cfg.accept_tag2 = true;
 466         txvlan_cfg.accept_untag2 = true;
 467         txvlan_cfg.insert_tag2_en = false;
 468         txvlan_cfg.default_tag2 = 0;
 469
 470         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 471         if (ret) {
 472                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 473                          ret);
 474                 return ret;
 475         }
 476
 477         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 478         return ret;
 479 }
 480
 481 static void
 482 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 483 {
 484         struct hns3_pf *pf = &hns->pf;
 485
 486         pf->port_base_vlan_cfg.state = on ?
 487             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 488
 489         pf->port_base_vlan_cfg.pvid = pvid;
 490 }
 491
 492 static void
 493 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 494 {
 495         struct hns3_user_vlan_table *vlan_entry;
 496         struct hns3_pf *pf = &hns->pf;
 497
 498         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 499                 if (vlan_entry->hd_tbl_status)
 500                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 501
 502                 vlan_entry->hd_tbl_status = false;
 503         }
 504
 505         if (is_del_list) {
 506                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 507                 while (vlan_entry) {
 508                         LIST_REMOVE(vlan_entry, next);
 509                         rte_free(vlan_entry);
 510                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 511                 }
 512         }
 513 }
 514
 515 static void
 516 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 517 {
 518         struct hns3_user_vlan_table *vlan_entry;
 519         struct hns3_pf *pf = &hns->pf;
 520
 521         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 522                 if (!vlan_entry->hd_tbl_status)
 523                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 524
 525                 vlan_entry->hd_tbl_status = true;
 526         }
 527 }
 528
 529 static int
 530 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 531                                 uint16_t port_base_vlan_state,
 532                                 uint16_t new_pvid, uint16_t old_pvid)
 533 {
 534         struct hns3_pf *pf = &hns->pf;
 535         struct hns3_hw *hw = &hns->hw;
 536         int ret = 0;
 537
 538         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 539                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 540                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 541                         if (ret) {
 542                                 hns3_err(hw,
 543                                          "Failed to clear clear old pvid filter, ret =%d",
 544                                          ret);
 545                                 return ret;
 546                         }
 547                 }
 548
 549                 hns3_rm_all_vlan_table(hns, false);
 550                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 551         }
 552
 553         if (new_pvid != 0) {
 554                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 555                 if (ret) {
 556                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 557                                  ret);
 558                         return ret;
 559                 }
 560         }
 561
 562         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 563                 hns3_add_all_vlan_table(hns);
 564
 565         return ret;
 566 }
 567
 568 static int
 569 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 570 {
 571         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 572         struct hns3_hw *hw = &hns->hw;
 573         bool rx_strip_en;
 574         int ret;
 575
 576         rx_strip_en = on ? true : false;
 577         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 578         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 579         rx_vlan_cfg.vlan1_vlan_prionly = false;
 580         rx_vlan_cfg.vlan2_vlan_prionly = false;
 581         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 582
 583         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 584         if (ret) {
 585                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 586                 return ret;
 587         }
 588
 589         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 590         return ret;
 591 }
 592
 593 static int
 594 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 595 {
 596         struct hns3_pf *pf = &hns->pf;
 597         struct hns3_hw *hw = &hns->hw;
 598         uint16_t port_base_vlan_state;
 599         uint16_t old_pvid;
 600         int ret;
 601
 602         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 603                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 604                         hns3_warn(hw, "Invalid operation! As current pvid set "
 605                                   "is %u, disable pvid %u is invalid",
 606                                   pf->port_base_vlan_cfg.pvid, pvid);
 607                 return 0;
 608         }
 609
 610         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 611                                     HNS3_PORT_BASE_VLAN_DISABLE;
 612         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 613         if (ret) {
 614                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 615                 return ret;
 616         }
 617
 618         ret = hns3_en_rx_strip_all(hns, on);
 619         if (ret) {
 620                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 621                 return ret;
 622         }
 623
 624         if (pvid == HNS3_INVLID_PVID)
 625                 goto out;
 626         old_pvid = pf->port_base_vlan_cfg.pvid;
 627         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 628                                               old_pvid);
 629         if (ret) {
 630                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 631                          ret);
 632                 return ret;
 633         }
 634
 635 out:
 636         hns3_store_port_base_vlan_info(hns, pvid, on);
 637         return ret;
 638 }
 639
 640 static int
 641 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 642 {
 643         struct hns3_adapter *hns = dev->data->dev_private;
 644         struct hns3_hw *hw = &hns->hw;
 645         int ret;
 646
 647         rte_spinlock_lock(&hw->lock);
 648         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 649         rte_spinlock_unlock(&hw->lock);
 650         return ret;
 651 }
 652
 653 static void
 654 init_port_base_vlan_info(struct hns3_hw *hw)
 655 {
 656         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 657         struct hns3_pf *pf = &hns->pf;
 658
 659         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 660         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 661 }
 662
 663 static int
 664 hns3_default_vlan_config(struct hns3_adapter *hns)
 665 {
 666         struct hns3_hw *hw = &hns->hw;
 667         int ret;
 668
 669         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 670         if (ret)
 671                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 672         return ret;
 673 }
 674
 675 static int
 676 hns3_init_vlan_config(struct hns3_adapter *hns)
 677 {
 678         struct hns3_hw *hw = &hns->hw;
 679         int ret;
 680
 681         /*
 682          * This function can be called in the initialization and reset process,
 683          * when in reset process, it means that hardware had been reseted
 684          * successfully and we need to restore the hardware configuration to
 685          * ensure that the hardware configuration remains unchanged before and
 686          * after reset.
 687          */
 688         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 689                 init_port_base_vlan_info(hw);
 690
 691         ret = hns3_enable_vlan_filter(hns, true);
 692         if (ret) {
 693                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 694                 return ret;
 695         }
 696
 697         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 698                                        RTE_ETHER_TYPE_VLAN);
 699         if (ret) {
 700                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 701                 return ret;
 702         }
 703
 704         /*
 705          * When in the reinit dev stage of the reset process, the following
 706          * vlan-related configurations may differ from those at initialization,
 707          * we will restore configurations to hardware in hns3_restore_vlan_table
 708          * and hns3_restore_vlan_conf later.
 709          */
 710         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 711                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 712                 if (ret) {
 713                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 714                         return ret;
 715                 }
 716
 717                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 718                 if (ret) {
 719                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 720                                  ret);
 721                         return ret;
 722                 }
 723         }
 724
 725         return hns3_default_vlan_config(hns);
 726 }
 727
 728 static int
 729 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
 730                 unsigned int tso_mss_max)
 731 {
 732         struct hns3_cfg_tso_status_cmd *req;
 733         struct hns3_cmd_desc desc;
 734         uint16_t tso_mss;
 735
 736         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
 737
 738         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
 739
 740         tso_mss = 0;
 741         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
 742                        tso_mss_min);
 743         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
 744
 745         tso_mss = 0;
 746         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
 747                        tso_mss_max);
 748         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
 749
 750         return hns3_cmd_send(hw, &desc, 1);
 751 }
 752
 753 int
 754 hns3_config_gro(struct hns3_hw *hw, bool en)
 755 {
 756         struct hns3_cfg_gro_status_cmd *req;
 757         struct hns3_cmd_desc desc;
 758         int ret;
 759
 760         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
 761         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
 762
 763         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
 764
 765         ret = hns3_cmd_send(hw, &desc, 1);
 766         if (ret)
 767                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
 768
 769         return ret;
 770 }
 771
 772 static int
 773 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
 774                    uint16_t *allocated_size, bool is_alloc)
 775 {
 776         struct hns3_umv_spc_alc_cmd *req;
 777         struct hns3_cmd_desc desc;
 778         int ret;
 779
 780         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
 781         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
 782         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
 783         req->space_size = rte_cpu_to_le_32(space_size);
 784
 785         ret = hns3_cmd_send(hw, &desc, 1);
 786         if (ret) {
 787                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
 788                              is_alloc ? "allocate" : "free", ret);
 789                 return ret;
 790         }
 791
 792         if (is_alloc && allocated_size)
 793                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 794
 795         return 0;
 796 }
 797
 798 static int
 799 hns3_init_umv_space(struct hns3_hw *hw)
 800 {
 801         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 802         struct hns3_pf *pf = &hns->pf;
 803         uint16_t allocated_size = 0;
 804         int ret;
 805
 806         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 807                                  true);
 808         if (ret)
 809                 return ret;
 810
 811         if (allocated_size < pf->wanted_umv_size)
 812                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 813                              pf->wanted_umv_size, allocated_size);
 814
 815         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 816                                                 pf->wanted_umv_size;
 817         pf->used_umv_size = 0;
 818         return 0;
 819 }
 820
 821 static int
 822 hns3_uninit_umv_space(struct hns3_hw *hw)
 823 {
 824         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 825         struct hns3_pf *pf = &hns->pf;
 826         int ret;
 827
 828         if (pf->max_umv_size == 0)
 829                 return 0;
 830
 831         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 832         if (ret)
 833                 return ret;
 834
 835         pf->max_umv_size = 0;
 836
 837         return 0;
 838 }
 839
 840 static bool
 841 hns3_is_umv_space_full(struct hns3_hw *hw)
 842 {
 843         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 844         struct hns3_pf *pf = &hns->pf;
 845         bool is_full;
 846
 847         is_full = (pf->used_umv_size >= pf->max_umv_size);
 848
 849         return is_full;
 850 }
 851
 852 static void
 853 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 854 {
 855         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 856         struct hns3_pf *pf = &hns->pf;
 857
 858         if (is_free) {
 859                 if (pf->used_umv_size > 0)
 860                         pf->used_umv_size--;
 861         } else
 862                 pf->used_umv_size++;
 863 }
 864
 865 static void
 866 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 867                       const uint8_t *addr, bool is_mc)
 868 {
 869         const unsigned char *mac_addr = addr;
 870         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 871                             ((uint32_t)mac_addr[2] << 16) |
 872                             ((uint32_t)mac_addr[1] << 8) |
 873                             (uint32_t)mac_addr[0];
 874         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 875
 876         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 877         if (is_mc) {
 878                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 879                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 880                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 881         }
 882
 883         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 884         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 885 }
 886
 887 static int
 888 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 889                              uint8_t resp_code,
 890                              enum hns3_mac_vlan_tbl_opcode op)
 891 {
 892         if (cmdq_resp) {
 893                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 894                          cmdq_resp);
 895                 return -EIO;
 896         }
 897
 898         if (op == HNS3_MAC_VLAN_ADD) {
 899                 if (resp_code == 0 || resp_code == 1) {
 900                         return 0;
 901                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 902                         hns3_err(hw, "add mac addr failed for uc_overflow");
 903                         return -ENOSPC;
 904                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 905                         hns3_err(hw, "add mac addr failed for mc_overflow");
 906                         return -ENOSPC;
 907                 }
 908
 909                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 910                          resp_code);
 911                 return -EIO;
 912         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 913                 if (resp_code == 0) {
 914                         return 0;
 915                 } else if (resp_code == 1) {
 916                         hns3_dbg(hw, "remove mac addr failed for miss");
 917                         return -ENOENT;
 918                 }
 919
 920                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 921                          resp_code);
 922                 return -EIO;
 923         } else if (op == HNS3_MAC_VLAN_LKUP) {
 924                 if (resp_code == 0) {
 925                         return 0;
 926                 } else if (resp_code == 1) {
 927                         hns3_dbg(hw, "lookup mac addr failed for miss");
 928                         return -ENOENT;
 929                 }
 930
 931                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 932                          resp_code);
 933                 return -EIO;
 934         }
 935
 936         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 937                  op);
 938
 939         return -EINVAL;
 940 }
 941
 942 static int
 943 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 944                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 945                          struct hns3_cmd_desc *desc, bool is_mc)
 946 {
 947         uint8_t resp_code;
 948         uint16_t retval;
 949         int ret;
 950
 951         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 952         if (is_mc) {
 953                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 954                 memcpy(desc[0].data, req,
 955                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 956                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 957                                           true);
 958                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 959                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 960                                           true);
 961                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 962         } else {
 963                 memcpy(desc[0].data, req,
 964                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 965                 ret = hns3_cmd_send(hw, desc, 1);
 966         }
 967         if (ret) {
 968                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 969                          ret);
 970                 return ret;
 971         }
 972         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 973         retval = rte_le_to_cpu_16(desc[0].retval);
 974
 975         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 976                                             HNS3_MAC_VLAN_LKUP);
 977 }
 978
 979 static int
 980 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 981                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 982                       struct hns3_cmd_desc *mc_desc)
 983 {
 984         uint8_t resp_code;
 985         uint16_t retval;
 986         int cfg_status;
 987         int ret;
 988
 989         if (mc_desc == NULL) {
 990                 struct hns3_cmd_desc desc;
 991
 992                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 993                 memcpy(desc.data, req,
 994                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 995                 ret = hns3_cmd_send(hw, &desc, 1);
 996                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 997                 retval = rte_le_to_cpu_16(desc.retval);
 998
 999                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1000                                                           HNS3_MAC_VLAN_ADD);
1001         } else {
1002                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1003                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1004                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1005                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1006                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1007                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1008                 memcpy(mc_desc[0].data, req,
1009                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1010                 mc_desc[0].retval = 0;
1011                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1012                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1013                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1014
1015                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1016                                                           HNS3_MAC_VLAN_ADD);
1017         }
1018
1019         if (ret) {
1020                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1021                 return ret;
1022         }
1023
1024         return cfg_status;
1025 }
1026
1027 static int
1028 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1029                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1030 {
1031         struct hns3_cmd_desc desc;
1032         uint8_t resp_code;
1033         uint16_t retval;
1034         int ret;
1035
1036         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1037
1038         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1039
1040         ret = hns3_cmd_send(hw, &desc, 1);
1041         if (ret) {
1042                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1043                 return ret;
1044         }
1045         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1046         retval = rte_le_to_cpu_16(desc.retval);
1047
1048         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1049                                             HNS3_MAC_VLAN_REMOVE);
1050 }
1051
1052 static int
1053 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1054 {
1055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1056         struct hns3_mac_vlan_tbl_entry_cmd req;
1057         struct hns3_pf *pf = &hns->pf;
1058         struct hns3_cmd_desc desc;
1059         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1060         uint16_t egress_port = 0;
1061         uint8_t vf_id;
1062         int ret;
1063
1064         /* check if mac addr is valid */
1065         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1066                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1067                                       mac_addr);
1068                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1069                          mac_str);
1070                 return -EINVAL;
1071         }
1072
1073         memset(&req, 0, sizeof(req));
1074
1075         /*
1076          * In current version VF is not supported when PF is driven by DPDK
1077          * driver, the PF-related vf_id is 0, just need to configure parameters
1078          * for vf_id 0.
1079          */
1080         vf_id = 0;
1081         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1082                        HNS3_MAC_EPORT_VFID_S, vf_id);
1083
1084         req.egress_port = rte_cpu_to_le_16(egress_port);
1085
1086         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1087
1088         /*
1089          * Lookup the mac address in the mac_vlan table, and add
1090          * it if the entry is inexistent. Repeated unicast entry
1091          * is not allowed in the mac vlan table.
1092          */
1093         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1094         if (ret == -ENOENT) {
1095                 if (!hns3_is_umv_space_full(hw)) {
1096                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1097                         if (!ret)
1098                                 hns3_update_umv_space(hw, false);
1099                         return ret;
1100                 }
1101
1102                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1103
1104                 return -ENOSPC;
1105         }
1106
1107         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1108
1109         /* check if we just hit the duplicate */
1110         if (ret == 0) {
1111                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1112                 return 0;
1113         }
1114
1115         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1116                  mac_str);
1117
1118         return ret;
1119 }
1120
1121 static int
1122 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1123                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1124 {
1125         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1127         int ret;
1128
1129         rte_spinlock_lock(&hw->lock);
1130         ret = hns3_add_uc_addr_common(hw, mac_addr);
1131         if (ret) {
1132                 rte_spinlock_unlock(&hw->lock);
1133                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1134                                       mac_addr);
1135                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1136                 return ret;
1137         }
1138
1139         if (idx == 0)
1140                 hw->mac.default_addr_setted = true;
1141         rte_spinlock_unlock(&hw->lock);
1142
1143         return ret;
1144 }
1145
1146 static int
1147 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1148 {
1149         struct hns3_mac_vlan_tbl_entry_cmd req;
1150         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1151         int ret;
1152
1153         /* check if mac addr is valid */
1154         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1155                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1156                                       mac_addr);
1157                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1158                          mac_str);
1159                 return -EINVAL;
1160         }
1161
1162         memset(&req, 0, sizeof(req));
1163         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1164         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1165         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1166         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1167                 return 0;
1168         else if (ret == 0)
1169                 hns3_update_umv_space(hw, true);
1170
1171         return ret;
1172 }
1173
1174 static void
1175 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1176 {
1177         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178         /* index will be checked by upper level rte interface */
1179         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1180         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1181         int ret;
1182
1183         rte_spinlock_lock(&hw->lock);
1184         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1185         if (ret) {
1186                 rte_spinlock_unlock(&hw->lock);
1187                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1188                                       mac_addr);
1189                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1190                 return;
1191         }
1192
1193         if (idx == 0)
1194                 hw->mac.default_addr_setted = false;
1195         rte_spinlock_unlock(&hw->lock);
1196 }
1197
1198 static int
1199 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1200                           struct rte_ether_addr *mac_addr)
1201 {
1202         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         struct rte_ether_addr *oaddr;
1204         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1205         bool default_addr_setted;
1206         bool rm_succes = false;
1207         int ret, ret_val;
1208
1209         /* check if mac addr is valid */
1210         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1211                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1212                                       mac_addr);
1213                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1214                          mac_str);
1215                 return -EINVAL;
1216         }
1217
1218         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1219         default_addr_setted = hw->mac.default_addr_setted;
1220         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1221                 return 0;
1222
1223         rte_spinlock_lock(&hw->lock);
1224         if (default_addr_setted) {
1225                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1226                 if (ret) {
1227                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1228                                               oaddr);
1229                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1230                                   mac_str, ret);
1231                         rm_succes = false;
1232                 } else
1233                         rm_succes = true;
1234         }
1235
1236         ret = hns3_add_uc_addr_common(hw, mac_addr);
1237         if (ret) {
1238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1239                                       mac_addr);
1240                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1241                 goto err_add_uc_addr;
1242         }
1243
1244         rte_ether_addr_copy(mac_addr,
1245                             (struct rte_ether_addr *)hw->mac.mac_addr);
1246         hw->mac.default_addr_setted = true;
1247         rte_spinlock_unlock(&hw->lock);
1248
1249         return 0;
1250
1251 err_add_uc_addr:
1252         if (rm_succes) {
1253                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1254                 if (ret_val) {
1255                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1256                                               oaddr);
1257                         hns3_warn(hw,
1258                                   "Failed to restore old uc mac addr(%s): %d",
1259                                   mac_str, ret_val);
1260                         hw->mac.default_addr_setted = false;
1261                 }
1262         }
1263         rte_spinlock_unlock(&hw->lock);
1264
1265         return ret;
1266 }
1267
1268 static void
1269 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1270 {
1271 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1272         uint8_t word_num;
1273         uint8_t bit_num;
1274
1275         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1276                 word_num = vfid / 32;
1277                 bit_num = vfid % 32;
1278                 if (clr)
1279                         desc[1].data[word_num] &=
1280                             rte_cpu_to_le_32(~(1UL << bit_num));
1281                 else
1282                         desc[1].data[word_num] |=
1283                             rte_cpu_to_le_32(1UL << bit_num);
1284         } else {
1285                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1286                 bit_num = vfid % 32;
1287                 if (clr)
1288                         desc[2].data[word_num] &=
1289                             rte_cpu_to_le_32(~(1UL << bit_num));
1290                 else
1291                         desc[2].data[word_num] |=
1292                             rte_cpu_to_le_32(1UL << bit_num);
1293         }
1294 }
1295
1296 static int
1297 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1298 {
1299         struct hns3_mac_vlan_tbl_entry_cmd req;
1300         struct hns3_cmd_desc desc[3];
1301         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1302         uint8_t vf_id;
1303         int ret;
1304
1305         /* Check if mac addr is valid */
1306         if (!rte_is_multicast_ether_addr(mac_addr)) {
1307                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1308                                       mac_addr);
1309                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1310                          mac_str);
1311                 return -EINVAL;
1312         }
1313
1314         memset(&req, 0, sizeof(req));
1315         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1316         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1317         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1318         if (ret) {
1319                 /* This mac addr do not exist, add new entry for it */
1320                 memset(desc[0].data, 0, sizeof(desc[0].data));
1321                 memset(desc[1].data, 0, sizeof(desc[0].data));
1322                 memset(desc[2].data, 0, sizeof(desc[0].data));
1323         }
1324
1325         /*
1326          * In current version VF is not supported when PF is driven by DPDK
1327          * driver, the PF-related vf_id is 0, just need to configure parameters
1328          * for vf_id 0.
1329          */
1330         vf_id = 0;
1331         hns3_update_desc_vfid(desc, vf_id, false);
1332         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1333         if (ret) {
1334                 if (ret == -ENOSPC)
1335                         hns3_err(hw, "mc mac vlan table is full");
1336                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1337                                       mac_addr);
1338                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1339         }
1340
1341         return ret;
1342 }
1343
1344 static int
1345 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1346 {
1347         struct hns3_mac_vlan_tbl_entry_cmd req;
1348         struct hns3_cmd_desc desc[3];
1349         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1350         uint8_t vf_id;
1351         int ret;
1352
1353         /* Check if mac addr is valid */
1354         if (!rte_is_multicast_ether_addr(mac_addr)) {
1355                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1356                                       mac_addr);
1357                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1358                          mac_str);
1359                 return -EINVAL;
1360         }
1361
1362         memset(&req, 0, sizeof(req));
1363         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1365         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1366         if (ret == 0) {
1367                 /*
1368                  * This mac addr exist, remove this handle's VFID for it.
1369                  * In current version VF is not supported when PF is driven by
1370                  * DPDK driver, the PF-related vf_id is 0, just need to
1371                  * configure parameters for vf_id 0.
1372                  */
1373                 vf_id = 0;
1374                 hns3_update_desc_vfid(desc, vf_id, true);
1375
1376                 /* All the vfid is zero, so need to delete this entry */
1377                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1378         } else if (ret == -ENOENT) {
1379                 /* This mac addr doesn't exist. */
1380                 return 0;
1381         }
1382
1383         if (ret) {
1384                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1385                                       mac_addr);
1386                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1387         }
1388
1389         return ret;
1390 }
1391
1392 static int
1393 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1394                            struct rte_ether_addr *mc_addr_set,
1395                            uint32_t nb_mc_addr)
1396 {
1397         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1398         struct rte_ether_addr *addr;
1399         uint32_t i;
1400         uint32_t j;
1401
1402         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1403                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1404                          "invalid. valid range: 0~%d",
1405                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1406                 return -EINVAL;
1407         }
1408
1409         /* Check if input mac addresses are valid */
1410         for (i = 0; i < nb_mc_addr; i++) {
1411                 addr = &mc_addr_set[i];
1412                 if (!rte_is_multicast_ether_addr(addr)) {
1413                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1414                                               addr);
1415                         hns3_err(hw,
1416                                  "Failed to set mc mac addr, addr(%s) invalid.",
1417                                  mac_str);
1418                         return -EINVAL;
1419                 }
1420
1421                 /* Check if there are duplicate addresses */
1422                 for (j = i + 1; j < nb_mc_addr; j++) {
1423                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1424                                 rte_ether_format_addr(mac_str,
1425                                                       RTE_ETHER_ADDR_FMT_SIZE,
1426                                                       addr);
1427                                 hns3_err(hw, "Failed to set mc mac addr, "
1428                                          "addrs invalid. two same addrs(%s).",
1429                                          mac_str);
1430                                 return -EINVAL;
1431                         }
1432                 }
1433         }
1434
1435         return 0;
1436 }
1437
1438 static void
1439 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1440                            struct rte_ether_addr *mc_addr_set,
1441                            int mc_addr_num,
1442                            struct rte_ether_addr *reserved_addr_list,
1443                            int *reserved_addr_num,
1444                            struct rte_ether_addr *add_addr_list,
1445                            int *add_addr_num,
1446                            struct rte_ether_addr *rm_addr_list,
1447                            int *rm_addr_num)
1448 {
1449         struct rte_ether_addr *addr;
1450         int current_addr_num;
1451         int reserved_num = 0;
1452         int add_num = 0;
1453         int rm_num = 0;
1454         int num;
1455         int i;
1456         int j;
1457         bool same_addr;
1458
1459         /* Calculate the mc mac address list that should be removed */
1460         current_addr_num = hw->mc_addrs_num;
1461         for (i = 0; i < current_addr_num; i++) {
1462                 addr = &hw->mc_addrs[i];
1463                 same_addr = false;
1464                 for (j = 0; j < mc_addr_num; j++) {
1465                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1466                                 same_addr = true;
1467                                 break;
1468                         }
1469                 }
1470
1471                 if (!same_addr) {
1472                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1473                         rm_num++;
1474                 } else {
1475                         rte_ether_addr_copy(addr,
1476                                             &reserved_addr_list[reserved_num]);
1477                         reserved_num++;
1478                 }
1479         }
1480
1481         /* Calculate the mc mac address list that should be added */
1482         for (i = 0; i < mc_addr_num; i++) {
1483                 addr = &mc_addr_set[i];
1484                 same_addr = false;
1485                 for (j = 0; j < current_addr_num; j++) {
1486                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1487                                 same_addr = true;
1488                                 break;
1489                         }
1490                 }
1491
1492                 if (!same_addr) {
1493                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1494                         add_num++;
1495                 }
1496         }
1497
1498         /* Reorder the mc mac address list maintained by driver */
1499         for (i = 0; i < reserved_num; i++)
1500                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1501
1502         for (i = 0; i < rm_num; i++) {
1503                 num = reserved_num + i;
1504                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1505         }
1506
1507         *reserved_addr_num = reserved_num;
1508         *add_addr_num = add_num;
1509         *rm_addr_num = rm_num;
1510 }
1511
1512 static int
1513 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1514                           struct rte_ether_addr *mc_addr_set,
1515                           uint32_t nb_mc_addr)
1516 {
1517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1519         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1520         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1521         struct rte_ether_addr *addr;
1522         int reserved_addr_num;
1523         int add_addr_num;
1524         int rm_addr_num;
1525         int mc_addr_num;
1526         int num;
1527         int ret;
1528         int i;
1529
1530         /* Check if input parameters are valid */
1531         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1532         if (ret)
1533                 return ret;
1534
1535         rte_spinlock_lock(&hw->lock);
1536
1537         /*
1538          * Calculate the mc mac address lists those should be removed and be
1539          * added, Reorder the mc mac address list maintained by driver.
1540          */
1541         mc_addr_num = (int)nb_mc_addr;
1542         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1543                                    reserved_addr_list, &reserved_addr_num,
1544                                    add_addr_list, &add_addr_num,
1545                                    rm_addr_list, &rm_addr_num);
1546
1547         /* Remove mc mac addresses */
1548         for (i = 0; i < rm_addr_num; i++) {
1549                 num = rm_addr_num - i - 1;
1550                 addr = &rm_addr_list[num];
1551                 ret = hns3_remove_mc_addr(hw, addr);
1552                 if (ret) {
1553                         rte_spinlock_unlock(&hw->lock);
1554                         return ret;
1555                 }
1556                 hw->mc_addrs_num--;
1557         }
1558
1559         /* Add mc mac addresses */
1560         for (i = 0; i < add_addr_num; i++) {
1561                 addr = &add_addr_list[i];
1562                 ret = hns3_add_mc_addr(hw, addr);
1563                 if (ret) {
1564                         rte_spinlock_unlock(&hw->lock);
1565                         return ret;
1566                 }
1567
1568                 num = reserved_addr_num + i;
1569                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1570                 hw->mc_addrs_num++;
1571         }
1572         rte_spinlock_unlock(&hw->lock);
1573
1574         return 0;
1575 }
1576
1577 static int
1578 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1579 {
1580         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1581         struct hns3_hw *hw = &hns->hw;
1582         struct rte_ether_addr *addr;
1583         int err = 0;
1584         int ret;
1585         int i;
1586
1587         for (i = 0; i < hw->mc_addrs_num; i++) {
1588                 addr = &hw->mc_addrs[i];
1589                 if (!rte_is_multicast_ether_addr(addr))
1590                         continue;
1591                 if (del)
1592                         ret = hns3_remove_mc_addr(hw, addr);
1593                 else
1594                         ret = hns3_add_mc_addr(hw, addr);
1595                 if (ret) {
1596                         err = ret;
1597                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1598                                               addr);
1599                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1600                                  del ? "Remove" : "Restore", mac_str);
1601                 }
1602         }
1603         return err;
1604 }
1605
1606 static int
1607 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
1608 {
1609         struct hns3_config_max_frm_size_cmd *req;
1610         struct hns3_cmd_desc desc;
1611
1612         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
1613
1614         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
1615         req->max_frm_size = rte_cpu_to_le_16(new_mps);
1616         req->min_frm_size = HNS3_MIN_FRAME_LEN;
1617
1618         return hns3_cmd_send(hw, &desc, 1);
1619 }
1620
1621 static int
1622 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
1623 {
1624         int ret;
1625
1626         ret = hns3_set_mac_mtu(hw, mps);
1627         if (ret) {
1628                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
1629                 return ret;
1630         }
1631
1632         ret = hns3_buffer_alloc(hw);
1633         if (ret) {
1634                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
1635                 return ret;
1636         }
1637
1638         return 0;
1639 }
1640
1641 static int
1642 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1643 {
1644         struct hns3_adapter *hns = dev->data->dev_private;
1645         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
1646         struct hns3_hw *hw = &hns->hw;
1647         bool is_jumbo_frame;
1648         int ret;
1649
1650         if (dev->data->dev_started) {
1651                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
1652                          "before configuration", dev->data->port_id);
1653                 return -EBUSY;
1654         }
1655
1656         rte_spinlock_lock(&hw->lock);
1657         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
1658         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
1659
1660         /*
1661          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
1662          * assign to "uint16_t" type variable.
1663          */
1664         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
1665         if (ret) {
1666                 rte_spinlock_unlock(&hw->lock);
1667                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
1668                          dev->data->port_id, mtu, ret);
1669                 return ret;
1670         }
1671         hns->pf.mps = (uint16_t)frame_size;
1672         if (is_jumbo_frame)
1673                 dev->data->dev_conf.rxmode.offloads |=
1674                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1675         else
1676                 dev->data->dev_conf.rxmode.offloads &=
1677                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1678         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1679         rte_spinlock_unlock(&hw->lock);
1680
1681         return 0;
1682 }
1683
1684 static int
1685 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
1686 {
1687         struct hns3_adapter *hns = eth_dev->data->dev_private;
1688         struct hns3_hw *hw = &hns->hw;
1689
1690         info->max_rx_queues = hw->tqps_num;
1691         info->max_tx_queues = hw->tqps_num;
1692         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1693         info->min_rx_bufsize = hw->rx_buf_len;
1694         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1695         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1696         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1697                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1698                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1699                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1700                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1701                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1702                                  DEV_RX_OFFLOAD_KEEP_CRC |
1703                                  DEV_RX_OFFLOAD_SCATTER |
1704                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1705                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1706                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1707                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1708                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1709         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1710         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1711                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1712                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1713                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1714                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1715                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1716                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1717                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1718                                  info->tx_queue_offload_capa);
1719
1720         info->vmdq_queue_num = 0;
1721
1722         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1723         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1724         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1725
1726         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1727         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1728         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1729         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1730
1731         return 0;
1732 }
1733
1734 static int
1735 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1736                     size_t fw_size)
1737 {
1738         struct hns3_adapter *hns = eth_dev->data->dev_private;
1739         struct hns3_hw *hw = &hns->hw;
1740         int ret;
1741
1742         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1743         ret += 1; /* add the size of '\0' */
1744         if (fw_size < (uint32_t)ret)
1745                 return ret;
1746         else
1747                 return 0;
1748 }
1749
1750 static int
1751 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1752                      __rte_unused int wait_to_complete)
1753 {
1754         struct hns3_adapter *hns = eth_dev->data->dev_private;
1755         struct hns3_hw *hw = &hns->hw;
1756         struct hns3_mac *mac = &hw->mac;
1757         struct rte_eth_link new_link;
1758
1759         memset(&new_link, 0, sizeof(new_link));
1760         switch (mac->link_speed) {
1761         case ETH_SPEED_NUM_10M:
1762         case ETH_SPEED_NUM_100M:
1763         case ETH_SPEED_NUM_1G:
1764         case ETH_SPEED_NUM_10G:
1765         case ETH_SPEED_NUM_25G:
1766         case ETH_SPEED_NUM_40G:
1767         case ETH_SPEED_NUM_50G:
1768         case ETH_SPEED_NUM_100G:
1769                 new_link.link_speed = mac->link_speed;
1770                 break;
1771         default:
1772                 new_link.link_speed = ETH_SPEED_NUM_100M;
1773                 break;
1774         }
1775
1776         new_link.link_duplex = mac->link_duplex;
1777         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1778         new_link.link_autoneg =
1779             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1780
1781         return rte_eth_linkstatus_set(eth_dev, &new_link);
1782 }
1783
1784 static int
1785 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1786 {
1787         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1788         struct hns3_pf *pf = &hns->pf;
1789
1790         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1791                 return -EINVAL;
1792
1793         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1794
1795         return 0;
1796 }
1797
1798 static int
1799 hns3_query_function_status(struct hns3_hw *hw)
1800 {
1801 #define HNS3_QUERY_MAX_CNT              10
1802 #define HNS3_QUERY_SLEEP_MSCOEND        1
1803         struct hns3_func_status_cmd *req;
1804         struct hns3_cmd_desc desc;
1805         int timeout = 0;
1806         int ret;
1807
1808         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1809         req = (struct hns3_func_status_cmd *)desc.data;
1810
1811         do {
1812                 ret = hns3_cmd_send(hw, &desc, 1);
1813                 if (ret) {
1814                         PMD_INIT_LOG(ERR, "query function status failed %d",
1815                                      ret);
1816                         return ret;
1817                 }
1818
1819                 /* Check pf reset is done */
1820                 if (req->pf_state)
1821                         break;
1822
1823                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1824         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1825
1826         return hns3_parse_func_status(hw, req);
1827 }
1828
1829 static int
1830 hns3_query_pf_resource(struct hns3_hw *hw)
1831 {
1832         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1833         struct hns3_pf *pf = &hns->pf;
1834         struct hns3_pf_res_cmd *req;
1835         struct hns3_cmd_desc desc;
1836         int ret;
1837
1838         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1839         ret = hns3_cmd_send(hw, &desc, 1);
1840         if (ret) {
1841                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1842                 return ret;
1843         }
1844
1845         req = (struct hns3_pf_res_cmd *)desc.data;
1846         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1847         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1848         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1849
1850         if (req->tx_buf_size)
1851                 pf->tx_buf_size =
1852                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1853         else
1854                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1855
1856         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1857
1858         if (req->dv_buf_size)
1859                 pf->dv_buf_size =
1860                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1861         else
1862                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1863
1864         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1865
1866         hw->num_msi =
1867             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1868                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1869
1870         return 0;
1871 }
1872
1873 static void
1874 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1875 {
1876         struct hns3_cfg_param_cmd *req;
1877         uint64_t mac_addr_tmp_high;
1878         uint64_t mac_addr_tmp;
1879         uint32_t i;
1880
1881         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1882
1883         /* get the configuration */
1884         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1885                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1886         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1887                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1888         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1889                                            HNS3_CFG_TQP_DESC_N_M,
1890                                            HNS3_CFG_TQP_DESC_N_S);
1891
1892         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1893                                        HNS3_CFG_PHY_ADDR_M,
1894                                        HNS3_CFG_PHY_ADDR_S);
1895         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1896                                          HNS3_CFG_MEDIA_TP_M,
1897                                          HNS3_CFG_MEDIA_TP_S);
1898         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1899                                          HNS3_CFG_RX_BUF_LEN_M,
1900                                          HNS3_CFG_RX_BUF_LEN_S);
1901         /* get mac address */
1902         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1903         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1904                                            HNS3_CFG_MAC_ADDR_H_M,
1905                                            HNS3_CFG_MAC_ADDR_H_S);
1906
1907         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1908
1909         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1910                                             HNS3_CFG_DEFAULT_SPEED_M,
1911                                             HNS3_CFG_DEFAULT_SPEED_S);
1912         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1913                                            HNS3_CFG_RSS_SIZE_M,
1914                                            HNS3_CFG_RSS_SIZE_S);
1915
1916         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1917                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1918
1919         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1920         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1921
1922         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1923                                             HNS3_CFG_SPEED_ABILITY_M,
1924                                             HNS3_CFG_SPEED_ABILITY_S);
1925         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1926                                         HNS3_CFG_UMV_TBL_SPACE_M,
1927                                         HNS3_CFG_UMV_TBL_SPACE_S);
1928         if (!cfg->umv_space)
1929                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1930 }
1931
1932 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1933  * @hw: pointer to struct hns3_hw
1934  * @hcfg: the config structure to be getted
1935  */
1936 static int
1937 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1938 {
1939         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1940         struct hns3_cfg_param_cmd *req;
1941         uint32_t offset;
1942         uint32_t i;
1943         int ret;
1944
1945         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1946                 offset = 0;
1947                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1948                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1949                                           true);
1950                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1951                                i * HNS3_CFG_RD_LEN_BYTES);
1952                 /* Len should be divided by 4 when send to hardware */
1953                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1954                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1955                 req->offset = rte_cpu_to_le_32(offset);
1956         }
1957
1958         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1959         if (ret) {
1960                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1961                 return ret;
1962         }
1963
1964         hns3_parse_cfg(hcfg, desc);
1965
1966         return 0;
1967 }
1968
1969 static int
1970 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1971 {
1972         switch (speed_cmd) {
1973         case HNS3_CFG_SPEED_10M:
1974                 *speed = ETH_SPEED_NUM_10M;
1975                 break;
1976         case HNS3_CFG_SPEED_100M:
1977                 *speed = ETH_SPEED_NUM_100M;
1978                 break;
1979         case HNS3_CFG_SPEED_1G:
1980                 *speed = ETH_SPEED_NUM_1G;
1981                 break;
1982         case HNS3_CFG_SPEED_10G:
1983                 *speed = ETH_SPEED_NUM_10G;
1984                 break;
1985         case HNS3_CFG_SPEED_25G:
1986                 *speed = ETH_SPEED_NUM_25G;
1987                 break;
1988         case HNS3_CFG_SPEED_40G:
1989                 *speed = ETH_SPEED_NUM_40G;
1990                 break;
1991         case HNS3_CFG_SPEED_50G:
1992                 *speed = ETH_SPEED_NUM_50G;
1993                 break;
1994         case HNS3_CFG_SPEED_100G:
1995                 *speed = ETH_SPEED_NUM_100G;
1996                 break;
1997         default:
1998                 return -EINVAL;
1999         }
2000
2001         return 0;
2002 }
2003
2004 static int
2005 hns3_get_board_configuration(struct hns3_hw *hw)
2006 {
2007         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2008         struct hns3_pf *pf = &hns->pf;
2009         struct hns3_cfg cfg;
2010         int ret;
2011
2012         ret = hns3_get_board_cfg(hw, &cfg);
2013         if (ret) {
2014                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2015                 return ret;
2016         }
2017
2018         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2019                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2020                 return -EOPNOTSUPP;
2021         }
2022
2023         hw->mac.media_type = cfg.media_type;
2024         hw->rss_size_max = cfg.rss_size_max;
2025         hw->rx_buf_len = cfg.rx_buf_len;
2026         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2027         hw->mac.phy_addr = cfg.phy_addr;
2028         hw->mac.default_addr_setted = false;
2029         hw->num_tx_desc = cfg.tqp_desc_num;
2030         hw->num_rx_desc = cfg.tqp_desc_num;
2031         hw->dcb_info.num_pg = 1;
2032         hw->dcb_info.hw_pfc_map = 0;
2033
2034         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2035         if (ret) {
2036                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2037                              cfg.default_speed, ret);
2038                 return ret;
2039         }
2040
2041         pf->tc_max = cfg.tc_num;
2042         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2043                 PMD_INIT_LOG(WARNING,
2044                              "Get TC num(%u) from flash, set TC num to 1",
2045                              pf->tc_max);
2046                 pf->tc_max = 1;
2047         }
2048
2049         /* Dev does not support DCB */
2050         if (!hns3_dev_dcb_supported(hw)) {
2051                 pf->tc_max = 1;
2052                 pf->pfc_max = 0;
2053         } else
2054                 pf->pfc_max = pf->tc_max;
2055
2056         hw->dcb_info.num_tc = 1;
2057         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2058                                      hw->tqps_num / hw->dcb_info.num_tc);
2059         hns3_set_bit(hw->hw_tc_map, 0, 1);
2060         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2061
2062         pf->wanted_umv_size = cfg.umv_space;
2063
2064         return ret;
2065 }
2066
2067 static int
2068 hns3_get_configuration(struct hns3_hw *hw)
2069 {
2070         int ret;
2071
2072         ret = hns3_query_function_status(hw);
2073         if (ret) {
2074                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2075                 return ret;
2076         }
2077
2078         /* Get pf resource */
2079         ret = hns3_query_pf_resource(hw);
2080         if (ret) {
2081                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2082                 return ret;
2083         }
2084
2085         ret = hns3_get_board_configuration(hw);
2086         if (ret) {
2087                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2088                 return ret;
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int
2095 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2096                       uint16_t tqp_vid, bool is_pf)
2097 {
2098         struct hns3_tqp_map_cmd *req;
2099         struct hns3_cmd_desc desc;
2100         int ret;
2101
2102         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2103
2104         req = (struct hns3_tqp_map_cmd *)desc.data;
2105         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2106         req->tqp_vf = func_id;
2107         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2108         if (!is_pf)
2109                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2110         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2111
2112         ret = hns3_cmd_send(hw, &desc, 1);
2113         if (ret)
2114                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2115
2116         return ret;
2117 }
2118
2119 static int
2120 hns3_map_tqp(struct hns3_hw *hw)
2121 {
2122         uint16_t tqps_num = hw->total_tqps_num;
2123         uint16_t func_id;
2124         uint16_t tqp_id;
2125         int num;
2126         int ret;
2127         int i;
2128
2129         /*
2130          * In current version VF is not supported when PF is driven by DPDK
2131          * driver, so we allocate tqps to PF as much as possible.
2132          */
2133         tqp_id = 0;
2134         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2135         for (func_id = 0; func_id < num; func_id++) {
2136                 for (i = 0;
2137                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2138                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2139                                                     true);
2140                         if (ret)
2141                                 return ret;
2142                 }
2143         }
2144
2145         return 0;
2146 }
2147
2148 static int
2149 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2150 {
2151         struct hns3_config_mac_speed_dup_cmd *req;
2152         struct hns3_cmd_desc desc;
2153         int ret;
2154
2155         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2156
2157         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2158
2159         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2160
2161         switch (speed) {
2162         case ETH_SPEED_NUM_10M:
2163                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2164                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2165                 break;
2166         case ETH_SPEED_NUM_100M:
2167                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2168                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2169                 break;
2170         case ETH_SPEED_NUM_1G:
2171                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2172                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2173                 break;
2174         case ETH_SPEED_NUM_10G:
2175                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2176                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2177                 break;
2178         case ETH_SPEED_NUM_25G:
2179                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2180                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2181                 break;
2182         case ETH_SPEED_NUM_40G:
2183                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2184                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2185                 break;
2186         case ETH_SPEED_NUM_50G:
2187                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2188                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2189                 break;
2190         case ETH_SPEED_NUM_100G:
2191                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2192                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2193                 break;
2194         default:
2195                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2196                 return -EINVAL;
2197         }
2198
2199         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2200
2201         ret = hns3_cmd_send(hw, &desc, 1);
2202         if (ret)
2203                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2204
2205         return ret;
2206 }
2207
2208 static int
2209 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2210 {
2211         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2212         struct hns3_pf *pf = &hns->pf;
2213         struct hns3_priv_buf *priv;
2214         uint32_t i, total_size;
2215
2216         total_size = pf->pkt_buf_size;
2217
2218         /* alloc tx buffer for all enabled tc */
2219         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2220                 priv = &buf_alloc->priv_buf[i];
2221
2222                 if (hw->hw_tc_map & BIT(i)) {
2223                         if (total_size < pf->tx_buf_size)
2224                                 return -ENOMEM;
2225
2226                         priv->tx_buf_size = pf->tx_buf_size;
2227                 } else
2228                         priv->tx_buf_size = 0;
2229
2230                 total_size -= priv->tx_buf_size;
2231         }
2232
2233         return 0;
2234 }
2235
2236 static int
2237 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2238 {
2239 /* TX buffer size is unit by 128 byte */
2240 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2241 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2242         struct hns3_tx_buff_alloc_cmd *req;
2243         struct hns3_cmd_desc desc;
2244         uint32_t buf_size;
2245         uint32_t i;
2246         int ret;
2247
2248         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2249
2250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2251         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2252                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2253
2254                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2255                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2256                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2257         }
2258
2259         ret = hns3_cmd_send(hw, &desc, 1);
2260         if (ret)
2261                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2262
2263         return ret;
2264 }
2265
2266 static int
2267 hns3_get_tc_num(struct hns3_hw *hw)
2268 {
2269         int cnt = 0;
2270         uint8_t i;
2271
2272         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2273                 if (hw->hw_tc_map & BIT(i))
2274                         cnt++;
2275         return cnt;
2276 }
2277
2278 static uint32_t
2279 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2280 {
2281         struct hns3_priv_buf *priv;
2282         uint32_t rx_priv = 0;
2283         int i;
2284
2285         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2286                 priv = &buf_alloc->priv_buf[i];
2287                 if (priv->enable)
2288                         rx_priv += priv->buf_size;
2289         }
2290         return rx_priv;
2291 }
2292
2293 static uint32_t
2294 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2295 {
2296         uint32_t total_tx_size = 0;
2297         uint32_t i;
2298
2299         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2300                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2301
2302         return total_tx_size;
2303 }
2304
2305 /* Get the number of pfc enabled TCs, which have private buffer */
2306 static int
2307 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2308 {
2309         struct hns3_priv_buf *priv;
2310         int cnt = 0;
2311         uint8_t i;
2312
2313         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2314                 priv = &buf_alloc->priv_buf[i];
2315                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2316                         cnt++;
2317         }
2318
2319         return cnt;
2320 }
2321
2322 /* Get the number of pfc disabled TCs, which have private buffer */
2323 static int
2324 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2325                          struct hns3_pkt_buf_alloc *buf_alloc)
2326 {
2327         struct hns3_priv_buf *priv;
2328         int cnt = 0;
2329         uint8_t i;
2330
2331         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2332                 priv = &buf_alloc->priv_buf[i];
2333                 if (hw->hw_tc_map & BIT(i) &&
2334                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2335                         cnt++;
2336         }
2337
2338         return cnt;
2339 }
2340
2341 static bool
2342 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2343                   uint32_t rx_all)
2344 {
2345         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2346         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2347         struct hns3_pf *pf = &hns->pf;
2348         uint32_t shared_buf, aligned_mps;
2349         uint32_t rx_priv;
2350         uint8_t tc_num;
2351         uint8_t i;
2352
2353         tc_num = hns3_get_tc_num(hw);
2354         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2355
2356         if (hns3_dev_dcb_supported(hw))
2357                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2358                                         pf->dv_buf_size;
2359         else
2360                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2361                                         + pf->dv_buf_size;
2362
2363         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2364         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2365                              HNS3_BUF_SIZE_UNIT);
2366
2367         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2368         if (rx_all < rx_priv + shared_std)
2369                 return false;
2370
2371         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2372         buf_alloc->s_buf.buf_size = shared_buf;
2373         if (hns3_dev_dcb_supported(hw)) {
2374                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2375                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2376                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2377                                   HNS3_BUF_SIZE_UNIT);
2378         } else {
2379                 buf_alloc->s_buf.self.high =
2380                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2381                 buf_alloc->s_buf.self.low = aligned_mps;
2382         }
2383
2384         if (hns3_dev_dcb_supported(hw)) {
2385                 hi_thrd = shared_buf - pf->dv_buf_size;
2386
2387                 if (tc_num <= NEED_RESERVE_TC_NUM)
2388                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2389                                         / BUF_MAX_PERCENT;
2390
2391                 if (tc_num)
2392                         hi_thrd = hi_thrd / tc_num;
2393
2394                 hi_thrd = max_t(uint32_t, hi_thrd,
2395                                 HNS3_BUF_MUL_BY * aligned_mps);
2396                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2397                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2398         } else {
2399                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2400                 lo_thrd = aligned_mps;
2401         }
2402
2403         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2404                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2405                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2406         }
2407
2408         return true;
2409 }
2410
2411 static bool
2412 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2413                      struct hns3_pkt_buf_alloc *buf_alloc)
2414 {
2415         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2416         struct hns3_pf *pf = &hns->pf;
2417         struct hns3_priv_buf *priv;
2418         uint32_t aligned_mps;
2419         uint32_t rx_all;
2420         uint8_t i;
2421
2422         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2423         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2424
2425         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2426                 priv = &buf_alloc->priv_buf[i];
2427
2428                 priv->enable = 0;
2429                 priv->wl.low = 0;
2430                 priv->wl.high = 0;
2431                 priv->buf_size = 0;
2432
2433                 if (!(hw->hw_tc_map & BIT(i)))
2434                         continue;
2435
2436                 priv->enable = 1;
2437                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2438                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2439                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2440                                                 HNS3_BUF_SIZE_UNIT);
2441                 } else {
2442                         priv->wl.low = 0;
2443                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
2444                                         aligned_mps;
2445                 }
2446
2447                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
2448         }
2449
2450         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2451 }
2452
2453 static bool
2454 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
2455                              struct hns3_pkt_buf_alloc *buf_alloc)
2456 {
2457         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2458         struct hns3_pf *pf = &hns->pf;
2459         struct hns3_priv_buf *priv;
2460         int no_pfc_priv_num;
2461         uint32_t rx_all;
2462         uint8_t mask;
2463         int i;
2464
2465         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2466         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
2467
2468         /* let the last to be cleared first */
2469         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2470                 priv = &buf_alloc->priv_buf[i];
2471                 mask = BIT((uint8_t)i);
2472
2473                 if (hw->hw_tc_map & mask &&
2474                     !(hw->dcb_info.hw_pfc_map & mask)) {
2475                         /* Clear the no pfc TC private buffer */
2476                         priv->wl.low = 0;
2477                         priv->wl.high = 0;
2478                         priv->buf_size = 0;
2479                         priv->enable = 0;
2480                         no_pfc_priv_num--;
2481                 }
2482
2483                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2484                     no_pfc_priv_num == 0)
2485                         break;
2486         }
2487
2488         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2489 }
2490
2491 static bool
2492 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
2493                            struct hns3_pkt_buf_alloc *buf_alloc)
2494 {
2495         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2496         struct hns3_pf *pf = &hns->pf;
2497         struct hns3_priv_buf *priv;
2498         uint32_t rx_all;
2499         int pfc_priv_num;
2500         uint8_t mask;
2501         int i;
2502
2503         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2504         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
2505
2506         /* let the last to be cleared first */
2507         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2508                 priv = &buf_alloc->priv_buf[i];
2509                 mask = BIT((uint8_t)i);
2510
2511                 if (hw->hw_tc_map & mask &&
2512                     hw->dcb_info.hw_pfc_map & mask) {
2513                         /* Reduce the number of pfc TC with private buffer */
2514                         priv->wl.low = 0;
2515                         priv->enable = 0;
2516                         priv->wl.high = 0;
2517                         priv->buf_size = 0;
2518                         pfc_priv_num--;
2519                 }
2520                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2521                     pfc_priv_num == 0)
2522                         break;
2523         }
2524
2525         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2526 }
2527
2528 static bool
2529 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
2530                           struct hns3_pkt_buf_alloc *buf_alloc)
2531 {
2532 #define COMPENSATE_BUFFER       0x3C00
2533 #define COMPENSATE_HALF_MPS_NUM 5
2534 #define PRIV_WL_GAP             0x1800
2535         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2536         struct hns3_pf *pf = &hns->pf;
2537         uint32_t tc_num = hns3_get_tc_num(hw);
2538         uint32_t half_mps = pf->mps >> 1;
2539         struct hns3_priv_buf *priv;
2540         uint32_t min_rx_priv;
2541         uint32_t rx_priv;
2542         uint8_t i;
2543
2544         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2545         if (tc_num)
2546                 rx_priv = rx_priv / tc_num;
2547
2548         if (tc_num <= NEED_RESERVE_TC_NUM)
2549                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2550
2551         /*
2552          * Minimum value of private buffer in rx direction (min_rx_priv) is
2553          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
2554          * buffer if rx_priv is greater than min_rx_priv.
2555          */
2556         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
2557                         COMPENSATE_HALF_MPS_NUM * half_mps;
2558         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
2559         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
2560
2561         if (rx_priv < min_rx_priv)
2562                 return false;
2563
2564         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2565                 priv = &buf_alloc->priv_buf[i];
2566
2567                 priv->enable = 0;
2568                 priv->wl.low = 0;
2569                 priv->wl.high = 0;
2570                 priv->buf_size = 0;
2571
2572                 if (!(hw->hw_tc_map & BIT(i)))
2573                         continue;
2574
2575                 priv->enable = 1;
2576                 priv->buf_size = rx_priv;
2577                 priv->wl.high = rx_priv - pf->dv_buf_size;
2578                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2579         }
2580
2581         buf_alloc->s_buf.buf_size = 0;
2582
2583         return true;
2584 }
2585
2586 /*
2587  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
2588  * @hw: pointer to struct hns3_hw
2589  * @buf_alloc: pointer to buffer calculation data
2590  * @return: 0: calculate sucessful, negative: fail
2591  */
2592 static int
2593 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2594 {
2595         /* When DCB is not supported, rx private buffer is not allocated. */
2596         if (!hns3_dev_dcb_supported(hw)) {
2597                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2598                 struct hns3_pf *pf = &hns->pf;
2599                 uint32_t rx_all = pf->pkt_buf_size;
2600
2601                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
2602                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
2603                         return -ENOMEM;
2604
2605                 return 0;
2606         }
2607
2608         /*
2609          * Try to allocate privated packet buffer for all TCs without share
2610          * buffer.
2611          */
2612         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
2613                 return 0;
2614
2615         /*
2616          * Try to allocate privated packet buffer for all TCs with share
2617          * buffer.
2618          */
2619         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
2620                 return 0;
2621
2622         /*
2623          * For different application scenes, the enabled port number, TC number
2624          * and no_drop TC number are different. In order to obtain the better
2625          * performance, software could allocate the buffer size and configure
2626          * the waterline by tring to decrease the private buffer size according
2627          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
2628          * enabled tc.
2629          */
2630         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
2631                 return 0;
2632
2633         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
2634                 return 0;
2635
2636         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
2637                 return 0;
2638
2639         return -ENOMEM;
2640 }
2641
2642 static int
2643 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2644 {
2645         struct hns3_rx_priv_buff_cmd *req;
2646         struct hns3_cmd_desc desc;
2647         uint32_t buf_size;
2648         int ret;
2649         int i;
2650
2651         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
2652         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
2653
2654         /* Alloc private buffer TCs */
2655         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2656                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
2657
2658                 req->buf_num[i] =
2659                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
2660                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
2661         }
2662
2663         buf_size = buf_alloc->s_buf.buf_size;
2664         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
2665                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
2666
2667         ret = hns3_cmd_send(hw, &desc, 1);
2668         if (ret)
2669                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
2670
2671         return ret;
2672 }
2673
2674 static int
2675 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2676 {
2677 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
2678         struct hns3_rx_priv_wl_buf *req;
2679         struct hns3_priv_buf *priv;
2680         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
2681         int i, j;
2682         int ret;
2683
2684         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
2685                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
2686                                           false);
2687                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
2688
2689                 /* The first descriptor set the NEXT bit to 1 */
2690                 if (i == 0)
2691                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2692                 else
2693                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2694
2695                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2696                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2697
2698                         priv = &buf_alloc->priv_buf[idx];
2699                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2700                                                         HNS3_BUF_UNIT_S);
2701                         req->tc_wl[j].high |=
2702                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2703                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2704                                                         HNS3_BUF_UNIT_S);
2705                         req->tc_wl[j].low |=
2706                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2707                 }
2708         }
2709
2710         /* Send 2 descriptor at one time */
2711         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2712         if (ret)
2713                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2714                              ret);
2715         return ret;
2716 }
2717
2718 static int
2719 hns3_common_thrd_config(struct hns3_hw *hw,
2720                         struct hns3_pkt_buf_alloc *buf_alloc)
2721 {
2722 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2723         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2724         struct hns3_rx_com_thrd *req;
2725         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2726         struct hns3_tc_thrd *tc;
2727         int tc_idx;
2728         int i, j;
2729         int ret;
2730
2731         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2732                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2733                                           false);
2734                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2735
2736                 /* The first descriptor set the NEXT bit to 1 */
2737                 if (i == 0)
2738                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2739                 else
2740                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2741
2742                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2743                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2744                         tc = &s_buf->tc_thrd[tc_idx];
2745
2746                         req->com_thrd[j].high =
2747                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2748                         req->com_thrd[j].high |=
2749                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2750                         req->com_thrd[j].low =
2751                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2752                         req->com_thrd[j].low |=
2753                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2754                 }
2755         }
2756
2757         /* Send 2 descriptors at one time */
2758         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2759         if (ret)
2760                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2761
2762         return ret;
2763 }
2764
2765 static int
2766 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2767 {
2768         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2769         struct hns3_rx_com_wl *req;
2770         struct hns3_cmd_desc desc;
2771         int ret;
2772
2773         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2774
2775         req = (struct hns3_rx_com_wl *)desc.data;
2776         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2777         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2778
2779         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2780         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2781
2782         ret = hns3_cmd_send(hw, &desc, 1);
2783         if (ret)
2784                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2785
2786         return ret;
2787 }
2788
2789 int
2790 hns3_buffer_alloc(struct hns3_hw *hw)
2791 {
2792         struct hns3_pkt_buf_alloc pkt_buf;
2793         int ret;
2794
2795         memset(&pkt_buf, 0, sizeof(pkt_buf));
2796         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2797         if (ret) {
2798                 PMD_INIT_LOG(ERR,
2799                              "could not calc tx buffer size for all TCs %d",
2800                              ret);
2801                 return ret;
2802         }
2803
2804         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2805         if (ret) {
2806                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2807                 return ret;
2808         }
2809
2810         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2811         if (ret) {
2812                 PMD_INIT_LOG(ERR,
2813                              "could not calc rx priv buffer size for all TCs %d",
2814                              ret);
2815                 return ret;
2816         }
2817
2818         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2819         if (ret) {
2820                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2821                 return ret;
2822         }
2823
2824         if (hns3_dev_dcb_supported(hw)) {
2825                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2826                 if (ret) {
2827                         PMD_INIT_LOG(ERR,
2828                                      "could not configure rx private waterline %d",
2829                                      ret);
2830                         return ret;
2831                 }
2832
2833                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2834                 if (ret) {
2835                         PMD_INIT_LOG(ERR,
2836                                      "could not configure common threshold %d",
2837                                      ret);
2838                         return ret;
2839                 }
2840         }
2841
2842         ret = hns3_common_wl_config(hw, &pkt_buf);
2843         if (ret)
2844                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2845                              ret);
2846
2847         return ret;
2848 }
2849
2850 static int
2851 hns3_mac_init(struct hns3_hw *hw)
2852 {
2853         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2854         struct hns3_mac *mac = &hw->mac;
2855         struct hns3_pf *pf = &hns->pf;
2856         int ret;
2857
2858         pf->support_sfp_query = true;
2859         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2860         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2861         if (ret) {
2862                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2863                 return ret;
2864         }
2865
2866         mac->link_status = ETH_LINK_DOWN;
2867
2868         return hns3_config_mtu(hw, pf->mps);
2869 }
2870
2871 static int
2872 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2873 {
2874 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2875 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2876 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2877 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2878         int return_status;
2879
2880         if (cmdq_resp) {
2881                 PMD_INIT_LOG(ERR,
2882                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2883                              cmdq_resp);
2884                 return -EIO;
2885         }
2886
2887         switch (resp_code) {
2888         case HNS3_ETHERTYPE_SUCCESS_ADD:
2889         case HNS3_ETHERTYPE_ALREADY_ADD:
2890                 return_status = 0;
2891                 break;
2892         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2893                 PMD_INIT_LOG(ERR,
2894                              "add mac ethertype failed for manager table overflow.");
2895                 return_status = -EIO;
2896                 break;
2897         case HNS3_ETHERTYPE_KEY_CONFLICT:
2898                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2899                 return_status = -EIO;
2900                 break;
2901         default:
2902                 PMD_INIT_LOG(ERR,
2903                              "add mac ethertype failed for undefined, code=%d.",
2904                              resp_code);
2905                 return_status = -EIO;
2906         }
2907
2908         return return_status;
2909 }
2910
2911 static int
2912 hns3_add_mgr_tbl(struct hns3_hw *hw,
2913                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2914 {
2915         struct hns3_cmd_desc desc;
2916         uint8_t resp_code;
2917         uint16_t retval;
2918         int ret;
2919
2920         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2921         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2922
2923         ret = hns3_cmd_send(hw, &desc, 1);
2924         if (ret) {
2925                 PMD_INIT_LOG(ERR,
2926                              "add mac ethertype failed for cmd_send, ret =%d.",
2927                              ret);
2928                 return ret;
2929         }
2930
2931         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2932         retval = rte_le_to_cpu_16(desc.retval);
2933
2934         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2935 }
2936
2937 static void
2938 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2939                      int *table_item_num)
2940 {
2941         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2942
2943         /*
2944          * In current version, we add one item in management table as below:
2945          * 0x0180C200000E -- LLDP MC address
2946          */
2947         tbl = mgr_table;
2948         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2949         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2950         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2951         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2952         tbl->i_port_bitmap = 0x1;
2953         *table_item_num = 1;
2954 }
2955
2956 static int
2957 hns3_init_mgr_tbl(struct hns3_hw *hw)
2958 {
2959 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2960         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2961         int table_item_num;
2962         int ret;
2963         int i;
2964
2965         memset(mgr_table, 0, sizeof(mgr_table));
2966         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2967         for (i = 0; i < table_item_num; i++) {
2968                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2969                 if (ret) {
2970                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2971                                      ret);
2972                         return ret;
2973                 }
2974         }
2975
2976         return 0;
2977 }
2978
2979 static void
2980 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2981                         bool en_mc, bool en_bc, int vport_id)
2982 {
2983         if (!param)
2984                 return;
2985
2986         memset(param, 0, sizeof(struct hns3_promisc_param));
2987         if (en_uc)
2988                 param->enable = HNS3_PROMISC_EN_UC;
2989         if (en_mc)
2990                 param->enable |= HNS3_PROMISC_EN_MC;
2991         if (en_bc)
2992                 param->enable |= HNS3_PROMISC_EN_BC;
2993         param->vf_id = vport_id;
2994 }
2995
2996 static int
2997 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2998 {
2999         struct hns3_promisc_cfg_cmd *req;
3000         struct hns3_cmd_desc desc;
3001         int ret;
3002
3003         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3004
3005         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3006         req->vf_id = param->vf_id;
3007         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3008             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3009
3010         ret = hns3_cmd_send(hw, &desc, 1);
3011         if (ret)
3012                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3013
3014         return ret;
3015 }
3016
3017 static int
3018 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3019 {
3020         struct hns3_promisc_param param;
3021         bool en_bc_pmc = true;
3022         uint8_t vf_id;
3023         int ret;
3024
3025         /*
3026          * In current version VF is not supported when PF is driven by DPDK
3027          * driver, the PF-related vf_id is 0, just need to configure parameters
3028          * for vf_id 0.
3029          */
3030         vf_id = 0;
3031
3032         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3033         ret = hns3_cmd_set_promisc_mode(hw, &param);
3034         if (ret)
3035                 return ret;
3036
3037         return 0;
3038 }
3039
3040 static int
3041 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3042 {
3043         struct hns3_sfp_speed_cmd *resp;
3044         struct hns3_cmd_desc desc;
3045         int ret;
3046
3047         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3048         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3049         ret = hns3_cmd_send(hw, &desc, 1);
3050         if (ret == -EOPNOTSUPP) {
3051                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3052                 return ret;
3053         } else if (ret) {
3054                 hns3_err(hw, "get sfp speed failed %d", ret);
3055                 return ret;
3056         }
3057
3058         *speed = resp->sfp_speed;
3059
3060         return 0;
3061 }
3062
3063 static uint8_t
3064 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3065 {
3066         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3067                 duplex = ETH_LINK_FULL_DUPLEX;
3068
3069         return duplex;
3070 }
3071
3072 static int
3073 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3074 {
3075         struct hns3_mac *mac = &hw->mac;
3076         int ret;
3077
3078         duplex = hns3_check_speed_dup(duplex, speed);
3079         if (mac->link_speed == speed && mac->link_duplex == duplex)
3080                 return 0;
3081
3082         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3083         if (ret)
3084                 return ret;
3085
3086         mac->link_speed = speed;
3087         mac->link_duplex = duplex;
3088
3089         return 0;
3090 }
3091
3092 static int
3093 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3094 {
3095         struct hns3_adapter *hns = eth_dev->data->dev_private;
3096         struct hns3_hw *hw = &hns->hw;
3097         struct hns3_pf *pf = &hns->pf;
3098         uint32_t speed;
3099         int ret;
3100
3101         /* If IMP do not support get SFP/qSFP speed, return directly */
3102         if (!pf->support_sfp_query)
3103                 return 0;
3104
3105         ret = hns3_get_sfp_speed(hw, &speed);
3106         if (ret == -EOPNOTSUPP) {
3107                 pf->support_sfp_query = false;
3108                 return ret;
3109         } else if (ret)
3110                 return ret;
3111
3112         if (speed == ETH_SPEED_NUM_NONE)
3113                 return 0; /* do nothing if no SFP */
3114
3115         /* Config full duplex for SFP */
3116         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3117 }
3118
3119 static int
3120 hns3_get_mac_link_status(struct hns3_hw *hw)
3121 {
3122         struct hns3_link_status_cmd *req;
3123         struct hns3_cmd_desc desc;
3124         int link_status;
3125         int ret;
3126
3127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3128         ret = hns3_cmd_send(hw, &desc, 1);
3129         if (ret) {
3130                 hns3_err(hw, "get link status cmd failed %d", ret);
3131                 return ret;
3132         }
3133
3134         req = (struct hns3_link_status_cmd *)desc.data;
3135         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3136
3137         return !!link_status;
3138 }
3139
3140 static void
3141 hns3_update_link_status(struct hns3_hw *hw)
3142 {
3143         int state;
3144
3145         state = hns3_get_mac_link_status(hw);
3146         if (state != hw->mac.link_status)
3147                 hw->mac.link_status = state;
3148 }
3149
3150 static void
3151 hns3_service_handler(void *param)
3152 {
3153         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3154         struct hns3_adapter *hns = eth_dev->data->dev_private;
3155         struct hns3_hw *hw = &hns->hw;
3156
3157         hns3_update_speed_duplex(eth_dev);
3158         hns3_update_link_status(hw);
3159
3160         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3161 }
3162
3163 static int
3164 hns3_init_hardware(struct hns3_adapter *hns)
3165 {
3166         struct hns3_hw *hw = &hns->hw;
3167         int ret;
3168
3169         ret = hns3_map_tqp(hw);
3170         if (ret) {
3171                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3172                 return ret;
3173         }
3174
3175         ret = hns3_init_umv_space(hw);
3176         if (ret) {
3177                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3178                 return ret;
3179         }
3180
3181         ret = hns3_mac_init(hw);
3182         if (ret) {
3183                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3184                 goto err_mac_init;
3185         }
3186
3187         ret = hns3_init_mgr_tbl(hw);
3188         if (ret) {
3189                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3190                 goto err_mac_init;
3191         }
3192
3193         ret = hns3_set_promisc_mode(hw, false, false);
3194         if (ret) {
3195                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3196                 goto err_mac_init;
3197         }
3198
3199         ret = hns3_init_vlan_config(hns);
3200         if (ret) {
3201                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3202                 goto err_mac_init;
3203         }
3204
3205         ret = hns3_dcb_init(hw);
3206         if (ret) {
3207                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3208                 goto err_mac_init;
3209         }
3210
3211         ret = hns3_init_fd_config(hns);
3212         if (ret) {
3213                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3214                 goto err_mac_init;
3215         }
3216
3217         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3218         if (ret) {
3219                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3220                 goto err_mac_init;
3221         }
3222
3223         ret = hns3_config_gro(hw, false);
3224         if (ret) {
3225                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3226                 goto err_mac_init;
3227         }
3228         return 0;
3229
3230 err_mac_init:
3231         hns3_uninit_umv_space(hw);
3232         return ret;
3233 }
3234
3235 static int
3236 hns3_init_pf(struct rte_eth_dev *eth_dev)
3237 {
3238         struct rte_device *dev = eth_dev->device;
3239         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3240         struct hns3_adapter *hns = eth_dev->data->dev_private;
3241         struct hns3_hw *hw = &hns->hw;
3242         int ret;
3243
3244         PMD_INIT_FUNC_TRACE();
3245
3246         /* Get hardware io base address from pcie BAR2 IO space */
3247         hw->io_base = pci_dev->mem_resource[2].addr;
3248
3249         /* Firmware command queue initialize */
3250         ret = hns3_cmd_init_queue(hw);
3251         if (ret) {
3252                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3253                 goto err_cmd_init_queue;
3254         }
3255
3256         /* Firmware command initialize */
3257         ret = hns3_cmd_init(hw);
3258         if (ret) {
3259                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3260                 goto err_cmd_init;
3261         }
3262
3263         /* Get configuration */
3264         ret = hns3_get_configuration(hw);
3265         if (ret) {
3266                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3267                 goto err_get_config;
3268         }
3269
3270         ret = hns3_init_hardware(hns);
3271         if (ret) {
3272                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3273                 goto err_get_config;
3274         }
3275
3276         /* Initialize flow director filter list & hash */
3277         ret = hns3_fdir_filter_init(hns);
3278         if (ret) {
3279                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3280                 goto err_hw_init;
3281         }
3282
3283         hns3_set_default_rss_args(hw);
3284
3285         return 0;
3286
3287 err_hw_init:
3288         hns3_uninit_umv_space(hw);
3289
3290 err_get_config:
3291         hns3_cmd_uninit(hw);
3292
3293 err_cmd_init:
3294         hns3_cmd_destroy_queue(hw);
3295
3296 err_cmd_init_queue:
3297         hw->io_base = NULL;
3298
3299         return ret;
3300 }
3301
3302 static void
3303 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
3304 {
3305         struct hns3_adapter *hns = eth_dev->data->dev_private;
3306         struct hns3_hw *hw = &hns->hw;
3307
3308         PMD_INIT_FUNC_TRACE();
3309
3310         hns3_rss_uninit(hns);
3311         hns3_fdir_filter_uninit(hns);
3312         hns3_uninit_umv_space(hw);
3313         hns3_cmd_uninit(hw);
3314         hns3_cmd_destroy_queue(hw);
3315         hw->io_base = NULL;
3316 }
3317
3318 static void
3319 hns3_dev_close(struct rte_eth_dev *eth_dev)
3320 {
3321         struct hns3_adapter *hns = eth_dev->data->dev_private;
3322         struct hns3_hw *hw = &hns->hw;
3323
3324         hw->adapter_state = HNS3_NIC_CLOSING;
3325         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
3326
3327         hns3_configure_all_mc_mac_addr(hns, true);
3328         hns3_uninit_pf(eth_dev);
3329         rte_free(eth_dev->process_private);
3330         eth_dev->process_private = NULL;
3331         hw->adapter_state = HNS3_NIC_CLOSED;
3332 }
3333
3334 static int
3335 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3336 {
3337         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3339
3340         fc_conf->pause_time = pf->pause_time;
3341
3342         /* return fc current mode */
3343         switch (hw->current_mode) {
3344         case HNS3_FC_FULL:
3345                 fc_conf->mode = RTE_FC_FULL;
3346                 break;
3347         case HNS3_FC_TX_PAUSE:
3348                 fc_conf->mode = RTE_FC_TX_PAUSE;
3349                 break;
3350         case HNS3_FC_RX_PAUSE:
3351                 fc_conf->mode = RTE_FC_RX_PAUSE;
3352                 break;
3353         case HNS3_FC_NONE:
3354         default:
3355                 fc_conf->mode = RTE_FC_NONE;
3356                 break;
3357         }
3358
3359         return 0;
3360 }
3361
3362 static void
3363 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
3364 {
3365         switch (mode) {
3366         case RTE_FC_NONE:
3367                 hw->requested_mode = HNS3_FC_NONE;
3368                 break;
3369         case RTE_FC_RX_PAUSE:
3370                 hw->requested_mode = HNS3_FC_RX_PAUSE;
3371                 break;
3372         case RTE_FC_TX_PAUSE:
3373                 hw->requested_mode = HNS3_FC_TX_PAUSE;
3374                 break;
3375         case RTE_FC_FULL:
3376                 hw->requested_mode = HNS3_FC_FULL;
3377                 break;
3378         default:
3379                 hw->requested_mode = HNS3_FC_NONE;
3380                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
3381                           "configured to RTE_FC_NONE", mode);
3382                 break;
3383         }
3384 }
3385
3386 static int
3387 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3388 {
3389         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3391         int ret;
3392
3393         if (fc_conf->high_water || fc_conf->low_water ||
3394             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
3395                 hns3_err(hw, "Unsupported flow control settings specified, "
3396                          "high_water(%u), low_water(%u), send_xon(%u) and "
3397                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
3398                          fc_conf->high_water, fc_conf->low_water,
3399                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
3400                 return -EINVAL;
3401         }
3402         if (fc_conf->autoneg) {
3403                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
3404                 return -EINVAL;
3405         }
3406         if (!fc_conf->pause_time) {
3407                 hns3_err(hw, "Invalid pause time %d setting.",
3408                          fc_conf->pause_time);
3409                 return -EINVAL;
3410         }
3411
3412         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
3413             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
3414                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
3415                          "current_fc_status = %d", hw->current_fc_status);
3416                 return -EOPNOTSUPP;
3417         }
3418
3419         hns3_get_fc_mode(hw, fc_conf->mode);
3420         if (hw->requested_mode == hw->current_mode &&
3421             pf->pause_time == fc_conf->pause_time)
3422                 return 0;
3423
3424         rte_spinlock_lock(&hw->lock);
3425         ret = hns3_fc_enable(dev, fc_conf);
3426         rte_spinlock_unlock(&hw->lock);
3427
3428         return ret;
3429 }
3430
3431 static int
3432 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3433                             struct rte_eth_pfc_conf *pfc_conf)
3434 {
3435         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437         uint8_t priority;
3438         int ret;
3439
3440         if (!hns3_dev_dcb_supported(hw)) {
3441                 hns3_err(hw, "This port does not support dcb configurations.");
3442                 return -EOPNOTSUPP;
3443         }
3444
3445         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
3446             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
3447                 hns3_err(hw, "Unsupported flow control settings specified, "
3448                          "high_water(%u), low_water(%u), send_xon(%u) and "
3449                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
3450                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
3451                          pfc_conf->fc.send_xon,
3452                          pfc_conf->fc.mac_ctrl_frame_fwd);
3453                 return -EINVAL;
3454         }
3455         if (pfc_conf->fc.autoneg) {
3456                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
3457                 return -EINVAL;
3458         }
3459         if (pfc_conf->fc.pause_time == 0) {
3460                 hns3_err(hw, "Invalid pause time %d setting.",
3461                          pfc_conf->fc.pause_time);
3462                 return -EINVAL;
3463         }
3464
3465         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
3466             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
3467                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
3468                              "current_fc_status = %d", hw->current_fc_status);
3469                 return -EOPNOTSUPP;
3470         }
3471
3472         priority = pfc_conf->priority;
3473         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
3474         if (hw->dcb_info.pfc_en & BIT(priority) &&
3475             hw->requested_mode == hw->current_mode &&
3476             pfc_conf->fc.pause_time == pf->pause_time)
3477                 return 0;
3478
3479         rte_spinlock_lock(&hw->lock);
3480         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
3481         rte_spinlock_unlock(&hw->lock);
3482
3483         return ret;
3484 }
3485
3486 static int
3487 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
3488 {
3489         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3491         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
3492         int i;
3493
3494         rte_spinlock_lock(&hw->lock);
3495         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
3496                 dcb_info->nb_tcs = pf->local_max_tc;
3497         else
3498                 dcb_info->nb_tcs = 1;
3499
3500         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
3501                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
3502         for (i = 0; i < dcb_info->nb_tcs; i++)
3503                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
3504
3505         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3506                 dcb_info->tc_queue.tc_rxq[0][i].base =
3507                                         hw->tc_queue[i].tqp_offset;
3508                 dcb_info->tc_queue.tc_txq[0][i].base =
3509                                         hw->tc_queue[i].tqp_offset;
3510                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
3511                                         hw->tc_queue[i].tqp_count;
3512                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
3513                                         hw->tc_queue[i].tqp_count;
3514         }
3515         rte_spinlock_unlock(&hw->lock);
3516
3517         return 0;
3518 }
3519
3520 static const struct eth_dev_ops hns3_eth_dev_ops = {
3521         .dev_close          = hns3_dev_close,
3522         .mtu_set            = hns3_dev_mtu_set,
3523         .dev_infos_get          = hns3_dev_infos_get,
3524         .fw_version_get         = hns3_fw_version_get,
3525         .flow_ctrl_get          = hns3_flow_ctrl_get,
3526         .flow_ctrl_set          = hns3_flow_ctrl_set,
3527         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
3528         .mac_addr_add           = hns3_add_mac_addr,
3529         .mac_addr_remove        = hns3_remove_mac_addr,
3530         .mac_addr_set           = hns3_set_default_mac_addr,
3531         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
3532         .link_update            = hns3_dev_link_update,
3533         .rss_hash_update        = hns3_dev_rss_hash_update,
3534         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
3535         .reta_update            = hns3_dev_rss_reta_update,
3536         .reta_query             = hns3_dev_rss_reta_query,
3537         .filter_ctrl            = hns3_dev_filter_ctrl,
3538         .vlan_filter_set        = hns3_vlan_filter_set,
3539         .vlan_tpid_set          = hns3_vlan_tpid_set,
3540         .vlan_offload_set       = hns3_vlan_offload_set,
3541         .vlan_pvid_set          = hns3_vlan_pvid_set,
3542         .get_dcb_info           = hns3_get_dcb_info,
3543 };
3544
3545 static int
3546 hns3_dev_init(struct rte_eth_dev *eth_dev)
3547 {
3548         struct rte_device *dev = eth_dev->device;
3549         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3550         struct hns3_adapter *hns = eth_dev->data->dev_private;
3551         struct hns3_hw *hw = &hns->hw;
3552         uint16_t device_id = pci_dev->id.device_id;
3553         int ret;
3554
3555         PMD_INIT_FUNC_TRACE();
3556         eth_dev->process_private = (struct hns3_process_private *)
3557             rte_zmalloc_socket("hns3_filter_list",
3558                                sizeof(struct hns3_process_private),
3559                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
3560         if (eth_dev->process_private == NULL) {
3561                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
3562                 return -ENOMEM;
3563         }
3564         /* initialize flow filter lists */
3565         hns3_filterlist_init(eth_dev);
3566
3567         eth_dev->dev_ops = &hns3_eth_dev_ops;
3568         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3569                 return 0;
3570
3571         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
3572
3573         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3574             device_id == HNS3_DEV_ID_50GE_RDMA ||
3575             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
3576                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
3577
3578         hns->is_vf = false;
3579         hw->data = eth_dev->data;
3580
3581         /*
3582          * Set default max packet size according to the mtu
3583          * default vale in DPDK frame.
3584          */
3585         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
3586
3587         ret = hns3_init_pf(eth_dev);
3588         if (ret) {
3589                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
3590                 goto err_init_pf;
3591         }
3592
3593         /* Allocate memory for storing MAC addresses */
3594         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
3595                                                sizeof(struct rte_ether_addr) *
3596                                                HNS3_UC_MACADDR_NUM, 0);
3597         if (eth_dev->data->mac_addrs == NULL) {
3598                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
3599                              "to store MAC addresses",
3600                              sizeof(struct rte_ether_addr) *
3601                              HNS3_UC_MACADDR_NUM);
3602                 ret = -ENOMEM;
3603                 goto err_rte_zmalloc;
3604         }
3605
3606         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3607                             &eth_dev->data->mac_addrs[0]);
3608
3609         hw->adapter_state = HNS3_NIC_INITIALIZED;
3610         /*
3611          * Pass the information to the rte_eth_dev_close() that it should also
3612          * release the private port resources.
3613          */
3614         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
3615
3616         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3617         hns3_info(hw, "hns3 dev initialization successful!");
3618         return 0;
3619
3620 err_rte_zmalloc:
3621         hns3_uninit_pf(eth_dev);
3622
3623 err_init_pf:
3624         eth_dev->dev_ops = NULL;
3625         eth_dev->rx_pkt_burst = NULL;
3626         eth_dev->tx_pkt_burst = NULL;
3627         eth_dev->tx_pkt_prepare = NULL;
3628         rte_free(eth_dev->process_private);
3629         eth_dev->process_private = NULL;
3630         return ret;
3631 }
3632
3633 static int
3634 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
3635 {
3636         struct hns3_adapter *hns = eth_dev->data->dev_private;
3637         struct hns3_hw *hw = &hns->hw;
3638
3639         PMD_INIT_FUNC_TRACE();
3640
3641         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3642                 return -EPERM;
3643
3644         eth_dev->dev_ops = NULL;
3645         eth_dev->rx_pkt_burst = NULL;
3646         eth_dev->tx_pkt_burst = NULL;
3647         eth_dev->tx_pkt_prepare = NULL;
3648         if (hw->adapter_state < HNS3_NIC_CLOSING)
3649                 hns3_dev_close(eth_dev);
3650
3651         hw->adapter_state = HNS3_NIC_REMOVED;
3652         return 0;
3653 }
3654
3655 static int
3656 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3657                    struct rte_pci_device *pci_dev)
3658 {
3659         return rte_eth_dev_pci_generic_probe(pci_dev,
3660                                              sizeof(struct hns3_adapter),
3661                                              hns3_dev_init);
3662 }
3663
3664 static int
3665 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
3666 {
3667         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
3668 }
3669
3670 static const struct rte_pci_id pci_id_hns3_map[] = {
3671         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
3672         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
3673         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
3674         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
3675         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
3676         { .vendor_id = 0, /* sentinel */ },
3677 };
3678
3679 static struct rte_pci_driver rte_hns3_pmd = {
3680         .id_table = pci_id_hns3_map,
3681         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
3682         .probe = eth_hns3_pci_probe,
3683         .remove = eth_hns3_pci_remove,
3684 };
3685
3686 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
3687 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
3688 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
3689
3690 RTE_INIT(hns3_init_log)
3691 {
3692         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
3693         if (hns3_logtype_init >= 0)
3694                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
3695         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
3696         if (hns3_logtype_driver >= 0)
3697                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
3698 }