drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVALID_PVID               0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  60 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  62
  63 #define HNS3_RESET_WAIT_MS      100
  64 #define HNS3_RESET_WAIT_CNT     200
  65
  66 /* FEC mode order defined in HNS3 hardware */
  67 #define HNS3_HW_FEC_MODE_NOFEC  0
  68 #define HNS3_HW_FEC_MODE_BASER  1
  69 #define HNS3_HW_FEC_MODE_RS     2
  70
  71 enum hns3_evt_cause {
  72         HNS3_VECTOR0_EVENT_RST,
  73         HNS3_VECTOR0_EVENT_MBX,
  74         HNS3_VECTOR0_EVENT_ERR,
  75         HNS3_VECTOR0_EVENT_OTHER,
  76 };
  77
  78 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  79         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  82
  83         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  84                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  85                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  86                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  91
  92         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  93                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  94                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  95                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  96
  97         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  98                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  99                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
 100
 101         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
 102                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
 103                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
 104 };
 105
 106 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
 107                                                  uint64_t *levels);
 108 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 109 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
 110                                     int on);
 111 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
 112
 113 static int hns3_add_mc_addr(struct hns3_hw *hw,
 114                             struct rte_ether_addr *mac_addr);
 115 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 116                             struct rte_ether_addr *mac_addr);
 117 static int hns3_restore_fec(struct hns3_hw *hw);
 118 static int hns3_query_dev_fec_info(struct rte_eth_dev *dev);
 119
 120 static void
 121 hns3_pf_disable_irq0(struct hns3_hw *hw)
 122 {
 123         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 124 }
 125
 126 static void
 127 hns3_pf_enable_irq0(struct hns3_hw *hw)
 128 {
 129         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 130 }
 131
 132 static enum hns3_evt_cause
 133 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 134 {
 135         struct hns3_hw *hw = &hns->hw;
 136         uint32_t vector0_int_stats;
 137         uint32_t cmdq_src_val;
 138         uint32_t hw_err_src_reg;
 139         uint32_t val;
 140         enum hns3_evt_cause ret;
 141
 142         /* fetch the events from their corresponding regs */
 143         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 144         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 145         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 146
 147         /*
 148          * Assumption: If by any chance reset and mailbox events are reported
 149          * together then we will only process reset event and defer the
 150          * processing of the mailbox events. Since, we would have not cleared
 151          * RX CMDQ event this time we would receive again another interrupt
 152          * from H/W just for the mailbox.
 153          */
 154         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 155                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 156                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 157                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 158                 if (clearval) {
 159                         hw->reset.stats.imp_cnt++;
 160                         hns3_warn(hw, "IMP reset detected, clear reset status");
 161                 } else {
 162                         hns3_schedule_delayed_reset(hns);
 163                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 164                 }
 165
 166                 ret = HNS3_VECTOR0_EVENT_RST;
 167                 goto out;
 168         }
 169
 170         /* Global reset */
 171         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 172                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 173                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 174                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 175                 if (clearval) {
 176                         hw->reset.stats.global_cnt++;
 177                         hns3_warn(hw, "Global reset detected, clear reset status");
 178                 } else {
 179                         hns3_schedule_delayed_reset(hns);
 180                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 181                 }
 182
 183                 ret = HNS3_VECTOR0_EVENT_RST;
 184                 goto out;
 185         }
 186
 187         /* check for vector0 msix event source */
 188         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 189             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 190                 val = vector0_int_stats | hw_err_src_reg;
 191                 ret = HNS3_VECTOR0_EVENT_ERR;
 192                 goto out;
 193         }
 194
 195         /* check for vector0 mailbox(=CMDQ RX) event source */
 196         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 197                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 198                 val = cmdq_src_val;
 199                 ret = HNS3_VECTOR0_EVENT_MBX;
 200                 goto out;
 201         }
 202
 203         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 204                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 205                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 206         val = vector0_int_stats;
 207         ret = HNS3_VECTOR0_EVENT_OTHER;
 208 out:
 209
 210         if (clearval)
 211                 *clearval = val;
 212         return ret;
 213 }
 214
 215 static void
 216 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 217 {
 218         if (event_type == HNS3_VECTOR0_EVENT_RST)
 219                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 220         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 221                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 222 }
 223
 224 static void
 225 hns3_clear_all_event_cause(struct hns3_hw *hw)
 226 {
 227         uint32_t vector0_int_stats;
 228         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 229
 230         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 231                 hns3_warn(hw, "Probe during IMP reset interrupt");
 232
 233         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 234                 hns3_warn(hw, "Probe during Global reset interrupt");
 235
 236         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 237                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 238                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 239                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 240         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 241 }
 242
 243 static void
 244 hns3_interrupt_handler(void *param)
 245 {
 246         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 247         struct hns3_adapter *hns = dev->data->dev_private;
 248         struct hns3_hw *hw = &hns->hw;
 249         enum hns3_evt_cause event_cause;
 250         uint32_t clearval = 0;
 251
 252         /* Disable interrupt */
 253         hns3_pf_disable_irq0(hw);
 254
 255         event_cause = hns3_check_event_cause(hns, &clearval);
 256
 257         /* vector 0 interrupt is shared with reset and mailbox source events. */
 258         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 259                 hns3_warn(hw, "Received err interrupt");
 260                 hns3_handle_msix_error(hns, &hw->reset.request);
 261                 hns3_handle_ras_error(hns, &hw->reset.request);
 262                 hns3_schedule_reset(hns);
 263         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 264                 hns3_warn(hw, "Received reset interrupt");
 265                 hns3_schedule_reset(hns);
 266         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 267                 hns3_dev_handle_mbx_msg(hw);
 268         else
 269                 hns3_err(hw, "Received unknown event");
 270
 271         hns3_clear_event_cause(hw, event_cause, clearval);
 272         /* Enable interrupt if it is not cause by reset */
 273         hns3_pf_enable_irq0(hw);
 274 }
 275
 276 static int
 277 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 278 {
 279 #define HNS3_VLAN_ID_OFFSET_STEP        160
 280 #define HNS3_VLAN_BYTE_SIZE             8
 281         struct hns3_vlan_filter_pf_cfg_cmd *req;
 282         struct hns3_hw *hw = &hns->hw;
 283         uint8_t vlan_offset_byte_val;
 284         struct hns3_cmd_desc desc;
 285         uint8_t vlan_offset_byte;
 286         uint8_t vlan_offset_base;
 287         int ret;
 288
 289         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 290
 291         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 292         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 293                            HNS3_VLAN_BYTE_SIZE;
 294         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 295
 296         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 297         req->vlan_offset = vlan_offset_base;
 298         req->vlan_cfg = on ? 0 : 1;
 299         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 300
 301         ret = hns3_cmd_send(hw, &desc, 1);
 302         if (ret)
 303                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 304                          vlan_id, ret);
 305
 306         return ret;
 307 }
 308
 309 static void
 310 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 311 {
 312         struct hns3_user_vlan_table *vlan_entry;
 313         struct hns3_pf *pf = &hns->pf;
 314
 315         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 316                 if (vlan_entry->vlan_id == vlan_id) {
 317                         if (vlan_entry->hd_tbl_status)
 318                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 319                         LIST_REMOVE(vlan_entry, next);
 320                         rte_free(vlan_entry);
 321                         break;
 322                 }
 323         }
 324 }
 325
 326 static void
 327 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 328                         bool writen_to_tbl)
 329 {
 330         struct hns3_user_vlan_table *vlan_entry;
 331         struct hns3_hw *hw = &hns->hw;
 332         struct hns3_pf *pf = &hns->pf;
 333
 334         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 335                 if (vlan_entry->vlan_id == vlan_id)
 336                         return;
 337         }
 338
 339         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 340         if (vlan_entry == NULL) {
 341                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 342                 return;
 343         }
 344
 345         vlan_entry->hd_tbl_status = writen_to_tbl;
 346         vlan_entry->vlan_id = vlan_id;
 347
 348         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 349 }
 350
 351 static int
 352 hns3_restore_vlan_table(struct hns3_adapter *hns)
 353 {
 354         struct hns3_user_vlan_table *vlan_entry;
 355         struct hns3_hw *hw = &hns->hw;
 356         struct hns3_pf *pf = &hns->pf;
 357         uint16_t vlan_id;
 358         int ret = 0;
 359
 360         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 361                 return hns3_vlan_pvid_configure(hns,
 362                                                 hw->port_base_vlan_cfg.pvid, 1);
 363
 364         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 365                 if (vlan_entry->hd_tbl_status) {
 366                         vlan_id = vlan_entry->vlan_id;
 367                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 368                         if (ret)
 369                                 break;
 370                 }
 371         }
 372
 373         return ret;
 374 }
 375
 376 static int
 377 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 378 {
 379         struct hns3_hw *hw = &hns->hw;
 380         bool writen_to_tbl = false;
 381         int ret = 0;
 382
 383         /*
 384          * When vlan filter is enabled, hardware regards packets without vlan
 385          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 386          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 387          */
 388         if (on == 0 && vlan_id == 0)
 389                 return 0;
 390
 391         /*
 392          * When port base vlan enabled, we use port base vlan as the vlan
 393          * filter condition. In this case, we don't update vlan filter table
 394          * when user add new vlan or remove exist vlan, just update the
 395          * vlan list. The vlan id in vlan list will be writen in vlan filter
 396          * table until port base vlan disabled
 397          */
 398         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 399                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 400                 writen_to_tbl = true;
 401         }
 402
 403         if (ret == 0) {
 404                 if (on)
 405                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 406                 else
 407                         hns3_rm_dev_vlan_table(hns, vlan_id);
 408         }
 409         return ret;
 410 }
 411
 412 static int
 413 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 414 {
 415         struct hns3_adapter *hns = dev->data->dev_private;
 416         struct hns3_hw *hw = &hns->hw;
 417         int ret;
 418
 419         rte_spinlock_lock(&hw->lock);
 420         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 421         rte_spinlock_unlock(&hw->lock);
 422         return ret;
 423 }
 424
 425 static int
 426 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 427                          uint16_t tpid)
 428 {
 429         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 430         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 431         struct hns3_hw *hw = &hns->hw;
 432         struct hns3_cmd_desc desc;
 433         int ret;
 434
 435         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 436              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 437                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 438                 return -EINVAL;
 439         }
 440
 441         if (tpid != RTE_ETHER_TYPE_VLAN) {
 442                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 443                 return -EINVAL;
 444         }
 445
 446         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 447         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 448
 449         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 450                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 451                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 452         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 453                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 454                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 455                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 456                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 457         }
 458
 459         ret = hns3_cmd_send(hw, &desc, 1);
 460         if (ret) {
 461                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 462                          ret);
 463                 return ret;
 464         }
 465
 466         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 467
 468         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 469         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 470         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 471
 472         ret = hns3_cmd_send(hw, &desc, 1);
 473         if (ret)
 474                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 475                          ret);
 476         return ret;
 477 }
 478
 479 static int
 480 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 481                    uint16_t tpid)
 482 {
 483         struct hns3_adapter *hns = dev->data->dev_private;
 484         struct hns3_hw *hw = &hns->hw;
 485         int ret;
 486
 487         rte_spinlock_lock(&hw->lock);
 488         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 489         rte_spinlock_unlock(&hw->lock);
 490         return ret;
 491 }
 492
 493 static int
 494 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 495                              struct hns3_rx_vtag_cfg *vcfg)
 496 {
 497         struct hns3_vport_vtag_rx_cfg_cmd *req;
 498         struct hns3_hw *hw = &hns->hw;
 499         struct hns3_cmd_desc desc;
 500         uint16_t vport_id;
 501         uint8_t bitmap;
 502         int ret;
 503
 504         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 505
 506         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 507         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 508                      vcfg->strip_tag1_en ? 1 : 0);
 509         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 510                      vcfg->strip_tag2_en ? 1 : 0);
 511         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 512                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 513         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 514                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 515
 516         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 517         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 518                      vcfg->strip_tag1_discard_en ? 1 : 0);
 519         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 520                      vcfg->strip_tag2_discard_en ? 1 : 0);
 521         /*
 522          * In current version VF is not supported when PF is driven by DPDK
 523          * driver, just need to configure parameters for PF vport.
 524          */
 525         vport_id = HNS3_PF_FUNC_ID;
 526         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 527         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 528         req->vf_bitmap[req->vf_offset] = bitmap;
 529
 530         ret = hns3_cmd_send(hw, &desc, 1);
 531         if (ret)
 532                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 533         return ret;
 534 }
 535
 536 static void
 537 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 538                            struct hns3_rx_vtag_cfg *vcfg)
 539 {
 540         struct hns3_pf *pf = &hns->pf;
 541         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 542 }
 543
 544 static void
 545 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 546                            struct hns3_tx_vtag_cfg *vcfg)
 547 {
 548         struct hns3_pf *pf = &hns->pf;
 549         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 550 }
 551
 552 static int
 553 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 554 {
 555         struct hns3_rx_vtag_cfg rxvlan_cfg;
 556         struct hns3_hw *hw = &hns->hw;
 557         int ret;
 558
 559         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 560                 rxvlan_cfg.strip_tag1_en = false;
 561                 rxvlan_cfg.strip_tag2_en = enable;
 562                 rxvlan_cfg.strip_tag2_discard_en = false;
 563         } else {
 564                 rxvlan_cfg.strip_tag1_en = enable;
 565                 rxvlan_cfg.strip_tag2_en = true;
 566                 rxvlan_cfg.strip_tag2_discard_en = true;
 567         }
 568
 569         rxvlan_cfg.strip_tag1_discard_en = false;
 570         rxvlan_cfg.vlan1_vlan_prionly = false;
 571         rxvlan_cfg.vlan2_vlan_prionly = false;
 572         rxvlan_cfg.rx_vlan_offload_en = enable;
 573
 574         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 575         if (ret) {
 576                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 577                 return ret;
 578         }
 579
 580         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 587                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 588 {
 589         struct hns3_vlan_filter_ctrl_cmd *req;
 590         struct hns3_cmd_desc desc;
 591         int ret;
 592
 593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 594
 595         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 596         req->vlan_type = vlan_type;
 597         req->vlan_fe = filter_en ? fe_type : 0;
 598         req->vf_id = vf_id;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_vlan_filter_init(struct hns3_adapter *hns)
 609 {
 610         struct hns3_hw *hw = &hns->hw;
 611         int ret;
 612
 613         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 614                                         HNS3_FILTER_FE_EGRESS, false,
 615                                         HNS3_PF_FUNC_ID);
 616         if (ret) {
 617                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 618                 return ret;
 619         }
 620
 621         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 622                                         HNS3_FILTER_FE_INGRESS, false,
 623                                         HNS3_PF_FUNC_ID);
 624         if (ret)
 625                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 626
 627         return ret;
 628 }
 629
 630 static int
 631 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 632 {
 633         struct hns3_hw *hw = &hns->hw;
 634         int ret;
 635
 636         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 637                                         HNS3_FILTER_FE_INGRESS, enable,
 638                                         HNS3_PF_FUNC_ID);
 639         if (ret)
 640                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 641                          enable ? "enable" : "disable", ret);
 642
 643         return ret;
 644 }
 645
 646 static int
 647 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 648 {
 649         struct hns3_adapter *hns = dev->data->dev_private;
 650         struct hns3_hw *hw = &hns->hw;
 651         struct rte_eth_rxmode *rxmode;
 652         unsigned int tmp_mask;
 653         bool enable;
 654         int ret = 0;
 655
 656         rte_spinlock_lock(&hw->lock);
 657         rxmode = &dev->data->dev_conf.rxmode;
 658         tmp_mask = (unsigned int)mask;
 659         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 660                 /* ignore vlan filter configuration during promiscuous mode */
 661                 if (!dev->data->promiscuous) {
 662                         /* Enable or disable VLAN filter */
 663                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 664                                  true : false;
 665
 666                         ret = hns3_enable_vlan_filter(hns, enable);
 667                         if (ret) {
 668                                 rte_spinlock_unlock(&hw->lock);
 669                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 670                                          enable ? "enable" : "disable", ret);
 671                                 return ret;
 672                         }
 673                 }
 674         }
 675
 676         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 677                 /* Enable or disable VLAN stripping */
 678                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 679                     true : false;
 680
 681                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 682                 if (ret) {
 683                         rte_spinlock_unlock(&hw->lock);
 684                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 685                                  enable ? "enable" : "disable", ret);
 686                         return ret;
 687                 }
 688         }
 689
 690         rte_spinlock_unlock(&hw->lock);
 691
 692         return ret;
 693 }
 694
 695 static int
 696 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 697                              struct hns3_tx_vtag_cfg *vcfg)
 698 {
 699         struct hns3_vport_vtag_tx_cfg_cmd *req;
 700         struct hns3_cmd_desc desc;
 701         struct hns3_hw *hw = &hns->hw;
 702         uint16_t vport_id;
 703         uint8_t bitmap;
 704         int ret;
 705
 706         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 707
 708         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 709         req->def_vlan_tag1 = vcfg->default_tag1;
 710         req->def_vlan_tag2 = vcfg->default_tag2;
 711         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 712                      vcfg->accept_tag1 ? 1 : 0);
 713         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 714                      vcfg->accept_untag1 ? 1 : 0);
 715         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 716                      vcfg->accept_tag2 ? 1 : 0);
 717         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 718                      vcfg->accept_untag2 ? 1 : 0);
 719         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 720                      vcfg->insert_tag1_en ? 1 : 0);
 721         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 722                      vcfg->insert_tag2_en ? 1 : 0);
 723         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 724
 725         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 727                      vcfg->tag_shift_mode_en ? 1 : 0);
 728
 729         /*
 730          * In current version VF is not supported when PF is driven by DPDK
 731          * driver, just need to configure parameters for PF vport.
 732          */
 733         vport_id = HNS3_PF_FUNC_ID;
 734         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 735         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 736         req->vf_bitmap[req->vf_offset] = bitmap;
 737
 738         ret = hns3_cmd_send(hw, &desc, 1);
 739         if (ret)
 740                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 741
 742         return ret;
 743 }
 744
 745 static int
 746 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 747                      uint16_t pvid)
 748 {
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_tx_vtag_cfg txvlan_cfg;
 751         int ret;
 752
 753         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 754                 txvlan_cfg.accept_tag1 = true;
 755                 txvlan_cfg.insert_tag1_en = false;
 756                 txvlan_cfg.default_tag1 = 0;
 757         } else {
 758                 txvlan_cfg.accept_tag1 =
 759                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 760                 txvlan_cfg.insert_tag1_en = true;
 761                 txvlan_cfg.default_tag1 = pvid;
 762         }
 763
 764         txvlan_cfg.accept_untag1 = true;
 765         txvlan_cfg.accept_tag2 = true;
 766         txvlan_cfg.accept_untag2 = true;
 767         txvlan_cfg.insert_tag2_en = false;
 768         txvlan_cfg.default_tag2 = 0;
 769         txvlan_cfg.tag_shift_mode_en = true;
 770
 771         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 772         if (ret) {
 773                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 774                          ret);
 775                 return ret;
 776         }
 777
 778         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 779         return ret;
 780 }
 781
 782
 783 static void
 784 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 785 {
 786         struct hns3_user_vlan_table *vlan_entry;
 787         struct hns3_pf *pf = &hns->pf;
 788
 789         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 790                 if (vlan_entry->hd_tbl_status) {
 791                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 792                         vlan_entry->hd_tbl_status = false;
 793                 }
 794         }
 795
 796         if (is_del_list) {
 797                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 798                 while (vlan_entry) {
 799                         LIST_REMOVE(vlan_entry, next);
 800                         rte_free(vlan_entry);
 801                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 802                 }
 803         }
 804 }
 805
 806 static void
 807 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 808 {
 809         struct hns3_user_vlan_table *vlan_entry;
 810         struct hns3_pf *pf = &hns->pf;
 811
 812         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 813                 if (!vlan_entry->hd_tbl_status) {
 814                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 815                         vlan_entry->hd_tbl_status = true;
 816                 }
 817         }
 818 }
 819
 820 static void
 821 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 822 {
 823         struct hns3_hw *hw = &hns->hw;
 824         int ret;
 825
 826         hns3_rm_all_vlan_table(hns, true);
 827         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 828                 ret = hns3_set_port_vlan_filter(hns,
 829                                                 hw->port_base_vlan_cfg.pvid, 0);
 830                 if (ret) {
 831                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 832                                  ret);
 833                         return;
 834                 }
 835         }
 836 }
 837
 838 static int
 839 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 840                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 841 {
 842         struct hns3_hw *hw = &hns->hw;
 843         uint16_t old_pvid;
 844         int ret;
 845
 846         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 847                 old_pvid = hw->port_base_vlan_cfg.pvid;
 848                 if (old_pvid != HNS3_INVALID_PVID) {
 849                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 850                         if (ret) {
 851                                 hns3_err(hw, "failed to remove old pvid %u, "
 852                                                 "ret = %d", old_pvid, ret);
 853                                 return ret;
 854                         }
 855                 }
 856
 857                 hns3_rm_all_vlan_table(hns, false);
 858                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 859                 if (ret) {
 860                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 861                                         new_pvid, ret);
 862                         return ret;
 863                 }
 864         } else {
 865                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 866                 if (ret) {
 867                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 868                                         new_pvid, ret);
 869                         return ret;
 870                 }
 871
 872                 hns3_add_all_vlan_table(hns);
 873         }
 874         return 0;
 875 }
 876
 877 static int
 878 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 879 {
 880         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 881         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 882         bool rx_strip_en;
 883         int ret;
 884
 885         rx_strip_en = old_cfg->rx_vlan_offload_en;
 886         if (on) {
 887                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 888                 rx_vlan_cfg.strip_tag2_en = true;
 889                 rx_vlan_cfg.strip_tag2_discard_en = true;
 890         } else {
 891                 rx_vlan_cfg.strip_tag1_en = false;
 892                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 893                 rx_vlan_cfg.strip_tag2_discard_en = false;
 894         }
 895         rx_vlan_cfg.strip_tag1_discard_en = false;
 896         rx_vlan_cfg.vlan1_vlan_prionly = false;
 897         rx_vlan_cfg.vlan2_vlan_prionly = false;
 898         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 899
 900         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 901         if (ret)
 902                 return ret;
 903
 904         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 905         return ret;
 906 }
 907
 908 static int
 909 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         uint16_t port_base_vlan_state;
 913         int ret;
 914
 915         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 916                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 917                         hns3_warn(hw, "Invalid operation! As current pvid set "
 918                                   "is %u, disable pvid %u is invalid",
 919                                   hw->port_base_vlan_cfg.pvid, pvid);
 920                 return 0;
 921         }
 922
 923         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 924                                     HNS3_PORT_BASE_VLAN_DISABLE;
 925         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 926         if (ret) {
 927                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 928                          ret);
 929                 return ret;
 930         }
 931
 932         ret = hns3_en_pvid_strip(hns, on);
 933         if (ret) {
 934                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 935                          "ret = %d", ret);
 936                 return ret;
 937         }
 938
 939         if (pvid == HNS3_INVALID_PVID)
 940                 goto out;
 941         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 942         if (ret) {
 943                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 944                          ret);
 945                 return ret;
 946         }
 947
 948 out:
 949         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 950         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 951         return ret;
 952 }
 953
 954 static int
 955 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 956 {
 957         struct hns3_adapter *hns = dev->data->dev_private;
 958         struct hns3_hw *hw = &hns->hw;
 959         bool pvid_en_state_change;
 960         uint16_t pvid_state;
 961         int ret;
 962
 963         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 964                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 965                          RTE_ETHER_MAX_VLAN_ID);
 966                 return -EINVAL;
 967         }
 968
 969         /*
 970          * If PVID configuration state change, should refresh the PVID
 971          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 972          */
 973         pvid_state = hw->port_base_vlan_cfg.state;
 974         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 975             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 976                 pvid_en_state_change = false;
 977         else
 978                 pvid_en_state_change = true;
 979
 980         rte_spinlock_lock(&hw->lock);
 981         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 982         rte_spinlock_unlock(&hw->lock);
 983         if (ret)
 984                 return ret;
 985         /*
 986          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 987          * need be processed by PMD driver.
 988          */
 989         if (pvid_en_state_change &&
 990             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 991                 hns3_update_all_queues_pvid_proc_en(hw);
 992
 993         return 0;
 994 }
 995
 996 static int
 997 hns3_default_vlan_config(struct hns3_adapter *hns)
 998 {
 999         struct hns3_hw *hw = &hns->hw;
1000         int ret;
1001
1002         /*
1003          * When vlan filter is enabled, hardware regards packets without vlan
1004          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1005          * table, packets without vlan won't be received. So, add vlan 0 as
1006          * the default vlan.
1007          */
1008         ret = hns3_vlan_filter_configure(hns, 0, 1);
1009         if (ret)
1010                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1011         return ret;
1012 }
1013
1014 static int
1015 hns3_init_vlan_config(struct hns3_adapter *hns)
1016 {
1017         struct hns3_hw *hw = &hns->hw;
1018         int ret;
1019
1020         /*
1021          * This function can be called in the initialization and reset process,
1022          * when in reset process, it means that hardware had been reseted
1023          * successfully and we need to restore the hardware configuration to
1024          * ensure that the hardware configuration remains unchanged before and
1025          * after reset.
1026          */
1027         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1028                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1029                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1030         }
1031
1032         ret = hns3_vlan_filter_init(hns);
1033         if (ret) {
1034                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1035                 return ret;
1036         }
1037
1038         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1039                                        RTE_ETHER_TYPE_VLAN);
1040         if (ret) {
1041                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1042                 return ret;
1043         }
1044
1045         /*
1046          * When in the reinit dev stage of the reset process, the following
1047          * vlan-related configurations may differ from those at initialization,
1048          * we will restore configurations to hardware in hns3_restore_vlan_table
1049          * and hns3_restore_vlan_conf later.
1050          */
1051         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1052                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1053                 if (ret) {
1054                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1055                         return ret;
1056                 }
1057
1058                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1059                 if (ret) {
1060                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1061                                  ret);
1062                         return ret;
1063                 }
1064         }
1065
1066         return hns3_default_vlan_config(hns);
1067 }
1068
1069 static int
1070 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1071 {
1072         struct hns3_pf *pf = &hns->pf;
1073         struct hns3_hw *hw = &hns->hw;
1074         uint64_t offloads;
1075         bool enable;
1076         int ret;
1077
1078         if (!hw->data->promiscuous) {
1079                 /* restore vlan filter states */
1080                 offloads = hw->data->dev_conf.rxmode.offloads;
1081                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1082                 ret = hns3_enable_vlan_filter(hns, enable);
1083                 if (ret) {
1084                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1085                                  "ret = %d", ret);
1086                         return ret;
1087                 }
1088         }
1089
1090         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1091         if (ret) {
1092                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1093                 return ret;
1094         }
1095
1096         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1097         if (ret)
1098                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1099
1100         return ret;
1101 }
1102
1103 static int
1104 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1105 {
1106         struct hns3_adapter *hns = dev->data->dev_private;
1107         struct rte_eth_dev_data *data = dev->data;
1108         struct rte_eth_txmode *txmode;
1109         struct hns3_hw *hw = &hns->hw;
1110         int mask;
1111         int ret;
1112
1113         txmode = &data->dev_conf.txmode;
1114         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1115                 hns3_warn(hw,
1116                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1117                           "configuration is not supported! Ignore these two "
1118                           "parameters: hw_vlan_reject_tagged(%d), "
1119                           "hw_vlan_reject_untagged(%d)",
1120                           txmode->hw_vlan_reject_tagged,
1121                           txmode->hw_vlan_reject_untagged);
1122
1123         /* Apply vlan offload setting */
1124         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1125         ret = hns3_vlan_offload_set(dev, mask);
1126         if (ret) {
1127                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1128                          ret);
1129                 return ret;
1130         }
1131
1132         /*
1133          * If pvid config is not set in rte_eth_conf, driver needn't to set
1134          * VLAN pvid related configuration to hardware.
1135          */
1136         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1137                 return 0;
1138
1139         /* Apply pvid setting */
1140         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1141                                  txmode->hw_vlan_insert_pvid);
1142         if (ret)
1143                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1144                          txmode->pvid, ret);
1145
1146         return ret;
1147 }
1148
1149 static int
1150 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1151                 unsigned int tso_mss_max)
1152 {
1153         struct hns3_cfg_tso_status_cmd *req;
1154         struct hns3_cmd_desc desc;
1155         uint16_t tso_mss;
1156
1157         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1158
1159         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1160
1161         tso_mss = 0;
1162         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1163                        tso_mss_min);
1164         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1165
1166         tso_mss = 0;
1167         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1168                        tso_mss_max);
1169         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1170
1171         return hns3_cmd_send(hw, &desc, 1);
1172 }
1173
1174 static int
1175 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1176                    uint16_t *allocated_size, bool is_alloc)
1177 {
1178         struct hns3_umv_spc_alc_cmd *req;
1179         struct hns3_cmd_desc desc;
1180         int ret;
1181
1182         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1183         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1184         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1185         req->space_size = rte_cpu_to_le_32(space_size);
1186
1187         ret = hns3_cmd_send(hw, &desc, 1);
1188         if (ret) {
1189                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1190                              is_alloc ? "allocate" : "free", ret);
1191                 return ret;
1192         }
1193
1194         if (is_alloc && allocated_size)
1195                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1196
1197         return 0;
1198 }
1199
1200 static int
1201 hns3_init_umv_space(struct hns3_hw *hw)
1202 {
1203         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1204         struct hns3_pf *pf = &hns->pf;
1205         uint16_t allocated_size = 0;
1206         int ret;
1207
1208         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1209                                  true);
1210         if (ret)
1211                 return ret;
1212
1213         if (allocated_size < pf->wanted_umv_size)
1214                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1215                              pf->wanted_umv_size, allocated_size);
1216
1217         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1218                                                 pf->wanted_umv_size;
1219         pf->used_umv_size = 0;
1220         return 0;
1221 }
1222
1223 static int
1224 hns3_uninit_umv_space(struct hns3_hw *hw)
1225 {
1226         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1227         struct hns3_pf *pf = &hns->pf;
1228         int ret;
1229
1230         if (pf->max_umv_size == 0)
1231                 return 0;
1232
1233         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1234         if (ret)
1235                 return ret;
1236
1237         pf->max_umv_size = 0;
1238
1239         return 0;
1240 }
1241
1242 static bool
1243 hns3_is_umv_space_full(struct hns3_hw *hw)
1244 {
1245         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1246         struct hns3_pf *pf = &hns->pf;
1247         bool is_full;
1248
1249         is_full = (pf->used_umv_size >= pf->max_umv_size);
1250
1251         return is_full;
1252 }
1253
1254 static void
1255 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1256 {
1257         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1258         struct hns3_pf *pf = &hns->pf;
1259
1260         if (is_free) {
1261                 if (pf->used_umv_size > 0)
1262                         pf->used_umv_size--;
1263         } else
1264                 pf->used_umv_size++;
1265 }
1266
1267 static void
1268 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1269                       const uint8_t *addr, bool is_mc)
1270 {
1271         const unsigned char *mac_addr = addr;
1272         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1273                             ((uint32_t)mac_addr[2] << 16) |
1274                             ((uint32_t)mac_addr[1] << 8) |
1275                             (uint32_t)mac_addr[0];
1276         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1277
1278         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1279         if (is_mc) {
1280                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1281                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1282                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1283         }
1284
1285         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1286         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1287 }
1288
1289 static int
1290 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1291                              uint8_t resp_code,
1292                              enum hns3_mac_vlan_tbl_opcode op)
1293 {
1294         if (cmdq_resp) {
1295                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1296                          cmdq_resp);
1297                 return -EIO;
1298         }
1299
1300         if (op == HNS3_MAC_VLAN_ADD) {
1301                 if (resp_code == 0 || resp_code == 1) {
1302                         return 0;
1303                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1304                         hns3_err(hw, "add mac addr failed for uc_overflow");
1305                         return -ENOSPC;
1306                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1307                         hns3_err(hw, "add mac addr failed for mc_overflow");
1308                         return -ENOSPC;
1309                 }
1310
1311                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1312                          resp_code);
1313                 return -EIO;
1314         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1315                 if (resp_code == 0) {
1316                         return 0;
1317                 } else if (resp_code == 1) {
1318                         hns3_dbg(hw, "remove mac addr failed for miss");
1319                         return -ENOENT;
1320                 }
1321
1322                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1323                          resp_code);
1324                 return -EIO;
1325         } else if (op == HNS3_MAC_VLAN_LKUP) {
1326                 if (resp_code == 0) {
1327                         return 0;
1328                 } else if (resp_code == 1) {
1329                         hns3_dbg(hw, "lookup mac addr failed for miss");
1330                         return -ENOENT;
1331                 }
1332
1333                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1334                          resp_code);
1335                 return -EIO;
1336         }
1337
1338         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1339                  op);
1340
1341         return -EINVAL;
1342 }
1343
1344 static int
1345 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1346                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1347                          struct hns3_cmd_desc *desc, bool is_mc)
1348 {
1349         uint8_t resp_code;
1350         uint16_t retval;
1351         int ret;
1352
1353         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1354         if (is_mc) {
1355                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1356                 memcpy(desc[0].data, req,
1357                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1358                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1359                                           true);
1360                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1361                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1362                                           true);
1363                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1364         } else {
1365                 memcpy(desc[0].data, req,
1366                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1367                 ret = hns3_cmd_send(hw, desc, 1);
1368         }
1369         if (ret) {
1370                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1371                          ret);
1372                 return ret;
1373         }
1374         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1375         retval = rte_le_to_cpu_16(desc[0].retval);
1376
1377         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1378                                             HNS3_MAC_VLAN_LKUP);
1379 }
1380
1381 static int
1382 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1383                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1384                       struct hns3_cmd_desc *mc_desc)
1385 {
1386         uint8_t resp_code;
1387         uint16_t retval;
1388         int cfg_status;
1389         int ret;
1390
1391         if (mc_desc == NULL) {
1392                 struct hns3_cmd_desc desc;
1393
1394                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1395                 memcpy(desc.data, req,
1396                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1397                 ret = hns3_cmd_send(hw, &desc, 1);
1398                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1399                 retval = rte_le_to_cpu_16(desc.retval);
1400
1401                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1402                                                           HNS3_MAC_VLAN_ADD);
1403         } else {
1404                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1405                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1406                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1407                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1408                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1409                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1410                 memcpy(mc_desc[0].data, req,
1411                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 mc_desc[0].retval = 0;
1413                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1414                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1415                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1416
1417                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1418                                                           HNS3_MAC_VLAN_ADD);
1419         }
1420
1421         if (ret) {
1422                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1423                 return ret;
1424         }
1425
1426         return cfg_status;
1427 }
1428
1429 static int
1430 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1431                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1432 {
1433         struct hns3_cmd_desc desc;
1434         uint8_t resp_code;
1435         uint16_t retval;
1436         int ret;
1437
1438         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1439
1440         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1441
1442         ret = hns3_cmd_send(hw, &desc, 1);
1443         if (ret) {
1444                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1445                 return ret;
1446         }
1447         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1448         retval = rte_le_to_cpu_16(desc.retval);
1449
1450         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1451                                             HNS3_MAC_VLAN_REMOVE);
1452 }
1453
1454 static int
1455 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1456 {
1457         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1458         struct hns3_mac_vlan_tbl_entry_cmd req;
1459         struct hns3_pf *pf = &hns->pf;
1460         struct hns3_cmd_desc desc[3];
1461         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1462         uint16_t egress_port = 0;
1463         uint8_t vf_id;
1464         int ret;
1465
1466         /* check if mac addr is valid */
1467         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1468                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1469                                       mac_addr);
1470                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1471                          mac_str);
1472                 return -EINVAL;
1473         }
1474
1475         memset(&req, 0, sizeof(req));
1476
1477         /*
1478          * In current version VF is not supported when PF is driven by DPDK
1479          * driver, just need to configure parameters for PF vport.
1480          */
1481         vf_id = HNS3_PF_FUNC_ID;
1482         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1483                        HNS3_MAC_EPORT_VFID_S, vf_id);
1484
1485         req.egress_port = rte_cpu_to_le_16(egress_port);
1486
1487         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1488
1489         /*
1490          * Lookup the mac address in the mac_vlan table, and add
1491          * it if the entry is inexistent. Repeated unicast entry
1492          * is not allowed in the mac vlan table.
1493          */
1494         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1495         if (ret == -ENOENT) {
1496                 if (!hns3_is_umv_space_full(hw)) {
1497                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1498                         if (!ret)
1499                                 hns3_update_umv_space(hw, false);
1500                         return ret;
1501                 }
1502
1503                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1504
1505                 return -ENOSPC;
1506         }
1507
1508         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1509
1510         /* check if we just hit the duplicate */
1511         if (ret == 0) {
1512                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1513                 return 0;
1514         }
1515
1516         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1517                  mac_str);
1518
1519         return ret;
1520 }
1521
1522 static int
1523 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1524 {
1525         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1526         struct rte_ether_addr *addr;
1527         int ret;
1528         int i;
1529
1530         for (i = 0; i < hw->mc_addrs_num; i++) {
1531                 addr = &hw->mc_addrs[i];
1532                 /* Check if there are duplicate addresses */
1533                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1534                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1535                                               addr);
1536                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1537                                  "(%s) is added by the set_mc_mac_addr_list "
1538                                  "API", mac_str);
1539                         return -EINVAL;
1540                 }
1541         }
1542
1543         ret = hns3_add_mc_addr(hw, mac_addr);
1544         if (ret) {
1545                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                       mac_addr);
1547                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1548                          mac_str, ret);
1549         }
1550         return ret;
1551 }
1552
1553 static int
1554 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1555 {
1556         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1557         int ret;
1558
1559         ret = hns3_remove_mc_addr(hw, mac_addr);
1560         if (ret) {
1561                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562                                       mac_addr);
1563                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1564                          mac_str, ret);
1565         }
1566         return ret;
1567 }
1568
1569 static int
1570 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1571                   uint32_t idx, __rte_unused uint32_t pool)
1572 {
1573         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1575         int ret;
1576
1577         rte_spinlock_lock(&hw->lock);
1578
1579         /*
1580          * In hns3 network engine adding UC and MC mac address with different
1581          * commands with firmware. We need to determine whether the input
1582          * address is a UC or a MC address to call different commands.
1583          * By the way, it is recommended calling the API function named
1584          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1585          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1586          * may affect the specifications of UC mac addresses.
1587          */
1588         if (rte_is_multicast_ether_addr(mac_addr))
1589                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1590         else
1591                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1592
1593         if (ret) {
1594                 rte_spinlock_unlock(&hw->lock);
1595                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1596                                       mac_addr);
1597                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1598                          ret);
1599                 return ret;
1600         }
1601
1602         if (idx == 0)
1603                 hw->mac.default_addr_setted = true;
1604         rte_spinlock_unlock(&hw->lock);
1605
1606         return ret;
1607 }
1608
1609 static int
1610 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1611 {
1612         struct hns3_mac_vlan_tbl_entry_cmd req;
1613         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1614         int ret;
1615
1616         /* check if mac addr is valid */
1617         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1618                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1619                                       mac_addr);
1620                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1621                          mac_str);
1622                 return -EINVAL;
1623         }
1624
1625         memset(&req, 0, sizeof(req));
1626         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1627         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1628         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1629         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1630                 return 0;
1631         else if (ret == 0)
1632                 hns3_update_umv_space(hw, true);
1633
1634         return ret;
1635 }
1636
1637 static void
1638 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1639 {
1640         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641         /* index will be checked by upper level rte interface */
1642         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1643         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1644         int ret;
1645
1646         rte_spinlock_lock(&hw->lock);
1647
1648         if (rte_is_multicast_ether_addr(mac_addr))
1649                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1650         else
1651                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1652         rte_spinlock_unlock(&hw->lock);
1653         if (ret) {
1654                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1655                                       mac_addr);
1656                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1657                          ret);
1658         }
1659 }
1660
1661 static int
1662 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1663                           struct rte_ether_addr *mac_addr)
1664 {
1665         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666         struct rte_ether_addr *oaddr;
1667         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1668         bool default_addr_setted;
1669         bool rm_succes = false;
1670         int ret, ret_val;
1671
1672         /*
1673          * It has been guaranteed that input parameter named mac_addr is valid
1674          * address in the rte layer of DPDK framework.
1675          */
1676         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1677         default_addr_setted = hw->mac.default_addr_setted;
1678         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1679                 return 0;
1680
1681         rte_spinlock_lock(&hw->lock);
1682         if (default_addr_setted) {
1683                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1684                 if (ret) {
1685                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1686                                               oaddr);
1687                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1688                                   mac_str, ret);
1689                         rm_succes = false;
1690                 } else
1691                         rm_succes = true;
1692         }
1693
1694         ret = hns3_add_uc_addr_common(hw, mac_addr);
1695         if (ret) {
1696                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1697                                       mac_addr);
1698                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1699                 goto err_add_uc_addr;
1700         }
1701
1702         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1703         if (ret) {
1704                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1705                 goto err_pause_addr_cfg;
1706         }
1707
1708         rte_ether_addr_copy(mac_addr,
1709                             (struct rte_ether_addr *)hw->mac.mac_addr);
1710         hw->mac.default_addr_setted = true;
1711         rte_spinlock_unlock(&hw->lock);
1712
1713         return 0;
1714
1715 err_pause_addr_cfg:
1716         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1717         if (ret_val) {
1718                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1719                                       mac_addr);
1720                 hns3_warn(hw,
1721                           "Failed to roll back to del setted mac addr(%s): %d",
1722                           mac_str, ret_val);
1723         }
1724
1725 err_add_uc_addr:
1726         if (rm_succes) {
1727                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1728                 if (ret_val) {
1729                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1730                                               oaddr);
1731                         hns3_warn(hw,
1732                                   "Failed to restore old uc mac addr(%s): %d",
1733                                   mac_str, ret_val);
1734                         hw->mac.default_addr_setted = false;
1735                 }
1736         }
1737         rte_spinlock_unlock(&hw->lock);
1738
1739         return ret;
1740 }
1741
1742 static int
1743 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1744 {
1745         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1746         struct hns3_hw *hw = &hns->hw;
1747         struct rte_ether_addr *addr;
1748         int err = 0;
1749         int ret;
1750         int i;
1751
1752         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1753                 addr = &hw->data->mac_addrs[i];
1754                 if (rte_is_zero_ether_addr(addr))
1755                         continue;
1756                 if (rte_is_multicast_ether_addr(addr))
1757                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1758                               hns3_add_mc_addr(hw, addr);
1759                 else
1760                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1761                               hns3_add_uc_addr_common(hw, addr);
1762
1763                 if (ret) {
1764                         err = ret;
1765                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1766                                               addr);
1767                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1768                                  "ret = %d.", del ? "remove" : "restore",
1769                                  mac_str, i, ret);
1770                 }
1771         }
1772         return err;
1773 }
1774
1775 static void
1776 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1777 {
1778 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1779         uint8_t word_num;
1780         uint8_t bit_num;
1781
1782         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1783                 word_num = vfid / 32;
1784                 bit_num = vfid % 32;
1785                 if (clr)
1786                         desc[1].data[word_num] &=
1787                             rte_cpu_to_le_32(~(1UL << bit_num));
1788                 else
1789                         desc[1].data[word_num] |=
1790                             rte_cpu_to_le_32(1UL << bit_num);
1791         } else {
1792                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1793                 bit_num = vfid % 32;
1794                 if (clr)
1795                         desc[2].data[word_num] &=
1796                             rte_cpu_to_le_32(~(1UL << bit_num));
1797                 else
1798                         desc[2].data[word_num] |=
1799                             rte_cpu_to_le_32(1UL << bit_num);
1800         }
1801 }
1802
1803 static int
1804 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1805 {
1806         struct hns3_mac_vlan_tbl_entry_cmd req;
1807         struct hns3_cmd_desc desc[3];
1808         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1809         uint8_t vf_id;
1810         int ret;
1811
1812         /* Check if mac addr is valid */
1813         if (!rte_is_multicast_ether_addr(mac_addr)) {
1814                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                       mac_addr);
1816                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1817                          mac_str);
1818                 return -EINVAL;
1819         }
1820
1821         memset(&req, 0, sizeof(req));
1822         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1823         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1824         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1825         if (ret) {
1826                 /* This mac addr do not exist, add new entry for it */
1827                 memset(desc[0].data, 0, sizeof(desc[0].data));
1828                 memset(desc[1].data, 0, sizeof(desc[0].data));
1829                 memset(desc[2].data, 0, sizeof(desc[0].data));
1830         }
1831
1832         /*
1833          * In current version VF is not supported when PF is driven by DPDK
1834          * driver, just need to configure parameters for PF vport.
1835          */
1836         vf_id = HNS3_PF_FUNC_ID;
1837         hns3_update_desc_vfid(desc, vf_id, false);
1838         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1839         if (ret) {
1840                 if (ret == -ENOSPC)
1841                         hns3_err(hw, "mc mac vlan table is full");
1842                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1843                                       mac_addr);
1844                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1845         }
1846
1847         return ret;
1848 }
1849
1850 static int
1851 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1852 {
1853         struct hns3_mac_vlan_tbl_entry_cmd req;
1854         struct hns3_cmd_desc desc[3];
1855         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1856         uint8_t vf_id;
1857         int ret;
1858
1859         /* Check if mac addr is valid */
1860         if (!rte_is_multicast_ether_addr(mac_addr)) {
1861                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1862                                       mac_addr);
1863                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1864                          mac_str);
1865                 return -EINVAL;
1866         }
1867
1868         memset(&req, 0, sizeof(req));
1869         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1870         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1871         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1872         if (ret == 0) {
1873                 /*
1874                  * This mac addr exist, remove this handle's VFID for it.
1875                  * In current version VF is not supported when PF is driven by
1876                  * DPDK driver, just need to configure parameters for PF vport.
1877                  */
1878                 vf_id = HNS3_PF_FUNC_ID;
1879                 hns3_update_desc_vfid(desc, vf_id, true);
1880
1881                 /* All the vfid is zero, so need to delete this entry */
1882                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1883         } else if (ret == -ENOENT) {
1884                 /* This mac addr doesn't exist. */
1885                 return 0;
1886         }
1887
1888         if (ret) {
1889                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1890                                       mac_addr);
1891                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1892         }
1893
1894         return ret;
1895 }
1896
1897 static int
1898 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1899                            struct rte_ether_addr *mc_addr_set,
1900                            uint32_t nb_mc_addr)
1901 {
1902         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1903         struct rte_ether_addr *addr;
1904         uint32_t i;
1905         uint32_t j;
1906
1907         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1908                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1909                          "invalid. valid range: 0~%d",
1910                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1911                 return -EINVAL;
1912         }
1913
1914         /* Check if input mac addresses are valid */
1915         for (i = 0; i < nb_mc_addr; i++) {
1916                 addr = &mc_addr_set[i];
1917                 if (!rte_is_multicast_ether_addr(addr)) {
1918                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1919                                               addr);
1920                         hns3_err(hw,
1921                                  "failed to set mc mac addr, addr(%s) invalid.",
1922                                  mac_str);
1923                         return -EINVAL;
1924                 }
1925
1926                 /* Check if there are duplicate addresses */
1927                 for (j = i + 1; j < nb_mc_addr; j++) {
1928                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1929                                 rte_ether_format_addr(mac_str,
1930                                                       RTE_ETHER_ADDR_FMT_SIZE,
1931                                                       addr);
1932                                 hns3_err(hw, "failed to set mc mac addr, "
1933                                          "addrs invalid. two same addrs(%s).",
1934                                          mac_str);
1935                                 return -EINVAL;
1936                         }
1937                 }
1938
1939                 /*
1940                  * Check if there are duplicate addresses between mac_addrs
1941                  * and mc_addr_set
1942                  */
1943                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1944                         if (rte_is_same_ether_addr(addr,
1945                                                    &hw->data->mac_addrs[j])) {
1946                                 rte_ether_format_addr(mac_str,
1947                                                       RTE_ETHER_ADDR_FMT_SIZE,
1948                                                       addr);
1949                                 hns3_err(hw, "failed to set mc mac addr, "
1950                                          "addrs invalid. addrs(%s) has already "
1951                                          "configured in mac_addr add API",
1952                                          mac_str);
1953                                 return -EINVAL;
1954                         }
1955                 }
1956         }
1957
1958         return 0;
1959 }
1960
1961 static void
1962 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1963                            struct rte_ether_addr *mc_addr_set,
1964                            int mc_addr_num,
1965                            struct rte_ether_addr *reserved_addr_list,
1966                            int *reserved_addr_num,
1967                            struct rte_ether_addr *add_addr_list,
1968                            int *add_addr_num,
1969                            struct rte_ether_addr *rm_addr_list,
1970                            int *rm_addr_num)
1971 {
1972         struct rte_ether_addr *addr;
1973         int current_addr_num;
1974         int reserved_num = 0;
1975         int add_num = 0;
1976         int rm_num = 0;
1977         int num;
1978         int i;
1979         int j;
1980         bool same_addr;
1981
1982         /* Calculate the mc mac address list that should be removed */
1983         current_addr_num = hw->mc_addrs_num;
1984         for (i = 0; i < current_addr_num; i++) {
1985                 addr = &hw->mc_addrs[i];
1986                 same_addr = false;
1987                 for (j = 0; j < mc_addr_num; j++) {
1988                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1989                                 same_addr = true;
1990                                 break;
1991                         }
1992                 }
1993
1994                 if (!same_addr) {
1995                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1996                         rm_num++;
1997                 } else {
1998                         rte_ether_addr_copy(addr,
1999                                             &reserved_addr_list[reserved_num]);
2000                         reserved_num++;
2001                 }
2002         }
2003
2004         /* Calculate the mc mac address list that should be added */
2005         for (i = 0; i < mc_addr_num; i++) {
2006                 addr = &mc_addr_set[i];
2007                 same_addr = false;
2008                 for (j = 0; j < current_addr_num; j++) {
2009                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2010                                 same_addr = true;
2011                                 break;
2012                         }
2013                 }
2014
2015                 if (!same_addr) {
2016                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2017                         add_num++;
2018                 }
2019         }
2020
2021         /* Reorder the mc mac address list maintained by driver */
2022         for (i = 0; i < reserved_num; i++)
2023                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2024
2025         for (i = 0; i < rm_num; i++) {
2026                 num = reserved_num + i;
2027                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2028         }
2029
2030         *reserved_addr_num = reserved_num;
2031         *add_addr_num = add_num;
2032         *rm_addr_num = rm_num;
2033 }
2034
2035 static int
2036 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2037                           struct rte_ether_addr *mc_addr_set,
2038                           uint32_t nb_mc_addr)
2039 {
2040         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2042         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2043         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2044         struct rte_ether_addr *addr;
2045         int reserved_addr_num;
2046         int add_addr_num;
2047         int rm_addr_num;
2048         int mc_addr_num;
2049         int num;
2050         int ret;
2051         int i;
2052
2053         /* Check if input parameters are valid */
2054         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2055         if (ret)
2056                 return ret;
2057
2058         rte_spinlock_lock(&hw->lock);
2059
2060         /*
2061          * Calculate the mc mac address lists those should be removed and be
2062          * added, Reorder the mc mac address list maintained by driver.
2063          */
2064         mc_addr_num = (int)nb_mc_addr;
2065         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2066                                    reserved_addr_list, &reserved_addr_num,
2067                                    add_addr_list, &add_addr_num,
2068                                    rm_addr_list, &rm_addr_num);
2069
2070         /* Remove mc mac addresses */
2071         for (i = 0; i < rm_addr_num; i++) {
2072                 num = rm_addr_num - i - 1;
2073                 addr = &rm_addr_list[num];
2074                 ret = hns3_remove_mc_addr(hw, addr);
2075                 if (ret) {
2076                         rte_spinlock_unlock(&hw->lock);
2077                         return ret;
2078                 }
2079                 hw->mc_addrs_num--;
2080         }
2081
2082         /* Add mc mac addresses */
2083         for (i = 0; i < add_addr_num; i++) {
2084                 addr = &add_addr_list[i];
2085                 ret = hns3_add_mc_addr(hw, addr);
2086                 if (ret) {
2087                         rte_spinlock_unlock(&hw->lock);
2088                         return ret;
2089                 }
2090
2091                 num = reserved_addr_num + i;
2092                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2093                 hw->mc_addrs_num++;
2094         }
2095         rte_spinlock_unlock(&hw->lock);
2096
2097         return 0;
2098 }
2099
2100 static int
2101 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2102 {
2103         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2104         struct hns3_hw *hw = &hns->hw;
2105         struct rte_ether_addr *addr;
2106         int err = 0;
2107         int ret;
2108         int i;
2109
2110         for (i = 0; i < hw->mc_addrs_num; i++) {
2111                 addr = &hw->mc_addrs[i];
2112                 if (!rte_is_multicast_ether_addr(addr))
2113                         continue;
2114                 if (del)
2115                         ret = hns3_remove_mc_addr(hw, addr);
2116                 else
2117                         ret = hns3_add_mc_addr(hw, addr);
2118                 if (ret) {
2119                         err = ret;
2120                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2121                                               addr);
2122                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2123                                  del ? "Remove" : "Restore", mac_str, ret);
2124                 }
2125         }
2126         return err;
2127 }
2128
2129 static int
2130 hns3_check_mq_mode(struct rte_eth_dev *dev)
2131 {
2132         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2133         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2134         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2137         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2138         uint8_t num_tc;
2139         int max_tc = 0;
2140         int i;
2141
2142         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2143         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2144
2145         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2146                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2147                          "rx_mq_mode = %d", rx_mq_mode);
2148                 return -EINVAL;
2149         }
2150
2151         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2152             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2153                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2154                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2155                          rx_mq_mode, tx_mq_mode);
2156                 return -EINVAL;
2157         }
2158
2159         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2160                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2161                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2162                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2163                         return -EINVAL;
2164                 }
2165
2166                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2167                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2168                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2169                                  "nb_tcs(%d) != %d or %d in rx direction.",
2170                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2171                         return -EINVAL;
2172                 }
2173
2174                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2175                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2176                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2177                         return -EINVAL;
2178                 }
2179
2180                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2181                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2182                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2183                                          "is not equal to one in tx direction.",
2184                                          i, dcb_rx_conf->dcb_tc[i]);
2185                                 return -EINVAL;
2186                         }
2187                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2188                                 max_tc = dcb_rx_conf->dcb_tc[i];
2189                 }
2190
2191                 num_tc = max_tc + 1;
2192                 if (num_tc > dcb_rx_conf->nb_tcs) {
2193                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2194                                  num_tc, dcb_rx_conf->nb_tcs);
2195                         return -EINVAL;
2196                 }
2197         }
2198
2199         return 0;
2200 }
2201
2202 static int
2203 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2204 {
2205         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206
2207         if (!hns3_dev_dcb_supported(hw)) {
2208                 hns3_err(hw, "this port does not support dcb configurations.");
2209                 return -EOPNOTSUPP;
2210         }
2211
2212         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2213                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2214                 return -EOPNOTSUPP;
2215         }
2216
2217         /* Check multiple queue mode */
2218         return hns3_check_mq_mode(dev);
2219 }
2220
2221 static int
2222 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2223                            enum hns3_ring_type queue_type, uint16_t queue_id)
2224 {
2225         struct hns3_cmd_desc desc;
2226         struct hns3_ctrl_vector_chain_cmd *req =
2227                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2228         enum hns3_cmd_status status;
2229         enum hns3_opcode_type op;
2230         uint16_t tqp_type_and_id = 0;
2231         const char *op_str;
2232         uint16_t type;
2233         uint16_t gl;
2234
2235         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2236         hns3_cmd_setup_basic_desc(&desc, op, false);
2237         req->int_vector_id = vector_id;
2238
2239         if (queue_type == HNS3_RING_TYPE_RX)
2240                 gl = HNS3_RING_GL_RX;
2241         else
2242                 gl = HNS3_RING_GL_TX;
2243
2244         type = queue_type;
2245
2246         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2247                        type);
2248         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2249         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2250                        gl);
2251         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2252         req->int_cause_num = 1;
2253         op_str = mmap ? "Map" : "Unmap";
2254         status = hns3_cmd_send(hw, &desc, 1);
2255         if (status) {
2256                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2257                          op_str, queue_id, req->int_vector_id, status);
2258                 return status;
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_init_ring_with_vector(struct hns3_hw *hw)
2266 {
2267         uint16_t vec;
2268         int ret;
2269         int i;
2270
2271         /*
2272          * In hns3 network engine, vector 0 is always the misc interrupt of this
2273          * function, vector 1~N can be used respectively for the queues of the
2274          * function. Tx and Rx queues with the same number share the interrupt
2275          * vector. In the initialization clearing the all hardware mapping
2276          * relationship configurations between queues and interrupt vectors is
2277          * needed, so some error caused by the residual configurations, such as
2278          * the unexpected Tx interrupt, can be avoid.
2279          */
2280         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2281         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2282                 vec = vec - 1; /* the last interrupt is reserved */
2283         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2284         for (i = 0; i < hw->intr_tqps_num; i++) {
2285                 /*
2286                  * Set gap limiter/rate limiter/quanity limiter algorithm
2287                  * configuration for interrupt coalesce of queue's interrupt.
2288                  */
2289                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2290                                        HNS3_TQP_INTR_GL_DEFAULT);
2291                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2292                                        HNS3_TQP_INTR_GL_DEFAULT);
2293                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2294                 /*
2295                  * QL(quantity limiter) is not used currently, just set 0 to
2296                  * close it.
2297                  */
2298                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2299
2300                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2301                                                  HNS3_RING_TYPE_TX, i);
2302                 if (ret) {
2303                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2304                                           "vector: %d, ret=%d", i, vec, ret);
2305                         return ret;
2306                 }
2307
2308                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2309                                                  HNS3_RING_TYPE_RX, i);
2310                 if (ret) {
2311                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2312                                           "vector: %d, ret=%d", i, vec, ret);
2313                         return ret;
2314                 }
2315         }
2316
2317         return 0;
2318 }
2319
2320 static int
2321 hns3_dev_configure(struct rte_eth_dev *dev)
2322 {
2323         struct hns3_adapter *hns = dev->data->dev_private;
2324         struct rte_eth_conf *conf = &dev->data->dev_conf;
2325         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2326         struct hns3_hw *hw = &hns->hw;
2327         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2328         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2329         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2330         struct rte_eth_rss_conf rss_conf;
2331         uint16_t mtu;
2332         bool gro_en;
2333         int ret;
2334
2335         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2336
2337         /*
2338          * Some versions of hardware network engine does not support
2339          * individually enable/disable/reset the Tx or Rx queue. These devices
2340          * must enable/disable/reset Tx and Rx queues at the same time. When the
2341          * numbers of Tx queues allocated by upper applications are not equal to
2342          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2343          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2344          * work as usual. But these fake queues are imperceptible, and can not
2345          * be used by upper applications.
2346          */
2347         if (!hns3_dev_indep_txrx_supported(hw)) {
2348                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2349                 if (ret) {
2350                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2351                                  ret);
2352                         return ret;
2353                 }
2354         }
2355
2356         hw->adapter_state = HNS3_NIC_CONFIGURING;
2357         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2358                 hns3_err(hw, "setting link speed/duplex not supported");
2359                 ret = -EINVAL;
2360                 goto cfg_err;
2361         }
2362
2363         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2364                 ret = hns3_check_dcb_cfg(dev);
2365                 if (ret)
2366                         goto cfg_err;
2367         }
2368
2369         /* When RSS is not configured, redirect the packet queue 0 */
2370         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2371                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2372                 rss_conf = conf->rx_adv_conf.rss_conf;
2373                 hw->rss_dis_flag = false;
2374                 if (rss_conf.rss_key == NULL) {
2375                         rss_conf.rss_key = rss_cfg->key;
2376                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2377                 }
2378
2379                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2380                 if (ret)
2381                         goto cfg_err;
2382         }
2383
2384         /*
2385          * If jumbo frames are enabled, MTU needs to be refreshed
2386          * according to the maximum RX packet length.
2387          */
2388         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2389                 /*
2390                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2391                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2392                  * can safely assign to "uint16_t" type variable.
2393                  */
2394                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2395                 ret = hns3_dev_mtu_set(dev, mtu);
2396                 if (ret)
2397                         goto cfg_err;
2398                 dev->data->mtu = mtu;
2399         }
2400
2401         ret = hns3_dev_configure_vlan(dev);
2402         if (ret)
2403                 goto cfg_err;
2404
2405         /* config hardware GRO */
2406         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2407         ret = hns3_config_gro(hw, gro_en);
2408         if (ret)
2409                 goto cfg_err;
2410
2411         hns->rx_simple_allowed = true;
2412         hns->rx_vec_allowed = true;
2413         hns->tx_simple_allowed = true;
2414         hns->tx_vec_allowed = true;
2415
2416         hns3_init_rx_ptype_tble(dev);
2417         hw->adapter_state = HNS3_NIC_CONFIGURED;
2418
2419         return 0;
2420
2421 cfg_err:
2422         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2423         hw->adapter_state = HNS3_NIC_INITIALIZED;
2424
2425         return ret;
2426 }
2427
2428 static int
2429 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2430 {
2431         struct hns3_config_max_frm_size_cmd *req;
2432         struct hns3_cmd_desc desc;
2433
2434         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2435
2436         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2437         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2438         req->min_frm_size = RTE_ETHER_MIN_LEN;
2439
2440         return hns3_cmd_send(hw, &desc, 1);
2441 }
2442
2443 static int
2444 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2445 {
2446         int ret;
2447
2448         ret = hns3_set_mac_mtu(hw, mps);
2449         if (ret) {
2450                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2451                 return ret;
2452         }
2453
2454         ret = hns3_buffer_alloc(hw);
2455         if (ret)
2456                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2457
2458         return ret;
2459 }
2460
2461 static int
2462 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2463 {
2464         struct hns3_adapter *hns = dev->data->dev_private;
2465         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2466         struct hns3_hw *hw = &hns->hw;
2467         bool is_jumbo_frame;
2468         int ret;
2469
2470         if (dev->data->dev_started) {
2471                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2472                          "before configuration", dev->data->port_id);
2473                 return -EBUSY;
2474         }
2475
2476         rte_spinlock_lock(&hw->lock);
2477         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2478         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2479
2480         /*
2481          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2482          * assign to "uint16_t" type variable.
2483          */
2484         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2485         if (ret) {
2486                 rte_spinlock_unlock(&hw->lock);
2487                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2488                          dev->data->port_id, mtu, ret);
2489                 return ret;
2490         }
2491         hns->pf.mps = (uint16_t)frame_size;
2492         if (is_jumbo_frame)
2493                 dev->data->dev_conf.rxmode.offloads |=
2494                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2495         else
2496                 dev->data->dev_conf.rxmode.offloads &=
2497                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2498         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2499         rte_spinlock_unlock(&hw->lock);
2500
2501         return 0;
2502 }
2503
2504 static int
2505 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2506 {
2507         struct hns3_adapter *hns = eth_dev->data->dev_private;
2508         struct hns3_hw *hw = &hns->hw;
2509         uint16_t queue_num = hw->tqps_num;
2510
2511         /*
2512          * In interrupt mode, 'max_rx_queues' is set based on the number of
2513          * MSI-X interrupt resources of the hardware.
2514          */
2515         if (hw->data->dev_conf.intr_conf.rxq == 1)
2516                 queue_num = hw->intr_tqps_num;
2517
2518         info->max_rx_queues = queue_num;
2519         info->max_tx_queues = hw->tqps_num;
2520         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2521         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2522         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2523         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2524         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2525         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2526                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2527                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2528                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2529                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2530                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2531                                  DEV_RX_OFFLOAD_KEEP_CRC |
2532                                  DEV_RX_OFFLOAD_SCATTER |
2533                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2534                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2535                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2536                                  DEV_RX_OFFLOAD_RSS_HASH |
2537                                  DEV_RX_OFFLOAD_TCP_LRO);
2538         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2539                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2540                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2541                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2542                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2543                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2544                                  DEV_TX_OFFLOAD_TCP_TSO |
2545                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2546                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2547                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2548                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2549                                  hns3_txvlan_cap_get(hw));
2550
2551         if (hns3_dev_indep_txrx_supported(hw))
2552                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2553                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2554
2555         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2556                 .nb_max = HNS3_MAX_RING_DESC,
2557                 .nb_min = HNS3_MIN_RING_DESC,
2558                 .nb_align = HNS3_ALIGN_RING_DESC,
2559         };
2560
2561         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2562                 .nb_max = HNS3_MAX_RING_DESC,
2563                 .nb_min = HNS3_MIN_RING_DESC,
2564                 .nb_align = HNS3_ALIGN_RING_DESC,
2565                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2566                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2567         };
2568
2569         info->default_rxconf = (struct rte_eth_rxconf) {
2570                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2571                 /*
2572                  * If there are no available Rx buffer descriptors, incoming
2573                  * packets are always dropped by hardware based on hns3 network
2574                  * engine.
2575                  */
2576                 .rx_drop_en = 1,
2577                 .offloads = 0,
2578         };
2579         info->default_txconf = (struct rte_eth_txconf) {
2580                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2581                 .offloads = 0,
2582         };
2583
2584         info->vmdq_queue_num = 0;
2585
2586         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2587         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2588         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2589
2590         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2591         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2592         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2593         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2594         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2595         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2596
2597         return 0;
2598 }
2599
2600 static int
2601 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2602                     size_t fw_size)
2603 {
2604         struct hns3_adapter *hns = eth_dev->data->dev_private;
2605         struct hns3_hw *hw = &hns->hw;
2606         uint32_t version = hw->fw_version;
2607         int ret;
2608
2609         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2610                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2611                                       HNS3_FW_VERSION_BYTE3_S),
2612                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2613                                       HNS3_FW_VERSION_BYTE2_S),
2614                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2615                                       HNS3_FW_VERSION_BYTE1_S),
2616                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2617                                       HNS3_FW_VERSION_BYTE0_S));
2618         ret += 1; /* add the size of '\0' */
2619         if (fw_size < (uint32_t)ret)
2620                 return ret;
2621         else
2622                 return 0;
2623 }
2624
2625 static int
2626 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2627                      __rte_unused int wait_to_complete)
2628 {
2629         struct hns3_adapter *hns = eth_dev->data->dev_private;
2630         struct hns3_hw *hw = &hns->hw;
2631         struct hns3_mac *mac = &hw->mac;
2632         struct rte_eth_link new_link;
2633
2634         if (!hns3_is_reset_pending(hns)) {
2635                 hns3_update_speed_duplex(eth_dev);
2636                 hns3_update_link_status(hw);
2637         }
2638
2639         memset(&new_link, 0, sizeof(new_link));
2640         switch (mac->link_speed) {
2641         case ETH_SPEED_NUM_10M:
2642         case ETH_SPEED_NUM_100M:
2643         case ETH_SPEED_NUM_1G:
2644         case ETH_SPEED_NUM_10G:
2645         case ETH_SPEED_NUM_25G:
2646         case ETH_SPEED_NUM_40G:
2647         case ETH_SPEED_NUM_50G:
2648         case ETH_SPEED_NUM_100G:
2649         case ETH_SPEED_NUM_200G:
2650                 new_link.link_speed = mac->link_speed;
2651                 break;
2652         default:
2653                 new_link.link_speed = ETH_SPEED_NUM_100M;
2654                 break;
2655         }
2656
2657         new_link.link_duplex = mac->link_duplex;
2658         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2659         new_link.link_autoneg =
2660             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2661
2662         return rte_eth_linkstatus_set(eth_dev, &new_link);
2663 }
2664
2665 static int
2666 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2667 {
2668         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2669         struct hns3_pf *pf = &hns->pf;
2670
2671         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2672                 return -EINVAL;
2673
2674         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2675
2676         return 0;
2677 }
2678
2679 static int
2680 hns3_query_function_status(struct hns3_hw *hw)
2681 {
2682 #define HNS3_QUERY_MAX_CNT              10
2683 #define HNS3_QUERY_SLEEP_MSCOEND        1
2684         struct hns3_func_status_cmd *req;
2685         struct hns3_cmd_desc desc;
2686         int timeout = 0;
2687         int ret;
2688
2689         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2690         req = (struct hns3_func_status_cmd *)desc.data;
2691
2692         do {
2693                 ret = hns3_cmd_send(hw, &desc, 1);
2694                 if (ret) {
2695                         PMD_INIT_LOG(ERR, "query function status failed %d",
2696                                      ret);
2697                         return ret;
2698                 }
2699
2700                 /* Check pf reset is done */
2701                 if (req->pf_state)
2702                         break;
2703
2704                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2705         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2706
2707         return hns3_parse_func_status(hw, req);
2708 }
2709
2710 static int
2711 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2712 {
2713         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2714         struct hns3_pf *pf = &hns->pf;
2715
2716         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2717                 /*
2718                  * The total_tqps_num obtained from firmware is maximum tqp
2719                  * numbers of this port, which should be used for PF and VFs.
2720                  * There is no need for pf to have so many tqp numbers in
2721                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2722                  * coming from config file, is assigned to maximum queue number
2723                  * for the PF of this port by user. So users can modify the
2724                  * maximum queue number of PF according to their own application
2725                  * scenarios, which is more flexible to use. In addition, many
2726                  * memories can be saved due to allocating queue statistics
2727                  * room according to the actual number of queues required. The
2728                  * maximum queue number of PF for network engine with
2729                  * revision_id greater than 0x30 is assigned by config file.
2730                  */
2731                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2732                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2733                                  "must be greater than 0.",
2734                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2735                         return -EINVAL;
2736                 }
2737
2738                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2739                                        hw->total_tqps_num);
2740         } else {
2741                 /*
2742                  * Due to the limitation on the number of PF interrupts
2743                  * available, the maximum queue number assigned to PF on
2744                  * the network engine with revision_id 0x21 is 64.
2745                  */
2746                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2747                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2748         }
2749
2750         return 0;
2751 }
2752
2753 static int
2754 hns3_query_pf_resource(struct hns3_hw *hw)
2755 {
2756         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2757         struct hns3_pf *pf = &hns->pf;
2758         struct hns3_pf_res_cmd *req;
2759         struct hns3_cmd_desc desc;
2760         int ret;
2761
2762         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2763         ret = hns3_cmd_send(hw, &desc, 1);
2764         if (ret) {
2765                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2766                 return ret;
2767         }
2768
2769         req = (struct hns3_pf_res_cmd *)desc.data;
2770         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2771                              rte_le_to_cpu_16(req->ext_tqp_num);
2772         ret = hns3_get_pf_max_tqp_num(hw);
2773         if (ret)
2774                 return ret;
2775
2776         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2777         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2778
2779         if (req->tx_buf_size)
2780                 pf->tx_buf_size =
2781                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2782         else
2783                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2784
2785         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2786
2787         if (req->dv_buf_size)
2788                 pf->dv_buf_size =
2789                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2790         else
2791                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2792
2793         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2794
2795         hw->num_msi =
2796                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2797                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2798
2799         return 0;
2800 }
2801
2802 static void
2803 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2804 {
2805         struct hns3_cfg_param_cmd *req;
2806         uint64_t mac_addr_tmp_high;
2807         uint8_t ext_rss_size_max;
2808         uint64_t mac_addr_tmp;
2809         uint32_t i;
2810
2811         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2812
2813         /* get the configuration */
2814         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2815                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2816         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2817                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2818         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2819                                            HNS3_CFG_TQP_DESC_N_M,
2820                                            HNS3_CFG_TQP_DESC_N_S);
2821
2822         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2823                                        HNS3_CFG_PHY_ADDR_M,
2824                                        HNS3_CFG_PHY_ADDR_S);
2825         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2826                                          HNS3_CFG_MEDIA_TP_M,
2827                                          HNS3_CFG_MEDIA_TP_S);
2828         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2829                                          HNS3_CFG_RX_BUF_LEN_M,
2830                                          HNS3_CFG_RX_BUF_LEN_S);
2831         /* get mac address */
2832         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2833         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2834                                            HNS3_CFG_MAC_ADDR_H_M,
2835                                            HNS3_CFG_MAC_ADDR_H_S);
2836
2837         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2838
2839         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2840                                             HNS3_CFG_DEFAULT_SPEED_M,
2841                                             HNS3_CFG_DEFAULT_SPEED_S);
2842         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2843                                            HNS3_CFG_RSS_SIZE_M,
2844                                            HNS3_CFG_RSS_SIZE_S);
2845
2846         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2847                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2848
2849         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2850         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2851
2852         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2853                                             HNS3_CFG_SPEED_ABILITY_M,
2854                                             HNS3_CFG_SPEED_ABILITY_S);
2855         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2856                                         HNS3_CFG_UMV_TBL_SPACE_M,
2857                                         HNS3_CFG_UMV_TBL_SPACE_S);
2858         if (!cfg->umv_space)
2859                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2860
2861         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2862                                                HNS3_CFG_EXT_RSS_SIZE_M,
2863                                                HNS3_CFG_EXT_RSS_SIZE_S);
2864
2865         /*
2866          * Field ext_rss_size_max obtained from firmware will be more flexible
2867          * for future changes and expansions, which is an exponent of 2, instead
2868          * of reading out directly. If this field is not zero, hns3 PF PMD
2869          * driver uses it as rss_size_max under one TC. Device, whose revision
2870          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2871          * maximum number of queues supported under a TC through this field.
2872          */
2873         if (ext_rss_size_max)
2874                 cfg->rss_size_max = 1U << ext_rss_size_max;
2875 }
2876
2877 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2878  * @hw: pointer to struct hns3_hw
2879  * @hcfg: the config structure to be getted
2880  */
2881 static int
2882 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2883 {
2884         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2885         struct hns3_cfg_param_cmd *req;
2886         uint32_t offset;
2887         uint32_t i;
2888         int ret;
2889
2890         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2891                 offset = 0;
2892                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2893                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2894                                           true);
2895                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2896                                i * HNS3_CFG_RD_LEN_BYTES);
2897                 /* Len should be divided by 4 when send to hardware */
2898                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2899                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2900                 req->offset = rte_cpu_to_le_32(offset);
2901         }
2902
2903         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2904         if (ret) {
2905                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2906                 return ret;
2907         }
2908
2909         hns3_parse_cfg(hcfg, desc);
2910
2911         return 0;
2912 }
2913
2914 static int
2915 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2916 {
2917         switch (speed_cmd) {
2918         case HNS3_CFG_SPEED_10M:
2919                 *speed = ETH_SPEED_NUM_10M;
2920                 break;
2921         case HNS3_CFG_SPEED_100M:
2922                 *speed = ETH_SPEED_NUM_100M;
2923                 break;
2924         case HNS3_CFG_SPEED_1G:
2925                 *speed = ETH_SPEED_NUM_1G;
2926                 break;
2927         case HNS3_CFG_SPEED_10G:
2928                 *speed = ETH_SPEED_NUM_10G;
2929                 break;
2930         case HNS3_CFG_SPEED_25G:
2931                 *speed = ETH_SPEED_NUM_25G;
2932                 break;
2933         case HNS3_CFG_SPEED_40G:
2934                 *speed = ETH_SPEED_NUM_40G;
2935                 break;
2936         case HNS3_CFG_SPEED_50G:
2937                 *speed = ETH_SPEED_NUM_50G;
2938                 break;
2939         case HNS3_CFG_SPEED_100G:
2940                 *speed = ETH_SPEED_NUM_100G;
2941                 break;
2942         case HNS3_CFG_SPEED_200G:
2943                 *speed = ETH_SPEED_NUM_200G;
2944                 break;
2945         default:
2946                 return -EINVAL;
2947         }
2948
2949         return 0;
2950 }
2951
2952 static void
2953 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2954 {
2955         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2956         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2957         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2958         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2959         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2960 }
2961
2962 static void
2963 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2964 {
2965         struct hns3_dev_specs_0_cmd *req0;
2966
2967         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2968
2969         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2970         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2971         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2972         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2973         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2974 }
2975
2976 static int
2977 hns3_query_dev_specifications(struct hns3_hw *hw)
2978 {
2979         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2980         int ret;
2981         int i;
2982
2983         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2984                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2985                                           true);
2986                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2987         }
2988         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2989
2990         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2991         if (ret)
2992                 return ret;
2993
2994         hns3_parse_dev_specifications(hw, desc);
2995
2996         return 0;
2997 }
2998
2999 static int
3000 hns3_get_capability(struct hns3_hw *hw)
3001 {
3002         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3003         struct rte_pci_device *pci_dev;
3004         struct hns3_pf *pf = &hns->pf;
3005         struct rte_eth_dev *eth_dev;
3006         uint16_t device_id;
3007         uint8_t revision;
3008         int ret;
3009
3010         eth_dev = &rte_eth_devices[hw->data->port_id];
3011         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3012         device_id = pci_dev->id.device_id;
3013
3014         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3015             device_id == HNS3_DEV_ID_50GE_RDMA ||
3016             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3017             device_id == HNS3_DEV_ID_200G_RDMA)
3018                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3019
3020         ret = hns3_query_dev_fec_info(eth_dev);
3021         if (ret) {
3022                 PMD_INIT_LOG(ERR,
3023                              "failed to query FEC information, ret = %d", ret);
3024                 return ret;
3025         }
3026
3027         /* Get PCI revision id */
3028         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3029                                   HNS3_PCI_REVISION_ID);
3030         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3031                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3032                              ret);
3033                 return -EIO;
3034         }
3035         hw->revision = revision;
3036
3037         if (revision < PCI_REVISION_ID_HIP09_A) {
3038                 hns3_set_default_dev_specifications(hw);
3039                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3040                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3041                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3042                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3043                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3044                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3045                 hw->rss_info.ipv6_sctp_offload_supported = false;
3046                 return 0;
3047         }
3048
3049         ret = hns3_query_dev_specifications(hw);
3050         if (ret) {
3051                 PMD_INIT_LOG(ERR,
3052                              "failed to query dev specifications, ret = %d",
3053                              ret);
3054                 return ret;
3055         }
3056
3057         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3058         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3059         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3060         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3061         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3062         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3063         hw->rss_info.ipv6_sctp_offload_supported = true;
3064
3065         return 0;
3066 }
3067
3068 static int
3069 hns3_get_board_configuration(struct hns3_hw *hw)
3070 {
3071         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3072         struct hns3_pf *pf = &hns->pf;
3073         struct hns3_cfg cfg;
3074         int ret;
3075
3076         ret = hns3_get_board_cfg(hw, &cfg);
3077         if (ret) {
3078                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3079                 return ret;
3080         }
3081
3082         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3083             !hns3_dev_copper_supported(hw)) {
3084                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3085                 return -EOPNOTSUPP;
3086         }
3087
3088         hw->mac.media_type = cfg.media_type;
3089         hw->rss_size_max = cfg.rss_size_max;
3090         hw->rss_dis_flag = false;
3091         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3092         hw->mac.phy_addr = cfg.phy_addr;
3093         hw->mac.default_addr_setted = false;
3094         hw->num_tx_desc = cfg.tqp_desc_num;
3095         hw->num_rx_desc = cfg.tqp_desc_num;
3096         hw->dcb_info.num_pg = 1;
3097         hw->dcb_info.hw_pfc_map = 0;
3098
3099         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3100         if (ret) {
3101                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
3102                              cfg.default_speed, ret);
3103                 return ret;
3104         }
3105
3106         pf->tc_max = cfg.tc_num;
3107         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3108                 PMD_INIT_LOG(WARNING,
3109                              "Get TC num(%u) from flash, set TC num to 1",
3110                              pf->tc_max);
3111                 pf->tc_max = 1;
3112         }
3113
3114         /* Dev does not support DCB */
3115         if (!hns3_dev_dcb_supported(hw)) {
3116                 pf->tc_max = 1;
3117                 pf->pfc_max = 0;
3118         } else
3119                 pf->pfc_max = pf->tc_max;
3120
3121         hw->dcb_info.num_tc = 1;
3122         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3123                                      hw->tqps_num / hw->dcb_info.num_tc);
3124         hns3_set_bit(hw->hw_tc_map, 0, 1);
3125         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3126
3127         pf->wanted_umv_size = cfg.umv_space;
3128
3129         return ret;
3130 }
3131
3132 static int
3133 hns3_get_configuration(struct hns3_hw *hw)
3134 {
3135         int ret;
3136
3137         ret = hns3_query_function_status(hw);
3138         if (ret) {
3139                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3140                 return ret;
3141         }
3142
3143         /* Get device capability */
3144         ret = hns3_get_capability(hw);
3145         if (ret) {
3146                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3147                 return ret;
3148         }
3149
3150         /* Get pf resource */
3151         ret = hns3_query_pf_resource(hw);
3152         if (ret) {
3153                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3154                 return ret;
3155         }
3156
3157         ret = hns3_get_board_configuration(hw);
3158         if (ret)
3159                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3160
3161         return ret;
3162 }
3163
3164 static int
3165 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3166                       uint16_t tqp_vid, bool is_pf)
3167 {
3168         struct hns3_tqp_map_cmd *req;
3169         struct hns3_cmd_desc desc;
3170         int ret;
3171
3172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3173
3174         req = (struct hns3_tqp_map_cmd *)desc.data;
3175         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3176         req->tqp_vf = func_id;
3177         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3178         if (!is_pf)
3179                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3180         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3181
3182         ret = hns3_cmd_send(hw, &desc, 1);
3183         if (ret)
3184                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3185
3186         return ret;
3187 }
3188
3189 static int
3190 hns3_map_tqp(struct hns3_hw *hw)
3191 {
3192         int ret;
3193         int i;
3194
3195         /*
3196          * In current version, VF is not supported when PF is driven by DPDK
3197          * driver, so we assign total tqps_num tqps allocated to this port
3198          * to PF.
3199          */
3200         for (i = 0; i < hw->total_tqps_num; i++) {
3201                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3202                 if (ret)
3203                         return ret;
3204         }
3205
3206         return 0;
3207 }
3208
3209 static int
3210 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3211 {
3212         struct hns3_config_mac_speed_dup_cmd *req;
3213         struct hns3_cmd_desc desc;
3214         int ret;
3215
3216         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3217
3218         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3219
3220         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3221
3222         switch (speed) {
3223         case ETH_SPEED_NUM_10M:
3224                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3225                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3226                 break;
3227         case ETH_SPEED_NUM_100M:
3228                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3229                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3230                 break;
3231         case ETH_SPEED_NUM_1G:
3232                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3233                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3234                 break;
3235         case ETH_SPEED_NUM_10G:
3236                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3237                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3238                 break;
3239         case ETH_SPEED_NUM_25G:
3240                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3241                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3242                 break;
3243         case ETH_SPEED_NUM_40G:
3244                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3245                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3246                 break;
3247         case ETH_SPEED_NUM_50G:
3248                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3249                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3250                 break;
3251         case ETH_SPEED_NUM_100G:
3252                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3253                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3254                 break;
3255         case ETH_SPEED_NUM_200G:
3256                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3257                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3258                 break;
3259         default:
3260                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3261                 return -EINVAL;
3262         }
3263
3264         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3265
3266         ret = hns3_cmd_send(hw, &desc, 1);
3267         if (ret)
3268                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3269
3270         return ret;
3271 }
3272
3273 static int
3274 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3275 {
3276         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3277         struct hns3_pf *pf = &hns->pf;
3278         struct hns3_priv_buf *priv;
3279         uint32_t i, total_size;
3280
3281         total_size = pf->pkt_buf_size;
3282
3283         /* alloc tx buffer for all enabled tc */
3284         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3285                 priv = &buf_alloc->priv_buf[i];
3286
3287                 if (hw->hw_tc_map & BIT(i)) {
3288                         if (total_size < pf->tx_buf_size)
3289                                 return -ENOMEM;
3290
3291                         priv->tx_buf_size = pf->tx_buf_size;
3292                 } else
3293                         priv->tx_buf_size = 0;
3294
3295                 total_size -= priv->tx_buf_size;
3296         }
3297
3298         return 0;
3299 }
3300
3301 static int
3302 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3303 {
3304 /* TX buffer size is unit by 128 byte */
3305 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3306 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3307         struct hns3_tx_buff_alloc_cmd *req;
3308         struct hns3_cmd_desc desc;
3309         uint32_t buf_size;
3310         uint32_t i;
3311         int ret;
3312
3313         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3314
3315         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3316         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3317                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3318
3319                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3320                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3321                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3322         }
3323
3324         ret = hns3_cmd_send(hw, &desc, 1);
3325         if (ret)
3326                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3327
3328         return ret;
3329 }
3330
3331 static int
3332 hns3_get_tc_num(struct hns3_hw *hw)
3333 {
3334         int cnt = 0;
3335         uint8_t i;
3336
3337         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3338                 if (hw->hw_tc_map & BIT(i))
3339                         cnt++;
3340         return cnt;
3341 }
3342
3343 static uint32_t
3344 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3345 {
3346         struct hns3_priv_buf *priv;
3347         uint32_t rx_priv = 0;
3348         int i;
3349
3350         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3351                 priv = &buf_alloc->priv_buf[i];
3352                 if (priv->enable)
3353                         rx_priv += priv->buf_size;
3354         }
3355         return rx_priv;
3356 }
3357
3358 static uint32_t
3359 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3360 {
3361         uint32_t total_tx_size = 0;
3362         uint32_t i;
3363
3364         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3365                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3366
3367         return total_tx_size;
3368 }
3369
3370 /* Get the number of pfc enabled TCs, which have private buffer */
3371 static int
3372 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3373 {
3374         struct hns3_priv_buf *priv;
3375         int cnt = 0;
3376         uint8_t i;
3377
3378         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3379                 priv = &buf_alloc->priv_buf[i];
3380                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3381                         cnt++;
3382         }
3383
3384         return cnt;
3385 }
3386
3387 /* Get the number of pfc disabled TCs, which have private buffer */
3388 static int
3389 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3390                          struct hns3_pkt_buf_alloc *buf_alloc)
3391 {
3392         struct hns3_priv_buf *priv;
3393         int cnt = 0;
3394         uint8_t i;
3395
3396         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3397                 priv = &buf_alloc->priv_buf[i];
3398                 if (hw->hw_tc_map & BIT(i) &&
3399                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3400                         cnt++;
3401         }
3402
3403         return cnt;
3404 }
3405
3406 static bool
3407 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3408                   uint32_t rx_all)
3409 {
3410         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3411         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3412         struct hns3_pf *pf = &hns->pf;
3413         uint32_t shared_buf, aligned_mps;
3414         uint32_t rx_priv;
3415         uint8_t tc_num;
3416         uint8_t i;
3417
3418         tc_num = hns3_get_tc_num(hw);
3419         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3420
3421         if (hns3_dev_dcb_supported(hw))
3422                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3423                                         pf->dv_buf_size;
3424         else
3425                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3426                                         + pf->dv_buf_size;
3427
3428         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3429         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3430                              HNS3_BUF_SIZE_UNIT);
3431
3432         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3433         if (rx_all < rx_priv + shared_std)
3434                 return false;
3435
3436         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3437         buf_alloc->s_buf.buf_size = shared_buf;
3438         if (hns3_dev_dcb_supported(hw)) {
3439                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3440                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3441                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3442                                   HNS3_BUF_SIZE_UNIT);
3443         } else {
3444                 buf_alloc->s_buf.self.high =
3445                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3446                 buf_alloc->s_buf.self.low = aligned_mps;
3447         }
3448
3449         if (hns3_dev_dcb_supported(hw)) {
3450                 hi_thrd = shared_buf - pf->dv_buf_size;
3451
3452                 if (tc_num <= NEED_RESERVE_TC_NUM)
3453                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3454                                         / BUF_MAX_PERCENT;
3455
3456                 if (tc_num)
3457                         hi_thrd = hi_thrd / tc_num;
3458
3459                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3460                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3461                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3462         } else {
3463                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3464                 lo_thrd = aligned_mps;
3465         }
3466
3467         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3468                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3469                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3470         }
3471
3472         return true;
3473 }
3474
3475 static bool
3476 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3477                      struct hns3_pkt_buf_alloc *buf_alloc)
3478 {
3479         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3480         struct hns3_pf *pf = &hns->pf;
3481         struct hns3_priv_buf *priv;
3482         uint32_t aligned_mps;
3483         uint32_t rx_all;
3484         uint8_t i;
3485
3486         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3487         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3488
3489         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3490                 priv = &buf_alloc->priv_buf[i];
3491
3492                 priv->enable = 0;
3493                 priv->wl.low = 0;
3494                 priv->wl.high = 0;
3495                 priv->buf_size = 0;
3496
3497                 if (!(hw->hw_tc_map & BIT(i)))
3498                         continue;
3499
3500                 priv->enable = 1;
3501                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3502                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3503                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3504                                                 HNS3_BUF_SIZE_UNIT);
3505                 } else {
3506                         priv->wl.low = 0;
3507                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3508                                         aligned_mps;
3509                 }
3510
3511                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3512         }
3513
3514         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3515 }
3516
3517 static bool
3518 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3519                              struct hns3_pkt_buf_alloc *buf_alloc)
3520 {
3521         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3522         struct hns3_pf *pf = &hns->pf;
3523         struct hns3_priv_buf *priv;
3524         int no_pfc_priv_num;
3525         uint32_t rx_all;
3526         uint8_t mask;
3527         int i;
3528
3529         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3530         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3531
3532         /* let the last to be cleared first */
3533         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3534                 priv = &buf_alloc->priv_buf[i];
3535                 mask = BIT((uint8_t)i);
3536
3537                 if (hw->hw_tc_map & mask &&
3538                     !(hw->dcb_info.hw_pfc_map & mask)) {
3539                         /* Clear the no pfc TC private buffer */
3540                         priv->wl.low = 0;
3541                         priv->wl.high = 0;
3542                         priv->buf_size = 0;
3543                         priv->enable = 0;
3544                         no_pfc_priv_num--;
3545                 }
3546
3547                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3548                     no_pfc_priv_num == 0)
3549                         break;
3550         }
3551
3552         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3553 }
3554
3555 static bool
3556 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3557                            struct hns3_pkt_buf_alloc *buf_alloc)
3558 {
3559         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3560         struct hns3_pf *pf = &hns->pf;
3561         struct hns3_priv_buf *priv;
3562         uint32_t rx_all;
3563         int pfc_priv_num;
3564         uint8_t mask;
3565         int i;
3566
3567         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3568         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3569
3570         /* let the last to be cleared first */
3571         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3572                 priv = &buf_alloc->priv_buf[i];
3573                 mask = BIT((uint8_t)i);
3574
3575                 if (hw->hw_tc_map & mask &&
3576                     hw->dcb_info.hw_pfc_map & mask) {
3577                         /* Reduce the number of pfc TC with private buffer */
3578                         priv->wl.low = 0;
3579                         priv->enable = 0;
3580                         priv->wl.high = 0;
3581                         priv->buf_size = 0;
3582                         pfc_priv_num--;
3583                 }
3584                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3585                     pfc_priv_num == 0)
3586                         break;
3587         }
3588
3589         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3590 }
3591
3592 static bool
3593 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3594                           struct hns3_pkt_buf_alloc *buf_alloc)
3595 {
3596 #define COMPENSATE_BUFFER       0x3C00
3597 #define COMPENSATE_HALF_MPS_NUM 5
3598 #define PRIV_WL_GAP             0x1800
3599         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3600         struct hns3_pf *pf = &hns->pf;
3601         uint32_t tc_num = hns3_get_tc_num(hw);
3602         uint32_t half_mps = pf->mps >> 1;
3603         struct hns3_priv_buf *priv;
3604         uint32_t min_rx_priv;
3605         uint32_t rx_priv;
3606         uint8_t i;
3607
3608         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3609         if (tc_num)
3610                 rx_priv = rx_priv / tc_num;
3611
3612         if (tc_num <= NEED_RESERVE_TC_NUM)
3613                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3614
3615         /*
3616          * Minimum value of private buffer in rx direction (min_rx_priv) is
3617          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3618          * buffer if rx_priv is greater than min_rx_priv.
3619          */
3620         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3621                         COMPENSATE_HALF_MPS_NUM * half_mps;
3622         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3623         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3624
3625         if (rx_priv < min_rx_priv)
3626                 return false;
3627
3628         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3629                 priv = &buf_alloc->priv_buf[i];
3630
3631                 priv->enable = 0;
3632                 priv->wl.low = 0;
3633                 priv->wl.high = 0;
3634                 priv->buf_size = 0;
3635
3636                 if (!(hw->hw_tc_map & BIT(i)))
3637                         continue;
3638
3639                 priv->enable = 1;
3640                 priv->buf_size = rx_priv;
3641                 priv->wl.high = rx_priv - pf->dv_buf_size;
3642                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3643         }
3644
3645         buf_alloc->s_buf.buf_size = 0;
3646
3647         return true;
3648 }
3649
3650 /*
3651  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3652  * @hw: pointer to struct hns3_hw
3653  * @buf_alloc: pointer to buffer calculation data
3654  * @return: 0: calculate sucessful, negative: fail
3655  */
3656 static int
3657 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3658 {
3659         /* When DCB is not supported, rx private buffer is not allocated. */
3660         if (!hns3_dev_dcb_supported(hw)) {
3661                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3662                 struct hns3_pf *pf = &hns->pf;
3663                 uint32_t rx_all = pf->pkt_buf_size;
3664
3665                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3666                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3667                         return -ENOMEM;
3668
3669                 return 0;
3670         }
3671
3672         /*
3673          * Try to allocate privated packet buffer for all TCs without share
3674          * buffer.
3675          */
3676         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3677                 return 0;
3678
3679         /*
3680          * Try to allocate privated packet buffer for all TCs with share
3681          * buffer.
3682          */
3683         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3684                 return 0;
3685
3686         /*
3687          * For different application scenes, the enabled port number, TC number
3688          * and no_drop TC number are different. In order to obtain the better
3689          * performance, software could allocate the buffer size and configure
3690          * the waterline by tring to decrease the private buffer size according
3691          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3692          * enabled tc.
3693          */
3694         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3695                 return 0;
3696
3697         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3698                 return 0;
3699
3700         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3701                 return 0;
3702
3703         return -ENOMEM;
3704 }
3705
3706 static int
3707 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3708 {
3709         struct hns3_rx_priv_buff_cmd *req;
3710         struct hns3_cmd_desc desc;
3711         uint32_t buf_size;
3712         int ret;
3713         int i;
3714
3715         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3716         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3717
3718         /* Alloc private buffer TCs */
3719         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3720                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3721
3722                 req->buf_num[i] =
3723                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3724                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3725         }
3726
3727         buf_size = buf_alloc->s_buf.buf_size;
3728         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3729                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3730
3731         ret = hns3_cmd_send(hw, &desc, 1);
3732         if (ret)
3733                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3734
3735         return ret;
3736 }
3737
3738 static int
3739 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3740 {
3741 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3742         struct hns3_rx_priv_wl_buf *req;
3743         struct hns3_priv_buf *priv;
3744         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3745         int i, j;
3746         int ret;
3747
3748         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3749                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3750                                           false);
3751                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3752
3753                 /* The first descriptor set the NEXT bit to 1 */
3754                 if (i == 0)
3755                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3756                 else
3757                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3758
3759                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3760                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3761
3762                         priv = &buf_alloc->priv_buf[idx];
3763                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3764                                                         HNS3_BUF_UNIT_S);
3765                         req->tc_wl[j].high |=
3766                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3767                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3768                                                         HNS3_BUF_UNIT_S);
3769                         req->tc_wl[j].low |=
3770                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3771                 }
3772         }
3773
3774         /* Send 2 descriptor at one time */
3775         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3776         if (ret)
3777                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3778                              ret);
3779         return ret;
3780 }
3781
3782 static int
3783 hns3_common_thrd_config(struct hns3_hw *hw,
3784                         struct hns3_pkt_buf_alloc *buf_alloc)
3785 {
3786 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3787         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3788         struct hns3_rx_com_thrd *req;
3789         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3790         struct hns3_tc_thrd *tc;
3791         int tc_idx;
3792         int i, j;
3793         int ret;
3794
3795         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3796                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3797                                           false);
3798                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3799
3800                 /* The first descriptor set the NEXT bit to 1 */
3801                 if (i == 0)
3802                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3803                 else
3804                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3805
3806                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3807                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3808                         tc = &s_buf->tc_thrd[tc_idx];
3809
3810                         req->com_thrd[j].high =
3811                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3812                         req->com_thrd[j].high |=
3813                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3814                         req->com_thrd[j].low =
3815                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3816                         req->com_thrd[j].low |=
3817                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3818                 }
3819         }
3820
3821         /* Send 2 descriptors at one time */
3822         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3823         if (ret)
3824                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3825
3826         return ret;
3827 }
3828
3829 static int
3830 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3831 {
3832         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3833         struct hns3_rx_com_wl *req;
3834         struct hns3_cmd_desc desc;
3835         int ret;
3836
3837         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3838
3839         req = (struct hns3_rx_com_wl *)desc.data;
3840         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3841         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3842
3843         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3844         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3845
3846         ret = hns3_cmd_send(hw, &desc, 1);
3847         if (ret)
3848                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3849
3850         return ret;
3851 }
3852
3853 int
3854 hns3_buffer_alloc(struct hns3_hw *hw)
3855 {
3856         struct hns3_pkt_buf_alloc pkt_buf;
3857         int ret;
3858
3859         memset(&pkt_buf, 0, sizeof(pkt_buf));
3860         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3861         if (ret) {
3862                 PMD_INIT_LOG(ERR,
3863                              "could not calc tx buffer size for all TCs %d",
3864                              ret);
3865                 return ret;
3866         }
3867
3868         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3869         if (ret) {
3870                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3871                 return ret;
3872         }
3873
3874         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3875         if (ret) {
3876                 PMD_INIT_LOG(ERR,
3877                              "could not calc rx priv buffer size for all TCs %d",
3878                              ret);
3879                 return ret;
3880         }
3881
3882         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3883         if (ret) {
3884                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3885                 return ret;
3886         }
3887
3888         if (hns3_dev_dcb_supported(hw)) {
3889                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3890                 if (ret) {
3891                         PMD_INIT_LOG(ERR,
3892                                      "could not configure rx private waterline %d",
3893                                      ret);
3894                         return ret;
3895                 }
3896
3897                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3898                 if (ret) {
3899                         PMD_INIT_LOG(ERR,
3900                                      "could not configure common threshold %d",
3901                                      ret);
3902                         return ret;
3903                 }
3904         }
3905
3906         ret = hns3_common_wl_config(hw, &pkt_buf);
3907         if (ret)
3908                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3909                              ret);
3910
3911         return ret;
3912 }
3913
3914 static int
3915 hns3_mac_init(struct hns3_hw *hw)
3916 {
3917         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3918         struct hns3_mac *mac = &hw->mac;
3919         struct hns3_pf *pf = &hns->pf;
3920         int ret;
3921
3922         pf->support_sfp_query = true;
3923         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3924         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3925         if (ret) {
3926                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3927                 return ret;
3928         }
3929
3930         mac->link_status = ETH_LINK_DOWN;
3931
3932         return hns3_config_mtu(hw, pf->mps);
3933 }
3934
3935 static int
3936 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3937 {
3938 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3939 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3940 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3941 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3942         int return_status;
3943
3944         if (cmdq_resp) {
3945                 PMD_INIT_LOG(ERR,
3946                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3947                              cmdq_resp);
3948                 return -EIO;
3949         }
3950
3951         switch (resp_code) {
3952         case HNS3_ETHERTYPE_SUCCESS_ADD:
3953         case HNS3_ETHERTYPE_ALREADY_ADD:
3954                 return_status = 0;
3955                 break;
3956         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3957                 PMD_INIT_LOG(ERR,
3958                              "add mac ethertype failed for manager table overflow.");
3959                 return_status = -EIO;
3960                 break;
3961         case HNS3_ETHERTYPE_KEY_CONFLICT:
3962                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3963                 return_status = -EIO;
3964                 break;
3965         default:
3966                 PMD_INIT_LOG(ERR,
3967                              "add mac ethertype failed for undefined, code=%d.",
3968                              resp_code);
3969                 return_status = -EIO;
3970                 break;
3971         }
3972
3973         return return_status;
3974 }
3975
3976 static int
3977 hns3_add_mgr_tbl(struct hns3_hw *hw,
3978                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3979 {
3980         struct hns3_cmd_desc desc;
3981         uint8_t resp_code;
3982         uint16_t retval;
3983         int ret;
3984
3985         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3986         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3987
3988         ret = hns3_cmd_send(hw, &desc, 1);
3989         if (ret) {
3990                 PMD_INIT_LOG(ERR,
3991                              "add mac ethertype failed for cmd_send, ret =%d.",
3992                              ret);
3993                 return ret;
3994         }
3995
3996         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3997         retval = rte_le_to_cpu_16(desc.retval);
3998
3999         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4000 }
4001
4002 static void
4003 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4004                      int *table_item_num)
4005 {
4006         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4007
4008         /*
4009          * In current version, we add one item in management table as below:
4010          * 0x0180C200000E -- LLDP MC address
4011          */
4012         tbl = mgr_table;
4013         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4014         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4015         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4016         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4017         tbl->i_port_bitmap = 0x1;
4018         *table_item_num = 1;
4019 }
4020
4021 static int
4022 hns3_init_mgr_tbl(struct hns3_hw *hw)
4023 {
4024 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4025         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4026         int table_item_num;
4027         int ret;
4028         int i;
4029
4030         memset(mgr_table, 0, sizeof(mgr_table));
4031         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4032         for (i = 0; i < table_item_num; i++) {
4033                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4034                 if (ret) {
4035                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4036                                      ret);
4037                         return ret;
4038                 }
4039         }
4040
4041         return 0;
4042 }
4043
4044 static void
4045 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4046                         bool en_mc, bool en_bc, int vport_id)
4047 {
4048         if (!param)
4049                 return;
4050
4051         memset(param, 0, sizeof(struct hns3_promisc_param));
4052         if (en_uc)
4053                 param->enable = HNS3_PROMISC_EN_UC;
4054         if (en_mc)
4055                 param->enable |= HNS3_PROMISC_EN_MC;
4056         if (en_bc)
4057                 param->enable |= HNS3_PROMISC_EN_BC;
4058         param->vf_id = vport_id;
4059 }
4060
4061 static int
4062 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4063 {
4064         struct hns3_promisc_cfg_cmd *req;
4065         struct hns3_cmd_desc desc;
4066         int ret;
4067
4068         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4069
4070         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4071         req->vf_id = param->vf_id;
4072         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4073             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4074
4075         ret = hns3_cmd_send(hw, &desc, 1);
4076         if (ret)
4077                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4078
4079         return ret;
4080 }
4081
4082 static int
4083 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4084 {
4085         struct hns3_promisc_param param;
4086         bool en_bc_pmc = true;
4087         uint8_t vf_id;
4088
4089         /*
4090          * In current version VF is not supported when PF is driven by DPDK
4091          * driver, just need to configure parameters for PF vport.
4092          */
4093         vf_id = HNS3_PF_FUNC_ID;
4094
4095         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4096         return hns3_cmd_set_promisc_mode(hw, &param);
4097 }
4098
4099 static int
4100 hns3_promisc_init(struct hns3_hw *hw)
4101 {
4102         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4103         struct hns3_pf *pf = &hns->pf;
4104         struct hns3_promisc_param param;
4105         uint16_t func_id;
4106         int ret;
4107
4108         ret = hns3_set_promisc_mode(hw, false, false);
4109         if (ret) {
4110                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4111                 return ret;
4112         }
4113
4114         /*
4115          * In current version VFs are not supported when PF is driven by DPDK
4116          * driver. After PF has been taken over by DPDK, the original VF will
4117          * be invalid. So, there is a possibility of entry residues. It should
4118          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4119          * during init.
4120          */
4121         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4122                 hns3_promisc_param_init(&param, false, false, false, func_id);
4123                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4124                 if (ret) {
4125                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4126                                         " ret = %d", func_id, ret);
4127                         return ret;
4128                 }
4129         }
4130
4131         return 0;
4132 }
4133
4134 static void
4135 hns3_promisc_uninit(struct hns3_hw *hw)
4136 {
4137         struct hns3_promisc_param param;
4138         uint16_t func_id;
4139         int ret;
4140
4141         func_id = HNS3_PF_FUNC_ID;
4142
4143         /*
4144          * In current version VFs are not supported when PF is driven by
4145          * DPDK driver, and VFs' promisc mode status has been cleared during
4146          * init and their status will not change. So just clear PF's promisc
4147          * mode status during uninit.
4148          */
4149         hns3_promisc_param_init(&param, false, false, false, func_id);
4150         ret = hns3_cmd_set_promisc_mode(hw, &param);
4151         if (ret)
4152                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4153                                 " uninit, ret = %d", ret);
4154 }
4155
4156 static int
4157 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4158 {
4159         bool allmulti = dev->data->all_multicast ? true : false;
4160         struct hns3_adapter *hns = dev->data->dev_private;
4161         struct hns3_hw *hw = &hns->hw;
4162         uint64_t offloads;
4163         int err;
4164         int ret;
4165
4166         rte_spinlock_lock(&hw->lock);
4167         ret = hns3_set_promisc_mode(hw, true, true);
4168         if (ret) {
4169                 rte_spinlock_unlock(&hw->lock);
4170                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4171                          ret);
4172                 return ret;
4173         }
4174
4175         /*
4176          * When promiscuous mode was enabled, disable the vlan filter to let
4177          * all packets coming in in the receiving direction.
4178          */
4179         offloads = dev->data->dev_conf.rxmode.offloads;
4180         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4181                 ret = hns3_enable_vlan_filter(hns, false);
4182                 if (ret) {
4183                         hns3_err(hw, "failed to enable promiscuous mode due to "
4184                                      "failure to disable vlan filter, ret = %d",
4185                                  ret);
4186                         err = hns3_set_promisc_mode(hw, false, allmulti);
4187                         if (err)
4188                                 hns3_err(hw, "failed to restore promiscuous "
4189                                          "status after disable vlan filter "
4190                                          "failed during enabling promiscuous "
4191                                          "mode, ret = %d", ret);
4192                 }
4193         }
4194
4195         rte_spinlock_unlock(&hw->lock);
4196
4197         return ret;
4198 }
4199
4200 static int
4201 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4202 {
4203         bool allmulti = dev->data->all_multicast ? true : false;
4204         struct hns3_adapter *hns = dev->data->dev_private;
4205         struct hns3_hw *hw = &hns->hw;
4206         uint64_t offloads;
4207         int err;
4208         int ret;
4209
4210         /* If now in all_multicast mode, must remain in all_multicast mode. */
4211         rte_spinlock_lock(&hw->lock);
4212         ret = hns3_set_promisc_mode(hw, false, allmulti);
4213         if (ret) {
4214                 rte_spinlock_unlock(&hw->lock);
4215                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4216                          ret);
4217                 return ret;
4218         }
4219         /* when promiscuous mode was disabled, restore the vlan filter status */
4220         offloads = dev->data->dev_conf.rxmode.offloads;
4221         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4222                 ret = hns3_enable_vlan_filter(hns, true);
4223                 if (ret) {
4224                         hns3_err(hw, "failed to disable promiscuous mode due to"
4225                                  " failure to restore vlan filter, ret = %d",
4226                                  ret);
4227                         err = hns3_set_promisc_mode(hw, true, true);
4228                         if (err)
4229                                 hns3_err(hw, "failed to restore promiscuous "
4230                                          "status after enabling vlan filter "
4231                                          "failed during disabling promiscuous "
4232                                          "mode, ret = %d", ret);
4233                 }
4234         }
4235         rte_spinlock_unlock(&hw->lock);
4236
4237         return ret;
4238 }
4239
4240 static int
4241 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4242 {
4243         struct hns3_adapter *hns = dev->data->dev_private;
4244         struct hns3_hw *hw = &hns->hw;
4245         int ret;
4246
4247         if (dev->data->promiscuous)
4248                 return 0;
4249
4250         rte_spinlock_lock(&hw->lock);
4251         ret = hns3_set_promisc_mode(hw, false, true);
4252         rte_spinlock_unlock(&hw->lock);
4253         if (ret)
4254                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4255                          ret);
4256
4257         return ret;
4258 }
4259
4260 static int
4261 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4262 {
4263         struct hns3_adapter *hns = dev->data->dev_private;
4264         struct hns3_hw *hw = &hns->hw;
4265         int ret;
4266
4267         /* If now in promiscuous mode, must remain in all_multicast mode. */
4268         if (dev->data->promiscuous)
4269                 return 0;
4270
4271         rte_spinlock_lock(&hw->lock);
4272         ret = hns3_set_promisc_mode(hw, false, false);
4273         rte_spinlock_unlock(&hw->lock);
4274         if (ret)
4275                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4276                          ret);
4277
4278         return ret;
4279 }
4280
4281 static int
4282 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4283 {
4284         struct hns3_hw *hw = &hns->hw;
4285         bool allmulti = hw->data->all_multicast ? true : false;
4286         int ret;
4287
4288         if (hw->data->promiscuous) {
4289                 ret = hns3_set_promisc_mode(hw, true, true);
4290                 if (ret)
4291                         hns3_err(hw, "failed to restore promiscuous mode, "
4292                                  "ret = %d", ret);
4293                 return ret;
4294         }
4295
4296         ret = hns3_set_promisc_mode(hw, false, allmulti);
4297         if (ret)
4298                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4299                          ret);
4300         return ret;
4301 }
4302
4303 static int
4304 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4305 {
4306         struct hns3_sfp_speed_cmd *resp;
4307         struct hns3_cmd_desc desc;
4308         int ret;
4309
4310         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4311         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4312         ret = hns3_cmd_send(hw, &desc, 1);
4313         if (ret == -EOPNOTSUPP) {
4314                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4315                 return ret;
4316         } else if (ret) {
4317                 hns3_err(hw, "get sfp speed failed %d", ret);
4318                 return ret;
4319         }
4320
4321         *speed = resp->sfp_speed;
4322
4323         return 0;
4324 }
4325
4326 static uint8_t
4327 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4328 {
4329         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4330                 duplex = ETH_LINK_FULL_DUPLEX;
4331
4332         return duplex;
4333 }
4334
4335 static int
4336 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4337 {
4338         struct hns3_mac *mac = &hw->mac;
4339         uint32_t cur_speed = mac->link_speed;
4340         int ret;
4341
4342         duplex = hns3_check_speed_dup(duplex, speed);
4343         if (mac->link_speed == speed && mac->link_duplex == duplex)
4344                 return 0;
4345
4346         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4347         if (ret)
4348                 return ret;
4349
4350         mac->link_speed = speed;
4351         ret = hns3_dcb_port_shaper_cfg(hw);
4352         if (ret) {
4353                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4354                 mac->link_speed = cur_speed;
4355                 return ret;
4356         }
4357
4358         mac->link_duplex = duplex;
4359
4360         return 0;
4361 }
4362
4363 static int
4364 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4365 {
4366         struct hns3_adapter *hns = eth_dev->data->dev_private;
4367         struct hns3_hw *hw = &hns->hw;
4368         struct hns3_pf *pf = &hns->pf;
4369         uint32_t speed;
4370         int ret;
4371
4372         /* If IMP do not support get SFP/qSFP speed, return directly */
4373         if (!pf->support_sfp_query)
4374                 return 0;
4375
4376         ret = hns3_get_sfp_speed(hw, &speed);
4377         if (ret == -EOPNOTSUPP) {
4378                 pf->support_sfp_query = false;
4379                 return ret;
4380         } else if (ret)
4381                 return ret;
4382
4383         if (speed == ETH_SPEED_NUM_NONE)
4384                 return 0; /* do nothing if no SFP */
4385
4386         /* Config full duplex for SFP */
4387         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4388 }
4389
4390 static int
4391 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4392 {
4393         struct hns3_config_mac_mode_cmd *req;
4394         struct hns3_cmd_desc desc;
4395         uint32_t loop_en = 0;
4396         uint8_t val = 0;
4397         int ret;
4398
4399         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4400
4401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4402         if (enable)
4403                 val = 1;
4404         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4405         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4406         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4407         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4408         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4409         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4410         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4411         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4412         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4413         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4414
4415         /*
4416          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4417          * when receiving frames. Otherwise, CRC will be stripped.
4418          */
4419         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4420                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4421         else
4422                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4423         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4424         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4425         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4426         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4427
4428         ret = hns3_cmd_send(hw, &desc, 1);
4429         if (ret)
4430                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4431
4432         return ret;
4433 }
4434
4435 static int
4436 hns3_get_mac_link_status(struct hns3_hw *hw)
4437 {
4438         struct hns3_link_status_cmd *req;
4439         struct hns3_cmd_desc desc;
4440         int link_status;
4441         int ret;
4442
4443         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4444         ret = hns3_cmd_send(hw, &desc, 1);
4445         if (ret) {
4446                 hns3_err(hw, "get link status cmd failed %d", ret);
4447                 return ETH_LINK_DOWN;
4448         }
4449
4450         req = (struct hns3_link_status_cmd *)desc.data;
4451         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4452
4453         return !!link_status;
4454 }
4455
4456 void
4457 hns3_update_link_status(struct hns3_hw *hw)
4458 {
4459         int state;
4460
4461         state = hns3_get_mac_link_status(hw);
4462         if (state != hw->mac.link_status) {
4463                 hw->mac.link_status = state;
4464                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4465         }
4466 }
4467
4468 static void
4469 hns3_service_handler(void *param)
4470 {
4471         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4472         struct hns3_adapter *hns = eth_dev->data->dev_private;
4473         struct hns3_hw *hw = &hns->hw;
4474
4475         if (!hns3_is_reset_pending(hns)) {
4476                 hns3_update_speed_duplex(eth_dev);
4477                 hns3_update_link_status(hw);
4478         } else
4479                 hns3_warn(hw, "Cancel the query when reset is pending");
4480
4481         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4482 }
4483
4484 static int
4485 hns3_init_hardware(struct hns3_adapter *hns)
4486 {
4487         struct hns3_hw *hw = &hns->hw;
4488         int ret;
4489
4490         ret = hns3_map_tqp(hw);
4491         if (ret) {
4492                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4493                 return ret;
4494         }
4495
4496         ret = hns3_init_umv_space(hw);
4497         if (ret) {
4498                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4499                 return ret;
4500         }
4501
4502         ret = hns3_mac_init(hw);
4503         if (ret) {
4504                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4505                 goto err_mac_init;
4506         }
4507
4508         ret = hns3_init_mgr_tbl(hw);
4509         if (ret) {
4510                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4511                 goto err_mac_init;
4512         }
4513
4514         ret = hns3_promisc_init(hw);
4515         if (ret) {
4516                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4517                              ret);
4518                 goto err_mac_init;
4519         }
4520
4521         ret = hns3_init_vlan_config(hns);
4522         if (ret) {
4523                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4524                 goto err_mac_init;
4525         }
4526
4527         ret = hns3_dcb_init(hw);
4528         if (ret) {
4529                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4530                 goto err_mac_init;
4531         }
4532
4533         ret = hns3_init_fd_config(hns);
4534         if (ret) {
4535                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4536                 goto err_mac_init;
4537         }
4538
4539         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4540         if (ret) {
4541                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4542                 goto err_mac_init;
4543         }
4544
4545         ret = hns3_config_gro(hw, false);
4546         if (ret) {
4547                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4548                 goto err_mac_init;
4549         }
4550
4551         /*
4552          * In the initialization clearing the all hardware mapping relationship
4553          * configurations between queues and interrupt vectors is needed, so
4554          * some error caused by the residual configurations, such as the
4555          * unexpected interrupt, can be avoid.
4556          */
4557         ret = hns3_init_ring_with_vector(hw);
4558         if (ret) {
4559                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4560                 goto err_mac_init;
4561         }
4562
4563         return 0;
4564
4565 err_mac_init:
4566         hns3_uninit_umv_space(hw);
4567         return ret;
4568 }
4569
4570 static int
4571 hns3_clear_hw(struct hns3_hw *hw)
4572 {
4573         struct hns3_cmd_desc desc;
4574         int ret;
4575
4576         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4577
4578         ret = hns3_cmd_send(hw, &desc, 1);
4579         if (ret && ret != -EOPNOTSUPP)
4580                 return ret;
4581
4582         return 0;
4583 }
4584
4585 static void
4586 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4587 {
4588         uint32_t val;
4589
4590         /*
4591          * The new firmware support report more hardware error types by
4592          * msix mode. These errors are defined as RAS errors in hardware
4593          * and belong to a different type from the MSI-x errors processed
4594          * by the network driver.
4595          *
4596          * Network driver should open the new error report on initialition
4597          */
4598         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4599         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4600         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4601 }
4602
4603 static int
4604 hns3_init_pf(struct rte_eth_dev *eth_dev)
4605 {
4606         struct rte_device *dev = eth_dev->device;
4607         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4608         struct hns3_adapter *hns = eth_dev->data->dev_private;
4609         struct hns3_hw *hw = &hns->hw;
4610         int ret;
4611
4612         PMD_INIT_FUNC_TRACE();
4613
4614         /* Get hardware io base address from pcie BAR2 IO space */
4615         hw->io_base = pci_dev->mem_resource[2].addr;
4616
4617         /* Firmware command queue initialize */
4618         ret = hns3_cmd_init_queue(hw);
4619         if (ret) {
4620                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4621                 goto err_cmd_init_queue;
4622         }
4623
4624         hns3_clear_all_event_cause(hw);
4625
4626         /* Firmware command initialize */
4627         ret = hns3_cmd_init(hw);
4628         if (ret) {
4629                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4630                 goto err_cmd_init;
4631         }
4632
4633         /*
4634          * To ensure that the hardware environment is clean during
4635          * initialization, the driver actively clear the hardware environment
4636          * during initialization, including PF and corresponding VFs' vlan, mac,
4637          * flow table configurations, etc.
4638          */
4639         ret = hns3_clear_hw(hw);
4640         if (ret) {
4641                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4642                 goto err_cmd_init;
4643         }
4644
4645         hns3_config_all_msix_error(hw, true);
4646
4647         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4648                                          hns3_interrupt_handler,
4649                                          eth_dev);
4650         if (ret) {
4651                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4652                 goto err_intr_callback_register;
4653         }
4654
4655         /* Enable interrupt */
4656         rte_intr_enable(&pci_dev->intr_handle);
4657         hns3_pf_enable_irq0(hw);
4658
4659         /* Get configuration */
4660         ret = hns3_get_configuration(hw);
4661         if (ret) {
4662                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4663                 goto err_get_config;
4664         }
4665
4666         ret = hns3_tqp_stats_init(hw);
4667         if (ret)
4668                 goto err_get_config;
4669
4670         ret = hns3_init_hardware(hns);
4671         if (ret) {
4672                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4673                 goto err_init_hw;
4674         }
4675
4676         /* Initialize flow director filter list & hash */
4677         ret = hns3_fdir_filter_init(hns);
4678         if (ret) {
4679                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4680                 goto err_fdir;
4681         }
4682
4683         hns3_set_default_rss_args(hw);
4684
4685         ret = hns3_enable_hw_error_intr(hns, true);
4686         if (ret) {
4687                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4688                              ret);
4689                 goto err_enable_intr;
4690         }
4691
4692         return 0;
4693
4694 err_enable_intr:
4695         hns3_fdir_filter_uninit(hns);
4696 err_fdir:
4697         hns3_uninit_umv_space(hw);
4698 err_init_hw:
4699         hns3_tqp_stats_uninit(hw);
4700 err_get_config:
4701         hns3_pf_disable_irq0(hw);
4702         rte_intr_disable(&pci_dev->intr_handle);
4703         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4704                              eth_dev);
4705 err_intr_callback_register:
4706 err_cmd_init:
4707         hns3_cmd_uninit(hw);
4708         hns3_cmd_destroy_queue(hw);
4709 err_cmd_init_queue:
4710         hw->io_base = NULL;
4711
4712         return ret;
4713 }
4714
4715 static void
4716 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4717 {
4718         struct hns3_adapter *hns = eth_dev->data->dev_private;
4719         struct rte_device *dev = eth_dev->device;
4720         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4721         struct hns3_hw *hw = &hns->hw;
4722
4723         PMD_INIT_FUNC_TRACE();
4724
4725         hns3_enable_hw_error_intr(hns, false);
4726         hns3_rss_uninit(hns);
4727         (void)hns3_config_gro(hw, false);
4728         hns3_promisc_uninit(hw);
4729         hns3_fdir_filter_uninit(hns);
4730         hns3_uninit_umv_space(hw);
4731         hns3_tqp_stats_uninit(hw);
4732         hns3_pf_disable_irq0(hw);
4733         rte_intr_disable(&pci_dev->intr_handle);
4734         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4735                              eth_dev);
4736         hns3_config_all_msix_error(hw, false);
4737         hns3_cmd_uninit(hw);
4738         hns3_cmd_destroy_queue(hw);
4739         hw->io_base = NULL;
4740 }
4741
4742 static int
4743 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4744 {
4745         struct hns3_hw *hw = &hns->hw;
4746         int ret;
4747
4748         ret = hns3_dcb_cfg_update(hns);
4749         if (ret)
4750                 return ret;
4751
4752         ret = hns3_init_queues(hns, reset_queue);
4753         if (ret) {
4754                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4755                 return ret;
4756         }
4757
4758         ret = hns3_cfg_mac_mode(hw, true);
4759         if (ret) {
4760                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4761                 goto err_config_mac_mode;
4762         }
4763         return 0;
4764
4765 err_config_mac_mode:
4766         hns3_dev_release_mbufs(hns);
4767         /*
4768          * Here is exception handling, hns3_reset_all_tqps will have the
4769          * corresponding error message if it is handled incorrectly, so it is
4770          * not necessary to check hns3_reset_all_tqps return value, here keep
4771          * ret as the error code causing the exception.
4772          */
4773         (void)hns3_reset_all_tqps(hns);
4774         return ret;
4775 }
4776
4777 static int
4778 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4779 {
4780         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4781         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4782         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4783         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4784         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4785         uint32_t intr_vector;
4786         uint16_t q_id;
4787         int ret;
4788
4789         if (dev->data->dev_conf.intr_conf.rxq == 0)
4790                 return 0;
4791
4792         /* disable uio/vfio intr/eventfd mapping */
4793         rte_intr_disable(intr_handle);
4794
4795         /* check and configure queue intr-vector mapping */
4796         if (rte_intr_cap_multiple(intr_handle) ||
4797             !RTE_ETH_DEV_SRIOV(dev).active) {
4798                 intr_vector = hw->used_rx_queues;
4799                 /* creates event fd for each intr vector when MSIX is used */
4800                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4801                         return -EINVAL;
4802         }
4803         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4804                 intr_handle->intr_vec =
4805                         rte_zmalloc("intr_vec",
4806                                     hw->used_rx_queues * sizeof(int), 0);
4807                 if (intr_handle->intr_vec == NULL) {
4808                         hns3_err(hw, "Failed to allocate %d rx_queues"
4809                                      " intr_vec", hw->used_rx_queues);
4810                         ret = -ENOMEM;
4811                         goto alloc_intr_vec_error;
4812                 }
4813         }
4814
4815         if (rte_intr_allow_others(intr_handle)) {
4816                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4817                 base = RTE_INTR_VEC_RXTX_OFFSET;
4818         }
4819         if (rte_intr_dp_is_en(intr_handle)) {
4820                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4821                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4822                                                          HNS3_RING_TYPE_RX,
4823                                                          q_id);
4824                         if (ret)
4825                                 goto bind_vector_error;
4826                         intr_handle->intr_vec[q_id] = vec;
4827                         if (vec < base + intr_handle->nb_efd - 1)
4828                                 vec++;
4829                 }
4830         }
4831         rte_intr_enable(intr_handle);
4832         return 0;
4833
4834 bind_vector_error:
4835         rte_intr_efd_disable(intr_handle);
4836         if (intr_handle->intr_vec) {
4837                 free(intr_handle->intr_vec);
4838                 intr_handle->intr_vec = NULL;
4839         }
4840         return ret;
4841 alloc_intr_vec_error:
4842         rte_intr_efd_disable(intr_handle);
4843         return ret;
4844 }
4845
4846 static int
4847 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4848 {
4849         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4850         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4851         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4852         uint16_t q_id;
4853         int ret;
4854
4855         if (dev->data->dev_conf.intr_conf.rxq == 0)
4856                 return 0;
4857
4858         if (rte_intr_dp_is_en(intr_handle)) {
4859                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4860                         ret = hns3_bind_ring_with_vector(hw,
4861                                         intr_handle->intr_vec[q_id], true,
4862                                         HNS3_RING_TYPE_RX, q_id);
4863                         if (ret)
4864                                 return ret;
4865                 }
4866         }
4867
4868         return 0;
4869 }
4870
4871 static void
4872 hns3_restore_filter(struct rte_eth_dev *dev)
4873 {
4874         hns3_restore_rss_filter(dev);
4875 }
4876
4877 static int
4878 hns3_dev_start(struct rte_eth_dev *dev)
4879 {
4880         struct hns3_adapter *hns = dev->data->dev_private;
4881         struct hns3_hw *hw = &hns->hw;
4882         int ret;
4883
4884         PMD_INIT_FUNC_TRACE();
4885         if (rte_atomic16_read(&hw->reset.resetting))
4886                 return -EBUSY;
4887
4888         rte_spinlock_lock(&hw->lock);
4889         hw->adapter_state = HNS3_NIC_STARTING;
4890
4891         ret = hns3_do_start(hns, true);
4892         if (ret) {
4893                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4894                 rte_spinlock_unlock(&hw->lock);
4895                 return ret;
4896         }
4897         ret = hns3_map_rx_interrupt(dev);
4898         if (ret) {
4899                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4900                 rte_spinlock_unlock(&hw->lock);
4901                 return ret;
4902         }
4903
4904         /*
4905          * There are three register used to control the status of a TQP
4906          * (contains a pair of Tx queue and Rx queue) in the new version network
4907          * engine. One is used to control the enabling of Tx queue, the other is
4908          * used to control the enabling of Rx queue, and the last is the master
4909          * switch used to control the enabling of the tqp. The Tx register and
4910          * TQP register must be enabled at the same time to enable a Tx queue.
4911          * The same applies to the Rx queue. For the older network engine, this
4912          * function only refresh the enabled flag, and it is used to update the
4913          * status of queue in the dpdk framework.
4914          */
4915         ret = hns3_start_all_txqs(dev);
4916         if (ret) {
4917                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4918                 rte_spinlock_unlock(&hw->lock);
4919                 return ret;
4920         }
4921
4922         ret = hns3_start_all_rxqs(dev);
4923         if (ret) {
4924                 hns3_stop_all_txqs(dev);
4925                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4926                 rte_spinlock_unlock(&hw->lock);
4927                 return ret;
4928         }
4929
4930         hw->adapter_state = HNS3_NIC_STARTED;
4931         rte_spinlock_unlock(&hw->lock);
4932
4933         hns3_rx_scattered_calc(dev);
4934         hns3_set_rxtx_function(dev);
4935         hns3_mp_req_start_rxtx(dev);
4936         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4937
4938         hns3_restore_filter(dev);
4939
4940         /* Enable interrupt of all rx queues before enabling queues */
4941         hns3_dev_all_rx_queue_intr_enable(hw, true);
4942
4943         /*
4944          * After finished the initialization, enable tqps to receive/transmit
4945          * packets and refresh all queue status.
4946          */
4947         hns3_start_tqps(hw);
4948
4949         hns3_info(hw, "hns3 dev start successful!");
4950         return 0;
4951 }
4952
4953 static int
4954 hns3_do_stop(struct hns3_adapter *hns)
4955 {
4956         struct hns3_hw *hw = &hns->hw;
4957         int ret;
4958
4959         ret = hns3_cfg_mac_mode(hw, false);
4960         if (ret)
4961                 return ret;
4962         hw->mac.link_status = ETH_LINK_DOWN;
4963
4964         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4965                 hns3_configure_all_mac_addr(hns, true);
4966                 ret = hns3_reset_all_tqps(hns);
4967                 if (ret) {
4968                         hns3_err(hw, "failed to reset all queues ret = %d.",
4969                                  ret);
4970                         return ret;
4971                 }
4972         }
4973         hw->mac.default_addr_setted = false;
4974         return 0;
4975 }
4976
4977 static void
4978 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4979 {
4980         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4981         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4982         struct hns3_adapter *hns = dev->data->dev_private;
4983         struct hns3_hw *hw = &hns->hw;
4984         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4985         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4986         uint16_t q_id;
4987
4988         if (dev->data->dev_conf.intr_conf.rxq == 0)
4989                 return;
4990
4991         /* unmap the ring with vector */
4992         if (rte_intr_allow_others(intr_handle)) {
4993                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4994                 base = RTE_INTR_VEC_RXTX_OFFSET;
4995         }
4996         if (rte_intr_dp_is_en(intr_handle)) {
4997                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4998                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4999                                                          HNS3_RING_TYPE_RX,
5000                                                          q_id);
5001                         if (vec < base + intr_handle->nb_efd - 1)
5002                                 vec++;
5003                 }
5004         }
5005         /* Clean datapath event and queue/vec mapping */
5006         rte_intr_efd_disable(intr_handle);
5007         if (intr_handle->intr_vec) {
5008                 rte_free(intr_handle->intr_vec);
5009                 intr_handle->intr_vec = NULL;
5010         }
5011 }
5012
5013 static int
5014 hns3_dev_stop(struct rte_eth_dev *dev)
5015 {
5016         struct hns3_adapter *hns = dev->data->dev_private;
5017         struct hns3_hw *hw = &hns->hw;
5018
5019         PMD_INIT_FUNC_TRACE();
5020         dev->data->dev_started = 0;
5021
5022         hw->adapter_state = HNS3_NIC_STOPPING;
5023         hns3_set_rxtx_function(dev);
5024         rte_wmb();
5025         /* Disable datapath on secondary process. */
5026         hns3_mp_req_stop_rxtx(dev);
5027         /* Prevent crashes when queues are still in use. */
5028         rte_delay_ms(hw->tqps_num);
5029
5030         rte_spinlock_lock(&hw->lock);
5031         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
5032                 hns3_stop_tqps(hw);
5033                 hns3_do_stop(hns);
5034                 hns3_unmap_rx_interrupt(dev);
5035                 hns3_dev_release_mbufs(hns);
5036                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5037         }
5038         hns3_rx_scattered_reset(dev);
5039         rte_eal_alarm_cancel(hns3_service_handler, dev);
5040         rte_spinlock_unlock(&hw->lock);
5041
5042         return 0;
5043 }
5044
5045 static int
5046 hns3_dev_close(struct rte_eth_dev *eth_dev)
5047 {
5048         struct hns3_adapter *hns = eth_dev->data->dev_private;
5049         struct hns3_hw *hw = &hns->hw;
5050         int ret = 0;
5051
5052         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5053                 rte_free(eth_dev->process_private);
5054                 eth_dev->process_private = NULL;
5055                 return 0;
5056         }
5057
5058         if (hw->adapter_state == HNS3_NIC_STARTED)
5059                 ret = hns3_dev_stop(eth_dev);
5060
5061         hw->adapter_state = HNS3_NIC_CLOSING;
5062         hns3_reset_abort(hns);
5063         hw->adapter_state = HNS3_NIC_CLOSED;
5064
5065         hns3_configure_all_mc_mac_addr(hns, true);
5066         hns3_remove_all_vlan_table(hns);
5067         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5068         hns3_uninit_pf(eth_dev);
5069         hns3_free_all_queues(eth_dev);
5070         rte_free(hw->reset.wait_data);
5071         rte_free(eth_dev->process_private);
5072         eth_dev->process_private = NULL;
5073         hns3_mp_uninit_primary();
5074         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
5075
5076         return ret;
5077 }
5078
5079 static int
5080 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5081 {
5082         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5084
5085         fc_conf->pause_time = pf->pause_time;
5086
5087         /* return fc current mode */
5088         switch (hw->current_mode) {
5089         case HNS3_FC_FULL:
5090                 fc_conf->mode = RTE_FC_FULL;
5091                 break;
5092         case HNS3_FC_TX_PAUSE:
5093                 fc_conf->mode = RTE_FC_TX_PAUSE;
5094                 break;
5095         case HNS3_FC_RX_PAUSE:
5096                 fc_conf->mode = RTE_FC_RX_PAUSE;
5097                 break;
5098         case HNS3_FC_NONE:
5099         default:
5100                 fc_conf->mode = RTE_FC_NONE;
5101                 break;
5102         }
5103
5104         return 0;
5105 }
5106
5107 static void
5108 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5109 {
5110         switch (mode) {
5111         case RTE_FC_NONE:
5112                 hw->requested_mode = HNS3_FC_NONE;
5113                 break;
5114         case RTE_FC_RX_PAUSE:
5115                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5116                 break;
5117         case RTE_FC_TX_PAUSE:
5118                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5119                 break;
5120         case RTE_FC_FULL:
5121                 hw->requested_mode = HNS3_FC_FULL;
5122                 break;
5123         default:
5124                 hw->requested_mode = HNS3_FC_NONE;
5125                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5126                           "configured to RTE_FC_NONE", mode);
5127                 break;
5128         }
5129 }
5130
5131 static int
5132 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5133 {
5134         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5136         int ret;
5137
5138         if (fc_conf->high_water || fc_conf->low_water ||
5139             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5140                 hns3_err(hw, "Unsupported flow control settings specified, "
5141                          "high_water(%u), low_water(%u), send_xon(%u) and "
5142                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5143                          fc_conf->high_water, fc_conf->low_water,
5144                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5145                 return -EINVAL;
5146         }
5147         if (fc_conf->autoneg) {
5148                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5149                 return -EINVAL;
5150         }
5151         if (!fc_conf->pause_time) {
5152                 hns3_err(hw, "Invalid pause time %d setting.",
5153                          fc_conf->pause_time);
5154                 return -EINVAL;
5155         }
5156
5157         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5158             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5159                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5160                          "current_fc_status = %d", hw->current_fc_status);
5161                 return -EOPNOTSUPP;
5162         }
5163
5164         hns3_get_fc_mode(hw, fc_conf->mode);
5165         if (hw->requested_mode == hw->current_mode &&
5166             pf->pause_time == fc_conf->pause_time)
5167                 return 0;
5168
5169         rte_spinlock_lock(&hw->lock);
5170         ret = hns3_fc_enable(dev, fc_conf);
5171         rte_spinlock_unlock(&hw->lock);
5172
5173         return ret;
5174 }
5175
5176 static int
5177 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5178                             struct rte_eth_pfc_conf *pfc_conf)
5179 {
5180         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5181         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5182         uint8_t priority;
5183         int ret;
5184
5185         if (!hns3_dev_dcb_supported(hw)) {
5186                 hns3_err(hw, "This port does not support dcb configurations.");
5187                 return -EOPNOTSUPP;
5188         }
5189
5190         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5191             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5192                 hns3_err(hw, "Unsupported flow control settings specified, "
5193                          "high_water(%u), low_water(%u), send_xon(%u) and "
5194                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5195                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5196                          pfc_conf->fc.send_xon,
5197                          pfc_conf->fc.mac_ctrl_frame_fwd);
5198                 return -EINVAL;
5199         }
5200         if (pfc_conf->fc.autoneg) {
5201                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5202                 return -EINVAL;
5203         }
5204         if (pfc_conf->fc.pause_time == 0) {
5205                 hns3_err(hw, "Invalid pause time %d setting.",
5206                          pfc_conf->fc.pause_time);
5207                 return -EINVAL;
5208         }
5209
5210         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5211             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5212                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5213                              "current_fc_status = %d", hw->current_fc_status);
5214                 return -EOPNOTSUPP;
5215         }
5216
5217         priority = pfc_conf->priority;
5218         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5219         if (hw->dcb_info.pfc_en & BIT(priority) &&
5220             hw->requested_mode == hw->current_mode &&
5221             pfc_conf->fc.pause_time == pf->pause_time)
5222                 return 0;
5223
5224         rte_spinlock_lock(&hw->lock);
5225         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5226         rte_spinlock_unlock(&hw->lock);
5227
5228         return ret;
5229 }
5230
5231 static int
5232 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5233 {
5234         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5235         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5236         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5237         int i;
5238
5239         rte_spinlock_lock(&hw->lock);
5240         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5241                 dcb_info->nb_tcs = pf->local_max_tc;
5242         else
5243                 dcb_info->nb_tcs = 1;
5244
5245         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5246                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5247         for (i = 0; i < dcb_info->nb_tcs; i++)
5248                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5249
5250         for (i = 0; i < hw->num_tc; i++) {
5251                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5252                 dcb_info->tc_queue.tc_txq[0][i].base =
5253                                                 hw->tc_queue[i].tqp_offset;
5254                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5255                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5256                                                 hw->tc_queue[i].tqp_count;
5257         }
5258         rte_spinlock_unlock(&hw->lock);
5259
5260         return 0;
5261 }
5262
5263 static int
5264 hns3_reinit_dev(struct hns3_adapter *hns)
5265 {
5266         struct hns3_hw *hw = &hns->hw;
5267         int ret;
5268
5269         ret = hns3_cmd_init(hw);
5270         if (ret) {
5271                 hns3_err(hw, "Failed to init cmd: %d", ret);
5272                 return ret;
5273         }
5274
5275         ret = hns3_reset_all_tqps(hns);
5276         if (ret) {
5277                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5278                 return ret;
5279         }
5280
5281         ret = hns3_init_hardware(hns);
5282         if (ret) {
5283                 hns3_err(hw, "Failed to init hardware: %d", ret);
5284                 return ret;
5285         }
5286
5287         ret = hns3_enable_hw_error_intr(hns, true);
5288         if (ret) {
5289                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5290                              ret);
5291                 return ret;
5292         }
5293         hns3_info(hw, "Reset done, driver initialization finished.");
5294
5295         return 0;
5296 }
5297
5298 static bool
5299 is_pf_reset_done(struct hns3_hw *hw)
5300 {
5301         uint32_t val, reg, reg_bit;
5302
5303         switch (hw->reset.level) {
5304         case HNS3_IMP_RESET:
5305                 reg = HNS3_GLOBAL_RESET_REG;
5306                 reg_bit = HNS3_IMP_RESET_BIT;
5307                 break;
5308         case HNS3_GLOBAL_RESET:
5309                 reg = HNS3_GLOBAL_RESET_REG;
5310                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5311                 break;
5312         case HNS3_FUNC_RESET:
5313                 reg = HNS3_FUN_RST_ING;
5314                 reg_bit = HNS3_FUN_RST_ING_B;
5315                 break;
5316         case HNS3_FLR_RESET:
5317         default:
5318                 hns3_err(hw, "Wait for unsupported reset level: %d",
5319                          hw->reset.level);
5320                 return true;
5321         }
5322         val = hns3_read_dev(hw, reg);
5323         if (hns3_get_bit(val, reg_bit))
5324                 return false;
5325         else
5326                 return true;
5327 }
5328
5329 bool
5330 hns3_is_reset_pending(struct hns3_adapter *hns)
5331 {
5332         struct hns3_hw *hw = &hns->hw;
5333         enum hns3_reset_level reset;
5334
5335         hns3_check_event_cause(hns, NULL);
5336         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5337         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5338                 hns3_warn(hw, "High level reset %d is pending", reset);
5339                 return true;
5340         }
5341         reset = hns3_get_reset_level(hns, &hw->reset.request);
5342         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5343                 hns3_warn(hw, "High level reset %d is request", reset);
5344                 return true;
5345         }
5346         return false;
5347 }
5348
5349 static int
5350 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5351 {
5352         struct hns3_hw *hw = &hns->hw;
5353         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5354         struct timeval tv;
5355
5356         if (wait_data->result == HNS3_WAIT_SUCCESS)
5357                 return 0;
5358         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5359                 gettimeofday(&tv, NULL);
5360                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5361                           tv.tv_sec, tv.tv_usec);
5362                 return -ETIME;
5363         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5364                 return -EAGAIN;
5365
5366         wait_data->hns = hns;
5367         wait_data->check_completion = is_pf_reset_done;
5368         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5369                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5370         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5371         wait_data->count = HNS3_RESET_WAIT_CNT;
5372         wait_data->result = HNS3_WAIT_REQUEST;
5373         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5374         return -EAGAIN;
5375 }
5376
5377 static int
5378 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5379 {
5380         struct hns3_cmd_desc desc;
5381         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5382
5383         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5384         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5385         req->fun_reset_vfid = func_id;
5386
5387         return hns3_cmd_send(hw, &desc, 1);
5388 }
5389
5390 static int
5391 hns3_imp_reset_cmd(struct hns3_hw *hw)
5392 {
5393         struct hns3_cmd_desc desc;
5394
5395         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5396         desc.data[0] = 0xeedd;
5397
5398         return hns3_cmd_send(hw, &desc, 1);
5399 }
5400
5401 static void
5402 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5403 {
5404         struct hns3_hw *hw = &hns->hw;
5405         struct timeval tv;
5406         uint32_t val;
5407
5408         gettimeofday(&tv, NULL);
5409         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5410             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5411                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5412                           tv.tv_sec, tv.tv_usec);
5413                 return;
5414         }
5415
5416         switch (reset_level) {
5417         case HNS3_IMP_RESET:
5418                 hns3_imp_reset_cmd(hw);
5419                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5420                           tv.tv_sec, tv.tv_usec);
5421                 break;
5422         case HNS3_GLOBAL_RESET:
5423                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5424                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5425                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5426                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5427                           tv.tv_sec, tv.tv_usec);
5428                 break;
5429         case HNS3_FUNC_RESET:
5430                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5431                           tv.tv_sec, tv.tv_usec);
5432                 /* schedule again to check later */
5433                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5434                 hns3_schedule_reset(hns);
5435                 break;
5436         default:
5437                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5438                 return;
5439         }
5440         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5441 }
5442
5443 static enum hns3_reset_level
5444 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5445 {
5446         struct hns3_hw *hw = &hns->hw;
5447         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5448
5449         /* Return the highest priority reset level amongst all */
5450         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5451                 reset_level = HNS3_IMP_RESET;
5452         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5453                 reset_level = HNS3_GLOBAL_RESET;
5454         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5455                 reset_level = HNS3_FUNC_RESET;
5456         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5457                 reset_level = HNS3_FLR_RESET;
5458
5459         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5460                 return HNS3_NONE_RESET;
5461
5462         return reset_level;
5463 }
5464
5465 static void
5466 hns3_record_imp_error(struct hns3_adapter *hns)
5467 {
5468         struct hns3_hw *hw = &hns->hw;
5469         uint32_t reg_val;
5470
5471         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5472         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5473                 hns3_warn(hw, "Detected IMP RD poison!");
5474                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5475                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5476                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5477         }
5478
5479         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5480                 hns3_warn(hw, "Detected IMP CMDQ error!");
5481                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5482                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5483                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5484         }
5485 }
5486
5487 static int
5488 hns3_prepare_reset(struct hns3_adapter *hns)
5489 {
5490         struct hns3_hw *hw = &hns->hw;
5491         uint32_t reg_val;
5492         int ret;
5493
5494         switch (hw->reset.level) {
5495         case HNS3_FUNC_RESET:
5496                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5497                 if (ret)
5498                         return ret;
5499
5500                 /*
5501                  * After performaning pf reset, it is not necessary to do the
5502                  * mailbox handling or send any command to firmware, because
5503                  * any mailbox handling or command to firmware is only valid
5504                  * after hns3_cmd_init is called.
5505                  */
5506                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5507                 hw->reset.stats.request_cnt++;
5508                 break;
5509         case HNS3_IMP_RESET:
5510                 hns3_record_imp_error(hns);
5511                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5512                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5513                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5514                 break;
5515         default:
5516                 break;
5517         }
5518         return 0;
5519 }
5520
5521 static int
5522 hns3_set_rst_done(struct hns3_hw *hw)
5523 {
5524         struct hns3_pf_rst_done_cmd *req;
5525         struct hns3_cmd_desc desc;
5526
5527         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5528         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5529         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5530         return hns3_cmd_send(hw, &desc, 1);
5531 }
5532
5533 static int
5534 hns3_stop_service(struct hns3_adapter *hns)
5535 {
5536         struct hns3_hw *hw = &hns->hw;
5537         struct rte_eth_dev *eth_dev;
5538
5539         eth_dev = &rte_eth_devices[hw->data->port_id];
5540         if (hw->adapter_state == HNS3_NIC_STARTED)
5541                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5542         hw->mac.link_status = ETH_LINK_DOWN;
5543
5544         hns3_set_rxtx_function(eth_dev);
5545         rte_wmb();
5546         /* Disable datapath on secondary process. */
5547         hns3_mp_req_stop_rxtx(eth_dev);
5548         rte_delay_ms(hw->tqps_num);
5549
5550         rte_spinlock_lock(&hw->lock);
5551         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5552             hw->adapter_state == HNS3_NIC_STOPPING) {
5553                 hns3_enable_all_queues(hw, false);
5554                 hns3_do_stop(hns);
5555                 hw->reset.mbuf_deferred_free = true;
5556         } else
5557                 hw->reset.mbuf_deferred_free = false;
5558
5559         /*
5560          * It is cumbersome for hardware to pick-and-choose entries for deletion
5561          * from table space. Hence, for function reset software intervention is
5562          * required to delete the entries
5563          */
5564         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5565                 hns3_configure_all_mc_mac_addr(hns, true);
5566         rte_spinlock_unlock(&hw->lock);
5567
5568         return 0;
5569 }
5570
5571 static int
5572 hns3_start_service(struct hns3_adapter *hns)
5573 {
5574         struct hns3_hw *hw = &hns->hw;
5575         struct rte_eth_dev *eth_dev;
5576
5577         if (hw->reset.level == HNS3_IMP_RESET ||
5578             hw->reset.level == HNS3_GLOBAL_RESET)
5579                 hns3_set_rst_done(hw);
5580         eth_dev = &rte_eth_devices[hw->data->port_id];
5581         hns3_set_rxtx_function(eth_dev);
5582         hns3_mp_req_start_rxtx(eth_dev);
5583         if (hw->adapter_state == HNS3_NIC_STARTED) {
5584                 hns3_service_handler(eth_dev);
5585
5586                 /* Enable interrupt of all rx queues before enabling queues */
5587                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5588                 /*
5589                  * When finished the initialization, enable queues to receive
5590                  * and transmit packets.
5591                  */
5592                 hns3_enable_all_queues(hw, true);
5593         }
5594
5595         return 0;
5596 }
5597
5598 static int
5599 hns3_restore_conf(struct hns3_adapter *hns)
5600 {
5601         struct hns3_hw *hw = &hns->hw;
5602         int ret;
5603
5604         ret = hns3_configure_all_mac_addr(hns, false);
5605         if (ret)
5606                 return ret;
5607
5608         ret = hns3_configure_all_mc_mac_addr(hns, false);
5609         if (ret)
5610                 goto err_mc_mac;
5611
5612         ret = hns3_dev_promisc_restore(hns);
5613         if (ret)
5614                 goto err_promisc;
5615
5616         ret = hns3_restore_vlan_table(hns);
5617         if (ret)
5618                 goto err_promisc;
5619
5620         ret = hns3_restore_vlan_conf(hns);
5621         if (ret)
5622                 goto err_promisc;
5623
5624         ret = hns3_restore_all_fdir_filter(hns);
5625         if (ret)
5626                 goto err_promisc;
5627
5628         ret = hns3_restore_rx_interrupt(hw);
5629         if (ret)
5630                 goto err_promisc;
5631
5632         ret = hns3_restore_gro_conf(hw);
5633         if (ret)
5634                 goto err_promisc;
5635
5636         ret = hns3_restore_fec(hw);
5637         if (ret)
5638                 goto err_promisc;
5639
5640         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5641                 ret = hns3_do_start(hns, false);
5642                 if (ret)
5643                         goto err_promisc;
5644                 hns3_info(hw, "hns3 dev restart successful!");
5645         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5646                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5647         return 0;
5648
5649 err_promisc:
5650         hns3_configure_all_mc_mac_addr(hns, true);
5651 err_mc_mac:
5652         hns3_configure_all_mac_addr(hns, true);
5653         return ret;
5654 }
5655
5656 static void
5657 hns3_reset_service(void *param)
5658 {
5659         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5660         struct hns3_hw *hw = &hns->hw;
5661         enum hns3_reset_level reset_level;
5662         struct timeval tv_delta;
5663         struct timeval tv_start;
5664         struct timeval tv;
5665         uint64_t msec;
5666         int ret;
5667
5668         /*
5669          * The interrupt is not triggered within the delay time.
5670          * The interrupt may have been lost. It is necessary to handle
5671          * the interrupt to recover from the error.
5672          */
5673         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5674                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5675                 hns3_err(hw, "Handling interrupts in delayed tasks");
5676                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5677                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5678                 if (reset_level == HNS3_NONE_RESET) {
5679                         hns3_err(hw, "No reset level is set, try IMP reset");
5680                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5681                 }
5682         }
5683         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5684
5685         /*
5686          * Check if there is any ongoing reset in the hardware. This status can
5687          * be checked from reset_pending. If there is then, we need to wait for
5688          * hardware to complete reset.
5689          *    a. If we are able to figure out in reasonable time that hardware
5690          *       has fully resetted then, we can proceed with driver, client
5691          *       reset.
5692          *    b. else, we can come back later to check this status so re-sched
5693          *       now.
5694          */
5695         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5696         if (reset_level != HNS3_NONE_RESET) {
5697                 gettimeofday(&tv_start, NULL);
5698                 ret = hns3_reset_process(hns, reset_level);
5699                 gettimeofday(&tv, NULL);
5700                 timersub(&tv, &tv_start, &tv_delta);
5701                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5702                        tv_delta.tv_usec / USEC_PER_MSEC;
5703                 if (msec > HNS3_RESET_PROCESS_MS)
5704                         hns3_err(hw, "%d handle long time delta %" PRIx64
5705                                      " ms time=%ld.%.6ld",
5706                                  hw->reset.level, msec,
5707                                  tv.tv_sec, tv.tv_usec);
5708                 if (ret == -EAGAIN)
5709                         return;
5710         }
5711
5712         /* Check if we got any *new* reset requests to be honored */
5713         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5714         if (reset_level != HNS3_NONE_RESET)
5715                 hns3_msix_process(hns, reset_level);
5716 }
5717
5718 static unsigned int
5719 hns3_get_speed_capa_num(uint16_t device_id)
5720 {
5721         unsigned int num;
5722
5723         switch (device_id) {
5724         case HNS3_DEV_ID_25GE:
5725         case HNS3_DEV_ID_25GE_RDMA:
5726                 num = 2;
5727                 break;
5728         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5729         case HNS3_DEV_ID_200G_RDMA:
5730                 num = 1;
5731                 break;
5732         default:
5733                 num = 0;
5734                 break;
5735         }
5736
5737         return num;
5738 }
5739
5740 static int
5741 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5742                         uint16_t device_id)
5743 {
5744         switch (device_id) {
5745         case HNS3_DEV_ID_25GE:
5746         /* fallthrough */
5747         case HNS3_DEV_ID_25GE_RDMA:
5748                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5749                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5750
5751                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5752                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5753                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5754                 break;
5755         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5756                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5757                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5758                 break;
5759         case HNS3_DEV_ID_200G_RDMA:
5760                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5761                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5762                 break;
5763         default:
5764                 return -ENOTSUP;
5765         }
5766
5767         return 0;
5768 }
5769
5770 static int
5771 hns3_fec_get_capability(struct rte_eth_dev *dev,
5772                         struct rte_eth_fec_capa *speed_fec_capa,
5773                         unsigned int num)
5774 {
5775         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5777         uint16_t device_id = pci_dev->id.device_id;
5778         unsigned int capa_num;
5779         int ret;
5780
5781         capa_num = hns3_get_speed_capa_num(device_id);
5782         if (capa_num == 0) {
5783                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5784                          device_id);
5785                 return -ENOTSUP;
5786         }
5787
5788         if (speed_fec_capa == NULL || num < capa_num)
5789                 return capa_num;
5790
5791         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5792         if (ret)
5793                 return -ENOTSUP;
5794
5795         return capa_num;
5796 }
5797
5798 static int
5799 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5800 {
5801         struct hns3_config_fec_cmd *req;
5802         struct hns3_cmd_desc desc;
5803         int ret;
5804
5805         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5806         req = (struct hns3_config_fec_cmd *)desc.data;
5807         ret = hns3_cmd_send(hw, &desc, 1);
5808         if (ret) {
5809                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5810                          ret);
5811                 return ret;
5812         }
5813
5814         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5815         return 0;
5816 }
5817
5818 static int
5819 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5820 {
5821 #define QUERY_ACTIVE_SPEED      1
5822         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823         struct hns3_sfp_speed_cmd *resp;
5824         uint32_t tmp_fec_capa;
5825         uint8_t auto_state;
5826         struct hns3_cmd_desc desc;
5827         int ret;
5828
5829         /*
5830          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5831          * configured FEC mode is returned.
5832          * If link is up, current FEC mode is returned.
5833          */
5834         if (hw->mac.link_status == ETH_LINK_DOWN) {
5835                 ret = get_current_fec_auto_state(hw, &auto_state);
5836                 if (ret)
5837                         return ret;
5838
5839                 if (auto_state == 0x1) {
5840                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5841                         return 0;
5842                 }
5843         }
5844
5845         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5846         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5847         resp->query_type = QUERY_ACTIVE_SPEED;
5848
5849         ret = hns3_cmd_send(hw, &desc, 1);
5850         if (ret == -EOPNOTSUPP) {
5851                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5852                 return ret;
5853         } else if (ret) {
5854                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5855                 return ret;
5856         }
5857
5858         /*
5859          * FEC mode order defined in hns3 hardware is inconsistend with
5860          * that defined in the ethdev library. So the sequence needs
5861          * to be converted.
5862          */
5863         switch (resp->active_fec) {
5864         case HNS3_HW_FEC_MODE_NOFEC:
5865                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5866                 break;
5867         case HNS3_HW_FEC_MODE_BASER:
5868                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5869                 break;
5870         case HNS3_HW_FEC_MODE_RS:
5871                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5872                 break;
5873         default:
5874                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5875                 break;
5876         }
5877
5878         *fec_capa = tmp_fec_capa;
5879         return 0;
5880 }
5881
5882 static int
5883 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5884 {
5885         struct hns3_config_fec_cmd *req;
5886         struct hns3_cmd_desc desc;
5887         int ret;
5888
5889         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5890
5891         req = (struct hns3_config_fec_cmd *)desc.data;
5892         switch (mode) {
5893         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5894                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5895                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5896                 break;
5897         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5898                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5899                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5900                 break;
5901         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5902                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5903                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5904                 break;
5905         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5906                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5907                 break;
5908         default:
5909                 return 0;
5910         }
5911         ret = hns3_cmd_send(hw, &desc, 1);
5912         if (ret)
5913                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5914
5915         return ret;
5916 }
5917
5918 static uint32_t
5919 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5920 {
5921         struct hns3_mac *mac = &hw->mac;
5922         uint32_t cur_capa;
5923
5924         switch (mac->link_speed) {
5925         case ETH_SPEED_NUM_10G:
5926                 cur_capa = fec_capa[1].capa;
5927                 break;
5928         case ETH_SPEED_NUM_25G:
5929         case ETH_SPEED_NUM_100G:
5930         case ETH_SPEED_NUM_200G:
5931                 cur_capa = fec_capa[0].capa;
5932                 break;
5933         default:
5934                 cur_capa = 0;
5935                 break;
5936         }
5937
5938         return cur_capa;
5939 }
5940
5941 static bool
5942 is_fec_mode_one_bit_set(uint32_t mode)
5943 {
5944         int cnt = 0;
5945         uint8_t i;
5946
5947         for (i = 0; i < sizeof(mode); i++)
5948                 if (mode >> i & 0x1)
5949                         cnt++;
5950
5951         return cnt == 1 ? true : false;
5952 }
5953
5954 static int
5955 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5956 {
5957 #define FEC_CAPA_NUM 2
5958         struct hns3_adapter *hns = dev->data->dev_private;
5959         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
5960         struct hns3_pf *pf = &hns->pf;
5961
5962         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
5963         uint32_t cur_capa;
5964         uint32_t num = FEC_CAPA_NUM;
5965         int ret;
5966
5967         ret = hns3_fec_get_capability(dev, fec_capa, num);
5968         if (ret < 0)
5969                 return ret;
5970
5971         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
5972         if (!is_fec_mode_one_bit_set(mode))
5973                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
5974                              "FEC mode should be only one bit set", mode);
5975
5976         /*
5977          * Check whether the configured mode is within the FEC capability.
5978          * If not, the configured mode will not be supported.
5979          */
5980         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
5981         if (!(cur_capa & mode)) {
5982                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
5983                 return -EINVAL;
5984         }
5985
5986         ret = hns3_set_fec_hw(hw, mode);
5987         if (ret)
5988                 return ret;
5989
5990         pf->fec_mode = mode;
5991         return 0;
5992 }
5993
5994 static int
5995 hns3_restore_fec(struct hns3_hw *hw)
5996 {
5997         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
5998         struct hns3_pf *pf = &hns->pf;
5999         uint32_t mode = pf->fec_mode;
6000         int ret;
6001
6002         ret = hns3_set_fec_hw(hw, mode);
6003         if (ret)
6004                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6005                          mode, ret);
6006
6007         return ret;
6008 }
6009
6010 static int
6011 hns3_query_dev_fec_info(struct rte_eth_dev *dev)
6012 {
6013         struct hns3_adapter *hns = dev->data->dev_private;
6014         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6015         struct hns3_pf *pf = &hns->pf;
6016         int ret;
6017
6018         ret = hns3_fec_get(dev, &pf->fec_mode);
6019         if (ret)
6020                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6021
6022         return ret;
6023 }
6024
6025 static const struct eth_dev_ops hns3_eth_dev_ops = {
6026         .dev_configure      = hns3_dev_configure,
6027         .dev_start          = hns3_dev_start,
6028         .dev_stop           = hns3_dev_stop,
6029         .dev_close          = hns3_dev_close,
6030         .promiscuous_enable = hns3_dev_promiscuous_enable,
6031         .promiscuous_disable = hns3_dev_promiscuous_disable,
6032         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6033         .allmulticast_disable = hns3_dev_allmulticast_disable,
6034         .mtu_set            = hns3_dev_mtu_set,
6035         .stats_get          = hns3_stats_get,
6036         .stats_reset        = hns3_stats_reset,
6037         .xstats_get         = hns3_dev_xstats_get,
6038         .xstats_get_names   = hns3_dev_xstats_get_names,
6039         .xstats_reset       = hns3_dev_xstats_reset,
6040         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6041         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6042         .dev_infos_get          = hns3_dev_infos_get,
6043         .fw_version_get         = hns3_fw_version_get,
6044         .rx_queue_setup         = hns3_rx_queue_setup,
6045         .tx_queue_setup         = hns3_tx_queue_setup,
6046         .rx_queue_release       = hns3_dev_rx_queue_release,
6047         .tx_queue_release       = hns3_dev_tx_queue_release,
6048         .rx_queue_start         = hns3_dev_rx_queue_start,
6049         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6050         .tx_queue_start         = hns3_dev_tx_queue_start,
6051         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6052         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6053         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6054         .rxq_info_get           = hns3_rxq_info_get,
6055         .txq_info_get           = hns3_txq_info_get,
6056         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6057         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6058         .flow_ctrl_get          = hns3_flow_ctrl_get,
6059         .flow_ctrl_set          = hns3_flow_ctrl_set,
6060         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6061         .mac_addr_add           = hns3_add_mac_addr,
6062         .mac_addr_remove        = hns3_remove_mac_addr,
6063         .mac_addr_set           = hns3_set_default_mac_addr,
6064         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6065         .link_update            = hns3_dev_link_update,
6066         .rss_hash_update        = hns3_dev_rss_hash_update,
6067         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6068         .reta_update            = hns3_dev_rss_reta_update,
6069         .reta_query             = hns3_dev_rss_reta_query,
6070         .filter_ctrl            = hns3_dev_filter_ctrl,
6071         .vlan_filter_set        = hns3_vlan_filter_set,
6072         .vlan_tpid_set          = hns3_vlan_tpid_set,
6073         .vlan_offload_set       = hns3_vlan_offload_set,
6074         .vlan_pvid_set          = hns3_vlan_pvid_set,
6075         .get_reg                = hns3_get_regs,
6076         .get_dcb_info           = hns3_get_dcb_info,
6077         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6078         .fec_get_capability     = hns3_fec_get_capability,
6079         .fec_get                = hns3_fec_get,
6080         .fec_set                = hns3_fec_set,
6081 };
6082
6083 static const struct hns3_reset_ops hns3_reset_ops = {
6084         .reset_service       = hns3_reset_service,
6085         .stop_service        = hns3_stop_service,
6086         .prepare_reset       = hns3_prepare_reset,
6087         .wait_hardware_ready = hns3_wait_hardware_ready,
6088         .reinit_dev          = hns3_reinit_dev,
6089         .restore_conf        = hns3_restore_conf,
6090         .start_service       = hns3_start_service,
6091 };
6092
6093 static int
6094 hns3_dev_init(struct rte_eth_dev *eth_dev)
6095 {
6096         struct hns3_adapter *hns = eth_dev->data->dev_private;
6097         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6098         struct rte_ether_addr *eth_addr;
6099         struct hns3_hw *hw = &hns->hw;
6100         int ret;
6101
6102         PMD_INIT_FUNC_TRACE();
6103
6104         eth_dev->process_private = (struct hns3_process_private *)
6105             rte_zmalloc_socket("hns3_filter_list",
6106                                sizeof(struct hns3_process_private),
6107                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6108         if (eth_dev->process_private == NULL) {
6109                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6110                 return -ENOMEM;
6111         }
6112         /* initialize flow filter lists */
6113         hns3_filterlist_init(eth_dev);
6114
6115         hns3_set_rxtx_function(eth_dev);
6116         eth_dev->dev_ops = &hns3_eth_dev_ops;
6117         eth_dev->rx_queue_count = hns3_rx_queue_count;
6118         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6119                 ret = hns3_mp_init_secondary();
6120                 if (ret) {
6121                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6122                                      "process, ret = %d", ret);
6123                         goto err_mp_init_secondary;
6124                 }
6125
6126                 hw->secondary_cnt++;
6127                 return 0;
6128         }
6129
6130         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6131
6132         ret = hns3_mp_init_primary();
6133         if (ret) {
6134                 PMD_INIT_LOG(ERR,
6135                              "Failed to init for primary process, ret = %d",
6136                              ret);
6137                 goto err_mp_init_primary;
6138         }
6139
6140         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6141         hns->is_vf = false;
6142         hw->data = eth_dev->data;
6143
6144         /*
6145          * Set default max packet size according to the mtu
6146          * default vale in DPDK frame.
6147          */
6148         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6149
6150         ret = hns3_reset_init(hw);
6151         if (ret)
6152                 goto err_init_reset;
6153         hw->reset.ops = &hns3_reset_ops;
6154
6155         ret = hns3_init_pf(eth_dev);
6156         if (ret) {
6157                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6158                 goto err_init_pf;
6159         }
6160
6161         /* Allocate memory for storing MAC addresses */
6162         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6163                                                sizeof(struct rte_ether_addr) *
6164                                                HNS3_UC_MACADDR_NUM, 0);
6165         if (eth_dev->data->mac_addrs == NULL) {
6166                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6167                              "to store MAC addresses",
6168                              sizeof(struct rte_ether_addr) *
6169                              HNS3_UC_MACADDR_NUM);
6170                 ret = -ENOMEM;
6171                 goto err_rte_zmalloc;
6172         }
6173
6174         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6175         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6176                 rte_eth_random_addr(hw->mac.mac_addr);
6177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6178                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6179                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6180                           "unicast address, using random MAC address %s",
6181                           mac_str);
6182         }
6183         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6184                             &eth_dev->data->mac_addrs[0]);
6185
6186         hw->adapter_state = HNS3_NIC_INITIALIZED;
6187
6188         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6189                 hns3_err(hw, "Reschedule reset service after dev_init");
6190                 hns3_schedule_reset(hns);
6191         } else {
6192                 /* IMP will wait ready flag before reset */
6193                 hns3_notify_reset_ready(hw, false);
6194         }
6195
6196         hns3_info(hw, "hns3 dev initialization successful!");
6197         return 0;
6198
6199 err_rte_zmalloc:
6200         hns3_uninit_pf(eth_dev);
6201
6202 err_init_pf:
6203         rte_free(hw->reset.wait_data);
6204
6205 err_init_reset:
6206         hns3_mp_uninit_primary();
6207
6208 err_mp_init_primary:
6209 err_mp_init_secondary:
6210         eth_dev->dev_ops = NULL;
6211         eth_dev->rx_pkt_burst = NULL;
6212         eth_dev->tx_pkt_burst = NULL;
6213         eth_dev->tx_pkt_prepare = NULL;
6214         rte_free(eth_dev->process_private);
6215         eth_dev->process_private = NULL;
6216         return ret;
6217 }
6218
6219 static int
6220 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6221 {
6222         struct hns3_adapter *hns = eth_dev->data->dev_private;
6223         struct hns3_hw *hw = &hns->hw;
6224
6225         PMD_INIT_FUNC_TRACE();
6226
6227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6228                 return -EPERM;
6229
6230         if (hw->adapter_state < HNS3_NIC_CLOSING)
6231                 hns3_dev_close(eth_dev);
6232
6233         hw->adapter_state = HNS3_NIC_REMOVED;
6234         return 0;
6235 }
6236
6237 static int
6238 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6239                    struct rte_pci_device *pci_dev)
6240 {
6241         return rte_eth_dev_pci_generic_probe(pci_dev,
6242                                              sizeof(struct hns3_adapter),
6243                                              hns3_dev_init);
6244 }
6245
6246 static int
6247 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6248 {
6249         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6250 }
6251
6252 static const struct rte_pci_id pci_id_hns3_map[] = {
6253         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6254         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6255         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6256         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6257         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6258         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6259         { .vendor_id = 0, /* sentinel */ },
6260 };
6261
6262 static struct rte_pci_driver rte_hns3_pmd = {
6263         .id_table = pci_id_hns3_map,
6264         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6265         .probe = eth_hns3_pci_probe,
6266         .remove = eth_hns3_pci_remove,
6267 };
6268
6269 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6270 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6271 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6272 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6273 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);