drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105 static int hns3_do_stop(struct hns3_adapter *hns);
 106
 107 void hns3_ether_format_addr(char *buf, uint16_t size,
 108                             const struct rte_ether_addr *ether_addr)
 109 {
 110         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 111                 ether_addr->addr_bytes[0],
 112                 ether_addr->addr_bytes[4],
 113                 ether_addr->addr_bytes[5]);
 114 }
 115
 116 static void
 117 hns3_pf_disable_irq0(struct hns3_hw *hw)
 118 {
 119         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 120 }
 121
 122 static void
 123 hns3_pf_enable_irq0(struct hns3_hw *hw)
 124 {
 125         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 126 }
 127
 128 static enum hns3_evt_cause
 129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 130                           uint32_t *vec_val)
 131 {
 132         struct hns3_hw *hw = &hns->hw;
 133
 134         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 135         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 136         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 137         if (!is_delay) {
 138                 hw->reset.stats.imp_cnt++;
 139                 hns3_warn(hw, "IMP reset detected, clear reset status");
 140         } else {
 141                 hns3_schedule_delayed_reset(hns);
 142                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 143         }
 144
 145         return HNS3_VECTOR0_EVENT_RST;
 146 }
 147
 148 static enum hns3_evt_cause
 149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 150                              uint32_t *vec_val)
 151 {
 152         struct hns3_hw *hw = &hns->hw;
 153
 154         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 155         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 156         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 157         if (!is_delay) {
 158                 hw->reset.stats.global_cnt++;
 159                 hns3_warn(hw, "Global reset detected, clear reset status");
 160         } else {
 161                 hns3_schedule_delayed_reset(hns);
 162                 hns3_warn(hw,
 163                           "Global reset detected, don't clear reset status");
 164         }
 165
 166         return HNS3_VECTOR0_EVENT_RST;
 167 }
 168
 169 static enum hns3_evt_cause
 170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 171 {
 172         struct hns3_hw *hw = &hns->hw;
 173         uint32_t vector0_int_stats;
 174         uint32_t cmdq_src_val;
 175         uint32_t hw_err_src_reg;
 176         uint32_t val;
 177         enum hns3_evt_cause ret;
 178         bool is_delay;
 179
 180         /* fetch the events from their corresponding regs */
 181         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 182         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 183         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 184
 185         is_delay = clearval == NULL ? true : false;
 186         /*
 187          * Assumption: If by any chance reset and mailbox events are reported
 188          * together then we will only process reset event and defer the
 189          * processing of the mailbox events. Since, we would have not cleared
 190          * RX CMDQ event this time we would receive again another interrupt
 191          * from H/W just for the mailbox.
 192          */
 193         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 194                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 195                 goto out;
 196         }
 197
 198         /* Global reset */
 199         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 200                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 201                 goto out;
 202         }
 203
 204         /* check for vector0 msix event source */
 205         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 206             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 207                 val = vector0_int_stats | hw_err_src_reg;
 208                 ret = HNS3_VECTOR0_EVENT_ERR;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 mailbox(=CMDQ RX) event source */
 213         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 214                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 215                 val = cmdq_src_val;
 216                 ret = HNS3_VECTOR0_EVENT_MBX;
 217                 goto out;
 218         }
 219
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static void
 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 231 {
 232         if (event_type == HNS3_VECTOR0_EVENT_RST)
 233                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 234         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 235                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 236 }
 237
 238 static void
 239 hns3_clear_all_event_cause(struct hns3_hw *hw)
 240 {
 241         uint32_t vector0_int_stats;
 242         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 243
 244         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 245                 hns3_warn(hw, "Probe during IMP reset interrupt");
 246
 247         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 248                 hns3_warn(hw, "Probe during Global reset interrupt");
 249
 250         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 251                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 252                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 254         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 255 }
 256
 257 static void
 258 hns3_handle_mac_tnl(struct hns3_hw *hw)
 259 {
 260         struct hns3_cmd_desc desc;
 261         uint32_t status;
 262         int ret;
 263
 264         /* query and clear mac tnl interruptions */
 265         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 266         ret = hns3_cmd_send(hw, &desc, 1);
 267         if (ret) {
 268                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 269                 return;
 270         }
 271
 272         status = rte_le_to_cpu_32(desc.data[0]);
 273         if (status) {
 274                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 276                                           false);
 277                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 278                 ret = hns3_cmd_send(hw, &desc, 1);
 279                 if (ret)
 280                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 281                                  ret);
 282         }
 283 }
 284
 285 static void
 286 hns3_interrupt_handler(void *param)
 287 {
 288         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 289         struct hns3_adapter *hns = dev->data->dev_private;
 290         struct hns3_hw *hw = &hns->hw;
 291         enum hns3_evt_cause event_cause;
 292         uint32_t clearval = 0;
 293         uint32_t vector0_int;
 294         uint32_t ras_int;
 295         uint32_t cmdq_int;
 296
 297         /* Disable interrupt */
 298         hns3_pf_disable_irq0(hw);
 299
 300         event_cause = hns3_check_event_cause(hns, &clearval);
 301         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 302         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 303         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 304         /* vector 0 interrupt is shared with reset and mailbox source events. */
 305         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 306                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 307                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 308                           vector0_int, ras_int, cmdq_int);
 309                 hns3_handle_msix_error(hns, &hw->reset.request);
 310                 hns3_handle_ras_error(hns, &hw->reset.request);
 311                 hns3_handle_mac_tnl(hw);
 312                 hns3_schedule_reset(hns);
 313         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 314                 hns3_warn(hw, "received reset interrupt");
 315                 hns3_schedule_reset(hns);
 316         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 317                 hns3_dev_handle_mbx_msg(hw);
 318         } else {
 319                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 320                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 321                           vector0_int, ras_int, cmdq_int);
 322         }
 323
 324         hns3_clear_event_cause(hw, event_cause, clearval);
 325         /* Enable interrupt if it is not cause by reset */
 326         hns3_pf_enable_irq0(hw);
 327 }
 328
 329 static int
 330 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 331 {
 332 #define HNS3_VLAN_ID_OFFSET_STEP        160
 333 #define HNS3_VLAN_BYTE_SIZE             8
 334         struct hns3_vlan_filter_pf_cfg_cmd *req;
 335         struct hns3_hw *hw = &hns->hw;
 336         uint8_t vlan_offset_byte_val;
 337         struct hns3_cmd_desc desc;
 338         uint8_t vlan_offset_byte;
 339         uint8_t vlan_offset_base;
 340         int ret;
 341
 342         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 343
 344         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 345         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 346                            HNS3_VLAN_BYTE_SIZE;
 347         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 348
 349         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 350         req->vlan_offset = vlan_offset_base;
 351         req->vlan_cfg = on ? 0 : 1;
 352         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 353
 354         ret = hns3_cmd_send(hw, &desc, 1);
 355         if (ret)
 356                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 357                          vlan_id, ret);
 358
 359         return ret;
 360 }
 361
 362 static void
 363 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 364 {
 365         struct hns3_user_vlan_table *vlan_entry;
 366         struct hns3_pf *pf = &hns->pf;
 367
 368         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 369                 if (vlan_entry->vlan_id == vlan_id) {
 370                         if (vlan_entry->hd_tbl_status)
 371                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 372                         LIST_REMOVE(vlan_entry, next);
 373                         rte_free(vlan_entry);
 374                         break;
 375                 }
 376         }
 377 }
 378
 379 static void
 380 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 381                         bool writen_to_tbl)
 382 {
 383         struct hns3_user_vlan_table *vlan_entry;
 384         struct hns3_hw *hw = &hns->hw;
 385         struct hns3_pf *pf = &hns->pf;
 386
 387         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 388                 if (vlan_entry->vlan_id == vlan_id)
 389                         return;
 390         }
 391
 392         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 393         if (vlan_entry == NULL) {
 394                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 395                 return;
 396         }
 397
 398         vlan_entry->hd_tbl_status = writen_to_tbl;
 399         vlan_entry->vlan_id = vlan_id;
 400
 401         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 402 }
 403
 404 static int
 405 hns3_restore_vlan_table(struct hns3_adapter *hns)
 406 {
 407         struct hns3_user_vlan_table *vlan_entry;
 408         struct hns3_hw *hw = &hns->hw;
 409         struct hns3_pf *pf = &hns->pf;
 410         uint16_t vlan_id;
 411         int ret = 0;
 412
 413         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 414                 return hns3_vlan_pvid_configure(hns,
 415                                                 hw->port_base_vlan_cfg.pvid, 1);
 416
 417         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 418                 if (vlan_entry->hd_tbl_status) {
 419                         vlan_id = vlan_entry->vlan_id;
 420                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 421                         if (ret)
 422                                 break;
 423                 }
 424         }
 425
 426         return ret;
 427 }
 428
 429 static int
 430 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 431 {
 432         struct hns3_hw *hw = &hns->hw;
 433         bool writen_to_tbl = false;
 434         int ret = 0;
 435
 436         /*
 437          * When vlan filter is enabled, hardware regards packets without vlan
 438          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 439          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 440          */
 441         if (on == 0 && vlan_id == 0)
 442                 return 0;
 443
 444         /*
 445          * When port base vlan enabled, we use port base vlan as the vlan
 446          * filter condition. In this case, we don't update vlan filter table
 447          * when user add new vlan or remove exist vlan, just update the
 448          * vlan list. The vlan id in vlan list will be writen in vlan filter
 449          * table until port base vlan disabled
 450          */
 451         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 452                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 453                 writen_to_tbl = true;
 454         }
 455
 456         if (ret == 0) {
 457                 if (on)
 458                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 459                 else
 460                         hns3_rm_dev_vlan_table(hns, vlan_id);
 461         }
 462         return ret;
 463 }
 464
 465 static int
 466 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 467 {
 468         struct hns3_adapter *hns = dev->data->dev_private;
 469         struct hns3_hw *hw = &hns->hw;
 470         int ret;
 471
 472         rte_spinlock_lock(&hw->lock);
 473         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 474         rte_spinlock_unlock(&hw->lock);
 475         return ret;
 476 }
 477
 478 static int
 479 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 480                          uint16_t tpid)
 481 {
 482         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 483         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 484         struct hns3_hw *hw = &hns->hw;
 485         struct hns3_cmd_desc desc;
 486         int ret;
 487
 488         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 489              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 490                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 491                 return -EINVAL;
 492         }
 493
 494         if (tpid != RTE_ETHER_TYPE_VLAN) {
 495                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 496                 return -EINVAL;
 497         }
 498
 499         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 500         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 501
 502         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 503                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 504                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 505         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 506                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 507                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 508                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 509                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 510         }
 511
 512         ret = hns3_cmd_send(hw, &desc, 1);
 513         if (ret) {
 514                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 515                          ret);
 516                 return ret;
 517         }
 518
 519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 520
 521         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 522         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 523         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 524
 525         ret = hns3_cmd_send(hw, &desc, 1);
 526         if (ret)
 527                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 528                          ret);
 529         return ret;
 530 }
 531
 532 static int
 533 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 534                    uint16_t tpid)
 535 {
 536         struct hns3_adapter *hns = dev->data->dev_private;
 537         struct hns3_hw *hw = &hns->hw;
 538         int ret;
 539
 540         rte_spinlock_lock(&hw->lock);
 541         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 542         rte_spinlock_unlock(&hw->lock);
 543         return ret;
 544 }
 545
 546 static int
 547 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 548                              struct hns3_rx_vtag_cfg *vcfg)
 549 {
 550         struct hns3_vport_vtag_rx_cfg_cmd *req;
 551         struct hns3_hw *hw = &hns->hw;
 552         struct hns3_cmd_desc desc;
 553         uint16_t vport_id;
 554         uint8_t bitmap;
 555         int ret;
 556
 557         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 558
 559         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 560         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 561                      vcfg->strip_tag1_en ? 1 : 0);
 562         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 563                      vcfg->strip_tag2_en ? 1 : 0);
 564         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 565                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 566         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 567                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 568
 569         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 570         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 571                      vcfg->strip_tag1_discard_en ? 1 : 0);
 572         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 573                      vcfg->strip_tag2_discard_en ? 1 : 0);
 574         /*
 575          * In current version VF is not supported when PF is driven by DPDK
 576          * driver, just need to configure parameters for PF vport.
 577          */
 578         vport_id = HNS3_PF_FUNC_ID;
 579         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 580         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 581         req->vf_bitmap[req->vf_offset] = bitmap;
 582
 583         ret = hns3_cmd_send(hw, &desc, 1);
 584         if (ret)
 585                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 586         return ret;
 587 }
 588
 589 static void
 590 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 591                            struct hns3_rx_vtag_cfg *vcfg)
 592 {
 593         struct hns3_pf *pf = &hns->pf;
 594         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 595 }
 596
 597 static void
 598 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 599                            struct hns3_tx_vtag_cfg *vcfg)
 600 {
 601         struct hns3_pf *pf = &hns->pf;
 602         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 603 }
 604
 605 static int
 606 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 607 {
 608         struct hns3_rx_vtag_cfg rxvlan_cfg;
 609         struct hns3_hw *hw = &hns->hw;
 610         int ret;
 611
 612         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 613                 rxvlan_cfg.strip_tag1_en = false;
 614                 rxvlan_cfg.strip_tag2_en = enable;
 615                 rxvlan_cfg.strip_tag2_discard_en = false;
 616         } else {
 617                 rxvlan_cfg.strip_tag1_en = enable;
 618                 rxvlan_cfg.strip_tag2_en = true;
 619                 rxvlan_cfg.strip_tag2_discard_en = true;
 620         }
 621
 622         rxvlan_cfg.strip_tag1_discard_en = false;
 623         rxvlan_cfg.vlan1_vlan_prionly = false;
 624         rxvlan_cfg.vlan2_vlan_prionly = false;
 625         rxvlan_cfg.rx_vlan_offload_en = enable;
 626
 627         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 628         if (ret) {
 629                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 630                 return ret;
 631         }
 632
 633         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 634
 635         return ret;
 636 }
 637
 638 static int
 639 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 640                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 641 {
 642         struct hns3_vlan_filter_ctrl_cmd *req;
 643         struct hns3_cmd_desc desc;
 644         int ret;
 645
 646         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 647
 648         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 649         req->vlan_type = vlan_type;
 650         req->vlan_fe = filter_en ? fe_type : 0;
 651         req->vf_id = vf_id;
 652
 653         ret = hns3_cmd_send(hw, &desc, 1);
 654         if (ret)
 655                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 656
 657         return ret;
 658 }
 659
 660 static int
 661 hns3_vlan_filter_init(struct hns3_adapter *hns)
 662 {
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 667                                         HNS3_FILTER_FE_EGRESS, false,
 668                                         HNS3_PF_FUNC_ID);
 669         if (ret) {
 670                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 671                 return ret;
 672         }
 673
 674         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 675                                         HNS3_FILTER_FE_INGRESS, false,
 676                                         HNS3_PF_FUNC_ID);
 677         if (ret)
 678                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 679
 680         return ret;
 681 }
 682
 683 static int
 684 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 685 {
 686         struct hns3_hw *hw = &hns->hw;
 687         int ret;
 688
 689         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 690                                         HNS3_FILTER_FE_INGRESS, enable,
 691                                         HNS3_PF_FUNC_ID);
 692         if (ret)
 693                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 694                          enable ? "enable" : "disable", ret);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 701 {
 702         struct hns3_adapter *hns = dev->data->dev_private;
 703         struct hns3_hw *hw = &hns->hw;
 704         struct rte_eth_rxmode *rxmode;
 705         unsigned int tmp_mask;
 706         bool enable;
 707         int ret = 0;
 708
 709         rte_spinlock_lock(&hw->lock);
 710         rxmode = &dev->data->dev_conf.rxmode;
 711         tmp_mask = (unsigned int)mask;
 712         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 713                 /* ignore vlan filter configuration during promiscuous mode */
 714                 if (!dev->data->promiscuous) {
 715                         /* Enable or disable VLAN filter */
 716                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 717                                  true : false;
 718
 719                         ret = hns3_enable_vlan_filter(hns, enable);
 720                         if (ret) {
 721                                 rte_spinlock_unlock(&hw->lock);
 722                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 723                                          enable ? "enable" : "disable", ret);
 724                                 return ret;
 725                         }
 726                 }
 727         }
 728
 729         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 730                 /* Enable or disable VLAN stripping */
 731                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 732                     true : false;
 733
 734                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 735                 if (ret) {
 736                         rte_spinlock_unlock(&hw->lock);
 737                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 738                                  enable ? "enable" : "disable", ret);
 739                         return ret;
 740                 }
 741         }
 742
 743         rte_spinlock_unlock(&hw->lock);
 744
 745         return ret;
 746 }
 747
 748 static int
 749 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 750                              struct hns3_tx_vtag_cfg *vcfg)
 751 {
 752         struct hns3_vport_vtag_tx_cfg_cmd *req;
 753         struct hns3_cmd_desc desc;
 754         struct hns3_hw *hw = &hns->hw;
 755         uint16_t vport_id;
 756         uint8_t bitmap;
 757         int ret;
 758
 759         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 760
 761         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 762         req->def_vlan_tag1 = vcfg->default_tag1;
 763         req->def_vlan_tag2 = vcfg->default_tag2;
 764         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 765                      vcfg->accept_tag1 ? 1 : 0);
 766         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 767                      vcfg->accept_untag1 ? 1 : 0);
 768         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 769                      vcfg->accept_tag2 ? 1 : 0);
 770         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 771                      vcfg->accept_untag2 ? 1 : 0);
 772         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 773                      vcfg->insert_tag1_en ? 1 : 0);
 774         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 775                      vcfg->insert_tag2_en ? 1 : 0);
 776         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 777
 778         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 779         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 780                      vcfg->tag_shift_mode_en ? 1 : 0);
 781
 782         /*
 783          * In current version VF is not supported when PF is driven by DPDK
 784          * driver, just need to configure parameters for PF vport.
 785          */
 786         vport_id = HNS3_PF_FUNC_ID;
 787         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 788         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 789         req->vf_bitmap[req->vf_offset] = bitmap;
 790
 791         ret = hns3_cmd_send(hw, &desc, 1);
 792         if (ret)
 793                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 794
 795         return ret;
 796 }
 797
 798 static int
 799 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 800                      uint16_t pvid)
 801 {
 802         struct hns3_hw *hw = &hns->hw;
 803         struct hns3_tx_vtag_cfg txvlan_cfg;
 804         int ret;
 805
 806         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 807                 txvlan_cfg.accept_tag1 = true;
 808                 txvlan_cfg.insert_tag1_en = false;
 809                 txvlan_cfg.default_tag1 = 0;
 810         } else {
 811                 txvlan_cfg.accept_tag1 =
 812                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 813                 txvlan_cfg.insert_tag1_en = true;
 814                 txvlan_cfg.default_tag1 = pvid;
 815         }
 816
 817         txvlan_cfg.accept_untag1 = true;
 818         txvlan_cfg.accept_tag2 = true;
 819         txvlan_cfg.accept_untag2 = true;
 820         txvlan_cfg.insert_tag2_en = false;
 821         txvlan_cfg.default_tag2 = 0;
 822         txvlan_cfg.tag_shift_mode_en = true;
 823
 824         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 825         if (ret) {
 826                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 827                          ret);
 828                 return ret;
 829         }
 830
 831         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 832         return ret;
 833 }
 834
 835
 836 static void
 837 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 838 {
 839         struct hns3_user_vlan_table *vlan_entry;
 840         struct hns3_pf *pf = &hns->pf;
 841
 842         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 843                 if (vlan_entry->hd_tbl_status) {
 844                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 845                         vlan_entry->hd_tbl_status = false;
 846                 }
 847         }
 848
 849         if (is_del_list) {
 850                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 851                 while (vlan_entry) {
 852                         LIST_REMOVE(vlan_entry, next);
 853                         rte_free(vlan_entry);
 854                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 855                 }
 856         }
 857 }
 858
 859 static void
 860 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 861 {
 862         struct hns3_user_vlan_table *vlan_entry;
 863         struct hns3_pf *pf = &hns->pf;
 864
 865         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 866                 if (!vlan_entry->hd_tbl_status) {
 867                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 868                         vlan_entry->hd_tbl_status = true;
 869                 }
 870         }
 871 }
 872
 873 static void
 874 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 875 {
 876         struct hns3_hw *hw = &hns->hw;
 877         int ret;
 878
 879         hns3_rm_all_vlan_table(hns, true);
 880         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 881                 ret = hns3_set_port_vlan_filter(hns,
 882                                                 hw->port_base_vlan_cfg.pvid, 0);
 883                 if (ret) {
 884                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 885                                  ret);
 886                         return;
 887                 }
 888         }
 889 }
 890
 891 static int
 892 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 893                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 894 {
 895         struct hns3_hw *hw = &hns->hw;
 896         uint16_t old_pvid;
 897         int ret;
 898
 899         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 900                 old_pvid = hw->port_base_vlan_cfg.pvid;
 901                 if (old_pvid != HNS3_INVALID_PVID) {
 902                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 903                         if (ret) {
 904                                 hns3_err(hw, "failed to remove old pvid %u, "
 905                                                 "ret = %d", old_pvid, ret);
 906                                 return ret;
 907                         }
 908                 }
 909
 910                 hns3_rm_all_vlan_table(hns, false);
 911                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 912                 if (ret) {
 913                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 914                                         new_pvid, ret);
 915                         return ret;
 916                 }
 917         } else {
 918                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 919                 if (ret) {
 920                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 921                                         new_pvid, ret);
 922                         return ret;
 923                 }
 924
 925                 hns3_add_all_vlan_table(hns);
 926         }
 927         return 0;
 928 }
 929
 930 static int
 931 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 932 {
 933         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 934         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 935         bool rx_strip_en;
 936         int ret;
 937
 938         rx_strip_en = old_cfg->rx_vlan_offload_en;
 939         if (on) {
 940                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 941                 rx_vlan_cfg.strip_tag2_en = true;
 942                 rx_vlan_cfg.strip_tag2_discard_en = true;
 943         } else {
 944                 rx_vlan_cfg.strip_tag1_en = false;
 945                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 946                 rx_vlan_cfg.strip_tag2_discard_en = false;
 947         }
 948         rx_vlan_cfg.strip_tag1_discard_en = false;
 949         rx_vlan_cfg.vlan1_vlan_prionly = false;
 950         rx_vlan_cfg.vlan2_vlan_prionly = false;
 951         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 952
 953         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 954         if (ret)
 955                 return ret;
 956
 957         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 958         return ret;
 959 }
 960
 961 static int
 962 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 963 {
 964         struct hns3_hw *hw = &hns->hw;
 965         uint16_t port_base_vlan_state;
 966         int ret;
 967
 968         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 969                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 970                         hns3_warn(hw, "Invalid operation! As current pvid set "
 971                                   "is %u, disable pvid %u is invalid",
 972                                   hw->port_base_vlan_cfg.pvid, pvid);
 973                 return 0;
 974         }
 975
 976         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 977                                     HNS3_PORT_BASE_VLAN_DISABLE;
 978         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 979         if (ret) {
 980                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 981                          ret);
 982                 return ret;
 983         }
 984
 985         ret = hns3_en_pvid_strip(hns, on);
 986         if (ret) {
 987                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 988                          "ret = %d", ret);
 989                 return ret;
 990         }
 991
 992         if (pvid == HNS3_INVALID_PVID)
 993                 goto out;
 994         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 995         if (ret) {
 996                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 997                          ret);
 998                 return ret;
 999         }
1000
1001 out:
1002         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1003         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1004         return ret;
1005 }
1006
1007 static int
1008 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1009 {
1010         struct hns3_adapter *hns = dev->data->dev_private;
1011         struct hns3_hw *hw = &hns->hw;
1012         bool pvid_en_state_change;
1013         uint16_t pvid_state;
1014         int ret;
1015
1016         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1017                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1018                          RTE_ETHER_MAX_VLAN_ID);
1019                 return -EINVAL;
1020         }
1021
1022         /*
1023          * If PVID configuration state change, should refresh the PVID
1024          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1025          */
1026         pvid_state = hw->port_base_vlan_cfg.state;
1027         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1028             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1029                 pvid_en_state_change = false;
1030         else
1031                 pvid_en_state_change = true;
1032
1033         rte_spinlock_lock(&hw->lock);
1034         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1035         rte_spinlock_unlock(&hw->lock);
1036         if (ret)
1037                 return ret;
1038         /*
1039          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1040          * need be processed by PMD driver.
1041          */
1042         if (pvid_en_state_change &&
1043             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1044                 hns3_update_all_queues_pvid_proc_en(hw);
1045
1046         return 0;
1047 }
1048
1049 static int
1050 hns3_default_vlan_config(struct hns3_adapter *hns)
1051 {
1052         struct hns3_hw *hw = &hns->hw;
1053         int ret;
1054
1055         /*
1056          * When vlan filter is enabled, hardware regards packets without vlan
1057          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1058          * table, packets without vlan won't be received. So, add vlan 0 as
1059          * the default vlan.
1060          */
1061         ret = hns3_vlan_filter_configure(hns, 0, 1);
1062         if (ret)
1063                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1064         return ret;
1065 }
1066
1067 static int
1068 hns3_init_vlan_config(struct hns3_adapter *hns)
1069 {
1070         struct hns3_hw *hw = &hns->hw;
1071         int ret;
1072
1073         /*
1074          * This function can be called in the initialization and reset process,
1075          * when in reset process, it means that hardware had been reseted
1076          * successfully and we need to restore the hardware configuration to
1077          * ensure that the hardware configuration remains unchanged before and
1078          * after reset.
1079          */
1080         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1081                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1082                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1083         }
1084
1085         ret = hns3_vlan_filter_init(hns);
1086         if (ret) {
1087                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1088                 return ret;
1089         }
1090
1091         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1092                                        RTE_ETHER_TYPE_VLAN);
1093         if (ret) {
1094                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1095                 return ret;
1096         }
1097
1098         /*
1099          * When in the reinit dev stage of the reset process, the following
1100          * vlan-related configurations may differ from those at initialization,
1101          * we will restore configurations to hardware in hns3_restore_vlan_table
1102          * and hns3_restore_vlan_conf later.
1103          */
1104         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1105                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1106                 if (ret) {
1107                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1108                         return ret;
1109                 }
1110
1111                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1112                 if (ret) {
1113                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1114                                  ret);
1115                         return ret;
1116                 }
1117         }
1118
1119         return hns3_default_vlan_config(hns);
1120 }
1121
1122 static int
1123 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1124 {
1125         struct hns3_pf *pf = &hns->pf;
1126         struct hns3_hw *hw = &hns->hw;
1127         uint64_t offloads;
1128         bool enable;
1129         int ret;
1130
1131         if (!hw->data->promiscuous) {
1132                 /* restore vlan filter states */
1133                 offloads = hw->data->dev_conf.rxmode.offloads;
1134                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1135                 ret = hns3_enable_vlan_filter(hns, enable);
1136                 if (ret) {
1137                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1138                                  "ret = %d", ret);
1139                         return ret;
1140                 }
1141         }
1142
1143         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1144         if (ret) {
1145                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1146                 return ret;
1147         }
1148
1149         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1150         if (ret)
1151                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1152
1153         return ret;
1154 }
1155
1156 static int
1157 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1158 {
1159         struct hns3_adapter *hns = dev->data->dev_private;
1160         struct rte_eth_dev_data *data = dev->data;
1161         struct rte_eth_txmode *txmode;
1162         struct hns3_hw *hw = &hns->hw;
1163         int mask;
1164         int ret;
1165
1166         txmode = &data->dev_conf.txmode;
1167         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1168                 hns3_warn(hw,
1169                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1170                           "configuration is not supported! Ignore these two "
1171                           "parameters: hw_vlan_reject_tagged(%u), "
1172                           "hw_vlan_reject_untagged(%u)",
1173                           txmode->hw_vlan_reject_tagged,
1174                           txmode->hw_vlan_reject_untagged);
1175
1176         /* Apply vlan offload setting */
1177         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1178         ret = hns3_vlan_offload_set(dev, mask);
1179         if (ret) {
1180                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1181                          ret);
1182                 return ret;
1183         }
1184
1185         /*
1186          * If pvid config is not set in rte_eth_conf, driver needn't to set
1187          * VLAN pvid related configuration to hardware.
1188          */
1189         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1190                 return 0;
1191
1192         /* Apply pvid setting */
1193         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1194                                  txmode->hw_vlan_insert_pvid);
1195         if (ret)
1196                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1197                          txmode->pvid, ret);
1198
1199         return ret;
1200 }
1201
1202 static int
1203 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1204                 unsigned int tso_mss_max)
1205 {
1206         struct hns3_cfg_tso_status_cmd *req;
1207         struct hns3_cmd_desc desc;
1208         uint16_t tso_mss;
1209
1210         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1211
1212         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1213
1214         tso_mss = 0;
1215         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1216                        tso_mss_min);
1217         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1218
1219         tso_mss = 0;
1220         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1221                        tso_mss_max);
1222         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1223
1224         return hns3_cmd_send(hw, &desc, 1);
1225 }
1226
1227 static int
1228 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1229                    uint16_t *allocated_size, bool is_alloc)
1230 {
1231         struct hns3_umv_spc_alc_cmd *req;
1232         struct hns3_cmd_desc desc;
1233         int ret;
1234
1235         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1236         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1237         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1238         req->space_size = rte_cpu_to_le_32(space_size);
1239
1240         ret = hns3_cmd_send(hw, &desc, 1);
1241         if (ret) {
1242                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1243                              is_alloc ? "allocate" : "free", ret);
1244                 return ret;
1245         }
1246
1247         if (is_alloc && allocated_size)
1248                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1249
1250         return 0;
1251 }
1252
1253 static int
1254 hns3_init_umv_space(struct hns3_hw *hw)
1255 {
1256         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1257         struct hns3_pf *pf = &hns->pf;
1258         uint16_t allocated_size = 0;
1259         int ret;
1260
1261         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1262                                  true);
1263         if (ret)
1264                 return ret;
1265
1266         if (allocated_size < pf->wanted_umv_size)
1267                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1268                              pf->wanted_umv_size, allocated_size);
1269
1270         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1271                                                 pf->wanted_umv_size;
1272         pf->used_umv_size = 0;
1273         return 0;
1274 }
1275
1276 static int
1277 hns3_uninit_umv_space(struct hns3_hw *hw)
1278 {
1279         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1280         struct hns3_pf *pf = &hns->pf;
1281         int ret;
1282
1283         if (pf->max_umv_size == 0)
1284                 return 0;
1285
1286         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1287         if (ret)
1288                 return ret;
1289
1290         pf->max_umv_size = 0;
1291
1292         return 0;
1293 }
1294
1295 static bool
1296 hns3_is_umv_space_full(struct hns3_hw *hw)
1297 {
1298         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1299         struct hns3_pf *pf = &hns->pf;
1300         bool is_full;
1301
1302         is_full = (pf->used_umv_size >= pf->max_umv_size);
1303
1304         return is_full;
1305 }
1306
1307 static void
1308 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1309 {
1310         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1311         struct hns3_pf *pf = &hns->pf;
1312
1313         if (is_free) {
1314                 if (pf->used_umv_size > 0)
1315                         pf->used_umv_size--;
1316         } else
1317                 pf->used_umv_size++;
1318 }
1319
1320 static void
1321 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1322                       const uint8_t *addr, bool is_mc)
1323 {
1324         const unsigned char *mac_addr = addr;
1325         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1326                             ((uint32_t)mac_addr[2] << 16) |
1327                             ((uint32_t)mac_addr[1] << 8) |
1328                             (uint32_t)mac_addr[0];
1329         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1330
1331         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1332         if (is_mc) {
1333                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1334                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1335                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1336         }
1337
1338         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1339         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1340 }
1341
1342 static int
1343 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1344                              uint8_t resp_code,
1345                              enum hns3_mac_vlan_tbl_opcode op)
1346 {
1347         if (cmdq_resp) {
1348                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1349                          cmdq_resp);
1350                 return -EIO;
1351         }
1352
1353         if (op == HNS3_MAC_VLAN_ADD) {
1354                 if (resp_code == 0 || resp_code == 1) {
1355                         return 0;
1356                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1357                         hns3_err(hw, "add mac addr failed for uc_overflow");
1358                         return -ENOSPC;
1359                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1360                         hns3_err(hw, "add mac addr failed for mc_overflow");
1361                         return -ENOSPC;
1362                 }
1363
1364                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1365                          resp_code);
1366                 return -EIO;
1367         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1368                 if (resp_code == 0) {
1369                         return 0;
1370                 } else if (resp_code == 1) {
1371                         hns3_dbg(hw, "remove mac addr failed for miss");
1372                         return -ENOENT;
1373                 }
1374
1375                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1376                          resp_code);
1377                 return -EIO;
1378         } else if (op == HNS3_MAC_VLAN_LKUP) {
1379                 if (resp_code == 0) {
1380                         return 0;
1381                 } else if (resp_code == 1) {
1382                         hns3_dbg(hw, "lookup mac addr failed for miss");
1383                         return -ENOENT;
1384                 }
1385
1386                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1387                          resp_code);
1388                 return -EIO;
1389         }
1390
1391         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1392                  op);
1393
1394         return -EINVAL;
1395 }
1396
1397 static int
1398 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1399                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1400                          struct hns3_cmd_desc *desc, bool is_mc)
1401 {
1402         uint8_t resp_code;
1403         uint16_t retval;
1404         int ret;
1405
1406         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1407         if (is_mc) {
1408                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1409                 memcpy(desc[0].data, req,
1410                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1411                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1412                                           true);
1413                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1414                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1415                                           true);
1416                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1417         } else {
1418                 memcpy(desc[0].data, req,
1419                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1420                 ret = hns3_cmd_send(hw, desc, 1);
1421         }
1422         if (ret) {
1423                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1424                          ret);
1425                 return ret;
1426         }
1427         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1428         retval = rte_le_to_cpu_16(desc[0].retval);
1429
1430         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1431                                             HNS3_MAC_VLAN_LKUP);
1432 }
1433
1434 static int
1435 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1436                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1437                       struct hns3_cmd_desc *mc_desc)
1438 {
1439         uint8_t resp_code;
1440         uint16_t retval;
1441         int cfg_status;
1442         int ret;
1443
1444         if (mc_desc == NULL) {
1445                 struct hns3_cmd_desc desc;
1446
1447                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1448                 memcpy(desc.data, req,
1449                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1450                 ret = hns3_cmd_send(hw, &desc, 1);
1451                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1452                 retval = rte_le_to_cpu_16(desc.retval);
1453
1454                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1455                                                           HNS3_MAC_VLAN_ADD);
1456         } else {
1457                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1458                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1459                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1460                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1461                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1462                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1463                 memcpy(mc_desc[0].data, req,
1464                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1465                 mc_desc[0].retval = 0;
1466                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1467                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1468                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1469
1470                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1471                                                           HNS3_MAC_VLAN_ADD);
1472         }
1473
1474         if (ret) {
1475                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1476                 return ret;
1477         }
1478
1479         return cfg_status;
1480 }
1481
1482 static int
1483 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1484                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1485 {
1486         struct hns3_cmd_desc desc;
1487         uint8_t resp_code;
1488         uint16_t retval;
1489         int ret;
1490
1491         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1492
1493         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1494
1495         ret = hns3_cmd_send(hw, &desc, 1);
1496         if (ret) {
1497                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1498                 return ret;
1499         }
1500         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1501         retval = rte_le_to_cpu_16(desc.retval);
1502
1503         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1504                                             HNS3_MAC_VLAN_REMOVE);
1505 }
1506
1507 static int
1508 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1509 {
1510         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1511         struct hns3_mac_vlan_tbl_entry_cmd req;
1512         struct hns3_pf *pf = &hns->pf;
1513         struct hns3_cmd_desc desc[3];
1514         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1515         uint16_t egress_port = 0;
1516         uint8_t vf_id;
1517         int ret;
1518
1519         /* check if mac addr is valid */
1520         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1521                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1522                                       mac_addr);
1523                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1524                          mac_str);
1525                 return -EINVAL;
1526         }
1527
1528         memset(&req, 0, sizeof(req));
1529
1530         /*
1531          * In current version VF is not supported when PF is driven by DPDK
1532          * driver, just need to configure parameters for PF vport.
1533          */
1534         vf_id = HNS3_PF_FUNC_ID;
1535         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1536                        HNS3_MAC_EPORT_VFID_S, vf_id);
1537
1538         req.egress_port = rte_cpu_to_le_16(egress_port);
1539
1540         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1541
1542         /*
1543          * Lookup the mac address in the mac_vlan table, and add
1544          * it if the entry is inexistent. Repeated unicast entry
1545          * is not allowed in the mac vlan table.
1546          */
1547         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1548         if (ret == -ENOENT) {
1549                 if (!hns3_is_umv_space_full(hw)) {
1550                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1551                         if (!ret)
1552                                 hns3_update_umv_space(hw, false);
1553                         return ret;
1554                 }
1555
1556                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1557
1558                 return -ENOSPC;
1559         }
1560
1561         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1562
1563         /* check if we just hit the duplicate */
1564         if (ret == 0) {
1565                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1566                 return 0;
1567         }
1568
1569         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1570                  mac_str);
1571
1572         return ret;
1573 }
1574
1575 static int
1576 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1577 {
1578         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1579         struct rte_ether_addr *addr;
1580         int ret;
1581         int i;
1582
1583         for (i = 0; i < hw->mc_addrs_num; i++) {
1584                 addr = &hw->mc_addrs[i];
1585                 /* Check if there are duplicate addresses */
1586                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1587                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1588                                               addr);
1589                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1590                                  "(%s) is added by the set_mc_mac_addr_list "
1591                                  "API", mac_str);
1592                         return -EINVAL;
1593                 }
1594         }
1595
1596         ret = hns3_add_mc_addr(hw, mac_addr);
1597         if (ret) {
1598                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                       mac_addr);
1600                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1601                          mac_str, ret);
1602         }
1603         return ret;
1604 }
1605
1606 static int
1607 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1608 {
1609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610         int ret;
1611
1612         ret = hns3_remove_mc_addr(hw, mac_addr);
1613         if (ret) {
1614                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1615                                       mac_addr);
1616                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1617                          mac_str, ret);
1618         }
1619         return ret;
1620 }
1621
1622 static int
1623 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1624                   uint32_t idx, __rte_unused uint32_t pool)
1625 {
1626         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1627         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1628         int ret;
1629
1630         rte_spinlock_lock(&hw->lock);
1631
1632         /*
1633          * In hns3 network engine adding UC and MC mac address with different
1634          * commands with firmware. We need to determine whether the input
1635          * address is a UC or a MC address to call different commands.
1636          * By the way, it is recommended calling the API function named
1637          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1638          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1639          * may affect the specifications of UC mac addresses.
1640          */
1641         if (rte_is_multicast_ether_addr(mac_addr))
1642                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1643         else
1644                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1645
1646         if (ret) {
1647                 rte_spinlock_unlock(&hw->lock);
1648                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1649                                       mac_addr);
1650                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1651                          ret);
1652                 return ret;
1653         }
1654
1655         if (idx == 0)
1656                 hw->mac.default_addr_setted = true;
1657         rte_spinlock_unlock(&hw->lock);
1658
1659         return ret;
1660 }
1661
1662 static int
1663 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1664 {
1665         struct hns3_mac_vlan_tbl_entry_cmd req;
1666         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1667         int ret;
1668
1669         /* check if mac addr is valid */
1670         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1671                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1672                                       mac_addr);
1673                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1674                          mac_str);
1675                 return -EINVAL;
1676         }
1677
1678         memset(&req, 0, sizeof(req));
1679         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1680         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1681         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1682         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1683                 return 0;
1684         else if (ret == 0)
1685                 hns3_update_umv_space(hw, true);
1686
1687         return ret;
1688 }
1689
1690 static void
1691 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1692 {
1693         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694         /* index will be checked by upper level rte interface */
1695         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1696         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1697         int ret;
1698
1699         rte_spinlock_lock(&hw->lock);
1700
1701         if (rte_is_multicast_ether_addr(mac_addr))
1702                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1703         else
1704                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1705         rte_spinlock_unlock(&hw->lock);
1706         if (ret) {
1707                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1708                                       mac_addr);
1709                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1710                          ret);
1711         }
1712 }
1713
1714 static int
1715 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1716                           struct rte_ether_addr *mac_addr)
1717 {
1718         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         struct rte_ether_addr *oaddr;
1720         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1721         bool default_addr_setted;
1722         bool rm_succes = false;
1723         int ret, ret_val;
1724
1725         /*
1726          * It has been guaranteed that input parameter named mac_addr is valid
1727          * address in the rte layer of DPDK framework.
1728          */
1729         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1730         default_addr_setted = hw->mac.default_addr_setted;
1731         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1732                 return 0;
1733
1734         rte_spinlock_lock(&hw->lock);
1735         if (default_addr_setted) {
1736                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1737                 if (ret) {
1738                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1739                                               oaddr);
1740                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1741                                   mac_str, ret);
1742                         rm_succes = false;
1743                 } else
1744                         rm_succes = true;
1745         }
1746
1747         ret = hns3_add_uc_addr_common(hw, mac_addr);
1748         if (ret) {
1749                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1750                                       mac_addr);
1751                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1752                 goto err_add_uc_addr;
1753         }
1754
1755         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1756         if (ret) {
1757                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1758                 goto err_pause_addr_cfg;
1759         }
1760
1761         rte_ether_addr_copy(mac_addr,
1762                             (struct rte_ether_addr *)hw->mac.mac_addr);
1763         hw->mac.default_addr_setted = true;
1764         rte_spinlock_unlock(&hw->lock);
1765
1766         return 0;
1767
1768 err_pause_addr_cfg:
1769         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1770         if (ret_val) {
1771                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1772                                       mac_addr);
1773                 hns3_warn(hw,
1774                           "Failed to roll back to del setted mac addr(%s): %d",
1775                           mac_str, ret_val);
1776         }
1777
1778 err_add_uc_addr:
1779         if (rm_succes) {
1780                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1781                 if (ret_val) {
1782                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1783                                               oaddr);
1784                         hns3_warn(hw,
1785                                   "Failed to restore old uc mac addr(%s): %d",
1786                                   mac_str, ret_val);
1787                         hw->mac.default_addr_setted = false;
1788                 }
1789         }
1790         rte_spinlock_unlock(&hw->lock);
1791
1792         return ret;
1793 }
1794
1795 static int
1796 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1797 {
1798         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1799         struct hns3_hw *hw = &hns->hw;
1800         struct rte_ether_addr *addr;
1801         int err = 0;
1802         int ret;
1803         int i;
1804
1805         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1806                 addr = &hw->data->mac_addrs[i];
1807                 if (rte_is_zero_ether_addr(addr))
1808                         continue;
1809                 if (rte_is_multicast_ether_addr(addr))
1810                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1811                               hns3_add_mc_addr(hw, addr);
1812                 else
1813                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1814                               hns3_add_uc_addr_common(hw, addr);
1815
1816                 if (ret) {
1817                         err = ret;
1818                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1819                                               addr);
1820                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1821                                  "ret = %d.", del ? "remove" : "restore",
1822                                  mac_str, i, ret);
1823                 }
1824         }
1825         return err;
1826 }
1827
1828 static void
1829 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1830 {
1831 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1832         uint8_t word_num;
1833         uint8_t bit_num;
1834
1835         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1836                 word_num = vfid / 32;
1837                 bit_num = vfid % 32;
1838                 if (clr)
1839                         desc[1].data[word_num] &=
1840                             rte_cpu_to_le_32(~(1UL << bit_num));
1841                 else
1842                         desc[1].data[word_num] |=
1843                             rte_cpu_to_le_32(1UL << bit_num);
1844         } else {
1845                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1846                 bit_num = vfid % 32;
1847                 if (clr)
1848                         desc[2].data[word_num] &=
1849                             rte_cpu_to_le_32(~(1UL << bit_num));
1850                 else
1851                         desc[2].data[word_num] |=
1852                             rte_cpu_to_le_32(1UL << bit_num);
1853         }
1854 }
1855
1856 static int
1857 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1858 {
1859         struct hns3_mac_vlan_tbl_entry_cmd req;
1860         struct hns3_cmd_desc desc[3];
1861         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1862         uint8_t vf_id;
1863         int ret;
1864
1865         /* Check if mac addr is valid */
1866         if (!rte_is_multicast_ether_addr(mac_addr)) {
1867                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1868                                       mac_addr);
1869                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1870                          mac_str);
1871                 return -EINVAL;
1872         }
1873
1874         memset(&req, 0, sizeof(req));
1875         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1876         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1877         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1878         if (ret) {
1879                 /* This mac addr do not exist, add new entry for it */
1880                 memset(desc[0].data, 0, sizeof(desc[0].data));
1881                 memset(desc[1].data, 0, sizeof(desc[0].data));
1882                 memset(desc[2].data, 0, sizeof(desc[0].data));
1883         }
1884
1885         /*
1886          * In current version VF is not supported when PF is driven by DPDK
1887          * driver, just need to configure parameters for PF vport.
1888          */
1889         vf_id = HNS3_PF_FUNC_ID;
1890         hns3_update_desc_vfid(desc, vf_id, false);
1891         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1892         if (ret) {
1893                 if (ret == -ENOSPC)
1894                         hns3_err(hw, "mc mac vlan table is full");
1895                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1896                                       mac_addr);
1897                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1898         }
1899
1900         return ret;
1901 }
1902
1903 static int
1904 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1905 {
1906         struct hns3_mac_vlan_tbl_entry_cmd req;
1907         struct hns3_cmd_desc desc[3];
1908         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1909         uint8_t vf_id;
1910         int ret;
1911
1912         /* Check if mac addr is valid */
1913         if (!rte_is_multicast_ether_addr(mac_addr)) {
1914                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1915                                       mac_addr);
1916                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1917                          mac_str);
1918                 return -EINVAL;
1919         }
1920
1921         memset(&req, 0, sizeof(req));
1922         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1923         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1924         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1925         if (ret == 0) {
1926                 /*
1927                  * This mac addr exist, remove this handle's VFID for it.
1928                  * In current version VF is not supported when PF is driven by
1929                  * DPDK driver, just need to configure parameters for PF vport.
1930                  */
1931                 vf_id = HNS3_PF_FUNC_ID;
1932                 hns3_update_desc_vfid(desc, vf_id, true);
1933
1934                 /* All the vfid is zero, so need to delete this entry */
1935                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1936         } else if (ret == -ENOENT) {
1937                 /* This mac addr doesn't exist. */
1938                 return 0;
1939         }
1940
1941         if (ret) {
1942                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1943                                       mac_addr);
1944                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1945         }
1946
1947         return ret;
1948 }
1949
1950 static int
1951 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1952                            struct rte_ether_addr *mc_addr_set,
1953                            uint32_t nb_mc_addr)
1954 {
1955         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1956         struct rte_ether_addr *addr;
1957         uint32_t i;
1958         uint32_t j;
1959
1960         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1961                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1962                          "invalid. valid range: 0~%d",
1963                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1964                 return -EINVAL;
1965         }
1966
1967         /* Check if input mac addresses are valid */
1968         for (i = 0; i < nb_mc_addr; i++) {
1969                 addr = &mc_addr_set[i];
1970                 if (!rte_is_multicast_ether_addr(addr)) {
1971                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1972                                               addr);
1973                         hns3_err(hw,
1974                                  "failed to set mc mac addr, addr(%s) invalid.",
1975                                  mac_str);
1976                         return -EINVAL;
1977                 }
1978
1979                 /* Check if there are duplicate addresses */
1980                 for (j = i + 1; j < nb_mc_addr; j++) {
1981                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1982                                 hns3_ether_format_addr(mac_str,
1983                                                       RTE_ETHER_ADDR_FMT_SIZE,
1984                                                       addr);
1985                                 hns3_err(hw, "failed to set mc mac addr, "
1986                                          "addrs invalid. two same addrs(%s).",
1987                                          mac_str);
1988                                 return -EINVAL;
1989                         }
1990                 }
1991
1992                 /*
1993                  * Check if there are duplicate addresses between mac_addrs
1994                  * and mc_addr_set
1995                  */
1996                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1997                         if (rte_is_same_ether_addr(addr,
1998                                                    &hw->data->mac_addrs[j])) {
1999                                 hns3_ether_format_addr(mac_str,
2000                                                       RTE_ETHER_ADDR_FMT_SIZE,
2001                                                       addr);
2002                                 hns3_err(hw, "failed to set mc mac addr, "
2003                                          "addrs invalid. addrs(%s) has already "
2004                                          "configured in mac_addr add API",
2005                                          mac_str);
2006                                 return -EINVAL;
2007                         }
2008                 }
2009         }
2010
2011         return 0;
2012 }
2013
2014 static void
2015 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2016                            struct rte_ether_addr *mc_addr_set,
2017                            int mc_addr_num,
2018                            struct rte_ether_addr *reserved_addr_list,
2019                            int *reserved_addr_num,
2020                            struct rte_ether_addr *add_addr_list,
2021                            int *add_addr_num,
2022                            struct rte_ether_addr *rm_addr_list,
2023                            int *rm_addr_num)
2024 {
2025         struct rte_ether_addr *addr;
2026         int current_addr_num;
2027         int reserved_num = 0;
2028         int add_num = 0;
2029         int rm_num = 0;
2030         int num;
2031         int i;
2032         int j;
2033         bool same_addr;
2034
2035         /* Calculate the mc mac address list that should be removed */
2036         current_addr_num = hw->mc_addrs_num;
2037         for (i = 0; i < current_addr_num; i++) {
2038                 addr = &hw->mc_addrs[i];
2039                 same_addr = false;
2040                 for (j = 0; j < mc_addr_num; j++) {
2041                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2042                                 same_addr = true;
2043                                 break;
2044                         }
2045                 }
2046
2047                 if (!same_addr) {
2048                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2049                         rm_num++;
2050                 } else {
2051                         rte_ether_addr_copy(addr,
2052                                             &reserved_addr_list[reserved_num]);
2053                         reserved_num++;
2054                 }
2055         }
2056
2057         /* Calculate the mc mac address list that should be added */
2058         for (i = 0; i < mc_addr_num; i++) {
2059                 addr = &mc_addr_set[i];
2060                 same_addr = false;
2061                 for (j = 0; j < current_addr_num; j++) {
2062                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2063                                 same_addr = true;
2064                                 break;
2065                         }
2066                 }
2067
2068                 if (!same_addr) {
2069                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2070                         add_num++;
2071                 }
2072         }
2073
2074         /* Reorder the mc mac address list maintained by driver */
2075         for (i = 0; i < reserved_num; i++)
2076                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2077
2078         for (i = 0; i < rm_num; i++) {
2079                 num = reserved_num + i;
2080                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2081         }
2082
2083         *reserved_addr_num = reserved_num;
2084         *add_addr_num = add_num;
2085         *rm_addr_num = rm_num;
2086 }
2087
2088 static int
2089 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2090                           struct rte_ether_addr *mc_addr_set,
2091                           uint32_t nb_mc_addr)
2092 {
2093         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2094         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2095         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2096         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2097         struct rte_ether_addr *addr;
2098         int reserved_addr_num;
2099         int add_addr_num;
2100         int rm_addr_num;
2101         int mc_addr_num;
2102         int num;
2103         int ret;
2104         int i;
2105
2106         /* Check if input parameters are valid */
2107         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2108         if (ret)
2109                 return ret;
2110
2111         rte_spinlock_lock(&hw->lock);
2112
2113         /*
2114          * Calculate the mc mac address lists those should be removed and be
2115          * added, Reorder the mc mac address list maintained by driver.
2116          */
2117         mc_addr_num = (int)nb_mc_addr;
2118         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2119                                    reserved_addr_list, &reserved_addr_num,
2120                                    add_addr_list, &add_addr_num,
2121                                    rm_addr_list, &rm_addr_num);
2122
2123         /* Remove mc mac addresses */
2124         for (i = 0; i < rm_addr_num; i++) {
2125                 num = rm_addr_num - i - 1;
2126                 addr = &rm_addr_list[num];
2127                 ret = hns3_remove_mc_addr(hw, addr);
2128                 if (ret) {
2129                         rte_spinlock_unlock(&hw->lock);
2130                         return ret;
2131                 }
2132                 hw->mc_addrs_num--;
2133         }
2134
2135         /* Add mc mac addresses */
2136         for (i = 0; i < add_addr_num; i++) {
2137                 addr = &add_addr_list[i];
2138                 ret = hns3_add_mc_addr(hw, addr);
2139                 if (ret) {
2140                         rte_spinlock_unlock(&hw->lock);
2141                         return ret;
2142                 }
2143
2144                 num = reserved_addr_num + i;
2145                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2146                 hw->mc_addrs_num++;
2147         }
2148         rte_spinlock_unlock(&hw->lock);
2149
2150         return 0;
2151 }
2152
2153 static int
2154 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2155 {
2156         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2157         struct hns3_hw *hw = &hns->hw;
2158         struct rte_ether_addr *addr;
2159         int err = 0;
2160         int ret;
2161         int i;
2162
2163         for (i = 0; i < hw->mc_addrs_num; i++) {
2164                 addr = &hw->mc_addrs[i];
2165                 if (!rte_is_multicast_ether_addr(addr))
2166                         continue;
2167                 if (del)
2168                         ret = hns3_remove_mc_addr(hw, addr);
2169                 else
2170                         ret = hns3_add_mc_addr(hw, addr);
2171                 if (ret) {
2172                         err = ret;
2173                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2174                                               addr);
2175                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2176                                  del ? "Remove" : "Restore", mac_str, ret);
2177                 }
2178         }
2179         return err;
2180 }
2181
2182 static int
2183 hns3_check_mq_mode(struct rte_eth_dev *dev)
2184 {
2185         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2186         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2187         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2189         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2190         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2191         uint8_t num_tc;
2192         int max_tc = 0;
2193         int i;
2194
2195         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2196         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2197
2198         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2199                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2200                          "rx_mq_mode = %d", rx_mq_mode);
2201                 return -EINVAL;
2202         }
2203
2204         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2205             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2206                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2207                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2208                          rx_mq_mode, tx_mq_mode);
2209                 return -EINVAL;
2210         }
2211
2212         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2213                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2214                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2215                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2216                         return -EINVAL;
2217                 }
2218
2219                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2220                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2221                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2222                                  "nb_tcs(%d) != %d or %d in rx direction.",
2223                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2224                         return -EINVAL;
2225                 }
2226
2227                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2228                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2229                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2230                         return -EINVAL;
2231                 }
2232
2233                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2234                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2235                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2236                                          "is not equal to one in tx direction.",
2237                                          i, dcb_rx_conf->dcb_tc[i]);
2238                                 return -EINVAL;
2239                         }
2240                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2241                                 max_tc = dcb_rx_conf->dcb_tc[i];
2242                 }
2243
2244                 num_tc = max_tc + 1;
2245                 if (num_tc > dcb_rx_conf->nb_tcs) {
2246                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2247                                  num_tc, dcb_rx_conf->nb_tcs);
2248                         return -EINVAL;
2249                 }
2250         }
2251
2252         return 0;
2253 }
2254
2255 static int
2256 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2257 {
2258         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259
2260         if (!hns3_dev_dcb_supported(hw)) {
2261                 hns3_err(hw, "this port does not support dcb configurations.");
2262                 return -EOPNOTSUPP;
2263         }
2264
2265         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2266                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2267                 return -EOPNOTSUPP;
2268         }
2269
2270         /* Check multiple queue mode */
2271         return hns3_check_mq_mode(dev);
2272 }
2273
2274 static int
2275 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2276                            enum hns3_ring_type queue_type, uint16_t queue_id)
2277 {
2278         struct hns3_cmd_desc desc;
2279         struct hns3_ctrl_vector_chain_cmd *req =
2280                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2281         enum hns3_cmd_status status;
2282         enum hns3_opcode_type op;
2283         uint16_t tqp_type_and_id = 0;
2284         uint16_t type;
2285         uint16_t gl;
2286
2287         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2288         hns3_cmd_setup_basic_desc(&desc, op, false);
2289         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2290                                               HNS3_TQP_INT_ID_L_S);
2291         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2292                                               HNS3_TQP_INT_ID_H_S);
2293
2294         if (queue_type == HNS3_RING_TYPE_RX)
2295                 gl = HNS3_RING_GL_RX;
2296         else
2297                 gl = HNS3_RING_GL_TX;
2298
2299         type = queue_type;
2300
2301         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2302                        type);
2303         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2304         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2305                        gl);
2306         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2307         req->int_cause_num = 1;
2308         status = hns3_cmd_send(hw, &desc, 1);
2309         if (status) {
2310                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2311                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2312                 return status;
2313         }
2314
2315         return 0;
2316 }
2317
2318 static int
2319 hns3_init_ring_with_vector(struct hns3_hw *hw)
2320 {
2321         uint16_t vec;
2322         int ret;
2323         int i;
2324
2325         /*
2326          * In hns3 network engine, vector 0 is always the misc interrupt of this
2327          * function, vector 1~N can be used respectively for the queues of the
2328          * function. Tx and Rx queues with the same number share the interrupt
2329          * vector. In the initialization clearing the all hardware mapping
2330          * relationship configurations between queues and interrupt vectors is
2331          * needed, so some error caused by the residual configurations, such as
2332          * the unexpected Tx interrupt, can be avoid.
2333          */
2334         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2335         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2336                 vec = vec - 1; /* the last interrupt is reserved */
2337         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2338         for (i = 0; i < hw->intr_tqps_num; i++) {
2339                 /*
2340                  * Set gap limiter/rate limiter/quanity limiter algorithm
2341                  * configuration for interrupt coalesce of queue's interrupt.
2342                  */
2343                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2344                                        HNS3_TQP_INTR_GL_DEFAULT);
2345                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2346                                        HNS3_TQP_INTR_GL_DEFAULT);
2347                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2348                 /*
2349                  * QL(quantity limiter) is not used currently, just set 0 to
2350                  * close it.
2351                  */
2352                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2353
2354                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2355                                                  HNS3_RING_TYPE_TX, i);
2356                 if (ret) {
2357                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2358                                           "vector: %u, ret=%d", i, vec, ret);
2359                         return ret;
2360                 }
2361
2362                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2363                                                  HNS3_RING_TYPE_RX, i);
2364                 if (ret) {
2365                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2366                                           "vector: %u, ret=%d", i, vec, ret);
2367                         return ret;
2368                 }
2369         }
2370
2371         return 0;
2372 }
2373
2374 static int
2375 hns3_dev_configure(struct rte_eth_dev *dev)
2376 {
2377         struct hns3_adapter *hns = dev->data->dev_private;
2378         struct rte_eth_conf *conf = &dev->data->dev_conf;
2379         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2380         struct hns3_hw *hw = &hns->hw;
2381         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2382         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2383         struct rte_eth_rss_conf rss_conf;
2384         uint32_t max_rx_pkt_len;
2385         uint16_t mtu;
2386         bool gro_en;
2387         int ret;
2388
2389         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2390
2391         /*
2392          * Some versions of hardware network engine does not support
2393          * individually enable/disable/reset the Tx or Rx queue. These devices
2394          * must enable/disable/reset Tx and Rx queues at the same time. When the
2395          * numbers of Tx queues allocated by upper applications are not equal to
2396          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2397          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2398          * work as usual. But these fake queues are imperceptible, and can not
2399          * be used by upper applications.
2400          */
2401         if (!hns3_dev_indep_txrx_supported(hw)) {
2402                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2403                 if (ret) {
2404                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2405                                  ret);
2406                         return ret;
2407                 }
2408         }
2409
2410         hw->adapter_state = HNS3_NIC_CONFIGURING;
2411         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2412                 hns3_err(hw, "setting link speed/duplex not supported");
2413                 ret = -EINVAL;
2414                 goto cfg_err;
2415         }
2416
2417         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2418                 ret = hns3_check_dcb_cfg(dev);
2419                 if (ret)
2420                         goto cfg_err;
2421         }
2422
2423         /* When RSS is not configured, redirect the packet queue 0 */
2424         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2425                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2426                 rss_conf = conf->rx_adv_conf.rss_conf;
2427                 hw->rss_dis_flag = false;
2428                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2429                 if (ret)
2430                         goto cfg_err;
2431         }
2432
2433         /*
2434          * If jumbo frames are enabled, MTU needs to be refreshed
2435          * according to the maximum RX packet length.
2436          */
2437         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2438                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2439                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2440                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2441                         hns3_err(hw, "maximum Rx packet length must be greater "
2442                                  "than %u and less than %u when jumbo frame enabled.",
2443                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2444                                  (uint16_t)HNS3_MAX_FRAME_LEN);
2445                         ret = -EINVAL;
2446                         goto cfg_err;
2447                 }
2448
2449                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2450                 ret = hns3_dev_mtu_set(dev, mtu);
2451                 if (ret)
2452                         goto cfg_err;
2453                 dev->data->mtu = mtu;
2454         }
2455
2456         ret = hns3_dev_configure_vlan(dev);
2457         if (ret)
2458                 goto cfg_err;
2459
2460         /* config hardware GRO */
2461         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2462         ret = hns3_config_gro(hw, gro_en);
2463         if (ret)
2464                 goto cfg_err;
2465
2466         hns->rx_simple_allowed = true;
2467         hns->rx_vec_allowed = true;
2468         hns->tx_simple_allowed = true;
2469         hns->tx_vec_allowed = true;
2470
2471         hns3_init_rx_ptype_tble(dev);
2472         hw->adapter_state = HNS3_NIC_CONFIGURED;
2473
2474         return 0;
2475
2476 cfg_err:
2477         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2478         hw->adapter_state = HNS3_NIC_INITIALIZED;
2479
2480         return ret;
2481 }
2482
2483 static int
2484 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2485 {
2486         struct hns3_config_max_frm_size_cmd *req;
2487         struct hns3_cmd_desc desc;
2488
2489         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2490
2491         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2492         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2493         req->min_frm_size = RTE_ETHER_MIN_LEN;
2494
2495         return hns3_cmd_send(hw, &desc, 1);
2496 }
2497
2498 static int
2499 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2500 {
2501         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2502         uint16_t original_mps = hns->pf.mps;
2503         int err;
2504         int ret;
2505
2506         ret = hns3_set_mac_mtu(hw, mps);
2507         if (ret) {
2508                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2509                 return ret;
2510         }
2511
2512         hns->pf.mps = mps;
2513         ret = hns3_buffer_alloc(hw);
2514         if (ret) {
2515                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2516                 goto rollback;
2517         }
2518
2519         return 0;
2520
2521 rollback:
2522         err = hns3_set_mac_mtu(hw, original_mps);
2523         if (err) {
2524                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2525                 return ret;
2526         }
2527         hns->pf.mps = original_mps;
2528
2529         return ret;
2530 }
2531
2532 static int
2533 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2534 {
2535         struct hns3_adapter *hns = dev->data->dev_private;
2536         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2537         struct hns3_hw *hw = &hns->hw;
2538         bool is_jumbo_frame;
2539         int ret;
2540
2541         if (dev->data->dev_started) {
2542                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2543                          "before configuration", dev->data->port_id);
2544                 return -EBUSY;
2545         }
2546
2547         rte_spinlock_lock(&hw->lock);
2548         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2549         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2550
2551         /*
2552          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2553          * assign to "uint16_t" type variable.
2554          */
2555         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2556         if (ret) {
2557                 rte_spinlock_unlock(&hw->lock);
2558                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2559                          dev->data->port_id, mtu, ret);
2560                 return ret;
2561         }
2562
2563         if (is_jumbo_frame)
2564                 dev->data->dev_conf.rxmode.offloads |=
2565                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2566         else
2567                 dev->data->dev_conf.rxmode.offloads &=
2568                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2569         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2570         rte_spinlock_unlock(&hw->lock);
2571
2572         return 0;
2573 }
2574
2575 int
2576 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2577 {
2578         struct hns3_adapter *hns = eth_dev->data->dev_private;
2579         struct hns3_hw *hw = &hns->hw;
2580         uint16_t queue_num = hw->tqps_num;
2581
2582         /*
2583          * In interrupt mode, 'max_rx_queues' is set based on the number of
2584          * MSI-X interrupt resources of the hardware.
2585          */
2586         if (hw->data->dev_conf.intr_conf.rxq == 1)
2587                 queue_num = hw->intr_tqps_num;
2588
2589         info->max_rx_queues = queue_num;
2590         info->max_tx_queues = hw->tqps_num;
2591         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2592         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2593         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2594         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2595         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2596         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2597                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2598                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2599                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2600                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2601                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2602                                  DEV_RX_OFFLOAD_KEEP_CRC |
2603                                  DEV_RX_OFFLOAD_SCATTER |
2604                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2605                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2606                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2607                                  DEV_RX_OFFLOAD_RSS_HASH |
2608                                  DEV_RX_OFFLOAD_TCP_LRO);
2609         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2610                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2611                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2612                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2613                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2614                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2615                                  DEV_TX_OFFLOAD_TCP_TSO |
2616                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2617                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2618                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2619                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2620                                  hns3_txvlan_cap_get(hw));
2621
2622         if (hns3_dev_indep_txrx_supported(hw))
2623                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2624                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2625
2626         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2627                 .nb_max = HNS3_MAX_RING_DESC,
2628                 .nb_min = HNS3_MIN_RING_DESC,
2629                 .nb_align = HNS3_ALIGN_RING_DESC,
2630         };
2631
2632         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2633                 .nb_max = HNS3_MAX_RING_DESC,
2634                 .nb_min = HNS3_MIN_RING_DESC,
2635                 .nb_align = HNS3_ALIGN_RING_DESC,
2636                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2637                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2638         };
2639
2640         info->default_rxconf = (struct rte_eth_rxconf) {
2641                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2642                 /*
2643                  * If there are no available Rx buffer descriptors, incoming
2644                  * packets are always dropped by hardware based on hns3 network
2645                  * engine.
2646                  */
2647                 .rx_drop_en = 1,
2648                 .offloads = 0,
2649         };
2650         info->default_txconf = (struct rte_eth_txconf) {
2651                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2652                 .offloads = 0,
2653         };
2654
2655         info->vmdq_queue_num = 0;
2656
2657         info->reta_size = hw->rss_ind_tbl_size;
2658         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2659         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2660
2661         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2662         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2663         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2664         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2665         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2666         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2667
2668         return 0;
2669 }
2670
2671 static int
2672 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2673                     size_t fw_size)
2674 {
2675         struct hns3_adapter *hns = eth_dev->data->dev_private;
2676         struct hns3_hw *hw = &hns->hw;
2677         uint32_t version = hw->fw_version;
2678         int ret;
2679
2680         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2681                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2682                                       HNS3_FW_VERSION_BYTE3_S),
2683                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2684                                       HNS3_FW_VERSION_BYTE2_S),
2685                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2686                                       HNS3_FW_VERSION_BYTE1_S),
2687                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2688                                       HNS3_FW_VERSION_BYTE0_S));
2689         ret += 1; /* add the size of '\0' */
2690         if (fw_size < (uint32_t)ret)
2691                 return ret;
2692         else
2693                 return 0;
2694 }
2695
2696 static int
2697 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2698                      __rte_unused int wait_to_complete)
2699 {
2700         struct hns3_adapter *hns = eth_dev->data->dev_private;
2701         struct hns3_hw *hw = &hns->hw;
2702         struct hns3_mac *mac = &hw->mac;
2703         struct rte_eth_link new_link;
2704
2705         if (!hns3_is_reset_pending(hns)) {
2706                 hns3_update_link_status(hw);
2707                 hns3_update_link_info(eth_dev);
2708         }
2709
2710         memset(&new_link, 0, sizeof(new_link));
2711         switch (mac->link_speed) {
2712         case ETH_SPEED_NUM_10M:
2713         case ETH_SPEED_NUM_100M:
2714         case ETH_SPEED_NUM_1G:
2715         case ETH_SPEED_NUM_10G:
2716         case ETH_SPEED_NUM_25G:
2717         case ETH_SPEED_NUM_40G:
2718         case ETH_SPEED_NUM_50G:
2719         case ETH_SPEED_NUM_100G:
2720         case ETH_SPEED_NUM_200G:
2721                 new_link.link_speed = mac->link_speed;
2722                 break;
2723         default:
2724                 new_link.link_speed = ETH_SPEED_NUM_100M;
2725                 break;
2726         }
2727
2728         new_link.link_duplex = mac->link_duplex;
2729         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2730         new_link.link_autoneg =
2731             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2732
2733         return rte_eth_linkstatus_set(eth_dev, &new_link);
2734 }
2735
2736 static int
2737 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2738 {
2739         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2740         struct hns3_pf *pf = &hns->pf;
2741
2742         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2743                 return -EINVAL;
2744
2745         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2746
2747         return 0;
2748 }
2749
2750 static int
2751 hns3_query_function_status(struct hns3_hw *hw)
2752 {
2753 #define HNS3_QUERY_MAX_CNT              10
2754 #define HNS3_QUERY_SLEEP_MSCOEND        1
2755         struct hns3_func_status_cmd *req;
2756         struct hns3_cmd_desc desc;
2757         int timeout = 0;
2758         int ret;
2759
2760         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2761         req = (struct hns3_func_status_cmd *)desc.data;
2762
2763         do {
2764                 ret = hns3_cmd_send(hw, &desc, 1);
2765                 if (ret) {
2766                         PMD_INIT_LOG(ERR, "query function status failed %d",
2767                                      ret);
2768                         return ret;
2769                 }
2770
2771                 /* Check pf reset is done */
2772                 if (req->pf_state)
2773                         break;
2774
2775                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2776         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2777
2778         return hns3_parse_func_status(hw, req);
2779 }
2780
2781 static int
2782 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2783 {
2784         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2785         struct hns3_pf *pf = &hns->pf;
2786
2787         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2788                 /*
2789                  * The total_tqps_num obtained from firmware is maximum tqp
2790                  * numbers of this port, which should be used for PF and VFs.
2791                  * There is no need for pf to have so many tqp numbers in
2792                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2793                  * coming from config file, is assigned to maximum queue number
2794                  * for the PF of this port by user. So users can modify the
2795                  * maximum queue number of PF according to their own application
2796                  * scenarios, which is more flexible to use. In addition, many
2797                  * memories can be saved due to allocating queue statistics
2798                  * room according to the actual number of queues required. The
2799                  * maximum queue number of PF for network engine with
2800                  * revision_id greater than 0x30 is assigned by config file.
2801                  */
2802                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2803                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2804                                  "must be greater than 0.",
2805                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2806                         return -EINVAL;
2807                 }
2808
2809                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2810                                        hw->total_tqps_num);
2811         } else {
2812                 /*
2813                  * Due to the limitation on the number of PF interrupts
2814                  * available, the maximum queue number assigned to PF on
2815                  * the network engine with revision_id 0x21 is 64.
2816                  */
2817                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2818                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2819         }
2820
2821         return 0;
2822 }
2823
2824 static int
2825 hns3_query_pf_resource(struct hns3_hw *hw)
2826 {
2827         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2828         struct hns3_pf *pf = &hns->pf;
2829         struct hns3_pf_res_cmd *req;
2830         struct hns3_cmd_desc desc;
2831         int ret;
2832
2833         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2834         ret = hns3_cmd_send(hw, &desc, 1);
2835         if (ret) {
2836                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2837                 return ret;
2838         }
2839
2840         req = (struct hns3_pf_res_cmd *)desc.data;
2841         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2842                              rte_le_to_cpu_16(req->ext_tqp_num);
2843         ret = hns3_get_pf_max_tqp_num(hw);
2844         if (ret)
2845                 return ret;
2846
2847         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2848         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2849
2850         if (req->tx_buf_size)
2851                 pf->tx_buf_size =
2852                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2853         else
2854                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2855
2856         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2857
2858         if (req->dv_buf_size)
2859                 pf->dv_buf_size =
2860                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2861         else
2862                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2863
2864         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2865
2866         hw->num_msi =
2867                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2868                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2869
2870         return 0;
2871 }
2872
2873 static void
2874 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2875 {
2876         struct hns3_cfg_param_cmd *req;
2877         uint64_t mac_addr_tmp_high;
2878         uint8_t ext_rss_size_max;
2879         uint64_t mac_addr_tmp;
2880         uint32_t i;
2881
2882         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2883
2884         /* get the configuration */
2885         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2886                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2887         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2888                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2889         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2890                                            HNS3_CFG_TQP_DESC_N_M,
2891                                            HNS3_CFG_TQP_DESC_N_S);
2892
2893         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2894                                        HNS3_CFG_PHY_ADDR_M,
2895                                        HNS3_CFG_PHY_ADDR_S);
2896         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2897                                          HNS3_CFG_MEDIA_TP_M,
2898                                          HNS3_CFG_MEDIA_TP_S);
2899         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2900                                          HNS3_CFG_RX_BUF_LEN_M,
2901                                          HNS3_CFG_RX_BUF_LEN_S);
2902         /* get mac address */
2903         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2904         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2905                                            HNS3_CFG_MAC_ADDR_H_M,
2906                                            HNS3_CFG_MAC_ADDR_H_S);
2907
2908         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2909
2910         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2911                                             HNS3_CFG_DEFAULT_SPEED_M,
2912                                             HNS3_CFG_DEFAULT_SPEED_S);
2913         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2914                                            HNS3_CFG_RSS_SIZE_M,
2915                                            HNS3_CFG_RSS_SIZE_S);
2916
2917         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2918                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2919
2920         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2921         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2922
2923         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2924                                             HNS3_CFG_SPEED_ABILITY_M,
2925                                             HNS3_CFG_SPEED_ABILITY_S);
2926         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2927                                         HNS3_CFG_UMV_TBL_SPACE_M,
2928                                         HNS3_CFG_UMV_TBL_SPACE_S);
2929         if (!cfg->umv_space)
2930                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2931
2932         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2933                                                HNS3_CFG_EXT_RSS_SIZE_M,
2934                                                HNS3_CFG_EXT_RSS_SIZE_S);
2935
2936         /*
2937          * Field ext_rss_size_max obtained from firmware will be more flexible
2938          * for future changes and expansions, which is an exponent of 2, instead
2939          * of reading out directly. If this field is not zero, hns3 PF PMD
2940          * driver uses it as rss_size_max under one TC. Device, whose revision
2941          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2942          * maximum number of queues supported under a TC through this field.
2943          */
2944         if (ext_rss_size_max)
2945                 cfg->rss_size_max = 1U << ext_rss_size_max;
2946 }
2947
2948 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2949  * @hw: pointer to struct hns3_hw
2950  * @hcfg: the config structure to be getted
2951  */
2952 static int
2953 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2954 {
2955         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2956         struct hns3_cfg_param_cmd *req;
2957         uint32_t offset;
2958         uint32_t i;
2959         int ret;
2960
2961         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2962                 offset = 0;
2963                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2964                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2965                                           true);
2966                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2967                                i * HNS3_CFG_RD_LEN_BYTES);
2968                 /* Len should be divided by 4 when send to hardware */
2969                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2970                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2971                 req->offset = rte_cpu_to_le_32(offset);
2972         }
2973
2974         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2975         if (ret) {
2976                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2977                 return ret;
2978         }
2979
2980         hns3_parse_cfg(hcfg, desc);
2981
2982         return 0;
2983 }
2984
2985 static int
2986 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2987 {
2988         switch (speed_cmd) {
2989         case HNS3_CFG_SPEED_10M:
2990                 *speed = ETH_SPEED_NUM_10M;
2991                 break;
2992         case HNS3_CFG_SPEED_100M:
2993                 *speed = ETH_SPEED_NUM_100M;
2994                 break;
2995         case HNS3_CFG_SPEED_1G:
2996                 *speed = ETH_SPEED_NUM_1G;
2997                 break;
2998         case HNS3_CFG_SPEED_10G:
2999                 *speed = ETH_SPEED_NUM_10G;
3000                 break;
3001         case HNS3_CFG_SPEED_25G:
3002                 *speed = ETH_SPEED_NUM_25G;
3003                 break;
3004         case HNS3_CFG_SPEED_40G:
3005                 *speed = ETH_SPEED_NUM_40G;
3006                 break;
3007         case HNS3_CFG_SPEED_50G:
3008                 *speed = ETH_SPEED_NUM_50G;
3009                 break;
3010         case HNS3_CFG_SPEED_100G:
3011                 *speed = ETH_SPEED_NUM_100G;
3012                 break;
3013         case HNS3_CFG_SPEED_200G:
3014                 *speed = ETH_SPEED_NUM_200G;
3015                 break;
3016         default:
3017                 return -EINVAL;
3018         }
3019
3020         return 0;
3021 }
3022
3023 static void
3024 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3025 {
3026         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3027         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3028         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3029         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3030         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3031 }
3032
3033 static void
3034 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3035 {
3036         struct hns3_dev_specs_0_cmd *req0;
3037
3038         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3039
3040         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3041         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3042         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3043         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3044         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3045 }
3046
3047 static int
3048 hns3_check_dev_specifications(struct hns3_hw *hw)
3049 {
3050         if (hw->rss_ind_tbl_size == 0 ||
3051             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3052                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3053                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3054                               HNS3_RSS_IND_TBL_SIZE_MAX);
3055                 return -EINVAL;
3056         }
3057
3058         return 0;
3059 }
3060
3061 static int
3062 hns3_query_dev_specifications(struct hns3_hw *hw)
3063 {
3064         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3065         int ret;
3066         int i;
3067
3068         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3069                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3070                                           true);
3071                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3072         }
3073         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3074
3075         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3076         if (ret)
3077                 return ret;
3078
3079         hns3_parse_dev_specifications(hw, desc);
3080
3081         return hns3_check_dev_specifications(hw);
3082 }
3083
3084 static int
3085 hns3_get_capability(struct hns3_hw *hw)
3086 {
3087         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3088         struct rte_pci_device *pci_dev;
3089         struct hns3_pf *pf = &hns->pf;
3090         struct rte_eth_dev *eth_dev;
3091         uint16_t device_id;
3092         uint8_t revision;
3093         int ret;
3094
3095         eth_dev = &rte_eth_devices[hw->data->port_id];
3096         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3097         device_id = pci_dev->id.device_id;
3098
3099         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3100             device_id == HNS3_DEV_ID_50GE_RDMA ||
3101             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3102             device_id == HNS3_DEV_ID_200G_RDMA)
3103                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3104
3105         /* Get PCI revision id */
3106         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3107                                   HNS3_PCI_REVISION_ID);
3108         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3109                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3110                              ret);
3111                 return -EIO;
3112         }
3113         hw->revision = revision;
3114
3115         if (revision < PCI_REVISION_ID_HIP09_A) {
3116                 hns3_set_default_dev_specifications(hw);
3117                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3118                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3119                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3120                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3121                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3122                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3123                 hw->rss_info.ipv6_sctp_offload_supported = false;
3124                 return 0;
3125         }
3126
3127         ret = hns3_query_dev_specifications(hw);
3128         if (ret) {
3129                 PMD_INIT_LOG(ERR,
3130                              "failed to query dev specifications, ret = %d",
3131                              ret);
3132                 return ret;
3133         }
3134
3135         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3136         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3137         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3138         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3139         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3140         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3141         hw->rss_info.ipv6_sctp_offload_supported = true;
3142
3143         return 0;
3144 }
3145
3146 static int
3147 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3148 {
3149         int ret;
3150
3151         switch (media_type) {
3152         case HNS3_MEDIA_TYPE_COPPER:
3153                 if (!hns3_dev_copper_supported(hw)) {
3154                         PMD_INIT_LOG(ERR,
3155                                      "Media type is copper, not supported.");
3156                         ret = -EOPNOTSUPP;
3157                 } else {
3158                         ret = 0;
3159                 }
3160                 break;
3161         case HNS3_MEDIA_TYPE_FIBER:
3162                 ret = 0;
3163                 break;
3164         case HNS3_MEDIA_TYPE_BACKPLANE:
3165                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3166                 ret = -EOPNOTSUPP;
3167                 break;
3168         default:
3169                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3170                 ret = -EINVAL;
3171                 break;
3172         }
3173
3174         return ret;
3175 }
3176
3177 static int
3178 hns3_get_board_configuration(struct hns3_hw *hw)
3179 {
3180         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3181         struct hns3_pf *pf = &hns->pf;
3182         struct hns3_cfg cfg;
3183         int ret;
3184
3185         ret = hns3_get_board_cfg(hw, &cfg);
3186         if (ret) {
3187                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3188                 return ret;
3189         }
3190
3191         ret = hns3_check_media_type(hw, cfg.media_type);
3192         if (ret)
3193                 return ret;
3194
3195         hw->mac.media_type = cfg.media_type;
3196         hw->rss_size_max = cfg.rss_size_max;
3197         hw->rss_dis_flag = false;
3198         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3199         hw->mac.phy_addr = cfg.phy_addr;
3200         hw->mac.default_addr_setted = false;
3201         hw->num_tx_desc = cfg.tqp_desc_num;
3202         hw->num_rx_desc = cfg.tqp_desc_num;
3203         hw->dcb_info.num_pg = 1;
3204         hw->dcb_info.hw_pfc_map = 0;
3205
3206         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3207         if (ret) {
3208                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3209                              cfg.default_speed, ret);
3210                 return ret;
3211         }
3212
3213         pf->tc_max = cfg.tc_num;
3214         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3215                 PMD_INIT_LOG(WARNING,
3216                              "Get TC num(%u) from flash, set TC num to 1",
3217                              pf->tc_max);
3218                 pf->tc_max = 1;
3219         }
3220
3221         /* Dev does not support DCB */
3222         if (!hns3_dev_dcb_supported(hw)) {
3223                 pf->tc_max = 1;
3224                 pf->pfc_max = 0;
3225         } else
3226                 pf->pfc_max = pf->tc_max;
3227
3228         hw->dcb_info.num_tc = 1;
3229         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3230                                      hw->tqps_num / hw->dcb_info.num_tc);
3231         hns3_set_bit(hw->hw_tc_map, 0, 1);
3232         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3233
3234         pf->wanted_umv_size = cfg.umv_space;
3235
3236         return ret;
3237 }
3238
3239 static int
3240 hns3_get_configuration(struct hns3_hw *hw)
3241 {
3242         int ret;
3243
3244         ret = hns3_query_function_status(hw);
3245         if (ret) {
3246                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3247                 return ret;
3248         }
3249
3250         /* Get device capability */
3251         ret = hns3_get_capability(hw);
3252         if (ret) {
3253                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3254                 return ret;
3255         }
3256
3257         /* Get pf resource */
3258         ret = hns3_query_pf_resource(hw);
3259         if (ret) {
3260                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3261                 return ret;
3262         }
3263
3264         ret = hns3_get_board_configuration(hw);
3265         if (ret) {
3266                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3267                 return ret;
3268         }
3269
3270         ret = hns3_query_dev_fec_info(hw);
3271         if (ret)
3272                 PMD_INIT_LOG(ERR,
3273                              "failed to query FEC information, ret = %d", ret);
3274
3275         return ret;
3276 }
3277
3278 static int
3279 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3280                       uint16_t tqp_vid, bool is_pf)
3281 {
3282         struct hns3_tqp_map_cmd *req;
3283         struct hns3_cmd_desc desc;
3284         int ret;
3285
3286         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3287
3288         req = (struct hns3_tqp_map_cmd *)desc.data;
3289         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3290         req->tqp_vf = func_id;
3291         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3292         if (!is_pf)
3293                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3294         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3295
3296         ret = hns3_cmd_send(hw, &desc, 1);
3297         if (ret)
3298                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3299
3300         return ret;
3301 }
3302
3303 static int
3304 hns3_map_tqp(struct hns3_hw *hw)
3305 {
3306         int ret;
3307         int i;
3308
3309         /*
3310          * In current version, VF is not supported when PF is driven by DPDK
3311          * driver, so we assign total tqps_num tqps allocated to this port
3312          * to PF.
3313          */
3314         for (i = 0; i < hw->total_tqps_num; i++) {
3315                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3316                 if (ret)
3317                         return ret;
3318         }
3319
3320         return 0;
3321 }
3322
3323 static int
3324 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3325 {
3326         struct hns3_config_mac_speed_dup_cmd *req;
3327         struct hns3_cmd_desc desc;
3328         int ret;
3329
3330         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3331
3332         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3333
3334         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3335
3336         switch (speed) {
3337         case ETH_SPEED_NUM_10M:
3338                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3339                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3340                 break;
3341         case ETH_SPEED_NUM_100M:
3342                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3343                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3344                 break;
3345         case ETH_SPEED_NUM_1G:
3346                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3347                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3348                 break;
3349         case ETH_SPEED_NUM_10G:
3350                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3351                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3352                 break;
3353         case ETH_SPEED_NUM_25G:
3354                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3355                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3356                 break;
3357         case ETH_SPEED_NUM_40G:
3358                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3359                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3360                 break;
3361         case ETH_SPEED_NUM_50G:
3362                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3363                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3364                 break;
3365         case ETH_SPEED_NUM_100G:
3366                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3367                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3368                 break;
3369         case ETH_SPEED_NUM_200G:
3370                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3371                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3372                 break;
3373         default:
3374                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3375                 return -EINVAL;
3376         }
3377
3378         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3379
3380         ret = hns3_cmd_send(hw, &desc, 1);
3381         if (ret)
3382                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3383
3384         return ret;
3385 }
3386
3387 static int
3388 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3389 {
3390         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3391         struct hns3_pf *pf = &hns->pf;
3392         struct hns3_priv_buf *priv;
3393         uint32_t i, total_size;
3394
3395         total_size = pf->pkt_buf_size;
3396
3397         /* alloc tx buffer for all enabled tc */
3398         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3399                 priv = &buf_alloc->priv_buf[i];
3400
3401                 if (hw->hw_tc_map & BIT(i)) {
3402                         if (total_size < pf->tx_buf_size)
3403                                 return -ENOMEM;
3404
3405                         priv->tx_buf_size = pf->tx_buf_size;
3406                 } else
3407                         priv->tx_buf_size = 0;
3408
3409                 total_size -= priv->tx_buf_size;
3410         }
3411
3412         return 0;
3413 }
3414
3415 static int
3416 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3417 {
3418 /* TX buffer size is unit by 128 byte */
3419 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3420 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3421         struct hns3_tx_buff_alloc_cmd *req;
3422         struct hns3_cmd_desc desc;
3423         uint32_t buf_size;
3424         uint32_t i;
3425         int ret;
3426
3427         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3428
3429         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3430         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3431                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3432
3433                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3434                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3435                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3436         }
3437
3438         ret = hns3_cmd_send(hw, &desc, 1);
3439         if (ret)
3440                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3441
3442         return ret;
3443 }
3444
3445 static int
3446 hns3_get_tc_num(struct hns3_hw *hw)
3447 {
3448         int cnt = 0;
3449         uint8_t i;
3450
3451         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3452                 if (hw->hw_tc_map & BIT(i))
3453                         cnt++;
3454         return cnt;
3455 }
3456
3457 static uint32_t
3458 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3459 {
3460         struct hns3_priv_buf *priv;
3461         uint32_t rx_priv = 0;
3462         int i;
3463
3464         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3465                 priv = &buf_alloc->priv_buf[i];
3466                 if (priv->enable)
3467                         rx_priv += priv->buf_size;
3468         }
3469         return rx_priv;
3470 }
3471
3472 static uint32_t
3473 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3474 {
3475         uint32_t total_tx_size = 0;
3476         uint32_t i;
3477
3478         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3479                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3480
3481         return total_tx_size;
3482 }
3483
3484 /* Get the number of pfc enabled TCs, which have private buffer */
3485 static int
3486 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3487 {
3488         struct hns3_priv_buf *priv;
3489         int cnt = 0;
3490         uint8_t i;
3491
3492         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3493                 priv = &buf_alloc->priv_buf[i];
3494                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3495                         cnt++;
3496         }
3497
3498         return cnt;
3499 }
3500
3501 /* Get the number of pfc disabled TCs, which have private buffer */
3502 static int
3503 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3504                          struct hns3_pkt_buf_alloc *buf_alloc)
3505 {
3506         struct hns3_priv_buf *priv;
3507         int cnt = 0;
3508         uint8_t i;
3509
3510         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3511                 priv = &buf_alloc->priv_buf[i];
3512                 if (hw->hw_tc_map & BIT(i) &&
3513                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3514                         cnt++;
3515         }
3516
3517         return cnt;
3518 }
3519
3520 static bool
3521 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3522                   uint32_t rx_all)
3523 {
3524         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3525         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3526         struct hns3_pf *pf = &hns->pf;
3527         uint32_t shared_buf, aligned_mps;
3528         uint32_t rx_priv;
3529         uint8_t tc_num;
3530         uint8_t i;
3531
3532         tc_num = hns3_get_tc_num(hw);
3533         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3534
3535         if (hns3_dev_dcb_supported(hw))
3536                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3537                                         pf->dv_buf_size;
3538         else
3539                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3540                                         + pf->dv_buf_size;
3541
3542         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3543         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3544                              HNS3_BUF_SIZE_UNIT);
3545
3546         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3547         if (rx_all < rx_priv + shared_std)
3548                 return false;
3549
3550         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3551         buf_alloc->s_buf.buf_size = shared_buf;
3552         if (hns3_dev_dcb_supported(hw)) {
3553                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3554                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3555                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3556                                   HNS3_BUF_SIZE_UNIT);
3557         } else {
3558                 buf_alloc->s_buf.self.high =
3559                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3560                 buf_alloc->s_buf.self.low = aligned_mps;
3561         }
3562
3563         if (hns3_dev_dcb_supported(hw)) {
3564                 hi_thrd = shared_buf - pf->dv_buf_size;
3565
3566                 if (tc_num <= NEED_RESERVE_TC_NUM)
3567                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3568                                   BUF_MAX_PERCENT;
3569
3570                 if (tc_num)
3571                         hi_thrd = hi_thrd / tc_num;
3572
3573                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3574                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3575                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3576         } else {
3577                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3578                 lo_thrd = aligned_mps;
3579         }
3580
3581         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3582                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3583                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3584         }
3585
3586         return true;
3587 }
3588
3589 static bool
3590 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3591                      struct hns3_pkt_buf_alloc *buf_alloc)
3592 {
3593         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3594         struct hns3_pf *pf = &hns->pf;
3595         struct hns3_priv_buf *priv;
3596         uint32_t aligned_mps;
3597         uint32_t rx_all;
3598         uint8_t i;
3599
3600         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3601         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3602
3603         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3604                 priv = &buf_alloc->priv_buf[i];
3605
3606                 priv->enable = 0;
3607                 priv->wl.low = 0;
3608                 priv->wl.high = 0;
3609                 priv->buf_size = 0;
3610
3611                 if (!(hw->hw_tc_map & BIT(i)))
3612                         continue;
3613
3614                 priv->enable = 1;
3615                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3616                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3617                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3618                                                 HNS3_BUF_SIZE_UNIT);
3619                 } else {
3620                         priv->wl.low = 0;
3621                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3622                                         aligned_mps;
3623                 }
3624
3625                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3626         }
3627
3628         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3629 }
3630
3631 static bool
3632 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3633                              struct hns3_pkt_buf_alloc *buf_alloc)
3634 {
3635         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3636         struct hns3_pf *pf = &hns->pf;
3637         struct hns3_priv_buf *priv;
3638         int no_pfc_priv_num;
3639         uint32_t rx_all;
3640         uint8_t mask;
3641         int i;
3642
3643         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3644         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3645
3646         /* let the last to be cleared first */
3647         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3648                 priv = &buf_alloc->priv_buf[i];
3649                 mask = BIT((uint8_t)i);
3650
3651                 if (hw->hw_tc_map & mask &&
3652                     !(hw->dcb_info.hw_pfc_map & mask)) {
3653                         /* Clear the no pfc TC private buffer */
3654                         priv->wl.low = 0;
3655                         priv->wl.high = 0;
3656                         priv->buf_size = 0;
3657                         priv->enable = 0;
3658                         no_pfc_priv_num--;
3659                 }
3660
3661                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3662                     no_pfc_priv_num == 0)
3663                         break;
3664         }
3665
3666         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3667 }
3668
3669 static bool
3670 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3671                            struct hns3_pkt_buf_alloc *buf_alloc)
3672 {
3673         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3674         struct hns3_pf *pf = &hns->pf;
3675         struct hns3_priv_buf *priv;
3676         uint32_t rx_all;
3677         int pfc_priv_num;
3678         uint8_t mask;
3679         int i;
3680
3681         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3682         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3683
3684         /* let the last to be cleared first */
3685         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3686                 priv = &buf_alloc->priv_buf[i];
3687                 mask = BIT((uint8_t)i);
3688                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3689                         /* Reduce the number of pfc TC with private buffer */
3690                         priv->wl.low = 0;
3691                         priv->enable = 0;
3692                         priv->wl.high = 0;
3693                         priv->buf_size = 0;
3694                         pfc_priv_num--;
3695                 }
3696                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3697                     pfc_priv_num == 0)
3698                         break;
3699         }
3700
3701         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3702 }
3703
3704 static bool
3705 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3706                           struct hns3_pkt_buf_alloc *buf_alloc)
3707 {
3708 #define COMPENSATE_BUFFER       0x3C00
3709 #define COMPENSATE_HALF_MPS_NUM 5
3710 #define PRIV_WL_GAP             0x1800
3711         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3712         struct hns3_pf *pf = &hns->pf;
3713         uint32_t tc_num = hns3_get_tc_num(hw);
3714         uint32_t half_mps = pf->mps >> 1;
3715         struct hns3_priv_buf *priv;
3716         uint32_t min_rx_priv;
3717         uint32_t rx_priv;
3718         uint8_t i;
3719
3720         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3721         if (tc_num)
3722                 rx_priv = rx_priv / tc_num;
3723
3724         if (tc_num <= NEED_RESERVE_TC_NUM)
3725                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3726
3727         /*
3728          * Minimum value of private buffer in rx direction (min_rx_priv) is
3729          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3730          * buffer if rx_priv is greater than min_rx_priv.
3731          */
3732         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3733                         COMPENSATE_HALF_MPS_NUM * half_mps;
3734         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3735         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3736
3737         if (rx_priv < min_rx_priv)
3738                 return false;
3739
3740         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3741                 priv = &buf_alloc->priv_buf[i];
3742                 priv->enable = 0;
3743                 priv->wl.low = 0;
3744                 priv->wl.high = 0;
3745                 priv->buf_size = 0;
3746
3747                 if (!(hw->hw_tc_map & BIT(i)))
3748                         continue;
3749
3750                 priv->enable = 1;
3751                 priv->buf_size = rx_priv;
3752                 priv->wl.high = rx_priv - pf->dv_buf_size;
3753                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3754         }
3755
3756         buf_alloc->s_buf.buf_size = 0;
3757
3758         return true;
3759 }
3760
3761 /*
3762  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3763  * @hw: pointer to struct hns3_hw
3764  * @buf_alloc: pointer to buffer calculation data
3765  * @return: 0: calculate sucessful, negative: fail
3766  */
3767 static int
3768 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3769 {
3770         /* When DCB is not supported, rx private buffer is not allocated. */
3771         if (!hns3_dev_dcb_supported(hw)) {
3772                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3773                 struct hns3_pf *pf = &hns->pf;
3774                 uint32_t rx_all = pf->pkt_buf_size;
3775
3776                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3777                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3778                         return -ENOMEM;
3779
3780                 return 0;
3781         }
3782
3783         /*
3784          * Try to allocate privated packet buffer for all TCs without share
3785          * buffer.
3786          */
3787         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3788                 return 0;
3789
3790         /*
3791          * Try to allocate privated packet buffer for all TCs with share
3792          * buffer.
3793          */
3794         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3795                 return 0;
3796
3797         /*
3798          * For different application scenes, the enabled port number, TC number
3799          * and no_drop TC number are different. In order to obtain the better
3800          * performance, software could allocate the buffer size and configure
3801          * the waterline by tring to decrease the private buffer size according
3802          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3803          * enabled tc.
3804          */
3805         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3806                 return 0;
3807
3808         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3809                 return 0;
3810
3811         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3812                 return 0;
3813
3814         return -ENOMEM;
3815 }
3816
3817 static int
3818 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3819 {
3820         struct hns3_rx_priv_buff_cmd *req;
3821         struct hns3_cmd_desc desc;
3822         uint32_t buf_size;
3823         int ret;
3824         int i;
3825
3826         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3827         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3828
3829         /* Alloc private buffer TCs */
3830         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3831                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3832
3833                 req->buf_num[i] =
3834                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3835                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3836         }
3837
3838         buf_size = buf_alloc->s_buf.buf_size;
3839         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3840                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3841
3842         ret = hns3_cmd_send(hw, &desc, 1);
3843         if (ret)
3844                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3845
3846         return ret;
3847 }
3848
3849 static int
3850 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3851 {
3852 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3853         struct hns3_rx_priv_wl_buf *req;
3854         struct hns3_priv_buf *priv;
3855         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3856         int i, j;
3857         int ret;
3858
3859         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3860                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3861                                           false);
3862                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3863
3864                 /* The first descriptor set the NEXT bit to 1 */
3865                 if (i == 0)
3866                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3867                 else
3868                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3869
3870                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3871                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3872
3873                         priv = &buf_alloc->priv_buf[idx];
3874                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3875                                                         HNS3_BUF_UNIT_S);
3876                         req->tc_wl[j].high |=
3877                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3878                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3879                                                         HNS3_BUF_UNIT_S);
3880                         req->tc_wl[j].low |=
3881                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3882                 }
3883         }
3884
3885         /* Send 2 descriptor at one time */
3886         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3887         if (ret)
3888                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3889                              ret);
3890         return ret;
3891 }
3892
3893 static int
3894 hns3_common_thrd_config(struct hns3_hw *hw,
3895                         struct hns3_pkt_buf_alloc *buf_alloc)
3896 {
3897 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3898         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3899         struct hns3_rx_com_thrd *req;
3900         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3901         struct hns3_tc_thrd *tc;
3902         int tc_idx;
3903         int i, j;
3904         int ret;
3905
3906         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3907                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3908                                           false);
3909                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3910
3911                 /* The first descriptor set the NEXT bit to 1 */
3912                 if (i == 0)
3913                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3914                 else
3915                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3916
3917                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3918                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3919                         tc = &s_buf->tc_thrd[tc_idx];
3920
3921                         req->com_thrd[j].high =
3922                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3923                         req->com_thrd[j].high |=
3924                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3925                         req->com_thrd[j].low =
3926                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3927                         req->com_thrd[j].low |=
3928                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3929                 }
3930         }
3931
3932         /* Send 2 descriptors at one time */
3933         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3934         if (ret)
3935                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3936
3937         return ret;
3938 }
3939
3940 static int
3941 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3942 {
3943         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3944         struct hns3_rx_com_wl *req;
3945         struct hns3_cmd_desc desc;
3946         int ret;
3947
3948         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3949
3950         req = (struct hns3_rx_com_wl *)desc.data;
3951         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3952         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3953
3954         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3955         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3956
3957         ret = hns3_cmd_send(hw, &desc, 1);
3958         if (ret)
3959                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3960
3961         return ret;
3962 }
3963
3964 int
3965 hns3_buffer_alloc(struct hns3_hw *hw)
3966 {
3967         struct hns3_pkt_buf_alloc pkt_buf;
3968         int ret;
3969
3970         memset(&pkt_buf, 0, sizeof(pkt_buf));
3971         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3972         if (ret) {
3973                 PMD_INIT_LOG(ERR,
3974                              "could not calc tx buffer size for all TCs %d",
3975                              ret);
3976                 return ret;
3977         }
3978
3979         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3980         if (ret) {
3981                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3982                 return ret;
3983         }
3984
3985         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3986         if (ret) {
3987                 PMD_INIT_LOG(ERR,
3988                              "could not calc rx priv buffer size for all TCs %d",
3989                              ret);
3990                 return ret;
3991         }
3992
3993         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3994         if (ret) {
3995                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3996                 return ret;
3997         }
3998
3999         if (hns3_dev_dcb_supported(hw)) {
4000                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4001                 if (ret) {
4002                         PMD_INIT_LOG(ERR,
4003                                      "could not configure rx private waterline %d",
4004                                      ret);
4005                         return ret;
4006                 }
4007
4008                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4009                 if (ret) {
4010                         PMD_INIT_LOG(ERR,
4011                                      "could not configure common threshold %d",
4012                                      ret);
4013                         return ret;
4014                 }
4015         }
4016
4017         ret = hns3_common_wl_config(hw, &pkt_buf);
4018         if (ret)
4019                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4020                              ret);
4021
4022         return ret;
4023 }
4024
4025 static int
4026 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4027 {
4028         struct hns3_firmware_compat_cmd *req;
4029         struct hns3_cmd_desc desc;
4030         uint32_t compat = 0;
4031
4032         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4033         req = (struct hns3_firmware_compat_cmd *)desc.data;
4034
4035         if (is_init) {
4036                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4037                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4038                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4039                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4040         }
4041
4042         req->compat = rte_cpu_to_le_32(compat);
4043
4044         return hns3_cmd_send(hw, &desc, 1);
4045 }
4046
4047 static int
4048 hns3_mac_init(struct hns3_hw *hw)
4049 {
4050         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4051         struct hns3_mac *mac = &hw->mac;
4052         struct hns3_pf *pf = &hns->pf;
4053         int ret;
4054
4055         pf->support_sfp_query = true;
4056         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4057         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4058         if (ret) {
4059                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4060                 return ret;
4061         }
4062
4063         mac->link_status = ETH_LINK_DOWN;
4064
4065         return hns3_config_mtu(hw, pf->mps);
4066 }
4067
4068 static int
4069 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4070 {
4071 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4072 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4073 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4074 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4075         int return_status;
4076
4077         if (cmdq_resp) {
4078                 PMD_INIT_LOG(ERR,
4079                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4080                              cmdq_resp);
4081                 return -EIO;
4082         }
4083
4084         switch (resp_code) {
4085         case HNS3_ETHERTYPE_SUCCESS_ADD:
4086         case HNS3_ETHERTYPE_ALREADY_ADD:
4087                 return_status = 0;
4088                 break;
4089         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4090                 PMD_INIT_LOG(ERR,
4091                              "add mac ethertype failed for manager table overflow.");
4092                 return_status = -EIO;
4093                 break;
4094         case HNS3_ETHERTYPE_KEY_CONFLICT:
4095                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4096                 return_status = -EIO;
4097                 break;
4098         default:
4099                 PMD_INIT_LOG(ERR,
4100                              "add mac ethertype failed for undefined, code=%u.",
4101                              resp_code);
4102                 return_status = -EIO;
4103                 break;
4104         }
4105
4106         return return_status;
4107 }
4108
4109 static int
4110 hns3_add_mgr_tbl(struct hns3_hw *hw,
4111                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4112 {
4113         struct hns3_cmd_desc desc;
4114         uint8_t resp_code;
4115         uint16_t retval;
4116         int ret;
4117
4118         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4119         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4120
4121         ret = hns3_cmd_send(hw, &desc, 1);
4122         if (ret) {
4123                 PMD_INIT_LOG(ERR,
4124                              "add mac ethertype failed for cmd_send, ret =%d.",
4125                              ret);
4126                 return ret;
4127         }
4128
4129         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4130         retval = rte_le_to_cpu_16(desc.retval);
4131
4132         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4133 }
4134
4135 static void
4136 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4137                      int *table_item_num)
4138 {
4139         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4140
4141         /*
4142          * In current version, we add one item in management table as below:
4143          * 0x0180C200000E -- LLDP MC address
4144          */
4145         tbl = mgr_table;
4146         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4147         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4148         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4149         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4150         tbl->i_port_bitmap = 0x1;
4151         *table_item_num = 1;
4152 }
4153
4154 static int
4155 hns3_init_mgr_tbl(struct hns3_hw *hw)
4156 {
4157 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4158         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4159         int table_item_num;
4160         int ret;
4161         int i;
4162
4163         memset(mgr_table, 0, sizeof(mgr_table));
4164         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4165         for (i = 0; i < table_item_num; i++) {
4166                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4167                 if (ret) {
4168                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4169                                      ret);
4170                         return ret;
4171                 }
4172         }
4173
4174         return 0;
4175 }
4176
4177 static void
4178 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4179                         bool en_mc, bool en_bc, int vport_id)
4180 {
4181         if (!param)
4182                 return;
4183
4184         memset(param, 0, sizeof(struct hns3_promisc_param));
4185         if (en_uc)
4186                 param->enable = HNS3_PROMISC_EN_UC;
4187         if (en_mc)
4188                 param->enable |= HNS3_PROMISC_EN_MC;
4189         if (en_bc)
4190                 param->enable |= HNS3_PROMISC_EN_BC;
4191         param->vf_id = vport_id;
4192 }
4193
4194 static int
4195 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4196 {
4197         struct hns3_promisc_cfg_cmd *req;
4198         struct hns3_cmd_desc desc;
4199         int ret;
4200
4201         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4202
4203         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4204         req->vf_id = param->vf_id;
4205         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4206             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4207
4208         ret = hns3_cmd_send(hw, &desc, 1);
4209         if (ret)
4210                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4211
4212         return ret;
4213 }
4214
4215 static int
4216 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4217 {
4218         struct hns3_promisc_param param;
4219         bool en_bc_pmc = true;
4220         uint8_t vf_id;
4221
4222         /*
4223          * In current version VF is not supported when PF is driven by DPDK
4224          * driver, just need to configure parameters for PF vport.
4225          */
4226         vf_id = HNS3_PF_FUNC_ID;
4227
4228         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4229         return hns3_cmd_set_promisc_mode(hw, &param);
4230 }
4231
4232 static int
4233 hns3_promisc_init(struct hns3_hw *hw)
4234 {
4235         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4236         struct hns3_pf *pf = &hns->pf;
4237         struct hns3_promisc_param param;
4238         uint16_t func_id;
4239         int ret;
4240
4241         ret = hns3_set_promisc_mode(hw, false, false);
4242         if (ret) {
4243                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4244                 return ret;
4245         }
4246
4247         /*
4248          * In current version VFs are not supported when PF is driven by DPDK
4249          * driver. After PF has been taken over by DPDK, the original VF will
4250          * be invalid. So, there is a possibility of entry residues. It should
4251          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4252          * during init.
4253          */
4254         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4255                 hns3_promisc_param_init(&param, false, false, false, func_id);
4256                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4257                 if (ret) {
4258                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4259                                         " ret = %d", func_id, ret);
4260                         return ret;
4261                 }
4262         }
4263
4264         return 0;
4265 }
4266
4267 static void
4268 hns3_promisc_uninit(struct hns3_hw *hw)
4269 {
4270         struct hns3_promisc_param param;
4271         uint16_t func_id;
4272         int ret;
4273
4274         func_id = HNS3_PF_FUNC_ID;
4275
4276         /*
4277          * In current version VFs are not supported when PF is driven by
4278          * DPDK driver, and VFs' promisc mode status has been cleared during
4279          * init and their status will not change. So just clear PF's promisc
4280          * mode status during uninit.
4281          */
4282         hns3_promisc_param_init(&param, false, false, false, func_id);
4283         ret = hns3_cmd_set_promisc_mode(hw, &param);
4284         if (ret)
4285                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4286                                 " uninit, ret = %d", ret);
4287 }
4288
4289 static int
4290 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4291 {
4292         bool allmulti = dev->data->all_multicast ? true : false;
4293         struct hns3_adapter *hns = dev->data->dev_private;
4294         struct hns3_hw *hw = &hns->hw;
4295         uint64_t offloads;
4296         int err;
4297         int ret;
4298
4299         rte_spinlock_lock(&hw->lock);
4300         ret = hns3_set_promisc_mode(hw, true, true);
4301         if (ret) {
4302                 rte_spinlock_unlock(&hw->lock);
4303                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4304                          ret);
4305                 return ret;
4306         }
4307
4308         /*
4309          * When promiscuous mode was enabled, disable the vlan filter to let
4310          * all packets coming in in the receiving direction.
4311          */
4312         offloads = dev->data->dev_conf.rxmode.offloads;
4313         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4314                 ret = hns3_enable_vlan_filter(hns, false);
4315                 if (ret) {
4316                         hns3_err(hw, "failed to enable promiscuous mode due to "
4317                                      "failure to disable vlan filter, ret = %d",
4318                                  ret);
4319                         err = hns3_set_promisc_mode(hw, false, allmulti);
4320                         if (err)
4321                                 hns3_err(hw, "failed to restore promiscuous "
4322                                          "status after disable vlan filter "
4323                                          "failed during enabling promiscuous "
4324                                          "mode, ret = %d", ret);
4325                 }
4326         }
4327
4328         rte_spinlock_unlock(&hw->lock);
4329
4330         return ret;
4331 }
4332
4333 static int
4334 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4335 {
4336         bool allmulti = dev->data->all_multicast ? true : false;
4337         struct hns3_adapter *hns = dev->data->dev_private;
4338         struct hns3_hw *hw = &hns->hw;
4339         uint64_t offloads;
4340         int err;
4341         int ret;
4342
4343         /* If now in all_multicast mode, must remain in all_multicast mode. */
4344         rte_spinlock_lock(&hw->lock);
4345         ret = hns3_set_promisc_mode(hw, false, allmulti);
4346         if (ret) {
4347                 rte_spinlock_unlock(&hw->lock);
4348                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4349                          ret);
4350                 return ret;
4351         }
4352         /* when promiscuous mode was disabled, restore the vlan filter status */
4353         offloads = dev->data->dev_conf.rxmode.offloads;
4354         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4355                 ret = hns3_enable_vlan_filter(hns, true);
4356                 if (ret) {
4357                         hns3_err(hw, "failed to disable promiscuous mode due to"
4358                                  " failure to restore vlan filter, ret = %d",
4359                                  ret);
4360                         err = hns3_set_promisc_mode(hw, true, true);
4361                         if (err)
4362                                 hns3_err(hw, "failed to restore promiscuous "
4363                                          "status after enabling vlan filter "
4364                                          "failed during disabling promiscuous "
4365                                          "mode, ret = %d", ret);
4366                 }
4367         }
4368         rte_spinlock_unlock(&hw->lock);
4369
4370         return ret;
4371 }
4372
4373 static int
4374 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4375 {
4376         struct hns3_adapter *hns = dev->data->dev_private;
4377         struct hns3_hw *hw = &hns->hw;
4378         int ret;
4379
4380         if (dev->data->promiscuous)
4381                 return 0;
4382
4383         rte_spinlock_lock(&hw->lock);
4384         ret = hns3_set_promisc_mode(hw, false, true);
4385         rte_spinlock_unlock(&hw->lock);
4386         if (ret)
4387                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4388                          ret);
4389
4390         return ret;
4391 }
4392
4393 static int
4394 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4395 {
4396         struct hns3_adapter *hns = dev->data->dev_private;
4397         struct hns3_hw *hw = &hns->hw;
4398         int ret;
4399
4400         /* If now in promiscuous mode, must remain in all_multicast mode. */
4401         if (dev->data->promiscuous)
4402                 return 0;
4403
4404         rte_spinlock_lock(&hw->lock);
4405         ret = hns3_set_promisc_mode(hw, false, false);
4406         rte_spinlock_unlock(&hw->lock);
4407         if (ret)
4408                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4409                          ret);
4410
4411         return ret;
4412 }
4413
4414 static int
4415 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4416 {
4417         struct hns3_hw *hw = &hns->hw;
4418         bool allmulti = hw->data->all_multicast ? true : false;
4419         int ret;
4420
4421         if (hw->data->promiscuous) {
4422                 ret = hns3_set_promisc_mode(hw, true, true);
4423                 if (ret)
4424                         hns3_err(hw, "failed to restore promiscuous mode, "
4425                                  "ret = %d", ret);
4426                 return ret;
4427         }
4428
4429         ret = hns3_set_promisc_mode(hw, false, allmulti);
4430         if (ret)
4431                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4432                          ret);
4433         return ret;
4434 }
4435
4436 static int
4437 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4438 {
4439         struct hns3_sfp_speed_cmd *resp;
4440         struct hns3_cmd_desc desc;
4441         int ret;
4442
4443         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4444         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4445         ret = hns3_cmd_send(hw, &desc, 1);
4446         if (ret == -EOPNOTSUPP) {
4447                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4448                 return ret;
4449         } else if (ret) {
4450                 hns3_err(hw, "get sfp speed failed %d", ret);
4451                 return ret;
4452         }
4453
4454         *speed = resp->sfp_speed;
4455
4456         return 0;
4457 }
4458
4459 static uint8_t
4460 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4461 {
4462         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4463                 duplex = ETH_LINK_FULL_DUPLEX;
4464
4465         return duplex;
4466 }
4467
4468 static int
4469 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4470 {
4471         struct hns3_mac *mac = &hw->mac;
4472         int ret;
4473
4474         duplex = hns3_check_speed_dup(duplex, speed);
4475         if (mac->link_speed == speed && mac->link_duplex == duplex)
4476                 return 0;
4477
4478         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4479         if (ret)
4480                 return ret;
4481
4482         ret = hns3_port_shaper_update(hw, speed);
4483         if (ret)
4484                 return ret;
4485
4486         mac->link_speed = speed;
4487         mac->link_duplex = duplex;
4488
4489         return 0;
4490 }
4491
4492 static int
4493 hns3_update_fiber_link_info(struct hns3_hw *hw)
4494 {
4495         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4496         uint32_t speed;
4497         int ret;
4498
4499         /* If IMP do not support get SFP/qSFP speed, return directly */
4500         if (!pf->support_sfp_query)
4501                 return 0;
4502
4503         ret = hns3_get_sfp_speed(hw, &speed);
4504         if (ret == -EOPNOTSUPP) {
4505                 pf->support_sfp_query = false;
4506                 return ret;
4507         } else if (ret)
4508                 return ret;
4509
4510         if (speed == ETH_SPEED_NUM_NONE)
4511                 return 0; /* do nothing if no SFP */
4512
4513         /* Config full duplex for SFP */
4514         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4515 }
4516
4517 static void
4518 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4519 {
4520         struct hns3_phy_params_bd0_cmd *req;
4521
4522         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4523         mac->link_speed = rte_le_to_cpu_32(req->speed);
4524         mac->link_duplex = hns3_get_bit(req->duplex,
4525                                            HNS3_PHY_DUPLEX_CFG_B);
4526         mac->link_autoneg = hns3_get_bit(req->autoneg,
4527                                            HNS3_PHY_AUTONEG_CFG_B);
4528         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4529         mac->advertising = rte_le_to_cpu_32(req->advertising);
4530         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4531         mac->support_autoneg = !!(mac->supported_capa &
4532                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4533 }
4534
4535 static int
4536 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4537 {
4538         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4539         uint16_t i;
4540         int ret;
4541
4542         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4543                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4544                                           true);
4545                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4546         }
4547         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4548
4549         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4550         if (ret) {
4551                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4552                 return ret;
4553         }
4554
4555         hns3_parse_phy_params(desc, mac);
4556
4557         return 0;
4558 }
4559
4560 static int
4561 hns3_update_phy_link_info(struct hns3_hw *hw)
4562 {
4563         struct hns3_mac *mac = &hw->mac;
4564         struct hns3_mac mac_info;
4565         int ret;
4566
4567         memset(&mac_info, 0, sizeof(struct hns3_mac));
4568         ret = hns3_get_phy_params(hw, &mac_info);
4569         if (ret)
4570                 return ret;
4571
4572         if (mac_info.link_speed != mac->link_speed) {
4573                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4574                 if (ret)
4575                         return ret;
4576         }
4577
4578         mac->link_speed = mac_info.link_speed;
4579         mac->link_duplex = mac_info.link_duplex;
4580         mac->link_autoneg = mac_info.link_autoneg;
4581         mac->supported_capa = mac_info.supported_capa;
4582         mac->advertising = mac_info.advertising;
4583         mac->lp_advertising = mac_info.lp_advertising;
4584         mac->support_autoneg = mac_info.support_autoneg;
4585
4586         return 0;
4587 }
4588
4589 static int
4590 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4591 {
4592         struct hns3_adapter *hns = eth_dev->data->dev_private;
4593         struct hns3_hw *hw = &hns->hw;
4594         int ret = 0;
4595
4596         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4597                 ret = hns3_update_phy_link_info(hw);
4598         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4599                 ret = hns3_update_fiber_link_info(hw);
4600
4601         return ret;
4602 }
4603
4604 static int
4605 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4606 {
4607         struct hns3_config_mac_mode_cmd *req;
4608         struct hns3_cmd_desc desc;
4609         uint32_t loop_en = 0;
4610         uint8_t val = 0;
4611         int ret;
4612
4613         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4614
4615         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4616         if (enable)
4617                 val = 1;
4618         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4619         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4620         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4621         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4622         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4623         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4624         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4625         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4626         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4627         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4628
4629         /*
4630          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4631          * when receiving frames. Otherwise, CRC will be stripped.
4632          */
4633         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4634                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4635         else
4636                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4637         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4638         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4639         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4640         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4641
4642         ret = hns3_cmd_send(hw, &desc, 1);
4643         if (ret)
4644                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4645
4646         return ret;
4647 }
4648
4649 static int
4650 hns3_get_mac_link_status(struct hns3_hw *hw)
4651 {
4652         struct hns3_link_status_cmd *req;
4653         struct hns3_cmd_desc desc;
4654         int link_status;
4655         int ret;
4656
4657         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4658         ret = hns3_cmd_send(hw, &desc, 1);
4659         if (ret) {
4660                 hns3_err(hw, "get link status cmd failed %d", ret);
4661                 return ETH_LINK_DOWN;
4662         }
4663
4664         req = (struct hns3_link_status_cmd *)desc.data;
4665         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4666
4667         return !!link_status;
4668 }
4669
4670 static bool
4671 hns3_update_link_status(struct hns3_hw *hw)
4672 {
4673         int state;
4674
4675         state = hns3_get_mac_link_status(hw);
4676         if (state != hw->mac.link_status) {
4677                 hw->mac.link_status = state;
4678                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4679                 hns3_config_mac_tnl_int(hw,
4680                                         state == ETH_LINK_UP ? true : false);
4681                 return true;
4682         }
4683
4684         return false;
4685 }
4686
4687 /*
4688  * Current, the PF driver get link status by two ways:
4689  * 1) Periodic polling in the intr thread context, driver call
4690  *    hns3_update_link_status to update link status.
4691  * 2) Firmware report async interrupt, driver process the event in the intr
4692  *    thread context, and call hns3_update_link_status to update link status.
4693  *
4694  * If detect link status changed, driver need report LSE. One method is add the
4695  * report LSE logic in hns3_update_link_status.
4696  *
4697  * But the PF driver ops(link_update) also call hns3_update_link_status to
4698  * update link status.
4699  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4700  * bonding application.
4701  *
4702  * So add the one new API which used only in intr thread context.
4703  */
4704 void
4705 hns3_update_link_status_and_event(struct hns3_hw *hw)
4706 {
4707         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4708         bool changed = hns3_update_link_status(hw);
4709         if (changed)
4710                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4711 }
4712
4713 static void
4714 hns3_service_handler(void *param)
4715 {
4716         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4717         struct hns3_adapter *hns = eth_dev->data->dev_private;
4718         struct hns3_hw *hw = &hns->hw;
4719
4720         if (!hns3_is_reset_pending(hns)) {
4721                 hns3_update_link_status_and_event(hw);
4722                 hns3_update_link_info(eth_dev);
4723         } else {
4724                 hns3_warn(hw, "Cancel the query when reset is pending");
4725         }
4726
4727         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4728 }
4729
4730 static int
4731 hns3_init_hardware(struct hns3_adapter *hns)
4732 {
4733         struct hns3_hw *hw = &hns->hw;
4734         int ret;
4735
4736         ret = hns3_map_tqp(hw);
4737         if (ret) {
4738                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4739                 return ret;
4740         }
4741
4742         ret = hns3_init_umv_space(hw);
4743         if (ret) {
4744                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4745                 return ret;
4746         }
4747
4748         ret = hns3_mac_init(hw);
4749         if (ret) {
4750                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4751                 goto err_mac_init;
4752         }
4753
4754         ret = hns3_init_mgr_tbl(hw);
4755         if (ret) {
4756                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4757                 goto err_mac_init;
4758         }
4759
4760         ret = hns3_promisc_init(hw);
4761         if (ret) {
4762                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4763                              ret);
4764                 goto err_mac_init;
4765         }
4766
4767         ret = hns3_init_vlan_config(hns);
4768         if (ret) {
4769                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4770                 goto err_mac_init;
4771         }
4772
4773         ret = hns3_dcb_init(hw);
4774         if (ret) {
4775                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4776                 goto err_mac_init;
4777         }
4778
4779         ret = hns3_init_fd_config(hns);
4780         if (ret) {
4781                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4782                 goto err_mac_init;
4783         }
4784
4785         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4786         if (ret) {
4787                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4788                 goto err_mac_init;
4789         }
4790
4791         ret = hns3_config_gro(hw, false);
4792         if (ret) {
4793                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4794                 goto err_mac_init;
4795         }
4796
4797         /*
4798          * In the initialization clearing the all hardware mapping relationship
4799          * configurations between queues and interrupt vectors is needed, so
4800          * some error caused by the residual configurations, such as the
4801          * unexpected interrupt, can be avoid.
4802          */
4803         ret = hns3_init_ring_with_vector(hw);
4804         if (ret) {
4805                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4806                 goto err_mac_init;
4807         }
4808
4809         /*
4810          * Requiring firmware to enable some features, driver can
4811          * still work without it.
4812          */
4813         ret = hns3_firmware_compat_config(hw, true);
4814         if (ret)
4815                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4816                              "supported, ret = %d.", ret);
4817
4818         return 0;
4819
4820 err_mac_init:
4821         hns3_uninit_umv_space(hw);
4822         return ret;
4823 }
4824
4825 static int
4826 hns3_clear_hw(struct hns3_hw *hw)
4827 {
4828         struct hns3_cmd_desc desc;
4829         int ret;
4830
4831         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4832
4833         ret = hns3_cmd_send(hw, &desc, 1);
4834         if (ret && ret != -EOPNOTSUPP)
4835                 return ret;
4836
4837         return 0;
4838 }
4839
4840 static void
4841 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4842 {
4843         uint32_t val;
4844
4845         /*
4846          * The new firmware support report more hardware error types by
4847          * msix mode. These errors are defined as RAS errors in hardware
4848          * and belong to a different type from the MSI-x errors processed
4849          * by the network driver.
4850          *
4851          * Network driver should open the new error report on initialition
4852          */
4853         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4854         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4855         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4856 }
4857
4858 static int
4859 hns3_init_pf(struct rte_eth_dev *eth_dev)
4860 {
4861         struct rte_device *dev = eth_dev->device;
4862         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4863         struct hns3_adapter *hns = eth_dev->data->dev_private;
4864         struct hns3_hw *hw = &hns->hw;
4865         int ret;
4866
4867         PMD_INIT_FUNC_TRACE();
4868
4869         /* Get hardware io base address from pcie BAR2 IO space */
4870         hw->io_base = pci_dev->mem_resource[2].addr;
4871
4872         /* Firmware command queue initialize */
4873         ret = hns3_cmd_init_queue(hw);
4874         if (ret) {
4875                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4876                 goto err_cmd_init_queue;
4877         }
4878
4879         hns3_clear_all_event_cause(hw);
4880
4881         /* Firmware command initialize */
4882         ret = hns3_cmd_init(hw);
4883         if (ret) {
4884                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4885                 goto err_cmd_init;
4886         }
4887
4888         /*
4889          * To ensure that the hardware environment is clean during
4890          * initialization, the driver actively clear the hardware environment
4891          * during initialization, including PF and corresponding VFs' vlan, mac,
4892          * flow table configurations, etc.
4893          */
4894         ret = hns3_clear_hw(hw);
4895         if (ret) {
4896                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4897                 goto err_cmd_init;
4898         }
4899
4900         /* Hardware statistics of imissed registers cleared. */
4901         ret = hns3_update_imissed_stats(hw, true);
4902         if (ret) {
4903                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4904                 return ret;
4905         }
4906
4907         hns3_config_all_msix_error(hw, true);
4908
4909         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4910                                          hns3_interrupt_handler,
4911                                          eth_dev);
4912         if (ret) {
4913                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4914                 goto err_intr_callback_register;
4915         }
4916
4917         /* Enable interrupt */
4918         rte_intr_enable(&pci_dev->intr_handle);
4919         hns3_pf_enable_irq0(hw);
4920
4921         /* Get configuration */
4922         ret = hns3_get_configuration(hw);
4923         if (ret) {
4924                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4925                 goto err_get_config;
4926         }
4927
4928         ret = hns3_tqp_stats_init(hw);
4929         if (ret)
4930                 goto err_get_config;
4931
4932         ret = hns3_init_hardware(hns);
4933         if (ret) {
4934                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4935                 goto err_init_hw;
4936         }
4937
4938         /* Initialize flow director filter list & hash */
4939         ret = hns3_fdir_filter_init(hns);
4940         if (ret) {
4941                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4942                 goto err_fdir;
4943         }
4944
4945         hns3_rss_set_default_args(hw);
4946
4947         ret = hns3_enable_hw_error_intr(hns, true);
4948         if (ret) {
4949                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4950                              ret);
4951                 goto err_enable_intr;
4952         }
4953
4954         hns3_tm_conf_init(eth_dev);
4955
4956         return 0;
4957
4958 err_enable_intr:
4959         hns3_fdir_filter_uninit(hns);
4960 err_fdir:
4961         (void)hns3_firmware_compat_config(hw, false);
4962         hns3_uninit_umv_space(hw);
4963 err_init_hw:
4964         hns3_tqp_stats_uninit(hw);
4965 err_get_config:
4966         hns3_pf_disable_irq0(hw);
4967         rte_intr_disable(&pci_dev->intr_handle);
4968         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4969                              eth_dev);
4970 err_intr_callback_register:
4971 err_cmd_init:
4972         hns3_cmd_uninit(hw);
4973         hns3_cmd_destroy_queue(hw);
4974 err_cmd_init_queue:
4975         hw->io_base = NULL;
4976
4977         return ret;
4978 }
4979
4980 static void
4981 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4982 {
4983         struct hns3_adapter *hns = eth_dev->data->dev_private;
4984         struct rte_device *dev = eth_dev->device;
4985         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4986         struct hns3_hw *hw = &hns->hw;
4987
4988         PMD_INIT_FUNC_TRACE();
4989
4990         hns3_tm_conf_uninit(eth_dev);
4991         hns3_enable_hw_error_intr(hns, false);
4992         hns3_rss_uninit(hns);
4993         (void)hns3_config_gro(hw, false);
4994         hns3_promisc_uninit(hw);
4995         hns3_fdir_filter_uninit(hns);
4996         (void)hns3_firmware_compat_config(hw, false);
4997         hns3_uninit_umv_space(hw);
4998         hns3_tqp_stats_uninit(hw);
4999         hns3_config_mac_tnl_int(hw, false);
5000         hns3_pf_disable_irq0(hw);
5001         rte_intr_disable(&pci_dev->intr_handle);
5002         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5003                              eth_dev);
5004         hns3_config_all_msix_error(hw, false);
5005         hns3_cmd_uninit(hw);
5006         hns3_cmd_destroy_queue(hw);
5007         hw->io_base = NULL;
5008 }
5009
5010 static int
5011 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5012 {
5013         struct hns3_hw *hw = &hns->hw;
5014         int ret;
5015
5016         ret = hns3_dcb_cfg_update(hns);
5017         if (ret)
5018                 return ret;
5019
5020         /*
5021          * The hns3_dcb_cfg_update may configure TM module, so
5022          * hns3_tm_conf_update must called later.
5023          */
5024         ret = hns3_tm_conf_update(hw);
5025         if (ret) {
5026                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5027                 return ret;
5028         }
5029
5030         hns3_enable_rxd_adv_layout(hw);
5031
5032         ret = hns3_init_queues(hns, reset_queue);
5033         if (ret) {
5034                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5035                 return ret;
5036         }
5037
5038         ret = hns3_cfg_mac_mode(hw, true);
5039         if (ret) {
5040                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5041                 goto err_config_mac_mode;
5042         }
5043         return 0;
5044
5045 err_config_mac_mode:
5046         hns3_dev_release_mbufs(hns);
5047         /*
5048          * Here is exception handling, hns3_reset_all_tqps will have the
5049          * corresponding error message if it is handled incorrectly, so it is
5050          * not necessary to check hns3_reset_all_tqps return value, here keep
5051          * ret as the error code causing the exception.
5052          */
5053         (void)hns3_reset_all_tqps(hns);
5054         return ret;
5055 }
5056
5057 static int
5058 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5059 {
5060         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5061         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5062         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5064         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5065         uint32_t intr_vector;
5066         uint16_t q_id;
5067         int ret;
5068
5069         /*
5070          * hns3 needs a separate interrupt to be used as event interrupt which
5071          * could not be shared with task queue pair, so KERNEL drivers need
5072          * support multiple interrupt vectors.
5073          */
5074         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5075             !rte_intr_cap_multiple(intr_handle))
5076                 return 0;
5077
5078         rte_intr_disable(intr_handle);
5079         intr_vector = hw->used_rx_queues;
5080         /* creates event fd for each intr vector when MSIX is used */
5081         if (rte_intr_efd_enable(intr_handle, intr_vector))
5082                 return -EINVAL;
5083
5084         if (intr_handle->intr_vec == NULL) {
5085                 intr_handle->intr_vec =
5086                         rte_zmalloc("intr_vec",
5087                                     hw->used_rx_queues * sizeof(int), 0);
5088                 if (intr_handle->intr_vec == NULL) {
5089                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5090                                         hw->used_rx_queues);
5091                         ret = -ENOMEM;
5092                         goto alloc_intr_vec_error;
5093                 }
5094         }
5095
5096         if (rte_intr_allow_others(intr_handle)) {
5097                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5098                 base = RTE_INTR_VEC_RXTX_OFFSET;
5099         }
5100
5101         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5102                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5103                                                  HNS3_RING_TYPE_RX, q_id);
5104                 if (ret)
5105                         goto bind_vector_error;
5106                 intr_handle->intr_vec[q_id] = vec;
5107                 /*
5108                  * If there are not enough efds (e.g. not enough interrupt),
5109                  * remaining queues will be bond to the last interrupt.
5110                  */
5111                 if (vec < base + intr_handle->nb_efd - 1)
5112                         vec++;
5113         }
5114         rte_intr_enable(intr_handle);
5115         return 0;
5116
5117 bind_vector_error:
5118         rte_free(intr_handle->intr_vec);
5119         intr_handle->intr_vec = NULL;
5120 alloc_intr_vec_error:
5121         rte_intr_efd_disable(intr_handle);
5122         return ret;
5123 }
5124
5125 static int
5126 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5127 {
5128         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5130         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5131         uint16_t q_id;
5132         int ret;
5133
5134         if (dev->data->dev_conf.intr_conf.rxq == 0)
5135                 return 0;
5136
5137         if (rte_intr_dp_is_en(intr_handle)) {
5138                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5139                         ret = hns3_bind_ring_with_vector(hw,
5140                                         intr_handle->intr_vec[q_id], true,
5141                                         HNS3_RING_TYPE_RX, q_id);
5142                         if (ret)
5143                                 return ret;
5144                 }
5145         }
5146
5147         return 0;
5148 }
5149
5150 static void
5151 hns3_restore_filter(struct rte_eth_dev *dev)
5152 {
5153         hns3_restore_rss_filter(dev);
5154 }
5155
5156 static int
5157 hns3_dev_start(struct rte_eth_dev *dev)
5158 {
5159         struct hns3_adapter *hns = dev->data->dev_private;
5160         struct hns3_hw *hw = &hns->hw;
5161         int ret;
5162
5163         PMD_INIT_FUNC_TRACE();
5164         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5165                 return -EBUSY;
5166
5167         rte_spinlock_lock(&hw->lock);
5168         hw->adapter_state = HNS3_NIC_STARTING;
5169
5170         ret = hns3_do_start(hns, true);
5171         if (ret) {
5172                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5173                 rte_spinlock_unlock(&hw->lock);
5174                 return ret;
5175         }
5176         ret = hns3_map_rx_interrupt(dev);
5177         if (ret)
5178                 goto map_rx_inter_err;
5179
5180         /*
5181          * There are three register used to control the status of a TQP
5182          * (contains a pair of Tx queue and Rx queue) in the new version network
5183          * engine. One is used to control the enabling of Tx queue, the other is
5184          * used to control the enabling of Rx queue, and the last is the master
5185          * switch used to control the enabling of the tqp. The Tx register and
5186          * TQP register must be enabled at the same time to enable a Tx queue.
5187          * The same applies to the Rx queue. For the older network engine, this
5188          * function only refresh the enabled flag, and it is used to update the
5189          * status of queue in the dpdk framework.
5190          */
5191         ret = hns3_start_all_txqs(dev);
5192         if (ret)
5193                 goto map_rx_inter_err;
5194
5195         ret = hns3_start_all_rxqs(dev);
5196         if (ret)
5197                 goto start_all_rxqs_fail;
5198
5199         hw->adapter_state = HNS3_NIC_STARTED;
5200         rte_spinlock_unlock(&hw->lock);
5201
5202         hns3_rx_scattered_calc(dev);
5203         hns3_set_rxtx_function(dev);
5204         hns3_mp_req_start_rxtx(dev);
5205         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5206
5207         hns3_restore_filter(dev);
5208
5209         /* Enable interrupt of all rx queues before enabling queues */
5210         hns3_dev_all_rx_queue_intr_enable(hw, true);
5211
5212         /*
5213          * After finished the initialization, enable tqps to receive/transmit
5214          * packets and refresh all queue status.
5215          */
5216         hns3_start_tqps(hw);
5217
5218         hns3_tm_dev_start_proc(hw);
5219
5220         hns3_info(hw, "hns3 dev start successful!");
5221
5222         return 0;
5223
5224 start_all_rxqs_fail:
5225         hns3_stop_all_txqs(dev);
5226 map_rx_inter_err:
5227         (void)hns3_do_stop(hns);
5228         hw->adapter_state = HNS3_NIC_CONFIGURED;
5229         rte_spinlock_unlock(&hw->lock);
5230
5231         return ret;
5232 }
5233
5234 static int
5235 hns3_do_stop(struct hns3_adapter *hns)
5236 {
5237         struct hns3_hw *hw = &hns->hw;
5238         int ret;
5239
5240         /*
5241          * The "hns3_do_stop" function will also be called by .stop_service to
5242          * prepare reset. At the time of global or IMP reset, the command cannot
5243          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5244          * accessed during the reset process. So the mbuf can not be released
5245          * during reset and is required to be released after the reset is
5246          * completed.
5247          */
5248         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5249                 hns3_dev_release_mbufs(hns);
5250
5251         ret = hns3_cfg_mac_mode(hw, false);
5252         if (ret)
5253                 return ret;
5254         hw->mac.link_status = ETH_LINK_DOWN;
5255
5256         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5257                 hns3_configure_all_mac_addr(hns, true);
5258                 ret = hns3_reset_all_tqps(hns);
5259                 if (ret) {
5260                         hns3_err(hw, "failed to reset all queues ret = %d.",
5261                                  ret);
5262                         return ret;
5263                 }
5264         }
5265         hw->mac.default_addr_setted = false;
5266         return 0;
5267 }
5268
5269 static void
5270 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5271 {
5272         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5273         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5274         struct hns3_adapter *hns = dev->data->dev_private;
5275         struct hns3_hw *hw = &hns->hw;
5276         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5277         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5278         uint16_t q_id;
5279
5280         if (dev->data->dev_conf.intr_conf.rxq == 0)
5281                 return;
5282
5283         /* unmap the ring with vector */
5284         if (rte_intr_allow_others(intr_handle)) {
5285                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5286                 base = RTE_INTR_VEC_RXTX_OFFSET;
5287         }
5288         if (rte_intr_dp_is_en(intr_handle)) {
5289                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5290                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5291                                                          HNS3_RING_TYPE_RX,
5292                                                          q_id);
5293                         if (vec < base + intr_handle->nb_efd - 1)
5294                                 vec++;
5295                 }
5296         }
5297         /* Clean datapath event and queue/vec mapping */
5298         rte_intr_efd_disable(intr_handle);
5299         if (intr_handle->intr_vec) {
5300                 rte_free(intr_handle->intr_vec);
5301                 intr_handle->intr_vec = NULL;
5302         }
5303 }
5304
5305 static int
5306 hns3_dev_stop(struct rte_eth_dev *dev)
5307 {
5308         struct hns3_adapter *hns = dev->data->dev_private;
5309         struct hns3_hw *hw = &hns->hw;
5310
5311         PMD_INIT_FUNC_TRACE();
5312         dev->data->dev_started = 0;
5313
5314         hw->adapter_state = HNS3_NIC_STOPPING;
5315         hns3_set_rxtx_function(dev);
5316         rte_wmb();
5317         /* Disable datapath on secondary process. */
5318         hns3_mp_req_stop_rxtx(dev);
5319         /* Prevent crashes when queues are still in use. */
5320         rte_delay_ms(hw->tqps_num);
5321
5322         rte_spinlock_lock(&hw->lock);
5323         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5324                 hns3_tm_dev_stop_proc(hw);
5325                 hns3_config_mac_tnl_int(hw, false);
5326                 hns3_stop_tqps(hw);
5327                 hns3_do_stop(hns);
5328                 hns3_unmap_rx_interrupt(dev);
5329                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5330         }
5331         hns3_rx_scattered_reset(dev);
5332         rte_eal_alarm_cancel(hns3_service_handler, dev);
5333         rte_spinlock_unlock(&hw->lock);
5334
5335         return 0;
5336 }
5337
5338 static int
5339 hns3_dev_close(struct rte_eth_dev *eth_dev)
5340 {
5341         struct hns3_adapter *hns = eth_dev->data->dev_private;
5342         struct hns3_hw *hw = &hns->hw;
5343         int ret = 0;
5344
5345         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5346                 rte_free(eth_dev->process_private);
5347                 eth_dev->process_private = NULL;
5348                 return 0;
5349         }
5350
5351         if (hw->adapter_state == HNS3_NIC_STARTED)
5352                 ret = hns3_dev_stop(eth_dev);
5353
5354         hw->adapter_state = HNS3_NIC_CLOSING;
5355         hns3_reset_abort(hns);
5356         hw->adapter_state = HNS3_NIC_CLOSED;
5357
5358         hns3_configure_all_mc_mac_addr(hns, true);
5359         hns3_remove_all_vlan_table(hns);
5360         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5361         hns3_uninit_pf(eth_dev);
5362         hns3_free_all_queues(eth_dev);
5363         rte_free(hw->reset.wait_data);
5364         rte_free(eth_dev->process_private);
5365         eth_dev->process_private = NULL;
5366         hns3_mp_uninit_primary();
5367         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5368
5369         return ret;
5370 }
5371
5372 static int
5373 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5374 {
5375         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5377
5378         fc_conf->pause_time = pf->pause_time;
5379
5380         /* return fc current mode */
5381         switch (hw->current_mode) {
5382         case HNS3_FC_FULL:
5383                 fc_conf->mode = RTE_FC_FULL;
5384                 break;
5385         case HNS3_FC_TX_PAUSE:
5386                 fc_conf->mode = RTE_FC_TX_PAUSE;
5387                 break;
5388         case HNS3_FC_RX_PAUSE:
5389                 fc_conf->mode = RTE_FC_RX_PAUSE;
5390                 break;
5391         case HNS3_FC_NONE:
5392         default:
5393                 fc_conf->mode = RTE_FC_NONE;
5394                 break;
5395         }
5396
5397         return 0;
5398 }
5399
5400 static void
5401 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5402 {
5403         switch (mode) {
5404         case RTE_FC_NONE:
5405                 hw->requested_mode = HNS3_FC_NONE;
5406                 break;
5407         case RTE_FC_RX_PAUSE:
5408                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5409                 break;
5410         case RTE_FC_TX_PAUSE:
5411                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5412                 break;
5413         case RTE_FC_FULL:
5414                 hw->requested_mode = HNS3_FC_FULL;
5415                 break;
5416         default:
5417                 hw->requested_mode = HNS3_FC_NONE;
5418                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5419                           "configured to RTE_FC_NONE", mode);
5420                 break;
5421         }
5422 }
5423
5424 static int
5425 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5426 {
5427         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5429         int ret;
5430
5431         if (fc_conf->high_water || fc_conf->low_water ||
5432             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5433                 hns3_err(hw, "Unsupported flow control settings specified, "
5434                          "high_water(%u), low_water(%u), send_xon(%u) and "
5435                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5436                          fc_conf->high_water, fc_conf->low_water,
5437                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5438                 return -EINVAL;
5439         }
5440         if (fc_conf->autoneg) {
5441                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5442                 return -EINVAL;
5443         }
5444         if (!fc_conf->pause_time) {
5445                 hns3_err(hw, "Invalid pause time %u setting.",
5446                          fc_conf->pause_time);
5447                 return -EINVAL;
5448         }
5449
5450         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5451             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5452                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5453                          "current_fc_status = %d", hw->current_fc_status);
5454                 return -EOPNOTSUPP;
5455         }
5456
5457         hns3_get_fc_mode(hw, fc_conf->mode);
5458         if (hw->requested_mode == hw->current_mode &&
5459             pf->pause_time == fc_conf->pause_time)
5460                 return 0;
5461
5462         rte_spinlock_lock(&hw->lock);
5463         ret = hns3_fc_enable(dev, fc_conf);
5464         rte_spinlock_unlock(&hw->lock);
5465
5466         return ret;
5467 }
5468
5469 static int
5470 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5471                             struct rte_eth_pfc_conf *pfc_conf)
5472 {
5473         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5475         uint8_t priority;
5476         int ret;
5477
5478         if (!hns3_dev_dcb_supported(hw)) {
5479                 hns3_err(hw, "This port does not support dcb configurations.");
5480                 return -EOPNOTSUPP;
5481         }
5482
5483         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5484             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5485                 hns3_err(hw, "Unsupported flow control settings specified, "
5486                          "high_water(%u), low_water(%u), send_xon(%u) and "
5487                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5488                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5489                          pfc_conf->fc.send_xon,
5490                          pfc_conf->fc.mac_ctrl_frame_fwd);
5491                 return -EINVAL;
5492         }
5493         if (pfc_conf->fc.autoneg) {
5494                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5495                 return -EINVAL;
5496         }
5497         if (pfc_conf->fc.pause_time == 0) {
5498                 hns3_err(hw, "Invalid pause time %u setting.",
5499                          pfc_conf->fc.pause_time);
5500                 return -EINVAL;
5501         }
5502
5503         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5504             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5505                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5506                              "current_fc_status = %d", hw->current_fc_status);
5507                 return -EOPNOTSUPP;
5508         }
5509
5510         priority = pfc_conf->priority;
5511         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5512         if (hw->dcb_info.pfc_en & BIT(priority) &&
5513             hw->requested_mode == hw->current_mode &&
5514             pfc_conf->fc.pause_time == pf->pause_time)
5515                 return 0;
5516
5517         rte_spinlock_lock(&hw->lock);
5518         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5519         rte_spinlock_unlock(&hw->lock);
5520
5521         return ret;
5522 }
5523
5524 static int
5525 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5526 {
5527         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5529         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5530         int i;
5531
5532         rte_spinlock_lock(&hw->lock);
5533         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5534                 dcb_info->nb_tcs = pf->local_max_tc;
5535         else
5536                 dcb_info->nb_tcs = 1;
5537
5538         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5539                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5540         for (i = 0; i < dcb_info->nb_tcs; i++)
5541                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5542
5543         for (i = 0; i < hw->num_tc; i++) {
5544                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5545                 dcb_info->tc_queue.tc_txq[0][i].base =
5546                                                 hw->tc_queue[i].tqp_offset;
5547                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5548                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5549                                                 hw->tc_queue[i].tqp_count;
5550         }
5551         rte_spinlock_unlock(&hw->lock);
5552
5553         return 0;
5554 }
5555
5556 static int
5557 hns3_reinit_dev(struct hns3_adapter *hns)
5558 {
5559         struct hns3_hw *hw = &hns->hw;
5560         int ret;
5561
5562         ret = hns3_cmd_init(hw);
5563         if (ret) {
5564                 hns3_err(hw, "Failed to init cmd: %d", ret);
5565                 return ret;
5566         }
5567
5568         ret = hns3_reset_all_tqps(hns);
5569         if (ret) {
5570                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5571                 return ret;
5572         }
5573
5574         ret = hns3_init_hardware(hns);
5575         if (ret) {
5576                 hns3_err(hw, "Failed to init hardware: %d", ret);
5577                 return ret;
5578         }
5579
5580         ret = hns3_enable_hw_error_intr(hns, true);
5581         if (ret) {
5582                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5583                              ret);
5584                 return ret;
5585         }
5586         hns3_info(hw, "Reset done, driver initialization finished.");
5587
5588         return 0;
5589 }
5590
5591 static bool
5592 is_pf_reset_done(struct hns3_hw *hw)
5593 {
5594         uint32_t val, reg, reg_bit;
5595
5596         switch (hw->reset.level) {
5597         case HNS3_IMP_RESET:
5598                 reg = HNS3_GLOBAL_RESET_REG;
5599                 reg_bit = HNS3_IMP_RESET_BIT;
5600                 break;
5601         case HNS3_GLOBAL_RESET:
5602                 reg = HNS3_GLOBAL_RESET_REG;
5603                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5604                 break;
5605         case HNS3_FUNC_RESET:
5606                 reg = HNS3_FUN_RST_ING;
5607                 reg_bit = HNS3_FUN_RST_ING_B;
5608                 break;
5609         case HNS3_FLR_RESET:
5610         default:
5611                 hns3_err(hw, "Wait for unsupported reset level: %d",
5612                          hw->reset.level);
5613                 return true;
5614         }
5615         val = hns3_read_dev(hw, reg);
5616         if (hns3_get_bit(val, reg_bit))
5617                 return false;
5618         else
5619                 return true;
5620 }
5621
5622 bool
5623 hns3_is_reset_pending(struct hns3_adapter *hns)
5624 {
5625         struct hns3_hw *hw = &hns->hw;
5626         enum hns3_reset_level reset;
5627
5628         hns3_check_event_cause(hns, NULL);
5629         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5630         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5631                 hns3_warn(hw, "High level reset %d is pending", reset);
5632                 return true;
5633         }
5634         reset = hns3_get_reset_level(hns, &hw->reset.request);
5635         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5636                 hns3_warn(hw, "High level reset %d is request", reset);
5637                 return true;
5638         }
5639         return false;
5640 }
5641
5642 static int
5643 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5644 {
5645         struct hns3_hw *hw = &hns->hw;
5646         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5647         struct timeval tv;
5648
5649         if (wait_data->result == HNS3_WAIT_SUCCESS)
5650                 return 0;
5651         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5652                 gettimeofday(&tv, NULL);
5653                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5654                           tv.tv_sec, tv.tv_usec);
5655                 return -ETIME;
5656         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5657                 return -EAGAIN;
5658
5659         wait_data->hns = hns;
5660         wait_data->check_completion = is_pf_reset_done;
5661         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5662                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5663         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5664         wait_data->count = HNS3_RESET_WAIT_CNT;
5665         wait_data->result = HNS3_WAIT_REQUEST;
5666         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5667         return -EAGAIN;
5668 }
5669
5670 static int
5671 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5672 {
5673         struct hns3_cmd_desc desc;
5674         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5675
5676         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5677         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5678         req->fun_reset_vfid = func_id;
5679
5680         return hns3_cmd_send(hw, &desc, 1);
5681 }
5682
5683 static int
5684 hns3_imp_reset_cmd(struct hns3_hw *hw)
5685 {
5686         struct hns3_cmd_desc desc;
5687
5688         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5689         desc.data[0] = 0xeedd;
5690
5691         return hns3_cmd_send(hw, &desc, 1);
5692 }
5693
5694 static void
5695 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5696 {
5697         struct hns3_hw *hw = &hns->hw;
5698         struct timeval tv;
5699         uint32_t val;
5700
5701         gettimeofday(&tv, NULL);
5702         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5703             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5704                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5705                           tv.tv_sec, tv.tv_usec);
5706                 return;
5707         }
5708
5709         switch (reset_level) {
5710         case HNS3_IMP_RESET:
5711                 hns3_imp_reset_cmd(hw);
5712                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5713                           tv.tv_sec, tv.tv_usec);
5714                 break;
5715         case HNS3_GLOBAL_RESET:
5716                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5717                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5718                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5719                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5720                           tv.tv_sec, tv.tv_usec);
5721                 break;
5722         case HNS3_FUNC_RESET:
5723                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5724                           tv.tv_sec, tv.tv_usec);
5725                 /* schedule again to check later */
5726                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5727                 hns3_schedule_reset(hns);
5728                 break;
5729         default:
5730                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5731                 return;
5732         }
5733         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5734 }
5735
5736 static enum hns3_reset_level
5737 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5738 {
5739         struct hns3_hw *hw = &hns->hw;
5740         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5741
5742         /* Return the highest priority reset level amongst all */
5743         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5744                 reset_level = HNS3_IMP_RESET;
5745         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5746                 reset_level = HNS3_GLOBAL_RESET;
5747         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5748                 reset_level = HNS3_FUNC_RESET;
5749         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5750                 reset_level = HNS3_FLR_RESET;
5751
5752         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5753                 return HNS3_NONE_RESET;
5754
5755         return reset_level;
5756 }
5757
5758 static void
5759 hns3_record_imp_error(struct hns3_adapter *hns)
5760 {
5761         struct hns3_hw *hw = &hns->hw;
5762         uint32_t reg_val;
5763
5764         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5765         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5766                 hns3_warn(hw, "Detected IMP RD poison!");
5767                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5768                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5769                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5770         }
5771
5772         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5773                 hns3_warn(hw, "Detected IMP CMDQ error!");
5774                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5775                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5776                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5777         }
5778 }
5779
5780 static int
5781 hns3_prepare_reset(struct hns3_adapter *hns)
5782 {
5783         struct hns3_hw *hw = &hns->hw;
5784         uint32_t reg_val;
5785         int ret;
5786
5787         switch (hw->reset.level) {
5788         case HNS3_FUNC_RESET:
5789                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5790                 if (ret)
5791                         return ret;
5792
5793                 /*
5794                  * After performaning pf reset, it is not necessary to do the
5795                  * mailbox handling or send any command to firmware, because
5796                  * any mailbox handling or command to firmware is only valid
5797                  * after hns3_cmd_init is called.
5798                  */
5799                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5800                 hw->reset.stats.request_cnt++;
5801                 break;
5802         case HNS3_IMP_RESET:
5803                 hns3_record_imp_error(hns);
5804                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5805                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5806                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5807                 break;
5808         default:
5809                 break;
5810         }
5811         return 0;
5812 }
5813
5814 static int
5815 hns3_set_rst_done(struct hns3_hw *hw)
5816 {
5817         struct hns3_pf_rst_done_cmd *req;
5818         struct hns3_cmd_desc desc;
5819
5820         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5821         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5822         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5823         return hns3_cmd_send(hw, &desc, 1);
5824 }
5825
5826 static int
5827 hns3_stop_service(struct hns3_adapter *hns)
5828 {
5829         struct hns3_hw *hw = &hns->hw;
5830         struct rte_eth_dev *eth_dev;
5831
5832         eth_dev = &rte_eth_devices[hw->data->port_id];
5833         if (hw->adapter_state == HNS3_NIC_STARTED) {
5834                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5835                 hns3_update_link_status_and_event(hw);
5836         }
5837         hw->mac.link_status = ETH_LINK_DOWN;
5838
5839         hns3_set_rxtx_function(eth_dev);
5840         rte_wmb();
5841         /* Disable datapath on secondary process. */
5842         hns3_mp_req_stop_rxtx(eth_dev);
5843         rte_delay_ms(hw->tqps_num);
5844
5845         rte_spinlock_lock(&hw->lock);
5846         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5847             hw->adapter_state == HNS3_NIC_STOPPING) {
5848                 hns3_enable_all_queues(hw, false);
5849                 hns3_do_stop(hns);
5850                 hw->reset.mbuf_deferred_free = true;
5851         } else
5852                 hw->reset.mbuf_deferred_free = false;
5853
5854         /*
5855          * It is cumbersome for hardware to pick-and-choose entries for deletion
5856          * from table space. Hence, for function reset software intervention is
5857          * required to delete the entries
5858          */
5859         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5860                 hns3_configure_all_mc_mac_addr(hns, true);
5861         rte_spinlock_unlock(&hw->lock);
5862
5863         return 0;
5864 }
5865
5866 static int
5867 hns3_start_service(struct hns3_adapter *hns)
5868 {
5869         struct hns3_hw *hw = &hns->hw;
5870         struct rte_eth_dev *eth_dev;
5871
5872         if (hw->reset.level == HNS3_IMP_RESET ||
5873             hw->reset.level == HNS3_GLOBAL_RESET)
5874                 hns3_set_rst_done(hw);
5875         eth_dev = &rte_eth_devices[hw->data->port_id];
5876         hns3_set_rxtx_function(eth_dev);
5877         hns3_mp_req_start_rxtx(eth_dev);
5878         if (hw->adapter_state == HNS3_NIC_STARTED) {
5879                 /*
5880                  * This API parent function already hold the hns3_hw.lock, the
5881                  * hns3_service_handler may report lse, in bonding application
5882                  * it will call driver's ops which may acquire the hns3_hw.lock
5883                  * again, thus lead to deadlock.
5884                  * We defer calls hns3_service_handler to avoid the deadlock.
5885                  */
5886                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5887                                   hns3_service_handler, eth_dev);
5888
5889                 /* Enable interrupt of all rx queues before enabling queues */
5890                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5891                 /*
5892                  * Enable state of each rxq and txq will be recovered after
5893                  * reset, so we need to restore them before enable all tqps;
5894                  */
5895                 hns3_restore_tqp_enable_state(hw);
5896                 /*
5897                  * When finished the initialization, enable queues to receive
5898                  * and transmit packets.
5899                  */
5900                 hns3_enable_all_queues(hw, true);
5901         }
5902
5903         return 0;
5904 }
5905
5906 static int
5907 hns3_restore_conf(struct hns3_adapter *hns)
5908 {
5909         struct hns3_hw *hw = &hns->hw;
5910         int ret;
5911
5912         ret = hns3_configure_all_mac_addr(hns, false);
5913         if (ret)
5914                 return ret;
5915
5916         ret = hns3_configure_all_mc_mac_addr(hns, false);
5917         if (ret)
5918                 goto err_mc_mac;
5919
5920         ret = hns3_dev_promisc_restore(hns);
5921         if (ret)
5922                 goto err_promisc;
5923
5924         ret = hns3_restore_vlan_table(hns);
5925         if (ret)
5926                 goto err_promisc;
5927
5928         ret = hns3_restore_vlan_conf(hns);
5929         if (ret)
5930                 goto err_promisc;
5931
5932         ret = hns3_restore_all_fdir_filter(hns);
5933         if (ret)
5934                 goto err_promisc;
5935
5936         ret = hns3_restore_rx_interrupt(hw);
5937         if (ret)
5938                 goto err_promisc;
5939
5940         ret = hns3_restore_gro_conf(hw);
5941         if (ret)
5942                 goto err_promisc;
5943
5944         ret = hns3_restore_fec(hw);
5945         if (ret)
5946                 goto err_promisc;
5947
5948         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5949                 ret = hns3_do_start(hns, false);
5950                 if (ret)
5951                         goto err_promisc;
5952                 hns3_info(hw, "hns3 dev restart successful!");
5953         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5954                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5955         return 0;
5956
5957 err_promisc:
5958         hns3_configure_all_mc_mac_addr(hns, true);
5959 err_mc_mac:
5960         hns3_configure_all_mac_addr(hns, true);
5961         return ret;
5962 }
5963
5964 static void
5965 hns3_reset_service(void *param)
5966 {
5967         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5968         struct hns3_hw *hw = &hns->hw;
5969         enum hns3_reset_level reset_level;
5970         struct timeval tv_delta;
5971         struct timeval tv_start;
5972         struct timeval tv;
5973         uint64_t msec;
5974         int ret;
5975
5976         /*
5977          * The interrupt is not triggered within the delay time.
5978          * The interrupt may have been lost. It is necessary to handle
5979          * the interrupt to recover from the error.
5980          */
5981         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5982                             SCHEDULE_DEFERRED) {
5983                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5984                                   __ATOMIC_RELAXED);
5985                 hns3_err(hw, "Handling interrupts in delayed tasks");
5986                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5987                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5988                 if (reset_level == HNS3_NONE_RESET) {
5989                         hns3_err(hw, "No reset level is set, try IMP reset");
5990                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5991                 }
5992         }
5993         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5994
5995         /*
5996          * Check if there is any ongoing reset in the hardware. This status can
5997          * be checked from reset_pending. If there is then, we need to wait for
5998          * hardware to complete reset.
5999          *    a. If we are able to figure out in reasonable time that hardware
6000          *       has fully resetted then, we can proceed with driver, client
6001          *       reset.
6002          *    b. else, we can come back later to check this status so re-sched
6003          *       now.
6004          */
6005         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6006         if (reset_level != HNS3_NONE_RESET) {
6007                 gettimeofday(&tv_start, NULL);
6008                 ret = hns3_reset_process(hns, reset_level);
6009                 gettimeofday(&tv, NULL);
6010                 timersub(&tv, &tv_start, &tv_delta);
6011                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6012                        tv_delta.tv_usec / USEC_PER_MSEC;
6013                 if (msec > HNS3_RESET_PROCESS_MS)
6014                         hns3_err(hw, "%d handle long time delta %" PRIx64
6015                                      " ms time=%ld.%.6ld",
6016                                  hw->reset.level, msec,
6017                                  tv.tv_sec, tv.tv_usec);
6018                 if (ret == -EAGAIN)
6019                         return;
6020         }
6021
6022         /* Check if we got any *new* reset requests to be honored */
6023         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6024         if (reset_level != HNS3_NONE_RESET)
6025                 hns3_msix_process(hns, reset_level);
6026 }
6027
6028 static unsigned int
6029 hns3_get_speed_capa_num(uint16_t device_id)
6030 {
6031         unsigned int num;
6032
6033         switch (device_id) {
6034         case HNS3_DEV_ID_25GE:
6035         case HNS3_DEV_ID_25GE_RDMA:
6036                 num = 2;
6037                 break;
6038         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6039         case HNS3_DEV_ID_200G_RDMA:
6040                 num = 1;
6041                 break;
6042         default:
6043                 num = 0;
6044                 break;
6045         }
6046
6047         return num;
6048 }
6049
6050 static int
6051 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6052                         uint16_t device_id)
6053 {
6054         switch (device_id) {
6055         case HNS3_DEV_ID_25GE:
6056         /* fallthrough */
6057         case HNS3_DEV_ID_25GE_RDMA:
6058                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6059                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6060
6061                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6062                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6063                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6064                 break;
6065         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6066                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6067                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6068                 break;
6069         case HNS3_DEV_ID_200G_RDMA:
6070                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6071                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6072                 break;
6073         default:
6074                 return -ENOTSUP;
6075         }
6076
6077         return 0;
6078 }
6079
6080 static int
6081 hns3_fec_get_capability(struct rte_eth_dev *dev,
6082                         struct rte_eth_fec_capa *speed_fec_capa,
6083                         unsigned int num)
6084 {
6085         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6086         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6087         uint16_t device_id = pci_dev->id.device_id;
6088         unsigned int capa_num;
6089         int ret;
6090
6091         capa_num = hns3_get_speed_capa_num(device_id);
6092         if (capa_num == 0) {
6093                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6094                          device_id);
6095                 return -ENOTSUP;
6096         }
6097
6098         if (speed_fec_capa == NULL || num < capa_num)
6099                 return capa_num;
6100
6101         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6102         if (ret)
6103                 return -ENOTSUP;
6104
6105         return capa_num;
6106 }
6107
6108 static int
6109 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6110 {
6111         struct hns3_config_fec_cmd *req;
6112         struct hns3_cmd_desc desc;
6113         int ret;
6114
6115         /*
6116          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6117          * in device of link speed
6118          * below 10 Gbps.
6119          */
6120         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6121                 *state = 0;
6122                 return 0;
6123         }
6124
6125         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6126         req = (struct hns3_config_fec_cmd *)desc.data;
6127         ret = hns3_cmd_send(hw, &desc, 1);
6128         if (ret) {
6129                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6130                          ret);
6131                 return ret;
6132         }
6133
6134         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6135         return 0;
6136 }
6137
6138 static int
6139 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6140 {
6141 #define QUERY_ACTIVE_SPEED      1
6142         struct hns3_sfp_speed_cmd *resp;
6143         uint32_t tmp_fec_capa;
6144         uint8_t auto_state;
6145         struct hns3_cmd_desc desc;
6146         int ret;
6147
6148         /*
6149          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6150          * configured FEC mode is returned.
6151          * If link is up, current FEC mode is returned.
6152          */
6153         if (hw->mac.link_status == ETH_LINK_DOWN) {
6154                 ret = get_current_fec_auto_state(hw, &auto_state);
6155                 if (ret)
6156                         return ret;
6157
6158                 if (auto_state == 0x1) {
6159                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6160                         return 0;
6161                 }
6162         }
6163
6164         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6165         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6166         resp->query_type = QUERY_ACTIVE_SPEED;
6167
6168         ret = hns3_cmd_send(hw, &desc, 1);
6169         if (ret == -EOPNOTSUPP) {
6170                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6171                 return ret;
6172         } else if (ret) {
6173                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6174                 return ret;
6175         }
6176
6177         /*
6178          * FEC mode order defined in hns3 hardware is inconsistend with
6179          * that defined in the ethdev library. So the sequence needs
6180          * to be converted.
6181          */
6182         switch (resp->active_fec) {
6183         case HNS3_HW_FEC_MODE_NOFEC:
6184                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6185                 break;
6186         case HNS3_HW_FEC_MODE_BASER:
6187                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6188                 break;
6189         case HNS3_HW_FEC_MODE_RS:
6190                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6191                 break;
6192         default:
6193                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6194                 break;
6195         }
6196
6197         *fec_capa = tmp_fec_capa;
6198         return 0;
6199 }
6200
6201 static int
6202 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6203 {
6204         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6205
6206         return hns3_fec_get_internal(hw, fec_capa);
6207 }
6208
6209 static int
6210 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6211 {
6212         struct hns3_config_fec_cmd *req;
6213         struct hns3_cmd_desc desc;
6214         int ret;
6215
6216         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6217
6218         req = (struct hns3_config_fec_cmd *)desc.data;
6219         switch (mode) {
6220         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6221                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6222                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6223                 break;
6224         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6225                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6226                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6227                 break;
6228         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6229                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6230                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6231                 break;
6232         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6233                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6234                 break;
6235         default:
6236                 return 0;
6237         }
6238         ret = hns3_cmd_send(hw, &desc, 1);
6239         if (ret)
6240                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6241
6242         return ret;
6243 }
6244
6245 static uint32_t
6246 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6247 {
6248         struct hns3_mac *mac = &hw->mac;
6249         uint32_t cur_capa;
6250
6251         switch (mac->link_speed) {
6252         case ETH_SPEED_NUM_10G:
6253                 cur_capa = fec_capa[1].capa;
6254                 break;
6255         case ETH_SPEED_NUM_25G:
6256         case ETH_SPEED_NUM_100G:
6257         case ETH_SPEED_NUM_200G:
6258                 cur_capa = fec_capa[0].capa;
6259                 break;
6260         default:
6261                 cur_capa = 0;
6262                 break;
6263         }
6264
6265         return cur_capa;
6266 }
6267
6268 static bool
6269 is_fec_mode_one_bit_set(uint32_t mode)
6270 {
6271         int cnt = 0;
6272         uint8_t i;
6273
6274         for (i = 0; i < sizeof(mode); i++)
6275                 if (mode >> i & 0x1)
6276                         cnt++;
6277
6278         return cnt == 1 ? true : false;
6279 }
6280
6281 static int
6282 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6283 {
6284 #define FEC_CAPA_NUM 2
6285         struct hns3_adapter *hns = dev->data->dev_private;
6286         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6287         struct hns3_pf *pf = &hns->pf;
6288
6289         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6290         uint32_t cur_capa;
6291         uint32_t num = FEC_CAPA_NUM;
6292         int ret;
6293
6294         ret = hns3_fec_get_capability(dev, fec_capa, num);
6295         if (ret < 0)
6296                 return ret;
6297
6298         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6299         if (!is_fec_mode_one_bit_set(mode))
6300                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6301                              "FEC mode should be only one bit set", mode);
6302
6303         /*
6304          * Check whether the configured mode is within the FEC capability.
6305          * If not, the configured mode will not be supported.
6306          */
6307         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6308         if (!(cur_capa & mode)) {
6309                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6310                 return -EINVAL;
6311         }
6312
6313         ret = hns3_set_fec_hw(hw, mode);
6314         if (ret)
6315                 return ret;
6316
6317         pf->fec_mode = mode;
6318         return 0;
6319 }
6320
6321 static int
6322 hns3_restore_fec(struct hns3_hw *hw)
6323 {
6324         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6325         struct hns3_pf *pf = &hns->pf;
6326         uint32_t mode = pf->fec_mode;
6327         int ret;
6328
6329         ret = hns3_set_fec_hw(hw, mode);
6330         if (ret)
6331                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6332                          mode, ret);
6333
6334         return ret;
6335 }
6336
6337 static int
6338 hns3_query_dev_fec_info(struct hns3_hw *hw)
6339 {
6340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6341         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6342         int ret;
6343
6344         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6345         if (ret)
6346                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6347
6348         return ret;
6349 }
6350
6351 static bool
6352 hns3_optical_module_existed(struct hns3_hw *hw)
6353 {
6354         struct hns3_cmd_desc desc;
6355         bool existed;
6356         int ret;
6357
6358         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6359         ret = hns3_cmd_send(hw, &desc, 1);
6360         if (ret) {
6361                 hns3_err(hw,
6362                          "fail to get optical module exist state, ret = %d.\n",
6363                          ret);
6364                 return false;
6365         }
6366         existed = !!desc.data[0];
6367
6368         return existed;
6369 }
6370
6371 static int
6372 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6373                                 uint32_t len, uint8_t *data)
6374 {
6375 #define HNS3_SFP_INFO_CMD_NUM 6
6376 #define HNS3_SFP_INFO_MAX_LEN \
6377         (HNS3_SFP_INFO_BD0_LEN + \
6378         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6379         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6380         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6381         uint16_t read_len;
6382         uint16_t copy_len;
6383         int ret;
6384         int i;
6385
6386         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6387                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6388                                           true);
6389                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6390                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6391         }
6392
6393         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6394         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6395         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6396         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6397
6398         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6399         if (ret) {
6400                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6401                                 ret);
6402                 return ret;
6403         }
6404
6405         /* The data format in BD0 is different with the others. */
6406         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6407         memcpy(data, sfp_info_bd0->data, copy_len);
6408         read_len = copy_len;
6409
6410         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6411                 if (read_len >= len)
6412                         break;
6413
6414                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6415                 memcpy(data + read_len, desc[i].data, copy_len);
6416                 read_len += copy_len;
6417         }
6418
6419         return (int)read_len;
6420 }
6421
6422 static int
6423 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6424                        struct rte_dev_eeprom_info *info)
6425 {
6426         struct hns3_adapter *hns = dev->data->dev_private;
6427         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6428         uint32_t offset = info->offset;
6429         uint32_t len = info->length;
6430         uint8_t *data = info->data;
6431         uint32_t read_len = 0;
6432
6433         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6434                 return -ENOTSUP;
6435
6436         if (!hns3_optical_module_existed(hw)) {
6437                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6438                 return -EIO;
6439         }
6440
6441         while (read_len < len) {
6442                 int ret;
6443                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6444                                                   len - read_len,
6445                                                   data + read_len);
6446                 if (ret < 0)
6447                         return -EIO;
6448                 read_len += ret;
6449         }
6450
6451         return 0;
6452 }
6453
6454 static int
6455 hns3_get_module_info(struct rte_eth_dev *dev,
6456                      struct rte_eth_dev_module_info *modinfo)
6457 {
6458 #define HNS3_SFF8024_ID_SFP             0x03
6459 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6460 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6461 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6462 #define HNS3_SFF_8636_V1_3              0x03
6463         struct hns3_adapter *hns = dev->data->dev_private;
6464         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6465         struct rte_dev_eeprom_info info;
6466         struct hns3_sfp_type sfp_type;
6467         int ret;
6468
6469         memset(&sfp_type, 0, sizeof(sfp_type));
6470         memset(&info, 0, sizeof(info));
6471         info.data = (uint8_t *)&sfp_type;
6472         info.length = sizeof(sfp_type);
6473         ret = hns3_get_module_eeprom(dev, &info);
6474         if (ret)
6475                 return ret;
6476
6477         switch (sfp_type.type) {
6478         case HNS3_SFF8024_ID_SFP:
6479                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6480                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6481                 break;
6482         case HNS3_SFF8024_ID_QSFP_8438:
6483                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6484                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6485                 break;
6486         case HNS3_SFF8024_ID_QSFP_8436_8636:
6487                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6488                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6489                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6490                 } else {
6491                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6492                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6493                 }
6494                 break;
6495         case HNS3_SFF8024_ID_QSFP28_8636:
6496                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6497                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6498                 break;
6499         default:
6500                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6501                          sfp_type.type, sfp_type.ext_type);
6502                 return -EINVAL;
6503         }
6504
6505         return 0;
6506 }
6507
6508 static const struct eth_dev_ops hns3_eth_dev_ops = {
6509         .dev_configure      = hns3_dev_configure,
6510         .dev_start          = hns3_dev_start,
6511         .dev_stop           = hns3_dev_stop,
6512         .dev_close          = hns3_dev_close,
6513         .promiscuous_enable = hns3_dev_promiscuous_enable,
6514         .promiscuous_disable = hns3_dev_promiscuous_disable,
6515         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6516         .allmulticast_disable = hns3_dev_allmulticast_disable,
6517         .mtu_set            = hns3_dev_mtu_set,
6518         .stats_get          = hns3_stats_get,
6519         .stats_reset        = hns3_stats_reset,
6520         .xstats_get         = hns3_dev_xstats_get,
6521         .xstats_get_names   = hns3_dev_xstats_get_names,
6522         .xstats_reset       = hns3_dev_xstats_reset,
6523         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6524         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6525         .dev_infos_get          = hns3_dev_infos_get,
6526         .fw_version_get         = hns3_fw_version_get,
6527         .rx_queue_setup         = hns3_rx_queue_setup,
6528         .tx_queue_setup         = hns3_tx_queue_setup,
6529         .rx_queue_release       = hns3_dev_rx_queue_release,
6530         .tx_queue_release       = hns3_dev_tx_queue_release,
6531         .rx_queue_start         = hns3_dev_rx_queue_start,
6532         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6533         .tx_queue_start         = hns3_dev_tx_queue_start,
6534         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6535         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6536         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6537         .rxq_info_get           = hns3_rxq_info_get,
6538         .txq_info_get           = hns3_txq_info_get,
6539         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6540         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6541         .flow_ctrl_get          = hns3_flow_ctrl_get,
6542         .flow_ctrl_set          = hns3_flow_ctrl_set,
6543         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6544         .mac_addr_add           = hns3_add_mac_addr,
6545         .mac_addr_remove        = hns3_remove_mac_addr,
6546         .mac_addr_set           = hns3_set_default_mac_addr,
6547         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6548         .link_update            = hns3_dev_link_update,
6549         .rss_hash_update        = hns3_dev_rss_hash_update,
6550         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6551         .reta_update            = hns3_dev_rss_reta_update,
6552         .reta_query             = hns3_dev_rss_reta_query,
6553         .filter_ctrl            = hns3_dev_filter_ctrl,
6554         .vlan_filter_set        = hns3_vlan_filter_set,
6555         .vlan_tpid_set          = hns3_vlan_tpid_set,
6556         .vlan_offload_set       = hns3_vlan_offload_set,
6557         .vlan_pvid_set          = hns3_vlan_pvid_set,
6558         .get_reg                = hns3_get_regs,
6559         .get_module_info        = hns3_get_module_info,
6560         .get_module_eeprom      = hns3_get_module_eeprom,
6561         .get_dcb_info           = hns3_get_dcb_info,
6562         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6563         .fec_get_capability     = hns3_fec_get_capability,
6564         .fec_get                = hns3_fec_get,
6565         .fec_set                = hns3_fec_set,
6566         .tm_ops_get             = hns3_tm_ops_get,
6567         .tx_done_cleanup        = hns3_tx_done_cleanup,
6568 };
6569
6570 static const struct hns3_reset_ops hns3_reset_ops = {
6571         .reset_service       = hns3_reset_service,
6572         .stop_service        = hns3_stop_service,
6573         .prepare_reset       = hns3_prepare_reset,
6574         .wait_hardware_ready = hns3_wait_hardware_ready,
6575         .reinit_dev          = hns3_reinit_dev,
6576         .restore_conf        = hns3_restore_conf,
6577         .start_service       = hns3_start_service,
6578 };
6579
6580 static int
6581 hns3_dev_init(struct rte_eth_dev *eth_dev)
6582 {
6583         struct hns3_adapter *hns = eth_dev->data->dev_private;
6584         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6585         struct rte_ether_addr *eth_addr;
6586         struct hns3_hw *hw = &hns->hw;
6587         int ret;
6588
6589         PMD_INIT_FUNC_TRACE();
6590
6591         eth_dev->process_private = (struct hns3_process_private *)
6592             rte_zmalloc_socket("hns3_filter_list",
6593                                sizeof(struct hns3_process_private),
6594                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6595         if (eth_dev->process_private == NULL) {
6596                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6597                 return -ENOMEM;
6598         }
6599         /* initialize flow filter lists */
6600         hns3_filterlist_init(eth_dev);
6601
6602         hns3_set_rxtx_function(eth_dev);
6603         eth_dev->dev_ops = &hns3_eth_dev_ops;
6604         eth_dev->rx_queue_count = hns3_rx_queue_count;
6605         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6606                 ret = hns3_mp_init_secondary();
6607                 if (ret) {
6608                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6609                                      "process, ret = %d", ret);
6610                         goto err_mp_init_secondary;
6611                 }
6612
6613                 hw->secondary_cnt++;
6614                 return 0;
6615         }
6616
6617         ret = hns3_mp_init_primary();
6618         if (ret) {
6619                 PMD_INIT_LOG(ERR,
6620                              "Failed to init for primary process, ret = %d",
6621                              ret);
6622                 goto err_mp_init_primary;
6623         }
6624
6625         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6626         hns->is_vf = false;
6627         hw->data = eth_dev->data;
6628
6629         /*
6630          * Set default max packet size according to the mtu
6631          * default vale in DPDK frame.
6632          */
6633         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6634
6635         ret = hns3_reset_init(hw);
6636         if (ret)
6637                 goto err_init_reset;
6638         hw->reset.ops = &hns3_reset_ops;
6639
6640         ret = hns3_init_pf(eth_dev);
6641         if (ret) {
6642                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6643                 goto err_init_pf;
6644         }
6645
6646         /* Allocate memory for storing MAC addresses */
6647         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6648                                                sizeof(struct rte_ether_addr) *
6649                                                HNS3_UC_MACADDR_NUM, 0);
6650         if (eth_dev->data->mac_addrs == NULL) {
6651                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6652                              "to store MAC addresses",
6653                              sizeof(struct rte_ether_addr) *
6654                              HNS3_UC_MACADDR_NUM);
6655                 ret = -ENOMEM;
6656                 goto err_rte_zmalloc;
6657         }
6658
6659         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6660         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6661                 rte_eth_random_addr(hw->mac.mac_addr);
6662                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6663                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6664                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6665                           "unicast address, using random MAC address %s",
6666                           mac_str);
6667         }
6668         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6669                             &eth_dev->data->mac_addrs[0]);
6670
6671         hw->adapter_state = HNS3_NIC_INITIALIZED;
6672
6673         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6674                             SCHEDULE_PENDING) {
6675                 hns3_err(hw, "Reschedule reset service after dev_init");
6676                 hns3_schedule_reset(hns);
6677         } else {
6678                 /* IMP will wait ready flag before reset */
6679                 hns3_notify_reset_ready(hw, false);
6680         }
6681
6682         hns3_info(hw, "hns3 dev initialization successful!");
6683         return 0;
6684
6685 err_rte_zmalloc:
6686         hns3_uninit_pf(eth_dev);
6687
6688 err_init_pf:
6689         rte_free(hw->reset.wait_data);
6690
6691 err_init_reset:
6692         hns3_mp_uninit_primary();
6693
6694 err_mp_init_primary:
6695 err_mp_init_secondary:
6696         eth_dev->dev_ops = NULL;
6697         eth_dev->rx_pkt_burst = NULL;
6698         eth_dev->tx_pkt_burst = NULL;
6699         eth_dev->tx_pkt_prepare = NULL;
6700         rte_free(eth_dev->process_private);
6701         eth_dev->process_private = NULL;
6702         return ret;
6703 }
6704
6705 static int
6706 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6707 {
6708         struct hns3_adapter *hns = eth_dev->data->dev_private;
6709         struct hns3_hw *hw = &hns->hw;
6710
6711         PMD_INIT_FUNC_TRACE();
6712
6713         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6714                 rte_free(eth_dev->process_private);
6715                 eth_dev->process_private = NULL;
6716                 return 0;
6717         }
6718
6719         if (hw->adapter_state < HNS3_NIC_CLOSING)
6720                 hns3_dev_close(eth_dev);
6721
6722         hw->adapter_state = HNS3_NIC_REMOVED;
6723         return 0;
6724 }
6725
6726 static int
6727 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6728                    struct rte_pci_device *pci_dev)
6729 {
6730         return rte_eth_dev_pci_generic_probe(pci_dev,
6731                                              sizeof(struct hns3_adapter),
6732                                              hns3_dev_init);
6733 }
6734
6735 static int
6736 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6737 {
6738         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6739 }
6740
6741 static const struct rte_pci_id pci_id_hns3_map[] = {
6742         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6743         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6744         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6745         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6746         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6747         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6748         { .vendor_id = 0, }, /* sentinel */
6749 };
6750
6751 static struct rte_pci_driver rte_hns3_pmd = {
6752         .id_table = pci_id_hns3_map,
6753         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6754         .probe = eth_hns3_pci_probe,
6755         .remove = eth_hns3_pci_remove,
6756 };
6757
6758 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6759 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6760 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6761 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6762 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);