drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27
  28 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  29 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  30
  31 int hns3_logtype_init;
  32 int hns3_logtype_driver;
  33
  34 static int
  35 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
  36                 unsigned int tso_mss_max)
  37 {
  38         struct hns3_cfg_tso_status_cmd *req;
  39         struct hns3_cmd_desc desc;
  40         uint16_t tso_mss;
  41
  42         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
  43
  44         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
  45
  46         tso_mss = 0;
  47         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  48                        tso_mss_min);
  49         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
  50
  51         tso_mss = 0;
  52         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  53                        tso_mss_max);
  54         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
  55
  56         return hns3_cmd_send(hw, &desc, 1);
  57 }
  58
  59 int
  60 hns3_config_gro(struct hns3_hw *hw, bool en)
  61 {
  62         struct hns3_cfg_gro_status_cmd *req;
  63         struct hns3_cmd_desc desc;
  64         int ret;
  65
  66         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
  67         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
  68
  69         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
  70
  71         ret = hns3_cmd_send(hw, &desc, 1);
  72         if (ret)
  73                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
  74
  75         return ret;
  76 }
  77
  78 static int
  79 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
  80                    uint16_t *allocated_size, bool is_alloc)
  81 {
  82         struct hns3_umv_spc_alc_cmd *req;
  83         struct hns3_cmd_desc desc;
  84         int ret;
  85
  86         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
  87         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
  88         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
  89         req->space_size = rte_cpu_to_le_32(space_size);
  90
  91         ret = hns3_cmd_send(hw, &desc, 1);
  92         if (ret) {
  93                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
  94                              is_alloc ? "allocate" : "free", ret);
  95                 return ret;
  96         }
  97
  98         if (is_alloc && allocated_size)
  99                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 100
 101         return 0;
 102 }
 103
 104 static int
 105 hns3_init_umv_space(struct hns3_hw *hw)
 106 {
 107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 108         struct hns3_pf *pf = &hns->pf;
 109         uint16_t allocated_size = 0;
 110         int ret;
 111
 112         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 113                                  true);
 114         if (ret)
 115                 return ret;
 116
 117         if (allocated_size < pf->wanted_umv_size)
 118                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 119                              pf->wanted_umv_size, allocated_size);
 120
 121         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 122                                                 pf->wanted_umv_size;
 123         pf->used_umv_size = 0;
 124         return 0;
 125 }
 126
 127 static int
 128 hns3_uninit_umv_space(struct hns3_hw *hw)
 129 {
 130         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 131         struct hns3_pf *pf = &hns->pf;
 132         int ret;
 133
 134         if (pf->max_umv_size == 0)
 135                 return 0;
 136
 137         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 138         if (ret)
 139                 return ret;
 140
 141         pf->max_umv_size = 0;
 142
 143         return 0;
 144 }
 145
 146 static bool
 147 hns3_is_umv_space_full(struct hns3_hw *hw)
 148 {
 149         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 150         struct hns3_pf *pf = &hns->pf;
 151         bool is_full;
 152
 153         is_full = (pf->used_umv_size >= pf->max_umv_size);
 154
 155         return is_full;
 156 }
 157
 158 static void
 159 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 160 {
 161         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 162         struct hns3_pf *pf = &hns->pf;
 163
 164         if (is_free) {
 165                 if (pf->used_umv_size > 0)
 166                         pf->used_umv_size--;
 167         } else
 168                 pf->used_umv_size++;
 169 }
 170
 171 static void
 172 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 173                       const uint8_t *addr, bool is_mc)
 174 {
 175         const unsigned char *mac_addr = addr;
 176         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 177                             ((uint32_t)mac_addr[2] << 16) |
 178                             ((uint32_t)mac_addr[1] << 8) |
 179                             (uint32_t)mac_addr[0];
 180         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 181
 182         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 183         if (is_mc) {
 184                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 185                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 186                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 187         }
 188
 189         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 190         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 191 }
 192
 193 static int
 194 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 195                              uint8_t resp_code,
 196                              enum hns3_mac_vlan_tbl_opcode op)
 197 {
 198         if (cmdq_resp) {
 199                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 200                          cmdq_resp);
 201                 return -EIO;
 202         }
 203
 204         if (op == HNS3_MAC_VLAN_ADD) {
 205                 if (resp_code == 0 || resp_code == 1) {
 206                         return 0;
 207                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 208                         hns3_err(hw, "add mac addr failed for uc_overflow");
 209                         return -ENOSPC;
 210                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 211                         hns3_err(hw, "add mac addr failed for mc_overflow");
 212                         return -ENOSPC;
 213                 }
 214
 215                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 216                          resp_code);
 217                 return -EIO;
 218         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 219                 if (resp_code == 0) {
 220                         return 0;
 221                 } else if (resp_code == 1) {
 222                         hns3_dbg(hw, "remove mac addr failed for miss");
 223                         return -ENOENT;
 224                 }
 225
 226                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 227                          resp_code);
 228                 return -EIO;
 229         } else if (op == HNS3_MAC_VLAN_LKUP) {
 230                 if (resp_code == 0) {
 231                         return 0;
 232                 } else if (resp_code == 1) {
 233                         hns3_dbg(hw, "lookup mac addr failed for miss");
 234                         return -ENOENT;
 235                 }
 236
 237                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 238                          resp_code);
 239                 return -EIO;
 240         }
 241
 242         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 243                  op);
 244
 245         return -EINVAL;
 246 }
 247
 248 static int
 249 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 250                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 251                          struct hns3_cmd_desc *desc, bool is_mc)
 252 {
 253         uint8_t resp_code;
 254         uint16_t retval;
 255         int ret;
 256
 257         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 258         if (is_mc) {
 259                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 260                 memcpy(desc[0].data, req,
 261                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 262                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 263                                           true);
 264                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 265                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 266                                           true);
 267                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 268         } else {
 269                 memcpy(desc[0].data, req,
 270                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 271                 ret = hns3_cmd_send(hw, desc, 1);
 272         }
 273         if (ret) {
 274                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 275                          ret);
 276                 return ret;
 277         }
 278         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 279         retval = rte_le_to_cpu_16(desc[0].retval);
 280
 281         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 282                                             HNS3_MAC_VLAN_LKUP);
 283 }
 284
 285 static int
 286 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 287                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 288                       struct hns3_cmd_desc *mc_desc)
 289 {
 290         uint8_t resp_code;
 291         uint16_t retval;
 292         int cfg_status;
 293         int ret;
 294
 295         if (mc_desc == NULL) {
 296                 struct hns3_cmd_desc desc;
 297
 298                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 299                 memcpy(desc.data, req,
 300                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 301                 ret = hns3_cmd_send(hw, &desc, 1);
 302                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 303                 retval = rte_le_to_cpu_16(desc.retval);
 304
 305                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 306                                                           HNS3_MAC_VLAN_ADD);
 307         } else {
 308                 hns3_cmd_reuse_desc(&mc_desc[0], false);
 309                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 310                 hns3_cmd_reuse_desc(&mc_desc[1], false);
 311                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 312                 hns3_cmd_reuse_desc(&mc_desc[2], false);
 313                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
 314                 memcpy(mc_desc[0].data, req,
 315                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 316                 mc_desc[0].retval = 0;
 317                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 318                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
 319                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
 320
 321                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 322                                                           HNS3_MAC_VLAN_ADD);
 323         }
 324
 325         if (ret) {
 326                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
 327                 return ret;
 328         }
 329
 330         return cfg_status;
 331 }
 332
 333 static int
 334 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
 335                          struct hns3_mac_vlan_tbl_entry_cmd *req)
 336 {
 337         struct hns3_cmd_desc desc;
 338         uint8_t resp_code;
 339         uint16_t retval;
 340         int ret;
 341
 342         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
 343
 344         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 345
 346         ret = hns3_cmd_send(hw, &desc, 1);
 347         if (ret) {
 348                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
 349                 return ret;
 350         }
 351         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 352         retval = rte_le_to_cpu_16(desc.retval);
 353
 354         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 355                                             HNS3_MAC_VLAN_REMOVE);
 356 }
 357
 358 static int
 359 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 360 {
 361         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 362         struct hns3_mac_vlan_tbl_entry_cmd req;
 363         struct hns3_pf *pf = &hns->pf;
 364         struct hns3_cmd_desc desc;
 365         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 366         uint16_t egress_port = 0;
 367         uint8_t vf_id;
 368         int ret;
 369
 370         /* check if mac addr is valid */
 371         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 372                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 373                                       mac_addr);
 374                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
 375                          mac_str);
 376                 return -EINVAL;
 377         }
 378
 379         memset(&req, 0, sizeof(req));
 380
 381         /*
 382          * In current version VF is not supported when PF is driven by DPDK
 383          * driver, the PF-related vf_id is 0, just need to configure parameters
 384          * for vf_id 0.
 385          */
 386         vf_id = 0;
 387         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
 388                        HNS3_MAC_EPORT_VFID_S, vf_id);
 389
 390         req.egress_port = rte_cpu_to_le_16(egress_port);
 391
 392         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 393
 394         /*
 395          * Lookup the mac address in the mac_vlan table, and add
 396          * it if the entry is inexistent. Repeated unicast entry
 397          * is not allowed in the mac vlan table.
 398          */
 399         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
 400         if (ret == -ENOENT) {
 401                 if (!hns3_is_umv_space_full(hw)) {
 402                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
 403                         if (!ret)
 404                                 hns3_update_umv_space(hw, false);
 405                         return ret;
 406                 }
 407
 408                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
 409
 410                 return -ENOSPC;
 411         }
 412
 413         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
 414
 415         /* check if we just hit the duplicate */
 416         if (ret == 0) {
 417                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
 418                 return 0;
 419         }
 420
 421         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
 422                  mac_str);
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 429                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
 430 {
 431         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         int ret;
 434
 435         rte_spinlock_lock(&hw->lock);
 436         ret = hns3_add_uc_addr_common(hw, mac_addr);
 437         if (ret) {
 438                 rte_spinlock_unlock(&hw->lock);
 439                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 440                                       mac_addr);
 441                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
 442                 return ret;
 443         }
 444
 445         if (idx == 0)
 446                 hw->mac.default_addr_setted = true;
 447         rte_spinlock_unlock(&hw->lock);
 448
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 454 {
 455         struct hns3_mac_vlan_tbl_entry_cmd req;
 456         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 457         int ret;
 458
 459         /* check if mac addr is valid */
 460         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 461                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 462                                       mac_addr);
 463                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
 464                          mac_str);
 465                 return -EINVAL;
 466         }
 467
 468         memset(&req, 0, sizeof(req));
 469         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 470         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 471         ret = hns3_remove_mac_vlan_tbl(hw, &req);
 472         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
 473                 return 0;
 474         else if (ret == 0)
 475                 hns3_update_umv_space(hw, true);
 476
 477         return ret;
 478 }
 479
 480 static void
 481 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 482 {
 483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 484         /* index will be checked by upper level rte interface */
 485         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 486         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 487         int ret;
 488
 489         rte_spinlock_lock(&hw->lock);
 490         ret = hns3_remove_uc_addr_common(hw, mac_addr);
 491         if (ret) {
 492                 rte_spinlock_unlock(&hw->lock);
 493                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 494                                       mac_addr);
 495                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
 496                 return;
 497         }
 498
 499         if (idx == 0)
 500                 hw->mac.default_addr_setted = false;
 501         rte_spinlock_unlock(&hw->lock);
 502 }
 503
 504 static int
 505 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
 506                           struct rte_ether_addr *mac_addr)
 507 {
 508         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509         struct rte_ether_addr *oaddr;
 510         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 511         bool default_addr_setted;
 512         bool rm_succes = false;
 513         int ret, ret_val;
 514
 515         /* check if mac addr is valid */
 516         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 517                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 518                                       mac_addr);
 519                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
 520                          mac_str);
 521                 return -EINVAL;
 522         }
 523
 524         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
 525         default_addr_setted = hw->mac.default_addr_setted;
 526         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
 527                 return 0;
 528
 529         rte_spinlock_lock(&hw->lock);
 530         if (default_addr_setted) {
 531                 ret = hns3_remove_uc_addr_common(hw, oaddr);
 532                 if (ret) {
 533                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 534                                               oaddr);
 535                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
 536                                   mac_str, ret);
 537                         rm_succes = false;
 538                 } else
 539                         rm_succes = true;
 540         }
 541
 542         ret = hns3_add_uc_addr_common(hw, mac_addr);
 543         if (ret) {
 544                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 545                                       mac_addr);
 546                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
 547                 goto err_add_uc_addr;
 548         }
 549
 550         rte_ether_addr_copy(mac_addr,
 551                             (struct rte_ether_addr *)hw->mac.mac_addr);
 552         hw->mac.default_addr_setted = true;
 553         rte_spinlock_unlock(&hw->lock);
 554
 555         return 0;
 556
 557 err_add_uc_addr:
 558         if (rm_succes) {
 559                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
 560                 if (ret_val) {
 561                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 562                                               oaddr);
 563                         hns3_warn(hw,
 564                                   "Failed to restore old uc mac addr(%s): %d",
 565                                   mac_str, ret_val);
 566                         hw->mac.default_addr_setted = false;
 567                 }
 568         }
 569         rte_spinlock_unlock(&hw->lock);
 570
 571         return ret;
 572 }
 573
 574 static void
 575 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
 576 {
 577 #define HNS3_VF_NUM_IN_FIRST_DESC 192
 578         uint8_t word_num;
 579         uint8_t bit_num;
 580
 581         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
 582                 word_num = vfid / 32;
 583                 bit_num = vfid % 32;
 584                 if (clr)
 585                         desc[1].data[word_num] &=
 586                             rte_cpu_to_le_32(~(1UL << bit_num));
 587                 else
 588                         desc[1].data[word_num] |=
 589                             rte_cpu_to_le_32(1UL << bit_num);
 590         } else {
 591                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
 592                 bit_num = vfid % 32;
 593                 if (clr)
 594                         desc[2].data[word_num] &=
 595                             rte_cpu_to_le_32(~(1UL << bit_num));
 596                 else
 597                         desc[2].data[word_num] |=
 598                             rte_cpu_to_le_32(1UL << bit_num);
 599         }
 600 }
 601
 602 static int
 603 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 604 {
 605         struct hns3_mac_vlan_tbl_entry_cmd req;
 606         struct hns3_cmd_desc desc[3];
 607         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 608         uint8_t vf_id;
 609         int ret;
 610
 611         /* Check if mac addr is valid */
 612         if (!rte_is_multicast_ether_addr(mac_addr)) {
 613                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 614                                       mac_addr);
 615                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
 616                          mac_str);
 617                 return -EINVAL;
 618         }
 619
 620         memset(&req, 0, sizeof(req));
 621         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 622         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 623         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 624         if (ret) {
 625                 /* This mac addr do not exist, add new entry for it */
 626                 memset(desc[0].data, 0, sizeof(desc[0].data));
 627                 memset(desc[1].data, 0, sizeof(desc[0].data));
 628                 memset(desc[2].data, 0, sizeof(desc[0].data));
 629         }
 630
 631         /*
 632          * In current version VF is not supported when PF is driven by DPDK
 633          * driver, the PF-related vf_id is 0, just need to configure parameters
 634          * for vf_id 0.
 635          */
 636         vf_id = 0;
 637         hns3_update_desc_vfid(desc, vf_id, false);
 638         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
 639         if (ret) {
 640                 if (ret == -ENOSPC)
 641                         hns3_err(hw, "mc mac vlan table is full");
 642                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 643                                       mac_addr);
 644                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
 645         }
 646
 647         return ret;
 648 }
 649
 650 static int
 651 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 652 {
 653         struct hns3_mac_vlan_tbl_entry_cmd req;
 654         struct hns3_cmd_desc desc[3];
 655         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 656         uint8_t vf_id;
 657         int ret;
 658
 659         /* Check if mac addr is valid */
 660         if (!rte_is_multicast_ether_addr(mac_addr)) {
 661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 662                                       mac_addr);
 663                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
 664                          mac_str);
 665                 return -EINVAL;
 666         }
 667
 668         memset(&req, 0, sizeof(req));
 669         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 670         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 671         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 672         if (ret == 0) {
 673                 /*
 674                  * This mac addr exist, remove this handle's VFID for it.
 675                  * In current version VF is not supported when PF is driven by
 676                  * DPDK driver, the PF-related vf_id is 0, just need to
 677                  * configure parameters for vf_id 0.
 678                  */
 679                 vf_id = 0;
 680                 hns3_update_desc_vfid(desc, vf_id, true);
 681
 682                 /* All the vfid is zero, so need to delete this entry */
 683                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
 684         } else if (ret == -ENOENT) {
 685                 /* This mac addr doesn't exist. */
 686                 return 0;
 687         }
 688
 689         if (ret) {
 690                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 691                                       mac_addr);
 692                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
 693         }
 694
 695         return ret;
 696 }
 697
 698 static int
 699 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
 700                            struct rte_ether_addr *mc_addr_set,
 701                            uint32_t nb_mc_addr)
 702 {
 703         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 704         struct rte_ether_addr *addr;
 705         uint32_t i;
 706         uint32_t j;
 707
 708         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 709                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 710                          "invalid. valid range: 0~%d",
 711                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 712                 return -EINVAL;
 713         }
 714
 715         /* Check if input mac addresses are valid */
 716         for (i = 0; i < nb_mc_addr; i++) {
 717                 addr = &mc_addr_set[i];
 718                 if (!rte_is_multicast_ether_addr(addr)) {
 719                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 720                                               addr);
 721                         hns3_err(hw,
 722                                  "Failed to set mc mac addr, addr(%s) invalid.",
 723                                  mac_str);
 724                         return -EINVAL;
 725                 }
 726
 727                 /* Check if there are duplicate addresses */
 728                 for (j = i + 1; j < nb_mc_addr; j++) {
 729                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 730                                 rte_ether_format_addr(mac_str,
 731                                                       RTE_ETHER_ADDR_FMT_SIZE,
 732                                                       addr);
 733                                 hns3_err(hw, "Failed to set mc mac addr, "
 734                                          "addrs invalid. two same addrs(%s).",
 735                                          mac_str);
 736                                 return -EINVAL;
 737                         }
 738                 }
 739         }
 740
 741         return 0;
 742 }
 743
 744 static void
 745 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
 746                            struct rte_ether_addr *mc_addr_set,
 747                            int mc_addr_num,
 748                            struct rte_ether_addr *reserved_addr_list,
 749                            int *reserved_addr_num,
 750                            struct rte_ether_addr *add_addr_list,
 751                            int *add_addr_num,
 752                            struct rte_ether_addr *rm_addr_list,
 753                            int *rm_addr_num)
 754 {
 755         struct rte_ether_addr *addr;
 756         int current_addr_num;
 757         int reserved_num = 0;
 758         int add_num = 0;
 759         int rm_num = 0;
 760         int num;
 761         int i;
 762         int j;
 763         bool same_addr;
 764
 765         /* Calculate the mc mac address list that should be removed */
 766         current_addr_num = hw->mc_addrs_num;
 767         for (i = 0; i < current_addr_num; i++) {
 768                 addr = &hw->mc_addrs[i];
 769                 same_addr = false;
 770                 for (j = 0; j < mc_addr_num; j++) {
 771                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 772                                 same_addr = true;
 773                                 break;
 774                         }
 775                 }
 776
 777                 if (!same_addr) {
 778                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
 779                         rm_num++;
 780                 } else {
 781                         rte_ether_addr_copy(addr,
 782                                             &reserved_addr_list[reserved_num]);
 783                         reserved_num++;
 784                 }
 785         }
 786
 787         /* Calculate the mc mac address list that should be added */
 788         for (i = 0; i < mc_addr_num; i++) {
 789                 addr = &mc_addr_set[i];
 790                 same_addr = false;
 791                 for (j = 0; j < current_addr_num; j++) {
 792                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
 793                                 same_addr = true;
 794                                 break;
 795                         }
 796                 }
 797
 798                 if (!same_addr) {
 799                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
 800                         add_num++;
 801                 }
 802         }
 803
 804         /* Reorder the mc mac address list maintained by driver */
 805         for (i = 0; i < reserved_num; i++)
 806                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
 807
 808         for (i = 0; i < rm_num; i++) {
 809                 num = reserved_num + i;
 810                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
 811         }
 812
 813         *reserved_addr_num = reserved_num;
 814         *add_addr_num = add_num;
 815         *rm_addr_num = rm_num;
 816 }
 817
 818 static int
 819 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 820                           struct rte_ether_addr *mc_addr_set,
 821                           uint32_t nb_mc_addr)
 822 {
 823         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 824         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
 825         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
 826         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
 827         struct rte_ether_addr *addr;
 828         int reserved_addr_num;
 829         int add_addr_num;
 830         int rm_addr_num;
 831         int mc_addr_num;
 832         int num;
 833         int ret;
 834         int i;
 835
 836         /* Check if input parameters are valid */
 837         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 838         if (ret)
 839                 return ret;
 840
 841         rte_spinlock_lock(&hw->lock);
 842
 843         /*
 844          * Calculate the mc mac address lists those should be removed and be
 845          * added, Reorder the mc mac address list maintained by driver.
 846          */
 847         mc_addr_num = (int)nb_mc_addr;
 848         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
 849                                    reserved_addr_list, &reserved_addr_num,
 850                                    add_addr_list, &add_addr_num,
 851                                    rm_addr_list, &rm_addr_num);
 852
 853         /* Remove mc mac addresses */
 854         for (i = 0; i < rm_addr_num; i++) {
 855                 num = rm_addr_num - i - 1;
 856                 addr = &rm_addr_list[num];
 857                 ret = hns3_remove_mc_addr(hw, addr);
 858                 if (ret) {
 859                         rte_spinlock_unlock(&hw->lock);
 860                         return ret;
 861                 }
 862                 hw->mc_addrs_num--;
 863         }
 864
 865         /* Add mc mac addresses */
 866         for (i = 0; i < add_addr_num; i++) {
 867                 addr = &add_addr_list[i];
 868                 ret = hns3_add_mc_addr(hw, addr);
 869                 if (ret) {
 870                         rte_spinlock_unlock(&hw->lock);
 871                         return ret;
 872                 }
 873
 874                 num = reserved_addr_num + i;
 875                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
 876                 hw->mc_addrs_num++;
 877         }
 878         rte_spinlock_unlock(&hw->lock);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 885 {
 886         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 887         struct hns3_hw *hw = &hns->hw;
 888         struct rte_ether_addr *addr;
 889         int err = 0;
 890         int ret;
 891         int i;
 892
 893         for (i = 0; i < hw->mc_addrs_num; i++) {
 894                 addr = &hw->mc_addrs[i];
 895                 if (!rte_is_multicast_ether_addr(addr))
 896                         continue;
 897                 if (del)
 898                         ret = hns3_remove_mc_addr(hw, addr);
 899                 else
 900                         ret = hns3_add_mc_addr(hw, addr);
 901                 if (ret) {
 902                         err = ret;
 903                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 904                                               addr);
 905                         hns3_dbg(hw, "%s mc mac addr: %s failed",
 906                                  del ? "Remove" : "Restore", mac_str);
 907                 }
 908         }
 909         return err;
 910 }
 911
 912 static int
 913 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
 914 {
 915         struct hns3_config_max_frm_size_cmd *req;
 916         struct hns3_cmd_desc desc;
 917
 918         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
 919
 920         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
 921         req->max_frm_size = rte_cpu_to_le_16(new_mps);
 922         req->min_frm_size = HNS3_MIN_FRAME_LEN;
 923
 924         return hns3_cmd_send(hw, &desc, 1);
 925 }
 926
 927 static int
 928 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
 929 {
 930         int ret;
 931
 932         ret = hns3_set_mac_mtu(hw, mps);
 933         if (ret) {
 934                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
 935                 return ret;
 936         }
 937
 938         ret = hns3_buffer_alloc(hw);
 939         if (ret) {
 940                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
 941                 return ret;
 942         }
 943
 944         return 0;
 945 }
 946
 947 static int
 948 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
 949 {
 950         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 951         struct hns3_pf *pf = &hns->pf;
 952
 953         if (!(status->pf_state & HNS3_PF_STATE_DONE))
 954                 return -EINVAL;
 955
 956         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
 957
 958         return 0;
 959 }
 960
 961 static int
 962 hns3_query_function_status(struct hns3_hw *hw)
 963 {
 964 #define HNS3_QUERY_MAX_CNT              10
 965 #define HNS3_QUERY_SLEEP_MSCOEND        1
 966         struct hns3_func_status_cmd *req;
 967         struct hns3_cmd_desc desc;
 968         int timeout = 0;
 969         int ret;
 970
 971         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
 972         req = (struct hns3_func_status_cmd *)desc.data;
 973
 974         do {
 975                 ret = hns3_cmd_send(hw, &desc, 1);
 976                 if (ret) {
 977                         PMD_INIT_LOG(ERR, "query function status failed %d",
 978                                      ret);
 979                         return ret;
 980                 }
 981
 982                 /* Check pf reset is done */
 983                 if (req->pf_state)
 984                         break;
 985
 986                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
 987         } while (timeout++ < HNS3_QUERY_MAX_CNT);
 988
 989         return hns3_parse_func_status(hw, req);
 990 }
 991
 992 static int
 993 hns3_query_pf_resource(struct hns3_hw *hw)
 994 {
 995         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 996         struct hns3_pf *pf = &hns->pf;
 997         struct hns3_pf_res_cmd *req;
 998         struct hns3_cmd_desc desc;
 999         int ret;
1000
1001         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1002         ret = hns3_cmd_send(hw, &desc, 1);
1003         if (ret) {
1004                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1005                 return ret;
1006         }
1007
1008         req = (struct hns3_pf_res_cmd *)desc.data;
1009         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1010         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1011         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1012
1013         if (req->tx_buf_size)
1014                 pf->tx_buf_size =
1015                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1016         else
1017                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1018
1019         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1020
1021         if (req->dv_buf_size)
1022                 pf->dv_buf_size =
1023                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1024         else
1025                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1026
1027         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1028
1029         hw->num_msi =
1030             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1031                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1032
1033         return 0;
1034 }
1035
1036 static void
1037 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1038 {
1039         struct hns3_cfg_param_cmd *req;
1040         uint64_t mac_addr_tmp_high;
1041         uint64_t mac_addr_tmp;
1042         uint32_t i;
1043
1044         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1045
1046         /* get the configuration */
1047         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1048                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1049         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1050                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1051         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1052                                            HNS3_CFG_TQP_DESC_N_M,
1053                                            HNS3_CFG_TQP_DESC_N_S);
1054
1055         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1056                                        HNS3_CFG_PHY_ADDR_M,
1057                                        HNS3_CFG_PHY_ADDR_S);
1058         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1059                                          HNS3_CFG_MEDIA_TP_M,
1060                                          HNS3_CFG_MEDIA_TP_S);
1061         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1062                                          HNS3_CFG_RX_BUF_LEN_M,
1063                                          HNS3_CFG_RX_BUF_LEN_S);
1064         /* get mac address */
1065         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1066         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1067                                            HNS3_CFG_MAC_ADDR_H_M,
1068                                            HNS3_CFG_MAC_ADDR_H_S);
1069
1070         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1071
1072         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1073                                             HNS3_CFG_DEFAULT_SPEED_M,
1074                                             HNS3_CFG_DEFAULT_SPEED_S);
1075         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1076                                            HNS3_CFG_RSS_SIZE_M,
1077                                            HNS3_CFG_RSS_SIZE_S);
1078
1079         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1080                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1081
1082         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1083         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1084
1085         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1086                                             HNS3_CFG_SPEED_ABILITY_M,
1087                                             HNS3_CFG_SPEED_ABILITY_S);
1088         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1089                                         HNS3_CFG_UMV_TBL_SPACE_M,
1090                                         HNS3_CFG_UMV_TBL_SPACE_S);
1091         if (!cfg->umv_space)
1092                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1093 }
1094
1095 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1096  * @hw: pointer to struct hns3_hw
1097  * @hcfg: the config structure to be getted
1098  */
1099 static int
1100 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1101 {
1102         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1103         struct hns3_cfg_param_cmd *req;
1104         uint32_t offset;
1105         uint32_t i;
1106         int ret;
1107
1108         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1109                 offset = 0;
1110                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1111                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1112                                           true);
1113                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1114                                i * HNS3_CFG_RD_LEN_BYTES);
1115                 /* Len should be divided by 4 when send to hardware */
1116                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1117                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1118                 req->offset = rte_cpu_to_le_32(offset);
1119         }
1120
1121         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1122         if (ret) {
1123                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1124                 return ret;
1125         }
1126
1127         hns3_parse_cfg(hcfg, desc);
1128
1129         return 0;
1130 }
1131
1132 static int
1133 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1134 {
1135         switch (speed_cmd) {
1136         case HNS3_CFG_SPEED_10M:
1137                 *speed = ETH_SPEED_NUM_10M;
1138                 break;
1139         case HNS3_CFG_SPEED_100M:
1140                 *speed = ETH_SPEED_NUM_100M;
1141                 break;
1142         case HNS3_CFG_SPEED_1G:
1143                 *speed = ETH_SPEED_NUM_1G;
1144                 break;
1145         case HNS3_CFG_SPEED_10G:
1146                 *speed = ETH_SPEED_NUM_10G;
1147                 break;
1148         case HNS3_CFG_SPEED_25G:
1149                 *speed = ETH_SPEED_NUM_25G;
1150                 break;
1151         case HNS3_CFG_SPEED_40G:
1152                 *speed = ETH_SPEED_NUM_40G;
1153                 break;
1154         case HNS3_CFG_SPEED_50G:
1155                 *speed = ETH_SPEED_NUM_50G;
1156                 break;
1157         case HNS3_CFG_SPEED_100G:
1158                 *speed = ETH_SPEED_NUM_100G;
1159                 break;
1160         default:
1161                 return -EINVAL;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int
1168 hns3_get_board_configuration(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         struct hns3_cfg cfg;
1173         int ret;
1174
1175         ret = hns3_get_board_cfg(hw, &cfg);
1176         if (ret) {
1177                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1178                 return ret;
1179         }
1180
1181         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1182                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1183                 return -EOPNOTSUPP;
1184         }
1185
1186         hw->mac.media_type = cfg.media_type;
1187         hw->rss_size_max = cfg.rss_size_max;
1188         hw->rx_buf_len = cfg.rx_buf_len;
1189         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1190         hw->mac.phy_addr = cfg.phy_addr;
1191         hw->mac.default_addr_setted = false;
1192         hw->num_tx_desc = cfg.tqp_desc_num;
1193         hw->num_rx_desc = cfg.tqp_desc_num;
1194         hw->dcb_info.num_pg = 1;
1195         hw->dcb_info.hw_pfc_map = 0;
1196
1197         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1198         if (ret) {
1199                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1200                              cfg.default_speed, ret);
1201                 return ret;
1202         }
1203
1204         pf->tc_max = cfg.tc_num;
1205         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1206                 PMD_INIT_LOG(WARNING,
1207                              "Get TC num(%u) from flash, set TC num to 1",
1208                              pf->tc_max);
1209                 pf->tc_max = 1;
1210         }
1211
1212         /* Dev does not support DCB */
1213         if (!hns3_dev_dcb_supported(hw)) {
1214                 pf->tc_max = 1;
1215                 pf->pfc_max = 0;
1216         } else
1217                 pf->pfc_max = pf->tc_max;
1218
1219         hw->dcb_info.num_tc = 1;
1220         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1221                                      hw->tqps_num / hw->dcb_info.num_tc);
1222         hns3_set_bit(hw->hw_tc_map, 0, 1);
1223         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1224
1225         pf->wanted_umv_size = cfg.umv_space;
1226
1227         return ret;
1228 }
1229
1230 static int
1231 hns3_get_configuration(struct hns3_hw *hw)
1232 {
1233         int ret;
1234
1235         ret = hns3_query_function_status(hw);
1236         if (ret) {
1237                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1238                 return ret;
1239         }
1240
1241         /* Get pf resource */
1242         ret = hns3_query_pf_resource(hw);
1243         if (ret) {
1244                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1245                 return ret;
1246         }
1247
1248         ret = hns3_get_board_configuration(hw);
1249         if (ret) {
1250                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1251                 return ret;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int
1258 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1259                       uint16_t tqp_vid, bool is_pf)
1260 {
1261         struct hns3_tqp_map_cmd *req;
1262         struct hns3_cmd_desc desc;
1263         int ret;
1264
1265         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1266
1267         req = (struct hns3_tqp_map_cmd *)desc.data;
1268         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1269         req->tqp_vf = func_id;
1270         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1271         if (!is_pf)
1272                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1273         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1274
1275         ret = hns3_cmd_send(hw, &desc, 1);
1276         if (ret)
1277                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1278
1279         return ret;
1280 }
1281
1282 static int
1283 hns3_map_tqp(struct hns3_hw *hw)
1284 {
1285         uint16_t tqps_num = hw->total_tqps_num;
1286         uint16_t func_id;
1287         uint16_t tqp_id;
1288         int num;
1289         int ret;
1290         int i;
1291
1292         /*
1293          * In current version VF is not supported when PF is driven by DPDK
1294          * driver, so we allocate tqps to PF as much as possible.
1295          */
1296         tqp_id = 0;
1297         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1298         for (func_id = 0; func_id < num; func_id++) {
1299                 for (i = 0;
1300                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1301                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1302                                                     true);
1303                         if (ret)
1304                                 return ret;
1305                 }
1306         }
1307
1308         return 0;
1309 }
1310
1311 static int
1312 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1313 {
1314         struct hns3_config_mac_speed_dup_cmd *req;
1315         struct hns3_cmd_desc desc;
1316         int ret;
1317
1318         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1319
1320         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1321
1322         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1323
1324         switch (speed) {
1325         case ETH_SPEED_NUM_10M:
1326                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1327                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1328                 break;
1329         case ETH_SPEED_NUM_100M:
1330                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1331                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1332                 break;
1333         case ETH_SPEED_NUM_1G:
1334                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1335                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1336                 break;
1337         case ETH_SPEED_NUM_10G:
1338                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1339                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1340                 break;
1341         case ETH_SPEED_NUM_25G:
1342                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1343                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1344                 break;
1345         case ETH_SPEED_NUM_40G:
1346                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1347                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1348                 break;
1349         case ETH_SPEED_NUM_50G:
1350                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1351                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1352                 break;
1353         case ETH_SPEED_NUM_100G:
1354                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1355                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1356                 break;
1357         default:
1358                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1359                 return -EINVAL;
1360         }
1361
1362         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1363
1364         ret = hns3_cmd_send(hw, &desc, 1);
1365         if (ret)
1366                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1367
1368         return ret;
1369 }
1370
1371 static int
1372 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1373 {
1374         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1375         struct hns3_pf *pf = &hns->pf;
1376         struct hns3_priv_buf *priv;
1377         uint32_t i, total_size;
1378
1379         total_size = pf->pkt_buf_size;
1380
1381         /* alloc tx buffer for all enabled tc */
1382         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1383                 priv = &buf_alloc->priv_buf[i];
1384
1385                 if (hw->hw_tc_map & BIT(i)) {
1386                         if (total_size < pf->tx_buf_size)
1387                                 return -ENOMEM;
1388
1389                         priv->tx_buf_size = pf->tx_buf_size;
1390                 } else
1391                         priv->tx_buf_size = 0;
1392
1393                 total_size -= priv->tx_buf_size;
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int
1400 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1401 {
1402 /* TX buffer size is unit by 128 byte */
1403 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
1404 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
1405         struct hns3_tx_buff_alloc_cmd *req;
1406         struct hns3_cmd_desc desc;
1407         uint32_t buf_size;
1408         uint32_t i;
1409         int ret;
1410
1411         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1412
1413         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1414         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1415                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1416
1417                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1418                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1419                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1420         }
1421
1422         ret = hns3_cmd_send(hw, &desc, 1);
1423         if (ret)
1424                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_get_tc_num(struct hns3_hw *hw)
1431 {
1432         int cnt = 0;
1433         uint8_t i;
1434
1435         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1436                 if (hw->hw_tc_map & BIT(i))
1437                         cnt++;
1438         return cnt;
1439 }
1440
1441 static uint32_t
1442 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1443 {
1444         struct hns3_priv_buf *priv;
1445         uint32_t rx_priv = 0;
1446         int i;
1447
1448         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1449                 priv = &buf_alloc->priv_buf[i];
1450                 if (priv->enable)
1451                         rx_priv += priv->buf_size;
1452         }
1453         return rx_priv;
1454 }
1455
1456 static uint32_t
1457 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1458 {
1459         uint32_t total_tx_size = 0;
1460         uint32_t i;
1461
1462         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1463                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1464
1465         return total_tx_size;
1466 }
1467
1468 /* Get the number of pfc enabled TCs, which have private buffer */
1469 static int
1470 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1471 {
1472         struct hns3_priv_buf *priv;
1473         int cnt = 0;
1474         uint8_t i;
1475
1476         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1477                 priv = &buf_alloc->priv_buf[i];
1478                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1479                         cnt++;
1480         }
1481
1482         return cnt;
1483 }
1484
1485 /* Get the number of pfc disabled TCs, which have private buffer */
1486 static int
1487 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1488                          struct hns3_pkt_buf_alloc *buf_alloc)
1489 {
1490         struct hns3_priv_buf *priv;
1491         int cnt = 0;
1492         uint8_t i;
1493
1494         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1495                 priv = &buf_alloc->priv_buf[i];
1496                 if (hw->hw_tc_map & BIT(i) &&
1497                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1498                         cnt++;
1499         }
1500
1501         return cnt;
1502 }
1503
1504 static bool
1505 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1506                   uint32_t rx_all)
1507 {
1508         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1509         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1510         struct hns3_pf *pf = &hns->pf;
1511         uint32_t shared_buf, aligned_mps;
1512         uint32_t rx_priv;
1513         uint8_t tc_num;
1514         uint8_t i;
1515
1516         tc_num = hns3_get_tc_num(hw);
1517         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1518
1519         if (hns3_dev_dcb_supported(hw))
1520                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1521                                         pf->dv_buf_size;
1522         else
1523                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1524                                         + pf->dv_buf_size;
1525
1526         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1527         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1528                              HNS3_BUF_SIZE_UNIT);
1529
1530         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1531         if (rx_all < rx_priv + shared_std)
1532                 return false;
1533
1534         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1535         buf_alloc->s_buf.buf_size = shared_buf;
1536         if (hns3_dev_dcb_supported(hw)) {
1537                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1538                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1539                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1540                                   HNS3_BUF_SIZE_UNIT);
1541         } else {
1542                 buf_alloc->s_buf.self.high =
1543                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1544                 buf_alloc->s_buf.self.low = aligned_mps;
1545         }
1546
1547         if (hns3_dev_dcb_supported(hw)) {
1548                 hi_thrd = shared_buf - pf->dv_buf_size;
1549
1550                 if (tc_num <= NEED_RESERVE_TC_NUM)
1551                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1552                                         / BUF_MAX_PERCENT;
1553
1554                 if (tc_num)
1555                         hi_thrd = hi_thrd / tc_num;
1556
1557                 hi_thrd = max_t(uint32_t, hi_thrd,
1558                                 HNS3_BUF_MUL_BY * aligned_mps);
1559                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1560                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1561         } else {
1562                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1563                 lo_thrd = aligned_mps;
1564         }
1565
1566         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1567                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1568                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1569         }
1570
1571         return true;
1572 }
1573
1574 static bool
1575 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1576                      struct hns3_pkt_buf_alloc *buf_alloc)
1577 {
1578         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1579         struct hns3_pf *pf = &hns->pf;
1580         struct hns3_priv_buf *priv;
1581         uint32_t aligned_mps;
1582         uint32_t rx_all;
1583         uint8_t i;
1584
1585         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1586         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1587
1588         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1589                 priv = &buf_alloc->priv_buf[i];
1590
1591                 priv->enable = 0;
1592                 priv->wl.low = 0;
1593                 priv->wl.high = 0;
1594                 priv->buf_size = 0;
1595
1596                 if (!(hw->hw_tc_map & BIT(i)))
1597                         continue;
1598
1599                 priv->enable = 1;
1600                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1601                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1602                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
1603                                                 HNS3_BUF_SIZE_UNIT);
1604                 } else {
1605                         priv->wl.low = 0;
1606                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1607                                         aligned_mps;
1608                 }
1609
1610                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1611         }
1612
1613         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1614 }
1615
1616 static bool
1617 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1618                              struct hns3_pkt_buf_alloc *buf_alloc)
1619 {
1620         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1621         struct hns3_pf *pf = &hns->pf;
1622         struct hns3_priv_buf *priv;
1623         int no_pfc_priv_num;
1624         uint32_t rx_all;
1625         uint8_t mask;
1626         int i;
1627
1628         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1629         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1630
1631         /* let the last to be cleared first */
1632         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1633                 priv = &buf_alloc->priv_buf[i];
1634                 mask = BIT((uint8_t)i);
1635
1636                 if (hw->hw_tc_map & mask &&
1637                     !(hw->dcb_info.hw_pfc_map & mask)) {
1638                         /* Clear the no pfc TC private buffer */
1639                         priv->wl.low = 0;
1640                         priv->wl.high = 0;
1641                         priv->buf_size = 0;
1642                         priv->enable = 0;
1643                         no_pfc_priv_num--;
1644                 }
1645
1646                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1647                     no_pfc_priv_num == 0)
1648                         break;
1649         }
1650
1651         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1652 }
1653
1654 static bool
1655 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1656                            struct hns3_pkt_buf_alloc *buf_alloc)
1657 {
1658         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1659         struct hns3_pf *pf = &hns->pf;
1660         struct hns3_priv_buf *priv;
1661         uint32_t rx_all;
1662         int pfc_priv_num;
1663         uint8_t mask;
1664         int i;
1665
1666         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1667         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1668
1669         /* let the last to be cleared first */
1670         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1671                 priv = &buf_alloc->priv_buf[i];
1672                 mask = BIT((uint8_t)i);
1673
1674                 if (hw->hw_tc_map & mask &&
1675                     hw->dcb_info.hw_pfc_map & mask) {
1676                         /* Reduce the number of pfc TC with private buffer */
1677                         priv->wl.low = 0;
1678                         priv->enable = 0;
1679                         priv->wl.high = 0;
1680                         priv->buf_size = 0;
1681                         pfc_priv_num--;
1682                 }
1683                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1684                     pfc_priv_num == 0)
1685                         break;
1686         }
1687
1688         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1689 }
1690
1691 static bool
1692 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1693                           struct hns3_pkt_buf_alloc *buf_alloc)
1694 {
1695 #define COMPENSATE_BUFFER       0x3C00
1696 #define COMPENSATE_HALF_MPS_NUM 5
1697 #define PRIV_WL_GAP             0x1800
1698         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1699         struct hns3_pf *pf = &hns->pf;
1700         uint32_t tc_num = hns3_get_tc_num(hw);
1701         uint32_t half_mps = pf->mps >> 1;
1702         struct hns3_priv_buf *priv;
1703         uint32_t min_rx_priv;
1704         uint32_t rx_priv;
1705         uint8_t i;
1706
1707         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1708         if (tc_num)
1709                 rx_priv = rx_priv / tc_num;
1710
1711         if (tc_num <= NEED_RESERVE_TC_NUM)
1712                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1713
1714         /*
1715          * Minimum value of private buffer in rx direction (min_rx_priv) is
1716          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1717          * buffer if rx_priv is greater than min_rx_priv.
1718          */
1719         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1720                         COMPENSATE_HALF_MPS_NUM * half_mps;
1721         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1722         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1723
1724         if (rx_priv < min_rx_priv)
1725                 return false;
1726
1727         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1728                 priv = &buf_alloc->priv_buf[i];
1729
1730                 priv->enable = 0;
1731                 priv->wl.low = 0;
1732                 priv->wl.high = 0;
1733                 priv->buf_size = 0;
1734
1735                 if (!(hw->hw_tc_map & BIT(i)))
1736                         continue;
1737
1738                 priv->enable = 1;
1739                 priv->buf_size = rx_priv;
1740                 priv->wl.high = rx_priv - pf->dv_buf_size;
1741                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1742         }
1743
1744         buf_alloc->s_buf.buf_size = 0;
1745
1746         return true;
1747 }
1748
1749 /*
1750  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1751  * @hw: pointer to struct hns3_hw
1752  * @buf_alloc: pointer to buffer calculation data
1753  * @return: 0: calculate sucessful, negative: fail
1754  */
1755 static int
1756 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1757 {
1758         /* When DCB is not supported, rx private buffer is not allocated. */
1759         if (!hns3_dev_dcb_supported(hw)) {
1760                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1761                 struct hns3_pf *pf = &hns->pf;
1762                 uint32_t rx_all = pf->pkt_buf_size;
1763
1764                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1765                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1766                         return -ENOMEM;
1767
1768                 return 0;
1769         }
1770
1771         /*
1772          * Try to allocate privated packet buffer for all TCs without share
1773          * buffer.
1774          */
1775         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1776                 return 0;
1777
1778         /*
1779          * Try to allocate privated packet buffer for all TCs with share
1780          * buffer.
1781          */
1782         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1783                 return 0;
1784
1785         /*
1786          * For different application scenes, the enabled port number, TC number
1787          * and no_drop TC number are different. In order to obtain the better
1788          * performance, software could allocate the buffer size and configure
1789          * the waterline by tring to decrease the private buffer size according
1790          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1791          * enabled tc.
1792          */
1793         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1794                 return 0;
1795
1796         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1797                 return 0;
1798
1799         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1800                 return 0;
1801
1802         return -ENOMEM;
1803 }
1804
1805 static int
1806 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1807 {
1808         struct hns3_rx_priv_buff_cmd *req;
1809         struct hns3_cmd_desc desc;
1810         uint32_t buf_size;
1811         int ret;
1812         int i;
1813
1814         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1815         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1816
1817         /* Alloc private buffer TCs */
1818         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1819                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1820
1821                 req->buf_num[i] =
1822                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1823                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1824         }
1825
1826         buf_size = buf_alloc->s_buf.buf_size;
1827         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1828                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
1829
1830         ret = hns3_cmd_send(hw, &desc, 1);
1831         if (ret)
1832                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1833
1834         return ret;
1835 }
1836
1837 static int
1838 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1839 {
1840 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1841         struct hns3_rx_priv_wl_buf *req;
1842         struct hns3_priv_buf *priv;
1843         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1844         int i, j;
1845         int ret;
1846
1847         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1848                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1849                                           false);
1850                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1851
1852                 /* The first descriptor set the NEXT bit to 1 */
1853                 if (i == 0)
1854                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1855                 else
1856                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1857
1858                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
1859                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
1860
1861                         priv = &buf_alloc->priv_buf[idx];
1862                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
1863                                                         HNS3_BUF_UNIT_S);
1864                         req->tc_wl[j].high |=
1865                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1866                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
1867                                                         HNS3_BUF_UNIT_S);
1868                         req->tc_wl[j].low |=
1869                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1870                 }
1871         }
1872
1873         /* Send 2 descriptor at one time */
1874         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
1875         if (ret)
1876                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
1877                              ret);
1878         return ret;
1879 }
1880
1881 static int
1882 hns3_common_thrd_config(struct hns3_hw *hw,
1883                         struct hns3_pkt_buf_alloc *buf_alloc)
1884 {
1885 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
1886         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
1887         struct hns3_rx_com_thrd *req;
1888         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
1889         struct hns3_tc_thrd *tc;
1890         int tc_idx;
1891         int i, j;
1892         int ret;
1893
1894         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
1895                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
1896                                           false);
1897                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
1898
1899                 /* The first descriptor set the NEXT bit to 1 */
1900                 if (i == 0)
1901                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1902                 else
1903                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1904
1905                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
1906                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
1907                         tc = &s_buf->tc_thrd[tc_idx];
1908
1909                         req->com_thrd[j].high =
1910                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
1911                         req->com_thrd[j].high |=
1912                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1913                         req->com_thrd[j].low =
1914                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
1915                         req->com_thrd[j].low |=
1916                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1917                 }
1918         }
1919
1920         /* Send 2 descriptors at one time */
1921         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
1922         if (ret)
1923                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
1924
1925         return ret;
1926 }
1927
1928 static int
1929 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1930 {
1931         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
1932         struct hns3_rx_com_wl *req;
1933         struct hns3_cmd_desc desc;
1934         int ret;
1935
1936         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
1937
1938         req = (struct hns3_rx_com_wl *)desc.data;
1939         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
1940         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1941
1942         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
1943         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
1944
1945         ret = hns3_cmd_send(hw, &desc, 1);
1946         if (ret)
1947                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
1948
1949         return ret;
1950 }
1951
1952 int
1953 hns3_buffer_alloc(struct hns3_hw *hw)
1954 {
1955         struct hns3_pkt_buf_alloc pkt_buf;
1956         int ret;
1957
1958         memset(&pkt_buf, 0, sizeof(pkt_buf));
1959         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
1960         if (ret) {
1961                 PMD_INIT_LOG(ERR,
1962                              "could not calc tx buffer size for all TCs %d",
1963                              ret);
1964                 return ret;
1965         }
1966
1967         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
1968         if (ret) {
1969                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
1970                 return ret;
1971         }
1972
1973         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
1974         if (ret) {
1975                 PMD_INIT_LOG(ERR,
1976                              "could not calc rx priv buffer size for all TCs %d",
1977                              ret);
1978                 return ret;
1979         }
1980
1981         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
1982         if (ret) {
1983                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
1984                 return ret;
1985         }
1986
1987         if (hns3_dev_dcb_supported(hw)) {
1988                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
1989                 if (ret) {
1990                         PMD_INIT_LOG(ERR,
1991                                      "could not configure rx private waterline %d",
1992                                      ret);
1993                         return ret;
1994                 }
1995
1996                 ret = hns3_common_thrd_config(hw, &pkt_buf);
1997                 if (ret) {
1998                         PMD_INIT_LOG(ERR,
1999                                      "could not configure common threshold %d",
2000                                      ret);
2001                         return ret;
2002                 }
2003         }
2004
2005         ret = hns3_common_wl_config(hw, &pkt_buf);
2006         if (ret)
2007                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2008                              ret);
2009
2010         return ret;
2011 }
2012
2013 static int
2014 hns3_mac_init(struct hns3_hw *hw)
2015 {
2016         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2017         struct hns3_mac *mac = &hw->mac;
2018         struct hns3_pf *pf = &hns->pf;
2019         int ret;
2020
2021         pf->support_sfp_query = true;
2022         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2023         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2024         if (ret) {
2025                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2026                 return ret;
2027         }
2028
2029         mac->link_status = ETH_LINK_DOWN;
2030
2031         return hns3_config_mtu(hw, pf->mps);
2032 }
2033
2034 static int
2035 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2036 {
2037 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2038 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2039 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2040 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2041         int return_status;
2042
2043         if (cmdq_resp) {
2044                 PMD_INIT_LOG(ERR,
2045                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2046                              cmdq_resp);
2047                 return -EIO;
2048         }
2049
2050         switch (resp_code) {
2051         case HNS3_ETHERTYPE_SUCCESS_ADD:
2052         case HNS3_ETHERTYPE_ALREADY_ADD:
2053                 return_status = 0;
2054                 break;
2055         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2056                 PMD_INIT_LOG(ERR,
2057                              "add mac ethertype failed for manager table overflow.");
2058                 return_status = -EIO;
2059                 break;
2060         case HNS3_ETHERTYPE_KEY_CONFLICT:
2061                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2062                 return_status = -EIO;
2063                 break;
2064         default:
2065                 PMD_INIT_LOG(ERR,
2066                              "add mac ethertype failed for undefined, code=%d.",
2067                              resp_code);
2068                 return_status = -EIO;
2069         }
2070
2071         return return_status;
2072 }
2073
2074 static int
2075 hns3_add_mgr_tbl(struct hns3_hw *hw,
2076                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2077 {
2078         struct hns3_cmd_desc desc;
2079         uint8_t resp_code;
2080         uint16_t retval;
2081         int ret;
2082
2083         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2084         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2085
2086         ret = hns3_cmd_send(hw, &desc, 1);
2087         if (ret) {
2088                 PMD_INIT_LOG(ERR,
2089                              "add mac ethertype failed for cmd_send, ret =%d.",
2090                              ret);
2091                 return ret;
2092         }
2093
2094         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2095         retval = rte_le_to_cpu_16(desc.retval);
2096
2097         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2098 }
2099
2100 static void
2101 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2102                      int *table_item_num)
2103 {
2104         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2105
2106         /*
2107          * In current version, we add one item in management table as below:
2108          * 0x0180C200000E -- LLDP MC address
2109          */
2110         tbl = mgr_table;
2111         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2112         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2113         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2114         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2115         tbl->i_port_bitmap = 0x1;
2116         *table_item_num = 1;
2117 }
2118
2119 static int
2120 hns3_init_mgr_tbl(struct hns3_hw *hw)
2121 {
2122 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2123         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2124         int table_item_num;
2125         int ret;
2126         int i;
2127
2128         memset(mgr_table, 0, sizeof(mgr_table));
2129         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2130         for (i = 0; i < table_item_num; i++) {
2131                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2132                 if (ret) {
2133                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2134                                      ret);
2135                         return ret;
2136                 }
2137         }
2138
2139         return 0;
2140 }
2141
2142 static void
2143 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2144                         bool en_mc, bool en_bc, int vport_id)
2145 {
2146         if (!param)
2147                 return;
2148
2149         memset(param, 0, sizeof(struct hns3_promisc_param));
2150         if (en_uc)
2151                 param->enable = HNS3_PROMISC_EN_UC;
2152         if (en_mc)
2153                 param->enable |= HNS3_PROMISC_EN_MC;
2154         if (en_bc)
2155                 param->enable |= HNS3_PROMISC_EN_BC;
2156         param->vf_id = vport_id;
2157 }
2158
2159 static int
2160 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2161 {
2162         struct hns3_promisc_cfg_cmd *req;
2163         struct hns3_cmd_desc desc;
2164         int ret;
2165
2166         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2167
2168         req = (struct hns3_promisc_cfg_cmd *)desc.data;
2169         req->vf_id = param->vf_id;
2170         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2171             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2172
2173         ret = hns3_cmd_send(hw, &desc, 1);
2174         if (ret)
2175                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2176
2177         return ret;
2178 }
2179
2180 static int
2181 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2182 {
2183         struct hns3_promisc_param param;
2184         bool en_bc_pmc = true;
2185         uint8_t vf_id;
2186         int ret;
2187
2188         /*
2189          * In current version VF is not supported when PF is driven by DPDK
2190          * driver, the PF-related vf_id is 0, just need to configure parameters
2191          * for vf_id 0.
2192          */
2193         vf_id = 0;
2194
2195         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2196         ret = hns3_cmd_set_promisc_mode(hw, &param);
2197         if (ret)
2198                 return ret;
2199
2200         return 0;
2201 }
2202
2203 static int
2204 hns3_init_hardware(struct hns3_adapter *hns)
2205 {
2206         struct hns3_hw *hw = &hns->hw;
2207         int ret;
2208
2209         ret = hns3_map_tqp(hw);
2210         if (ret) {
2211                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2212                 return ret;
2213         }
2214
2215         ret = hns3_init_umv_space(hw);
2216         if (ret) {
2217                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2218                 return ret;
2219         }
2220
2221         ret = hns3_mac_init(hw);
2222         if (ret) {
2223                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2224                 goto err_mac_init;
2225         }
2226
2227         ret = hns3_init_mgr_tbl(hw);
2228         if (ret) {
2229                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2230                 goto err_mac_init;
2231         }
2232
2233         ret = hns3_set_promisc_mode(hw, false, false);
2234         if (ret) {
2235                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2236                 goto err_mac_init;
2237         }
2238
2239         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2240         if (ret) {
2241                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2242                 goto err_mac_init;
2243         }
2244
2245         ret = hns3_config_gro(hw, false);
2246         if (ret) {
2247                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2248                 goto err_mac_init;
2249         }
2250         return 0;
2251
2252 err_mac_init:
2253         hns3_uninit_umv_space(hw);
2254         return ret;
2255 }
2256
2257 static int
2258 hns3_init_pf(struct rte_eth_dev *eth_dev)
2259 {
2260         struct rte_device *dev = eth_dev->device;
2261         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2262         struct hns3_adapter *hns = eth_dev->data->dev_private;
2263         struct hns3_hw *hw = &hns->hw;
2264         int ret;
2265
2266         PMD_INIT_FUNC_TRACE();
2267
2268         /* Get hardware io base address from pcie BAR2 IO space */
2269         hw->io_base = pci_dev->mem_resource[2].addr;
2270
2271         /* Firmware command queue initialize */
2272         ret = hns3_cmd_init_queue(hw);
2273         if (ret) {
2274                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2275                 goto err_cmd_init_queue;
2276         }
2277
2278         /* Firmware command initialize */
2279         ret = hns3_cmd_init(hw);
2280         if (ret) {
2281                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2282                 goto err_cmd_init;
2283         }
2284
2285         /* Get configuration */
2286         ret = hns3_get_configuration(hw);
2287         if (ret) {
2288                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2289                 goto err_get_config;
2290         }
2291
2292         ret = hns3_init_hardware(hns);
2293         if (ret) {
2294                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2295                 goto err_get_config;
2296         }
2297
2298         return 0;
2299
2300 err_get_config:
2301         hns3_cmd_uninit(hw);
2302
2303 err_cmd_init:
2304         hns3_cmd_destroy_queue(hw);
2305
2306 err_cmd_init_queue:
2307         hw->io_base = NULL;
2308
2309         return ret;
2310 }
2311
2312 static void
2313 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2314 {
2315         struct hns3_adapter *hns = eth_dev->data->dev_private;
2316         struct hns3_hw *hw = &hns->hw;
2317
2318         PMD_INIT_FUNC_TRACE();
2319
2320         hns3_uninit_umv_space(hw);
2321         hns3_cmd_uninit(hw);
2322         hns3_cmd_destroy_queue(hw);
2323         hw->io_base = NULL;
2324 }
2325
2326 static void
2327 hns3_dev_close(struct rte_eth_dev *eth_dev)
2328 {
2329         struct hns3_adapter *hns = eth_dev->data->dev_private;
2330         struct hns3_hw *hw = &hns->hw;
2331
2332         hw->adapter_state = HNS3_NIC_CLOSING;
2333
2334         hns3_configure_all_mc_mac_addr(hns, true);
2335         hns3_uninit_pf(eth_dev);
2336         hw->adapter_state = HNS3_NIC_CLOSED;
2337 }
2338
2339 static const struct eth_dev_ops hns3_eth_dev_ops = {
2340         .dev_close          = hns3_dev_close,
2341         .mac_addr_add           = hns3_add_mac_addr,
2342         .mac_addr_remove        = hns3_remove_mac_addr,
2343         .mac_addr_set           = hns3_set_default_mac_addr,
2344         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
2345 };
2346
2347 static int
2348 hns3_dev_init(struct rte_eth_dev *eth_dev)
2349 {
2350         struct hns3_adapter *hns = eth_dev->data->dev_private;
2351         struct hns3_hw *hw = &hns->hw;
2352         int ret;
2353
2354         PMD_INIT_FUNC_TRACE();
2355
2356         eth_dev->dev_ops = &hns3_eth_dev_ops;
2357         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2358                 return 0;
2359
2360         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2361         hns->is_vf = false;
2362         hw->data = eth_dev->data;
2363
2364         /*
2365          * Set default max packet size according to the mtu
2366          * default vale in DPDK frame.
2367          */
2368         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2369
2370         ret = hns3_init_pf(eth_dev);
2371         if (ret) {
2372                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2373                 goto err_init_pf;
2374         }
2375
2376         /* Allocate memory for storing MAC addresses */
2377         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2378                                                sizeof(struct rte_ether_addr) *
2379                                                HNS3_UC_MACADDR_NUM, 0);
2380         if (eth_dev->data->mac_addrs == NULL) {
2381                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2382                              "to store MAC addresses",
2383                              sizeof(struct rte_ether_addr) *
2384                              HNS3_UC_MACADDR_NUM);
2385                 ret = -ENOMEM;
2386                 goto err_rte_zmalloc;
2387         }
2388
2389         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2390                             &eth_dev->data->mac_addrs[0]);
2391
2392         hw->adapter_state = HNS3_NIC_INITIALIZED;
2393         /*
2394          * Pass the information to the rte_eth_dev_close() that it should also
2395          * release the private port resources.
2396          */
2397         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2398
2399         hns3_info(hw, "hns3 dev initialization successful!");
2400         return 0;
2401
2402 err_rte_zmalloc:
2403         hns3_uninit_pf(eth_dev);
2404
2405 err_init_pf:
2406         eth_dev->dev_ops = NULL;
2407         eth_dev->rx_pkt_burst = NULL;
2408         eth_dev->tx_pkt_burst = NULL;
2409         eth_dev->tx_pkt_prepare = NULL;
2410         return ret;
2411 }
2412
2413 static int
2414 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2415 {
2416         struct hns3_adapter *hns = eth_dev->data->dev_private;
2417         struct hns3_hw *hw = &hns->hw;
2418
2419         PMD_INIT_FUNC_TRACE();
2420
2421         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2422                 return -EPERM;
2423
2424         eth_dev->dev_ops = NULL;
2425         eth_dev->rx_pkt_burst = NULL;
2426         eth_dev->tx_pkt_burst = NULL;
2427         eth_dev->tx_pkt_prepare = NULL;
2428         if (hw->adapter_state < HNS3_NIC_CLOSING)
2429                 hns3_dev_close(eth_dev);
2430
2431         hw->adapter_state = HNS3_NIC_REMOVED;
2432         return 0;
2433 }
2434
2435 static int
2436 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2437                    struct rte_pci_device *pci_dev)
2438 {
2439         return rte_eth_dev_pci_generic_probe(pci_dev,
2440                                              sizeof(struct hns3_adapter),
2441                                              hns3_dev_init);
2442 }
2443
2444 static int
2445 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2446 {
2447         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2448 }
2449
2450 static const struct rte_pci_id pci_id_hns3_map[] = {
2451         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2452         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2453         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2454         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2455         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2456         { .vendor_id = 0, /* sentinel */ },
2457 };
2458
2459 static struct rte_pci_driver rte_hns3_pmd = {
2460         .id_table = pci_id_hns3_map,
2461         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2462         .probe = eth_hns3_pci_probe,
2463         .remove = eth_hns3_pci_remove,
2464 };
2465
2466 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2467 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2468 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2469
2470 RTE_INIT(hns3_init_log)
2471 {
2472         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2473         if (hns3_logtype_init >= 0)
2474                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2475         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2476         if (hns3_logtype_driver >= 0)
2477                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
2478 }