drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108
 109 void hns3_ether_format_addr(char *buf, uint16_t size,
 110                             const struct rte_ether_addr *ether_addr)
 111 {
 112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 113                 ether_addr->addr_bytes[0],
 114                 ether_addr->addr_bytes[4],
 115                 ether_addr->addr_bytes[5]);
 116 }
 117
 118 static void
 119 hns3_pf_disable_irq0(struct hns3_hw *hw)
 120 {
 121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 122 }
 123
 124 static void
 125 hns3_pf_enable_irq0(struct hns3_hw *hw)
 126 {
 127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 128 }
 129
 130 static enum hns3_evt_cause
 131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 132                           uint32_t *vec_val)
 133 {
 134         struct hns3_hw *hw = &hns->hw;
 135
 136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 139         if (!is_delay) {
 140                 hw->reset.stats.imp_cnt++;
 141                 hns3_warn(hw, "IMP reset detected, clear reset status");
 142         } else {
 143                 hns3_schedule_delayed_reset(hns);
 144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 145         }
 146
 147         return HNS3_VECTOR0_EVENT_RST;
 148 }
 149
 150 static enum hns3_evt_cause
 151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 152                              uint32_t *vec_val)
 153 {
 154         struct hns3_hw *hw = &hns->hw;
 155
 156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 159         if (!is_delay) {
 160                 hw->reset.stats.global_cnt++;
 161                 hns3_warn(hw, "Global reset detected, clear reset status");
 162         } else {
 163                 hns3_schedule_delayed_reset(hns);
 164                 hns3_warn(hw,
 165                           "Global reset detected, don't clear reset status");
 166         }
 167
 168         return HNS3_VECTOR0_EVENT_RST;
 169 }
 170
 171 static enum hns3_evt_cause
 172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 173 {
 174         struct hns3_hw *hw = &hns->hw;
 175         uint32_t vector0_int_stats;
 176         uint32_t cmdq_src_val;
 177         uint32_t hw_err_src_reg;
 178         uint32_t val;
 179         enum hns3_evt_cause ret;
 180         bool is_delay;
 181
 182         /* fetch the events from their corresponding regs */
 183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 186
 187         is_delay = clearval == NULL ? true : false;
 188         /*
 189          * Assumption: If by any chance reset and mailbox events are reported
 190          * together then we will only process reset event and defer the
 191          * processing of the mailbox events. Since, we would have not cleared
 192          * RX CMDQ event this time we would receive again another interrupt
 193          * from H/W just for the mailbox.
 194          */
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 197                 goto out;
 198         }
 199
 200         /* Global reset */
 201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 203                 goto out;
 204         }
 205
 206         /* Check for vector0 1588 event source */
 207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 209                 ret = HNS3_VECTOR0_EVENT_PTP;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 msix event source */
 214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 216                 val = vector0_int_stats | hw_err_src_reg;
 217                 ret = HNS3_VECTOR0_EVENT_ERR;
 218                 goto out;
 219         }
 220
 221         /* check for vector0 mailbox(=CMDQ RX) event source */
 222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 224                 val = cmdq_src_val;
 225                 ret = HNS3_VECTOR0_EVENT_MBX;
 226                 goto out;
 227         }
 228
 229         val = vector0_int_stats;
 230         ret = HNS3_VECTOR0_EVENT_OTHER;
 231 out:
 232
 233         if (clearval)
 234                 *clearval = val;
 235         return ret;
 236 }
 237
 238 static bool
 239 hns3_is_1588_event_type(uint32_t event_type)
 240 {
 241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 242 }
 243
 244 static void
 245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 246 {
 247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 248             hns3_is_1588_event_type(event_type))
 249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 252 }
 253
 254 static void
 255 hns3_clear_all_event_cause(struct hns3_hw *hw)
 256 {
 257         uint32_t vector0_int_stats;
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259
 260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 261                 hns3_warn(hw, "Probe during IMP reset interrupt");
 262
 263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 264                 hns3_warn(hw, "Probe during Global reset interrupt");
 265
 266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 272                                 BIT(HNS3_VECTOR0_1588_INT_B));
 273 }
 274
 275 static void
 276 hns3_handle_mac_tnl(struct hns3_hw *hw)
 277 {
 278         struct hns3_cmd_desc desc;
 279         uint32_t status;
 280         int ret;
 281
 282         /* query and clear mac tnl interruptions */
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 284         ret = hns3_cmd_send(hw, &desc, 1);
 285         if (ret) {
 286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 287                 return;
 288         }
 289
 290         status = rte_le_to_cpu_32(desc.data[0]);
 291         if (status) {
 292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 294                                           false);
 295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 296                 ret = hns3_cmd_send(hw, &desc, 1);
 297                 if (ret)
 298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 299                                  ret);
 300         }
 301 }
 302
 303 static void
 304 hns3_interrupt_handler(void *param)
 305 {
 306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 307         struct hns3_adapter *hns = dev->data->dev_private;
 308         struct hns3_hw *hw = &hns->hw;
 309         enum hns3_evt_cause event_cause;
 310         uint32_t clearval = 0;
 311         uint32_t vector0_int;
 312         uint32_t ras_int;
 313         uint32_t cmdq_int;
 314
 315         /* Disable interrupt */
 316         hns3_pf_disable_irq0(hw);
 317
 318         event_cause = hns3_check_event_cause(hns, &clearval);
 319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_msix_error(hns, &hw->reset.request);
 328                 hns3_handle_ras_error(hns, &hw->reset.request);
 329                 hns3_handle_mac_tnl(hw);
 330                 hns3_schedule_reset(hns);
 331         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 332                 hns3_warn(hw, "received reset interrupt");
 333                 hns3_schedule_reset(hns);
 334         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 335                 hns3_dev_handle_mbx_msg(hw);
 336         } else {
 337                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 338                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 339                           vector0_int, ras_int, cmdq_int);
 340         }
 341
 342         hns3_clear_event_cause(hw, event_cause, clearval);
 343         /* Enable interrupt if it is not cause by reset */
 344         hns3_pf_enable_irq0(hw);
 345 }
 346
 347 static int
 348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 349 {
 350 #define HNS3_VLAN_ID_OFFSET_STEP        160
 351 #define HNS3_VLAN_BYTE_SIZE             8
 352         struct hns3_vlan_filter_pf_cfg_cmd *req;
 353         struct hns3_hw *hw = &hns->hw;
 354         uint8_t vlan_offset_byte_val;
 355         struct hns3_cmd_desc desc;
 356         uint8_t vlan_offset_byte;
 357         uint8_t vlan_offset_base;
 358         int ret;
 359
 360         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 361
 362         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 363         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 364                            HNS3_VLAN_BYTE_SIZE;
 365         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 366
 367         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 368         req->vlan_offset = vlan_offset_base;
 369         req->vlan_cfg = on ? 0 : 1;
 370         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 371
 372         ret = hns3_cmd_send(hw, &desc, 1);
 373         if (ret)
 374                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 375                          vlan_id, ret);
 376
 377         return ret;
 378 }
 379
 380 static void
 381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 382 {
 383         struct hns3_user_vlan_table *vlan_entry;
 384         struct hns3_pf *pf = &hns->pf;
 385
 386         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 387                 if (vlan_entry->vlan_id == vlan_id) {
 388                         if (vlan_entry->hd_tbl_status)
 389                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 390                         LIST_REMOVE(vlan_entry, next);
 391                         rte_free(vlan_entry);
 392                         break;
 393                 }
 394         }
 395 }
 396
 397 static void
 398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 399                         bool writen_to_tbl)
 400 {
 401         struct hns3_user_vlan_table *vlan_entry;
 402         struct hns3_hw *hw = &hns->hw;
 403         struct hns3_pf *pf = &hns->pf;
 404
 405         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 406                 if (vlan_entry->vlan_id == vlan_id)
 407                         return;
 408         }
 409
 410         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 411         if (vlan_entry == NULL) {
 412                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 413                 return;
 414         }
 415
 416         vlan_entry->hd_tbl_status = writen_to_tbl;
 417         vlan_entry->vlan_id = vlan_id;
 418
 419         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 420 }
 421
 422 static int
 423 hns3_restore_vlan_table(struct hns3_adapter *hns)
 424 {
 425         struct hns3_user_vlan_table *vlan_entry;
 426         struct hns3_hw *hw = &hns->hw;
 427         struct hns3_pf *pf = &hns->pf;
 428         uint16_t vlan_id;
 429         int ret = 0;
 430
 431         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 432                 return hns3_vlan_pvid_configure(hns,
 433                                                 hw->port_base_vlan_cfg.pvid, 1);
 434
 435         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 436                 if (vlan_entry->hd_tbl_status) {
 437                         vlan_id = vlan_entry->vlan_id;
 438                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 439                         if (ret)
 440                                 break;
 441                 }
 442         }
 443
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 449 {
 450         struct hns3_hw *hw = &hns->hw;
 451         bool writen_to_tbl = false;
 452         int ret = 0;
 453
 454         /*
 455          * When vlan filter is enabled, hardware regards packets without vlan
 456          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 457          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 458          */
 459         if (on == 0 && vlan_id == 0)
 460                 return 0;
 461
 462         /*
 463          * When port base vlan enabled, we use port base vlan as the vlan
 464          * filter condition. In this case, we don't update vlan filter table
 465          * when user add new vlan or remove exist vlan, just update the
 466          * vlan list. The vlan id in vlan list will be writen in vlan filter
 467          * table until port base vlan disabled
 468          */
 469         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 470                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 471                 writen_to_tbl = true;
 472         }
 473
 474         if (ret == 0) {
 475                 if (on)
 476                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 477                 else
 478                         hns3_rm_dev_vlan_table(hns, vlan_id);
 479         }
 480         return ret;
 481 }
 482
 483 static int
 484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 485 {
 486         struct hns3_adapter *hns = dev->data->dev_private;
 487         struct hns3_hw *hw = &hns->hw;
 488         int ret;
 489
 490         rte_spinlock_lock(&hw->lock);
 491         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 492         rte_spinlock_unlock(&hw->lock);
 493         return ret;
 494 }
 495
 496 static int
 497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 498                          uint16_t tpid)
 499 {
 500         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 501         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 502         struct hns3_hw *hw = &hns->hw;
 503         struct hns3_cmd_desc desc;
 504         int ret;
 505
 506         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 507              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 508                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 509                 return -EINVAL;
 510         }
 511
 512         if (tpid != RTE_ETHER_TYPE_VLAN) {
 513                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 514                 return -EINVAL;
 515         }
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 518         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 519
 520         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 524                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 527                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 528         }
 529
 530         ret = hns3_cmd_send(hw, &desc, 1);
 531         if (ret) {
 532                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 533                          ret);
 534                 return ret;
 535         }
 536
 537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 538
 539         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 540         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 541         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 546                          ret);
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 552                    uint16_t tpid)
 553 {
 554         struct hns3_adapter *hns = dev->data->dev_private;
 555         struct hns3_hw *hw = &hns->hw;
 556         int ret;
 557
 558         rte_spinlock_lock(&hw->lock);
 559         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 560         rte_spinlock_unlock(&hw->lock);
 561         return ret;
 562 }
 563
 564 static int
 565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 566                              struct hns3_rx_vtag_cfg *vcfg)
 567 {
 568         struct hns3_vport_vtag_rx_cfg_cmd *req;
 569         struct hns3_hw *hw = &hns->hw;
 570         struct hns3_cmd_desc desc;
 571         uint16_t vport_id;
 572         uint8_t bitmap;
 573         int ret;
 574
 575         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 576
 577         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 579                      vcfg->strip_tag1_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 581                      vcfg->strip_tag2_en ? 1 : 0);
 582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 583                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 584         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 585                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 586
 587         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 589                      vcfg->strip_tag1_discard_en ? 1 : 0);
 590         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 591                      vcfg->strip_tag2_discard_en ? 1 : 0);
 592         /*
 593          * In current version VF is not supported when PF is driven by DPDK
 594          * driver, just need to configure parameters for PF vport.
 595          */
 596         vport_id = HNS3_PF_FUNC_ID;
 597         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 598         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 599         req->vf_bitmap[req->vf_offset] = bitmap;
 600
 601         ret = hns3_cmd_send(hw, &desc, 1);
 602         if (ret)
 603                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 604         return ret;
 605 }
 606
 607 static void
 608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 609                            struct hns3_rx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_pf *pf = &hns->pf;
 612         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 613 }
 614
 615 static void
 616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 617                            struct hns3_tx_vtag_cfg *vcfg)
 618 {
 619         struct hns3_pf *pf = &hns->pf;
 620         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 621 }
 622
 623 static int
 624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 625 {
 626         struct hns3_rx_vtag_cfg rxvlan_cfg;
 627         struct hns3_hw *hw = &hns->hw;
 628         int ret;
 629
 630         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 631                 rxvlan_cfg.strip_tag1_en = false;
 632                 rxvlan_cfg.strip_tag2_en = enable;
 633                 rxvlan_cfg.strip_tag2_discard_en = false;
 634         } else {
 635                 rxvlan_cfg.strip_tag1_en = enable;
 636                 rxvlan_cfg.strip_tag2_en = true;
 637                 rxvlan_cfg.strip_tag2_discard_en = true;
 638         }
 639
 640         rxvlan_cfg.strip_tag1_discard_en = false;
 641         rxvlan_cfg.vlan1_vlan_prionly = false;
 642         rxvlan_cfg.vlan2_vlan_prionly = false;
 643         rxvlan_cfg.rx_vlan_offload_en = enable;
 644
 645         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 646         if (ret) {
 647                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 648                 return ret;
 649         }
 650
 651         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 658                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 659 {
 660         struct hns3_vlan_filter_ctrl_cmd *req;
 661         struct hns3_cmd_desc desc;
 662         int ret;
 663
 664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 665
 666         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 667         req->vlan_type = vlan_type;
 668         req->vlan_fe = filter_en ? fe_type : 0;
 669         req->vf_id = vf_id;
 670
 671         ret = hns3_cmd_send(hw, &desc, 1);
 672         if (ret)
 673                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 674
 675         return ret;
 676 }
 677
 678 static int
 679 hns3_vlan_filter_init(struct hns3_adapter *hns)
 680 {
 681         struct hns3_hw *hw = &hns->hw;
 682         int ret;
 683
 684         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 685                                         HNS3_FILTER_FE_EGRESS, false,
 686                                         HNS3_PF_FUNC_ID);
 687         if (ret) {
 688                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 689                 return ret;
 690         }
 691
 692         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 693                                         HNS3_FILTER_FE_INGRESS, false,
 694                                         HNS3_PF_FUNC_ID);
 695         if (ret)
 696                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 697
 698         return ret;
 699 }
 700
 701 static int
 702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 703 {
 704         struct hns3_hw *hw = &hns->hw;
 705         int ret;
 706
 707         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 708                                         HNS3_FILTER_FE_INGRESS, enable,
 709                                         HNS3_PF_FUNC_ID);
 710         if (ret)
 711                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 712                          enable ? "enable" : "disable", ret);
 713
 714         return ret;
 715 }
 716
 717 static int
 718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 719 {
 720         struct hns3_adapter *hns = dev->data->dev_private;
 721         struct hns3_hw *hw = &hns->hw;
 722         struct rte_eth_rxmode *rxmode;
 723         unsigned int tmp_mask;
 724         bool enable;
 725         int ret = 0;
 726
 727         rte_spinlock_lock(&hw->lock);
 728         rxmode = &dev->data->dev_conf.rxmode;
 729         tmp_mask = (unsigned int)mask;
 730         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 731                 /* ignore vlan filter configuration during promiscuous mode */
 732                 if (!dev->data->promiscuous) {
 733                         /* Enable or disable VLAN filter */
 734                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 735                                  true : false;
 736
 737                         ret = hns3_enable_vlan_filter(hns, enable);
 738                         if (ret) {
 739                                 rte_spinlock_unlock(&hw->lock);
 740                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 741                                          enable ? "enable" : "disable", ret);
 742                                 return ret;
 743                         }
 744                 }
 745         }
 746
 747         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 748                 /* Enable or disable VLAN stripping */
 749                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 750                     true : false;
 751
 752                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 753                 if (ret) {
 754                         rte_spinlock_unlock(&hw->lock);
 755                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 756                                  enable ? "enable" : "disable", ret);
 757                         return ret;
 758                 }
 759         }
 760
 761         rte_spinlock_unlock(&hw->lock);
 762
 763         return ret;
 764 }
 765
 766 static int
 767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 768                              struct hns3_tx_vtag_cfg *vcfg)
 769 {
 770         struct hns3_vport_vtag_tx_cfg_cmd *req;
 771         struct hns3_cmd_desc desc;
 772         struct hns3_hw *hw = &hns->hw;
 773         uint16_t vport_id;
 774         uint8_t bitmap;
 775         int ret;
 776
 777         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 778
 779         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 780         req->def_vlan_tag1 = vcfg->default_tag1;
 781         req->def_vlan_tag2 = vcfg->default_tag2;
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 783                      vcfg->accept_tag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 785                      vcfg->accept_untag1 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 787                      vcfg->accept_tag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 789                      vcfg->accept_untag2 ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 791                      vcfg->insert_tag1_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 793                      vcfg->insert_tag2_en ? 1 : 0);
 794         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 795
 796         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 797         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 798                      vcfg->tag_shift_mode_en ? 1 : 0);
 799
 800         /*
 801          * In current version VF is not supported when PF is driven by DPDK
 802          * driver, just need to configure parameters for PF vport.
 803          */
 804         vport_id = HNS3_PF_FUNC_ID;
 805         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 806         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 807         req->vf_bitmap[req->vf_offset] = bitmap;
 808
 809         ret = hns3_cmd_send(hw, &desc, 1);
 810         if (ret)
 811                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 812
 813         return ret;
 814 }
 815
 816 static int
 817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 818                      uint16_t pvid)
 819 {
 820         struct hns3_hw *hw = &hns->hw;
 821         struct hns3_tx_vtag_cfg txvlan_cfg;
 822         int ret;
 823
 824         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 825                 txvlan_cfg.accept_tag1 = true;
 826                 txvlan_cfg.insert_tag1_en = false;
 827                 txvlan_cfg.default_tag1 = 0;
 828         } else {
 829                 txvlan_cfg.accept_tag1 =
 830                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 831                 txvlan_cfg.insert_tag1_en = true;
 832                 txvlan_cfg.default_tag1 = pvid;
 833         }
 834
 835         txvlan_cfg.accept_untag1 = true;
 836         txvlan_cfg.accept_tag2 = true;
 837         txvlan_cfg.accept_untag2 = true;
 838         txvlan_cfg.insert_tag2_en = false;
 839         txvlan_cfg.default_tag2 = 0;
 840         txvlan_cfg.tag_shift_mode_en = true;
 841
 842         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 843         if (ret) {
 844                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 845                          ret);
 846                 return ret;
 847         }
 848
 849         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 850         return ret;
 851 }
 852
 853
 854 static void
 855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 856 {
 857         struct hns3_user_vlan_table *vlan_entry;
 858         struct hns3_pf *pf = &hns->pf;
 859
 860         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 861                 if (vlan_entry->hd_tbl_status) {
 862                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 863                         vlan_entry->hd_tbl_status = false;
 864                 }
 865         }
 866
 867         if (is_del_list) {
 868                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 869                 while (vlan_entry) {
 870                         LIST_REMOVE(vlan_entry, next);
 871                         rte_free(vlan_entry);
 872                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 873                 }
 874         }
 875 }
 876
 877 static void
 878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 879 {
 880         struct hns3_user_vlan_table *vlan_entry;
 881         struct hns3_pf *pf = &hns->pf;
 882
 883         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 884                 if (!vlan_entry->hd_tbl_status) {
 885                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 886                         vlan_entry->hd_tbl_status = true;
 887                 }
 888         }
 889 }
 890
 891 static void
 892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 893 {
 894         struct hns3_hw *hw = &hns->hw;
 895         int ret;
 896
 897         hns3_rm_all_vlan_table(hns, true);
 898         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 899                 ret = hns3_set_port_vlan_filter(hns,
 900                                                 hw->port_base_vlan_cfg.pvid, 0);
 901                 if (ret) {
 902                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 903                                  ret);
 904                         return;
 905                 }
 906         }
 907 }
 908
 909 static int
 910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 911                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         uint16_t old_pvid;
 915         int ret;
 916
 917         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 918                 old_pvid = hw->port_base_vlan_cfg.pvid;
 919                 if (old_pvid != HNS3_INVALID_PVID) {
 920                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 921                         if (ret) {
 922                                 hns3_err(hw, "failed to remove old pvid %u, "
 923                                                 "ret = %d", old_pvid, ret);
 924                                 return ret;
 925                         }
 926                 }
 927
 928                 hns3_rm_all_vlan_table(hns, false);
 929                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 930                 if (ret) {
 931                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 932                                         new_pvid, ret);
 933                         return ret;
 934                 }
 935         } else {
 936                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 937                 if (ret) {
 938                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 939                                         new_pvid, ret);
 940                         return ret;
 941                 }
 942
 943                 hns3_add_all_vlan_table(hns);
 944         }
 945         return 0;
 946 }
 947
 948 static int
 949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 950 {
 951         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 952         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 953         bool rx_strip_en;
 954         int ret;
 955
 956         rx_strip_en = old_cfg->rx_vlan_offload_en;
 957         if (on) {
 958                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 959                 rx_vlan_cfg.strip_tag2_en = true;
 960                 rx_vlan_cfg.strip_tag2_discard_en = true;
 961         } else {
 962                 rx_vlan_cfg.strip_tag1_en = false;
 963                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 964                 rx_vlan_cfg.strip_tag2_discard_en = false;
 965         }
 966         rx_vlan_cfg.strip_tag1_discard_en = false;
 967         rx_vlan_cfg.vlan1_vlan_prionly = false;
 968         rx_vlan_cfg.vlan2_vlan_prionly = false;
 969         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 970
 971         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 972         if (ret)
 973                 return ret;
 974
 975         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         uint16_t port_base_vlan_state;
 984         int ret, err;
 985
 986         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 987                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 988                         hns3_warn(hw, "Invalid operation! As current pvid set "
 989                                   "is %u, disable pvid %u is invalid",
 990                                   hw->port_base_vlan_cfg.pvid, pvid);
 991                 return 0;
 992         }
 993
 994         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 995                                     HNS3_PORT_BASE_VLAN_DISABLE;
 996         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 997         if (ret) {
 998                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 999                          ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_en_pvid_strip(hns, on);
1004         if (ret) {
1005                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006                          "ret = %d", ret);
1007                 goto pvid_vlan_strip_fail;
1008         }
1009
1010         if (pvid == HNS3_INVALID_PVID)
1011                 goto out;
1012         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013         if (ret) {
1014                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015                          ret);
1016                 goto vlan_filter_set_fail;
1017         }
1018
1019 out:
1020         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022         return ret;
1023
1024 vlan_filter_set_fail:
1025         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1026                                         HNS3_PORT_BASE_VLAN_ENABLE);
1027         if (err)
1028                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1029
1030 pvid_vlan_strip_fail:
1031         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1032                                         hw->port_base_vlan_cfg.pvid);
1033         if (err)
1034                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1041 {
1042         struct hns3_adapter *hns = dev->data->dev_private;
1043         struct hns3_hw *hw = &hns->hw;
1044         bool pvid_en_state_change;
1045         uint16_t pvid_state;
1046         int ret;
1047
1048         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1049                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1050                          RTE_ETHER_MAX_VLAN_ID);
1051                 return -EINVAL;
1052         }
1053
1054         /*
1055          * If PVID configuration state change, should refresh the PVID
1056          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1057          */
1058         pvid_state = hw->port_base_vlan_cfg.state;
1059         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1060             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1061                 pvid_en_state_change = false;
1062         else
1063                 pvid_en_state_change = true;
1064
1065         rte_spinlock_lock(&hw->lock);
1066         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1067         rte_spinlock_unlock(&hw->lock);
1068         if (ret)
1069                 return ret;
1070         /*
1071          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1072          * need be processed by PMD driver.
1073          */
1074         if (pvid_en_state_change &&
1075             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1076                 hns3_update_all_queues_pvid_proc_en(hw);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_default_vlan_config(struct hns3_adapter *hns)
1083 {
1084         struct hns3_hw *hw = &hns->hw;
1085         int ret;
1086
1087         /*
1088          * When vlan filter is enabled, hardware regards packets without vlan
1089          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1090          * table, packets without vlan won't be received. So, add vlan 0 as
1091          * the default vlan.
1092          */
1093         ret = hns3_vlan_filter_configure(hns, 0, 1);
1094         if (ret)
1095                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1096         return ret;
1097 }
1098
1099 static int
1100 hns3_init_vlan_config(struct hns3_adapter *hns)
1101 {
1102         struct hns3_hw *hw = &hns->hw;
1103         int ret;
1104
1105         /*
1106          * This function can be called in the initialization and reset process,
1107          * when in reset process, it means that hardware had been reseted
1108          * successfully and we need to restore the hardware configuration to
1109          * ensure that the hardware configuration remains unchanged before and
1110          * after reset.
1111          */
1112         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1113                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1114                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115         }
1116
1117         ret = hns3_vlan_filter_init(hns);
1118         if (ret) {
1119                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120                 return ret;
1121         }
1122
1123         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1124                                        RTE_ETHER_TYPE_VLAN);
1125         if (ret) {
1126                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1127                 return ret;
1128         }
1129
1130         /*
1131          * When in the reinit dev stage of the reset process, the following
1132          * vlan-related configurations may differ from those at initialization,
1133          * we will restore configurations to hardware in hns3_restore_vlan_table
1134          * and hns3_restore_vlan_conf later.
1135          */
1136         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1137                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1138                 if (ret) {
1139                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140                         return ret;
1141                 }
1142
1143                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1144                 if (ret) {
1145                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1146                                  ret);
1147                         return ret;
1148                 }
1149         }
1150
1151         return hns3_default_vlan_config(hns);
1152 }
1153
1154 static int
1155 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1156 {
1157         struct hns3_pf *pf = &hns->pf;
1158         struct hns3_hw *hw = &hns->hw;
1159         uint64_t offloads;
1160         bool enable;
1161         int ret;
1162
1163         if (!hw->data->promiscuous) {
1164                 /* restore vlan filter states */
1165                 offloads = hw->data->dev_conf.rxmode.offloads;
1166                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1167                 ret = hns3_enable_vlan_filter(hns, enable);
1168                 if (ret) {
1169                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1170                                  "ret = %d", ret);
1171                         return ret;
1172                 }
1173         }
1174
1175         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1176         if (ret) {
1177                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178                 return ret;
1179         }
1180
1181         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1182         if (ret)
1183                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1184
1185         return ret;
1186 }
1187
1188 static int
1189 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1190 {
1191         struct hns3_adapter *hns = dev->data->dev_private;
1192         struct rte_eth_dev_data *data = dev->data;
1193         struct rte_eth_txmode *txmode;
1194         struct hns3_hw *hw = &hns->hw;
1195         int mask;
1196         int ret;
1197
1198         txmode = &data->dev_conf.txmode;
1199         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1200                 hns3_warn(hw,
1201                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1202                           "configuration is not supported! Ignore these two "
1203                           "parameters: hw_vlan_reject_tagged(%u), "
1204                           "hw_vlan_reject_untagged(%u)",
1205                           txmode->hw_vlan_reject_tagged,
1206                           txmode->hw_vlan_reject_untagged);
1207
1208         /* Apply vlan offload setting */
1209         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1210         ret = hns3_vlan_offload_set(dev, mask);
1211         if (ret) {
1212                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1213                          ret);
1214                 return ret;
1215         }
1216
1217         /*
1218          * If pvid config is not set in rte_eth_conf, driver needn't to set
1219          * VLAN pvid related configuration to hardware.
1220          */
1221         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222                 return 0;
1223
1224         /* Apply pvid setting */
1225         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1226                                  txmode->hw_vlan_insert_pvid);
1227         if (ret)
1228                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1229                          txmode->pvid, ret);
1230
1231         return ret;
1232 }
1233
1234 static int
1235 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1236                 unsigned int tso_mss_max)
1237 {
1238         struct hns3_cfg_tso_status_cmd *req;
1239         struct hns3_cmd_desc desc;
1240         uint16_t tso_mss;
1241
1242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1243
1244         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245
1246         tso_mss = 0;
1247         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1248                        tso_mss_min);
1249         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250
1251         tso_mss = 0;
1252         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1253                        tso_mss_max);
1254         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1255
1256         return hns3_cmd_send(hw, &desc, 1);
1257 }
1258
1259 static int
1260 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1261                    uint16_t *allocated_size, bool is_alloc)
1262 {
1263         struct hns3_umv_spc_alc_cmd *req;
1264         struct hns3_cmd_desc desc;
1265         int ret;
1266
1267         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1269         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1270         req->space_size = rte_cpu_to_le_32(space_size);
1271
1272         ret = hns3_cmd_send(hw, &desc, 1);
1273         if (ret) {
1274                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1275                              is_alloc ? "allocate" : "free", ret);
1276                 return ret;
1277         }
1278
1279         if (is_alloc && allocated_size)
1280                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 hns3_init_umv_space(struct hns3_hw *hw)
1287 {
1288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1289         struct hns3_pf *pf = &hns->pf;
1290         uint16_t allocated_size = 0;
1291         int ret;
1292
1293         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1294                                  true);
1295         if (ret)
1296                 return ret;
1297
1298         if (allocated_size < pf->wanted_umv_size)
1299                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1300                              pf->wanted_umv_size, allocated_size);
1301
1302         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1303                                                 pf->wanted_umv_size;
1304         pf->used_umv_size = 0;
1305         return 0;
1306 }
1307
1308 static int
1309 hns3_uninit_umv_space(struct hns3_hw *hw)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313         int ret;
1314
1315         if (pf->max_umv_size == 0)
1316                 return 0;
1317
1318         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319         if (ret)
1320                 return ret;
1321
1322         pf->max_umv_size = 0;
1323
1324         return 0;
1325 }
1326
1327 static bool
1328 hns3_is_umv_space_full(struct hns3_hw *hw)
1329 {
1330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331         struct hns3_pf *pf = &hns->pf;
1332         bool is_full;
1333
1334         is_full = (pf->used_umv_size >= pf->max_umv_size);
1335
1336         return is_full;
1337 }
1338
1339 static void
1340 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1341 {
1342         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1343         struct hns3_pf *pf = &hns->pf;
1344
1345         if (is_free) {
1346                 if (pf->used_umv_size > 0)
1347                         pf->used_umv_size--;
1348         } else
1349                 pf->used_umv_size++;
1350 }
1351
1352 static void
1353 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1354                       const uint8_t *addr, bool is_mc)
1355 {
1356         const unsigned char *mac_addr = addr;
1357         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1358                             ((uint32_t)mac_addr[2] << 16) |
1359                             ((uint32_t)mac_addr[1] << 8) |
1360                             (uint32_t)mac_addr[0];
1361         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1362
1363         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1364         if (is_mc) {
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1366                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1367                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368         }
1369
1370         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1371         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 }
1373
1374 static int
1375 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1376                              uint8_t resp_code,
1377                              enum hns3_mac_vlan_tbl_opcode op)
1378 {
1379         if (cmdq_resp) {
1380                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1381                          cmdq_resp);
1382                 return -EIO;
1383         }
1384
1385         if (op == HNS3_MAC_VLAN_ADD) {
1386                 if (resp_code == 0 || resp_code == 1) {
1387                         return 0;
1388                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1389                         hns3_err(hw, "add mac addr failed for uc_overflow");
1390                         return -ENOSPC;
1391                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1392                         hns3_err(hw, "add mac addr failed for mc_overflow");
1393                         return -ENOSPC;
1394                 }
1395
1396                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397                          resp_code);
1398                 return -EIO;
1399         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1400                 if (resp_code == 0) {
1401                         return 0;
1402                 } else if (resp_code == 1) {
1403                         hns3_dbg(hw, "remove mac addr failed for miss");
1404                         return -ENOENT;
1405                 }
1406
1407                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408                          resp_code);
1409                 return -EIO;
1410         } else if (op == HNS3_MAC_VLAN_LKUP) {
1411                 if (resp_code == 0) {
1412                         return 0;
1413                 } else if (resp_code == 1) {
1414                         hns3_dbg(hw, "lookup mac addr failed for miss");
1415                         return -ENOENT;
1416                 }
1417
1418                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1419                          resp_code);
1420                 return -EIO;
1421         }
1422
1423         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1424                  op);
1425
1426         return -EINVAL;
1427 }
1428
1429 static int
1430 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1431                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1432                          struct hns3_cmd_desc *desc, bool is_mc)
1433 {
1434         uint8_t resp_code;
1435         uint16_t retval;
1436         int ret;
1437
1438         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1439         if (is_mc) {
1440                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1441                 memcpy(desc[0].data, req,
1442                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1443                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1444                                           true);
1445                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1446                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1449         } else {
1450                 memcpy(desc[0].data, req,
1451                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1452                 ret = hns3_cmd_send(hw, desc, 1);
1453         }
1454         if (ret) {
1455                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456                          ret);
1457                 return ret;
1458         }
1459         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1460         retval = rte_le_to_cpu_16(desc[0].retval);
1461
1462         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1463                                             HNS3_MAC_VLAN_LKUP);
1464 }
1465
1466 static int
1467 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1468                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1469                       struct hns3_cmd_desc *mc_desc)
1470 {
1471         uint8_t resp_code;
1472         uint16_t retval;
1473         int cfg_status;
1474         int ret;
1475
1476         if (mc_desc == NULL) {
1477                 struct hns3_cmd_desc desc;
1478
1479                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc.data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, &desc, 1);
1483                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc.retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1490                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1492                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1493                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1494                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1495                 memcpy(mc_desc[0].data, req,
1496                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1497                 mc_desc[0].retval = 0;
1498                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1499                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1500                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1501
1502                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1503                                                           HNS3_MAC_VLAN_ADD);
1504         }
1505
1506         if (ret) {
1507                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510
1511         return cfg_status;
1512 }
1513
1514 static int
1515 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1516                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1517 {
1518         struct hns3_cmd_desc desc;
1519         uint8_t resp_code;
1520         uint16_t retval;
1521         int ret;
1522
1523         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1524
1525         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1526
1527         ret = hns3_cmd_send(hw, &desc, 1);
1528         if (ret) {
1529                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1530                 return ret;
1531         }
1532         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1533         retval = rte_le_to_cpu_16(desc.retval);
1534
1535         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1536                                             HNS3_MAC_VLAN_REMOVE);
1537 }
1538
1539 static int
1540 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1541 {
1542         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1543         struct hns3_mac_vlan_tbl_entry_cmd req;
1544         struct hns3_pf *pf = &hns->pf;
1545         struct hns3_cmd_desc desc[3];
1546         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1547         uint16_t egress_port = 0;
1548         uint8_t vf_id;
1549         int ret;
1550
1551         /* check if mac addr is valid */
1552         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1553                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                       mac_addr);
1555                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1556                          mac_str);
1557                 return -EINVAL;
1558         }
1559
1560         memset(&req, 0, sizeof(req));
1561
1562         /*
1563          * In current version VF is not supported when PF is driven by DPDK
1564          * driver, just need to configure parameters for PF vport.
1565          */
1566         vf_id = HNS3_PF_FUNC_ID;
1567         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1568                        HNS3_MAC_EPORT_VFID_S, vf_id);
1569
1570         req.egress_port = rte_cpu_to_le_16(egress_port);
1571
1572         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1573
1574         /*
1575          * Lookup the mac address in the mac_vlan table, and add
1576          * it if the entry is inexistent. Repeated unicast entry
1577          * is not allowed in the mac vlan table.
1578          */
1579         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1580         if (ret == -ENOENT) {
1581                 if (!hns3_is_umv_space_full(hw)) {
1582                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1583                         if (!ret)
1584                                 hns3_update_umv_space(hw, false);
1585                         return ret;
1586                 }
1587
1588                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1589
1590                 return -ENOSPC;
1591         }
1592
1593         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1594
1595         /* check if we just hit the duplicate */
1596         if (ret == 0) {
1597                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598                 return 0;
1599         }
1600
1601         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1602                  mac_str);
1603
1604         return ret;
1605 }
1606
1607 static int
1608 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 {
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         struct rte_ether_addr *addr;
1612         int ret;
1613         int i;
1614
1615         for (i = 0; i < hw->mc_addrs_num; i++) {
1616                 addr = &hw->mc_addrs[i];
1617                 /* Check if there are duplicate addresses */
1618                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1619                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                               addr);
1621                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1622                                  "(%s) is added by the set_mc_mac_addr_list "
1623                                  "API", mac_str);
1624                         return -EINVAL;
1625                 }
1626         }
1627
1628         ret = hns3_add_mc_addr(hw, mac_addr);
1629         if (ret) {
1630                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631                                       mac_addr);
1632                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1633                          mac_str, ret);
1634         }
1635         return ret;
1636 }
1637
1638 static int
1639 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1640 {
1641         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1642         int ret;
1643
1644         ret = hns3_remove_mc_addr(hw, mac_addr);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1649                          mac_str, ret);
1650         }
1651         return ret;
1652 }
1653
1654 static int
1655 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1656                   uint32_t idx, __rte_unused uint32_t pool)
1657 {
1658         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         int ret;
1661
1662         rte_spinlock_lock(&hw->lock);
1663
1664         /*
1665          * In hns3 network engine adding UC and MC mac address with different
1666          * commands with firmware. We need to determine whether the input
1667          * address is a UC or a MC address to call different commands.
1668          * By the way, it is recommended calling the API function named
1669          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1670          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1671          * may affect the specifications of UC mac addresses.
1672          */
1673         if (rte_is_multicast_ether_addr(mac_addr))
1674                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1675         else
1676                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1677
1678         if (ret) {
1679                 rte_spinlock_unlock(&hw->lock);
1680                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681                                       mac_addr);
1682                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1683                          ret);
1684                 return ret;
1685         }
1686
1687         if (idx == 0)
1688                 hw->mac.default_addr_setted = true;
1689         rte_spinlock_unlock(&hw->lock);
1690
1691         return ret;
1692 }
1693
1694 static int
1695 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1696 {
1697         struct hns3_mac_vlan_tbl_entry_cmd req;
1698         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1699         int ret;
1700
1701         /* check if mac addr is valid */
1702         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1703                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704                                       mac_addr);
1705                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1706                          mac_str);
1707                 return -EINVAL;
1708         }
1709
1710         memset(&req, 0, sizeof(req));
1711         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1712         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1713         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1714         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1715                 return 0;
1716         else if (ret == 0)
1717                 hns3_update_umv_space(hw, true);
1718
1719         return ret;
1720 }
1721
1722 static void
1723 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1724 {
1725         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         /* index will be checked by upper level rte interface */
1727         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1728         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1729         int ret;
1730
1731         rte_spinlock_lock(&hw->lock);
1732
1733         if (rte_is_multicast_ether_addr(mac_addr))
1734                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1735         else
1736                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1737         rte_spinlock_unlock(&hw->lock);
1738         if (ret) {
1739                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       mac_addr);
1741                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1742                          ret);
1743         }
1744 }
1745
1746 static int
1747 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1748                           struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751         struct rte_ether_addr *oaddr;
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         bool default_addr_setted;
1754         bool rm_succes = false;
1755         int ret, ret_val;
1756
1757         /*
1758          * It has been guaranteed that input parameter named mac_addr is valid
1759          * address in the rte layer of DPDK framework.
1760          */
1761         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1762         default_addr_setted = hw->mac.default_addr_setted;
1763         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1764                 return 0;
1765
1766         rte_spinlock_lock(&hw->lock);
1767         if (default_addr_setted) {
1768                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1769                 if (ret) {
1770                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1771                                               oaddr);
1772                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1773                                   mac_str, ret);
1774                         rm_succes = false;
1775                 } else
1776                         rm_succes = true;
1777         }
1778
1779         ret = hns3_add_uc_addr_common(hw, mac_addr);
1780         if (ret) {
1781                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                       mac_addr);
1783                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1784                 goto err_add_uc_addr;
1785         }
1786
1787         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1788         if (ret) {
1789                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1790                 goto err_pause_addr_cfg;
1791         }
1792
1793         rte_ether_addr_copy(mac_addr,
1794                             (struct rte_ether_addr *)hw->mac.mac_addr);
1795         hw->mac.default_addr_setted = true;
1796         rte_spinlock_unlock(&hw->lock);
1797
1798         return 0;
1799
1800 err_pause_addr_cfg:
1801         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1802         if (ret_val) {
1803                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1804                                       mac_addr);
1805                 hns3_warn(hw,
1806                           "Failed to roll back to del setted mac addr(%s): %d",
1807                           mac_str, ret_val);
1808         }
1809
1810 err_add_uc_addr:
1811         if (rm_succes) {
1812                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1813                 if (ret_val) {
1814                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                               oaddr);
1816                         hns3_warn(hw,
1817                                   "Failed to restore old uc mac addr(%s): %d",
1818                                   mac_str, ret_val);
1819                         hw->mac.default_addr_setted = false;
1820                 }
1821         }
1822         rte_spinlock_unlock(&hw->lock);
1823
1824         return ret;
1825 }
1826
1827 static int
1828 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1829 {
1830         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1831         struct hns3_hw *hw = &hns->hw;
1832         struct rte_ether_addr *addr;
1833         int err = 0;
1834         int ret;
1835         int i;
1836
1837         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1838                 addr = &hw->data->mac_addrs[i];
1839                 if (rte_is_zero_ether_addr(addr))
1840                         continue;
1841                 if (rte_is_multicast_ether_addr(addr))
1842                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1843                               hns3_add_mc_addr(hw, addr);
1844                 else
1845                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1846                               hns3_add_uc_addr_common(hw, addr);
1847
1848                 if (ret) {
1849                         err = ret;
1850                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1851                                               addr);
1852                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1853                                  "ret = %d.", del ? "remove" : "restore",
1854                                  mac_str, i, ret);
1855                 }
1856         }
1857         return err;
1858 }
1859
1860 static void
1861 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1862 {
1863 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864         uint8_t word_num;
1865         uint8_t bit_num;
1866
1867         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1868                 word_num = vfid / 32;
1869                 bit_num = vfid % 32;
1870                 if (clr)
1871                         desc[1].data[word_num] &=
1872                             rte_cpu_to_le_32(~(1UL << bit_num));
1873                 else
1874                         desc[1].data[word_num] |=
1875                             rte_cpu_to_le_32(1UL << bit_num);
1876         } else {
1877                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1878                 bit_num = vfid % 32;
1879                 if (clr)
1880                         desc[2].data[word_num] &=
1881                             rte_cpu_to_le_32(~(1UL << bit_num));
1882                 else
1883                         desc[2].data[word_num] |=
1884                             rte_cpu_to_le_32(1UL << bit_num);
1885         }
1886 }
1887
1888 static int
1889 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1890 {
1891         struct hns3_mac_vlan_tbl_entry_cmd req;
1892         struct hns3_cmd_desc desc[3];
1893         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894         uint8_t vf_id;
1895         int ret;
1896
1897         /* Check if mac addr is valid */
1898         if (!rte_is_multicast_ether_addr(mac_addr)) {
1899                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1900                                       mac_addr);
1901                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1902                          mac_str);
1903                 return -EINVAL;
1904         }
1905
1906         memset(&req, 0, sizeof(req));
1907         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1908         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1909         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1910         if (ret) {
1911                 /* This mac addr do not exist, add new entry for it */
1912                 memset(desc[0].data, 0, sizeof(desc[0].data));
1913                 memset(desc[1].data, 0, sizeof(desc[0].data));
1914                 memset(desc[2].data, 0, sizeof(desc[0].data));
1915         }
1916
1917         /*
1918          * In current version VF is not supported when PF is driven by DPDK
1919          * driver, just need to configure parameters for PF vport.
1920          */
1921         vf_id = HNS3_PF_FUNC_ID;
1922         hns3_update_desc_vfid(desc, vf_id, false);
1923         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1924         if (ret) {
1925                 if (ret == -ENOSPC)
1926                         hns3_err(hw, "mc mac vlan table is full");
1927                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                       mac_addr);
1929                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1930         }
1931
1932         return ret;
1933 }
1934
1935 static int
1936 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 {
1938         struct hns3_mac_vlan_tbl_entry_cmd req;
1939         struct hns3_cmd_desc desc[3];
1940         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1941         uint8_t vf_id;
1942         int ret;
1943
1944         /* Check if mac addr is valid */
1945         if (!rte_is_multicast_ether_addr(mac_addr)) {
1946                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947                                       mac_addr);
1948                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1949                          mac_str);
1950                 return -EINVAL;
1951         }
1952
1953         memset(&req, 0, sizeof(req));
1954         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1955         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1956         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1957         if (ret == 0) {
1958                 /*
1959                  * This mac addr exist, remove this handle's VFID for it.
1960                  * In current version VF is not supported when PF is driven by
1961                  * DPDK driver, just need to configure parameters for PF vport.
1962                  */
1963                 vf_id = HNS3_PF_FUNC_ID;
1964                 hns3_update_desc_vfid(desc, vf_id, true);
1965
1966                 /* All the vfid is zero, so need to delete this entry */
1967                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968         } else if (ret == -ENOENT) {
1969                 /* This mac addr doesn't exist. */
1970                 return 0;
1971         }
1972
1973         if (ret) {
1974                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975                                       mac_addr);
1976                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984                            struct rte_ether_addr *mc_addr_set,
1985                            uint32_t nb_mc_addr)
1986 {
1987         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988         struct rte_ether_addr *addr;
1989         uint32_t i;
1990         uint32_t j;
1991
1992         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994                          "invalid. valid range: 0~%d",
1995                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1996                 return -EINVAL;
1997         }
1998
1999         /* Check if input mac addresses are valid */
2000         for (i = 0; i < nb_mc_addr; i++) {
2001                 addr = &mc_addr_set[i];
2002                 if (!rte_is_multicast_ether_addr(addr)) {
2003                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2004                                               addr);
2005                         hns3_err(hw,
2006                                  "failed to set mc mac addr, addr(%s) invalid.",
2007                                  mac_str);
2008                         return -EINVAL;
2009                 }
2010
2011                 /* Check if there are duplicate addresses */
2012                 for (j = i + 1; j < nb_mc_addr; j++) {
2013                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014                                 hns3_ether_format_addr(mac_str,
2015                                                       RTE_ETHER_ADDR_FMT_SIZE,
2016                                                       addr);
2017                                 hns3_err(hw, "failed to set mc mac addr, "
2018                                          "addrs invalid. two same addrs(%s).",
2019                                          mac_str);
2020                                 return -EINVAL;
2021                         }
2022                 }
2023
2024                 /*
2025                  * Check if there are duplicate addresses between mac_addrs
2026                  * and mc_addr_set
2027                  */
2028                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029                         if (rte_is_same_ether_addr(addr,
2030                                                    &hw->data->mac_addrs[j])) {
2031                                 hns3_ether_format_addr(mac_str,
2032                                                       RTE_ETHER_ADDR_FMT_SIZE,
2033                                                       addr);
2034                                 hns3_err(hw, "failed to set mc mac addr, "
2035                                          "addrs invalid. addrs(%s) has already "
2036                                          "configured in mac_addr add API",
2037                                          mac_str);
2038                                 return -EINVAL;
2039                         }
2040                 }
2041         }
2042
2043         return 0;
2044 }
2045
2046 static void
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048                            struct rte_ether_addr *mc_addr_set,
2049                            int mc_addr_num,
2050                            struct rte_ether_addr *reserved_addr_list,
2051                            int *reserved_addr_num,
2052                            struct rte_ether_addr *add_addr_list,
2053                            int *add_addr_num,
2054                            struct rte_ether_addr *rm_addr_list,
2055                            int *rm_addr_num)
2056 {
2057         struct rte_ether_addr *addr;
2058         int current_addr_num;
2059         int reserved_num = 0;
2060         int add_num = 0;
2061         int rm_num = 0;
2062         int num;
2063         int i;
2064         int j;
2065         bool same_addr;
2066
2067         /* Calculate the mc mac address list that should be removed */
2068         current_addr_num = hw->mc_addrs_num;
2069         for (i = 0; i < current_addr_num; i++) {
2070                 addr = &hw->mc_addrs[i];
2071                 same_addr = false;
2072                 for (j = 0; j < mc_addr_num; j++) {
2073                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2074                                 same_addr = true;
2075                                 break;
2076                         }
2077                 }
2078
2079                 if (!same_addr) {
2080                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2081                         rm_num++;
2082                 } else {
2083                         rte_ether_addr_copy(addr,
2084                                             &reserved_addr_list[reserved_num]);
2085                         reserved_num++;
2086                 }
2087         }
2088
2089         /* Calculate the mc mac address list that should be added */
2090         for (i = 0; i < mc_addr_num; i++) {
2091                 addr = &mc_addr_set[i];
2092                 same_addr = false;
2093                 for (j = 0; j < current_addr_num; j++) {
2094                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2095                                 same_addr = true;
2096                                 break;
2097                         }
2098                 }
2099
2100                 if (!same_addr) {
2101                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2102                         add_num++;
2103                 }
2104         }
2105
2106         /* Reorder the mc mac address list maintained by driver */
2107         for (i = 0; i < reserved_num; i++)
2108                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2109
2110         for (i = 0; i < rm_num; i++) {
2111                 num = reserved_num + i;
2112                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2113         }
2114
2115         *reserved_addr_num = reserved_num;
2116         *add_addr_num = add_num;
2117         *rm_addr_num = rm_num;
2118 }
2119
2120 static int
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122                           struct rte_ether_addr *mc_addr_set,
2123                           uint32_t nb_mc_addr)
2124 {
2125         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129         struct rte_ether_addr *addr;
2130         int reserved_addr_num;
2131         int add_addr_num;
2132         int rm_addr_num;
2133         int mc_addr_num;
2134         int num;
2135         int ret;
2136         int i;
2137
2138         /* Check if input parameters are valid */
2139         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2140         if (ret)
2141                 return ret;
2142
2143         rte_spinlock_lock(&hw->lock);
2144
2145         /*
2146          * Calculate the mc mac address lists those should be removed and be
2147          * added, Reorder the mc mac address list maintained by driver.
2148          */
2149         mc_addr_num = (int)nb_mc_addr;
2150         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151                                    reserved_addr_list, &reserved_addr_num,
2152                                    add_addr_list, &add_addr_num,
2153                                    rm_addr_list, &rm_addr_num);
2154
2155         /* Remove mc mac addresses */
2156         for (i = 0; i < rm_addr_num; i++) {
2157                 num = rm_addr_num - i - 1;
2158                 addr = &rm_addr_list[num];
2159                 ret = hns3_remove_mc_addr(hw, addr);
2160                 if (ret) {
2161                         rte_spinlock_unlock(&hw->lock);
2162                         return ret;
2163                 }
2164                 hw->mc_addrs_num--;
2165         }
2166
2167         /* Add mc mac addresses */
2168         for (i = 0; i < add_addr_num; i++) {
2169                 addr = &add_addr_list[i];
2170                 ret = hns3_add_mc_addr(hw, addr);
2171                 if (ret) {
2172                         rte_spinlock_unlock(&hw->lock);
2173                         return ret;
2174                 }
2175
2176                 num = reserved_addr_num + i;
2177                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2178                 hw->mc_addrs_num++;
2179         }
2180         rte_spinlock_unlock(&hw->lock);
2181
2182         return 0;
2183 }
2184
2185 static int
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2187 {
2188         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189         struct hns3_hw *hw = &hns->hw;
2190         struct rte_ether_addr *addr;
2191         int err = 0;
2192         int ret;
2193         int i;
2194
2195         for (i = 0; i < hw->mc_addrs_num; i++) {
2196                 addr = &hw->mc_addrs[i];
2197                 if (!rte_is_multicast_ether_addr(addr))
2198                         continue;
2199                 if (del)
2200                         ret = hns3_remove_mc_addr(hw, addr);
2201                 else
2202                         ret = hns3_add_mc_addr(hw, addr);
2203                 if (ret) {
2204                         err = ret;
2205                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2206                                               addr);
2207                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208                                  del ? "Remove" : "Restore", mac_str, ret);
2209                 }
2210         }
2211         return err;
2212 }
2213
2214 static int
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2216 {
2217         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2223         uint8_t num_tc;
2224         int max_tc = 0;
2225         int i;
2226
2227         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2228         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2229
2230         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2231                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2232                          "rx_mq_mode = %d", rx_mq_mode);
2233                 return -EINVAL;
2234         }
2235
2236         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2237             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2238                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2239                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2240                          rx_mq_mode, tx_mq_mode);
2241                 return -EINVAL;
2242         }
2243
2244         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2245                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2246                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2247                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2252                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2253                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2254                                  "nb_tcs(%d) != %d or %d in rx direction.",
2255                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2256                         return -EINVAL;
2257                 }
2258
2259                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2260                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2261                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2262                         return -EINVAL;
2263                 }
2264
2265                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2266                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2267                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2268                                          "is not equal to one in tx direction.",
2269                                          i, dcb_rx_conf->dcb_tc[i]);
2270                                 return -EINVAL;
2271                         }
2272                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2273                                 max_tc = dcb_rx_conf->dcb_tc[i];
2274                 }
2275
2276                 num_tc = max_tc + 1;
2277                 if (num_tc > dcb_rx_conf->nb_tcs) {
2278                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2279                                  num_tc, dcb_rx_conf->nb_tcs);
2280                         return -EINVAL;
2281                 }
2282         }
2283
2284         return 0;
2285 }
2286
2287 static int
2288 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2289 {
2290         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291
2292         if (!hns3_dev_dcb_supported(hw)) {
2293                 hns3_err(hw, "this port does not support dcb configurations.");
2294                 return -EOPNOTSUPP;
2295         }
2296
2297         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2298                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2299                 return -EOPNOTSUPP;
2300         }
2301
2302         /* Check multiple queue mode */
2303         return hns3_check_mq_mode(dev);
2304 }
2305
2306 static int
2307 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2308                            enum hns3_ring_type queue_type, uint16_t queue_id)
2309 {
2310         struct hns3_cmd_desc desc;
2311         struct hns3_ctrl_vector_chain_cmd *req =
2312                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2313         enum hns3_opcode_type op;
2314         uint16_t tqp_type_and_id = 0;
2315         uint16_t type;
2316         uint16_t gl;
2317         int ret;
2318
2319         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2320         hns3_cmd_setup_basic_desc(&desc, op, false);
2321         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2322                                               HNS3_TQP_INT_ID_L_S);
2323         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2324                                               HNS3_TQP_INT_ID_H_S);
2325
2326         if (queue_type == HNS3_RING_TYPE_RX)
2327                 gl = HNS3_RING_GL_RX;
2328         else
2329                 gl = HNS3_RING_GL_TX;
2330
2331         type = queue_type;
2332
2333         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2334                        type);
2335         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2336         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2337                        gl);
2338         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2339         req->int_cause_num = 1;
2340         ret = hns3_cmd_send(hw, &desc, 1);
2341         if (ret) {
2342                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2343                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2344                 return ret;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int
2351 hns3_init_ring_with_vector(struct hns3_hw *hw)
2352 {
2353         uint16_t vec;
2354         int ret;
2355         int i;
2356
2357         /*
2358          * In hns3 network engine, vector 0 is always the misc interrupt of this
2359          * function, vector 1~N can be used respectively for the queues of the
2360          * function. Tx and Rx queues with the same number share the interrupt
2361          * vector. In the initialization clearing the all hardware mapping
2362          * relationship configurations between queues and interrupt vectors is
2363          * needed, so some error caused by the residual configurations, such as
2364          * the unexpected Tx interrupt, can be avoid.
2365          */
2366         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2367         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2368                 vec = vec - 1; /* the last interrupt is reserved */
2369         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2370         for (i = 0; i < hw->intr_tqps_num; i++) {
2371                 /*
2372                  * Set gap limiter/rate limiter/quanity limiter algorithm
2373                  * configuration for interrupt coalesce of queue's interrupt.
2374                  */
2375                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2376                                        HNS3_TQP_INTR_GL_DEFAULT);
2377                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2378                                        HNS3_TQP_INTR_GL_DEFAULT);
2379                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2380                 /*
2381                  * QL(quantity limiter) is not used currently, just set 0 to
2382                  * close it.
2383                  */
2384                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2385
2386                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2387                                                  HNS3_RING_TYPE_TX, i);
2388                 if (ret) {
2389                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2390                                           "vector: %u, ret=%d", i, vec, ret);
2391                         return ret;
2392                 }
2393
2394                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2395                                                  HNS3_RING_TYPE_RX, i);
2396                 if (ret) {
2397                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2398                                           "vector: %u, ret=%d", i, vec, ret);
2399                         return ret;
2400                 }
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int
2407 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2408 {
2409         struct hns3_adapter *hns = dev->data->dev_private;
2410         struct hns3_hw *hw = &hns->hw;
2411         uint32_t max_rx_pkt_len;
2412         uint16_t mtu;
2413         int ret;
2414
2415         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2416                 return 0;
2417
2418         /*
2419          * If jumbo frames are enabled, MTU needs to be refreshed
2420          * according to the maximum RX packet length.
2421          */
2422         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2423         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2424             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2425                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2426                          "and no more than %u when jumbo frame enabled.",
2427                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2428                          (uint16_t)HNS3_MAX_FRAME_LEN);
2429                 return -EINVAL;
2430         }
2431
2432         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2433         ret = hns3_dev_mtu_set(dev, mtu);
2434         if (ret)
2435                 return ret;
2436         dev->data->mtu = mtu;
2437
2438         return 0;
2439 }
2440
2441 static int
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2443 {
2444         struct hns3_adapter *hns = dev->data->dev_private;
2445         struct rte_eth_conf *conf = &dev->data->dev_conf;
2446         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447         struct hns3_hw *hw = &hns->hw;
2448         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450         struct rte_eth_rss_conf rss_conf;
2451         bool gro_en;
2452         int ret;
2453
2454         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2455
2456         /*
2457          * Some versions of hardware network engine does not support
2458          * individually enable/disable/reset the Tx or Rx queue. These devices
2459          * must enable/disable/reset Tx and Rx queues at the same time. When the
2460          * numbers of Tx queues allocated by upper applications are not equal to
2461          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463          * work as usual. But these fake queues are imperceptible, and can not
2464          * be used by upper applications.
2465          */
2466         if (!hns3_dev_indep_txrx_supported(hw)) {
2467                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2468                 if (ret) {
2469                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2470                                  ret);
2471                         return ret;
2472                 }
2473         }
2474
2475         hw->adapter_state = HNS3_NIC_CONFIGURING;
2476         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2477                 hns3_err(hw, "setting link speed/duplex not supported");
2478                 ret = -EINVAL;
2479                 goto cfg_err;
2480         }
2481
2482         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2483                 ret = hns3_check_dcb_cfg(dev);
2484                 if (ret)
2485                         goto cfg_err;
2486         }
2487
2488         /* When RSS is not configured, redirect the packet queue 0 */
2489         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2490                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2491                 rss_conf = conf->rx_adv_conf.rss_conf;
2492                 hw->rss_dis_flag = false;
2493                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2494                 if (ret)
2495                         goto cfg_err;
2496         }
2497
2498         ret = hns3_refresh_mtu(dev, conf);
2499         if (ret)
2500                 goto cfg_err;
2501
2502         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2503         if (ret)
2504                 goto cfg_err;
2505
2506         ret = hns3_dev_configure_vlan(dev);
2507         if (ret)
2508                 goto cfg_err;
2509
2510         /* config hardware GRO */
2511         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2512         ret = hns3_config_gro(hw, gro_en);
2513         if (ret)
2514                 goto cfg_err;
2515
2516         hns3_init_rx_ptype_tble(dev);
2517         hw->adapter_state = HNS3_NIC_CONFIGURED;
2518
2519         return 0;
2520
2521 cfg_err:
2522         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2523         hw->adapter_state = HNS3_NIC_INITIALIZED;
2524
2525         return ret;
2526 }
2527
2528 static int
2529 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2530 {
2531         struct hns3_config_max_frm_size_cmd *req;
2532         struct hns3_cmd_desc desc;
2533
2534         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2535
2536         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2537         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2538         req->min_frm_size = RTE_ETHER_MIN_LEN;
2539
2540         return hns3_cmd_send(hw, &desc, 1);
2541 }
2542
2543 static int
2544 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2545 {
2546         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2547         uint16_t original_mps = hns->pf.mps;
2548         int err;
2549         int ret;
2550
2551         ret = hns3_set_mac_mtu(hw, mps);
2552         if (ret) {
2553                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2554                 return ret;
2555         }
2556
2557         hns->pf.mps = mps;
2558         ret = hns3_buffer_alloc(hw);
2559         if (ret) {
2560                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2561                 goto rollback;
2562         }
2563
2564         return 0;
2565
2566 rollback:
2567         err = hns3_set_mac_mtu(hw, original_mps);
2568         if (err) {
2569                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2570                 return ret;
2571         }
2572         hns->pf.mps = original_mps;
2573
2574         return ret;
2575 }
2576
2577 static int
2578 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2579 {
2580         struct hns3_adapter *hns = dev->data->dev_private;
2581         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2582         struct hns3_hw *hw = &hns->hw;
2583         bool is_jumbo_frame;
2584         int ret;
2585
2586         if (dev->data->dev_started) {
2587                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2588                          "before configuration", dev->data->port_id);
2589                 return -EBUSY;
2590         }
2591
2592         rte_spinlock_lock(&hw->lock);
2593         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2594         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2595
2596         /*
2597          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2598          * assign to "uint16_t" type variable.
2599          */
2600         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2601         if (ret) {
2602                 rte_spinlock_unlock(&hw->lock);
2603                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2604                          dev->data->port_id, mtu, ret);
2605                 return ret;
2606         }
2607
2608         if (is_jumbo_frame)
2609                 dev->data->dev_conf.rxmode.offloads |=
2610                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2611         else
2612                 dev->data->dev_conf.rxmode.offloads &=
2613                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2614         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2615         rte_spinlock_unlock(&hw->lock);
2616
2617         return 0;
2618 }
2619
2620 int
2621 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2622 {
2623         struct hns3_adapter *hns = eth_dev->data->dev_private;
2624         struct hns3_hw *hw = &hns->hw;
2625         uint16_t queue_num = hw->tqps_num;
2626
2627         /*
2628          * In interrupt mode, 'max_rx_queues' is set based on the number of
2629          * MSI-X interrupt resources of the hardware.
2630          */
2631         if (hw->data->dev_conf.intr_conf.rxq == 1)
2632                 queue_num = hw->intr_tqps_num;
2633
2634         info->max_rx_queues = queue_num;
2635         info->max_tx_queues = hw->tqps_num;
2636         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2637         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2638         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2639         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2640         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2641         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2642                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2643                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2644                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2645                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2646                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2647                                  DEV_RX_OFFLOAD_KEEP_CRC |
2648                                  DEV_RX_OFFLOAD_SCATTER |
2649                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2650                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2651                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2652                                  DEV_RX_OFFLOAD_RSS_HASH |
2653                                  DEV_RX_OFFLOAD_TCP_LRO);
2654         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2655                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2656                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2657                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2658                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2659                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2660                                  DEV_TX_OFFLOAD_TCP_TSO |
2661                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2662                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2663                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2664                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2665                                  hns3_txvlan_cap_get(hw));
2666
2667         if (hns3_dev_outer_udp_cksum_supported(hw))
2668                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2669
2670         if (hns3_dev_indep_txrx_supported(hw))
2671                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2672                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2673
2674         if (hns3_dev_ptp_supported(hw))
2675                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2676
2677         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2678                 .nb_max = HNS3_MAX_RING_DESC,
2679                 .nb_min = HNS3_MIN_RING_DESC,
2680                 .nb_align = HNS3_ALIGN_RING_DESC,
2681         };
2682
2683         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2684                 .nb_max = HNS3_MAX_RING_DESC,
2685                 .nb_min = HNS3_MIN_RING_DESC,
2686                 .nb_align = HNS3_ALIGN_RING_DESC,
2687                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2688                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2689         };
2690
2691         info->default_rxconf = (struct rte_eth_rxconf) {
2692                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2693                 /*
2694                  * If there are no available Rx buffer descriptors, incoming
2695                  * packets are always dropped by hardware based on hns3 network
2696                  * engine.
2697                  */
2698                 .rx_drop_en = 1,
2699                 .offloads = 0,
2700         };
2701         info->default_txconf = (struct rte_eth_txconf) {
2702                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2703                 .offloads = 0,
2704         };
2705
2706         info->vmdq_queue_num = 0;
2707
2708         info->reta_size = hw->rss_ind_tbl_size;
2709         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2710         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2711
2712         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2713         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2714         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2715         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2716         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2717         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2718
2719         return 0;
2720 }
2721
2722 static int
2723 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2724                     size_t fw_size)
2725 {
2726         struct hns3_adapter *hns = eth_dev->data->dev_private;
2727         struct hns3_hw *hw = &hns->hw;
2728         uint32_t version = hw->fw_version;
2729         int ret;
2730
2731         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2732                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2733                                       HNS3_FW_VERSION_BYTE3_S),
2734                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2735                                       HNS3_FW_VERSION_BYTE2_S),
2736                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2737                                       HNS3_FW_VERSION_BYTE1_S),
2738                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2739                                       HNS3_FW_VERSION_BYTE0_S));
2740         ret += 1; /* add the size of '\0' */
2741         if (fw_size < (uint32_t)ret)
2742                 return ret;
2743         else
2744                 return 0;
2745 }
2746
2747 static int
2748 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2749 {
2750         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2751         int ret;
2752
2753         (void)hns3_update_link_status(hw);
2754
2755         ret = hns3_update_link_info(eth_dev);
2756         if (ret)
2757                 hw->mac.link_status = ETH_LINK_DOWN;
2758
2759         return ret;
2760 }
2761
2762 static void
2763 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2764                       struct rte_eth_link *new_link)
2765 {
2766         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2767         struct hns3_mac *mac = &hw->mac;
2768
2769         switch (mac->link_speed) {
2770         case ETH_SPEED_NUM_10M:
2771         case ETH_SPEED_NUM_100M:
2772         case ETH_SPEED_NUM_1G:
2773         case ETH_SPEED_NUM_10G:
2774         case ETH_SPEED_NUM_25G:
2775         case ETH_SPEED_NUM_40G:
2776         case ETH_SPEED_NUM_50G:
2777         case ETH_SPEED_NUM_100G:
2778         case ETH_SPEED_NUM_200G:
2779                 new_link->link_speed = mac->link_speed;
2780                 break;
2781         default:
2782                 if (mac->link_status)
2783                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2784                 else
2785                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2786                 break;
2787         }
2788
2789         new_link->link_duplex = mac->link_duplex;
2790         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2791         new_link->link_autoneg =
2792             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2793 }
2794
2795 static int
2796 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2797 {
2798 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2799 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2800
2801         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2802         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2803         struct hns3_mac *mac = &hw->mac;
2804         struct rte_eth_link new_link;
2805         int ret;
2806
2807         do {
2808                 ret = hns3_update_port_link_info(eth_dev);
2809                 if (ret) {
2810                         hns3_err(hw, "failed to get port link info, ret = %d.",
2811                                  ret);
2812                         break;
2813                 }
2814
2815                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2816                         break;
2817
2818                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2819         } while (retry_cnt--);
2820
2821         memset(&new_link, 0, sizeof(new_link));
2822         hns3_setup_linkstatus(eth_dev, &new_link);
2823
2824         return rte_eth_linkstatus_set(eth_dev, &new_link);
2825 }
2826
2827 static int
2828 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2829 {
2830         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2831         struct hns3_pf *pf = &hns->pf;
2832
2833         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2834                 return -EINVAL;
2835
2836         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2837
2838         return 0;
2839 }
2840
2841 static int
2842 hns3_query_function_status(struct hns3_hw *hw)
2843 {
2844 #define HNS3_QUERY_MAX_CNT              10
2845 #define HNS3_QUERY_SLEEP_MSCOEND        1
2846         struct hns3_func_status_cmd *req;
2847         struct hns3_cmd_desc desc;
2848         int timeout = 0;
2849         int ret;
2850
2851         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2852         req = (struct hns3_func_status_cmd *)desc.data;
2853
2854         do {
2855                 ret = hns3_cmd_send(hw, &desc, 1);
2856                 if (ret) {
2857                         PMD_INIT_LOG(ERR, "query function status failed %d",
2858                                      ret);
2859                         return ret;
2860                 }
2861
2862                 /* Check pf reset is done */
2863                 if (req->pf_state)
2864                         break;
2865
2866                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2867         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2868
2869         return hns3_parse_func_status(hw, req);
2870 }
2871
2872 static int
2873 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2874 {
2875         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2876         struct hns3_pf *pf = &hns->pf;
2877
2878         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2879                 /*
2880                  * The total_tqps_num obtained from firmware is maximum tqp
2881                  * numbers of this port, which should be used for PF and VFs.
2882                  * There is no need for pf to have so many tqp numbers in
2883                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2884                  * coming from config file, is assigned to maximum queue number
2885                  * for the PF of this port by user. So users can modify the
2886                  * maximum queue number of PF according to their own application
2887                  * scenarios, which is more flexible to use. In addition, many
2888                  * memories can be saved due to allocating queue statistics
2889                  * room according to the actual number of queues required. The
2890                  * maximum queue number of PF for network engine with
2891                  * revision_id greater than 0x30 is assigned by config file.
2892                  */
2893                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2894                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2895                                  "must be greater than 0.",
2896                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2897                         return -EINVAL;
2898                 }
2899
2900                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2901                                        hw->total_tqps_num);
2902         } else {
2903                 /*
2904                  * Due to the limitation on the number of PF interrupts
2905                  * available, the maximum queue number assigned to PF on
2906                  * the network engine with revision_id 0x21 is 64.
2907                  */
2908                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2909                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2910         }
2911
2912         return 0;
2913 }
2914
2915 static int
2916 hns3_query_pf_resource(struct hns3_hw *hw)
2917 {
2918         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2919         struct hns3_pf *pf = &hns->pf;
2920         struct hns3_pf_res_cmd *req;
2921         struct hns3_cmd_desc desc;
2922         int ret;
2923
2924         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2925         ret = hns3_cmd_send(hw, &desc, 1);
2926         if (ret) {
2927                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2928                 return ret;
2929         }
2930
2931         req = (struct hns3_pf_res_cmd *)desc.data;
2932         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2933                              rte_le_to_cpu_16(req->ext_tqp_num);
2934         ret = hns3_get_pf_max_tqp_num(hw);
2935         if (ret)
2936                 return ret;
2937
2938         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2939         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2940
2941         if (req->tx_buf_size)
2942                 pf->tx_buf_size =
2943                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2944         else
2945                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2946
2947         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2948
2949         if (req->dv_buf_size)
2950                 pf->dv_buf_size =
2951                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2952         else
2953                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2954
2955         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2956
2957         hw->num_msi =
2958                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2959                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2960
2961         return 0;
2962 }
2963
2964 static void
2965 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2966 {
2967         struct hns3_cfg_param_cmd *req;
2968         uint64_t mac_addr_tmp_high;
2969         uint8_t ext_rss_size_max;
2970         uint64_t mac_addr_tmp;
2971         uint32_t i;
2972
2973         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2974
2975         /* get the configuration */
2976         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2977                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2978         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2979                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2980         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2981                                            HNS3_CFG_TQP_DESC_N_M,
2982                                            HNS3_CFG_TQP_DESC_N_S);
2983
2984         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2985                                        HNS3_CFG_PHY_ADDR_M,
2986                                        HNS3_CFG_PHY_ADDR_S);
2987         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2988                                          HNS3_CFG_MEDIA_TP_M,
2989                                          HNS3_CFG_MEDIA_TP_S);
2990         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2991                                          HNS3_CFG_RX_BUF_LEN_M,
2992                                          HNS3_CFG_RX_BUF_LEN_S);
2993         /* get mac address */
2994         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2995         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2996                                            HNS3_CFG_MAC_ADDR_H_M,
2997                                            HNS3_CFG_MAC_ADDR_H_S);
2998
2999         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3000
3001         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3002                                             HNS3_CFG_DEFAULT_SPEED_M,
3003                                             HNS3_CFG_DEFAULT_SPEED_S);
3004         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3005                                            HNS3_CFG_RSS_SIZE_M,
3006                                            HNS3_CFG_RSS_SIZE_S);
3007
3008         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3009                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3010
3011         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3012         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3013
3014         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3015                                             HNS3_CFG_SPEED_ABILITY_M,
3016                                             HNS3_CFG_SPEED_ABILITY_S);
3017         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3018                                         HNS3_CFG_UMV_TBL_SPACE_M,
3019                                         HNS3_CFG_UMV_TBL_SPACE_S);
3020         if (!cfg->umv_space)
3021                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3022
3023         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3024                                                HNS3_CFG_EXT_RSS_SIZE_M,
3025                                                HNS3_CFG_EXT_RSS_SIZE_S);
3026
3027         /*
3028          * Field ext_rss_size_max obtained from firmware will be more flexible
3029          * for future changes and expansions, which is an exponent of 2, instead
3030          * of reading out directly. If this field is not zero, hns3 PF PMD
3031          * driver uses it as rss_size_max under one TC. Device, whose revision
3032          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3033          * maximum number of queues supported under a TC through this field.
3034          */
3035         if (ext_rss_size_max)
3036                 cfg->rss_size_max = 1U << ext_rss_size_max;
3037 }
3038
3039 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3040  * @hw: pointer to struct hns3_hw
3041  * @hcfg: the config structure to be getted
3042  */
3043 static int
3044 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3045 {
3046         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3047         struct hns3_cfg_param_cmd *req;
3048         uint32_t offset;
3049         uint32_t i;
3050         int ret;
3051
3052         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3053                 offset = 0;
3054                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3055                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3056                                           true);
3057                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3058                                i * HNS3_CFG_RD_LEN_BYTES);
3059                 /* Len should be divided by 4 when send to hardware */
3060                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3061                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3062                 req->offset = rte_cpu_to_le_32(offset);
3063         }
3064
3065         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3066         if (ret) {
3067                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3068                 return ret;
3069         }
3070
3071         hns3_parse_cfg(hcfg, desc);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3078 {
3079         switch (speed_cmd) {
3080         case HNS3_CFG_SPEED_10M:
3081                 *speed = ETH_SPEED_NUM_10M;
3082                 break;
3083         case HNS3_CFG_SPEED_100M:
3084                 *speed = ETH_SPEED_NUM_100M;
3085                 break;
3086         case HNS3_CFG_SPEED_1G:
3087                 *speed = ETH_SPEED_NUM_1G;
3088                 break;
3089         case HNS3_CFG_SPEED_10G:
3090                 *speed = ETH_SPEED_NUM_10G;
3091                 break;
3092         case HNS3_CFG_SPEED_25G:
3093                 *speed = ETH_SPEED_NUM_25G;
3094                 break;
3095         case HNS3_CFG_SPEED_40G:
3096                 *speed = ETH_SPEED_NUM_40G;
3097                 break;
3098         case HNS3_CFG_SPEED_50G:
3099                 *speed = ETH_SPEED_NUM_50G;
3100                 break;
3101         case HNS3_CFG_SPEED_100G:
3102                 *speed = ETH_SPEED_NUM_100G;
3103                 break;
3104         case HNS3_CFG_SPEED_200G:
3105                 *speed = ETH_SPEED_NUM_200G;
3106                 break;
3107         default:
3108                 return -EINVAL;
3109         }
3110
3111         return 0;
3112 }
3113
3114 static void
3115 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3116 {
3117         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3118         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3119         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3120         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3121         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3122 }
3123
3124 static void
3125 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3126 {
3127         struct hns3_dev_specs_0_cmd *req0;
3128
3129         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3130
3131         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3132         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3133         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3134         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3135         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3136 }
3137
3138 static int
3139 hns3_check_dev_specifications(struct hns3_hw *hw)
3140 {
3141         if (hw->rss_ind_tbl_size == 0 ||
3142             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3143                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3144                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3145                               HNS3_RSS_IND_TBL_SIZE_MAX);
3146                 return -EINVAL;
3147         }
3148
3149         return 0;
3150 }
3151
3152 static int
3153 hns3_query_dev_specifications(struct hns3_hw *hw)
3154 {
3155         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3156         int ret;
3157         int i;
3158
3159         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3160                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3161                                           true);
3162                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3163         }
3164         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3165
3166         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3167         if (ret)
3168                 return ret;
3169
3170         hns3_parse_dev_specifications(hw, desc);
3171
3172         return hns3_check_dev_specifications(hw);
3173 }
3174
3175 static int
3176 hns3_get_capability(struct hns3_hw *hw)
3177 {
3178         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3179         struct rte_pci_device *pci_dev;
3180         struct hns3_pf *pf = &hns->pf;
3181         struct rte_eth_dev *eth_dev;
3182         uint16_t device_id;
3183         uint8_t revision;
3184         int ret;
3185
3186         eth_dev = &rte_eth_devices[hw->data->port_id];
3187         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3188         device_id = pci_dev->id.device_id;
3189
3190         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3191             device_id == HNS3_DEV_ID_50GE_RDMA ||
3192             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3193             device_id == HNS3_DEV_ID_200G_RDMA)
3194                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3195
3196         /* Get PCI revision id */
3197         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3198                                   HNS3_PCI_REVISION_ID);
3199         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3200                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3201                              ret);
3202                 return -EIO;
3203         }
3204         hw->revision = revision;
3205
3206         if (revision < PCI_REVISION_ID_HIP09_A) {
3207                 hns3_set_default_dev_specifications(hw);
3208                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3209                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3210                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3211                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3212                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3213                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3214                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3215                 hw->rss_info.ipv6_sctp_offload_supported = false;
3216                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3217                 return 0;
3218         }
3219
3220         ret = hns3_query_dev_specifications(hw);
3221         if (ret) {
3222                 PMD_INIT_LOG(ERR,
3223                              "failed to query dev specifications, ret = %d",
3224                              ret);
3225                 return ret;
3226         }
3227
3228         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3229         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3230         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3231         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3232         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3233         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3234         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3235         hw->rss_info.ipv6_sctp_offload_supported = true;
3236         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3237
3238         return 0;
3239 }
3240
3241 static int
3242 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3243 {
3244         int ret;
3245
3246         switch (media_type) {
3247         case HNS3_MEDIA_TYPE_COPPER:
3248                 if (!hns3_dev_copper_supported(hw)) {
3249                         PMD_INIT_LOG(ERR,
3250                                      "Media type is copper, not supported.");
3251                         ret = -EOPNOTSUPP;
3252                 } else {
3253                         ret = 0;
3254                 }
3255                 break;
3256         case HNS3_MEDIA_TYPE_FIBER:
3257                 ret = 0;
3258                 break;
3259         case HNS3_MEDIA_TYPE_BACKPLANE:
3260                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3261                 ret = -EOPNOTSUPP;
3262                 break;
3263         default:
3264                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3265                 ret = -EINVAL;
3266                 break;
3267         }
3268
3269         return ret;
3270 }
3271
3272 static int
3273 hns3_get_board_configuration(struct hns3_hw *hw)
3274 {
3275         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3276         struct hns3_pf *pf = &hns->pf;
3277         struct hns3_cfg cfg;
3278         int ret;
3279
3280         ret = hns3_get_board_cfg(hw, &cfg);
3281         if (ret) {
3282                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3283                 return ret;
3284         }
3285
3286         ret = hns3_check_media_type(hw, cfg.media_type);
3287         if (ret)
3288                 return ret;
3289
3290         hw->mac.media_type = cfg.media_type;
3291         hw->rss_size_max = cfg.rss_size_max;
3292         hw->rss_dis_flag = false;
3293         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3294         hw->mac.phy_addr = cfg.phy_addr;
3295         hw->mac.default_addr_setted = false;
3296         hw->num_tx_desc = cfg.tqp_desc_num;
3297         hw->num_rx_desc = cfg.tqp_desc_num;
3298         hw->dcb_info.num_pg = 1;
3299         hw->dcb_info.hw_pfc_map = 0;
3300
3301         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3302         if (ret) {
3303                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3304                              cfg.default_speed, ret);
3305                 return ret;
3306         }
3307
3308         pf->tc_max = cfg.tc_num;
3309         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3310                 PMD_INIT_LOG(WARNING,
3311                              "Get TC num(%u) from flash, set TC num to 1",
3312                              pf->tc_max);
3313                 pf->tc_max = 1;
3314         }
3315
3316         /* Dev does not support DCB */
3317         if (!hns3_dev_dcb_supported(hw)) {
3318                 pf->tc_max = 1;
3319                 pf->pfc_max = 0;
3320         } else
3321                 pf->pfc_max = pf->tc_max;
3322
3323         hw->dcb_info.num_tc = 1;
3324         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3325                                      hw->tqps_num / hw->dcb_info.num_tc);
3326         hns3_set_bit(hw->hw_tc_map, 0, 1);
3327         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3328
3329         pf->wanted_umv_size = cfg.umv_space;
3330
3331         return ret;
3332 }
3333
3334 static int
3335 hns3_get_configuration(struct hns3_hw *hw)
3336 {
3337         int ret;
3338
3339         ret = hns3_query_function_status(hw);
3340         if (ret) {
3341                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3342                 return ret;
3343         }
3344
3345         /* Get device capability */
3346         ret = hns3_get_capability(hw);
3347         if (ret) {
3348                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3349                 return ret;
3350         }
3351
3352         /* Get pf resource */
3353         ret = hns3_query_pf_resource(hw);
3354         if (ret) {
3355                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3356                 return ret;
3357         }
3358
3359         ret = hns3_get_board_configuration(hw);
3360         if (ret) {
3361                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3362                 return ret;
3363         }
3364
3365         ret = hns3_query_dev_fec_info(hw);
3366         if (ret)
3367                 PMD_INIT_LOG(ERR,
3368                              "failed to query FEC information, ret = %d", ret);
3369
3370         return ret;
3371 }
3372
3373 static int
3374 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3375                       uint16_t tqp_vid, bool is_pf)
3376 {
3377         struct hns3_tqp_map_cmd *req;
3378         struct hns3_cmd_desc desc;
3379         int ret;
3380
3381         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3382
3383         req = (struct hns3_tqp_map_cmd *)desc.data;
3384         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3385         req->tqp_vf = func_id;
3386         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3387         if (!is_pf)
3388                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3389         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3390
3391         ret = hns3_cmd_send(hw, &desc, 1);
3392         if (ret)
3393                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3394
3395         return ret;
3396 }
3397
3398 static int
3399 hns3_map_tqp(struct hns3_hw *hw)
3400 {
3401         int ret;
3402         int i;
3403
3404         /*
3405          * In current version, VF is not supported when PF is driven by DPDK
3406          * driver, so we assign total tqps_num tqps allocated to this port
3407          * to PF.
3408          */
3409         for (i = 0; i < hw->total_tqps_num; i++) {
3410                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3411                 if (ret)
3412                         return ret;
3413         }
3414
3415         return 0;
3416 }
3417
3418 static int
3419 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3420 {
3421         struct hns3_config_mac_speed_dup_cmd *req;
3422         struct hns3_cmd_desc desc;
3423         int ret;
3424
3425         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3426
3427         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3428
3429         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3430
3431         switch (speed) {
3432         case ETH_SPEED_NUM_10M:
3433                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3434                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3435                 break;
3436         case ETH_SPEED_NUM_100M:
3437                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3438                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3439                 break;
3440         case ETH_SPEED_NUM_1G:
3441                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3442                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3443                 break;
3444         case ETH_SPEED_NUM_10G:
3445                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3446                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3447                 break;
3448         case ETH_SPEED_NUM_25G:
3449                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3450                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3451                 break;
3452         case ETH_SPEED_NUM_40G:
3453                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3454                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3455                 break;
3456         case ETH_SPEED_NUM_50G:
3457                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3458                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3459                 break;
3460         case ETH_SPEED_NUM_100G:
3461                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3462                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3463                 break;
3464         case ETH_SPEED_NUM_200G:
3465                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3466                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3467                 break;
3468         default:
3469                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3470                 return -EINVAL;
3471         }
3472
3473         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3474
3475         ret = hns3_cmd_send(hw, &desc, 1);
3476         if (ret)
3477                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3478
3479         return ret;
3480 }
3481
3482 static int
3483 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3484 {
3485         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3486         struct hns3_pf *pf = &hns->pf;
3487         struct hns3_priv_buf *priv;
3488         uint32_t i, total_size;
3489
3490         total_size = pf->pkt_buf_size;
3491
3492         /* alloc tx buffer for all enabled tc */
3493         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3494                 priv = &buf_alloc->priv_buf[i];
3495
3496                 if (hw->hw_tc_map & BIT(i)) {
3497                         if (total_size < pf->tx_buf_size)
3498                                 return -ENOMEM;
3499
3500                         priv->tx_buf_size = pf->tx_buf_size;
3501                 } else
3502                         priv->tx_buf_size = 0;
3503
3504                 total_size -= priv->tx_buf_size;
3505         }
3506
3507         return 0;
3508 }
3509
3510 static int
3511 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3512 {
3513 /* TX buffer size is unit by 128 byte */
3514 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3515 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3516         struct hns3_tx_buff_alloc_cmd *req;
3517         struct hns3_cmd_desc desc;
3518         uint32_t buf_size;
3519         uint32_t i;
3520         int ret;
3521
3522         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3523
3524         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3525         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3526                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3527
3528                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3529                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3530                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3531         }
3532
3533         ret = hns3_cmd_send(hw, &desc, 1);
3534         if (ret)
3535                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3536
3537         return ret;
3538 }
3539
3540 static int
3541 hns3_get_tc_num(struct hns3_hw *hw)
3542 {
3543         int cnt = 0;
3544         uint8_t i;
3545
3546         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3547                 if (hw->hw_tc_map & BIT(i))
3548                         cnt++;
3549         return cnt;
3550 }
3551
3552 static uint32_t
3553 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3554 {
3555         struct hns3_priv_buf *priv;
3556         uint32_t rx_priv = 0;
3557         int i;
3558
3559         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3560                 priv = &buf_alloc->priv_buf[i];
3561                 if (priv->enable)
3562                         rx_priv += priv->buf_size;
3563         }
3564         return rx_priv;
3565 }
3566
3567 static uint32_t
3568 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3569 {
3570         uint32_t total_tx_size = 0;
3571         uint32_t i;
3572
3573         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3574                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3575
3576         return total_tx_size;
3577 }
3578
3579 /* Get the number of pfc enabled TCs, which have private buffer */
3580 static int
3581 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3582 {
3583         struct hns3_priv_buf *priv;
3584         int cnt = 0;
3585         uint8_t i;
3586
3587         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3588                 priv = &buf_alloc->priv_buf[i];
3589                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3590                         cnt++;
3591         }
3592
3593         return cnt;
3594 }
3595
3596 /* Get the number of pfc disabled TCs, which have private buffer */
3597 static int
3598 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3599                          struct hns3_pkt_buf_alloc *buf_alloc)
3600 {
3601         struct hns3_priv_buf *priv;
3602         int cnt = 0;
3603         uint8_t i;
3604
3605         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3606                 priv = &buf_alloc->priv_buf[i];
3607                 if (hw->hw_tc_map & BIT(i) &&
3608                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3609                         cnt++;
3610         }
3611
3612         return cnt;
3613 }
3614
3615 static bool
3616 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3617                   uint32_t rx_all)
3618 {
3619         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3620         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3621         struct hns3_pf *pf = &hns->pf;
3622         uint32_t shared_buf, aligned_mps;
3623         uint32_t rx_priv;
3624         uint8_t tc_num;
3625         uint8_t i;
3626
3627         tc_num = hns3_get_tc_num(hw);
3628         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3629
3630         if (hns3_dev_dcb_supported(hw))
3631                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3632                                         pf->dv_buf_size;
3633         else
3634                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3635                                         + pf->dv_buf_size;
3636
3637         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3638         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3639                              HNS3_BUF_SIZE_UNIT);
3640
3641         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3642         if (rx_all < rx_priv + shared_std)
3643                 return false;
3644
3645         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3646         buf_alloc->s_buf.buf_size = shared_buf;
3647         if (hns3_dev_dcb_supported(hw)) {
3648                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3649                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3650                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3651                                   HNS3_BUF_SIZE_UNIT);
3652         } else {
3653                 buf_alloc->s_buf.self.high =
3654                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3655                 buf_alloc->s_buf.self.low = aligned_mps;
3656         }
3657
3658         if (hns3_dev_dcb_supported(hw)) {
3659                 hi_thrd = shared_buf - pf->dv_buf_size;
3660
3661                 if (tc_num <= NEED_RESERVE_TC_NUM)
3662                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3663                                   BUF_MAX_PERCENT;
3664
3665                 if (tc_num)
3666                         hi_thrd = hi_thrd / tc_num;
3667
3668                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3669                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3670                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3671         } else {
3672                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3673                 lo_thrd = aligned_mps;
3674         }
3675
3676         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3677                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3678                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3679         }
3680
3681         return true;
3682 }
3683
3684 static bool
3685 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3686                      struct hns3_pkt_buf_alloc *buf_alloc)
3687 {
3688         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3689         struct hns3_pf *pf = &hns->pf;
3690         struct hns3_priv_buf *priv;
3691         uint32_t aligned_mps;
3692         uint32_t rx_all;
3693         uint8_t i;
3694
3695         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3696         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3697
3698         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3699                 priv = &buf_alloc->priv_buf[i];
3700
3701                 priv->enable = 0;
3702                 priv->wl.low = 0;
3703                 priv->wl.high = 0;
3704                 priv->buf_size = 0;
3705
3706                 if (!(hw->hw_tc_map & BIT(i)))
3707                         continue;
3708
3709                 priv->enable = 1;
3710                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3711                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3712                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3713                                                 HNS3_BUF_SIZE_UNIT);
3714                 } else {
3715                         priv->wl.low = 0;
3716                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3717                                         aligned_mps;
3718                 }
3719
3720                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3721         }
3722
3723         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3724 }
3725
3726 static bool
3727 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3728                              struct hns3_pkt_buf_alloc *buf_alloc)
3729 {
3730         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3731         struct hns3_pf *pf = &hns->pf;
3732         struct hns3_priv_buf *priv;
3733         int no_pfc_priv_num;
3734         uint32_t rx_all;
3735         uint8_t mask;
3736         int i;
3737
3738         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3739         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3740
3741         /* let the last to be cleared first */
3742         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3743                 priv = &buf_alloc->priv_buf[i];
3744                 mask = BIT((uint8_t)i);
3745
3746                 if (hw->hw_tc_map & mask &&
3747                     !(hw->dcb_info.hw_pfc_map & mask)) {
3748                         /* Clear the no pfc TC private buffer */
3749                         priv->wl.low = 0;
3750                         priv->wl.high = 0;
3751                         priv->buf_size = 0;
3752                         priv->enable = 0;
3753                         no_pfc_priv_num--;
3754                 }
3755
3756                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3757                     no_pfc_priv_num == 0)
3758                         break;
3759         }
3760
3761         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3762 }
3763
3764 static bool
3765 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3766                            struct hns3_pkt_buf_alloc *buf_alloc)
3767 {
3768         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3769         struct hns3_pf *pf = &hns->pf;
3770         struct hns3_priv_buf *priv;
3771         uint32_t rx_all;
3772         int pfc_priv_num;
3773         uint8_t mask;
3774         int i;
3775
3776         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3777         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3778
3779         /* let the last to be cleared first */
3780         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3781                 priv = &buf_alloc->priv_buf[i];
3782                 mask = BIT((uint8_t)i);
3783                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3784                         /* Reduce the number of pfc TC with private buffer */
3785                         priv->wl.low = 0;
3786                         priv->enable = 0;
3787                         priv->wl.high = 0;
3788                         priv->buf_size = 0;
3789                         pfc_priv_num--;
3790                 }
3791                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3792                     pfc_priv_num == 0)
3793                         break;
3794         }
3795
3796         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3797 }
3798
3799 static bool
3800 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3801                           struct hns3_pkt_buf_alloc *buf_alloc)
3802 {
3803 #define COMPENSATE_BUFFER       0x3C00
3804 #define COMPENSATE_HALF_MPS_NUM 5
3805 #define PRIV_WL_GAP             0x1800
3806         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3807         struct hns3_pf *pf = &hns->pf;
3808         uint32_t tc_num = hns3_get_tc_num(hw);
3809         uint32_t half_mps = pf->mps >> 1;
3810         struct hns3_priv_buf *priv;
3811         uint32_t min_rx_priv;
3812         uint32_t rx_priv;
3813         uint8_t i;
3814
3815         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3816         if (tc_num)
3817                 rx_priv = rx_priv / tc_num;
3818
3819         if (tc_num <= NEED_RESERVE_TC_NUM)
3820                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3821
3822         /*
3823          * Minimum value of private buffer in rx direction (min_rx_priv) is
3824          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3825          * buffer if rx_priv is greater than min_rx_priv.
3826          */
3827         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3828                         COMPENSATE_HALF_MPS_NUM * half_mps;
3829         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3830         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3831
3832         if (rx_priv < min_rx_priv)
3833                 return false;
3834
3835         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3836                 priv = &buf_alloc->priv_buf[i];
3837                 priv->enable = 0;
3838                 priv->wl.low = 0;
3839                 priv->wl.high = 0;
3840                 priv->buf_size = 0;
3841
3842                 if (!(hw->hw_tc_map & BIT(i)))
3843                         continue;
3844
3845                 priv->enable = 1;
3846                 priv->buf_size = rx_priv;
3847                 priv->wl.high = rx_priv - pf->dv_buf_size;
3848                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3849         }
3850
3851         buf_alloc->s_buf.buf_size = 0;
3852
3853         return true;
3854 }
3855
3856 /*
3857  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3858  * @hw: pointer to struct hns3_hw
3859  * @buf_alloc: pointer to buffer calculation data
3860  * @return: 0: calculate sucessful, negative: fail
3861  */
3862 static int
3863 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3864 {
3865         /* When DCB is not supported, rx private buffer is not allocated. */
3866         if (!hns3_dev_dcb_supported(hw)) {
3867                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3868                 struct hns3_pf *pf = &hns->pf;
3869                 uint32_t rx_all = pf->pkt_buf_size;
3870
3871                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3872                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3873                         return -ENOMEM;
3874
3875                 return 0;
3876         }
3877
3878         /*
3879          * Try to allocate privated packet buffer for all TCs without share
3880          * buffer.
3881          */
3882         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3883                 return 0;
3884
3885         /*
3886          * Try to allocate privated packet buffer for all TCs with share
3887          * buffer.
3888          */
3889         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3890                 return 0;
3891
3892         /*
3893          * For different application scenes, the enabled port number, TC number
3894          * and no_drop TC number are different. In order to obtain the better
3895          * performance, software could allocate the buffer size and configure
3896          * the waterline by tring to decrease the private buffer size according
3897          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3898          * enabled tc.
3899          */
3900         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3901                 return 0;
3902
3903         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3904                 return 0;
3905
3906         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3907                 return 0;
3908
3909         return -ENOMEM;
3910 }
3911
3912 static int
3913 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3914 {
3915         struct hns3_rx_priv_buff_cmd *req;
3916         struct hns3_cmd_desc desc;
3917         uint32_t buf_size;
3918         int ret;
3919         int i;
3920
3921         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3922         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3923
3924         /* Alloc private buffer TCs */
3925         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3926                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3927
3928                 req->buf_num[i] =
3929                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3930                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3931         }
3932
3933         buf_size = buf_alloc->s_buf.buf_size;
3934         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3935                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3936
3937         ret = hns3_cmd_send(hw, &desc, 1);
3938         if (ret)
3939                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3940
3941         return ret;
3942 }
3943
3944 static int
3945 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3946 {
3947 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3948         struct hns3_rx_priv_wl_buf *req;
3949         struct hns3_priv_buf *priv;
3950         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3951         int i, j;
3952         int ret;
3953
3954         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3955                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3956                                           false);
3957                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3958
3959                 /* The first descriptor set the NEXT bit to 1 */
3960                 if (i == 0)
3961                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3962                 else
3963                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3964
3965                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3966                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3967
3968                         priv = &buf_alloc->priv_buf[idx];
3969                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3970                                                         HNS3_BUF_UNIT_S);
3971                         req->tc_wl[j].high |=
3972                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3973                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3974                                                         HNS3_BUF_UNIT_S);
3975                         req->tc_wl[j].low |=
3976                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3977                 }
3978         }
3979
3980         /* Send 2 descriptor at one time */
3981         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3982         if (ret)
3983                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3984                              ret);
3985         return ret;
3986 }
3987
3988 static int
3989 hns3_common_thrd_config(struct hns3_hw *hw,
3990                         struct hns3_pkt_buf_alloc *buf_alloc)
3991 {
3992 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3993         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3994         struct hns3_rx_com_thrd *req;
3995         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3996         struct hns3_tc_thrd *tc;
3997         int tc_idx;
3998         int i, j;
3999         int ret;
4000
4001         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4002                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4003                                           false);
4004                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4005
4006                 /* The first descriptor set the NEXT bit to 1 */
4007                 if (i == 0)
4008                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4009                 else
4010                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4011
4012                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4013                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4014                         tc = &s_buf->tc_thrd[tc_idx];
4015
4016                         req->com_thrd[j].high =
4017                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4018                         req->com_thrd[j].high |=
4019                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4020                         req->com_thrd[j].low =
4021                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4022                         req->com_thrd[j].low |=
4023                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4024                 }
4025         }
4026
4027         /* Send 2 descriptors at one time */
4028         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4029         if (ret)
4030                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4031
4032         return ret;
4033 }
4034
4035 static int
4036 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4037 {
4038         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4039         struct hns3_rx_com_wl *req;
4040         struct hns3_cmd_desc desc;
4041         int ret;
4042
4043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4044
4045         req = (struct hns3_rx_com_wl *)desc.data;
4046         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4047         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4048
4049         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4050         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4051
4052         ret = hns3_cmd_send(hw, &desc, 1);
4053         if (ret)
4054                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4055
4056         return ret;
4057 }
4058
4059 int
4060 hns3_buffer_alloc(struct hns3_hw *hw)
4061 {
4062         struct hns3_pkt_buf_alloc pkt_buf;
4063         int ret;
4064
4065         memset(&pkt_buf, 0, sizeof(pkt_buf));
4066         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4067         if (ret) {
4068                 PMD_INIT_LOG(ERR,
4069                              "could not calc tx buffer size for all TCs %d",
4070                              ret);
4071                 return ret;
4072         }
4073
4074         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4075         if (ret) {
4076                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4077                 return ret;
4078         }
4079
4080         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4081         if (ret) {
4082                 PMD_INIT_LOG(ERR,
4083                              "could not calc rx priv buffer size for all TCs %d",
4084                              ret);
4085                 return ret;
4086         }
4087
4088         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4089         if (ret) {
4090                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4091                 return ret;
4092         }
4093
4094         if (hns3_dev_dcb_supported(hw)) {
4095                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4096                 if (ret) {
4097                         PMD_INIT_LOG(ERR,
4098                                      "could not configure rx private waterline %d",
4099                                      ret);
4100                         return ret;
4101                 }
4102
4103                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4104                 if (ret) {
4105                         PMD_INIT_LOG(ERR,
4106                                      "could not configure common threshold %d",
4107                                      ret);
4108                         return ret;
4109                 }
4110         }
4111
4112         ret = hns3_common_wl_config(hw, &pkt_buf);
4113         if (ret)
4114                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4115                              ret);
4116
4117         return ret;
4118 }
4119
4120 static int
4121 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4122 {
4123         struct hns3_firmware_compat_cmd *req;
4124         struct hns3_cmd_desc desc;
4125         uint32_t compat = 0;
4126
4127         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4128         req = (struct hns3_firmware_compat_cmd *)desc.data;
4129
4130         if (is_init) {
4131                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4132                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4133                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4134                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4135         }
4136
4137         req->compat = rte_cpu_to_le_32(compat);
4138
4139         return hns3_cmd_send(hw, &desc, 1);
4140 }
4141
4142 static int
4143 hns3_mac_init(struct hns3_hw *hw)
4144 {
4145         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4146         struct hns3_mac *mac = &hw->mac;
4147         struct hns3_pf *pf = &hns->pf;
4148         int ret;
4149
4150         pf->support_sfp_query = true;
4151         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4152         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4153         if (ret) {
4154                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4155                 return ret;
4156         }
4157
4158         mac->link_status = ETH_LINK_DOWN;
4159
4160         return hns3_config_mtu(hw, pf->mps);
4161 }
4162
4163 static int
4164 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4165 {
4166 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4167 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4168 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4169 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4170         int return_status;
4171
4172         if (cmdq_resp) {
4173                 PMD_INIT_LOG(ERR,
4174                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4175                              cmdq_resp);
4176                 return -EIO;
4177         }
4178
4179         switch (resp_code) {
4180         case HNS3_ETHERTYPE_SUCCESS_ADD:
4181         case HNS3_ETHERTYPE_ALREADY_ADD:
4182                 return_status = 0;
4183                 break;
4184         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4185                 PMD_INIT_LOG(ERR,
4186                              "add mac ethertype failed for manager table overflow.");
4187                 return_status = -EIO;
4188                 break;
4189         case HNS3_ETHERTYPE_KEY_CONFLICT:
4190                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4191                 return_status = -EIO;
4192                 break;
4193         default:
4194                 PMD_INIT_LOG(ERR,
4195                              "add mac ethertype failed for undefined, code=%u.",
4196                              resp_code);
4197                 return_status = -EIO;
4198                 break;
4199         }
4200
4201         return return_status;
4202 }
4203
4204 static int
4205 hns3_add_mgr_tbl(struct hns3_hw *hw,
4206                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4207 {
4208         struct hns3_cmd_desc desc;
4209         uint8_t resp_code;
4210         uint16_t retval;
4211         int ret;
4212
4213         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4214         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4215
4216         ret = hns3_cmd_send(hw, &desc, 1);
4217         if (ret) {
4218                 PMD_INIT_LOG(ERR,
4219                              "add mac ethertype failed for cmd_send, ret =%d.",
4220                              ret);
4221                 return ret;
4222         }
4223
4224         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4225         retval = rte_le_to_cpu_16(desc.retval);
4226
4227         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4228 }
4229
4230 static void
4231 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4232                      int *table_item_num)
4233 {
4234         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4235
4236         /*
4237          * In current version, we add one item in management table as below:
4238          * 0x0180C200000E -- LLDP MC address
4239          */
4240         tbl = mgr_table;
4241         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4242         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4243         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4244         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4245         tbl->i_port_bitmap = 0x1;
4246         *table_item_num = 1;
4247 }
4248
4249 static int
4250 hns3_init_mgr_tbl(struct hns3_hw *hw)
4251 {
4252 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4253         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4254         int table_item_num;
4255         int ret;
4256         int i;
4257
4258         memset(mgr_table, 0, sizeof(mgr_table));
4259         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4260         for (i = 0; i < table_item_num; i++) {
4261                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4262                 if (ret) {
4263                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4264                                      ret);
4265                         return ret;
4266                 }
4267         }
4268
4269         return 0;
4270 }
4271
4272 static void
4273 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4274                         bool en_mc, bool en_bc, int vport_id)
4275 {
4276         if (!param)
4277                 return;
4278
4279         memset(param, 0, sizeof(struct hns3_promisc_param));
4280         if (en_uc)
4281                 param->enable = HNS3_PROMISC_EN_UC;
4282         if (en_mc)
4283                 param->enable |= HNS3_PROMISC_EN_MC;
4284         if (en_bc)
4285                 param->enable |= HNS3_PROMISC_EN_BC;
4286         param->vf_id = vport_id;
4287 }
4288
4289 static int
4290 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4291 {
4292         struct hns3_promisc_cfg_cmd *req;
4293         struct hns3_cmd_desc desc;
4294         int ret;
4295
4296         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4297
4298         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4299         req->vf_id = param->vf_id;
4300         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4301             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4302
4303         ret = hns3_cmd_send(hw, &desc, 1);
4304         if (ret)
4305                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4306
4307         return ret;
4308 }
4309
4310 static int
4311 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4312 {
4313         struct hns3_promisc_param param;
4314         bool en_bc_pmc = true;
4315         uint8_t vf_id;
4316
4317         /*
4318          * In current version VF is not supported when PF is driven by DPDK
4319          * driver, just need to configure parameters for PF vport.
4320          */
4321         vf_id = HNS3_PF_FUNC_ID;
4322
4323         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4324         return hns3_cmd_set_promisc_mode(hw, &param);
4325 }
4326
4327 static int
4328 hns3_promisc_init(struct hns3_hw *hw)
4329 {
4330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4331         struct hns3_pf *pf = &hns->pf;
4332         struct hns3_promisc_param param;
4333         uint16_t func_id;
4334         int ret;
4335
4336         ret = hns3_set_promisc_mode(hw, false, false);
4337         if (ret) {
4338                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4339                 return ret;
4340         }
4341
4342         /*
4343          * In current version VFs are not supported when PF is driven by DPDK
4344          * driver. After PF has been taken over by DPDK, the original VF will
4345          * be invalid. So, there is a possibility of entry residues. It should
4346          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4347          * during init.
4348          */
4349         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4350                 hns3_promisc_param_init(&param, false, false, false, func_id);
4351                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4352                 if (ret) {
4353                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4354                                         " ret = %d", func_id, ret);
4355                         return ret;
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 static void
4363 hns3_promisc_uninit(struct hns3_hw *hw)
4364 {
4365         struct hns3_promisc_param param;
4366         uint16_t func_id;
4367         int ret;
4368
4369         func_id = HNS3_PF_FUNC_ID;
4370
4371         /*
4372          * In current version VFs are not supported when PF is driven by
4373          * DPDK driver, and VFs' promisc mode status has been cleared during
4374          * init and their status will not change. So just clear PF's promisc
4375          * mode status during uninit.
4376          */
4377         hns3_promisc_param_init(&param, false, false, false, func_id);
4378         ret = hns3_cmd_set_promisc_mode(hw, &param);
4379         if (ret)
4380                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4381                                 " uninit, ret = %d", ret);
4382 }
4383
4384 static int
4385 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4386 {
4387         bool allmulti = dev->data->all_multicast ? true : false;
4388         struct hns3_adapter *hns = dev->data->dev_private;
4389         struct hns3_hw *hw = &hns->hw;
4390         uint64_t offloads;
4391         int err;
4392         int ret;
4393
4394         rte_spinlock_lock(&hw->lock);
4395         ret = hns3_set_promisc_mode(hw, true, true);
4396         if (ret) {
4397                 rte_spinlock_unlock(&hw->lock);
4398                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4399                          ret);
4400                 return ret;
4401         }
4402
4403         /*
4404          * When promiscuous mode was enabled, disable the vlan filter to let
4405          * all packets coming in in the receiving direction.
4406          */
4407         offloads = dev->data->dev_conf.rxmode.offloads;
4408         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4409                 ret = hns3_enable_vlan_filter(hns, false);
4410                 if (ret) {
4411                         hns3_err(hw, "failed to enable promiscuous mode due to "
4412                                      "failure to disable vlan filter, ret = %d",
4413                                  ret);
4414                         err = hns3_set_promisc_mode(hw, false, allmulti);
4415                         if (err)
4416                                 hns3_err(hw, "failed to restore promiscuous "
4417                                          "status after disable vlan filter "
4418                                          "failed during enabling promiscuous "
4419                                          "mode, ret = %d", ret);
4420                 }
4421         }
4422
4423         rte_spinlock_unlock(&hw->lock);
4424
4425         return ret;
4426 }
4427
4428 static int
4429 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4430 {
4431         bool allmulti = dev->data->all_multicast ? true : false;
4432         struct hns3_adapter *hns = dev->data->dev_private;
4433         struct hns3_hw *hw = &hns->hw;
4434         uint64_t offloads;
4435         int err;
4436         int ret;
4437
4438         /* If now in all_multicast mode, must remain in all_multicast mode. */
4439         rte_spinlock_lock(&hw->lock);
4440         ret = hns3_set_promisc_mode(hw, false, allmulti);
4441         if (ret) {
4442                 rte_spinlock_unlock(&hw->lock);
4443                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4444                          ret);
4445                 return ret;
4446         }
4447         /* when promiscuous mode was disabled, restore the vlan filter status */
4448         offloads = dev->data->dev_conf.rxmode.offloads;
4449         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4450                 ret = hns3_enable_vlan_filter(hns, true);
4451                 if (ret) {
4452                         hns3_err(hw, "failed to disable promiscuous mode due to"
4453                                  " failure to restore vlan filter, ret = %d",
4454                                  ret);
4455                         err = hns3_set_promisc_mode(hw, true, true);
4456                         if (err)
4457                                 hns3_err(hw, "failed to restore promiscuous "
4458                                          "status after enabling vlan filter "
4459                                          "failed during disabling promiscuous "
4460                                          "mode, ret = %d", ret);
4461                 }
4462         }
4463         rte_spinlock_unlock(&hw->lock);
4464
4465         return ret;
4466 }
4467
4468 static int
4469 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4470 {
4471         struct hns3_adapter *hns = dev->data->dev_private;
4472         struct hns3_hw *hw = &hns->hw;
4473         int ret;
4474
4475         if (dev->data->promiscuous)
4476                 return 0;
4477
4478         rte_spinlock_lock(&hw->lock);
4479         ret = hns3_set_promisc_mode(hw, false, true);
4480         rte_spinlock_unlock(&hw->lock);
4481         if (ret)
4482                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4483                          ret);
4484
4485         return ret;
4486 }
4487
4488 static int
4489 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4490 {
4491         struct hns3_adapter *hns = dev->data->dev_private;
4492         struct hns3_hw *hw = &hns->hw;
4493         int ret;
4494
4495         /* If now in promiscuous mode, must remain in all_multicast mode. */
4496         if (dev->data->promiscuous)
4497                 return 0;
4498
4499         rte_spinlock_lock(&hw->lock);
4500         ret = hns3_set_promisc_mode(hw, false, false);
4501         rte_spinlock_unlock(&hw->lock);
4502         if (ret)
4503                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4504                          ret);
4505
4506         return ret;
4507 }
4508
4509 static int
4510 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4511 {
4512         struct hns3_hw *hw = &hns->hw;
4513         bool allmulti = hw->data->all_multicast ? true : false;
4514         int ret;
4515
4516         if (hw->data->promiscuous) {
4517                 ret = hns3_set_promisc_mode(hw, true, true);
4518                 if (ret)
4519                         hns3_err(hw, "failed to restore promiscuous mode, "
4520                                  "ret = %d", ret);
4521                 return ret;
4522         }
4523
4524         ret = hns3_set_promisc_mode(hw, false, allmulti);
4525         if (ret)
4526                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4527                          ret);
4528         return ret;
4529 }
4530
4531 static int
4532 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4533 {
4534         struct hns3_sfp_speed_cmd *resp;
4535         struct hns3_cmd_desc desc;
4536         int ret;
4537
4538         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4539         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4540         ret = hns3_cmd_send(hw, &desc, 1);
4541         if (ret == -EOPNOTSUPP) {
4542                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4543                 return ret;
4544         } else if (ret) {
4545                 hns3_err(hw, "get sfp speed failed %d", ret);
4546                 return ret;
4547         }
4548
4549         *speed = resp->sfp_speed;
4550
4551         return 0;
4552 }
4553
4554 static uint8_t
4555 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4556 {
4557         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4558                 duplex = ETH_LINK_FULL_DUPLEX;
4559
4560         return duplex;
4561 }
4562
4563 static int
4564 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4565 {
4566         struct hns3_mac *mac = &hw->mac;
4567         int ret;
4568
4569         duplex = hns3_check_speed_dup(duplex, speed);
4570         if (mac->link_speed == speed && mac->link_duplex == duplex)
4571                 return 0;
4572
4573         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4574         if (ret)
4575                 return ret;
4576
4577         ret = hns3_port_shaper_update(hw, speed);
4578         if (ret)
4579                 return ret;
4580
4581         mac->link_speed = speed;
4582         mac->link_duplex = duplex;
4583
4584         return 0;
4585 }
4586
4587 static int
4588 hns3_update_fiber_link_info(struct hns3_hw *hw)
4589 {
4590         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4591         uint32_t speed;
4592         int ret;
4593
4594         /* If IMP do not support get SFP/qSFP speed, return directly */
4595         if (!pf->support_sfp_query)
4596                 return 0;
4597
4598         ret = hns3_get_sfp_speed(hw, &speed);
4599         if (ret == -EOPNOTSUPP) {
4600                 pf->support_sfp_query = false;
4601                 return ret;
4602         } else if (ret)
4603                 return ret;
4604
4605         if (speed == ETH_SPEED_NUM_NONE)
4606                 return 0; /* do nothing if no SFP */
4607
4608         /* Config full duplex for SFP */
4609         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4610 }
4611
4612 static void
4613 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4614 {
4615         struct hns3_phy_params_bd0_cmd *req;
4616
4617         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4618         mac->link_speed = rte_le_to_cpu_32(req->speed);
4619         mac->link_duplex = hns3_get_bit(req->duplex,
4620                                            HNS3_PHY_DUPLEX_CFG_B);
4621         mac->link_autoneg = hns3_get_bit(req->autoneg,
4622                                            HNS3_PHY_AUTONEG_CFG_B);
4623         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4624         mac->advertising = rte_le_to_cpu_32(req->advertising);
4625         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4626         mac->support_autoneg = !!(mac->supported_capa &
4627                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4628 }
4629
4630 static int
4631 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4632 {
4633         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4634         uint16_t i;
4635         int ret;
4636
4637         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4638                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4639                                           true);
4640                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4641         }
4642         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4643
4644         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4645         if (ret) {
4646                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4647                 return ret;
4648         }
4649
4650         hns3_parse_copper_phy_params(desc, mac);
4651
4652         return 0;
4653 }
4654
4655 static int
4656 hns3_update_copper_link_info(struct hns3_hw *hw)
4657 {
4658         struct hns3_mac *mac = &hw->mac;
4659         struct hns3_mac mac_info;
4660         int ret;
4661
4662         memset(&mac_info, 0, sizeof(struct hns3_mac));
4663         ret = hns3_get_copper_phy_params(hw, &mac_info);
4664         if (ret)
4665                 return ret;
4666
4667         if (mac_info.link_speed != mac->link_speed) {
4668                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4669                 if (ret)
4670                         return ret;
4671         }
4672
4673         mac->link_speed = mac_info.link_speed;
4674         mac->link_duplex = mac_info.link_duplex;
4675         mac->link_autoneg = mac_info.link_autoneg;
4676         mac->supported_capa = mac_info.supported_capa;
4677         mac->advertising = mac_info.advertising;
4678         mac->lp_advertising = mac_info.lp_advertising;
4679         mac->support_autoneg = mac_info.support_autoneg;
4680
4681         return 0;
4682 }
4683
4684 static int
4685 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4686 {
4687         struct hns3_adapter *hns = eth_dev->data->dev_private;
4688         struct hns3_hw *hw = &hns->hw;
4689         int ret = 0;
4690
4691         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4692                 ret = hns3_update_copper_link_info(hw);
4693         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4694                 ret = hns3_update_fiber_link_info(hw);
4695
4696         return ret;
4697 }
4698
4699 static int
4700 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4701 {
4702         struct hns3_config_mac_mode_cmd *req;
4703         struct hns3_cmd_desc desc;
4704         uint32_t loop_en = 0;
4705         uint8_t val = 0;
4706         int ret;
4707
4708         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4709
4710         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4711         if (enable)
4712                 val = 1;
4713         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4714         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4715         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4716         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4717         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4718         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4719         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4720         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4721         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4722         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4723
4724         /*
4725          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4726          * when receiving frames. Otherwise, CRC will be stripped.
4727          */
4728         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4729                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4730         else
4731                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4732         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4733         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4734         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4735         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4736
4737         ret = hns3_cmd_send(hw, &desc, 1);
4738         if (ret)
4739                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4740
4741         return ret;
4742 }
4743
4744 static int
4745 hns3_get_mac_link_status(struct hns3_hw *hw)
4746 {
4747         struct hns3_link_status_cmd *req;
4748         struct hns3_cmd_desc desc;
4749         int link_status;
4750         int ret;
4751
4752         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4753         ret = hns3_cmd_send(hw, &desc, 1);
4754         if (ret) {
4755                 hns3_err(hw, "get link status cmd failed %d", ret);
4756                 return ETH_LINK_DOWN;
4757         }
4758
4759         req = (struct hns3_link_status_cmd *)desc.data;
4760         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4761
4762         return !!link_status;
4763 }
4764
4765 static bool
4766 hns3_update_link_status(struct hns3_hw *hw)
4767 {
4768         int state;
4769
4770         state = hns3_get_mac_link_status(hw);
4771         if (state != hw->mac.link_status) {
4772                 hw->mac.link_status = state;
4773                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4774                 hns3_config_mac_tnl_int(hw,
4775                                         state == ETH_LINK_UP ? true : false);
4776                 return true;
4777         }
4778
4779         return false;
4780 }
4781
4782 void
4783 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4784 {
4785         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4786         struct rte_eth_link new_link;
4787         int ret;
4788
4789         if (query)
4790                 hns3_update_port_link_info(dev);
4791
4792         memset(&new_link, 0, sizeof(new_link));
4793         hns3_setup_linkstatus(dev, &new_link);
4794
4795         ret = rte_eth_linkstatus_set(dev, &new_link);
4796         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4797                 hns3_start_report_lse(dev);
4798 }
4799
4800 static void
4801 hns3_service_handler(void *param)
4802 {
4803         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4804         struct hns3_adapter *hns = eth_dev->data->dev_private;
4805         struct hns3_hw *hw = &hns->hw;
4806
4807         if (!hns3_is_reset_pending(hns))
4808                 hns3_update_linkstatus_and_event(hw, true);
4809         else
4810                 hns3_warn(hw, "Cancel the query when reset is pending");
4811
4812         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4813 }
4814
4815 static void
4816 hns3_update_dev_lsc_cap(struct hns3_hw *hw,
4817                         int fw_compact_cmd_result)
4818 {
4819         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4820
4821         if (hw->adapter_state != HNS3_NIC_UNINITIALIZED)
4822                 return;
4823
4824         if (fw_compact_cmd_result != 0) {
4825                 /*
4826                  * If fw_compact_cmd_result is not zero, it means firmware don't
4827                  * support link status change interrupt.
4828                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
4829                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. It need to clear
4830                  * the RTE_ETH_DEV_INTR_LSC capability when detect firmware
4831                  * don't support link status change interrupt.
4832                  */
4833                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
4834         }
4835 }
4836
4837 static int
4838 hns3_init_hardware(struct hns3_adapter *hns)
4839 {
4840         struct hns3_hw *hw = &hns->hw;
4841         int ret;
4842
4843         ret = hns3_map_tqp(hw);
4844         if (ret) {
4845                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4846                 return ret;
4847         }
4848
4849         ret = hns3_init_umv_space(hw);
4850         if (ret) {
4851                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4852                 return ret;
4853         }
4854
4855         ret = hns3_mac_init(hw);
4856         if (ret) {
4857                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4858                 goto err_mac_init;
4859         }
4860
4861         ret = hns3_init_mgr_tbl(hw);
4862         if (ret) {
4863                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4864                 goto err_mac_init;
4865         }
4866
4867         ret = hns3_promisc_init(hw);
4868         if (ret) {
4869                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4870                              ret);
4871                 goto err_mac_init;
4872         }
4873
4874         ret = hns3_init_vlan_config(hns);
4875         if (ret) {
4876                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4877                 goto err_mac_init;
4878         }
4879
4880         ret = hns3_dcb_init(hw);
4881         if (ret) {
4882                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4883                 goto err_mac_init;
4884         }
4885
4886         ret = hns3_init_fd_config(hns);
4887         if (ret) {
4888                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4889                 goto err_mac_init;
4890         }
4891
4892         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4893         if (ret) {
4894                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4895                 goto err_mac_init;
4896         }
4897
4898         ret = hns3_config_gro(hw, false);
4899         if (ret) {
4900                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4901                 goto err_mac_init;
4902         }
4903
4904         /*
4905          * In the initialization clearing the all hardware mapping relationship
4906          * configurations between queues and interrupt vectors is needed, so
4907          * some error caused by the residual configurations, such as the
4908          * unexpected interrupt, can be avoid.
4909          */
4910         ret = hns3_init_ring_with_vector(hw);
4911         if (ret) {
4912                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4913                 goto err_mac_init;
4914         }
4915
4916         /*
4917          * Requiring firmware to enable some features, driver can
4918          * still work without it.
4919          */
4920         ret = hns3_firmware_compat_config(hw, true);
4921         if (ret)
4922                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4923                              "supported, ret = %d.", ret);
4924         hns3_update_dev_lsc_cap(hw, ret);
4925
4926         return 0;
4927
4928 err_mac_init:
4929         hns3_uninit_umv_space(hw);
4930         return ret;
4931 }
4932
4933 static int
4934 hns3_clear_hw(struct hns3_hw *hw)
4935 {
4936         struct hns3_cmd_desc desc;
4937         int ret;
4938
4939         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4940
4941         ret = hns3_cmd_send(hw, &desc, 1);
4942         if (ret && ret != -EOPNOTSUPP)
4943                 return ret;
4944
4945         return 0;
4946 }
4947
4948 static void
4949 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4950 {
4951         uint32_t val;
4952
4953         /*
4954          * The new firmware support report more hardware error types by
4955          * msix mode. These errors are defined as RAS errors in hardware
4956          * and belong to a different type from the MSI-x errors processed
4957          * by the network driver.
4958          *
4959          * Network driver should open the new error report on initialition
4960          */
4961         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4962         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4963         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4964 }
4965
4966 static int
4967 hns3_init_pf(struct rte_eth_dev *eth_dev)
4968 {
4969         struct rte_device *dev = eth_dev->device;
4970         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4971         struct hns3_adapter *hns = eth_dev->data->dev_private;
4972         struct hns3_hw *hw = &hns->hw;
4973         int ret;
4974
4975         PMD_INIT_FUNC_TRACE();
4976
4977         /* Get hardware io base address from pcie BAR2 IO space */
4978         hw->io_base = pci_dev->mem_resource[2].addr;
4979
4980         /* Firmware command queue initialize */
4981         ret = hns3_cmd_init_queue(hw);
4982         if (ret) {
4983                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4984                 goto err_cmd_init_queue;
4985         }
4986
4987         hns3_clear_all_event_cause(hw);
4988
4989         /* Firmware command initialize */
4990         ret = hns3_cmd_init(hw);
4991         if (ret) {
4992                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4993                 goto err_cmd_init;
4994         }
4995
4996         /*
4997          * To ensure that the hardware environment is clean during
4998          * initialization, the driver actively clear the hardware environment
4999          * during initialization, including PF and corresponding VFs' vlan, mac,
5000          * flow table configurations, etc.
5001          */
5002         ret = hns3_clear_hw(hw);
5003         if (ret) {
5004                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5005                 goto err_cmd_init;
5006         }
5007
5008         /* Hardware statistics of imissed registers cleared. */
5009         ret = hns3_update_imissed_stats(hw, true);
5010         if (ret) {
5011                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5012                 goto err_cmd_init;
5013         }
5014
5015         hns3_config_all_msix_error(hw, true);
5016
5017         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5018                                          hns3_interrupt_handler,
5019                                          eth_dev);
5020         if (ret) {
5021                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5022                 goto err_intr_callback_register;
5023         }
5024
5025         ret = hns3_ptp_init(hw);
5026         if (ret)
5027                 goto err_get_config;
5028
5029         /* Enable interrupt */
5030         rte_intr_enable(&pci_dev->intr_handle);
5031         hns3_pf_enable_irq0(hw);
5032
5033         /* Get configuration */
5034         ret = hns3_get_configuration(hw);
5035         if (ret) {
5036                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5037                 goto err_get_config;
5038         }
5039
5040         ret = hns3_tqp_stats_init(hw);
5041         if (ret)
5042                 goto err_get_config;
5043
5044         ret = hns3_init_hardware(hns);
5045         if (ret) {
5046                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5047                 goto err_init_hw;
5048         }
5049
5050         /* Initialize flow director filter list & hash */
5051         ret = hns3_fdir_filter_init(hns);
5052         if (ret) {
5053                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5054                 goto err_fdir;
5055         }
5056
5057         hns3_rss_set_default_args(hw);
5058
5059         ret = hns3_enable_hw_error_intr(hns, true);
5060         if (ret) {
5061                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5062                              ret);
5063                 goto err_enable_intr;
5064         }
5065
5066         hns3_tm_conf_init(eth_dev);
5067
5068         return 0;
5069
5070 err_enable_intr:
5071         hns3_fdir_filter_uninit(hns);
5072 err_fdir:
5073         (void)hns3_firmware_compat_config(hw, false);
5074         hns3_uninit_umv_space(hw);
5075 err_init_hw:
5076         hns3_tqp_stats_uninit(hw);
5077 err_get_config:
5078         hns3_pf_disable_irq0(hw);
5079         rte_intr_disable(&pci_dev->intr_handle);
5080         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5081                              eth_dev);
5082 err_intr_callback_register:
5083 err_cmd_init:
5084         hns3_cmd_uninit(hw);
5085         hns3_cmd_destroy_queue(hw);
5086 err_cmd_init_queue:
5087         hw->io_base = NULL;
5088
5089         return ret;
5090 }
5091
5092 static void
5093 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5094 {
5095         struct hns3_adapter *hns = eth_dev->data->dev_private;
5096         struct rte_device *dev = eth_dev->device;
5097         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5098         struct hns3_hw *hw = &hns->hw;
5099
5100         PMD_INIT_FUNC_TRACE();
5101
5102         hns3_tm_conf_uninit(eth_dev);
5103         hns3_enable_hw_error_intr(hns, false);
5104         hns3_rss_uninit(hns);
5105         (void)hns3_config_gro(hw, false);
5106         hns3_promisc_uninit(hw);
5107         hns3_fdir_filter_uninit(hns);
5108         (void)hns3_firmware_compat_config(hw, false);
5109         hns3_uninit_umv_space(hw);
5110         hns3_tqp_stats_uninit(hw);
5111         hns3_config_mac_tnl_int(hw, false);
5112         hns3_pf_disable_irq0(hw);
5113         rte_intr_disable(&pci_dev->intr_handle);
5114         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5115                              eth_dev);
5116         hns3_config_all_msix_error(hw, false);
5117         hns3_cmd_uninit(hw);
5118         hns3_cmd_destroy_queue(hw);
5119         hw->io_base = NULL;
5120 }
5121
5122 static int
5123 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5124 {
5125         struct hns3_hw *hw = &hns->hw;
5126         int ret;
5127
5128         ret = hns3_dcb_cfg_update(hns);
5129         if (ret)
5130                 return ret;
5131
5132         /*
5133          * The hns3_dcb_cfg_update may configure TM module, so
5134          * hns3_tm_conf_update must called later.
5135          */
5136         ret = hns3_tm_conf_update(hw);
5137         if (ret) {
5138                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5139                 return ret;
5140         }
5141
5142         hns3_enable_rxd_adv_layout(hw);
5143
5144         ret = hns3_init_queues(hns, reset_queue);
5145         if (ret) {
5146                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5147                 return ret;
5148         }
5149
5150         ret = hns3_cfg_mac_mode(hw, true);
5151         if (ret) {
5152                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5153                 goto err_config_mac_mode;
5154         }
5155         return 0;
5156
5157 err_config_mac_mode:
5158         hns3_dev_release_mbufs(hns);
5159         /*
5160          * Here is exception handling, hns3_reset_all_tqps will have the
5161          * corresponding error message if it is handled incorrectly, so it is
5162          * not necessary to check hns3_reset_all_tqps return value, here keep
5163          * ret as the error code causing the exception.
5164          */
5165         (void)hns3_reset_all_tqps(hns);
5166         return ret;
5167 }
5168
5169 static int
5170 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5171 {
5172         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5173         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5174         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5175         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5176         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5177         uint32_t intr_vector;
5178         uint16_t q_id;
5179         int ret;
5180
5181         /*
5182          * hns3 needs a separate interrupt to be used as event interrupt which
5183          * could not be shared with task queue pair, so KERNEL drivers need
5184          * support multiple interrupt vectors.
5185          */
5186         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5187             !rte_intr_cap_multiple(intr_handle))
5188                 return 0;
5189
5190         rte_intr_disable(intr_handle);
5191         intr_vector = hw->used_rx_queues;
5192         /* creates event fd for each intr vector when MSIX is used */
5193         if (rte_intr_efd_enable(intr_handle, intr_vector))
5194                 return -EINVAL;
5195
5196         if (intr_handle->intr_vec == NULL) {
5197                 intr_handle->intr_vec =
5198                         rte_zmalloc("intr_vec",
5199                                     hw->used_rx_queues * sizeof(int), 0);
5200                 if (intr_handle->intr_vec == NULL) {
5201                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5202                                         hw->used_rx_queues);
5203                         ret = -ENOMEM;
5204                         goto alloc_intr_vec_error;
5205                 }
5206         }
5207
5208         if (rte_intr_allow_others(intr_handle)) {
5209                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5210                 base = RTE_INTR_VEC_RXTX_OFFSET;
5211         }
5212
5213         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5214                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5215                                                  HNS3_RING_TYPE_RX, q_id);
5216                 if (ret)
5217                         goto bind_vector_error;
5218                 intr_handle->intr_vec[q_id] = vec;
5219                 /*
5220                  * If there are not enough efds (e.g. not enough interrupt),
5221                  * remaining queues will be bond to the last interrupt.
5222                  */
5223                 if (vec < base + intr_handle->nb_efd - 1)
5224                         vec++;
5225         }
5226         rte_intr_enable(intr_handle);
5227         return 0;
5228
5229 bind_vector_error:
5230         rte_free(intr_handle->intr_vec);
5231         intr_handle->intr_vec = NULL;
5232 alloc_intr_vec_error:
5233         rte_intr_efd_disable(intr_handle);
5234         return ret;
5235 }
5236
5237 static int
5238 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5239 {
5240         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5242         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5243         uint16_t q_id;
5244         int ret;
5245
5246         if (dev->data->dev_conf.intr_conf.rxq == 0)
5247                 return 0;
5248
5249         if (rte_intr_dp_is_en(intr_handle)) {
5250                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5251                         ret = hns3_bind_ring_with_vector(hw,
5252                                         intr_handle->intr_vec[q_id], true,
5253                                         HNS3_RING_TYPE_RX, q_id);
5254                         if (ret)
5255                                 return ret;
5256                 }
5257         }
5258
5259         return 0;
5260 }
5261
5262 static void
5263 hns3_restore_filter(struct rte_eth_dev *dev)
5264 {
5265         hns3_restore_rss_filter(dev);
5266 }
5267
5268 static int
5269 hns3_dev_start(struct rte_eth_dev *dev)
5270 {
5271         struct hns3_adapter *hns = dev->data->dev_private;
5272         struct hns3_hw *hw = &hns->hw;
5273         int ret;
5274
5275         PMD_INIT_FUNC_TRACE();
5276         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5277                 return -EBUSY;
5278
5279         rte_spinlock_lock(&hw->lock);
5280         hw->adapter_state = HNS3_NIC_STARTING;
5281
5282         ret = hns3_do_start(hns, true);
5283         if (ret) {
5284                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5285                 rte_spinlock_unlock(&hw->lock);
5286                 return ret;
5287         }
5288         ret = hns3_map_rx_interrupt(dev);
5289         if (ret)
5290                 goto map_rx_inter_err;
5291
5292         /*
5293          * There are three register used to control the status of a TQP
5294          * (contains a pair of Tx queue and Rx queue) in the new version network
5295          * engine. One is used to control the enabling of Tx queue, the other is
5296          * used to control the enabling of Rx queue, and the last is the master
5297          * switch used to control the enabling of the tqp. The Tx register and
5298          * TQP register must be enabled at the same time to enable a Tx queue.
5299          * The same applies to the Rx queue. For the older network engine, this
5300          * function only refresh the enabled flag, and it is used to update the
5301          * status of queue in the dpdk framework.
5302          */
5303         ret = hns3_start_all_txqs(dev);
5304         if (ret)
5305                 goto map_rx_inter_err;
5306
5307         ret = hns3_start_all_rxqs(dev);
5308         if (ret)
5309                 goto start_all_rxqs_fail;
5310
5311         hw->adapter_state = HNS3_NIC_STARTED;
5312         rte_spinlock_unlock(&hw->lock);
5313
5314         hns3_rx_scattered_calc(dev);
5315         hns3_set_rxtx_function(dev);
5316         hns3_mp_req_start_rxtx(dev);
5317
5318         hns3_restore_filter(dev);
5319
5320         /* Enable interrupt of all rx queues before enabling queues */
5321         hns3_dev_all_rx_queue_intr_enable(hw, true);
5322
5323         /*
5324          * After finished the initialization, enable tqps to receive/transmit
5325          * packets and refresh all queue status.
5326          */
5327         hns3_start_tqps(hw);
5328
5329         hns3_tm_dev_start_proc(hw);
5330
5331         if (dev->data->dev_conf.intr_conf.lsc != 0)
5332                 hns3_dev_link_update(dev, 0);
5333         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5334
5335         hns3_info(hw, "hns3 dev start successful!");
5336
5337         return 0;
5338
5339 start_all_rxqs_fail:
5340         hns3_stop_all_txqs(dev);
5341 map_rx_inter_err:
5342         (void)hns3_do_stop(hns);
5343         hw->adapter_state = HNS3_NIC_CONFIGURED;
5344         rte_spinlock_unlock(&hw->lock);
5345
5346         return ret;
5347 }
5348
5349 static int
5350 hns3_do_stop(struct hns3_adapter *hns)
5351 {
5352         struct hns3_hw *hw = &hns->hw;
5353         int ret;
5354
5355         /*
5356          * The "hns3_do_stop" function will also be called by .stop_service to
5357          * prepare reset. At the time of global or IMP reset, the command cannot
5358          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5359          * accessed during the reset process. So the mbuf can not be released
5360          * during reset and is required to be released after the reset is
5361          * completed.
5362          */
5363         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5364                 hns3_dev_release_mbufs(hns);
5365
5366         ret = hns3_cfg_mac_mode(hw, false);
5367         if (ret)
5368                 return ret;
5369         hw->mac.link_status = ETH_LINK_DOWN;
5370
5371         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5372                 hns3_configure_all_mac_addr(hns, true);
5373                 ret = hns3_reset_all_tqps(hns);
5374                 if (ret) {
5375                         hns3_err(hw, "failed to reset all queues ret = %d.",
5376                                  ret);
5377                         return ret;
5378                 }
5379         }
5380         hw->mac.default_addr_setted = false;
5381         return 0;
5382 }
5383
5384 static void
5385 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5386 {
5387         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5389         struct hns3_adapter *hns = dev->data->dev_private;
5390         struct hns3_hw *hw = &hns->hw;
5391         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5392         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5393         uint16_t q_id;
5394
5395         if (dev->data->dev_conf.intr_conf.rxq == 0)
5396                 return;
5397
5398         /* unmap the ring with vector */
5399         if (rte_intr_allow_others(intr_handle)) {
5400                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5401                 base = RTE_INTR_VEC_RXTX_OFFSET;
5402         }
5403         if (rte_intr_dp_is_en(intr_handle)) {
5404                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5405                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5406                                                          HNS3_RING_TYPE_RX,
5407                                                          q_id);
5408                         if (vec < base + intr_handle->nb_efd - 1)
5409                                 vec++;
5410                 }
5411         }
5412         /* Clean datapath event and queue/vec mapping */
5413         rte_intr_efd_disable(intr_handle);
5414         if (intr_handle->intr_vec) {
5415                 rte_free(intr_handle->intr_vec);
5416                 intr_handle->intr_vec = NULL;
5417         }
5418 }
5419
5420 static int
5421 hns3_dev_stop(struct rte_eth_dev *dev)
5422 {
5423         struct hns3_adapter *hns = dev->data->dev_private;
5424         struct hns3_hw *hw = &hns->hw;
5425
5426         PMD_INIT_FUNC_TRACE();
5427         dev->data->dev_started = 0;
5428
5429         hw->adapter_state = HNS3_NIC_STOPPING;
5430         hns3_set_rxtx_function(dev);
5431         rte_wmb();
5432         /* Disable datapath on secondary process. */
5433         hns3_mp_req_stop_rxtx(dev);
5434         /* Prevent crashes when queues are still in use. */
5435         rte_delay_ms(hw->tqps_num);
5436
5437         rte_spinlock_lock(&hw->lock);
5438         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5439                 hns3_tm_dev_stop_proc(hw);
5440                 hns3_config_mac_tnl_int(hw, false);
5441                 hns3_stop_tqps(hw);
5442                 hns3_do_stop(hns);
5443                 hns3_unmap_rx_interrupt(dev);
5444                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5445         }
5446         hns3_rx_scattered_reset(dev);
5447         rte_eal_alarm_cancel(hns3_service_handler, dev);
5448         hns3_stop_report_lse(dev);
5449         rte_spinlock_unlock(&hw->lock);
5450
5451         return 0;
5452 }
5453
5454 static int
5455 hns3_dev_close(struct rte_eth_dev *eth_dev)
5456 {
5457         struct hns3_adapter *hns = eth_dev->data->dev_private;
5458         struct hns3_hw *hw = &hns->hw;
5459         int ret = 0;
5460
5461         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5462                 rte_free(eth_dev->process_private);
5463                 eth_dev->process_private = NULL;
5464                 return 0;
5465         }
5466
5467         if (hw->adapter_state == HNS3_NIC_STARTED)
5468                 ret = hns3_dev_stop(eth_dev);
5469
5470         hw->adapter_state = HNS3_NIC_CLOSING;
5471         hns3_reset_abort(hns);
5472         hw->adapter_state = HNS3_NIC_CLOSED;
5473
5474         hns3_configure_all_mc_mac_addr(hns, true);
5475         hns3_remove_all_vlan_table(hns);
5476         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5477         hns3_uninit_pf(eth_dev);
5478         hns3_free_all_queues(eth_dev);
5479         rte_free(hw->reset.wait_data);
5480         rte_free(eth_dev->process_private);
5481         eth_dev->process_private = NULL;
5482         hns3_mp_uninit_primary();
5483         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5484
5485         return ret;
5486 }
5487
5488 static int
5489 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5490 {
5491         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5493
5494         fc_conf->pause_time = pf->pause_time;
5495
5496         /* return fc current mode */
5497         switch (hw->current_mode) {
5498         case HNS3_FC_FULL:
5499                 fc_conf->mode = RTE_FC_FULL;
5500                 break;
5501         case HNS3_FC_TX_PAUSE:
5502                 fc_conf->mode = RTE_FC_TX_PAUSE;
5503                 break;
5504         case HNS3_FC_RX_PAUSE:
5505                 fc_conf->mode = RTE_FC_RX_PAUSE;
5506                 break;
5507         case HNS3_FC_NONE:
5508         default:
5509                 fc_conf->mode = RTE_FC_NONE;
5510                 break;
5511         }
5512
5513         return 0;
5514 }
5515
5516 static void
5517 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5518 {
5519         switch (mode) {
5520         case RTE_FC_NONE:
5521                 hw->requested_mode = HNS3_FC_NONE;
5522                 break;
5523         case RTE_FC_RX_PAUSE:
5524                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5525                 break;
5526         case RTE_FC_TX_PAUSE:
5527                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5528                 break;
5529         case RTE_FC_FULL:
5530                 hw->requested_mode = HNS3_FC_FULL;
5531                 break;
5532         default:
5533                 hw->requested_mode = HNS3_FC_NONE;
5534                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5535                           "configured to RTE_FC_NONE", mode);
5536                 break;
5537         }
5538 }
5539
5540 static int
5541 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5542 {
5543         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5545         int ret;
5546
5547         if (fc_conf->high_water || fc_conf->low_water ||
5548             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5549                 hns3_err(hw, "Unsupported flow control settings specified, "
5550                          "high_water(%u), low_water(%u), send_xon(%u) and "
5551                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5552                          fc_conf->high_water, fc_conf->low_water,
5553                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5554                 return -EINVAL;
5555         }
5556         if (fc_conf->autoneg) {
5557                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5558                 return -EINVAL;
5559         }
5560         if (!fc_conf->pause_time) {
5561                 hns3_err(hw, "Invalid pause time %u setting.",
5562                          fc_conf->pause_time);
5563                 return -EINVAL;
5564         }
5565
5566         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5567             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5568                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5569                          "current_fc_status = %d", hw->current_fc_status);
5570                 return -EOPNOTSUPP;
5571         }
5572
5573         if (hw->num_tc > 1) {
5574                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5575                 return -EOPNOTSUPP;
5576         }
5577
5578         hns3_get_fc_mode(hw, fc_conf->mode);
5579         if (hw->requested_mode == hw->current_mode &&
5580             pf->pause_time == fc_conf->pause_time)
5581                 return 0;
5582
5583         rte_spinlock_lock(&hw->lock);
5584         ret = hns3_fc_enable(dev, fc_conf);
5585         rte_spinlock_unlock(&hw->lock);
5586
5587         return ret;
5588 }
5589
5590 static int
5591 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5592                             struct rte_eth_pfc_conf *pfc_conf)
5593 {
5594         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5596         uint8_t priority;
5597         int ret;
5598
5599         if (!hns3_dev_dcb_supported(hw)) {
5600                 hns3_err(hw, "This port does not support dcb configurations.");
5601                 return -EOPNOTSUPP;
5602         }
5603
5604         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5605             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5606                 hns3_err(hw, "Unsupported flow control settings specified, "
5607                          "high_water(%u), low_water(%u), send_xon(%u) and "
5608                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5609                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5610                          pfc_conf->fc.send_xon,
5611                          pfc_conf->fc.mac_ctrl_frame_fwd);
5612                 return -EINVAL;
5613         }
5614         if (pfc_conf->fc.autoneg) {
5615                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5616                 return -EINVAL;
5617         }
5618         if (pfc_conf->fc.pause_time == 0) {
5619                 hns3_err(hw, "Invalid pause time %u setting.",
5620                          pfc_conf->fc.pause_time);
5621                 return -EINVAL;
5622         }
5623
5624         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5625             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5626                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5627                              "current_fc_status = %d", hw->current_fc_status);
5628                 return -EOPNOTSUPP;
5629         }
5630
5631         priority = pfc_conf->priority;
5632         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5633         if (hw->dcb_info.pfc_en & BIT(priority) &&
5634             hw->requested_mode == hw->current_mode &&
5635             pfc_conf->fc.pause_time == pf->pause_time)
5636                 return 0;
5637
5638         rte_spinlock_lock(&hw->lock);
5639         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5640         rte_spinlock_unlock(&hw->lock);
5641
5642         return ret;
5643 }
5644
5645 static int
5646 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5647 {
5648         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5650         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5651         int i;
5652
5653         rte_spinlock_lock(&hw->lock);
5654         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5655                 dcb_info->nb_tcs = pf->local_max_tc;
5656         else
5657                 dcb_info->nb_tcs = 1;
5658
5659         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5660                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5661         for (i = 0; i < dcb_info->nb_tcs; i++)
5662                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5663
5664         for (i = 0; i < hw->num_tc; i++) {
5665                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5666                 dcb_info->tc_queue.tc_txq[0][i].base =
5667                                                 hw->tc_queue[i].tqp_offset;
5668                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5669                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5670                                                 hw->tc_queue[i].tqp_count;
5671         }
5672         rte_spinlock_unlock(&hw->lock);
5673
5674         return 0;
5675 }
5676
5677 static int
5678 hns3_reinit_dev(struct hns3_adapter *hns)
5679 {
5680         struct hns3_hw *hw = &hns->hw;
5681         int ret;
5682
5683         ret = hns3_cmd_init(hw);
5684         if (ret) {
5685                 hns3_err(hw, "Failed to init cmd: %d", ret);
5686                 return ret;
5687         }
5688
5689         ret = hns3_reset_all_tqps(hns);
5690         if (ret) {
5691                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5692                 return ret;
5693         }
5694
5695         ret = hns3_init_hardware(hns);
5696         if (ret) {
5697                 hns3_err(hw, "Failed to init hardware: %d", ret);
5698                 return ret;
5699         }
5700
5701         ret = hns3_enable_hw_error_intr(hns, true);
5702         if (ret) {
5703                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5704                              ret);
5705                 return ret;
5706         }
5707         hns3_info(hw, "Reset done, driver initialization finished.");
5708
5709         return 0;
5710 }
5711
5712 static bool
5713 is_pf_reset_done(struct hns3_hw *hw)
5714 {
5715         uint32_t val, reg, reg_bit;
5716
5717         switch (hw->reset.level) {
5718         case HNS3_IMP_RESET:
5719                 reg = HNS3_GLOBAL_RESET_REG;
5720                 reg_bit = HNS3_IMP_RESET_BIT;
5721                 break;
5722         case HNS3_GLOBAL_RESET:
5723                 reg = HNS3_GLOBAL_RESET_REG;
5724                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5725                 break;
5726         case HNS3_FUNC_RESET:
5727                 reg = HNS3_FUN_RST_ING;
5728                 reg_bit = HNS3_FUN_RST_ING_B;
5729                 break;
5730         case HNS3_FLR_RESET:
5731         default:
5732                 hns3_err(hw, "Wait for unsupported reset level: %d",
5733                          hw->reset.level);
5734                 return true;
5735         }
5736         val = hns3_read_dev(hw, reg);
5737         if (hns3_get_bit(val, reg_bit))
5738                 return false;
5739         else
5740                 return true;
5741 }
5742
5743 bool
5744 hns3_is_reset_pending(struct hns3_adapter *hns)
5745 {
5746         struct hns3_hw *hw = &hns->hw;
5747         enum hns3_reset_level reset;
5748
5749         hns3_check_event_cause(hns, NULL);
5750         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5751         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5752                 hns3_warn(hw, "High level reset %d is pending", reset);
5753                 return true;
5754         }
5755         reset = hns3_get_reset_level(hns, &hw->reset.request);
5756         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5757                 hns3_warn(hw, "High level reset %d is request", reset);
5758                 return true;
5759         }
5760         return false;
5761 }
5762
5763 static int
5764 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5765 {
5766         struct hns3_hw *hw = &hns->hw;
5767         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5768         struct timeval tv;
5769
5770         if (wait_data->result == HNS3_WAIT_SUCCESS)
5771                 return 0;
5772         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5773                 gettimeofday(&tv, NULL);
5774                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5775                           tv.tv_sec, tv.tv_usec);
5776                 return -ETIME;
5777         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5778                 return -EAGAIN;
5779
5780         wait_data->hns = hns;
5781         wait_data->check_completion = is_pf_reset_done;
5782         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5783                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5784         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5785         wait_data->count = HNS3_RESET_WAIT_CNT;
5786         wait_data->result = HNS3_WAIT_REQUEST;
5787         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5788         return -EAGAIN;
5789 }
5790
5791 static int
5792 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5793 {
5794         struct hns3_cmd_desc desc;
5795         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5796
5797         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5798         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5799         req->fun_reset_vfid = func_id;
5800
5801         return hns3_cmd_send(hw, &desc, 1);
5802 }
5803
5804 static int
5805 hns3_imp_reset_cmd(struct hns3_hw *hw)
5806 {
5807         struct hns3_cmd_desc desc;
5808
5809         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5810         desc.data[0] = 0xeedd;
5811
5812         return hns3_cmd_send(hw, &desc, 1);
5813 }
5814
5815 static void
5816 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5817 {
5818         struct hns3_hw *hw = &hns->hw;
5819         struct timeval tv;
5820         uint32_t val;
5821
5822         gettimeofday(&tv, NULL);
5823         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5824             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5825                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5826                           tv.tv_sec, tv.tv_usec);
5827                 return;
5828         }
5829
5830         switch (reset_level) {
5831         case HNS3_IMP_RESET:
5832                 hns3_imp_reset_cmd(hw);
5833                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5834                           tv.tv_sec, tv.tv_usec);
5835                 break;
5836         case HNS3_GLOBAL_RESET:
5837                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5838                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5839                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5840                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5841                           tv.tv_sec, tv.tv_usec);
5842                 break;
5843         case HNS3_FUNC_RESET:
5844                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5845                           tv.tv_sec, tv.tv_usec);
5846                 /* schedule again to check later */
5847                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5848                 hns3_schedule_reset(hns);
5849                 break;
5850         default:
5851                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5852                 return;
5853         }
5854         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5855 }
5856
5857 static enum hns3_reset_level
5858 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5859 {
5860         struct hns3_hw *hw = &hns->hw;
5861         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5862
5863         /* Return the highest priority reset level amongst all */
5864         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5865                 reset_level = HNS3_IMP_RESET;
5866         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5867                 reset_level = HNS3_GLOBAL_RESET;
5868         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5869                 reset_level = HNS3_FUNC_RESET;
5870         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5871                 reset_level = HNS3_FLR_RESET;
5872
5873         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5874                 return HNS3_NONE_RESET;
5875
5876         return reset_level;
5877 }
5878
5879 static void
5880 hns3_record_imp_error(struct hns3_adapter *hns)
5881 {
5882         struct hns3_hw *hw = &hns->hw;
5883         uint32_t reg_val;
5884
5885         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5886         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5887                 hns3_warn(hw, "Detected IMP RD poison!");
5888                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5889                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5890         }
5891
5892         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5893                 hns3_warn(hw, "Detected IMP CMDQ error!");
5894                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5895                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5896         }
5897 }
5898
5899 static int
5900 hns3_prepare_reset(struct hns3_adapter *hns)
5901 {
5902         struct hns3_hw *hw = &hns->hw;
5903         uint32_t reg_val;
5904         int ret;
5905
5906         switch (hw->reset.level) {
5907         case HNS3_FUNC_RESET:
5908                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5909                 if (ret)
5910                         return ret;
5911
5912                 /*
5913                  * After performaning pf reset, it is not necessary to do the
5914                  * mailbox handling or send any command to firmware, because
5915                  * any mailbox handling or command to firmware is only valid
5916                  * after hns3_cmd_init is called.
5917                  */
5918                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5919                 hw->reset.stats.request_cnt++;
5920                 break;
5921         case HNS3_IMP_RESET:
5922                 hns3_record_imp_error(hns);
5923                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5924                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5925                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5926                 break;
5927         default:
5928                 break;
5929         }
5930         return 0;
5931 }
5932
5933 static int
5934 hns3_set_rst_done(struct hns3_hw *hw)
5935 {
5936         struct hns3_pf_rst_done_cmd *req;
5937         struct hns3_cmd_desc desc;
5938
5939         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5940         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5941         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5942         return hns3_cmd_send(hw, &desc, 1);
5943 }
5944
5945 static int
5946 hns3_stop_service(struct hns3_adapter *hns)
5947 {
5948         struct hns3_hw *hw = &hns->hw;
5949         struct rte_eth_dev *eth_dev;
5950
5951         eth_dev = &rte_eth_devices[hw->data->port_id];
5952         hw->mac.link_status = ETH_LINK_DOWN;
5953         if (hw->adapter_state == HNS3_NIC_STARTED) {
5954                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5955                 hns3_update_linkstatus_and_event(hw, false);
5956         }
5957
5958         hns3_set_rxtx_function(eth_dev);
5959         rte_wmb();
5960         /* Disable datapath on secondary process. */
5961         hns3_mp_req_stop_rxtx(eth_dev);
5962         rte_delay_ms(hw->tqps_num);
5963
5964         rte_spinlock_lock(&hw->lock);
5965         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5966             hw->adapter_state == HNS3_NIC_STOPPING) {
5967                 hns3_enable_all_queues(hw, false);
5968                 hns3_do_stop(hns);
5969                 hw->reset.mbuf_deferred_free = true;
5970         } else
5971                 hw->reset.mbuf_deferred_free = false;
5972
5973         /*
5974          * It is cumbersome for hardware to pick-and-choose entries for deletion
5975          * from table space. Hence, for function reset software intervention is
5976          * required to delete the entries
5977          */
5978         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5979                 hns3_configure_all_mc_mac_addr(hns, true);
5980         rte_spinlock_unlock(&hw->lock);
5981
5982         return 0;
5983 }
5984
5985 static int
5986 hns3_start_service(struct hns3_adapter *hns)
5987 {
5988         struct hns3_hw *hw = &hns->hw;
5989         struct rte_eth_dev *eth_dev;
5990
5991         if (hw->reset.level == HNS3_IMP_RESET ||
5992             hw->reset.level == HNS3_GLOBAL_RESET)
5993                 hns3_set_rst_done(hw);
5994         eth_dev = &rte_eth_devices[hw->data->port_id];
5995         hns3_set_rxtx_function(eth_dev);
5996         hns3_mp_req_start_rxtx(eth_dev);
5997         if (hw->adapter_state == HNS3_NIC_STARTED) {
5998                 /*
5999                  * This API parent function already hold the hns3_hw.lock, the
6000                  * hns3_service_handler may report lse, in bonding application
6001                  * it will call driver's ops which may acquire the hns3_hw.lock
6002                  * again, thus lead to deadlock.
6003                  * We defer calls hns3_service_handler to avoid the deadlock.
6004                  */
6005                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6006                                   hns3_service_handler, eth_dev);
6007
6008                 /* Enable interrupt of all rx queues before enabling queues */
6009                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6010                 /*
6011                  * Enable state of each rxq and txq will be recovered after
6012                  * reset, so we need to restore them before enable all tqps;
6013                  */
6014                 hns3_restore_tqp_enable_state(hw);
6015                 /*
6016                  * When finished the initialization, enable queues to receive
6017                  * and transmit packets.
6018                  */
6019                 hns3_enable_all_queues(hw, true);
6020         }
6021
6022         return 0;
6023 }
6024
6025 static int
6026 hns3_restore_conf(struct hns3_adapter *hns)
6027 {
6028         struct hns3_hw *hw = &hns->hw;
6029         int ret;
6030
6031         ret = hns3_configure_all_mac_addr(hns, false);
6032         if (ret)
6033                 return ret;
6034
6035         ret = hns3_configure_all_mc_mac_addr(hns, false);
6036         if (ret)
6037                 goto err_mc_mac;
6038
6039         ret = hns3_dev_promisc_restore(hns);
6040         if (ret)
6041                 goto err_promisc;
6042
6043         ret = hns3_restore_vlan_table(hns);
6044         if (ret)
6045                 goto err_promisc;
6046
6047         ret = hns3_restore_vlan_conf(hns);
6048         if (ret)
6049                 goto err_promisc;
6050
6051         ret = hns3_restore_all_fdir_filter(hns);
6052         if (ret)
6053                 goto err_promisc;
6054
6055         ret = hns3_restore_ptp(hns);
6056         if (ret)
6057                 goto err_promisc;
6058
6059         ret = hns3_restore_rx_interrupt(hw);
6060         if (ret)
6061                 goto err_promisc;
6062
6063         ret = hns3_restore_gro_conf(hw);
6064         if (ret)
6065                 goto err_promisc;
6066
6067         ret = hns3_restore_fec(hw);
6068         if (ret)
6069                 goto err_promisc;
6070
6071         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6072                 ret = hns3_do_start(hns, false);
6073                 if (ret)
6074                         goto err_promisc;
6075                 hns3_info(hw, "hns3 dev restart successful!");
6076         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6077                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6078         return 0;
6079
6080 err_promisc:
6081         hns3_configure_all_mc_mac_addr(hns, true);
6082 err_mc_mac:
6083         hns3_configure_all_mac_addr(hns, true);
6084         return ret;
6085 }
6086
6087 static void
6088 hns3_reset_service(void *param)
6089 {
6090         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6091         struct hns3_hw *hw = &hns->hw;
6092         enum hns3_reset_level reset_level;
6093         struct timeval tv_delta;
6094         struct timeval tv_start;
6095         struct timeval tv;
6096         uint64_t msec;
6097         int ret;
6098
6099         /*
6100          * The interrupt is not triggered within the delay time.
6101          * The interrupt may have been lost. It is necessary to handle
6102          * the interrupt to recover from the error.
6103          */
6104         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6105                             SCHEDULE_DEFERRED) {
6106                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6107                                   __ATOMIC_RELAXED);
6108                 hns3_err(hw, "Handling interrupts in delayed tasks");
6109                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6110                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6111                 if (reset_level == HNS3_NONE_RESET) {
6112                         hns3_err(hw, "No reset level is set, try IMP reset");
6113                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6114                 }
6115         }
6116         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6117
6118         /*
6119          * Check if there is any ongoing reset in the hardware. This status can
6120          * be checked from reset_pending. If there is then, we need to wait for
6121          * hardware to complete reset.
6122          *    a. If we are able to figure out in reasonable time that hardware
6123          *       has fully resetted then, we can proceed with driver, client
6124          *       reset.
6125          *    b. else, we can come back later to check this status so re-sched
6126          *       now.
6127          */
6128         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6129         if (reset_level != HNS3_NONE_RESET) {
6130                 gettimeofday(&tv_start, NULL);
6131                 ret = hns3_reset_process(hns, reset_level);
6132                 gettimeofday(&tv, NULL);
6133                 timersub(&tv, &tv_start, &tv_delta);
6134                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6135                        tv_delta.tv_usec / USEC_PER_MSEC;
6136                 if (msec > HNS3_RESET_PROCESS_MS)
6137                         hns3_err(hw, "%d handle long time delta %" PRIx64
6138                                      " ms time=%ld.%.6ld",
6139                                  hw->reset.level, msec,
6140                                  tv.tv_sec, tv.tv_usec);
6141                 if (ret == -EAGAIN)
6142                         return;
6143         }
6144
6145         /* Check if we got any *new* reset requests to be honored */
6146         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6147         if (reset_level != HNS3_NONE_RESET)
6148                 hns3_msix_process(hns, reset_level);
6149 }
6150
6151 static unsigned int
6152 hns3_get_speed_capa_num(uint16_t device_id)
6153 {
6154         unsigned int num;
6155
6156         switch (device_id) {
6157         case HNS3_DEV_ID_25GE:
6158         case HNS3_DEV_ID_25GE_RDMA:
6159                 num = 2;
6160                 break;
6161         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6162         case HNS3_DEV_ID_200G_RDMA:
6163                 num = 1;
6164                 break;
6165         default:
6166                 num = 0;
6167                 break;
6168         }
6169
6170         return num;
6171 }
6172
6173 static int
6174 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6175                         uint16_t device_id)
6176 {
6177         switch (device_id) {
6178         case HNS3_DEV_ID_25GE:
6179         /* fallthrough */
6180         case HNS3_DEV_ID_25GE_RDMA:
6181                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6182                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6183
6184                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6185                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6186                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6187                 break;
6188         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6189                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6190                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6191                 break;
6192         case HNS3_DEV_ID_200G_RDMA:
6193                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6194                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6195                 break;
6196         default:
6197                 return -ENOTSUP;
6198         }
6199
6200         return 0;
6201 }
6202
6203 static int
6204 hns3_fec_get_capability(struct rte_eth_dev *dev,
6205                         struct rte_eth_fec_capa *speed_fec_capa,
6206                         unsigned int num)
6207 {
6208         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6209         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6210         uint16_t device_id = pci_dev->id.device_id;
6211         unsigned int capa_num;
6212         int ret;
6213
6214         capa_num = hns3_get_speed_capa_num(device_id);
6215         if (capa_num == 0) {
6216                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6217                          device_id);
6218                 return -ENOTSUP;
6219         }
6220
6221         if (speed_fec_capa == NULL || num < capa_num)
6222                 return capa_num;
6223
6224         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6225         if (ret)
6226                 return -ENOTSUP;
6227
6228         return capa_num;
6229 }
6230
6231 static int
6232 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6233 {
6234         struct hns3_config_fec_cmd *req;
6235         struct hns3_cmd_desc desc;
6236         int ret;
6237
6238         /*
6239          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6240          * in device of link speed
6241          * below 10 Gbps.
6242          */
6243         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6244                 *state = 0;
6245                 return 0;
6246         }
6247
6248         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6249         req = (struct hns3_config_fec_cmd *)desc.data;
6250         ret = hns3_cmd_send(hw, &desc, 1);
6251         if (ret) {
6252                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6253                          ret);
6254                 return ret;
6255         }
6256
6257         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6258         return 0;
6259 }
6260
6261 static int
6262 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6263 {
6264 #define QUERY_ACTIVE_SPEED      1
6265         struct hns3_sfp_speed_cmd *resp;
6266         uint32_t tmp_fec_capa;
6267         uint8_t auto_state;
6268         struct hns3_cmd_desc desc;
6269         int ret;
6270
6271         /*
6272          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6273          * configured FEC mode is returned.
6274          * If link is up, current FEC mode is returned.
6275          */
6276         if (hw->mac.link_status == ETH_LINK_DOWN) {
6277                 ret = get_current_fec_auto_state(hw, &auto_state);
6278                 if (ret)
6279                         return ret;
6280
6281                 if (auto_state == 0x1) {
6282                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6283                         return 0;
6284                 }
6285         }
6286
6287         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6288         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6289         resp->query_type = QUERY_ACTIVE_SPEED;
6290
6291         ret = hns3_cmd_send(hw, &desc, 1);
6292         if (ret == -EOPNOTSUPP) {
6293                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6294                 return ret;
6295         } else if (ret) {
6296                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6297                 return ret;
6298         }
6299
6300         /*
6301          * FEC mode order defined in hns3 hardware is inconsistend with
6302          * that defined in the ethdev library. So the sequence needs
6303          * to be converted.
6304          */
6305         switch (resp->active_fec) {
6306         case HNS3_HW_FEC_MODE_NOFEC:
6307                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6308                 break;
6309         case HNS3_HW_FEC_MODE_BASER:
6310                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6311                 break;
6312         case HNS3_HW_FEC_MODE_RS:
6313                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6314                 break;
6315         default:
6316                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6317                 break;
6318         }
6319
6320         *fec_capa = tmp_fec_capa;
6321         return 0;
6322 }
6323
6324 static int
6325 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6326 {
6327         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6328
6329         return hns3_fec_get_internal(hw, fec_capa);
6330 }
6331
6332 static int
6333 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6334 {
6335         struct hns3_config_fec_cmd *req;
6336         struct hns3_cmd_desc desc;
6337         int ret;
6338
6339         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6340
6341         req = (struct hns3_config_fec_cmd *)desc.data;
6342         switch (mode) {
6343         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6344                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6345                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6346                 break;
6347         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6348                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6349                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6350                 break;
6351         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6352                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6353                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6354                 break;
6355         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6356                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6357                 break;
6358         default:
6359                 return 0;
6360         }
6361         ret = hns3_cmd_send(hw, &desc, 1);
6362         if (ret)
6363                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6364
6365         return ret;
6366 }
6367
6368 static uint32_t
6369 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6370 {
6371         struct hns3_mac *mac = &hw->mac;
6372         uint32_t cur_capa;
6373
6374         switch (mac->link_speed) {
6375         case ETH_SPEED_NUM_10G:
6376                 cur_capa = fec_capa[1].capa;
6377                 break;
6378         case ETH_SPEED_NUM_25G:
6379         case ETH_SPEED_NUM_100G:
6380         case ETH_SPEED_NUM_200G:
6381                 cur_capa = fec_capa[0].capa;
6382                 break;
6383         default:
6384                 cur_capa = 0;
6385                 break;
6386         }
6387
6388         return cur_capa;
6389 }
6390
6391 static bool
6392 is_fec_mode_one_bit_set(uint32_t mode)
6393 {
6394         int cnt = 0;
6395         uint8_t i;
6396
6397         for (i = 0; i < sizeof(mode); i++)
6398                 if (mode >> i & 0x1)
6399                         cnt++;
6400
6401         return cnt == 1 ? true : false;
6402 }
6403
6404 static int
6405 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6406 {
6407 #define FEC_CAPA_NUM 2
6408         struct hns3_adapter *hns = dev->data->dev_private;
6409         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6410         struct hns3_pf *pf = &hns->pf;
6411
6412         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6413         uint32_t cur_capa;
6414         uint32_t num = FEC_CAPA_NUM;
6415         int ret;
6416
6417         ret = hns3_fec_get_capability(dev, fec_capa, num);
6418         if (ret < 0)
6419                 return ret;
6420
6421         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6422         if (!is_fec_mode_one_bit_set(mode))
6423                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6424                              "FEC mode should be only one bit set", mode);
6425
6426         /*
6427          * Check whether the configured mode is within the FEC capability.
6428          * If not, the configured mode will not be supported.
6429          */
6430         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6431         if (!(cur_capa & mode)) {
6432                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6433                 return -EINVAL;
6434         }
6435
6436         rte_spinlock_lock(&hw->lock);
6437         ret = hns3_set_fec_hw(hw, mode);
6438         if (ret) {
6439                 rte_spinlock_unlock(&hw->lock);
6440                 return ret;
6441         }
6442
6443         pf->fec_mode = mode;
6444         rte_spinlock_unlock(&hw->lock);
6445
6446         return 0;
6447 }
6448
6449 static int
6450 hns3_restore_fec(struct hns3_hw *hw)
6451 {
6452         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6453         struct hns3_pf *pf = &hns->pf;
6454         uint32_t mode = pf->fec_mode;
6455         int ret;
6456
6457         ret = hns3_set_fec_hw(hw, mode);
6458         if (ret)
6459                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6460                          mode, ret);
6461
6462         return ret;
6463 }
6464
6465 static int
6466 hns3_query_dev_fec_info(struct hns3_hw *hw)
6467 {
6468         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6469         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6470         int ret;
6471
6472         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6473         if (ret)
6474                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6475
6476         return ret;
6477 }
6478
6479 static bool
6480 hns3_optical_module_existed(struct hns3_hw *hw)
6481 {
6482         struct hns3_cmd_desc desc;
6483         bool existed;
6484         int ret;
6485
6486         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6487         ret = hns3_cmd_send(hw, &desc, 1);
6488         if (ret) {
6489                 hns3_err(hw,
6490                          "fail to get optical module exist state, ret = %d.\n",
6491                          ret);
6492                 return false;
6493         }
6494         existed = !!desc.data[0];
6495
6496         return existed;
6497 }
6498
6499 static int
6500 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6501                                 uint32_t len, uint8_t *data)
6502 {
6503 #define HNS3_SFP_INFO_CMD_NUM 6
6504 #define HNS3_SFP_INFO_MAX_LEN \
6505         (HNS3_SFP_INFO_BD0_LEN + \
6506         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6507         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6508         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6509         uint16_t read_len;
6510         uint16_t copy_len;
6511         int ret;
6512         int i;
6513
6514         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6515                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6516                                           true);
6517                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6518                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6519         }
6520
6521         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6522         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6523         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6524         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6525
6526         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6527         if (ret) {
6528                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6529                                 ret);
6530                 return ret;
6531         }
6532
6533         /* The data format in BD0 is different with the others. */
6534         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6535         memcpy(data, sfp_info_bd0->data, copy_len);
6536         read_len = copy_len;
6537
6538         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6539                 if (read_len >= len)
6540                         break;
6541
6542                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6543                 memcpy(data + read_len, desc[i].data, copy_len);
6544                 read_len += copy_len;
6545         }
6546
6547         return (int)read_len;
6548 }
6549
6550 static int
6551 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6552                        struct rte_dev_eeprom_info *info)
6553 {
6554         struct hns3_adapter *hns = dev->data->dev_private;
6555         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6556         uint32_t offset = info->offset;
6557         uint32_t len = info->length;
6558         uint8_t *data = info->data;
6559         uint32_t read_len = 0;
6560
6561         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6562                 return -ENOTSUP;
6563
6564         if (!hns3_optical_module_existed(hw)) {
6565                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6566                 return -EIO;
6567         }
6568
6569         while (read_len < len) {
6570                 int ret;
6571                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6572                                                   len - read_len,
6573                                                   data + read_len);
6574                 if (ret < 0)
6575                         return -EIO;
6576                 read_len += ret;
6577         }
6578
6579         return 0;
6580 }
6581
6582 static int
6583 hns3_get_module_info(struct rte_eth_dev *dev,
6584                      struct rte_eth_dev_module_info *modinfo)
6585 {
6586 #define HNS3_SFF8024_ID_SFP             0x03
6587 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6588 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6589 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6590 #define HNS3_SFF_8636_V1_3              0x03
6591         struct hns3_adapter *hns = dev->data->dev_private;
6592         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6593         struct rte_dev_eeprom_info info;
6594         struct hns3_sfp_type sfp_type;
6595         int ret;
6596
6597         memset(&sfp_type, 0, sizeof(sfp_type));
6598         memset(&info, 0, sizeof(info));
6599         info.data = (uint8_t *)&sfp_type;
6600         info.length = sizeof(sfp_type);
6601         ret = hns3_get_module_eeprom(dev, &info);
6602         if (ret)
6603                 return ret;
6604
6605         switch (sfp_type.type) {
6606         case HNS3_SFF8024_ID_SFP:
6607                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6608                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6609                 break;
6610         case HNS3_SFF8024_ID_QSFP_8438:
6611                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6612                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6613                 break;
6614         case HNS3_SFF8024_ID_QSFP_8436_8636:
6615                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6616                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6617                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6618                 } else {
6619                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6620                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6621                 }
6622                 break;
6623         case HNS3_SFF8024_ID_QSFP28_8636:
6624                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6625                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6626                 break;
6627         default:
6628                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6629                          sfp_type.type, sfp_type.ext_type);
6630                 return -EINVAL;
6631         }
6632
6633         return 0;
6634 }
6635
6636 static int
6637 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6638 {
6639         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6640
6641         RTE_SET_USED(key);
6642
6643         if (strcmp(value, "vec") == 0)
6644                 hint = HNS3_IO_FUNC_HINT_VEC;
6645         else if (strcmp(value, "sve") == 0)
6646                 hint = HNS3_IO_FUNC_HINT_SVE;
6647         else if (strcmp(value, "simple") == 0)
6648                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6649         else if (strcmp(value, "common") == 0)
6650                 hint = HNS3_IO_FUNC_HINT_COMMON;
6651
6652         /* If the hint is valid then update output parameters */
6653         if (hint != HNS3_IO_FUNC_HINT_NONE)
6654                 *(uint32_t *)extra_args = hint;
6655
6656         return 0;
6657 }
6658
6659 static const char *
6660 hns3_get_io_hint_func_name(uint32_t hint)
6661 {
6662         switch (hint) {
6663         case HNS3_IO_FUNC_HINT_VEC:
6664                 return "vec";
6665         case HNS3_IO_FUNC_HINT_SVE:
6666                 return "sve";
6667         case HNS3_IO_FUNC_HINT_SIMPLE:
6668                 return "simple";
6669         case HNS3_IO_FUNC_HINT_COMMON:
6670                 return "common";
6671         default:
6672                 return "none";
6673         }
6674 }
6675
6676 void
6677 hns3_parse_devargs(struct rte_eth_dev *dev)
6678 {
6679         struct hns3_adapter *hns = dev->data->dev_private;
6680         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6681         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6682         struct hns3_hw *hw = &hns->hw;
6683         struct rte_kvargs *kvlist;
6684
6685         if (dev->device->devargs == NULL)
6686                 return;
6687
6688         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6689         if (!kvlist)
6690                 return;
6691
6692         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6693                            &hns3_parse_io_hint_func, &rx_func_hint);
6694         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6695                            &hns3_parse_io_hint_func, &tx_func_hint);
6696         rte_kvargs_free(kvlist);
6697
6698         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6699                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6700                           hns3_get_io_hint_func_name(rx_func_hint));
6701         hns->rx_func_hint = rx_func_hint;
6702         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6703                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6704                           hns3_get_io_hint_func_name(tx_func_hint));
6705         hns->tx_func_hint = tx_func_hint;
6706 }
6707
6708 static const struct eth_dev_ops hns3_eth_dev_ops = {
6709         .dev_configure      = hns3_dev_configure,
6710         .dev_start          = hns3_dev_start,
6711         .dev_stop           = hns3_dev_stop,
6712         .dev_close          = hns3_dev_close,
6713         .promiscuous_enable = hns3_dev_promiscuous_enable,
6714         .promiscuous_disable = hns3_dev_promiscuous_disable,
6715         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6716         .allmulticast_disable = hns3_dev_allmulticast_disable,
6717         .mtu_set            = hns3_dev_mtu_set,
6718         .stats_get          = hns3_stats_get,
6719         .stats_reset        = hns3_stats_reset,
6720         .xstats_get         = hns3_dev_xstats_get,
6721         .xstats_get_names   = hns3_dev_xstats_get_names,
6722         .xstats_reset       = hns3_dev_xstats_reset,
6723         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6724         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6725         .dev_infos_get          = hns3_dev_infos_get,
6726         .fw_version_get         = hns3_fw_version_get,
6727         .rx_queue_setup         = hns3_rx_queue_setup,
6728         .tx_queue_setup         = hns3_tx_queue_setup,
6729         .rx_queue_release       = hns3_dev_rx_queue_release,
6730         .tx_queue_release       = hns3_dev_tx_queue_release,
6731         .rx_queue_start         = hns3_dev_rx_queue_start,
6732         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6733         .tx_queue_start         = hns3_dev_tx_queue_start,
6734         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6735         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6736         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6737         .rxq_info_get           = hns3_rxq_info_get,
6738         .txq_info_get           = hns3_txq_info_get,
6739         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6740         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6741         .flow_ctrl_get          = hns3_flow_ctrl_get,
6742         .flow_ctrl_set          = hns3_flow_ctrl_set,
6743         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6744         .mac_addr_add           = hns3_add_mac_addr,
6745         .mac_addr_remove        = hns3_remove_mac_addr,
6746         .mac_addr_set           = hns3_set_default_mac_addr,
6747         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6748         .link_update            = hns3_dev_link_update,
6749         .rss_hash_update        = hns3_dev_rss_hash_update,
6750         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6751         .reta_update            = hns3_dev_rss_reta_update,
6752         .reta_query             = hns3_dev_rss_reta_query,
6753         .flow_ops_get           = hns3_dev_flow_ops_get,
6754         .vlan_filter_set        = hns3_vlan_filter_set,
6755         .vlan_tpid_set          = hns3_vlan_tpid_set,
6756         .vlan_offload_set       = hns3_vlan_offload_set,
6757         .vlan_pvid_set          = hns3_vlan_pvid_set,
6758         .get_reg                = hns3_get_regs,
6759         .get_module_info        = hns3_get_module_info,
6760         .get_module_eeprom      = hns3_get_module_eeprom,
6761         .get_dcb_info           = hns3_get_dcb_info,
6762         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6763         .fec_get_capability     = hns3_fec_get_capability,
6764         .fec_get                = hns3_fec_get,
6765         .fec_set                = hns3_fec_set,
6766         .tm_ops_get             = hns3_tm_ops_get,
6767         .tx_done_cleanup        = hns3_tx_done_cleanup,
6768         .timesync_enable            = hns3_timesync_enable,
6769         .timesync_disable           = hns3_timesync_disable,
6770         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6771         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6772         .timesync_adjust_time       = hns3_timesync_adjust_time,
6773         .timesync_read_time         = hns3_timesync_read_time,
6774         .timesync_write_time        = hns3_timesync_write_time,
6775 };
6776
6777 static const struct hns3_reset_ops hns3_reset_ops = {
6778         .reset_service       = hns3_reset_service,
6779         .stop_service        = hns3_stop_service,
6780         .prepare_reset       = hns3_prepare_reset,
6781         .wait_hardware_ready = hns3_wait_hardware_ready,
6782         .reinit_dev          = hns3_reinit_dev,
6783         .restore_conf        = hns3_restore_conf,
6784         .start_service       = hns3_start_service,
6785 };
6786
6787 static int
6788 hns3_dev_init(struct rte_eth_dev *eth_dev)
6789 {
6790         struct hns3_adapter *hns = eth_dev->data->dev_private;
6791         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6792         struct rte_ether_addr *eth_addr;
6793         struct hns3_hw *hw = &hns->hw;
6794         int ret;
6795
6796         PMD_INIT_FUNC_TRACE();
6797
6798         eth_dev->process_private = (struct hns3_process_private *)
6799             rte_zmalloc_socket("hns3_filter_list",
6800                                sizeof(struct hns3_process_private),
6801                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6802         if (eth_dev->process_private == NULL) {
6803                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6804                 return -ENOMEM;
6805         }
6806         /* initialize flow filter lists */
6807         hns3_filterlist_init(eth_dev);
6808
6809         hns3_set_rxtx_function(eth_dev);
6810         eth_dev->dev_ops = &hns3_eth_dev_ops;
6811         eth_dev->rx_queue_count = hns3_rx_queue_count;
6812         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6813                 ret = hns3_mp_init_secondary();
6814                 if (ret) {
6815                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6816                                      "process, ret = %d", ret);
6817                         goto err_mp_init_secondary;
6818                 }
6819
6820                 hw->secondary_cnt++;
6821                 return 0;
6822         }
6823
6824         ret = hns3_mp_init_primary();
6825         if (ret) {
6826                 PMD_INIT_LOG(ERR,
6827                              "Failed to init for primary process, ret = %d",
6828                              ret);
6829                 goto err_mp_init_primary;
6830         }
6831
6832         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6833         hns->is_vf = false;
6834         hw->data = eth_dev->data;
6835         hns3_parse_devargs(eth_dev);
6836
6837         /*
6838          * Set default max packet size according to the mtu
6839          * default vale in DPDK frame.
6840          */
6841         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6842
6843         ret = hns3_reset_init(hw);
6844         if (ret)
6845                 goto err_init_reset;
6846         hw->reset.ops = &hns3_reset_ops;
6847
6848         ret = hns3_init_pf(eth_dev);
6849         if (ret) {
6850                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6851                 goto err_init_pf;
6852         }
6853
6854         /* Allocate memory for storing MAC addresses */
6855         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6856                                                sizeof(struct rte_ether_addr) *
6857                                                HNS3_UC_MACADDR_NUM, 0);
6858         if (eth_dev->data->mac_addrs == NULL) {
6859                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6860                              "to store MAC addresses",
6861                              sizeof(struct rte_ether_addr) *
6862                              HNS3_UC_MACADDR_NUM);
6863                 ret = -ENOMEM;
6864                 goto err_rte_zmalloc;
6865         }
6866
6867         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6868         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6869                 rte_eth_random_addr(hw->mac.mac_addr);
6870                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6871                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6872                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6873                           "unicast address, using random MAC address %s",
6874                           mac_str);
6875         }
6876         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6877                             &eth_dev->data->mac_addrs[0]);
6878
6879         hw->adapter_state = HNS3_NIC_INITIALIZED;
6880
6881         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6882                             SCHEDULE_PENDING) {
6883                 hns3_err(hw, "Reschedule reset service after dev_init");
6884                 hns3_schedule_reset(hns);
6885         } else {
6886                 /* IMP will wait ready flag before reset */
6887                 hns3_notify_reset_ready(hw, false);
6888         }
6889
6890         hns3_info(hw, "hns3 dev initialization successful!");
6891         return 0;
6892
6893 err_rte_zmalloc:
6894         hns3_uninit_pf(eth_dev);
6895
6896 err_init_pf:
6897         rte_free(hw->reset.wait_data);
6898
6899 err_init_reset:
6900         hns3_mp_uninit_primary();
6901
6902 err_mp_init_primary:
6903 err_mp_init_secondary:
6904         eth_dev->dev_ops = NULL;
6905         eth_dev->rx_pkt_burst = NULL;
6906         eth_dev->rx_descriptor_status = NULL;
6907         eth_dev->tx_pkt_burst = NULL;
6908         eth_dev->tx_pkt_prepare = NULL;
6909         eth_dev->tx_descriptor_status = NULL;
6910         rte_free(eth_dev->process_private);
6911         eth_dev->process_private = NULL;
6912         return ret;
6913 }
6914
6915 static int
6916 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6917 {
6918         struct hns3_adapter *hns = eth_dev->data->dev_private;
6919         struct hns3_hw *hw = &hns->hw;
6920
6921         PMD_INIT_FUNC_TRACE();
6922
6923         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6924                 rte_free(eth_dev->process_private);
6925                 eth_dev->process_private = NULL;
6926                 return 0;
6927         }
6928
6929         if (hw->adapter_state < HNS3_NIC_CLOSING)
6930                 hns3_dev_close(eth_dev);
6931
6932         hw->adapter_state = HNS3_NIC_REMOVED;
6933         return 0;
6934 }
6935
6936 static int
6937 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6938                    struct rte_pci_device *pci_dev)
6939 {
6940         return rte_eth_dev_pci_generic_probe(pci_dev,
6941                                              sizeof(struct hns3_adapter),
6942                                              hns3_dev_init);
6943 }
6944
6945 static int
6946 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6947 {
6948         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6949 }
6950
6951 static const struct rte_pci_id pci_id_hns3_map[] = {
6952         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6953         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6954         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6955         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6956         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6957         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6958         { .vendor_id = 0, }, /* sentinel */
6959 };
6960
6961 static struct rte_pci_driver rte_hns3_pmd = {
6962         .id_table = pci_id_hns3_map,
6963         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
6964         .probe = eth_hns3_pci_probe,
6965         .remove = eth_hns3_pci_remove,
6966 };
6967
6968 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6969 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6970 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6971 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6972                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6973                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6974 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6975 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);