drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_pf *pf = &hns->pf;
 312         uint16_t vlan_id;
 313         int ret = 0;
 314
 315         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 316                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 317                                                1);
 318                 return ret;
 319         }
 320
 321         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 322                 if (vlan_entry->hd_tbl_status) {
 323                         vlan_id = vlan_entry->vlan_id;
 324                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 325                         if (ret)
 326                                 break;
 327                 }
 328         }
 329
 330         return ret;
 331 }
 332
 333 static int
 334 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 335 {
 336         struct hns3_pf *pf = &hns->pf;
 337         bool writen_to_tbl = false;
 338         int ret = 0;
 339
 340         /*
 341          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 342          * for normal packet, deleting vlan id 0 is not allowed.
 343          */
 344         if (on == 0 && vlan_id == 0)
 345                 return 0;
 346
 347         /*
 348          * When port base vlan enabled, we use port base vlan as the vlan
 349          * filter condition. In this case, we don't update vlan filter table
 350          * when user add new vlan or remove exist vlan, just update the
 351          * vlan list. The vlan id in vlan list will be writen in vlan filter
 352          * table until port base vlan disabled
 353          */
 354         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 355                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 356                 writen_to_tbl = true;
 357         }
 358
 359         if (ret == 0 && vlan_id) {
 360                 if (on)
 361                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 362                 else
 363                         hns3_rm_dev_vlan_table(hns, vlan_id);
 364         }
 365         return ret;
 366 }
 367
 368 static int
 369 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 370 {
 371         struct hns3_adapter *hns = dev->data->dev_private;
 372         struct hns3_hw *hw = &hns->hw;
 373         int ret;
 374
 375         rte_spinlock_lock(&hw->lock);
 376         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 377         rte_spinlock_unlock(&hw->lock);
 378         return ret;
 379 }
 380
 381 static int
 382 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 383                          uint16_t tpid)
 384 {
 385         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 386         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 387         struct hns3_hw *hw = &hns->hw;
 388         struct hns3_cmd_desc desc;
 389         int ret;
 390
 391         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 392              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 393                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 394                 return -EINVAL;
 395         }
 396
 397         if (tpid != RTE_ETHER_TYPE_VLAN) {
 398                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 399                 return -EINVAL;
 400         }
 401
 402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 403         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 404
 405         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 406                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 407                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 408         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 412                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 413         }
 414
 415         ret = hns3_cmd_send(hw, &desc, 1);
 416         if (ret) {
 417                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 418                          ret);
 419                 return ret;
 420         }
 421
 422         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 423
 424         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 425         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 426         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 427
 428         ret = hns3_cmd_send(hw, &desc, 1);
 429         if (ret)
 430                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 431                          ret);
 432         return ret;
 433 }
 434
 435 static int
 436 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 437                    uint16_t tpid)
 438 {
 439         struct hns3_adapter *hns = dev->data->dev_private;
 440         struct hns3_hw *hw = &hns->hw;
 441         int ret;
 442
 443         rte_spinlock_lock(&hw->lock);
 444         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 445         rte_spinlock_unlock(&hw->lock);
 446         return ret;
 447 }
 448
 449 static int
 450 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 451                              struct hns3_rx_vtag_cfg *vcfg)
 452 {
 453         struct hns3_vport_vtag_rx_cfg_cmd *req;
 454         struct hns3_hw *hw = &hns->hw;
 455         struct hns3_cmd_desc desc;
 456         uint16_t vport_id;
 457         uint8_t bitmap;
 458         int ret;
 459
 460         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 461
 462         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 464                      vcfg->strip_tag1_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 466                      vcfg->strip_tag2_en ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 468                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 469         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 470                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 471
 472         /*
 473          * In current version VF is not supported when PF is driven by DPDK
 474          * driver, the PF-related vf_id is 0, just need to configure parameters
 475          * for vport_id 0.
 476          */
 477         vport_id = 0;
 478         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 479         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 480         req->vf_bitmap[req->vf_offset] = bitmap;
 481
 482         ret = hns3_cmd_send(hw, &desc, 1);
 483         if (ret)
 484                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 485         return ret;
 486 }
 487
 488 static void
 489 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 490                            struct hns3_rx_vtag_cfg *vcfg)
 491 {
 492         struct hns3_pf *pf = &hns->pf;
 493         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 494 }
 495
 496 static void
 497 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 498                            struct hns3_tx_vtag_cfg *vcfg)
 499 {
 500         struct hns3_pf *pf = &hns->pf;
 501         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 502 }
 503
 504 static int
 505 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 506 {
 507         struct hns3_rx_vtag_cfg rxvlan_cfg;
 508         struct hns3_pf *pf = &hns->pf;
 509         struct hns3_hw *hw = &hns->hw;
 510         int ret;
 511
 512         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 513                 rxvlan_cfg.strip_tag1_en = false;
 514                 rxvlan_cfg.strip_tag2_en = enable;
 515         } else {
 516                 rxvlan_cfg.strip_tag1_en = enable;
 517                 rxvlan_cfg.strip_tag2_en = true;
 518         }
 519
 520         rxvlan_cfg.vlan1_vlan_prionly = false;
 521         rxvlan_cfg.vlan2_vlan_prionly = false;
 522         rxvlan_cfg.rx_vlan_offload_en = enable;
 523
 524         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 525         if (ret) {
 526                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 527                 return ret;
 528         }
 529
 530         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 531
 532         return ret;
 533 }
 534
 535 static int
 536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 537                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 538 {
 539         struct hns3_vlan_filter_ctrl_cmd *req;
 540         struct hns3_cmd_desc desc;
 541         int ret;
 542
 543         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 544
 545         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 546         req->vlan_type = vlan_type;
 547         req->vlan_fe = filter_en ? fe_type : 0;
 548         req->vf_id = vf_id;
 549
 550         ret = hns3_cmd_send(hw, &desc, 1);
 551         if (ret)
 552                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 553
 554         return ret;
 555 }
 556
 557 static int
 558 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 559 {
 560         struct hns3_hw *hw = &hns->hw;
 561         int ret;
 562
 563         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 564                                         HNS3_FILTER_FE_EGRESS, false, 0);
 565         if (ret) {
 566                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 567                 return ret;
 568         }
 569
 570         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 571                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 572         if (ret)
 573                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 574
 575         return ret;
 576 }
 577
 578 static int
 579 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 580 {
 581         struct hns3_adapter *hns = dev->data->dev_private;
 582         struct hns3_hw *hw = &hns->hw;
 583         struct rte_eth_rxmode *rxmode;
 584         unsigned int tmp_mask;
 585         bool enable;
 586         int ret = 0;
 587
 588         rte_spinlock_lock(&hw->lock);
 589         rxmode = &dev->data->dev_conf.rxmode;
 590         tmp_mask = (unsigned int)mask;
 591         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 592                 /* Enable or disable VLAN stripping */
 593                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 594                     true : false;
 595
 596                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 597                 if (ret) {
 598                         rte_spinlock_unlock(&hw->lock);
 599                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 600                         return ret;
 601                 }
 602         }
 603
 604         rte_spinlock_unlock(&hw->lock);
 605
 606         return ret;
 607 }
 608
 609 static int
 610 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 611                              struct hns3_tx_vtag_cfg *vcfg)
 612 {
 613         struct hns3_vport_vtag_tx_cfg_cmd *req;
 614         struct hns3_cmd_desc desc;
 615         struct hns3_hw *hw = &hns->hw;
 616         uint16_t vport_id;
 617         uint8_t bitmap;
 618         int ret;
 619
 620         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 621
 622         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 623         req->def_vlan_tag1 = vcfg->default_tag1;
 624         req->def_vlan_tag2 = vcfg->default_tag2;
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 626                      vcfg->accept_tag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 628                      vcfg->accept_untag1 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 630                      vcfg->accept_tag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 632                      vcfg->accept_untag2 ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 634                      vcfg->insert_tag1_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 636                      vcfg->insert_tag2_en ? 1 : 0);
 637         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 638
 639         /*
 640          * In current version VF is not supported when PF is driven by DPDK
 641          * driver, the PF-related vf_id is 0, just need to configure parameters
 642          * for vport_id 0.
 643          */
 644         vport_id = 0;
 645         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 646         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 647         req->vf_bitmap[req->vf_offset] = bitmap;
 648
 649         ret = hns3_cmd_send(hw, &desc, 1);
 650         if (ret)
 651                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 658                      uint16_t pvid)
 659 {
 660         struct hns3_hw *hw = &hns->hw;
 661         struct hns3_tx_vtag_cfg txvlan_cfg;
 662         int ret;
 663
 664         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 665                 txvlan_cfg.accept_tag1 = true;
 666                 txvlan_cfg.insert_tag1_en = false;
 667                 txvlan_cfg.default_tag1 = 0;
 668         } else {
 669                 txvlan_cfg.accept_tag1 = false;
 670                 txvlan_cfg.insert_tag1_en = true;
 671                 txvlan_cfg.default_tag1 = pvid;
 672         }
 673
 674         txvlan_cfg.accept_untag1 = true;
 675         txvlan_cfg.accept_tag2 = true;
 676         txvlan_cfg.accept_untag2 = true;
 677         txvlan_cfg.insert_tag2_en = false;
 678         txvlan_cfg.default_tag2 = 0;
 679
 680         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 681         if (ret) {
 682                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 683                          ret);
 684                 return ret;
 685         }
 686
 687         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 688         return ret;
 689 }
 690
 691 static void
 692 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 693 {
 694         struct hns3_pf *pf = &hns->pf;
 695
 696         pf->port_base_vlan_cfg.state = on ?
 697             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 698
 699         pf->port_base_vlan_cfg.pvid = pvid;
 700 }
 701
 702 static void
 703 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 704 {
 705         struct hns3_user_vlan_table *vlan_entry;
 706         struct hns3_pf *pf = &hns->pf;
 707
 708         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 709                 if (vlan_entry->hd_tbl_status)
 710                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 711
 712                 vlan_entry->hd_tbl_status = false;
 713         }
 714
 715         if (is_del_list) {
 716                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 717                 while (vlan_entry) {
 718                         LIST_REMOVE(vlan_entry, next);
 719                         rte_free(vlan_entry);
 720                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 721                 }
 722         }
 723 }
 724
 725 static void
 726 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 727 {
 728         struct hns3_user_vlan_table *vlan_entry;
 729         struct hns3_pf *pf = &hns->pf;
 730
 731         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 732                 if (!vlan_entry->hd_tbl_status)
 733                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 734
 735                 vlan_entry->hd_tbl_status = true;
 736         }
 737 }
 738
 739 static void
 740 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 741 {
 742         struct hns3_hw *hw = &hns->hw;
 743         struct hns3_pf *pf = &hns->pf;
 744         int ret;
 745
 746         hns3_rm_all_vlan_table(hns, true);
 747         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 748                 ret = hns3_set_port_vlan_filter(hns,
 749                                                 pf->port_base_vlan_cfg.pvid, 0);
 750                 if (ret) {
 751                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 752                                  ret);
 753                         return;
 754                 }
 755         }
 756 }
 757
 758 static int
 759 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 760                                 uint16_t port_base_vlan_state,
 761                                 uint16_t new_pvid, uint16_t old_pvid)
 762 {
 763         struct hns3_pf *pf = &hns->pf;
 764         struct hns3_hw *hw = &hns->hw;
 765         int ret = 0;
 766
 767         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 768                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 769                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 770                         if (ret) {
 771                                 hns3_err(hw,
 772                                          "Failed to clear clear old pvid filter, ret =%d",
 773                                          ret);
 774                                 return ret;
 775                         }
 776                 }
 777
 778                 hns3_rm_all_vlan_table(hns, false);
 779                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 780         }
 781
 782         if (new_pvid != 0) {
 783                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 784                 if (ret) {
 785                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 786                                  ret);
 787                         return ret;
 788                 }
 789         }
 790
 791         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 792                 hns3_add_all_vlan_table(hns);
 793
 794         return ret;
 795 }
 796
 797 static int
 798 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 799 {
 800         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 801         struct hns3_hw *hw = &hns->hw;
 802         bool rx_strip_en;
 803         int ret;
 804
 805         rx_strip_en = on ? true : false;
 806         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 807         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 808         rx_vlan_cfg.vlan1_vlan_prionly = false;
 809         rx_vlan_cfg.vlan2_vlan_prionly = false;
 810         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 811
 812         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 813         if (ret) {
 814                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 815                 return ret;
 816         }
 817
 818         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 819         return ret;
 820 }
 821
 822 static int
 823 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 824 {
 825         struct hns3_pf *pf = &hns->pf;
 826         struct hns3_hw *hw = &hns->hw;
 827         uint16_t port_base_vlan_state;
 828         uint16_t old_pvid;
 829         int ret;
 830
 831         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 832                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 833                         hns3_warn(hw, "Invalid operation! As current pvid set "
 834                                   "is %u, disable pvid %u is invalid",
 835                                   pf->port_base_vlan_cfg.pvid, pvid);
 836                 return 0;
 837         }
 838
 839         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 840                                     HNS3_PORT_BASE_VLAN_DISABLE;
 841         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 842         if (ret) {
 843                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 844                 return ret;
 845         }
 846
 847         ret = hns3_en_rx_strip_all(hns, on);
 848         if (ret) {
 849                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 850                 return ret;
 851         }
 852
 853         if (pvid == HNS3_INVLID_PVID)
 854                 goto out;
 855         old_pvid = pf->port_base_vlan_cfg.pvid;
 856         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 857                                               old_pvid);
 858         if (ret) {
 859                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 860                          ret);
 861                 return ret;
 862         }
 863
 864 out:
 865         hns3_store_port_base_vlan_info(hns, pvid, on);
 866         return ret;
 867 }
 868
 869 static int
 870 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 871 {
 872         struct hns3_adapter *hns = dev->data->dev_private;
 873         struct hns3_hw *hw = &hns->hw;
 874         int ret;
 875
 876         rte_spinlock_lock(&hw->lock);
 877         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 878         rte_spinlock_unlock(&hw->lock);
 879         return ret;
 880 }
 881
 882 static void
 883 init_port_base_vlan_info(struct hns3_hw *hw)
 884 {
 885         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 886         struct hns3_pf *pf = &hns->pf;
 887
 888         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 889         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 890 }
 891
 892 static int
 893 hns3_default_vlan_config(struct hns3_adapter *hns)
 894 {
 895         struct hns3_hw *hw = &hns->hw;
 896         int ret;
 897
 898         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 899         if (ret)
 900                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 901         return ret;
 902 }
 903
 904 static int
 905 hns3_init_vlan_config(struct hns3_adapter *hns)
 906 {
 907         struct hns3_hw *hw = &hns->hw;
 908         int ret;
 909
 910         /*
 911          * This function can be called in the initialization and reset process,
 912          * when in reset process, it means that hardware had been reseted
 913          * successfully and we need to restore the hardware configuration to
 914          * ensure that the hardware configuration remains unchanged before and
 915          * after reset.
 916          */
 917         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 918                 init_port_base_vlan_info(hw);
 919
 920         ret = hns3_enable_vlan_filter(hns, true);
 921         if (ret) {
 922                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 923                 return ret;
 924         }
 925
 926         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 927                                        RTE_ETHER_TYPE_VLAN);
 928         if (ret) {
 929                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 930                 return ret;
 931         }
 932
 933         /*
 934          * When in the reinit dev stage of the reset process, the following
 935          * vlan-related configurations may differ from those at initialization,
 936          * we will restore configurations to hardware in hns3_restore_vlan_table
 937          * and hns3_restore_vlan_conf later.
 938          */
 939         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 940                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 941                 if (ret) {
 942                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 943                         return ret;
 944                 }
 945
 946                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 947                 if (ret) {
 948                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 949                                  ret);
 950                         return ret;
 951                 }
 952         }
 953
 954         return hns3_default_vlan_config(hns);
 955 }
 956
 957 static int
 958 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 959 {
 960         struct hns3_pf *pf = &hns->pf;
 961         struct hns3_hw *hw = &hns->hw;
 962         int ret;
 963
 964         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 965         if (ret) {
 966                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 967                 return ret;
 968         }
 969
 970         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 971         if (ret)
 972                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 973
 974         return ret;
 975 }
 976
 977 static int
 978 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 979 {
 980         struct hns3_adapter *hns = dev->data->dev_private;
 981         struct rte_eth_dev_data *data = dev->data;
 982         struct rte_eth_txmode *txmode;
 983         struct hns3_hw *hw = &hns->hw;
 984         int ret;
 985
 986         txmode = &data->dev_conf.txmode;
 987         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 988                 hns3_warn(hw,
 989                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 990                           "configuration is not supported! Ignore these two "
 991                           "parameters: hw_vlan_reject_tagged(%d), "
 992                           "hw_vlan_reject_untagged(%d)",
 993                           txmode->hw_vlan_reject_tagged,
 994                           txmode->hw_vlan_reject_untagged);
 995
 996         /* Apply vlan offload setting */
 997         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 998         if (ret) {
 999                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
1000                 return ret;
1001         }
1002
1003         /* Apply pvid setting */
1004         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1005                                  txmode->hw_vlan_insert_pvid);
1006         if (ret)
1007                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1008                          txmode->pvid, ret);
1009
1010         return ret;
1011 }
1012
1013 static int
1014 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1015                 unsigned int tso_mss_max)
1016 {
1017         struct hns3_cfg_tso_status_cmd *req;
1018         struct hns3_cmd_desc desc;
1019         uint16_t tso_mss;
1020
1021         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1022
1023         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1024
1025         tso_mss = 0;
1026         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1027                        tso_mss_min);
1028         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1029
1030         tso_mss = 0;
1031         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1032                        tso_mss_max);
1033         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1034
1035         return hns3_cmd_send(hw, &desc, 1);
1036 }
1037
1038 int
1039 hns3_config_gro(struct hns3_hw *hw, bool en)
1040 {
1041         struct hns3_cfg_gro_status_cmd *req;
1042         struct hns3_cmd_desc desc;
1043         int ret;
1044
1045         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1046         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1047
1048         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1049
1050         ret = hns3_cmd_send(hw, &desc, 1);
1051         if (ret)
1052                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1053
1054         return ret;
1055 }
1056
1057 static int
1058 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1059                    uint16_t *allocated_size, bool is_alloc)
1060 {
1061         struct hns3_umv_spc_alc_cmd *req;
1062         struct hns3_cmd_desc desc;
1063         int ret;
1064
1065         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1066         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1067         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1068         req->space_size = rte_cpu_to_le_32(space_size);
1069
1070         ret = hns3_cmd_send(hw, &desc, 1);
1071         if (ret) {
1072                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1073                              is_alloc ? "allocate" : "free", ret);
1074                 return ret;
1075         }
1076
1077         if (is_alloc && allocated_size)
1078                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1079
1080         return 0;
1081 }
1082
1083 static int
1084 hns3_init_umv_space(struct hns3_hw *hw)
1085 {
1086         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1087         struct hns3_pf *pf = &hns->pf;
1088         uint16_t allocated_size = 0;
1089         int ret;
1090
1091         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1092                                  true);
1093         if (ret)
1094                 return ret;
1095
1096         if (allocated_size < pf->wanted_umv_size)
1097                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1098                              pf->wanted_umv_size, allocated_size);
1099
1100         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1101                                                 pf->wanted_umv_size;
1102         pf->used_umv_size = 0;
1103         return 0;
1104 }
1105
1106 static int
1107 hns3_uninit_umv_space(struct hns3_hw *hw)
1108 {
1109         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1110         struct hns3_pf *pf = &hns->pf;
1111         int ret;
1112
1113         if (pf->max_umv_size == 0)
1114                 return 0;
1115
1116         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1117         if (ret)
1118                 return ret;
1119
1120         pf->max_umv_size = 0;
1121
1122         return 0;
1123 }
1124
1125 static bool
1126 hns3_is_umv_space_full(struct hns3_hw *hw)
1127 {
1128         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1129         struct hns3_pf *pf = &hns->pf;
1130         bool is_full;
1131
1132         is_full = (pf->used_umv_size >= pf->max_umv_size);
1133
1134         return is_full;
1135 }
1136
1137 static void
1138 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1139 {
1140         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1141         struct hns3_pf *pf = &hns->pf;
1142
1143         if (is_free) {
1144                 if (pf->used_umv_size > 0)
1145                         pf->used_umv_size--;
1146         } else
1147                 pf->used_umv_size++;
1148 }
1149
1150 static void
1151 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1152                       const uint8_t *addr, bool is_mc)
1153 {
1154         const unsigned char *mac_addr = addr;
1155         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1156                             ((uint32_t)mac_addr[2] << 16) |
1157                             ((uint32_t)mac_addr[1] << 8) |
1158                             (uint32_t)mac_addr[0];
1159         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1160
1161         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1162         if (is_mc) {
1163                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1164                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1165                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1166         }
1167
1168         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1169         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1170 }
1171
1172 static int
1173 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1174                              uint8_t resp_code,
1175                              enum hns3_mac_vlan_tbl_opcode op)
1176 {
1177         if (cmdq_resp) {
1178                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1179                          cmdq_resp);
1180                 return -EIO;
1181         }
1182
1183         if (op == HNS3_MAC_VLAN_ADD) {
1184                 if (resp_code == 0 || resp_code == 1) {
1185                         return 0;
1186                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1187                         hns3_err(hw, "add mac addr failed for uc_overflow");
1188                         return -ENOSPC;
1189                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1190                         hns3_err(hw, "add mac addr failed for mc_overflow");
1191                         return -ENOSPC;
1192                 }
1193
1194                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1195                          resp_code);
1196                 return -EIO;
1197         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1198                 if (resp_code == 0) {
1199                         return 0;
1200                 } else if (resp_code == 1) {
1201                         hns3_dbg(hw, "remove mac addr failed for miss");
1202                         return -ENOENT;
1203                 }
1204
1205                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1206                          resp_code);
1207                 return -EIO;
1208         } else if (op == HNS3_MAC_VLAN_LKUP) {
1209                 if (resp_code == 0) {
1210                         return 0;
1211                 } else if (resp_code == 1) {
1212                         hns3_dbg(hw, "lookup mac addr failed for miss");
1213                         return -ENOENT;
1214                 }
1215
1216                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1217                          resp_code);
1218                 return -EIO;
1219         }
1220
1221         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1222                  op);
1223
1224         return -EINVAL;
1225 }
1226
1227 static int
1228 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1229                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1230                          struct hns3_cmd_desc *desc, bool is_mc)
1231 {
1232         uint8_t resp_code;
1233         uint16_t retval;
1234         int ret;
1235
1236         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1237         if (is_mc) {
1238                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1239                 memcpy(desc[0].data, req,
1240                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1241                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1242                                           true);
1243                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1244                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1245                                           true);
1246                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1247         } else {
1248                 memcpy(desc[0].data, req,
1249                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1250                 ret = hns3_cmd_send(hw, desc, 1);
1251         }
1252         if (ret) {
1253                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1254                          ret);
1255                 return ret;
1256         }
1257         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1258         retval = rte_le_to_cpu_16(desc[0].retval);
1259
1260         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1261                                             HNS3_MAC_VLAN_LKUP);
1262 }
1263
1264 static int
1265 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1266                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1267                       struct hns3_cmd_desc *mc_desc)
1268 {
1269         uint8_t resp_code;
1270         uint16_t retval;
1271         int cfg_status;
1272         int ret;
1273
1274         if (mc_desc == NULL) {
1275                 struct hns3_cmd_desc desc;
1276
1277                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1278                 memcpy(desc.data, req,
1279                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1280                 ret = hns3_cmd_send(hw, &desc, 1);
1281                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1282                 retval = rte_le_to_cpu_16(desc.retval);
1283
1284                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1285                                                           HNS3_MAC_VLAN_ADD);
1286         } else {
1287                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1288                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1290                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1291                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1292                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1293                 memcpy(mc_desc[0].data, req,
1294                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1295                 mc_desc[0].retval = 0;
1296                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1297                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1298                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1299
1300                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1301                                                           HNS3_MAC_VLAN_ADD);
1302         }
1303
1304         if (ret) {
1305                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1306                 return ret;
1307         }
1308
1309         return cfg_status;
1310 }
1311
1312 static int
1313 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1314                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1315 {
1316         struct hns3_cmd_desc desc;
1317         uint8_t resp_code;
1318         uint16_t retval;
1319         int ret;
1320
1321         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1322
1323         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1324
1325         ret = hns3_cmd_send(hw, &desc, 1);
1326         if (ret) {
1327                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1328                 return ret;
1329         }
1330         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1331         retval = rte_le_to_cpu_16(desc.retval);
1332
1333         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1334                                             HNS3_MAC_VLAN_REMOVE);
1335 }
1336
1337 static int
1338 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1339 {
1340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341         struct hns3_mac_vlan_tbl_entry_cmd req;
1342         struct hns3_pf *pf = &hns->pf;
1343         struct hns3_cmd_desc desc;
1344         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1345         uint16_t egress_port = 0;
1346         uint8_t vf_id;
1347         int ret;
1348
1349         /* check if mac addr is valid */
1350         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1351                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1352                                       mac_addr);
1353                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1354                          mac_str);
1355                 return -EINVAL;
1356         }
1357
1358         memset(&req, 0, sizeof(req));
1359
1360         /*
1361          * In current version VF is not supported when PF is driven by DPDK
1362          * driver, the PF-related vf_id is 0, just need to configure parameters
1363          * for vf_id 0.
1364          */
1365         vf_id = 0;
1366         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1367                        HNS3_MAC_EPORT_VFID_S, vf_id);
1368
1369         req.egress_port = rte_cpu_to_le_16(egress_port);
1370
1371         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1372
1373         /*
1374          * Lookup the mac address in the mac_vlan table, and add
1375          * it if the entry is inexistent. Repeated unicast entry
1376          * is not allowed in the mac vlan table.
1377          */
1378         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1379         if (ret == -ENOENT) {
1380                 if (!hns3_is_umv_space_full(hw)) {
1381                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1382                         if (!ret)
1383                                 hns3_update_umv_space(hw, false);
1384                         return ret;
1385                 }
1386
1387                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1388
1389                 return -ENOSPC;
1390         }
1391
1392         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1393
1394         /* check if we just hit the duplicate */
1395         if (ret == 0) {
1396                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1397                 return 0;
1398         }
1399
1400         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1401                  mac_str);
1402
1403         return ret;
1404 }
1405
1406 static int
1407 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1408                   uint32_t idx, __rte_unused uint32_t pool)
1409 {
1410         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1412         int ret;
1413
1414         rte_spinlock_lock(&hw->lock);
1415         ret = hns3_add_uc_addr_common(hw, mac_addr);
1416         if (ret) {
1417                 rte_spinlock_unlock(&hw->lock);
1418                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1419                                       mac_addr);
1420                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1421                 return ret;
1422         }
1423
1424         if (idx == 0)
1425                 hw->mac.default_addr_setted = true;
1426         rte_spinlock_unlock(&hw->lock);
1427
1428         return ret;
1429 }
1430
1431 static int
1432 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1433 {
1434         struct hns3_mac_vlan_tbl_entry_cmd req;
1435         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1436         int ret;
1437
1438         /* check if mac addr is valid */
1439         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1440                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1441                                       mac_addr);
1442                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1443                          mac_str);
1444                 return -EINVAL;
1445         }
1446
1447         memset(&req, 0, sizeof(req));
1448         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1449         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1450         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1451         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1452                 return 0;
1453         else if (ret == 0)
1454                 hns3_update_umv_space(hw, true);
1455
1456         return ret;
1457 }
1458
1459 static void
1460 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1461 {
1462         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1463         /* index will be checked by upper level rte interface */
1464         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1465         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1466         int ret;
1467
1468         rte_spinlock_lock(&hw->lock);
1469         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1470         if (ret) {
1471                 rte_spinlock_unlock(&hw->lock);
1472                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1473                                       mac_addr);
1474                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1475                 return;
1476         }
1477
1478         rte_spinlock_unlock(&hw->lock);
1479 }
1480
1481 static int
1482 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1483                           struct rte_ether_addr *mac_addr)
1484 {
1485         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1486         struct rte_ether_addr *oaddr;
1487         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1488         bool default_addr_setted;
1489         bool rm_succes = false;
1490         int ret, ret_val;
1491
1492         /*
1493          * It has been guaranteed that input parameter named mac_addr is valid
1494          * address in the rte layer of DPDK framework.
1495          */
1496         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1497         default_addr_setted = hw->mac.default_addr_setted;
1498         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1499                 return 0;
1500
1501         rte_spinlock_lock(&hw->lock);
1502         if (default_addr_setted) {
1503                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1504                 if (ret) {
1505                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1506                                               oaddr);
1507                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1508                                   mac_str, ret);
1509                         rm_succes = false;
1510                 } else
1511                         rm_succes = true;
1512         }
1513
1514         ret = hns3_add_uc_addr_common(hw, mac_addr);
1515         if (ret) {
1516                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1517                                       mac_addr);
1518                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1519                 goto err_add_uc_addr;
1520         }
1521
1522         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1523         if (ret) {
1524                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1525                 goto err_pause_addr_cfg;
1526         }
1527
1528         rte_ether_addr_copy(mac_addr,
1529                             (struct rte_ether_addr *)hw->mac.mac_addr);
1530         hw->mac.default_addr_setted = true;
1531         rte_spinlock_unlock(&hw->lock);
1532
1533         return 0;
1534
1535 err_pause_addr_cfg:
1536         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1537         if (ret_val) {
1538                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1539                                       mac_addr);
1540                 hns3_warn(hw,
1541                           "Failed to roll back to del setted mac addr(%s): %d",
1542                           mac_str, ret_val);
1543         }
1544
1545 err_add_uc_addr:
1546         if (rm_succes) {
1547                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1548                 if (ret_val) {
1549                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                               oaddr);
1551                         hns3_warn(hw,
1552                                   "Failed to restore old uc mac addr(%s): %d",
1553                                   mac_str, ret_val);
1554                         hw->mac.default_addr_setted = false;
1555                 }
1556         }
1557         rte_spinlock_unlock(&hw->lock);
1558
1559         return ret;
1560 }
1561
1562 static int
1563 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1564 {
1565         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1566         struct hns3_hw *hw = &hns->hw;
1567         struct rte_ether_addr *addr;
1568         int err = 0;
1569         int ret;
1570         int i;
1571
1572         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1573                 addr = &hw->data->mac_addrs[i];
1574                 if (!rte_is_valid_assigned_ether_addr(addr))
1575                         continue;
1576                 if (del)
1577                         ret = hns3_remove_uc_addr_common(hw, addr);
1578                 else
1579                         ret = hns3_add_uc_addr_common(hw, addr);
1580                 if (ret) {
1581                         err = ret;
1582                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1583                                               addr);
1584                         hns3_dbg(hw,
1585                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1586                                  del ? "remove" : "restore", mac_str, ret, i);
1587                 }
1588         }
1589         return err;
1590 }
1591
1592 static void
1593 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1594 {
1595 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1596         uint8_t word_num;
1597         uint8_t bit_num;
1598
1599         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1600                 word_num = vfid / 32;
1601                 bit_num = vfid % 32;
1602                 if (clr)
1603                         desc[1].data[word_num] &=
1604                             rte_cpu_to_le_32(~(1UL << bit_num));
1605                 else
1606                         desc[1].data[word_num] |=
1607                             rte_cpu_to_le_32(1UL << bit_num);
1608         } else {
1609                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1610                 bit_num = vfid % 32;
1611                 if (clr)
1612                         desc[2].data[word_num] &=
1613                             rte_cpu_to_le_32(~(1UL << bit_num));
1614                 else
1615                         desc[2].data[word_num] |=
1616                             rte_cpu_to_le_32(1UL << bit_num);
1617         }
1618 }
1619
1620 static int
1621 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1622 {
1623         struct hns3_mac_vlan_tbl_entry_cmd req;
1624         struct hns3_cmd_desc desc[3];
1625         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1626         uint8_t vf_id;
1627         int ret;
1628
1629         /* Check if mac addr is valid */
1630         if (!rte_is_multicast_ether_addr(mac_addr)) {
1631                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1632                                       mac_addr);
1633                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1634                          mac_str);
1635                 return -EINVAL;
1636         }
1637
1638         memset(&req, 0, sizeof(req));
1639         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1640         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1641         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1642         if (ret) {
1643                 /* This mac addr do not exist, add new entry for it */
1644                 memset(desc[0].data, 0, sizeof(desc[0].data));
1645                 memset(desc[1].data, 0, sizeof(desc[0].data));
1646                 memset(desc[2].data, 0, sizeof(desc[0].data));
1647         }
1648
1649         /*
1650          * In current version VF is not supported when PF is driven by DPDK
1651          * driver, the PF-related vf_id is 0, just need to configure parameters
1652          * for vf_id 0.
1653          */
1654         vf_id = 0;
1655         hns3_update_desc_vfid(desc, vf_id, false);
1656         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1657         if (ret) {
1658                 if (ret == -ENOSPC)
1659                         hns3_err(hw, "mc mac vlan table is full");
1660                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1661                                       mac_addr);
1662                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1663         }
1664
1665         return ret;
1666 }
1667
1668 static int
1669 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1670 {
1671         struct hns3_mac_vlan_tbl_entry_cmd req;
1672         struct hns3_cmd_desc desc[3];
1673         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1674         uint8_t vf_id;
1675         int ret;
1676
1677         /* Check if mac addr is valid */
1678         if (!rte_is_multicast_ether_addr(mac_addr)) {
1679                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                       mac_addr);
1681                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1682                          mac_str);
1683                 return -EINVAL;
1684         }
1685
1686         memset(&req, 0, sizeof(req));
1687         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1688         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1689         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1690         if (ret == 0) {
1691                 /*
1692                  * This mac addr exist, remove this handle's VFID for it.
1693                  * In current version VF is not supported when PF is driven by
1694                  * DPDK driver, the PF-related vf_id is 0, just need to
1695                  * configure parameters for vf_id 0.
1696                  */
1697                 vf_id = 0;
1698                 hns3_update_desc_vfid(desc, vf_id, true);
1699
1700                 /* All the vfid is zero, so need to delete this entry */
1701                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1702         } else if (ret == -ENOENT) {
1703                 /* This mac addr doesn't exist. */
1704                 return 0;
1705         }
1706
1707         if (ret) {
1708                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1709                                       mac_addr);
1710                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1711         }
1712
1713         return ret;
1714 }
1715
1716 static int
1717 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1718                            struct rte_ether_addr *mc_addr_set,
1719                            uint32_t nb_mc_addr)
1720 {
1721         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1722         struct rte_ether_addr *addr;
1723         uint32_t i;
1724         uint32_t j;
1725
1726         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1727                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1728                          "invalid. valid range: 0~%d",
1729                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1730                 return -EINVAL;
1731         }
1732
1733         /* Check if input mac addresses are valid */
1734         for (i = 0; i < nb_mc_addr; i++) {
1735                 addr = &mc_addr_set[i];
1736                 if (!rte_is_multicast_ether_addr(addr)) {
1737                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1738                                               addr);
1739                         hns3_err(hw,
1740                                  "Failed to set mc mac addr, addr(%s) invalid.",
1741                                  mac_str);
1742                         return -EINVAL;
1743                 }
1744
1745                 /* Check if there are duplicate addresses */
1746                 for (j = i + 1; j < nb_mc_addr; j++) {
1747                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1748                                 rte_ether_format_addr(mac_str,
1749                                                       RTE_ETHER_ADDR_FMT_SIZE,
1750                                                       addr);
1751                                 hns3_err(hw, "Failed to set mc mac addr, "
1752                                          "addrs invalid. two same addrs(%s).",
1753                                          mac_str);
1754                                 return -EINVAL;
1755                         }
1756                 }
1757         }
1758
1759         return 0;
1760 }
1761
1762 static void
1763 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1764                            struct rte_ether_addr *mc_addr_set,
1765                            int mc_addr_num,
1766                            struct rte_ether_addr *reserved_addr_list,
1767                            int *reserved_addr_num,
1768                            struct rte_ether_addr *add_addr_list,
1769                            int *add_addr_num,
1770                            struct rte_ether_addr *rm_addr_list,
1771                            int *rm_addr_num)
1772 {
1773         struct rte_ether_addr *addr;
1774         int current_addr_num;
1775         int reserved_num = 0;
1776         int add_num = 0;
1777         int rm_num = 0;
1778         int num;
1779         int i;
1780         int j;
1781         bool same_addr;
1782
1783         /* Calculate the mc mac address list that should be removed */
1784         current_addr_num = hw->mc_addrs_num;
1785         for (i = 0; i < current_addr_num; i++) {
1786                 addr = &hw->mc_addrs[i];
1787                 same_addr = false;
1788                 for (j = 0; j < mc_addr_num; j++) {
1789                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1790                                 same_addr = true;
1791                                 break;
1792                         }
1793                 }
1794
1795                 if (!same_addr) {
1796                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1797                         rm_num++;
1798                 } else {
1799                         rte_ether_addr_copy(addr,
1800                                             &reserved_addr_list[reserved_num]);
1801                         reserved_num++;
1802                 }
1803         }
1804
1805         /* Calculate the mc mac address list that should be added */
1806         for (i = 0; i < mc_addr_num; i++) {
1807                 addr = &mc_addr_set[i];
1808                 same_addr = false;
1809                 for (j = 0; j < current_addr_num; j++) {
1810                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1811                                 same_addr = true;
1812                                 break;
1813                         }
1814                 }
1815
1816                 if (!same_addr) {
1817                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1818                         add_num++;
1819                 }
1820         }
1821
1822         /* Reorder the mc mac address list maintained by driver */
1823         for (i = 0; i < reserved_num; i++)
1824                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1825
1826         for (i = 0; i < rm_num; i++) {
1827                 num = reserved_num + i;
1828                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1829         }
1830
1831         *reserved_addr_num = reserved_num;
1832         *add_addr_num = add_num;
1833         *rm_addr_num = rm_num;
1834 }
1835
1836 static int
1837 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1838                           struct rte_ether_addr *mc_addr_set,
1839                           uint32_t nb_mc_addr)
1840 {
1841         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1843         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1844         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1845         struct rte_ether_addr *addr;
1846         int reserved_addr_num;
1847         int add_addr_num;
1848         int rm_addr_num;
1849         int mc_addr_num;
1850         int num;
1851         int ret;
1852         int i;
1853
1854         /* Check if input parameters are valid */
1855         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1856         if (ret)
1857                 return ret;
1858
1859         rte_spinlock_lock(&hw->lock);
1860
1861         /*
1862          * Calculate the mc mac address lists those should be removed and be
1863          * added, Reorder the mc mac address list maintained by driver.
1864          */
1865         mc_addr_num = (int)nb_mc_addr;
1866         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1867                                    reserved_addr_list, &reserved_addr_num,
1868                                    add_addr_list, &add_addr_num,
1869                                    rm_addr_list, &rm_addr_num);
1870
1871         /* Remove mc mac addresses */
1872         for (i = 0; i < rm_addr_num; i++) {
1873                 num = rm_addr_num - i - 1;
1874                 addr = &rm_addr_list[num];
1875                 ret = hns3_remove_mc_addr(hw, addr);
1876                 if (ret) {
1877                         rte_spinlock_unlock(&hw->lock);
1878                         return ret;
1879                 }
1880                 hw->mc_addrs_num--;
1881         }
1882
1883         /* Add mc mac addresses */
1884         for (i = 0; i < add_addr_num; i++) {
1885                 addr = &add_addr_list[i];
1886                 ret = hns3_add_mc_addr(hw, addr);
1887                 if (ret) {
1888                         rte_spinlock_unlock(&hw->lock);
1889                         return ret;
1890                 }
1891
1892                 num = reserved_addr_num + i;
1893                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1894                 hw->mc_addrs_num++;
1895         }
1896         rte_spinlock_unlock(&hw->lock);
1897
1898         return 0;
1899 }
1900
1901 static int
1902 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1903 {
1904         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1905         struct hns3_hw *hw = &hns->hw;
1906         struct rte_ether_addr *addr;
1907         int err = 0;
1908         int ret;
1909         int i;
1910
1911         for (i = 0; i < hw->mc_addrs_num; i++) {
1912                 addr = &hw->mc_addrs[i];
1913                 if (!rte_is_multicast_ether_addr(addr))
1914                         continue;
1915                 if (del)
1916                         ret = hns3_remove_mc_addr(hw, addr);
1917                 else
1918                         ret = hns3_add_mc_addr(hw, addr);
1919                 if (ret) {
1920                         err = ret;
1921                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1922                                               addr);
1923                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1924                                  del ? "Remove" : "Restore", mac_str);
1925                 }
1926         }
1927         return err;
1928 }
1929
1930 static int
1931 hns3_check_mq_mode(struct rte_eth_dev *dev)
1932 {
1933         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1934         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1935         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1937         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1938         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1939         uint8_t num_tc;
1940         int max_tc = 0;
1941         int i;
1942
1943         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1944         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1945
1946         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1947                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1948                          "rx_mq_mode = %d", rx_mq_mode);
1949                 return -EINVAL;
1950         }
1951
1952         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1953             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1954                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1955                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1956                          rx_mq_mode, tx_mq_mode);
1957                 return -EINVAL;
1958         }
1959
1960         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1961                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1962                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1963                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1964                         return -EINVAL;
1965                 }
1966
1967                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1968                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1969                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1970                                  "nb_tcs(%d) != %d or %d in rx direction.",
1971                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1972                         return -EINVAL;
1973                 }
1974
1975                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1976                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1977                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1978                         return -EINVAL;
1979                 }
1980
1981                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1982                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1983                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1984                                          "is not equal to one in tx direction.",
1985                                          i, dcb_rx_conf->dcb_tc[i]);
1986                                 return -EINVAL;
1987                         }
1988                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1989                                 max_tc = dcb_rx_conf->dcb_tc[i];
1990                 }
1991
1992                 num_tc = max_tc + 1;
1993                 if (num_tc > dcb_rx_conf->nb_tcs) {
1994                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1995                                  num_tc, dcb_rx_conf->nb_tcs);
1996                         return -EINVAL;
1997                 }
1998         }
1999
2000         return 0;
2001 }
2002
2003 static int
2004 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2005 {
2006         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2007
2008         if (!hns3_dev_dcb_supported(hw)) {
2009                 hns3_err(hw, "this port does not support dcb configurations.");
2010                 return -EOPNOTSUPP;
2011         }
2012
2013         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2014                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2015                 return -EOPNOTSUPP;
2016         }
2017
2018         /* Check multiple queue mode */
2019         return hns3_check_mq_mode(dev);
2020 }
2021
2022 static int
2023 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2024                            enum hns3_ring_type queue_type, uint16_t queue_id)
2025 {
2026         struct hns3_cmd_desc desc;
2027         struct hns3_ctrl_vector_chain_cmd *req =
2028                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2029         enum hns3_cmd_status status;
2030         enum hns3_opcode_type op;
2031         uint16_t tqp_type_and_id = 0;
2032         const char *op_str;
2033         uint16_t type;
2034         uint16_t gl;
2035
2036         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2037         hns3_cmd_setup_basic_desc(&desc, op, false);
2038         req->int_vector_id = vector_id;
2039
2040         if (queue_type == HNS3_RING_TYPE_RX)
2041                 gl = HNS3_RING_GL_RX;
2042         else
2043                 gl = HNS3_RING_GL_TX;
2044
2045         type = queue_type;
2046
2047         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2048                        type);
2049         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2050         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2051                        gl);
2052         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2053         req->int_cause_num = 1;
2054         op_str = mmap ? "Map" : "Unmap";
2055         status = hns3_cmd_send(hw, &desc, 1);
2056         if (status) {
2057                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2058                          op_str, queue_id, req->int_vector_id, status);
2059                 return status;
2060         }
2061
2062         return 0;
2063 }
2064
2065 static int
2066 hns3_init_ring_with_vector(struct hns3_hw *hw)
2067 {
2068         uint8_t vec;
2069         int ret;
2070         int i;
2071
2072         /*
2073          * In hns3 network engine, vector 0 is always the misc interrupt of this
2074          * function, vector 1~N can be used respectively for the queues of the
2075          * function. Tx and Rx queues with the same number share the interrupt
2076          * vector. In the initialization clearing the all hardware mapping
2077          * relationship configurations between queues and interrupt vectors is
2078          * needed, so some error caused by the residual configurations, such as
2079          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2080          * constraints in hns3 hardware engine, we have to implement clearing
2081          * the mapping relationship configurations by binding all queues to the
2082          * last interrupt vector and reserving the last interrupt vector. This
2083          * method results in a decrease of the maximum queues when upper
2084          * applications call the rte_eth_dev_configure API function to enable
2085          * Rx interrupt.
2086          */
2087         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2088         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2089         for (i = 0; i < hw->intr_tqps_num; i++) {
2090                 /*
2091                  * Set gap limiter and rate limiter configuration of queue's
2092                  * interrupt.
2093                  */
2094                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2095                                        HNS3_TQP_INTR_GL_DEFAULT);
2096                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2097                                        HNS3_TQP_INTR_GL_DEFAULT);
2098                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2099
2100                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2101                                                  HNS3_RING_TYPE_TX, i);
2102                 if (ret) {
2103                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2104                                           "vector: %d, ret=%d", i, vec, ret);
2105                         return ret;
2106                 }
2107
2108                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2109                                                  HNS3_RING_TYPE_RX, i);
2110                 if (ret) {
2111                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2112                                           "vector: %d, ret=%d", i, vec, ret);
2113                         return ret;
2114                 }
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int
2121 hns3_dev_configure(struct rte_eth_dev *dev)
2122 {
2123         struct hns3_adapter *hns = dev->data->dev_private;
2124         struct rte_eth_conf *conf = &dev->data->dev_conf;
2125         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2126         struct hns3_hw *hw = &hns->hw;
2127         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2128         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2129         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2130         struct rte_eth_rss_conf rss_conf;
2131         uint16_t mtu;
2132         int ret;
2133
2134         /*
2135          * Hardware does not support individually enable/disable/reset the Tx or
2136          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2137          * and Rx queues at the same time. When the numbers of Tx queues
2138          * allocated by upper applications are not equal to the numbers of Rx
2139          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2140          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2141          * these fake queues are imperceptible, and can not be used by upper
2142          * applications.
2143          */
2144         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2145         if (ret) {
2146                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2147                 return ret;
2148         }
2149
2150         hw->adapter_state = HNS3_NIC_CONFIGURING;
2151         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2152                 hns3_err(hw, "setting link speed/duplex not supported");
2153                 ret = -EINVAL;
2154                 goto cfg_err;
2155         }
2156
2157         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2158                 ret = hns3_check_dcb_cfg(dev);
2159                 if (ret)
2160                         goto cfg_err;
2161         }
2162
2163         /* When RSS is not configured, redirect the packet queue 0 */
2164         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2165                 rss_conf = conf->rx_adv_conf.rss_conf;
2166                 if (rss_conf.rss_key == NULL) {
2167                         rss_conf.rss_key = rss_cfg->key;
2168                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2169                 }
2170
2171                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2172                 if (ret)
2173                         goto cfg_err;
2174         }
2175
2176         /*
2177          * If jumbo frames are enabled, MTU needs to be refreshed
2178          * according to the maximum RX packet length.
2179          */
2180         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2181                 /*
2182                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2183                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2184                  * can safely assign to "uint16_t" type variable.
2185                  */
2186                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2187                 ret = hns3_dev_mtu_set(dev, mtu);
2188                 if (ret)
2189                         goto cfg_err;
2190                 dev->data->mtu = mtu;
2191         }
2192
2193         ret = hns3_dev_configure_vlan(dev);
2194         if (ret)
2195                 goto cfg_err;
2196
2197         hw->adapter_state = HNS3_NIC_CONFIGURED;
2198
2199         return 0;
2200
2201 cfg_err:
2202         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2203         hw->adapter_state = HNS3_NIC_INITIALIZED;
2204
2205         return ret;
2206 }
2207
2208 static int
2209 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2210 {
2211         struct hns3_config_max_frm_size_cmd *req;
2212         struct hns3_cmd_desc desc;
2213
2214         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2215
2216         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2217         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2218         req->min_frm_size = RTE_ETHER_MIN_LEN;
2219
2220         return hns3_cmd_send(hw, &desc, 1);
2221 }
2222
2223 static int
2224 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2225 {
2226         int ret;
2227
2228         ret = hns3_set_mac_mtu(hw, mps);
2229         if (ret) {
2230                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2231                 return ret;
2232         }
2233
2234         ret = hns3_buffer_alloc(hw);
2235         if (ret) {
2236                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2237                 return ret;
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int
2244 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2245 {
2246         struct hns3_adapter *hns = dev->data->dev_private;
2247         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2248         struct hns3_hw *hw = &hns->hw;
2249         bool is_jumbo_frame;
2250         int ret;
2251
2252         if (dev->data->dev_started) {
2253                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2254                          "before configuration", dev->data->port_id);
2255                 return -EBUSY;
2256         }
2257
2258         rte_spinlock_lock(&hw->lock);
2259         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2260         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2261
2262         /*
2263          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2264          * assign to "uint16_t" type variable.
2265          */
2266         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2267         if (ret) {
2268                 rte_spinlock_unlock(&hw->lock);
2269                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2270                          dev->data->port_id, mtu, ret);
2271                 return ret;
2272         }
2273         hns->pf.mps = (uint16_t)frame_size;
2274         if (is_jumbo_frame)
2275                 dev->data->dev_conf.rxmode.offloads |=
2276                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2277         else
2278                 dev->data->dev_conf.rxmode.offloads &=
2279                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2280         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2281         rte_spinlock_unlock(&hw->lock);
2282
2283         return 0;
2284 }
2285
2286 static int
2287 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2288 {
2289         struct hns3_adapter *hns = eth_dev->data->dev_private;
2290         struct hns3_hw *hw = &hns->hw;
2291         uint16_t queue_num = hw->tqps_num;
2292
2293         /*
2294          * In interrupt mode, 'max_rx_queues' is set based on the number of
2295          * MSI-X interrupt resources of the hardware.
2296          */
2297         if (hw->data->dev_conf.intr_conf.rxq == 1)
2298                 queue_num = hw->intr_tqps_num;
2299
2300         info->max_rx_queues = queue_num;
2301         info->max_tx_queues = hw->tqps_num;
2302         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2303         info->min_rx_bufsize = hw->rx_buf_len;
2304         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2305         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2306         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2307                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2308                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2309                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2310                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2311                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2312                                  DEV_RX_OFFLOAD_KEEP_CRC |
2313                                  DEV_RX_OFFLOAD_SCATTER |
2314                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2315                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2316                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2317                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2318                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2319         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2320         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2321                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2322                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2323                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2324                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2325                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2326                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2327                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2328                                  DEV_TX_OFFLOAD_TCP_TSO |
2329                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2330                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2331                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2332                                  info->tx_queue_offload_capa);
2333
2334         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2335                 .nb_max = HNS3_MAX_RING_DESC,
2336                 .nb_min = HNS3_MIN_RING_DESC,
2337                 .nb_align = HNS3_ALIGN_RING_DESC,
2338         };
2339
2340         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2341                 .nb_max = HNS3_MAX_RING_DESC,
2342                 .nb_min = HNS3_MIN_RING_DESC,
2343                 .nb_align = HNS3_ALIGN_RING_DESC,
2344         };
2345
2346         info->vmdq_queue_num = 0;
2347
2348         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2349         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2350         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2351
2352         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2353         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2354         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2355         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2356         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2357         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2358
2359         return 0;
2360 }
2361
2362 static int
2363 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2364                     size_t fw_size)
2365 {
2366         struct hns3_adapter *hns = eth_dev->data->dev_private;
2367         struct hns3_hw *hw = &hns->hw;
2368         int ret;
2369
2370         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2371         ret += 1; /* add the size of '\0' */
2372         if (fw_size < (uint32_t)ret)
2373                 return ret;
2374         else
2375                 return 0;
2376 }
2377
2378 static int
2379 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2380                      __rte_unused int wait_to_complete)
2381 {
2382         struct hns3_adapter *hns = eth_dev->data->dev_private;
2383         struct hns3_hw *hw = &hns->hw;
2384         struct hns3_mac *mac = &hw->mac;
2385         struct rte_eth_link new_link;
2386
2387         if (!hns3_is_reset_pending(hns)) {
2388                 hns3_update_speed_duplex(eth_dev);
2389                 hns3_update_link_status(hw);
2390         }
2391
2392         memset(&new_link, 0, sizeof(new_link));
2393         switch (mac->link_speed) {
2394         case ETH_SPEED_NUM_10M:
2395         case ETH_SPEED_NUM_100M:
2396         case ETH_SPEED_NUM_1G:
2397         case ETH_SPEED_NUM_10G:
2398         case ETH_SPEED_NUM_25G:
2399         case ETH_SPEED_NUM_40G:
2400         case ETH_SPEED_NUM_50G:
2401         case ETH_SPEED_NUM_100G:
2402                 new_link.link_speed = mac->link_speed;
2403                 break;
2404         default:
2405                 new_link.link_speed = ETH_SPEED_NUM_100M;
2406                 break;
2407         }
2408
2409         new_link.link_duplex = mac->link_duplex;
2410         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2411         new_link.link_autoneg =
2412             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2413
2414         return rte_eth_linkstatus_set(eth_dev, &new_link);
2415 }
2416
2417 static int
2418 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2419 {
2420         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2421         struct hns3_pf *pf = &hns->pf;
2422
2423         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2424                 return -EINVAL;
2425
2426         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2427
2428         return 0;
2429 }
2430
2431 static int
2432 hns3_query_function_status(struct hns3_hw *hw)
2433 {
2434 #define HNS3_QUERY_MAX_CNT              10
2435 #define HNS3_QUERY_SLEEP_MSCOEND        1
2436         struct hns3_func_status_cmd *req;
2437         struct hns3_cmd_desc desc;
2438         int timeout = 0;
2439         int ret;
2440
2441         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2442         req = (struct hns3_func_status_cmd *)desc.data;
2443
2444         do {
2445                 ret = hns3_cmd_send(hw, &desc, 1);
2446                 if (ret) {
2447                         PMD_INIT_LOG(ERR, "query function status failed %d",
2448                                      ret);
2449                         return ret;
2450                 }
2451
2452                 /* Check pf reset is done */
2453                 if (req->pf_state)
2454                         break;
2455
2456                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2457         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2458
2459         return hns3_parse_func_status(hw, req);
2460 }
2461
2462 static int
2463 hns3_query_pf_resource(struct hns3_hw *hw)
2464 {
2465         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2466         struct hns3_pf *pf = &hns->pf;
2467         struct hns3_pf_res_cmd *req;
2468         struct hns3_cmd_desc desc;
2469         uint16_t num_msi;
2470         int ret;
2471
2472         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2473         ret = hns3_cmd_send(hw, &desc, 1);
2474         if (ret) {
2475                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2476                 return ret;
2477         }
2478
2479         req = (struct hns3_pf_res_cmd *)desc.data;
2480         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2481         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2482         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2483         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2484
2485         if (req->tx_buf_size)
2486                 pf->tx_buf_size =
2487                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2488         else
2489                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2490
2491         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2492
2493         if (req->dv_buf_size)
2494                 pf->dv_buf_size =
2495                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2496         else
2497                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2498
2499         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2500
2501         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2502                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2503         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2504
2505         return 0;
2506 }
2507
2508 static void
2509 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2510 {
2511         struct hns3_cfg_param_cmd *req;
2512         uint64_t mac_addr_tmp_high;
2513         uint64_t mac_addr_tmp;
2514         uint32_t i;
2515
2516         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2517
2518         /* get the configuration */
2519         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2520                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2521         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2522                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2523         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2524                                            HNS3_CFG_TQP_DESC_N_M,
2525                                            HNS3_CFG_TQP_DESC_N_S);
2526
2527         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2528                                        HNS3_CFG_PHY_ADDR_M,
2529                                        HNS3_CFG_PHY_ADDR_S);
2530         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2531                                          HNS3_CFG_MEDIA_TP_M,
2532                                          HNS3_CFG_MEDIA_TP_S);
2533         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534                                          HNS3_CFG_RX_BUF_LEN_M,
2535                                          HNS3_CFG_RX_BUF_LEN_S);
2536         /* get mac address */
2537         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2538         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2539                                            HNS3_CFG_MAC_ADDR_H_M,
2540                                            HNS3_CFG_MAC_ADDR_H_S);
2541
2542         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2543
2544         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2545                                             HNS3_CFG_DEFAULT_SPEED_M,
2546                                             HNS3_CFG_DEFAULT_SPEED_S);
2547         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2548                                            HNS3_CFG_RSS_SIZE_M,
2549                                            HNS3_CFG_RSS_SIZE_S);
2550
2551         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2552                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2553
2554         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2555         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2556
2557         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2558                                             HNS3_CFG_SPEED_ABILITY_M,
2559                                             HNS3_CFG_SPEED_ABILITY_S);
2560         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2561                                         HNS3_CFG_UMV_TBL_SPACE_M,
2562                                         HNS3_CFG_UMV_TBL_SPACE_S);
2563         if (!cfg->umv_space)
2564                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2565 }
2566
2567 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2568  * @hw: pointer to struct hns3_hw
2569  * @hcfg: the config structure to be getted
2570  */
2571 static int
2572 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2573 {
2574         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2575         struct hns3_cfg_param_cmd *req;
2576         uint32_t offset;
2577         uint32_t i;
2578         int ret;
2579
2580         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2581                 offset = 0;
2582                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2583                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2584                                           true);
2585                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2586                                i * HNS3_CFG_RD_LEN_BYTES);
2587                 /* Len should be divided by 4 when send to hardware */
2588                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2589                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2590                 req->offset = rte_cpu_to_le_32(offset);
2591         }
2592
2593         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2594         if (ret) {
2595                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2596                 return ret;
2597         }
2598
2599         hns3_parse_cfg(hcfg, desc);
2600
2601         return 0;
2602 }
2603
2604 static int
2605 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2606 {
2607         switch (speed_cmd) {
2608         case HNS3_CFG_SPEED_10M:
2609                 *speed = ETH_SPEED_NUM_10M;
2610                 break;
2611         case HNS3_CFG_SPEED_100M:
2612                 *speed = ETH_SPEED_NUM_100M;
2613                 break;
2614         case HNS3_CFG_SPEED_1G:
2615                 *speed = ETH_SPEED_NUM_1G;
2616                 break;
2617         case HNS3_CFG_SPEED_10G:
2618                 *speed = ETH_SPEED_NUM_10G;
2619                 break;
2620         case HNS3_CFG_SPEED_25G:
2621                 *speed = ETH_SPEED_NUM_25G;
2622                 break;
2623         case HNS3_CFG_SPEED_40G:
2624                 *speed = ETH_SPEED_NUM_40G;
2625                 break;
2626         case HNS3_CFG_SPEED_50G:
2627                 *speed = ETH_SPEED_NUM_50G;
2628                 break;
2629         case HNS3_CFG_SPEED_100G:
2630                 *speed = ETH_SPEED_NUM_100G;
2631                 break;
2632         default:
2633                 return -EINVAL;
2634         }
2635
2636         return 0;
2637 }
2638
2639 static int
2640 hns3_get_board_configuration(struct hns3_hw *hw)
2641 {
2642         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2643         struct hns3_pf *pf = &hns->pf;
2644         struct hns3_cfg cfg;
2645         int ret;
2646
2647         ret = hns3_get_board_cfg(hw, &cfg);
2648         if (ret) {
2649                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2650                 return ret;
2651         }
2652
2653         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2654                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2655                 return -EOPNOTSUPP;
2656         }
2657
2658         hw->mac.media_type = cfg.media_type;
2659         hw->rss_size_max = cfg.rss_size_max;
2660         hw->rx_buf_len = cfg.rx_buf_len;
2661         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2662         hw->mac.phy_addr = cfg.phy_addr;
2663         hw->mac.default_addr_setted = false;
2664         hw->num_tx_desc = cfg.tqp_desc_num;
2665         hw->num_rx_desc = cfg.tqp_desc_num;
2666         hw->dcb_info.num_pg = 1;
2667         hw->dcb_info.hw_pfc_map = 0;
2668
2669         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2670         if (ret) {
2671                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2672                              cfg.default_speed, ret);
2673                 return ret;
2674         }
2675
2676         pf->tc_max = cfg.tc_num;
2677         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2678                 PMD_INIT_LOG(WARNING,
2679                              "Get TC num(%u) from flash, set TC num to 1",
2680                              pf->tc_max);
2681                 pf->tc_max = 1;
2682         }
2683
2684         /* Dev does not support DCB */
2685         if (!hns3_dev_dcb_supported(hw)) {
2686                 pf->tc_max = 1;
2687                 pf->pfc_max = 0;
2688         } else
2689                 pf->pfc_max = pf->tc_max;
2690
2691         hw->dcb_info.num_tc = 1;
2692         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2693                                      hw->tqps_num / hw->dcb_info.num_tc);
2694         hns3_set_bit(hw->hw_tc_map, 0, 1);
2695         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2696
2697         pf->wanted_umv_size = cfg.umv_space;
2698
2699         return ret;
2700 }
2701
2702 static int
2703 hns3_get_configuration(struct hns3_hw *hw)
2704 {
2705         int ret;
2706
2707         ret = hns3_query_function_status(hw);
2708         if (ret) {
2709                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2710                 return ret;
2711         }
2712
2713         /* Get pf resource */
2714         ret = hns3_query_pf_resource(hw);
2715         if (ret) {
2716                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2717                 return ret;
2718         }
2719
2720         ret = hns3_get_board_configuration(hw);
2721         if (ret) {
2722                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2723                 return ret;
2724         }
2725
2726         return 0;
2727 }
2728
2729 static int
2730 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2731                       uint16_t tqp_vid, bool is_pf)
2732 {
2733         struct hns3_tqp_map_cmd *req;
2734         struct hns3_cmd_desc desc;
2735         int ret;
2736
2737         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2738
2739         req = (struct hns3_tqp_map_cmd *)desc.data;
2740         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2741         req->tqp_vf = func_id;
2742         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2743         if (!is_pf)
2744                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2745         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2746
2747         ret = hns3_cmd_send(hw, &desc, 1);
2748         if (ret)
2749                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2750
2751         return ret;
2752 }
2753
2754 static int
2755 hns3_map_tqp(struct hns3_hw *hw)
2756 {
2757         uint16_t tqps_num = hw->total_tqps_num;
2758         uint16_t func_id;
2759         uint16_t tqp_id;
2760         bool is_pf;
2761         int num;
2762         int ret;
2763         int i;
2764
2765         /*
2766          * In current version VF is not supported when PF is driven by DPDK
2767          * driver, so we allocate tqps to PF as much as possible.
2768          */
2769         tqp_id = 0;
2770         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2771         for (func_id = 0; func_id < num; func_id++) {
2772                 is_pf = func_id == 0 ? true : false;
2773                 for (i = 0;
2774                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2775                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2776                                                     is_pf);
2777                         if (ret)
2778                                 return ret;
2779                 }
2780         }
2781
2782         return 0;
2783 }
2784
2785 static int
2786 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2787 {
2788         struct hns3_config_mac_speed_dup_cmd *req;
2789         struct hns3_cmd_desc desc;
2790         int ret;
2791
2792         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2793
2794         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2795
2796         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2797
2798         switch (speed) {
2799         case ETH_SPEED_NUM_10M:
2800                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2801                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2802                 break;
2803         case ETH_SPEED_NUM_100M:
2804                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2805                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2806                 break;
2807         case ETH_SPEED_NUM_1G:
2808                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2809                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2810                 break;
2811         case ETH_SPEED_NUM_10G:
2812                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2813                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2814                 break;
2815         case ETH_SPEED_NUM_25G:
2816                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2817                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2818                 break;
2819         case ETH_SPEED_NUM_40G:
2820                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2821                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2822                 break;
2823         case ETH_SPEED_NUM_50G:
2824                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2825                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2826                 break;
2827         case ETH_SPEED_NUM_100G:
2828                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2829                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2830                 break;
2831         default:
2832                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2833                 return -EINVAL;
2834         }
2835
2836         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2837
2838         ret = hns3_cmd_send(hw, &desc, 1);
2839         if (ret)
2840                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2841
2842         return ret;
2843 }
2844
2845 static int
2846 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2847 {
2848         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2849         struct hns3_pf *pf = &hns->pf;
2850         struct hns3_priv_buf *priv;
2851         uint32_t i, total_size;
2852
2853         total_size = pf->pkt_buf_size;
2854
2855         /* alloc tx buffer for all enabled tc */
2856         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2857                 priv = &buf_alloc->priv_buf[i];
2858
2859                 if (hw->hw_tc_map & BIT(i)) {
2860                         if (total_size < pf->tx_buf_size)
2861                                 return -ENOMEM;
2862
2863                         priv->tx_buf_size = pf->tx_buf_size;
2864                 } else
2865                         priv->tx_buf_size = 0;
2866
2867                 total_size -= priv->tx_buf_size;
2868         }
2869
2870         return 0;
2871 }
2872
2873 static int
2874 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2875 {
2876 /* TX buffer size is unit by 128 byte */
2877 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2878 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2879         struct hns3_tx_buff_alloc_cmd *req;
2880         struct hns3_cmd_desc desc;
2881         uint32_t buf_size;
2882         uint32_t i;
2883         int ret;
2884
2885         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2886
2887         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2888         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2889                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2890
2891                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2892                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2893                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2894         }
2895
2896         ret = hns3_cmd_send(hw, &desc, 1);
2897         if (ret)
2898                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2899
2900         return ret;
2901 }
2902
2903 static int
2904 hns3_get_tc_num(struct hns3_hw *hw)
2905 {
2906         int cnt = 0;
2907         uint8_t i;
2908
2909         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2910                 if (hw->hw_tc_map & BIT(i))
2911                         cnt++;
2912         return cnt;
2913 }
2914
2915 static uint32_t
2916 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2917 {
2918         struct hns3_priv_buf *priv;
2919         uint32_t rx_priv = 0;
2920         int i;
2921
2922         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2923                 priv = &buf_alloc->priv_buf[i];
2924                 if (priv->enable)
2925                         rx_priv += priv->buf_size;
2926         }
2927         return rx_priv;
2928 }
2929
2930 static uint32_t
2931 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2932 {
2933         uint32_t total_tx_size = 0;
2934         uint32_t i;
2935
2936         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2937                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2938
2939         return total_tx_size;
2940 }
2941
2942 /* Get the number of pfc enabled TCs, which have private buffer */
2943 static int
2944 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2945 {
2946         struct hns3_priv_buf *priv;
2947         int cnt = 0;
2948         uint8_t i;
2949
2950         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2951                 priv = &buf_alloc->priv_buf[i];
2952                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2953                         cnt++;
2954         }
2955
2956         return cnt;
2957 }
2958
2959 /* Get the number of pfc disabled TCs, which have private buffer */
2960 static int
2961 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2962                          struct hns3_pkt_buf_alloc *buf_alloc)
2963 {
2964         struct hns3_priv_buf *priv;
2965         int cnt = 0;
2966         uint8_t i;
2967
2968         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2969                 priv = &buf_alloc->priv_buf[i];
2970                 if (hw->hw_tc_map & BIT(i) &&
2971                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2972                         cnt++;
2973         }
2974
2975         return cnt;
2976 }
2977
2978 static bool
2979 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2980                   uint32_t rx_all)
2981 {
2982         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2983         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2984         struct hns3_pf *pf = &hns->pf;
2985         uint32_t shared_buf, aligned_mps;
2986         uint32_t rx_priv;
2987         uint8_t tc_num;
2988         uint8_t i;
2989
2990         tc_num = hns3_get_tc_num(hw);
2991         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2992
2993         if (hns3_dev_dcb_supported(hw))
2994                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2995                                         pf->dv_buf_size;
2996         else
2997                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2998                                         + pf->dv_buf_size;
2999
3000         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3001         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3002                              HNS3_BUF_SIZE_UNIT);
3003
3004         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3005         if (rx_all < rx_priv + shared_std)
3006                 return false;
3007
3008         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3009         buf_alloc->s_buf.buf_size = shared_buf;
3010         if (hns3_dev_dcb_supported(hw)) {
3011                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3012                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3013                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3014                                   HNS3_BUF_SIZE_UNIT);
3015         } else {
3016                 buf_alloc->s_buf.self.high =
3017                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3018                 buf_alloc->s_buf.self.low = aligned_mps;
3019         }
3020
3021         if (hns3_dev_dcb_supported(hw)) {
3022                 hi_thrd = shared_buf - pf->dv_buf_size;
3023
3024                 if (tc_num <= NEED_RESERVE_TC_NUM)
3025                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3026                                         / BUF_MAX_PERCENT;
3027
3028                 if (tc_num)
3029                         hi_thrd = hi_thrd / tc_num;
3030
3031                 hi_thrd = max_t(uint32_t, hi_thrd,
3032                                 HNS3_BUF_MUL_BY * aligned_mps);
3033                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3034                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3035         } else {
3036                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3037                 lo_thrd = aligned_mps;
3038         }
3039
3040         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3041                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3042                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3043         }
3044
3045         return true;
3046 }
3047
3048 static bool
3049 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3050                      struct hns3_pkt_buf_alloc *buf_alloc)
3051 {
3052         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3053         struct hns3_pf *pf = &hns->pf;
3054         struct hns3_priv_buf *priv;
3055         uint32_t aligned_mps;
3056         uint32_t rx_all;
3057         uint8_t i;
3058
3059         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3060         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3061
3062         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3063                 priv = &buf_alloc->priv_buf[i];
3064
3065                 priv->enable = 0;
3066                 priv->wl.low = 0;
3067                 priv->wl.high = 0;
3068                 priv->buf_size = 0;
3069
3070                 if (!(hw->hw_tc_map & BIT(i)))
3071                         continue;
3072
3073                 priv->enable = 1;
3074                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3075                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3076                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3077                                                 HNS3_BUF_SIZE_UNIT);
3078                 } else {
3079                         priv->wl.low = 0;
3080                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3081                                         aligned_mps;
3082                 }
3083
3084                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3085         }
3086
3087         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3088 }
3089
3090 static bool
3091 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3092                              struct hns3_pkt_buf_alloc *buf_alloc)
3093 {
3094         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3095         struct hns3_pf *pf = &hns->pf;
3096         struct hns3_priv_buf *priv;
3097         int no_pfc_priv_num;
3098         uint32_t rx_all;
3099         uint8_t mask;
3100         int i;
3101
3102         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3103         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3104
3105         /* let the last to be cleared first */
3106         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3107                 priv = &buf_alloc->priv_buf[i];
3108                 mask = BIT((uint8_t)i);
3109
3110                 if (hw->hw_tc_map & mask &&
3111                     !(hw->dcb_info.hw_pfc_map & mask)) {
3112                         /* Clear the no pfc TC private buffer */
3113                         priv->wl.low = 0;
3114                         priv->wl.high = 0;
3115                         priv->buf_size = 0;
3116                         priv->enable = 0;
3117                         no_pfc_priv_num--;
3118                 }
3119
3120                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3121                     no_pfc_priv_num == 0)
3122                         break;
3123         }
3124
3125         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3126 }
3127
3128 static bool
3129 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3130                            struct hns3_pkt_buf_alloc *buf_alloc)
3131 {
3132         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3133         struct hns3_pf *pf = &hns->pf;
3134         struct hns3_priv_buf *priv;
3135         uint32_t rx_all;
3136         int pfc_priv_num;
3137         uint8_t mask;
3138         int i;
3139
3140         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3141         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3142
3143         /* let the last to be cleared first */
3144         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3145                 priv = &buf_alloc->priv_buf[i];
3146                 mask = BIT((uint8_t)i);
3147
3148                 if (hw->hw_tc_map & mask &&
3149                     hw->dcb_info.hw_pfc_map & mask) {
3150                         /* Reduce the number of pfc TC with private buffer */
3151                         priv->wl.low = 0;
3152                         priv->enable = 0;
3153                         priv->wl.high = 0;
3154                         priv->buf_size = 0;
3155                         pfc_priv_num--;
3156                 }
3157                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3158                     pfc_priv_num == 0)
3159                         break;
3160         }
3161
3162         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3163 }
3164
3165 static bool
3166 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3167                           struct hns3_pkt_buf_alloc *buf_alloc)
3168 {
3169 #define COMPENSATE_BUFFER       0x3C00
3170 #define COMPENSATE_HALF_MPS_NUM 5
3171 #define PRIV_WL_GAP             0x1800
3172         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3173         struct hns3_pf *pf = &hns->pf;
3174         uint32_t tc_num = hns3_get_tc_num(hw);
3175         uint32_t half_mps = pf->mps >> 1;
3176         struct hns3_priv_buf *priv;
3177         uint32_t min_rx_priv;
3178         uint32_t rx_priv;
3179         uint8_t i;
3180
3181         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3182         if (tc_num)
3183                 rx_priv = rx_priv / tc_num;
3184
3185         if (tc_num <= NEED_RESERVE_TC_NUM)
3186                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3187
3188         /*
3189          * Minimum value of private buffer in rx direction (min_rx_priv) is
3190          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3191          * buffer if rx_priv is greater than min_rx_priv.
3192          */
3193         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3194                         COMPENSATE_HALF_MPS_NUM * half_mps;
3195         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3196         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3197
3198         if (rx_priv < min_rx_priv)
3199                 return false;
3200
3201         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3202                 priv = &buf_alloc->priv_buf[i];
3203
3204                 priv->enable = 0;
3205                 priv->wl.low = 0;
3206                 priv->wl.high = 0;
3207                 priv->buf_size = 0;
3208
3209                 if (!(hw->hw_tc_map & BIT(i)))
3210                         continue;
3211
3212                 priv->enable = 1;
3213                 priv->buf_size = rx_priv;
3214                 priv->wl.high = rx_priv - pf->dv_buf_size;
3215                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3216         }
3217
3218         buf_alloc->s_buf.buf_size = 0;
3219
3220         return true;
3221 }
3222
3223 /*
3224  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3225  * @hw: pointer to struct hns3_hw
3226  * @buf_alloc: pointer to buffer calculation data
3227  * @return: 0: calculate sucessful, negative: fail
3228  */
3229 static int
3230 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3231 {
3232         /* When DCB is not supported, rx private buffer is not allocated. */
3233         if (!hns3_dev_dcb_supported(hw)) {
3234                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3235                 struct hns3_pf *pf = &hns->pf;
3236                 uint32_t rx_all = pf->pkt_buf_size;
3237
3238                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3239                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3240                         return -ENOMEM;
3241
3242                 return 0;
3243         }
3244
3245         /*
3246          * Try to allocate privated packet buffer for all TCs without share
3247          * buffer.
3248          */
3249         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3250                 return 0;
3251
3252         /*
3253          * Try to allocate privated packet buffer for all TCs with share
3254          * buffer.
3255          */
3256         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3257                 return 0;
3258
3259         /*
3260          * For different application scenes, the enabled port number, TC number
3261          * and no_drop TC number are different. In order to obtain the better
3262          * performance, software could allocate the buffer size and configure
3263          * the waterline by tring to decrease the private buffer size according
3264          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3265          * enabled tc.
3266          */
3267         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3268                 return 0;
3269
3270         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3271                 return 0;
3272
3273         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3274                 return 0;
3275
3276         return -ENOMEM;
3277 }
3278
3279 static int
3280 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3281 {
3282         struct hns3_rx_priv_buff_cmd *req;
3283         struct hns3_cmd_desc desc;
3284         uint32_t buf_size;
3285         int ret;
3286         int i;
3287
3288         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3289         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3290
3291         /* Alloc private buffer TCs */
3292         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3293                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3294
3295                 req->buf_num[i] =
3296                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3297                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3298         }
3299
3300         buf_size = buf_alloc->s_buf.buf_size;
3301         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3302                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3303
3304         ret = hns3_cmd_send(hw, &desc, 1);
3305         if (ret)
3306                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3307
3308         return ret;
3309 }
3310
3311 static int
3312 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3313 {
3314 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3315         struct hns3_rx_priv_wl_buf *req;
3316         struct hns3_priv_buf *priv;
3317         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3318         int i, j;
3319         int ret;
3320
3321         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3322                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3323                                           false);
3324                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3325
3326                 /* The first descriptor set the NEXT bit to 1 */
3327                 if (i == 0)
3328                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3329                 else
3330                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3331
3332                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3333                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3334
3335                         priv = &buf_alloc->priv_buf[idx];
3336                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3337                                                         HNS3_BUF_UNIT_S);
3338                         req->tc_wl[j].high |=
3339                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3340                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3341                                                         HNS3_BUF_UNIT_S);
3342                         req->tc_wl[j].low |=
3343                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3344                 }
3345         }
3346
3347         /* Send 2 descriptor at one time */
3348         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3349         if (ret)
3350                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3351                              ret);
3352         return ret;
3353 }
3354
3355 static int
3356 hns3_common_thrd_config(struct hns3_hw *hw,
3357                         struct hns3_pkt_buf_alloc *buf_alloc)
3358 {
3359 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3360         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3361         struct hns3_rx_com_thrd *req;
3362         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3363         struct hns3_tc_thrd *tc;
3364         int tc_idx;
3365         int i, j;
3366         int ret;
3367
3368         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3369                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3370                                           false);
3371                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3372
3373                 /* The first descriptor set the NEXT bit to 1 */
3374                 if (i == 0)
3375                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3376                 else
3377                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3378
3379                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3380                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3381                         tc = &s_buf->tc_thrd[tc_idx];
3382
3383                         req->com_thrd[j].high =
3384                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3385                         req->com_thrd[j].high |=
3386                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3387                         req->com_thrd[j].low =
3388                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3389                         req->com_thrd[j].low |=
3390                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3391                 }
3392         }
3393
3394         /* Send 2 descriptors at one time */
3395         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3396         if (ret)
3397                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3398
3399         return ret;
3400 }
3401
3402 static int
3403 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3404 {
3405         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3406         struct hns3_rx_com_wl *req;
3407         struct hns3_cmd_desc desc;
3408         int ret;
3409
3410         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3411
3412         req = (struct hns3_rx_com_wl *)desc.data;
3413         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3414         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3415
3416         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3417         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3418
3419         ret = hns3_cmd_send(hw, &desc, 1);
3420         if (ret)
3421                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3422
3423         return ret;
3424 }
3425
3426 int
3427 hns3_buffer_alloc(struct hns3_hw *hw)
3428 {
3429         struct hns3_pkt_buf_alloc pkt_buf;
3430         int ret;
3431
3432         memset(&pkt_buf, 0, sizeof(pkt_buf));
3433         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3434         if (ret) {
3435                 PMD_INIT_LOG(ERR,
3436                              "could not calc tx buffer size for all TCs %d",
3437                              ret);
3438                 return ret;
3439         }
3440
3441         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3442         if (ret) {
3443                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3444                 return ret;
3445         }
3446
3447         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3448         if (ret) {
3449                 PMD_INIT_LOG(ERR,
3450                              "could not calc rx priv buffer size for all TCs %d",
3451                              ret);
3452                 return ret;
3453         }
3454
3455         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3456         if (ret) {
3457                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3458                 return ret;
3459         }
3460
3461         if (hns3_dev_dcb_supported(hw)) {
3462                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3463                 if (ret) {
3464                         PMD_INIT_LOG(ERR,
3465                                      "could not configure rx private waterline %d",
3466                                      ret);
3467                         return ret;
3468                 }
3469
3470                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3471                 if (ret) {
3472                         PMD_INIT_LOG(ERR,
3473                                      "could not configure common threshold %d",
3474                                      ret);
3475                         return ret;
3476                 }
3477         }
3478
3479         ret = hns3_common_wl_config(hw, &pkt_buf);
3480         if (ret)
3481                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3482                              ret);
3483
3484         return ret;
3485 }
3486
3487 static int
3488 hns3_mac_init(struct hns3_hw *hw)
3489 {
3490         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3491         struct hns3_mac *mac = &hw->mac;
3492         struct hns3_pf *pf = &hns->pf;
3493         int ret;
3494
3495         pf->support_sfp_query = true;
3496         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3497         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3498         if (ret) {
3499                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3500                 return ret;
3501         }
3502
3503         mac->link_status = ETH_LINK_DOWN;
3504
3505         return hns3_config_mtu(hw, pf->mps);
3506 }
3507
3508 static int
3509 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3510 {
3511 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3512 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3513 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3514 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3515         int return_status;
3516
3517         if (cmdq_resp) {
3518                 PMD_INIT_LOG(ERR,
3519                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3520                              cmdq_resp);
3521                 return -EIO;
3522         }
3523
3524         switch (resp_code) {
3525         case HNS3_ETHERTYPE_SUCCESS_ADD:
3526         case HNS3_ETHERTYPE_ALREADY_ADD:
3527                 return_status = 0;
3528                 break;
3529         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3530                 PMD_INIT_LOG(ERR,
3531                              "add mac ethertype failed for manager table overflow.");
3532                 return_status = -EIO;
3533                 break;
3534         case HNS3_ETHERTYPE_KEY_CONFLICT:
3535                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3536                 return_status = -EIO;
3537                 break;
3538         default:
3539                 PMD_INIT_LOG(ERR,
3540                              "add mac ethertype failed for undefined, code=%d.",
3541                              resp_code);
3542                 return_status = -EIO;
3543         }
3544
3545         return return_status;
3546 }
3547
3548 static int
3549 hns3_add_mgr_tbl(struct hns3_hw *hw,
3550                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3551 {
3552         struct hns3_cmd_desc desc;
3553         uint8_t resp_code;
3554         uint16_t retval;
3555         int ret;
3556
3557         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3558         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3559
3560         ret = hns3_cmd_send(hw, &desc, 1);
3561         if (ret) {
3562                 PMD_INIT_LOG(ERR,
3563                              "add mac ethertype failed for cmd_send, ret =%d.",
3564                              ret);
3565                 return ret;
3566         }
3567
3568         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3569         retval = rte_le_to_cpu_16(desc.retval);
3570
3571         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3572 }
3573
3574 static void
3575 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3576                      int *table_item_num)
3577 {
3578         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3579
3580         /*
3581          * In current version, we add one item in management table as below:
3582          * 0x0180C200000E -- LLDP MC address
3583          */
3584         tbl = mgr_table;
3585         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3586         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3587         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3588         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3589         tbl->i_port_bitmap = 0x1;
3590         *table_item_num = 1;
3591 }
3592
3593 static int
3594 hns3_init_mgr_tbl(struct hns3_hw *hw)
3595 {
3596 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3597         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3598         int table_item_num;
3599         int ret;
3600         int i;
3601
3602         memset(mgr_table, 0, sizeof(mgr_table));
3603         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3604         for (i = 0; i < table_item_num; i++) {
3605                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3606                 if (ret) {
3607                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3608                                      ret);
3609                         return ret;
3610                 }
3611         }
3612
3613         return 0;
3614 }
3615
3616 static void
3617 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3618                         bool en_mc, bool en_bc, int vport_id)
3619 {
3620         if (!param)
3621                 return;
3622
3623         memset(param, 0, sizeof(struct hns3_promisc_param));
3624         if (en_uc)
3625                 param->enable = HNS3_PROMISC_EN_UC;
3626         if (en_mc)
3627                 param->enable |= HNS3_PROMISC_EN_MC;
3628         if (en_bc)
3629                 param->enable |= HNS3_PROMISC_EN_BC;
3630         param->vf_id = vport_id;
3631 }
3632
3633 static int
3634 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3635 {
3636         struct hns3_promisc_cfg_cmd *req;
3637         struct hns3_cmd_desc desc;
3638         int ret;
3639
3640         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3641
3642         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3643         req->vf_id = param->vf_id;
3644         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3645             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3646
3647         ret = hns3_cmd_send(hw, &desc, 1);
3648         if (ret)
3649                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3650
3651         return ret;
3652 }
3653
3654 static int
3655 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3656 {
3657         struct hns3_promisc_param param;
3658         bool en_bc_pmc = true;
3659         uint8_t vf_id;
3660         int ret;
3661
3662         /*
3663          * In current version VF is not supported when PF is driven by DPDK
3664          * driver, the PF-related vf_id is 0, just need to configure parameters
3665          * for vf_id 0.
3666          */
3667         vf_id = 0;
3668
3669         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3670         ret = hns3_cmd_set_promisc_mode(hw, &param);
3671         if (ret)
3672                 return ret;
3673
3674         return 0;
3675 }
3676
3677 static int
3678 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3679 {
3680         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3681         struct hns3_pf *pf = &hns->pf;
3682         struct hns3_promisc_param param;
3683         uint16_t func_id;
3684         int ret;
3685
3686         /* func_id 0 is denoted PF, the VFs start from 1 */
3687         for (func_id = 1; func_id < pf->func_num; func_id++) {
3688                 hns3_promisc_param_init(&param, false, false, false, func_id);
3689                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3690                 if (ret)
3691                         return ret;
3692         }
3693
3694         return 0;
3695 }
3696
3697 static int
3698 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3699 {
3700         struct hns3_adapter *hns = dev->data->dev_private;
3701         struct hns3_hw *hw = &hns->hw;
3702         int ret;
3703
3704         rte_spinlock_lock(&hw->lock);
3705         ret = hns3_set_promisc_mode(hw, true, true);
3706         rte_spinlock_unlock(&hw->lock);
3707         if (ret)
3708                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3709                          ret);
3710
3711         return ret;
3712 }
3713
3714 static int
3715 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3716 {
3717         bool allmulti = dev->data->all_multicast ? true : false;
3718         struct hns3_adapter *hns = dev->data->dev_private;
3719         struct hns3_hw *hw = &hns->hw;
3720         int ret;
3721
3722         /* If now in all_multicast mode, must remain in all_multicast mode. */
3723         rte_spinlock_lock(&hw->lock);
3724         ret = hns3_set_promisc_mode(hw, false, allmulti);
3725         rte_spinlock_unlock(&hw->lock);
3726         if (ret)
3727                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3728                          ret);
3729
3730         return ret;
3731 }
3732
3733 static int
3734 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3735 {
3736         struct hns3_adapter *hns = dev->data->dev_private;
3737         struct hns3_hw *hw = &hns->hw;
3738         int ret;
3739
3740         if (dev->data->promiscuous)
3741                 return 0;
3742
3743         rte_spinlock_lock(&hw->lock);
3744         ret = hns3_set_promisc_mode(hw, false, true);
3745         rte_spinlock_unlock(&hw->lock);
3746         if (ret)
3747                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3748                          ret);
3749
3750         return ret;
3751 }
3752
3753 static int
3754 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3755 {
3756         struct hns3_adapter *hns = dev->data->dev_private;
3757         struct hns3_hw *hw = &hns->hw;
3758         int ret;
3759
3760         /* If now in promiscuous mode, must remain in all_multicast mode. */
3761         if (dev->data->promiscuous)
3762                 return 0;
3763
3764         rte_spinlock_lock(&hw->lock);
3765         ret = hns3_set_promisc_mode(hw, false, false);
3766         rte_spinlock_unlock(&hw->lock);
3767         if (ret)
3768                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3769                          ret);
3770
3771         return ret;
3772 }
3773
3774 static int
3775 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3776 {
3777         struct hns3_hw *hw = &hns->hw;
3778         bool allmulti = hw->data->all_multicast ? true : false;
3779
3780         if (hw->data->promiscuous)
3781                 return hns3_set_promisc_mode(hw, true, true);
3782
3783         return hns3_set_promisc_mode(hw, false, allmulti);
3784 }
3785
3786 static int
3787 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3788 {
3789         struct hns3_sfp_speed_cmd *resp;
3790         struct hns3_cmd_desc desc;
3791         int ret;
3792
3793         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3794         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3795         ret = hns3_cmd_send(hw, &desc, 1);
3796         if (ret == -EOPNOTSUPP) {
3797                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3798                 return ret;
3799         } else if (ret) {
3800                 hns3_err(hw, "get sfp speed failed %d", ret);
3801                 return ret;
3802         }
3803
3804         *speed = resp->sfp_speed;
3805
3806         return 0;
3807 }
3808
3809 static uint8_t
3810 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3811 {
3812         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3813                 duplex = ETH_LINK_FULL_DUPLEX;
3814
3815         return duplex;
3816 }
3817
3818 static int
3819 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3820 {
3821         struct hns3_mac *mac = &hw->mac;
3822         int ret;
3823
3824         duplex = hns3_check_speed_dup(duplex, speed);
3825         if (mac->link_speed == speed && mac->link_duplex == duplex)
3826                 return 0;
3827
3828         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3829         if (ret)
3830                 return ret;
3831
3832         mac->link_speed = speed;
3833         mac->link_duplex = duplex;
3834
3835         return 0;
3836 }
3837
3838 static int
3839 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3840 {
3841         struct hns3_adapter *hns = eth_dev->data->dev_private;
3842         struct hns3_hw *hw = &hns->hw;
3843         struct hns3_pf *pf = &hns->pf;
3844         uint32_t speed;
3845         int ret;
3846
3847         /* If IMP do not support get SFP/qSFP speed, return directly */
3848         if (!pf->support_sfp_query)
3849                 return 0;
3850
3851         ret = hns3_get_sfp_speed(hw, &speed);
3852         if (ret == -EOPNOTSUPP) {
3853                 pf->support_sfp_query = false;
3854                 return ret;
3855         } else if (ret)
3856                 return ret;
3857
3858         if (speed == ETH_SPEED_NUM_NONE)
3859                 return 0; /* do nothing if no SFP */
3860
3861         /* Config full duplex for SFP */
3862         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3863 }
3864
3865 static int
3866 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3867 {
3868         struct hns3_config_mac_mode_cmd *req;
3869         struct hns3_cmd_desc desc;
3870         uint32_t loop_en = 0;
3871         uint8_t val = 0;
3872         int ret;
3873
3874         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3875
3876         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3877         if (enable)
3878                 val = 1;
3879         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3880         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3881         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3882         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3883         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3884         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3885         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3886         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3887         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3888         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3889         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3890         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3891         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3892         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3893         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3894
3895         ret = hns3_cmd_send(hw, &desc, 1);
3896         if (ret)
3897                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3898
3899         return ret;
3900 }
3901
3902 static int
3903 hns3_get_mac_link_status(struct hns3_hw *hw)
3904 {
3905         struct hns3_link_status_cmd *req;
3906         struct hns3_cmd_desc desc;
3907         int link_status;
3908         int ret;
3909
3910         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3911         ret = hns3_cmd_send(hw, &desc, 1);
3912         if (ret) {
3913                 hns3_err(hw, "get link status cmd failed %d", ret);
3914                 return ETH_LINK_DOWN;
3915         }
3916
3917         req = (struct hns3_link_status_cmd *)desc.data;
3918         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3919
3920         return !!link_status;
3921 }
3922
3923 void
3924 hns3_update_link_status(struct hns3_hw *hw)
3925 {
3926         int state;
3927
3928         state = hns3_get_mac_link_status(hw);
3929         if (state != hw->mac.link_status) {
3930                 hw->mac.link_status = state;
3931                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3932         }
3933 }
3934
3935 static void
3936 hns3_service_handler(void *param)
3937 {
3938         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3939         struct hns3_adapter *hns = eth_dev->data->dev_private;
3940         struct hns3_hw *hw = &hns->hw;
3941
3942         if (!hns3_is_reset_pending(hns)) {
3943                 hns3_update_speed_duplex(eth_dev);
3944                 hns3_update_link_status(hw);
3945         } else
3946                 hns3_warn(hw, "Cancel the query when reset is pending");
3947
3948         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3949 }
3950
3951 static int
3952 hns3_init_hardware(struct hns3_adapter *hns)
3953 {
3954         struct hns3_hw *hw = &hns->hw;
3955         int ret;
3956
3957         ret = hns3_map_tqp(hw);
3958         if (ret) {
3959                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3960                 return ret;
3961         }
3962
3963         ret = hns3_init_umv_space(hw);
3964         if (ret) {
3965                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3966                 return ret;
3967         }
3968
3969         ret = hns3_mac_init(hw);
3970         if (ret) {
3971                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3972                 goto err_mac_init;
3973         }
3974
3975         ret = hns3_init_mgr_tbl(hw);
3976         if (ret) {
3977                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3978                 goto err_mac_init;
3979         }
3980
3981         ret = hns3_set_promisc_mode(hw, false, false);
3982         if (ret) {
3983                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3984                 goto err_mac_init;
3985         }
3986
3987         ret = hns3_clear_all_vfs_promisc_mode(hw);
3988         if (ret) {
3989                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3990                              ret);
3991                 goto err_mac_init;
3992         }
3993
3994         ret = hns3_init_vlan_config(hns);
3995         if (ret) {
3996                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3997                 goto err_mac_init;
3998         }
3999
4000         ret = hns3_dcb_init(hw);
4001         if (ret) {
4002                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4003                 goto err_mac_init;
4004         }
4005
4006         ret = hns3_init_fd_config(hns);
4007         if (ret) {
4008                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4009                 goto err_mac_init;
4010         }
4011
4012         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4013         if (ret) {
4014                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4015                 goto err_mac_init;
4016         }
4017
4018         ret = hns3_config_gro(hw, false);
4019         if (ret) {
4020                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4021                 goto err_mac_init;
4022         }
4023         return 0;
4024
4025 err_mac_init:
4026         hns3_uninit_umv_space(hw);
4027         return ret;
4028 }
4029
4030 static int
4031 hns3_init_pf(struct rte_eth_dev *eth_dev)
4032 {
4033         struct rte_device *dev = eth_dev->device;
4034         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4035         struct hns3_adapter *hns = eth_dev->data->dev_private;
4036         struct hns3_hw *hw = &hns->hw;
4037         int ret;
4038
4039         PMD_INIT_FUNC_TRACE();
4040
4041         /* Get hardware io base address from pcie BAR2 IO space */
4042         hw->io_base = pci_dev->mem_resource[2].addr;
4043
4044         /* Firmware command queue initialize */
4045         ret = hns3_cmd_init_queue(hw);
4046         if (ret) {
4047                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4048                 goto err_cmd_init_queue;
4049         }
4050
4051         hns3_clear_all_event_cause(hw);
4052
4053         /* Firmware command initialize */
4054         ret = hns3_cmd_init(hw);
4055         if (ret) {
4056                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4057                 goto err_cmd_init;
4058         }
4059
4060         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4061                                          hns3_interrupt_handler,
4062                                          eth_dev);
4063         if (ret) {
4064                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4065                 goto err_intr_callback_register;
4066         }
4067
4068         /* Enable interrupt */
4069         rte_intr_enable(&pci_dev->intr_handle);
4070         hns3_pf_enable_irq0(hw);
4071
4072         /* Get configuration */
4073         ret = hns3_get_configuration(hw);
4074         if (ret) {
4075                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4076                 goto err_get_config;
4077         }
4078
4079         ret = hns3_init_hardware(hns);
4080         if (ret) {
4081                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4082                 goto err_get_config;
4083         }
4084
4085         /* Initialize flow director filter list & hash */
4086         ret = hns3_fdir_filter_init(hns);
4087         if (ret) {
4088                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4089                 goto err_hw_init;
4090         }
4091
4092         hns3_set_default_rss_args(hw);
4093
4094         ret = hns3_enable_hw_error_intr(hns, true);
4095         if (ret) {
4096                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4097                              ret);
4098                 goto err_fdir;
4099         }
4100
4101         /*
4102          * In the initialization clearing the all hardware mapping relationship
4103          * configurations between queues and interrupt vectors is needed, so
4104          * some error caused by the residual configurations, such as the
4105          * unexpected interrupt, can be avoid.
4106          */
4107         ret = hns3_init_ring_with_vector(hw);
4108         if (ret)
4109                 goto err_fdir;
4110
4111         return 0;
4112
4113 err_fdir:
4114         hns3_fdir_filter_uninit(hns);
4115 err_hw_init:
4116         hns3_uninit_umv_space(hw);
4117
4118 err_get_config:
4119         hns3_pf_disable_irq0(hw);
4120         rte_intr_disable(&pci_dev->intr_handle);
4121         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4122                              eth_dev);
4123
4124 err_intr_callback_register:
4125         hns3_cmd_uninit(hw);
4126
4127 err_cmd_init:
4128         hns3_cmd_destroy_queue(hw);
4129
4130 err_cmd_init_queue:
4131         hw->io_base = NULL;
4132
4133         return ret;
4134 }
4135
4136 static void
4137 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4138 {
4139         struct hns3_adapter *hns = eth_dev->data->dev_private;
4140         struct rte_device *dev = eth_dev->device;
4141         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4142         struct hns3_hw *hw = &hns->hw;
4143
4144         PMD_INIT_FUNC_TRACE();
4145
4146         hns3_enable_hw_error_intr(hns, false);
4147         hns3_rss_uninit(hns);
4148         hns3_fdir_filter_uninit(hns);
4149         hns3_uninit_umv_space(hw);
4150         hns3_pf_disable_irq0(hw);
4151         rte_intr_disable(&pci_dev->intr_handle);
4152         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4153                              eth_dev);
4154         hns3_cmd_uninit(hw);
4155         hns3_cmd_destroy_queue(hw);
4156         hw->io_base = NULL;
4157 }
4158
4159 static int
4160 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4161 {
4162         struct hns3_hw *hw = &hns->hw;
4163         int ret;
4164
4165         ret = hns3_dcb_cfg_update(hns);
4166         if (ret)
4167                 return ret;
4168
4169         /* Enable queues */
4170         ret = hns3_start_queues(hns, reset_queue);
4171         if (ret) {
4172                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4173                 return ret;
4174         }
4175
4176         /* Enable MAC */
4177         ret = hns3_cfg_mac_mode(hw, true);
4178         if (ret) {
4179                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4180                 goto err_config_mac_mode;
4181         }
4182         return 0;
4183
4184 err_config_mac_mode:
4185         hns3_stop_queues(hns, true);
4186         return ret;
4187 }
4188
4189 static int
4190 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4191 {
4192         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4193         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4194         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4195         uint32_t intr_vector;
4196         uint8_t base = 0;
4197         uint8_t vec = 0;
4198         uint16_t q_id;
4199         int ret;
4200
4201         if (dev->data->dev_conf.intr_conf.rxq == 0)
4202                 return 0;
4203
4204         /* disable uio/vfio intr/eventfd mapping */
4205         rte_intr_disable(intr_handle);
4206
4207         /* check and configure queue intr-vector mapping */
4208         if (rte_intr_cap_multiple(intr_handle) ||
4209             !RTE_ETH_DEV_SRIOV(dev).active) {
4210                 intr_vector = hw->used_rx_queues;
4211                 /* creates event fd for each intr vector when MSIX is used */
4212                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4213                         return -EINVAL;
4214         }
4215         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4216                 intr_handle->intr_vec =
4217                         rte_zmalloc("intr_vec",
4218                                     hw->used_rx_queues * sizeof(int), 0);
4219                 if (intr_handle->intr_vec == NULL) {
4220                         hns3_err(hw, "Failed to allocate %d rx_queues"
4221                                      " intr_vec", hw->used_rx_queues);
4222                         ret = -ENOMEM;
4223                         goto alloc_intr_vec_error;
4224                 }
4225         }
4226
4227         if (rte_intr_allow_others(intr_handle)) {
4228                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4229                 base = RTE_INTR_VEC_RXTX_OFFSET;
4230         }
4231         if (rte_intr_dp_is_en(intr_handle)) {
4232                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4233                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4234                                                          HNS3_RING_TYPE_RX,
4235                                                          q_id);
4236                         if (ret)
4237                                 goto bind_vector_error;
4238                         intr_handle->intr_vec[q_id] = vec;
4239                         if (vec < base + intr_handle->nb_efd - 1)
4240                                 vec++;
4241                 }
4242         }
4243         rte_intr_enable(intr_handle);
4244         return 0;
4245
4246 bind_vector_error:
4247         rte_intr_efd_disable(intr_handle);
4248         if (intr_handle->intr_vec) {
4249                 free(intr_handle->intr_vec);
4250                 intr_handle->intr_vec = NULL;
4251         }
4252         return ret;
4253 alloc_intr_vec_error:
4254         rte_intr_efd_disable(intr_handle);
4255         return ret;
4256 }
4257
4258 static int
4259 hns3_dev_start(struct rte_eth_dev *dev)
4260 {
4261         struct hns3_adapter *hns = dev->data->dev_private;
4262         struct hns3_hw *hw = &hns->hw;
4263         int ret;
4264
4265         PMD_INIT_FUNC_TRACE();
4266         if (rte_atomic16_read(&hw->reset.resetting))
4267                 return -EBUSY;
4268
4269         rte_spinlock_lock(&hw->lock);
4270         hw->adapter_state = HNS3_NIC_STARTING;
4271
4272         ret = hns3_do_start(hns, true);
4273         if (ret) {
4274                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4275                 rte_spinlock_unlock(&hw->lock);
4276                 return ret;
4277         }
4278
4279         hw->adapter_state = HNS3_NIC_STARTED;
4280         rte_spinlock_unlock(&hw->lock);
4281
4282         ret = hns3_map_rx_interrupt(dev);
4283         if (ret)
4284                 return ret;
4285         hns3_set_rxtx_function(dev);
4286         hns3_mp_req_start_rxtx(dev);
4287         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4288
4289         hns3_info(hw, "hns3 dev start successful!");
4290         return 0;
4291 }
4292
4293 static int
4294 hns3_do_stop(struct hns3_adapter *hns)
4295 {
4296         struct hns3_hw *hw = &hns->hw;
4297         bool reset_queue;
4298         int ret;
4299
4300         ret = hns3_cfg_mac_mode(hw, false);
4301         if (ret)
4302                 return ret;
4303         hw->mac.link_status = ETH_LINK_DOWN;
4304
4305         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4306                 hns3_configure_all_mac_addr(hns, true);
4307                 reset_queue = true;
4308         } else
4309                 reset_queue = false;
4310         hw->mac.default_addr_setted = false;
4311         return hns3_stop_queues(hns, reset_queue);
4312 }
4313
4314 static void
4315 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4316 {
4317         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4319         struct hns3_adapter *hns = dev->data->dev_private;
4320         struct hns3_hw *hw = &hns->hw;
4321         uint8_t base = 0;
4322         uint8_t vec = 0;
4323         uint16_t q_id;
4324
4325         if (dev->data->dev_conf.intr_conf.rxq == 0)
4326                 return;
4327
4328         /* unmap the ring with vector */
4329         if (rte_intr_allow_others(intr_handle)) {
4330                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4331                 base = RTE_INTR_VEC_RXTX_OFFSET;
4332         }
4333         if (rte_intr_dp_is_en(intr_handle)) {
4334                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4335                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4336                                                          HNS3_RING_TYPE_RX,
4337                                                          q_id);
4338                         if (vec < base + intr_handle->nb_efd - 1)
4339                                 vec++;
4340                 }
4341         }
4342         /* Clean datapath event and queue/vec mapping */
4343         rte_intr_efd_disable(intr_handle);
4344         if (intr_handle->intr_vec) {
4345                 rte_free(intr_handle->intr_vec);
4346                 intr_handle->intr_vec = NULL;
4347         }
4348 }
4349
4350 static void
4351 hns3_dev_stop(struct rte_eth_dev *dev)
4352 {
4353         struct hns3_adapter *hns = dev->data->dev_private;
4354         struct hns3_hw *hw = &hns->hw;
4355
4356         PMD_INIT_FUNC_TRACE();
4357
4358         hw->adapter_state = HNS3_NIC_STOPPING;
4359         hns3_set_rxtx_function(dev);
4360         rte_wmb();
4361         /* Disable datapath on secondary process. */
4362         hns3_mp_req_stop_rxtx(dev);
4363         /* Prevent crashes when queues are still in use. */
4364         rte_delay_ms(hw->tqps_num);
4365
4366         rte_spinlock_lock(&hw->lock);
4367         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4368                 hns3_do_stop(hns);
4369                 hns3_dev_release_mbufs(hns);
4370                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4371         }
4372         rte_eal_alarm_cancel(hns3_service_handler, dev);
4373         rte_spinlock_unlock(&hw->lock);
4374         hns3_unmap_rx_interrupt(dev);
4375 }
4376
4377 static void
4378 hns3_dev_close(struct rte_eth_dev *eth_dev)
4379 {
4380         struct hns3_adapter *hns = eth_dev->data->dev_private;
4381         struct hns3_hw *hw = &hns->hw;
4382
4383         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4384                 rte_free(eth_dev->process_private);
4385                 eth_dev->process_private = NULL;
4386                 return;
4387         }
4388
4389         if (hw->adapter_state == HNS3_NIC_STARTED)
4390                 hns3_dev_stop(eth_dev);
4391
4392         hw->adapter_state = HNS3_NIC_CLOSING;
4393         hns3_reset_abort(hns);
4394         hw->adapter_state = HNS3_NIC_CLOSED;
4395
4396         hns3_configure_all_mc_mac_addr(hns, true);
4397         hns3_remove_all_vlan_table(hns);
4398         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4399         hns3_uninit_pf(eth_dev);
4400         hns3_free_all_queues(eth_dev);
4401         rte_free(hw->reset.wait_data);
4402         rte_free(eth_dev->process_private);
4403         eth_dev->process_private = NULL;
4404         hns3_mp_uninit_primary();
4405         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4406 }
4407
4408 static int
4409 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4410 {
4411         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4413
4414         fc_conf->pause_time = pf->pause_time;
4415
4416         /* return fc current mode */
4417         switch (hw->current_mode) {
4418         case HNS3_FC_FULL:
4419                 fc_conf->mode = RTE_FC_FULL;
4420                 break;
4421         case HNS3_FC_TX_PAUSE:
4422                 fc_conf->mode = RTE_FC_TX_PAUSE;
4423                 break;
4424         case HNS3_FC_RX_PAUSE:
4425                 fc_conf->mode = RTE_FC_RX_PAUSE;
4426                 break;
4427         case HNS3_FC_NONE:
4428         default:
4429                 fc_conf->mode = RTE_FC_NONE;
4430                 break;
4431         }
4432
4433         return 0;
4434 }
4435
4436 static void
4437 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4438 {
4439         switch (mode) {
4440         case RTE_FC_NONE:
4441                 hw->requested_mode = HNS3_FC_NONE;
4442                 break;
4443         case RTE_FC_RX_PAUSE:
4444                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4445                 break;
4446         case RTE_FC_TX_PAUSE:
4447                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4448                 break;
4449         case RTE_FC_FULL:
4450                 hw->requested_mode = HNS3_FC_FULL;
4451                 break;
4452         default:
4453                 hw->requested_mode = HNS3_FC_NONE;
4454                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4455                           "configured to RTE_FC_NONE", mode);
4456                 break;
4457         }
4458 }
4459
4460 static int
4461 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4462 {
4463         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4465         int ret;
4466
4467         if (fc_conf->high_water || fc_conf->low_water ||
4468             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4469                 hns3_err(hw, "Unsupported flow control settings specified, "
4470                          "high_water(%u), low_water(%u), send_xon(%u) and "
4471                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4472                          fc_conf->high_water, fc_conf->low_water,
4473                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4474                 return -EINVAL;
4475         }
4476         if (fc_conf->autoneg) {
4477                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4478                 return -EINVAL;
4479         }
4480         if (!fc_conf->pause_time) {
4481                 hns3_err(hw, "Invalid pause time %d setting.",
4482                          fc_conf->pause_time);
4483                 return -EINVAL;
4484         }
4485
4486         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4487             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4488                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4489                          "current_fc_status = %d", hw->current_fc_status);
4490                 return -EOPNOTSUPP;
4491         }
4492
4493         hns3_get_fc_mode(hw, fc_conf->mode);
4494         if (hw->requested_mode == hw->current_mode &&
4495             pf->pause_time == fc_conf->pause_time)
4496                 return 0;
4497
4498         rte_spinlock_lock(&hw->lock);
4499         ret = hns3_fc_enable(dev, fc_conf);
4500         rte_spinlock_unlock(&hw->lock);
4501
4502         return ret;
4503 }
4504
4505 static int
4506 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4507                             struct rte_eth_pfc_conf *pfc_conf)
4508 {
4509         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4511         uint8_t priority;
4512         int ret;
4513
4514         if (!hns3_dev_dcb_supported(hw)) {
4515                 hns3_err(hw, "This port does not support dcb configurations.");
4516                 return -EOPNOTSUPP;
4517         }
4518
4519         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4520             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4521                 hns3_err(hw, "Unsupported flow control settings specified, "
4522                          "high_water(%u), low_water(%u), send_xon(%u) and "
4523                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4524                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4525                          pfc_conf->fc.send_xon,
4526                          pfc_conf->fc.mac_ctrl_frame_fwd);
4527                 return -EINVAL;
4528         }
4529         if (pfc_conf->fc.autoneg) {
4530                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4531                 return -EINVAL;
4532         }
4533         if (pfc_conf->fc.pause_time == 0) {
4534                 hns3_err(hw, "Invalid pause time %d setting.",
4535                          pfc_conf->fc.pause_time);
4536                 return -EINVAL;
4537         }
4538
4539         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4540             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4541                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4542                              "current_fc_status = %d", hw->current_fc_status);
4543                 return -EOPNOTSUPP;
4544         }
4545
4546         priority = pfc_conf->priority;
4547         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4548         if (hw->dcb_info.pfc_en & BIT(priority) &&
4549             hw->requested_mode == hw->current_mode &&
4550             pfc_conf->fc.pause_time == pf->pause_time)
4551                 return 0;
4552
4553         rte_spinlock_lock(&hw->lock);
4554         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4555         rte_spinlock_unlock(&hw->lock);
4556
4557         return ret;
4558 }
4559
4560 static int
4561 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4562 {
4563         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4565         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4566         int i;
4567
4568         rte_spinlock_lock(&hw->lock);
4569         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4570                 dcb_info->nb_tcs = pf->local_max_tc;
4571         else
4572                 dcb_info->nb_tcs = 1;
4573
4574         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4575                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4576         for (i = 0; i < dcb_info->nb_tcs; i++)
4577                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4578
4579         for (i = 0; i < hw->num_tc; i++) {
4580                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4581                 dcb_info->tc_queue.tc_txq[0][i].base =
4582                                                 hw->tc_queue[i].tqp_offset;
4583                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4584                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4585                                                 hw->tc_queue[i].tqp_count;
4586         }
4587         rte_spinlock_unlock(&hw->lock);
4588
4589         return 0;
4590 }
4591
4592 static int
4593 hns3_reinit_dev(struct hns3_adapter *hns)
4594 {
4595         struct hns3_hw *hw = &hns->hw;
4596         int ret;
4597
4598         ret = hns3_cmd_init(hw);
4599         if (ret) {
4600                 hns3_err(hw, "Failed to init cmd: %d", ret);
4601                 return ret;
4602         }
4603
4604         ret = hns3_reset_all_queues(hns);
4605         if (ret) {
4606                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4607                 goto err_init;
4608         }
4609
4610         ret = hns3_init_hardware(hns);
4611         if (ret) {
4612                 hns3_err(hw, "Failed to init hardware: %d", ret);
4613                 goto err_init;
4614         }
4615
4616         ret = hns3_enable_hw_error_intr(hns, true);
4617         if (ret) {
4618                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4619                              ret);
4620                 goto err_mac_init;
4621         }
4622         hns3_info(hw, "Reset done, driver initialization finished.");
4623
4624         return 0;
4625
4626 err_mac_init:
4627         hns3_uninit_umv_space(hw);
4628 err_init:
4629         hns3_cmd_uninit(hw);
4630
4631         return ret;
4632 }
4633
4634 static bool
4635 is_pf_reset_done(struct hns3_hw *hw)
4636 {
4637         uint32_t val, reg, reg_bit;
4638
4639         switch (hw->reset.level) {
4640         case HNS3_IMP_RESET:
4641                 reg = HNS3_GLOBAL_RESET_REG;
4642                 reg_bit = HNS3_IMP_RESET_BIT;
4643                 break;
4644         case HNS3_GLOBAL_RESET:
4645                 reg = HNS3_GLOBAL_RESET_REG;
4646                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4647                 break;
4648         case HNS3_FUNC_RESET:
4649                 reg = HNS3_FUN_RST_ING;
4650                 reg_bit = HNS3_FUN_RST_ING_B;
4651                 break;
4652         case HNS3_FLR_RESET:
4653         default:
4654                 hns3_err(hw, "Wait for unsupported reset level: %d",
4655                          hw->reset.level);
4656                 return true;
4657         }
4658         val = hns3_read_dev(hw, reg);
4659         if (hns3_get_bit(val, reg_bit))
4660                 return false;
4661         else
4662                 return true;
4663 }
4664
4665 bool
4666 hns3_is_reset_pending(struct hns3_adapter *hns)
4667 {
4668         struct hns3_hw *hw = &hns->hw;
4669         enum hns3_reset_level reset;
4670
4671         hns3_check_event_cause(hns, NULL);
4672         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4673         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4674                 hns3_warn(hw, "High level reset %d is pending", reset);
4675                 return true;
4676         }
4677         reset = hns3_get_reset_level(hns, &hw->reset.request);
4678         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4679                 hns3_warn(hw, "High level reset %d is request", reset);
4680                 return true;
4681         }
4682         return false;
4683 }
4684
4685 static int
4686 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4687 {
4688         struct hns3_hw *hw = &hns->hw;
4689         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4690         struct timeval tv;
4691
4692         if (wait_data->result == HNS3_WAIT_SUCCESS)
4693                 return 0;
4694         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4695                 gettimeofday(&tv, NULL);
4696                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4697                           tv.tv_sec, tv.tv_usec);
4698                 return -ETIME;
4699         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4700                 return -EAGAIN;
4701
4702         wait_data->hns = hns;
4703         wait_data->check_completion = is_pf_reset_done;
4704         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4705                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4706         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4707         wait_data->count = HNS3_RESET_WAIT_CNT;
4708         wait_data->result = HNS3_WAIT_REQUEST;
4709         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4710         return -EAGAIN;
4711 }
4712
4713 static int
4714 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4715 {
4716         struct hns3_cmd_desc desc;
4717         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4718
4719         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4720         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4721         req->fun_reset_vfid = func_id;
4722
4723         return hns3_cmd_send(hw, &desc, 1);
4724 }
4725
4726 static int
4727 hns3_imp_reset_cmd(struct hns3_hw *hw)
4728 {
4729         struct hns3_cmd_desc desc;
4730
4731         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4732         desc.data[0] = 0xeedd;
4733
4734         return hns3_cmd_send(hw, &desc, 1);
4735 }
4736
4737 static void
4738 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4739 {
4740         struct hns3_hw *hw = &hns->hw;
4741         struct timeval tv;
4742         uint32_t val;
4743
4744         gettimeofday(&tv, NULL);
4745         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4746             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4747                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4748                           tv.tv_sec, tv.tv_usec);
4749                 return;
4750         }
4751
4752         switch (reset_level) {
4753         case HNS3_IMP_RESET:
4754                 hns3_imp_reset_cmd(hw);
4755                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4756                           tv.tv_sec, tv.tv_usec);
4757                 break;
4758         case HNS3_GLOBAL_RESET:
4759                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4760                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4761                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4762                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4763                           tv.tv_sec, tv.tv_usec);
4764                 break;
4765         case HNS3_FUNC_RESET:
4766                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4767                           tv.tv_sec, tv.tv_usec);
4768                 /* schedule again to check later */
4769                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4770                 hns3_schedule_reset(hns);
4771                 break;
4772         default:
4773                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4774                 return;
4775         }
4776         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4777 }
4778
4779 static enum hns3_reset_level
4780 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4781 {
4782         struct hns3_hw *hw = &hns->hw;
4783         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4784
4785         /* Return the highest priority reset level amongst all */
4786         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4787                 reset_level = HNS3_IMP_RESET;
4788         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4789                 reset_level = HNS3_GLOBAL_RESET;
4790         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4791                 reset_level = HNS3_FUNC_RESET;
4792         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4793                 reset_level = HNS3_FLR_RESET;
4794
4795         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4796                 return HNS3_NONE_RESET;
4797
4798         return reset_level;
4799 }
4800
4801 static int
4802 hns3_prepare_reset(struct hns3_adapter *hns)
4803 {
4804         struct hns3_hw *hw = &hns->hw;
4805         uint32_t reg_val;
4806         int ret;
4807
4808         switch (hw->reset.level) {
4809         case HNS3_FUNC_RESET:
4810                 ret = hns3_func_reset_cmd(hw, 0);
4811                 if (ret)
4812                         return ret;
4813
4814                 /*
4815                  * After performaning pf reset, it is not necessary to do the
4816                  * mailbox handling or send any command to firmware, because
4817                  * any mailbox handling or command to firmware is only valid
4818                  * after hns3_cmd_init is called.
4819                  */
4820                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4821                 hw->reset.stats.request_cnt++;
4822                 break;
4823         case HNS3_IMP_RESET:
4824                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4825                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4826                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4827                 break;
4828         default:
4829                 break;
4830         }
4831         return 0;
4832 }
4833
4834 static int
4835 hns3_set_rst_done(struct hns3_hw *hw)
4836 {
4837         struct hns3_pf_rst_done_cmd *req;
4838         struct hns3_cmd_desc desc;
4839
4840         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4841         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4842         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4843         return hns3_cmd_send(hw, &desc, 1);
4844 }
4845
4846 static int
4847 hns3_stop_service(struct hns3_adapter *hns)
4848 {
4849         struct hns3_hw *hw = &hns->hw;
4850         struct rte_eth_dev *eth_dev;
4851
4852         eth_dev = &rte_eth_devices[hw->data->port_id];
4853         if (hw->adapter_state == HNS3_NIC_STARTED)
4854                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4855         hw->mac.link_status = ETH_LINK_DOWN;
4856
4857         hns3_set_rxtx_function(eth_dev);
4858         rte_wmb();
4859         /* Disable datapath on secondary process. */
4860         hns3_mp_req_stop_rxtx(eth_dev);
4861         rte_delay_ms(hw->tqps_num);
4862
4863         rte_spinlock_lock(&hw->lock);
4864         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4865             hw->adapter_state == HNS3_NIC_STOPPING) {
4866                 hns3_do_stop(hns);
4867                 hw->reset.mbuf_deferred_free = true;
4868         } else
4869                 hw->reset.mbuf_deferred_free = false;
4870
4871         /*
4872          * It is cumbersome for hardware to pick-and-choose entries for deletion
4873          * from table space. Hence, for function reset software intervention is
4874          * required to delete the entries
4875          */
4876         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4877                 hns3_configure_all_mc_mac_addr(hns, true);
4878         rte_spinlock_unlock(&hw->lock);
4879
4880         return 0;
4881 }
4882
4883 static int
4884 hns3_start_service(struct hns3_adapter *hns)
4885 {
4886         struct hns3_hw *hw = &hns->hw;
4887         struct rte_eth_dev *eth_dev;
4888
4889         if (hw->reset.level == HNS3_IMP_RESET ||
4890             hw->reset.level == HNS3_GLOBAL_RESET)
4891                 hns3_set_rst_done(hw);
4892         eth_dev = &rte_eth_devices[hw->data->port_id];
4893         hns3_set_rxtx_function(eth_dev);
4894         hns3_mp_req_start_rxtx(eth_dev);
4895         if (hw->adapter_state == HNS3_NIC_STARTED)
4896                 hns3_service_handler(eth_dev);
4897
4898         return 0;
4899 }
4900
4901 static int
4902 hns3_restore_conf(struct hns3_adapter *hns)
4903 {
4904         struct hns3_hw *hw = &hns->hw;
4905         int ret;
4906
4907         ret = hns3_configure_all_mac_addr(hns, false);
4908         if (ret)
4909                 return ret;
4910
4911         ret = hns3_configure_all_mc_mac_addr(hns, false);
4912         if (ret)
4913                 goto err_mc_mac;
4914
4915         ret = hns3_dev_promisc_restore(hns);
4916         if (ret)
4917                 goto err_promisc;
4918
4919         ret = hns3_restore_vlan_table(hns);
4920         if (ret)
4921                 goto err_promisc;
4922
4923         ret = hns3_restore_vlan_conf(hns);
4924         if (ret)
4925                 goto err_promisc;
4926
4927         ret = hns3_restore_all_fdir_filter(hns);
4928         if (ret)
4929                 goto err_promisc;
4930
4931         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4932                 ret = hns3_do_start(hns, false);
4933                 if (ret)
4934                         goto err_promisc;
4935                 hns3_info(hw, "hns3 dev restart successful!");
4936         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4937                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4938         return 0;
4939
4940 err_promisc:
4941         hns3_configure_all_mc_mac_addr(hns, true);
4942 err_mc_mac:
4943         hns3_configure_all_mac_addr(hns, true);
4944         return ret;
4945 }
4946
4947 static void
4948 hns3_reset_service(void *param)
4949 {
4950         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4951         struct hns3_hw *hw = &hns->hw;
4952         enum hns3_reset_level reset_level;
4953         struct timeval tv_delta;
4954         struct timeval tv_start;
4955         struct timeval tv;
4956         uint64_t msec;
4957         int ret;
4958
4959         /*
4960          * The interrupt is not triggered within the delay time.
4961          * The interrupt may have been lost. It is necessary to handle
4962          * the interrupt to recover from the error.
4963          */
4964         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4965                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4966                 hns3_err(hw, "Handling interrupts in delayed tasks");
4967                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4968                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4969                 if (reset_level == HNS3_NONE_RESET) {
4970                         hns3_err(hw, "No reset level is set, try IMP reset");
4971                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4972                 }
4973         }
4974         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4975
4976         /*
4977          * Check if there is any ongoing reset in the hardware. This status can
4978          * be checked from reset_pending. If there is then, we need to wait for
4979          * hardware to complete reset.
4980          *    a. If we are able to figure out in reasonable time that hardware
4981          *       has fully resetted then, we can proceed with driver, client
4982          *       reset.
4983          *    b. else, we can come back later to check this status so re-sched
4984          *       now.
4985          */
4986         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4987         if (reset_level != HNS3_NONE_RESET) {
4988                 gettimeofday(&tv_start, NULL);
4989                 ret = hns3_reset_process(hns, reset_level);
4990                 gettimeofday(&tv, NULL);
4991                 timersub(&tv, &tv_start, &tv_delta);
4992                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4993                        tv_delta.tv_usec / USEC_PER_MSEC;
4994                 if (msec > HNS3_RESET_PROCESS_MS)
4995                         hns3_err(hw, "%d handle long time delta %" PRIx64
4996                                      " ms time=%ld.%.6ld",
4997                                  hw->reset.level, msec,
4998                                  tv.tv_sec, tv.tv_usec);
4999                 if (ret == -EAGAIN)
5000                         return;
5001         }
5002
5003         /* Check if we got any *new* reset requests to be honored */
5004         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5005         if (reset_level != HNS3_NONE_RESET)
5006                 hns3_msix_process(hns, reset_level);
5007 }
5008
5009 static const struct eth_dev_ops hns3_eth_dev_ops = {
5010         .dev_start          = hns3_dev_start,
5011         .dev_stop           = hns3_dev_stop,
5012         .dev_close          = hns3_dev_close,
5013         .promiscuous_enable = hns3_dev_promiscuous_enable,
5014         .promiscuous_disable = hns3_dev_promiscuous_disable,
5015         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5016         .allmulticast_disable = hns3_dev_allmulticast_disable,
5017         .mtu_set            = hns3_dev_mtu_set,
5018         .stats_get          = hns3_stats_get,
5019         .stats_reset        = hns3_stats_reset,
5020         .xstats_get         = hns3_dev_xstats_get,
5021         .xstats_get_names   = hns3_dev_xstats_get_names,
5022         .xstats_reset       = hns3_dev_xstats_reset,
5023         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5024         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5025         .dev_infos_get          = hns3_dev_infos_get,
5026         .fw_version_get         = hns3_fw_version_get,
5027         .rx_queue_setup         = hns3_rx_queue_setup,
5028         .tx_queue_setup         = hns3_tx_queue_setup,
5029         .rx_queue_release       = hns3_dev_rx_queue_release,
5030         .tx_queue_release       = hns3_dev_tx_queue_release,
5031         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5032         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5033         .dev_configure          = hns3_dev_configure,
5034         .flow_ctrl_get          = hns3_flow_ctrl_get,
5035         .flow_ctrl_set          = hns3_flow_ctrl_set,
5036         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5037         .mac_addr_add           = hns3_add_mac_addr,
5038         .mac_addr_remove        = hns3_remove_mac_addr,
5039         .mac_addr_set           = hns3_set_default_mac_addr,
5040         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5041         .link_update            = hns3_dev_link_update,
5042         .rss_hash_update        = hns3_dev_rss_hash_update,
5043         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5044         .reta_update            = hns3_dev_rss_reta_update,
5045         .reta_query             = hns3_dev_rss_reta_query,
5046         .filter_ctrl            = hns3_dev_filter_ctrl,
5047         .vlan_filter_set        = hns3_vlan_filter_set,
5048         .vlan_tpid_set          = hns3_vlan_tpid_set,
5049         .vlan_offload_set       = hns3_vlan_offload_set,
5050         .vlan_pvid_set          = hns3_vlan_pvid_set,
5051         .get_reg                = hns3_get_regs,
5052         .get_dcb_info           = hns3_get_dcb_info,
5053         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5054 };
5055
5056 static const struct hns3_reset_ops hns3_reset_ops = {
5057         .reset_service       = hns3_reset_service,
5058         .stop_service        = hns3_stop_service,
5059         .prepare_reset       = hns3_prepare_reset,
5060         .wait_hardware_ready = hns3_wait_hardware_ready,
5061         .reinit_dev          = hns3_reinit_dev,
5062         .restore_conf        = hns3_restore_conf,
5063         .start_service       = hns3_start_service,
5064 };
5065
5066 static int
5067 hns3_dev_init(struct rte_eth_dev *eth_dev)
5068 {
5069         struct rte_device *dev = eth_dev->device;
5070         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5071         struct hns3_adapter *hns = eth_dev->data->dev_private;
5072         struct hns3_hw *hw = &hns->hw;
5073         uint16_t device_id = pci_dev->id.device_id;
5074         int ret;
5075
5076         PMD_INIT_FUNC_TRACE();
5077         eth_dev->process_private = (struct hns3_process_private *)
5078             rte_zmalloc_socket("hns3_filter_list",
5079                                sizeof(struct hns3_process_private),
5080                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5081         if (eth_dev->process_private == NULL) {
5082                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5083                 return -ENOMEM;
5084         }
5085         /* initialize flow filter lists */
5086         hns3_filterlist_init(eth_dev);
5087
5088         hns3_set_rxtx_function(eth_dev);
5089         eth_dev->dev_ops = &hns3_eth_dev_ops;
5090         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5091                 hns3_mp_init_secondary();
5092                 hw->secondary_cnt++;
5093                 return 0;
5094         }
5095
5096         hns3_mp_init_primary();
5097         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5098
5099         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5100             device_id == HNS3_DEV_ID_50GE_RDMA ||
5101             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5102                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5103
5104         hns->is_vf = false;
5105         hw->data = eth_dev->data;
5106
5107         /*
5108          * Set default max packet size according to the mtu
5109          * default vale in DPDK frame.
5110          */
5111         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5112
5113         ret = hns3_reset_init(hw);
5114         if (ret)
5115                 goto err_init_reset;
5116         hw->reset.ops = &hns3_reset_ops;
5117
5118         ret = hns3_init_pf(eth_dev);
5119         if (ret) {
5120                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5121                 goto err_init_pf;
5122         }
5123
5124         /* Allocate memory for storing MAC addresses */
5125         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5126                                                sizeof(struct rte_ether_addr) *
5127                                                HNS3_UC_MACADDR_NUM, 0);
5128         if (eth_dev->data->mac_addrs == NULL) {
5129                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5130                              "to store MAC addresses",
5131                              sizeof(struct rte_ether_addr) *
5132                              HNS3_UC_MACADDR_NUM);
5133                 ret = -ENOMEM;
5134                 goto err_rte_zmalloc;
5135         }
5136
5137         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5138                             &eth_dev->data->mac_addrs[0]);
5139
5140         hw->adapter_state = HNS3_NIC_INITIALIZED;
5141         /*
5142          * Pass the information to the rte_eth_dev_close() that it should also
5143          * release the private port resources.
5144          */
5145         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5146
5147         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5148                 hns3_err(hw, "Reschedule reset service after dev_init");
5149                 hns3_schedule_reset(hns);
5150         } else {
5151                 /* IMP will wait ready flag before reset */
5152                 hns3_notify_reset_ready(hw, false);
5153         }
5154
5155         hns3_info(hw, "hns3 dev initialization successful!");
5156         return 0;
5157
5158 err_rte_zmalloc:
5159         hns3_uninit_pf(eth_dev);
5160
5161 err_init_pf:
5162         rte_free(hw->reset.wait_data);
5163 err_init_reset:
5164         eth_dev->dev_ops = NULL;
5165         eth_dev->rx_pkt_burst = NULL;
5166         eth_dev->tx_pkt_burst = NULL;
5167         eth_dev->tx_pkt_prepare = NULL;
5168         rte_free(eth_dev->process_private);
5169         eth_dev->process_private = NULL;
5170         return ret;
5171 }
5172
5173 static int
5174 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5175 {
5176         struct hns3_adapter *hns = eth_dev->data->dev_private;
5177         struct hns3_hw *hw = &hns->hw;
5178
5179         PMD_INIT_FUNC_TRACE();
5180
5181         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5182                 return -EPERM;
5183
5184         eth_dev->dev_ops = NULL;
5185         eth_dev->rx_pkt_burst = NULL;
5186         eth_dev->tx_pkt_burst = NULL;
5187         eth_dev->tx_pkt_prepare = NULL;
5188         if (hw->adapter_state < HNS3_NIC_CLOSING)
5189                 hns3_dev_close(eth_dev);
5190
5191         hw->adapter_state = HNS3_NIC_REMOVED;
5192         return 0;
5193 }
5194
5195 static int
5196 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5197                    struct rte_pci_device *pci_dev)
5198 {
5199         return rte_eth_dev_pci_generic_probe(pci_dev,
5200                                              sizeof(struct hns3_adapter),
5201                                              hns3_dev_init);
5202 }
5203
5204 static int
5205 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5206 {
5207         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5208 }
5209
5210 static const struct rte_pci_id pci_id_hns3_map[] = {
5211         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5212         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5213         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5214         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5215         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5216         { .vendor_id = 0, /* sentinel */ },
5217 };
5218
5219 static struct rte_pci_driver rte_hns3_pmd = {
5220         .id_table = pci_id_hns3_map,
5221         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5222         .probe = eth_hns3_pci_probe,
5223         .remove = eth_hns3_pci_remove,
5224 };
5225
5226 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5227 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5228 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5229
5230 RTE_INIT(hns3_init_log)
5231 {
5232         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5233         if (hns3_logtype_init >= 0)
5234                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5235         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5236         if (hns3_logtype_driver >= 0)
5237                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5238 }