drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_INVALID_PVID               0xFFFF
  23
  24 #define HNS3_FILTER_TYPE_VF             0
  25 #define HNS3_FILTER_TYPE_PORT           1
  26 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  27 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  28 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  29 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  30 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  31 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  32                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  33 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  35
  36 /* Reset related Registers */
  37 #define HNS3_GLOBAL_RESET_BIT           0
  38 #define HNS3_CORE_RESET_BIT             1
  39 #define HNS3_IMP_RESET_BIT              2
  40 #define HNS3_FUN_RST_ING_B              0
  41
  42 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  44 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  46
  47 #define HNS3_RESET_WAIT_MS      100
  48 #define HNS3_RESET_WAIT_CNT     200
  49
  50 /* FEC mode order defined in HNS3 hardware */
  51 #define HNS3_HW_FEC_MODE_NOFEC  0
  52 #define HNS3_HW_FEC_MODE_BASER  1
  53 #define HNS3_HW_FEC_MODE_RS     2
  54
  55 enum hns3_evt_cause {
  56         HNS3_VECTOR0_EVENT_RST,
  57         HNS3_VECTOR0_EVENT_MBX,
  58         HNS3_VECTOR0_EVENT_ERR,
  59         HNS3_VECTOR0_EVENT_OTHER,
  60 };
  61
  62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  63         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  64                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  66
  67         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  71
  72         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  75
  76         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  80
  81         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  82                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  84
  85         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  88 };
  89
  90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  91                                                  uint64_t *levels);
  92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  94                                     int on);
  95 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  96
  97 static int hns3_add_mc_addr(struct hns3_hw *hw,
  98                             struct rte_ether_addr *mac_addr);
  99 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_restore_fec(struct hns3_hw *hw);
 102 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 103
 104 void hns3_ether_format_addr(char *buf, uint16_t size,
 105                             const struct rte_ether_addr *ether_addr)
 106 {
 107         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 108                 ether_addr->addr_bytes[0],
 109                 ether_addr->addr_bytes[4],
 110                 ether_addr->addr_bytes[5]);
 111 }
 112
 113 static void
 114 hns3_pf_disable_irq0(struct hns3_hw *hw)
 115 {
 116         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 117 }
 118
 119 static void
 120 hns3_pf_enable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 123 }
 124
 125 static enum hns3_evt_cause
 126 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 127                           uint32_t *vec_val)
 128 {
 129         struct hns3_hw *hw = &hns->hw;
 130
 131         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 132         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 133         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 134         if (!is_delay) {
 135                 hw->reset.stats.imp_cnt++;
 136                 hns3_warn(hw, "IMP reset detected, clear reset status");
 137         } else {
 138                 hns3_schedule_delayed_reset(hns);
 139                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 140         }
 141
 142         return HNS3_VECTOR0_EVENT_RST;
 143 }
 144
 145 static enum hns3_evt_cause
 146 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 147                              uint32_t *vec_val)
 148 {
 149         struct hns3_hw *hw = &hns->hw;
 150
 151         rte_atomic16_set(&hw->reset.disable_cmd, 1);
 152         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 153         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 154         if (!is_delay) {
 155                 hw->reset.stats.global_cnt++;
 156                 hns3_warn(hw, "Global reset detected, clear reset status");
 157         } else {
 158                 hns3_schedule_delayed_reset(hns);
 159                 hns3_warn(hw,
 160                           "Global reset detected, don't clear reset status");
 161         }
 162
 163         return HNS3_VECTOR0_EVENT_RST;
 164 }
 165
 166 static enum hns3_evt_cause
 167 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 168 {
 169         struct hns3_hw *hw = &hns->hw;
 170         uint32_t vector0_int_stats;
 171         uint32_t cmdq_src_val;
 172         uint32_t hw_err_src_reg;
 173         uint32_t val;
 174         enum hns3_evt_cause ret;
 175         bool is_delay;
 176
 177         /* fetch the events from their corresponding regs */
 178         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 179         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 180         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 181
 182         is_delay = clearval == NULL ? true : false;
 183         /*
 184          * Assumption: If by any chance reset and mailbox events are reported
 185          * together then we will only process reset event and defer the
 186          * processing of the mailbox events. Since, we would have not cleared
 187          * RX CMDQ event this time we would receive again another interrupt
 188          * from H/W just for the mailbox.
 189          */
 190         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 191                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 192                 goto out;
 193         }
 194
 195         /* Global reset */
 196         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 197                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 198                 goto out;
 199         }
 200
 201         /* check for vector0 msix event source */
 202         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 203             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 204                 val = vector0_int_stats | hw_err_src_reg;
 205                 ret = HNS3_VECTOR0_EVENT_ERR;
 206                 goto out;
 207         }
 208
 209         /* check for vector0 mailbox(=CMDQ RX) event source */
 210         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 211                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 212                 val = cmdq_src_val;
 213                 ret = HNS3_VECTOR0_EVENT_MBX;
 214                 goto out;
 215         }
 216
 217         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 218                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 219                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 220         val = vector0_int_stats;
 221         ret = HNS3_VECTOR0_EVENT_OTHER;
 222 out:
 223
 224         if (clearval)
 225                 *clearval = val;
 226         return ret;
 227 }
 228
 229 static void
 230 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 231 {
 232         if (event_type == HNS3_VECTOR0_EVENT_RST)
 233                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 234         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 235                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 236 }
 237
 238 static void
 239 hns3_clear_all_event_cause(struct hns3_hw *hw)
 240 {
 241         uint32_t vector0_int_stats;
 242         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 243
 244         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 245                 hns3_warn(hw, "Probe during IMP reset interrupt");
 246
 247         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 248                 hns3_warn(hw, "Probe during Global reset interrupt");
 249
 250         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 251                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 252                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 254         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 255 }
 256
 257 static void
 258 hns3_interrupt_handler(void *param)
 259 {
 260         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 261         struct hns3_adapter *hns = dev->data->dev_private;
 262         struct hns3_hw *hw = &hns->hw;
 263         enum hns3_evt_cause event_cause;
 264         uint32_t clearval = 0;
 265
 266         /* Disable interrupt */
 267         hns3_pf_disable_irq0(hw);
 268
 269         event_cause = hns3_check_event_cause(hns, &clearval);
 270         /* vector 0 interrupt is shared with reset and mailbox source events. */
 271         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 272                 hns3_warn(hw, "Received err interrupt");
 273                 hns3_handle_msix_error(hns, &hw->reset.request);
 274                 hns3_handle_ras_error(hns, &hw->reset.request);
 275                 hns3_schedule_reset(hns);
 276         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 277                 hns3_warn(hw, "Received reset interrupt");
 278                 hns3_schedule_reset(hns);
 279         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 280                 hns3_dev_handle_mbx_msg(hw);
 281         else
 282                 hns3_err(hw, "Received unknown event");
 283
 284         hns3_clear_event_cause(hw, event_cause, clearval);
 285         /* Enable interrupt if it is not cause by reset */
 286         hns3_pf_enable_irq0(hw);
 287 }
 288
 289 static int
 290 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 291 {
 292 #define HNS3_VLAN_ID_OFFSET_STEP        160
 293 #define HNS3_VLAN_BYTE_SIZE             8
 294         struct hns3_vlan_filter_pf_cfg_cmd *req;
 295         struct hns3_hw *hw = &hns->hw;
 296         uint8_t vlan_offset_byte_val;
 297         struct hns3_cmd_desc desc;
 298         uint8_t vlan_offset_byte;
 299         uint8_t vlan_offset_base;
 300         int ret;
 301
 302         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 303
 304         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 305         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 306                            HNS3_VLAN_BYTE_SIZE;
 307         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 308
 309         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 310         req->vlan_offset = vlan_offset_base;
 311         req->vlan_cfg = on ? 0 : 1;
 312         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 313
 314         ret = hns3_cmd_send(hw, &desc, 1);
 315         if (ret)
 316                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 317                          vlan_id, ret);
 318
 319         return ret;
 320 }
 321
 322 static void
 323 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 324 {
 325         struct hns3_user_vlan_table *vlan_entry;
 326         struct hns3_pf *pf = &hns->pf;
 327
 328         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 329                 if (vlan_entry->vlan_id == vlan_id) {
 330                         if (vlan_entry->hd_tbl_status)
 331                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 332                         LIST_REMOVE(vlan_entry, next);
 333                         rte_free(vlan_entry);
 334                         break;
 335                 }
 336         }
 337 }
 338
 339 static void
 340 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 341                         bool writen_to_tbl)
 342 {
 343         struct hns3_user_vlan_table *vlan_entry;
 344         struct hns3_hw *hw = &hns->hw;
 345         struct hns3_pf *pf = &hns->pf;
 346
 347         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 348                 if (vlan_entry->vlan_id == vlan_id)
 349                         return;
 350         }
 351
 352         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 353         if (vlan_entry == NULL) {
 354                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 355                 return;
 356         }
 357
 358         vlan_entry->hd_tbl_status = writen_to_tbl;
 359         vlan_entry->vlan_id = vlan_id;
 360
 361         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 362 }
 363
 364 static int
 365 hns3_restore_vlan_table(struct hns3_adapter *hns)
 366 {
 367         struct hns3_user_vlan_table *vlan_entry;
 368         struct hns3_hw *hw = &hns->hw;
 369         struct hns3_pf *pf = &hns->pf;
 370         uint16_t vlan_id;
 371         int ret = 0;
 372
 373         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 374                 return hns3_vlan_pvid_configure(hns,
 375                                                 hw->port_base_vlan_cfg.pvid, 1);
 376
 377         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 378                 if (vlan_entry->hd_tbl_status) {
 379                         vlan_id = vlan_entry->vlan_id;
 380                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 381                         if (ret)
 382                                 break;
 383                 }
 384         }
 385
 386         return ret;
 387 }
 388
 389 static int
 390 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 391 {
 392         struct hns3_hw *hw = &hns->hw;
 393         bool writen_to_tbl = false;
 394         int ret = 0;
 395
 396         /*
 397          * When vlan filter is enabled, hardware regards packets without vlan
 398          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 399          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 400          */
 401         if (on == 0 && vlan_id == 0)
 402                 return 0;
 403
 404         /*
 405          * When port base vlan enabled, we use port base vlan as the vlan
 406          * filter condition. In this case, we don't update vlan filter table
 407          * when user add new vlan or remove exist vlan, just update the
 408          * vlan list. The vlan id in vlan list will be writen in vlan filter
 409          * table until port base vlan disabled
 410          */
 411         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 412                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 413                 writen_to_tbl = true;
 414         }
 415
 416         if (ret == 0) {
 417                 if (on)
 418                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 419                 else
 420                         hns3_rm_dev_vlan_table(hns, vlan_id);
 421         }
 422         return ret;
 423 }
 424
 425 static int
 426 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 427 {
 428         struct hns3_adapter *hns = dev->data->dev_private;
 429         struct hns3_hw *hw = &hns->hw;
 430         int ret;
 431
 432         rte_spinlock_lock(&hw->lock);
 433         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 434         rte_spinlock_unlock(&hw->lock);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 440                          uint16_t tpid)
 441 {
 442         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 443         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 444         struct hns3_hw *hw = &hns->hw;
 445         struct hns3_cmd_desc desc;
 446         int ret;
 447
 448         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 449              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 450                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 451                 return -EINVAL;
 452         }
 453
 454         if (tpid != RTE_ETHER_TYPE_VLAN) {
 455                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 456                 return -EINVAL;
 457         }
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 460         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 461
 462         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 463                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 464                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 465         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 466                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 467                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 468                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 469                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 470         }
 471
 472         ret = hns3_cmd_send(hw, &desc, 1);
 473         if (ret) {
 474                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 475                          ret);
 476                 return ret;
 477         }
 478
 479         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 480
 481         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 482         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 483         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 488                          ret);
 489         return ret;
 490 }
 491
 492 static int
 493 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 494                    uint16_t tpid)
 495 {
 496         struct hns3_adapter *hns = dev->data->dev_private;
 497         struct hns3_hw *hw = &hns->hw;
 498         int ret;
 499
 500         rte_spinlock_lock(&hw->lock);
 501         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 502         rte_spinlock_unlock(&hw->lock);
 503         return ret;
 504 }
 505
 506 static int
 507 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 508                              struct hns3_rx_vtag_cfg *vcfg)
 509 {
 510         struct hns3_vport_vtag_rx_cfg_cmd *req;
 511         struct hns3_hw *hw = &hns->hw;
 512         struct hns3_cmd_desc desc;
 513         uint16_t vport_id;
 514         uint8_t bitmap;
 515         int ret;
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 518
 519         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 520         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 521                      vcfg->strip_tag1_en ? 1 : 0);
 522         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 523                      vcfg->strip_tag2_en ? 1 : 0);
 524         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 525                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 526         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 527                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 528
 529         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 530         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 531                      vcfg->strip_tag1_discard_en ? 1 : 0);
 532         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 533                      vcfg->strip_tag2_discard_en ? 1 : 0);
 534         /*
 535          * In current version VF is not supported when PF is driven by DPDK
 536          * driver, just need to configure parameters for PF vport.
 537          */
 538         vport_id = HNS3_PF_FUNC_ID;
 539         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 540         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 541         req->vf_bitmap[req->vf_offset] = bitmap;
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 546         return ret;
 547 }
 548
 549 static void
 550 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 551                            struct hns3_rx_vtag_cfg *vcfg)
 552 {
 553         struct hns3_pf *pf = &hns->pf;
 554         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 555 }
 556
 557 static void
 558 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 559                            struct hns3_tx_vtag_cfg *vcfg)
 560 {
 561         struct hns3_pf *pf = &hns->pf;
 562         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 563 }
 564
 565 static int
 566 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 567 {
 568         struct hns3_rx_vtag_cfg rxvlan_cfg;
 569         struct hns3_hw *hw = &hns->hw;
 570         int ret;
 571
 572         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 573                 rxvlan_cfg.strip_tag1_en = false;
 574                 rxvlan_cfg.strip_tag2_en = enable;
 575                 rxvlan_cfg.strip_tag2_discard_en = false;
 576         } else {
 577                 rxvlan_cfg.strip_tag1_en = enable;
 578                 rxvlan_cfg.strip_tag2_en = true;
 579                 rxvlan_cfg.strip_tag2_discard_en = true;
 580         }
 581
 582         rxvlan_cfg.strip_tag1_discard_en = false;
 583         rxvlan_cfg.vlan1_vlan_prionly = false;
 584         rxvlan_cfg.vlan2_vlan_prionly = false;
 585         rxvlan_cfg.rx_vlan_offload_en = enable;
 586
 587         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 588         if (ret) {
 589                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 590                 return ret;
 591         }
 592
 593         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 600                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 601 {
 602         struct hns3_vlan_filter_ctrl_cmd *req;
 603         struct hns3_cmd_desc desc;
 604         int ret;
 605
 606         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 607
 608         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 609         req->vlan_type = vlan_type;
 610         req->vlan_fe = filter_en ? fe_type : 0;
 611         req->vf_id = vf_id;
 612
 613         ret = hns3_cmd_send(hw, &desc, 1);
 614         if (ret)
 615                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 616
 617         return ret;
 618 }
 619
 620 static int
 621 hns3_vlan_filter_init(struct hns3_adapter *hns)
 622 {
 623         struct hns3_hw *hw = &hns->hw;
 624         int ret;
 625
 626         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 627                                         HNS3_FILTER_FE_EGRESS, false,
 628                                         HNS3_PF_FUNC_ID);
 629         if (ret) {
 630                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 631                 return ret;
 632         }
 633
 634         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 635                                         HNS3_FILTER_FE_INGRESS, false,
 636                                         HNS3_PF_FUNC_ID);
 637         if (ret)
 638                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 639
 640         return ret;
 641 }
 642
 643 static int
 644 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 645 {
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 650                                         HNS3_FILTER_FE_INGRESS, enable,
 651                                         HNS3_PF_FUNC_ID);
 652         if (ret)
 653                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 654                          enable ? "enable" : "disable", ret);
 655
 656         return ret;
 657 }
 658
 659 static int
 660 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         struct rte_eth_rxmode *rxmode;
 665         unsigned int tmp_mask;
 666         bool enable;
 667         int ret = 0;
 668
 669         rte_spinlock_lock(&hw->lock);
 670         rxmode = &dev->data->dev_conf.rxmode;
 671         tmp_mask = (unsigned int)mask;
 672         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 673                 /* ignore vlan filter configuration during promiscuous mode */
 674                 if (!dev->data->promiscuous) {
 675                         /* Enable or disable VLAN filter */
 676                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 677                                  true : false;
 678
 679                         ret = hns3_enable_vlan_filter(hns, enable);
 680                         if (ret) {
 681                                 rte_spinlock_unlock(&hw->lock);
 682                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 683                                          enable ? "enable" : "disable", ret);
 684                                 return ret;
 685                         }
 686                 }
 687         }
 688
 689         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 690                 /* Enable or disable VLAN stripping */
 691                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 692                     true : false;
 693
 694                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 695                 if (ret) {
 696                         rte_spinlock_unlock(&hw->lock);
 697                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 698                                  enable ? "enable" : "disable", ret);
 699                         return ret;
 700                 }
 701         }
 702
 703         rte_spinlock_unlock(&hw->lock);
 704
 705         return ret;
 706 }
 707
 708 static int
 709 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 710                              struct hns3_tx_vtag_cfg *vcfg)
 711 {
 712         struct hns3_vport_vtag_tx_cfg_cmd *req;
 713         struct hns3_cmd_desc desc;
 714         struct hns3_hw *hw = &hns->hw;
 715         uint16_t vport_id;
 716         uint8_t bitmap;
 717         int ret;
 718
 719         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 720
 721         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 722         req->def_vlan_tag1 = vcfg->default_tag1;
 723         req->def_vlan_tag2 = vcfg->default_tag2;
 724         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 725                      vcfg->accept_tag1 ? 1 : 0);
 726         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 727                      vcfg->accept_untag1 ? 1 : 0);
 728         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 729                      vcfg->accept_tag2 ? 1 : 0);
 730         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 731                      vcfg->accept_untag2 ? 1 : 0);
 732         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 733                      vcfg->insert_tag1_en ? 1 : 0);
 734         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 735                      vcfg->insert_tag2_en ? 1 : 0);
 736         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 737
 738         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 739         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 740                      vcfg->tag_shift_mode_en ? 1 : 0);
 741
 742         /*
 743          * In current version VF is not supported when PF is driven by DPDK
 744          * driver, just need to configure parameters for PF vport.
 745          */
 746         vport_id = HNS3_PF_FUNC_ID;
 747         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 748         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 749         req->vf_bitmap[req->vf_offset] = bitmap;
 750
 751         ret = hns3_cmd_send(hw, &desc, 1);
 752         if (ret)
 753                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 754
 755         return ret;
 756 }
 757
 758 static int
 759 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 760                      uint16_t pvid)
 761 {
 762         struct hns3_hw *hw = &hns->hw;
 763         struct hns3_tx_vtag_cfg txvlan_cfg;
 764         int ret;
 765
 766         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 767                 txvlan_cfg.accept_tag1 = true;
 768                 txvlan_cfg.insert_tag1_en = false;
 769                 txvlan_cfg.default_tag1 = 0;
 770         } else {
 771                 txvlan_cfg.accept_tag1 =
 772                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 773                 txvlan_cfg.insert_tag1_en = true;
 774                 txvlan_cfg.default_tag1 = pvid;
 775         }
 776
 777         txvlan_cfg.accept_untag1 = true;
 778         txvlan_cfg.accept_tag2 = true;
 779         txvlan_cfg.accept_untag2 = true;
 780         txvlan_cfg.insert_tag2_en = false;
 781         txvlan_cfg.default_tag2 = 0;
 782         txvlan_cfg.tag_shift_mode_en = true;
 783
 784         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 785         if (ret) {
 786                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 787                          ret);
 788                 return ret;
 789         }
 790
 791         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 792         return ret;
 793 }
 794
 795
 796 static void
 797 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 798 {
 799         struct hns3_user_vlan_table *vlan_entry;
 800         struct hns3_pf *pf = &hns->pf;
 801
 802         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 803                 if (vlan_entry->hd_tbl_status) {
 804                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 805                         vlan_entry->hd_tbl_status = false;
 806                 }
 807         }
 808
 809         if (is_del_list) {
 810                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 811                 while (vlan_entry) {
 812                         LIST_REMOVE(vlan_entry, next);
 813                         rte_free(vlan_entry);
 814                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 815                 }
 816         }
 817 }
 818
 819 static void
 820 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 821 {
 822         struct hns3_user_vlan_table *vlan_entry;
 823         struct hns3_pf *pf = &hns->pf;
 824
 825         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 826                 if (!vlan_entry->hd_tbl_status) {
 827                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 828                         vlan_entry->hd_tbl_status = true;
 829                 }
 830         }
 831 }
 832
 833 static void
 834 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 835 {
 836         struct hns3_hw *hw = &hns->hw;
 837         int ret;
 838
 839         hns3_rm_all_vlan_table(hns, true);
 840         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 841                 ret = hns3_set_port_vlan_filter(hns,
 842                                                 hw->port_base_vlan_cfg.pvid, 0);
 843                 if (ret) {
 844                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 845                                  ret);
 846                         return;
 847                 }
 848         }
 849 }
 850
 851 static int
 852 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 853                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 854 {
 855         struct hns3_hw *hw = &hns->hw;
 856         uint16_t old_pvid;
 857         int ret;
 858
 859         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 860                 old_pvid = hw->port_base_vlan_cfg.pvid;
 861                 if (old_pvid != HNS3_INVALID_PVID) {
 862                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 863                         if (ret) {
 864                                 hns3_err(hw, "failed to remove old pvid %u, "
 865                                                 "ret = %d", old_pvid, ret);
 866                                 return ret;
 867                         }
 868                 }
 869
 870                 hns3_rm_all_vlan_table(hns, false);
 871                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 872                 if (ret) {
 873                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 874                                         new_pvid, ret);
 875                         return ret;
 876                 }
 877         } else {
 878                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 879                 if (ret) {
 880                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 881                                         new_pvid, ret);
 882                         return ret;
 883                 }
 884
 885                 hns3_add_all_vlan_table(hns);
 886         }
 887         return 0;
 888 }
 889
 890 static int
 891 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 892 {
 893         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 894         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 895         bool rx_strip_en;
 896         int ret;
 897
 898         rx_strip_en = old_cfg->rx_vlan_offload_en;
 899         if (on) {
 900                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 901                 rx_vlan_cfg.strip_tag2_en = true;
 902                 rx_vlan_cfg.strip_tag2_discard_en = true;
 903         } else {
 904                 rx_vlan_cfg.strip_tag1_en = false;
 905                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 906                 rx_vlan_cfg.strip_tag2_discard_en = false;
 907         }
 908         rx_vlan_cfg.strip_tag1_discard_en = false;
 909         rx_vlan_cfg.vlan1_vlan_prionly = false;
 910         rx_vlan_cfg.vlan2_vlan_prionly = false;
 911         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 912
 913         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 914         if (ret)
 915                 return ret;
 916
 917         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 918         return ret;
 919 }
 920
 921 static int
 922 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 923 {
 924         struct hns3_hw *hw = &hns->hw;
 925         uint16_t port_base_vlan_state;
 926         int ret;
 927
 928         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 929                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 930                         hns3_warn(hw, "Invalid operation! As current pvid set "
 931                                   "is %u, disable pvid %u is invalid",
 932                                   hw->port_base_vlan_cfg.pvid, pvid);
 933                 return 0;
 934         }
 935
 936         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 937                                     HNS3_PORT_BASE_VLAN_DISABLE;
 938         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 939         if (ret) {
 940                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 941                          ret);
 942                 return ret;
 943         }
 944
 945         ret = hns3_en_pvid_strip(hns, on);
 946         if (ret) {
 947                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 948                          "ret = %d", ret);
 949                 return ret;
 950         }
 951
 952         if (pvid == HNS3_INVALID_PVID)
 953                 goto out;
 954         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 955         if (ret) {
 956                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 957                          ret);
 958                 return ret;
 959         }
 960
 961 out:
 962         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 963         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 964         return ret;
 965 }
 966
 967 static int
 968 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 969 {
 970         struct hns3_adapter *hns = dev->data->dev_private;
 971         struct hns3_hw *hw = &hns->hw;
 972         bool pvid_en_state_change;
 973         uint16_t pvid_state;
 974         int ret;
 975
 976         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 977                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 978                          RTE_ETHER_MAX_VLAN_ID);
 979                 return -EINVAL;
 980         }
 981
 982         /*
 983          * If PVID configuration state change, should refresh the PVID
 984          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 985          */
 986         pvid_state = hw->port_base_vlan_cfg.state;
 987         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 988             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 989                 pvid_en_state_change = false;
 990         else
 991                 pvid_en_state_change = true;
 992
 993         rte_spinlock_lock(&hw->lock);
 994         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 995         rte_spinlock_unlock(&hw->lock);
 996         if (ret)
 997                 return ret;
 998         /*
 999          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1000          * need be processed by PMD driver.
1001          */
1002         if (pvid_en_state_change &&
1003             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1004                 hns3_update_all_queues_pvid_proc_en(hw);
1005
1006         return 0;
1007 }
1008
1009 static int
1010 hns3_default_vlan_config(struct hns3_adapter *hns)
1011 {
1012         struct hns3_hw *hw = &hns->hw;
1013         int ret;
1014
1015         /*
1016          * When vlan filter is enabled, hardware regards packets without vlan
1017          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1018          * table, packets without vlan won't be received. So, add vlan 0 as
1019          * the default vlan.
1020          */
1021         ret = hns3_vlan_filter_configure(hns, 0, 1);
1022         if (ret)
1023                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1024         return ret;
1025 }
1026
1027 static int
1028 hns3_init_vlan_config(struct hns3_adapter *hns)
1029 {
1030         struct hns3_hw *hw = &hns->hw;
1031         int ret;
1032
1033         /*
1034          * This function can be called in the initialization and reset process,
1035          * when in reset process, it means that hardware had been reseted
1036          * successfully and we need to restore the hardware configuration to
1037          * ensure that the hardware configuration remains unchanged before and
1038          * after reset.
1039          */
1040         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1041                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1042                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1043         }
1044
1045         ret = hns3_vlan_filter_init(hns);
1046         if (ret) {
1047                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1048                 return ret;
1049         }
1050
1051         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1052                                        RTE_ETHER_TYPE_VLAN);
1053         if (ret) {
1054                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1055                 return ret;
1056         }
1057
1058         /*
1059          * When in the reinit dev stage of the reset process, the following
1060          * vlan-related configurations may differ from those at initialization,
1061          * we will restore configurations to hardware in hns3_restore_vlan_table
1062          * and hns3_restore_vlan_conf later.
1063          */
1064         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1065                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1066                 if (ret) {
1067                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1068                         return ret;
1069                 }
1070
1071                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1072                 if (ret) {
1073                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1074                                  ret);
1075                         return ret;
1076                 }
1077         }
1078
1079         return hns3_default_vlan_config(hns);
1080 }
1081
1082 static int
1083 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1084 {
1085         struct hns3_pf *pf = &hns->pf;
1086         struct hns3_hw *hw = &hns->hw;
1087         uint64_t offloads;
1088         bool enable;
1089         int ret;
1090
1091         if (!hw->data->promiscuous) {
1092                 /* restore vlan filter states */
1093                 offloads = hw->data->dev_conf.rxmode.offloads;
1094                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1095                 ret = hns3_enable_vlan_filter(hns, enable);
1096                 if (ret) {
1097                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1098                                  "ret = %d", ret);
1099                         return ret;
1100                 }
1101         }
1102
1103         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1104         if (ret) {
1105                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1106                 return ret;
1107         }
1108
1109         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1110         if (ret)
1111                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1112
1113         return ret;
1114 }
1115
1116 static int
1117 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1118 {
1119         struct hns3_adapter *hns = dev->data->dev_private;
1120         struct rte_eth_dev_data *data = dev->data;
1121         struct rte_eth_txmode *txmode;
1122         struct hns3_hw *hw = &hns->hw;
1123         int mask;
1124         int ret;
1125
1126         txmode = &data->dev_conf.txmode;
1127         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1128                 hns3_warn(hw,
1129                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1130                           "configuration is not supported! Ignore these two "
1131                           "parameters: hw_vlan_reject_tagged(%u), "
1132                           "hw_vlan_reject_untagged(%u)",
1133                           txmode->hw_vlan_reject_tagged,
1134                           txmode->hw_vlan_reject_untagged);
1135
1136         /* Apply vlan offload setting */
1137         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1138         ret = hns3_vlan_offload_set(dev, mask);
1139         if (ret) {
1140                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1141                          ret);
1142                 return ret;
1143         }
1144
1145         /*
1146          * If pvid config is not set in rte_eth_conf, driver needn't to set
1147          * VLAN pvid related configuration to hardware.
1148          */
1149         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1150                 return 0;
1151
1152         /* Apply pvid setting */
1153         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1154                                  txmode->hw_vlan_insert_pvid);
1155         if (ret)
1156                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1157                          txmode->pvid, ret);
1158
1159         return ret;
1160 }
1161
1162 static int
1163 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1164                 unsigned int tso_mss_max)
1165 {
1166         struct hns3_cfg_tso_status_cmd *req;
1167         struct hns3_cmd_desc desc;
1168         uint16_t tso_mss;
1169
1170         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1171
1172         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1173
1174         tso_mss = 0;
1175         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1176                        tso_mss_min);
1177         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1178
1179         tso_mss = 0;
1180         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1181                        tso_mss_max);
1182         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1183
1184         return hns3_cmd_send(hw, &desc, 1);
1185 }
1186
1187 static int
1188 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1189                    uint16_t *allocated_size, bool is_alloc)
1190 {
1191         struct hns3_umv_spc_alc_cmd *req;
1192         struct hns3_cmd_desc desc;
1193         int ret;
1194
1195         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1196         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1197         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1198         req->space_size = rte_cpu_to_le_32(space_size);
1199
1200         ret = hns3_cmd_send(hw, &desc, 1);
1201         if (ret) {
1202                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1203                              is_alloc ? "allocate" : "free", ret);
1204                 return ret;
1205         }
1206
1207         if (is_alloc && allocated_size)
1208                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1209
1210         return 0;
1211 }
1212
1213 static int
1214 hns3_init_umv_space(struct hns3_hw *hw)
1215 {
1216         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1217         struct hns3_pf *pf = &hns->pf;
1218         uint16_t allocated_size = 0;
1219         int ret;
1220
1221         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1222                                  true);
1223         if (ret)
1224                 return ret;
1225
1226         if (allocated_size < pf->wanted_umv_size)
1227                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1228                              pf->wanted_umv_size, allocated_size);
1229
1230         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1231                                                 pf->wanted_umv_size;
1232         pf->used_umv_size = 0;
1233         return 0;
1234 }
1235
1236 static int
1237 hns3_uninit_umv_space(struct hns3_hw *hw)
1238 {
1239         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1240         struct hns3_pf *pf = &hns->pf;
1241         int ret;
1242
1243         if (pf->max_umv_size == 0)
1244                 return 0;
1245
1246         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1247         if (ret)
1248                 return ret;
1249
1250         pf->max_umv_size = 0;
1251
1252         return 0;
1253 }
1254
1255 static bool
1256 hns3_is_umv_space_full(struct hns3_hw *hw)
1257 {
1258         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1259         struct hns3_pf *pf = &hns->pf;
1260         bool is_full;
1261
1262         is_full = (pf->used_umv_size >= pf->max_umv_size);
1263
1264         return is_full;
1265 }
1266
1267 static void
1268 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1269 {
1270         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1271         struct hns3_pf *pf = &hns->pf;
1272
1273         if (is_free) {
1274                 if (pf->used_umv_size > 0)
1275                         pf->used_umv_size--;
1276         } else
1277                 pf->used_umv_size++;
1278 }
1279
1280 static void
1281 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1282                       const uint8_t *addr, bool is_mc)
1283 {
1284         const unsigned char *mac_addr = addr;
1285         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1286                             ((uint32_t)mac_addr[2] << 16) |
1287                             ((uint32_t)mac_addr[1] << 8) |
1288                             (uint32_t)mac_addr[0];
1289         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1290
1291         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1292         if (is_mc) {
1293                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1294                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1295                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1296         }
1297
1298         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1299         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1300 }
1301
1302 static int
1303 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1304                              uint8_t resp_code,
1305                              enum hns3_mac_vlan_tbl_opcode op)
1306 {
1307         if (cmdq_resp) {
1308                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1309                          cmdq_resp);
1310                 return -EIO;
1311         }
1312
1313         if (op == HNS3_MAC_VLAN_ADD) {
1314                 if (resp_code == 0 || resp_code == 1) {
1315                         return 0;
1316                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1317                         hns3_err(hw, "add mac addr failed for uc_overflow");
1318                         return -ENOSPC;
1319                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1320                         hns3_err(hw, "add mac addr failed for mc_overflow");
1321                         return -ENOSPC;
1322                 }
1323
1324                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1325                          resp_code);
1326                 return -EIO;
1327         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1328                 if (resp_code == 0) {
1329                         return 0;
1330                 } else if (resp_code == 1) {
1331                         hns3_dbg(hw, "remove mac addr failed for miss");
1332                         return -ENOENT;
1333                 }
1334
1335                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1336                          resp_code);
1337                 return -EIO;
1338         } else if (op == HNS3_MAC_VLAN_LKUP) {
1339                 if (resp_code == 0) {
1340                         return 0;
1341                 } else if (resp_code == 1) {
1342                         hns3_dbg(hw, "lookup mac addr failed for miss");
1343                         return -ENOENT;
1344                 }
1345
1346                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1347                          resp_code);
1348                 return -EIO;
1349         }
1350
1351         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1352                  op);
1353
1354         return -EINVAL;
1355 }
1356
1357 static int
1358 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1359                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1360                          struct hns3_cmd_desc *desc, bool is_mc)
1361 {
1362         uint8_t resp_code;
1363         uint16_t retval;
1364         int ret;
1365
1366         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1367         if (is_mc) {
1368                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1369                 memcpy(desc[0].data, req,
1370                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1371                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1372                                           true);
1373                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1374                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1375                                           true);
1376                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1377         } else {
1378                 memcpy(desc[0].data, req,
1379                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1380                 ret = hns3_cmd_send(hw, desc, 1);
1381         }
1382         if (ret) {
1383                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1384                          ret);
1385                 return ret;
1386         }
1387         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1388         retval = rte_le_to_cpu_16(desc[0].retval);
1389
1390         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1391                                             HNS3_MAC_VLAN_LKUP);
1392 }
1393
1394 static int
1395 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1396                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1397                       struct hns3_cmd_desc *mc_desc)
1398 {
1399         uint8_t resp_code;
1400         uint16_t retval;
1401         int cfg_status;
1402         int ret;
1403
1404         if (mc_desc == NULL) {
1405                 struct hns3_cmd_desc desc;
1406
1407                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1408                 memcpy(desc.data, req,
1409                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1410                 ret = hns3_cmd_send(hw, &desc, 1);
1411                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1412                 retval = rte_le_to_cpu_16(desc.retval);
1413
1414                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1415                                                           HNS3_MAC_VLAN_ADD);
1416         } else {
1417                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1418                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1419                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1420                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1421                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1422                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1423                 memcpy(mc_desc[0].data, req,
1424                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1425                 mc_desc[0].retval = 0;
1426                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1427                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1428                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1429
1430                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1431                                                           HNS3_MAC_VLAN_ADD);
1432         }
1433
1434         if (ret) {
1435                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1436                 return ret;
1437         }
1438
1439         return cfg_status;
1440 }
1441
1442 static int
1443 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1444                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1445 {
1446         struct hns3_cmd_desc desc;
1447         uint8_t resp_code;
1448         uint16_t retval;
1449         int ret;
1450
1451         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1452
1453         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1454
1455         ret = hns3_cmd_send(hw, &desc, 1);
1456         if (ret) {
1457                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1458                 return ret;
1459         }
1460         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1461         retval = rte_le_to_cpu_16(desc.retval);
1462
1463         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1464                                             HNS3_MAC_VLAN_REMOVE);
1465 }
1466
1467 static int
1468 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1469 {
1470         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1471         struct hns3_mac_vlan_tbl_entry_cmd req;
1472         struct hns3_pf *pf = &hns->pf;
1473         struct hns3_cmd_desc desc[3];
1474         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1475         uint16_t egress_port = 0;
1476         uint8_t vf_id;
1477         int ret;
1478
1479         /* check if mac addr is valid */
1480         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1481                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1482                                       mac_addr);
1483                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1484                          mac_str);
1485                 return -EINVAL;
1486         }
1487
1488         memset(&req, 0, sizeof(req));
1489
1490         /*
1491          * In current version VF is not supported when PF is driven by DPDK
1492          * driver, just need to configure parameters for PF vport.
1493          */
1494         vf_id = HNS3_PF_FUNC_ID;
1495         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1496                        HNS3_MAC_EPORT_VFID_S, vf_id);
1497
1498         req.egress_port = rte_cpu_to_le_16(egress_port);
1499
1500         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1501
1502         /*
1503          * Lookup the mac address in the mac_vlan table, and add
1504          * it if the entry is inexistent. Repeated unicast entry
1505          * is not allowed in the mac vlan table.
1506          */
1507         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1508         if (ret == -ENOENT) {
1509                 if (!hns3_is_umv_space_full(hw)) {
1510                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1511                         if (!ret)
1512                                 hns3_update_umv_space(hw, false);
1513                         return ret;
1514                 }
1515
1516                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1517
1518                 return -ENOSPC;
1519         }
1520
1521         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1522
1523         /* check if we just hit the duplicate */
1524         if (ret == 0) {
1525                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1526                 return 0;
1527         }
1528
1529         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1530                  mac_str);
1531
1532         return ret;
1533 }
1534
1535 static int
1536 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1537 {
1538         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1539         struct rte_ether_addr *addr;
1540         int ret;
1541         int i;
1542
1543         for (i = 0; i < hw->mc_addrs_num; i++) {
1544                 addr = &hw->mc_addrs[i];
1545                 /* Check if there are duplicate addresses */
1546                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1547                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1548                                               addr);
1549                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1550                                  "(%s) is added by the set_mc_mac_addr_list "
1551                                  "API", mac_str);
1552                         return -EINVAL;
1553                 }
1554         }
1555
1556         ret = hns3_add_mc_addr(hw, mac_addr);
1557         if (ret) {
1558                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1559                                       mac_addr);
1560                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1561                          mac_str, ret);
1562         }
1563         return ret;
1564 }
1565
1566 static int
1567 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1568 {
1569         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1570         int ret;
1571
1572         ret = hns3_remove_mc_addr(hw, mac_addr);
1573         if (ret) {
1574                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1575                                       mac_addr);
1576                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1577                          mac_str, ret);
1578         }
1579         return ret;
1580 }
1581
1582 static int
1583 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1584                   uint32_t idx, __rte_unused uint32_t pool)
1585 {
1586         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1587         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1588         int ret;
1589
1590         rte_spinlock_lock(&hw->lock);
1591
1592         /*
1593          * In hns3 network engine adding UC and MC mac address with different
1594          * commands with firmware. We need to determine whether the input
1595          * address is a UC or a MC address to call different commands.
1596          * By the way, it is recommended calling the API function named
1597          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1598          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1599          * may affect the specifications of UC mac addresses.
1600          */
1601         if (rte_is_multicast_ether_addr(mac_addr))
1602                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1603         else
1604                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1605
1606         if (ret) {
1607                 rte_spinlock_unlock(&hw->lock);
1608                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1609                                       mac_addr);
1610                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1611                          ret);
1612                 return ret;
1613         }
1614
1615         if (idx == 0)
1616                 hw->mac.default_addr_setted = true;
1617         rte_spinlock_unlock(&hw->lock);
1618
1619         return ret;
1620 }
1621
1622 static int
1623 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1624 {
1625         struct hns3_mac_vlan_tbl_entry_cmd req;
1626         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1627         int ret;
1628
1629         /* check if mac addr is valid */
1630         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1631                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1632                                       mac_addr);
1633                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1634                          mac_str);
1635                 return -EINVAL;
1636         }
1637
1638         memset(&req, 0, sizeof(req));
1639         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1640         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1641         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1642         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1643                 return 0;
1644         else if (ret == 0)
1645                 hns3_update_umv_space(hw, true);
1646
1647         return ret;
1648 }
1649
1650 static void
1651 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1652 {
1653         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         /* index will be checked by upper level rte interface */
1655         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1656         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1657         int ret;
1658
1659         rte_spinlock_lock(&hw->lock);
1660
1661         if (rte_is_multicast_ether_addr(mac_addr))
1662                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1663         else
1664                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1665         rte_spinlock_unlock(&hw->lock);
1666         if (ret) {
1667                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668                                       mac_addr);
1669                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1670                          ret);
1671         }
1672 }
1673
1674 static int
1675 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1676                           struct rte_ether_addr *mac_addr)
1677 {
1678         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679         struct rte_ether_addr *oaddr;
1680         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1681         bool default_addr_setted;
1682         bool rm_succes = false;
1683         int ret, ret_val;
1684
1685         /*
1686          * It has been guaranteed that input parameter named mac_addr is valid
1687          * address in the rte layer of DPDK framework.
1688          */
1689         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1690         default_addr_setted = hw->mac.default_addr_setted;
1691         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1692                 return 0;
1693
1694         rte_spinlock_lock(&hw->lock);
1695         if (default_addr_setted) {
1696                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1697                 if (ret) {
1698                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1699                                               oaddr);
1700                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1701                                   mac_str, ret);
1702                         rm_succes = false;
1703                 } else
1704                         rm_succes = true;
1705         }
1706
1707         ret = hns3_add_uc_addr_common(hw, mac_addr);
1708         if (ret) {
1709                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1710                                       mac_addr);
1711                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1712                 goto err_add_uc_addr;
1713         }
1714
1715         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1716         if (ret) {
1717                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1718                 goto err_pause_addr_cfg;
1719         }
1720
1721         rte_ether_addr_copy(mac_addr,
1722                             (struct rte_ether_addr *)hw->mac.mac_addr);
1723         hw->mac.default_addr_setted = true;
1724         rte_spinlock_unlock(&hw->lock);
1725
1726         return 0;
1727
1728 err_pause_addr_cfg:
1729         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1730         if (ret_val) {
1731                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1732                                       mac_addr);
1733                 hns3_warn(hw,
1734                           "Failed to roll back to del setted mac addr(%s): %d",
1735                           mac_str, ret_val);
1736         }
1737
1738 err_add_uc_addr:
1739         if (rm_succes) {
1740                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1741                 if (ret_val) {
1742                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1743                                               oaddr);
1744                         hns3_warn(hw,
1745                                   "Failed to restore old uc mac addr(%s): %d",
1746                                   mac_str, ret_val);
1747                         hw->mac.default_addr_setted = false;
1748                 }
1749         }
1750         rte_spinlock_unlock(&hw->lock);
1751
1752         return ret;
1753 }
1754
1755 static int
1756 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1757 {
1758         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1759         struct hns3_hw *hw = &hns->hw;
1760         struct rte_ether_addr *addr;
1761         int err = 0;
1762         int ret;
1763         int i;
1764
1765         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1766                 addr = &hw->data->mac_addrs[i];
1767                 if (rte_is_zero_ether_addr(addr))
1768                         continue;
1769                 if (rte_is_multicast_ether_addr(addr))
1770                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1771                               hns3_add_mc_addr(hw, addr);
1772                 else
1773                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1774                               hns3_add_uc_addr_common(hw, addr);
1775
1776                 if (ret) {
1777                         err = ret;
1778                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1779                                               addr);
1780                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1781                                  "ret = %d.", del ? "remove" : "restore",
1782                                  mac_str, i, ret);
1783                 }
1784         }
1785         return err;
1786 }
1787
1788 static void
1789 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1790 {
1791 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1792         uint8_t word_num;
1793         uint8_t bit_num;
1794
1795         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1796                 word_num = vfid / 32;
1797                 bit_num = vfid % 32;
1798                 if (clr)
1799                         desc[1].data[word_num] &=
1800                             rte_cpu_to_le_32(~(1UL << bit_num));
1801                 else
1802                         desc[1].data[word_num] |=
1803                             rte_cpu_to_le_32(1UL << bit_num);
1804         } else {
1805                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1806                 bit_num = vfid % 32;
1807                 if (clr)
1808                         desc[2].data[word_num] &=
1809                             rte_cpu_to_le_32(~(1UL << bit_num));
1810                 else
1811                         desc[2].data[word_num] |=
1812                             rte_cpu_to_le_32(1UL << bit_num);
1813         }
1814 }
1815
1816 static int
1817 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1818 {
1819         struct hns3_mac_vlan_tbl_entry_cmd req;
1820         struct hns3_cmd_desc desc[3];
1821         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1822         uint8_t vf_id;
1823         int ret;
1824
1825         /* Check if mac addr is valid */
1826         if (!rte_is_multicast_ether_addr(mac_addr)) {
1827                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1828                                       mac_addr);
1829                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1830                          mac_str);
1831                 return -EINVAL;
1832         }
1833
1834         memset(&req, 0, sizeof(req));
1835         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1836         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1837         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1838         if (ret) {
1839                 /* This mac addr do not exist, add new entry for it */
1840                 memset(desc[0].data, 0, sizeof(desc[0].data));
1841                 memset(desc[1].data, 0, sizeof(desc[0].data));
1842                 memset(desc[2].data, 0, sizeof(desc[0].data));
1843         }
1844
1845         /*
1846          * In current version VF is not supported when PF is driven by DPDK
1847          * driver, just need to configure parameters for PF vport.
1848          */
1849         vf_id = HNS3_PF_FUNC_ID;
1850         hns3_update_desc_vfid(desc, vf_id, false);
1851         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1852         if (ret) {
1853                 if (ret == -ENOSPC)
1854                         hns3_err(hw, "mc mac vlan table is full");
1855                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1856                                       mac_addr);
1857                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1858         }
1859
1860         return ret;
1861 }
1862
1863 static int
1864 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1865 {
1866         struct hns3_mac_vlan_tbl_entry_cmd req;
1867         struct hns3_cmd_desc desc[3];
1868         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1869         uint8_t vf_id;
1870         int ret;
1871
1872         /* Check if mac addr is valid */
1873         if (!rte_is_multicast_ether_addr(mac_addr)) {
1874                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1875                                       mac_addr);
1876                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1877                          mac_str);
1878                 return -EINVAL;
1879         }
1880
1881         memset(&req, 0, sizeof(req));
1882         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1883         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1884         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1885         if (ret == 0) {
1886                 /*
1887                  * This mac addr exist, remove this handle's VFID for it.
1888                  * In current version VF is not supported when PF is driven by
1889                  * DPDK driver, just need to configure parameters for PF vport.
1890                  */
1891                 vf_id = HNS3_PF_FUNC_ID;
1892                 hns3_update_desc_vfid(desc, vf_id, true);
1893
1894                 /* All the vfid is zero, so need to delete this entry */
1895                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1896         } else if (ret == -ENOENT) {
1897                 /* This mac addr doesn't exist. */
1898                 return 0;
1899         }
1900
1901         if (ret) {
1902                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1903                                       mac_addr);
1904                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1905         }
1906
1907         return ret;
1908 }
1909
1910 static int
1911 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1912                            struct rte_ether_addr *mc_addr_set,
1913                            uint32_t nb_mc_addr)
1914 {
1915         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1916         struct rte_ether_addr *addr;
1917         uint32_t i;
1918         uint32_t j;
1919
1920         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1921                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1922                          "invalid. valid range: 0~%d",
1923                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1924                 return -EINVAL;
1925         }
1926
1927         /* Check if input mac addresses are valid */
1928         for (i = 0; i < nb_mc_addr; i++) {
1929                 addr = &mc_addr_set[i];
1930                 if (!rte_is_multicast_ether_addr(addr)) {
1931                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1932                                               addr);
1933                         hns3_err(hw,
1934                                  "failed to set mc mac addr, addr(%s) invalid.",
1935                                  mac_str);
1936                         return -EINVAL;
1937                 }
1938
1939                 /* Check if there are duplicate addresses */
1940                 for (j = i + 1; j < nb_mc_addr; j++) {
1941                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1942                                 hns3_ether_format_addr(mac_str,
1943                                                       RTE_ETHER_ADDR_FMT_SIZE,
1944                                                       addr);
1945                                 hns3_err(hw, "failed to set mc mac addr, "
1946                                          "addrs invalid. two same addrs(%s).",
1947                                          mac_str);
1948                                 return -EINVAL;
1949                         }
1950                 }
1951
1952                 /*
1953                  * Check if there are duplicate addresses between mac_addrs
1954                  * and mc_addr_set
1955                  */
1956                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1957                         if (rte_is_same_ether_addr(addr,
1958                                                    &hw->data->mac_addrs[j])) {
1959                                 hns3_ether_format_addr(mac_str,
1960                                                       RTE_ETHER_ADDR_FMT_SIZE,
1961                                                       addr);
1962                                 hns3_err(hw, "failed to set mc mac addr, "
1963                                          "addrs invalid. addrs(%s) has already "
1964                                          "configured in mac_addr add API",
1965                                          mac_str);
1966                                 return -EINVAL;
1967                         }
1968                 }
1969         }
1970
1971         return 0;
1972 }
1973
1974 static void
1975 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1976                            struct rte_ether_addr *mc_addr_set,
1977                            int mc_addr_num,
1978                            struct rte_ether_addr *reserved_addr_list,
1979                            int *reserved_addr_num,
1980                            struct rte_ether_addr *add_addr_list,
1981                            int *add_addr_num,
1982                            struct rte_ether_addr *rm_addr_list,
1983                            int *rm_addr_num)
1984 {
1985         struct rte_ether_addr *addr;
1986         int current_addr_num;
1987         int reserved_num = 0;
1988         int add_num = 0;
1989         int rm_num = 0;
1990         int num;
1991         int i;
1992         int j;
1993         bool same_addr;
1994
1995         /* Calculate the mc mac address list that should be removed */
1996         current_addr_num = hw->mc_addrs_num;
1997         for (i = 0; i < current_addr_num; i++) {
1998                 addr = &hw->mc_addrs[i];
1999                 same_addr = false;
2000                 for (j = 0; j < mc_addr_num; j++) {
2001                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2002                                 same_addr = true;
2003                                 break;
2004                         }
2005                 }
2006
2007                 if (!same_addr) {
2008                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2009                         rm_num++;
2010                 } else {
2011                         rte_ether_addr_copy(addr,
2012                                             &reserved_addr_list[reserved_num]);
2013                         reserved_num++;
2014                 }
2015         }
2016
2017         /* Calculate the mc mac address list that should be added */
2018         for (i = 0; i < mc_addr_num; i++) {
2019                 addr = &mc_addr_set[i];
2020                 same_addr = false;
2021                 for (j = 0; j < current_addr_num; j++) {
2022                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2023                                 same_addr = true;
2024                                 break;
2025                         }
2026                 }
2027
2028                 if (!same_addr) {
2029                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2030                         add_num++;
2031                 }
2032         }
2033
2034         /* Reorder the mc mac address list maintained by driver */
2035         for (i = 0; i < reserved_num; i++)
2036                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2037
2038         for (i = 0; i < rm_num; i++) {
2039                 num = reserved_num + i;
2040                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2041         }
2042
2043         *reserved_addr_num = reserved_num;
2044         *add_addr_num = add_num;
2045         *rm_addr_num = rm_num;
2046 }
2047
2048 static int
2049 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2050                           struct rte_ether_addr *mc_addr_set,
2051                           uint32_t nb_mc_addr)
2052 {
2053         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2055         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2056         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2057         struct rte_ether_addr *addr;
2058         int reserved_addr_num;
2059         int add_addr_num;
2060         int rm_addr_num;
2061         int mc_addr_num;
2062         int num;
2063         int ret;
2064         int i;
2065
2066         /* Check if input parameters are valid */
2067         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2068         if (ret)
2069                 return ret;
2070
2071         rte_spinlock_lock(&hw->lock);
2072
2073         /*
2074          * Calculate the mc mac address lists those should be removed and be
2075          * added, Reorder the mc mac address list maintained by driver.
2076          */
2077         mc_addr_num = (int)nb_mc_addr;
2078         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2079                                    reserved_addr_list, &reserved_addr_num,
2080                                    add_addr_list, &add_addr_num,
2081                                    rm_addr_list, &rm_addr_num);
2082
2083         /* Remove mc mac addresses */
2084         for (i = 0; i < rm_addr_num; i++) {
2085                 num = rm_addr_num - i - 1;
2086                 addr = &rm_addr_list[num];
2087                 ret = hns3_remove_mc_addr(hw, addr);
2088                 if (ret) {
2089                         rte_spinlock_unlock(&hw->lock);
2090                         return ret;
2091                 }
2092                 hw->mc_addrs_num--;
2093         }
2094
2095         /* Add mc mac addresses */
2096         for (i = 0; i < add_addr_num; i++) {
2097                 addr = &add_addr_list[i];
2098                 ret = hns3_add_mc_addr(hw, addr);
2099                 if (ret) {
2100                         rte_spinlock_unlock(&hw->lock);
2101                         return ret;
2102                 }
2103
2104                 num = reserved_addr_num + i;
2105                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2106                 hw->mc_addrs_num++;
2107         }
2108         rte_spinlock_unlock(&hw->lock);
2109
2110         return 0;
2111 }
2112
2113 static int
2114 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2115 {
2116         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2117         struct hns3_hw *hw = &hns->hw;
2118         struct rte_ether_addr *addr;
2119         int err = 0;
2120         int ret;
2121         int i;
2122
2123         for (i = 0; i < hw->mc_addrs_num; i++) {
2124                 addr = &hw->mc_addrs[i];
2125                 if (!rte_is_multicast_ether_addr(addr))
2126                         continue;
2127                 if (del)
2128                         ret = hns3_remove_mc_addr(hw, addr);
2129                 else
2130                         ret = hns3_add_mc_addr(hw, addr);
2131                 if (ret) {
2132                         err = ret;
2133                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2134                                               addr);
2135                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2136                                  del ? "Remove" : "Restore", mac_str, ret);
2137                 }
2138         }
2139         return err;
2140 }
2141
2142 static int
2143 hns3_check_mq_mode(struct rte_eth_dev *dev)
2144 {
2145         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2146         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2147         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2150         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2151         uint8_t num_tc;
2152         int max_tc = 0;
2153         int i;
2154
2155         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2156         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2157
2158         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2159                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2160                          "rx_mq_mode = %d", rx_mq_mode);
2161                 return -EINVAL;
2162         }
2163
2164         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2165             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2166                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2167                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2168                          rx_mq_mode, tx_mq_mode);
2169                 return -EINVAL;
2170         }
2171
2172         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2173                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2174                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2175                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2176                         return -EINVAL;
2177                 }
2178
2179                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2180                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2181                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2182                                  "nb_tcs(%d) != %d or %d in rx direction.",
2183                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2184                         return -EINVAL;
2185                 }
2186
2187                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2188                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2189                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2190                         return -EINVAL;
2191                 }
2192
2193                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2194                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2195                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2196                                          "is not equal to one in tx direction.",
2197                                          i, dcb_rx_conf->dcb_tc[i]);
2198                                 return -EINVAL;
2199                         }
2200                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2201                                 max_tc = dcb_rx_conf->dcb_tc[i];
2202                 }
2203
2204                 num_tc = max_tc + 1;
2205                 if (num_tc > dcb_rx_conf->nb_tcs) {
2206                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2207                                  num_tc, dcb_rx_conf->nb_tcs);
2208                         return -EINVAL;
2209                 }
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int
2216 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2217 {
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219
2220         if (!hns3_dev_dcb_supported(hw)) {
2221                 hns3_err(hw, "this port does not support dcb configurations.");
2222                 return -EOPNOTSUPP;
2223         }
2224
2225         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2226                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2227                 return -EOPNOTSUPP;
2228         }
2229
2230         /* Check multiple queue mode */
2231         return hns3_check_mq_mode(dev);
2232 }
2233
2234 static int
2235 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2236                            enum hns3_ring_type queue_type, uint16_t queue_id)
2237 {
2238         struct hns3_cmd_desc desc;
2239         struct hns3_ctrl_vector_chain_cmd *req =
2240                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2241         enum hns3_cmd_status status;
2242         enum hns3_opcode_type op;
2243         uint16_t tqp_type_and_id = 0;
2244         const char *op_str;
2245         uint16_t type;
2246         uint16_t gl;
2247
2248         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2249         hns3_cmd_setup_basic_desc(&desc, op, false);
2250         req->int_vector_id = vector_id;
2251
2252         if (queue_type == HNS3_RING_TYPE_RX)
2253                 gl = HNS3_RING_GL_RX;
2254         else
2255                 gl = HNS3_RING_GL_TX;
2256
2257         type = queue_type;
2258
2259         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2260                        type);
2261         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2262         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2263                        gl);
2264         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2265         req->int_cause_num = 1;
2266         op_str = mmap ? "Map" : "Unmap";
2267         status = hns3_cmd_send(hw, &desc, 1);
2268         if (status) {
2269                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2270                          op_str, queue_id, req->int_vector_id, status);
2271                 return status;
2272         }
2273
2274         return 0;
2275 }
2276
2277 static int
2278 hns3_init_ring_with_vector(struct hns3_hw *hw)
2279 {
2280         uint16_t vec;
2281         int ret;
2282         int i;
2283
2284         /*
2285          * In hns3 network engine, vector 0 is always the misc interrupt of this
2286          * function, vector 1~N can be used respectively for the queues of the
2287          * function. Tx and Rx queues with the same number share the interrupt
2288          * vector. In the initialization clearing the all hardware mapping
2289          * relationship configurations between queues and interrupt vectors is
2290          * needed, so some error caused by the residual configurations, such as
2291          * the unexpected Tx interrupt, can be avoid.
2292          */
2293         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2294         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2295                 vec = vec - 1; /* the last interrupt is reserved */
2296         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2297         for (i = 0; i < hw->intr_tqps_num; i++) {
2298                 /*
2299                  * Set gap limiter/rate limiter/quanity limiter algorithm
2300                  * configuration for interrupt coalesce of queue's interrupt.
2301                  */
2302                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2303                                        HNS3_TQP_INTR_GL_DEFAULT);
2304                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2305                                        HNS3_TQP_INTR_GL_DEFAULT);
2306                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2307                 /*
2308                  * QL(quantity limiter) is not used currently, just set 0 to
2309                  * close it.
2310                  */
2311                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2312
2313                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2314                                                  HNS3_RING_TYPE_TX, i);
2315                 if (ret) {
2316                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2317                                           "vector: %u, ret=%d", i, vec, ret);
2318                         return ret;
2319                 }
2320
2321                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2322                                                  HNS3_RING_TYPE_RX, i);
2323                 if (ret) {
2324                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2325                                           "vector: %u, ret=%d", i, vec, ret);
2326                         return ret;
2327                 }
2328         }
2329
2330         return 0;
2331 }
2332
2333 static int
2334 hns3_dev_configure(struct rte_eth_dev *dev)
2335 {
2336         struct hns3_adapter *hns = dev->data->dev_private;
2337         struct rte_eth_conf *conf = &dev->data->dev_conf;
2338         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2339         struct hns3_hw *hw = &hns->hw;
2340         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2341         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2342         struct rte_eth_rss_conf rss_conf;
2343         uint16_t mtu;
2344         bool gro_en;
2345         int ret;
2346
2347         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2348
2349         /*
2350          * Some versions of hardware network engine does not support
2351          * individually enable/disable/reset the Tx or Rx queue. These devices
2352          * must enable/disable/reset Tx and Rx queues at the same time. When the
2353          * numbers of Tx queues allocated by upper applications are not equal to
2354          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2355          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2356          * work as usual. But these fake queues are imperceptible, and can not
2357          * be used by upper applications.
2358          */
2359         if (!hns3_dev_indep_txrx_supported(hw)) {
2360                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2361                 if (ret) {
2362                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2363                                  ret);
2364                         return ret;
2365                 }
2366         }
2367
2368         hw->adapter_state = HNS3_NIC_CONFIGURING;
2369         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2370                 hns3_err(hw, "setting link speed/duplex not supported");
2371                 ret = -EINVAL;
2372                 goto cfg_err;
2373         }
2374
2375         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2376                 ret = hns3_check_dcb_cfg(dev);
2377                 if (ret)
2378                         goto cfg_err;
2379         }
2380
2381         /* When RSS is not configured, redirect the packet queue 0 */
2382         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2383                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2384                 rss_conf = conf->rx_adv_conf.rss_conf;
2385                 hw->rss_dis_flag = false;
2386                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2387                 if (ret)
2388                         goto cfg_err;
2389         }
2390
2391         /*
2392          * If jumbo frames are enabled, MTU needs to be refreshed
2393          * according to the maximum RX packet length.
2394          */
2395         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2396                 /*
2397                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2398                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2399                  * can safely assign to "uint16_t" type variable.
2400                  */
2401                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2402                 ret = hns3_dev_mtu_set(dev, mtu);
2403                 if (ret)
2404                         goto cfg_err;
2405                 dev->data->mtu = mtu;
2406         }
2407
2408         ret = hns3_dev_configure_vlan(dev);
2409         if (ret)
2410                 goto cfg_err;
2411
2412         /* config hardware GRO */
2413         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2414         ret = hns3_config_gro(hw, gro_en);
2415         if (ret)
2416                 goto cfg_err;
2417
2418         hns->rx_simple_allowed = true;
2419         hns->rx_vec_allowed = true;
2420         hns->tx_simple_allowed = true;
2421         hns->tx_vec_allowed = true;
2422
2423         hns3_init_rx_ptype_tble(dev);
2424         hw->adapter_state = HNS3_NIC_CONFIGURED;
2425
2426         return 0;
2427
2428 cfg_err:
2429         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2430         hw->adapter_state = HNS3_NIC_INITIALIZED;
2431
2432         return ret;
2433 }
2434
2435 static int
2436 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2437 {
2438         struct hns3_config_max_frm_size_cmd *req;
2439         struct hns3_cmd_desc desc;
2440
2441         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2442
2443         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2444         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2445         req->min_frm_size = RTE_ETHER_MIN_LEN;
2446
2447         return hns3_cmd_send(hw, &desc, 1);
2448 }
2449
2450 static int
2451 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2452 {
2453         int ret;
2454
2455         ret = hns3_set_mac_mtu(hw, mps);
2456         if (ret) {
2457                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2458                 return ret;
2459         }
2460
2461         ret = hns3_buffer_alloc(hw);
2462         if (ret)
2463                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2464
2465         return ret;
2466 }
2467
2468 static int
2469 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2470 {
2471         struct hns3_adapter *hns = dev->data->dev_private;
2472         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2473         struct hns3_hw *hw = &hns->hw;
2474         bool is_jumbo_frame;
2475         int ret;
2476
2477         if (dev->data->dev_started) {
2478                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2479                          "before configuration", dev->data->port_id);
2480                 return -EBUSY;
2481         }
2482
2483         rte_spinlock_lock(&hw->lock);
2484         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2485         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2486
2487         /*
2488          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2489          * assign to "uint16_t" type variable.
2490          */
2491         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2492         if (ret) {
2493                 rte_spinlock_unlock(&hw->lock);
2494                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2495                          dev->data->port_id, mtu, ret);
2496                 return ret;
2497         }
2498         hns->pf.mps = (uint16_t)frame_size;
2499         if (is_jumbo_frame)
2500                 dev->data->dev_conf.rxmode.offloads |=
2501                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2502         else
2503                 dev->data->dev_conf.rxmode.offloads &=
2504                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2505         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2506         rte_spinlock_unlock(&hw->lock);
2507
2508         return 0;
2509 }
2510
2511 int
2512 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2513 {
2514         struct hns3_adapter *hns = eth_dev->data->dev_private;
2515         struct hns3_hw *hw = &hns->hw;
2516         uint16_t queue_num = hw->tqps_num;
2517
2518         /*
2519          * In interrupt mode, 'max_rx_queues' is set based on the number of
2520          * MSI-X interrupt resources of the hardware.
2521          */
2522         if (hw->data->dev_conf.intr_conf.rxq == 1)
2523                 queue_num = hw->intr_tqps_num;
2524
2525         info->max_rx_queues = queue_num;
2526         info->max_tx_queues = hw->tqps_num;
2527         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2528         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2529         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2530         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2531         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2532         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2533                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2534                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2535                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2536                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2537                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2538                                  DEV_RX_OFFLOAD_KEEP_CRC |
2539                                  DEV_RX_OFFLOAD_SCATTER |
2540                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2541                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2542                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2543                                  DEV_RX_OFFLOAD_RSS_HASH |
2544                                  DEV_RX_OFFLOAD_TCP_LRO);
2545         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2546                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2547                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2548                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2549                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2550                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2551                                  DEV_TX_OFFLOAD_TCP_TSO |
2552                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2553                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2554                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2555                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2556                                  hns3_txvlan_cap_get(hw));
2557
2558         if (hns3_dev_indep_txrx_supported(hw))
2559                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2560                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2561
2562         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2563                 .nb_max = HNS3_MAX_RING_DESC,
2564                 .nb_min = HNS3_MIN_RING_DESC,
2565                 .nb_align = HNS3_ALIGN_RING_DESC,
2566         };
2567
2568         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2569                 .nb_max = HNS3_MAX_RING_DESC,
2570                 .nb_min = HNS3_MIN_RING_DESC,
2571                 .nb_align = HNS3_ALIGN_RING_DESC,
2572                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2573                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2574         };
2575
2576         info->default_rxconf = (struct rte_eth_rxconf) {
2577                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2578                 /*
2579                  * If there are no available Rx buffer descriptors, incoming
2580                  * packets are always dropped by hardware based on hns3 network
2581                  * engine.
2582                  */
2583                 .rx_drop_en = 1,
2584                 .offloads = 0,
2585         };
2586         info->default_txconf = (struct rte_eth_txconf) {
2587                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2588                 .offloads = 0,
2589         };
2590
2591         info->vmdq_queue_num = 0;
2592
2593         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2594         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2595         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2596
2597         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2598         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2599         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2600         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2601         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2602         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2603
2604         return 0;
2605 }
2606
2607 static int
2608 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2609                     size_t fw_size)
2610 {
2611         struct hns3_adapter *hns = eth_dev->data->dev_private;
2612         struct hns3_hw *hw = &hns->hw;
2613         uint32_t version = hw->fw_version;
2614         int ret;
2615
2616         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2617                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2618                                       HNS3_FW_VERSION_BYTE3_S),
2619                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2620                                       HNS3_FW_VERSION_BYTE2_S),
2621                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2622                                       HNS3_FW_VERSION_BYTE1_S),
2623                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2624                                       HNS3_FW_VERSION_BYTE0_S));
2625         ret += 1; /* add the size of '\0' */
2626         if (fw_size < (uint32_t)ret)
2627                 return ret;
2628         else
2629                 return 0;
2630 }
2631
2632 static int
2633 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2634                      __rte_unused int wait_to_complete)
2635 {
2636         struct hns3_adapter *hns = eth_dev->data->dev_private;
2637         struct hns3_hw *hw = &hns->hw;
2638         struct hns3_mac *mac = &hw->mac;
2639         struct rte_eth_link new_link;
2640
2641         if (!hns3_is_reset_pending(hns)) {
2642                 hns3_update_speed_duplex(eth_dev);
2643                 hns3_update_link_status(hw);
2644         }
2645
2646         memset(&new_link, 0, sizeof(new_link));
2647         switch (mac->link_speed) {
2648         case ETH_SPEED_NUM_10M:
2649         case ETH_SPEED_NUM_100M:
2650         case ETH_SPEED_NUM_1G:
2651         case ETH_SPEED_NUM_10G:
2652         case ETH_SPEED_NUM_25G:
2653         case ETH_SPEED_NUM_40G:
2654         case ETH_SPEED_NUM_50G:
2655         case ETH_SPEED_NUM_100G:
2656         case ETH_SPEED_NUM_200G:
2657                 new_link.link_speed = mac->link_speed;
2658                 break;
2659         default:
2660                 new_link.link_speed = ETH_SPEED_NUM_100M;
2661                 break;
2662         }
2663
2664         new_link.link_duplex = mac->link_duplex;
2665         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2666         new_link.link_autoneg =
2667             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2668
2669         return rte_eth_linkstatus_set(eth_dev, &new_link);
2670 }
2671
2672 static int
2673 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2674 {
2675         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2676         struct hns3_pf *pf = &hns->pf;
2677
2678         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2679                 return -EINVAL;
2680
2681         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2682
2683         return 0;
2684 }
2685
2686 static int
2687 hns3_query_function_status(struct hns3_hw *hw)
2688 {
2689 #define HNS3_QUERY_MAX_CNT              10
2690 #define HNS3_QUERY_SLEEP_MSCOEND        1
2691         struct hns3_func_status_cmd *req;
2692         struct hns3_cmd_desc desc;
2693         int timeout = 0;
2694         int ret;
2695
2696         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2697         req = (struct hns3_func_status_cmd *)desc.data;
2698
2699         do {
2700                 ret = hns3_cmd_send(hw, &desc, 1);
2701                 if (ret) {
2702                         PMD_INIT_LOG(ERR, "query function status failed %d",
2703                                      ret);
2704                         return ret;
2705                 }
2706
2707                 /* Check pf reset is done */
2708                 if (req->pf_state)
2709                         break;
2710
2711                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2712         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2713
2714         return hns3_parse_func_status(hw, req);
2715 }
2716
2717 static int
2718 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2719 {
2720         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2721         struct hns3_pf *pf = &hns->pf;
2722
2723         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2724                 /*
2725                  * The total_tqps_num obtained from firmware is maximum tqp
2726                  * numbers of this port, which should be used for PF and VFs.
2727                  * There is no need for pf to have so many tqp numbers in
2728                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2729                  * coming from config file, is assigned to maximum queue number
2730                  * for the PF of this port by user. So users can modify the
2731                  * maximum queue number of PF according to their own application
2732                  * scenarios, which is more flexible to use. In addition, many
2733                  * memories can be saved due to allocating queue statistics
2734                  * room according to the actual number of queues required. The
2735                  * maximum queue number of PF for network engine with
2736                  * revision_id greater than 0x30 is assigned by config file.
2737                  */
2738                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2739                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2740                                  "must be greater than 0.",
2741                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2742                         return -EINVAL;
2743                 }
2744
2745                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2746                                        hw->total_tqps_num);
2747         } else {
2748                 /*
2749                  * Due to the limitation on the number of PF interrupts
2750                  * available, the maximum queue number assigned to PF on
2751                  * the network engine with revision_id 0x21 is 64.
2752                  */
2753                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2754                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2755         }
2756
2757         return 0;
2758 }
2759
2760 static int
2761 hns3_query_pf_resource(struct hns3_hw *hw)
2762 {
2763         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2764         struct hns3_pf *pf = &hns->pf;
2765         struct hns3_pf_res_cmd *req;
2766         struct hns3_cmd_desc desc;
2767         int ret;
2768
2769         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2770         ret = hns3_cmd_send(hw, &desc, 1);
2771         if (ret) {
2772                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2773                 return ret;
2774         }
2775
2776         req = (struct hns3_pf_res_cmd *)desc.data;
2777         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2778                              rte_le_to_cpu_16(req->ext_tqp_num);
2779         ret = hns3_get_pf_max_tqp_num(hw);
2780         if (ret)
2781                 return ret;
2782
2783         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2784         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2785
2786         if (req->tx_buf_size)
2787                 pf->tx_buf_size =
2788                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2789         else
2790                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2791
2792         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2793
2794         if (req->dv_buf_size)
2795                 pf->dv_buf_size =
2796                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2797         else
2798                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2799
2800         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2801
2802         hw->num_msi =
2803                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2804                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2805
2806         return 0;
2807 }
2808
2809 static void
2810 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2811 {
2812         struct hns3_cfg_param_cmd *req;
2813         uint64_t mac_addr_tmp_high;
2814         uint8_t ext_rss_size_max;
2815         uint64_t mac_addr_tmp;
2816         uint32_t i;
2817
2818         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2819
2820         /* get the configuration */
2821         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2822                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2823         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2824                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2825         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2826                                            HNS3_CFG_TQP_DESC_N_M,
2827                                            HNS3_CFG_TQP_DESC_N_S);
2828
2829         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2830                                        HNS3_CFG_PHY_ADDR_M,
2831                                        HNS3_CFG_PHY_ADDR_S);
2832         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2833                                          HNS3_CFG_MEDIA_TP_M,
2834                                          HNS3_CFG_MEDIA_TP_S);
2835         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2836                                          HNS3_CFG_RX_BUF_LEN_M,
2837                                          HNS3_CFG_RX_BUF_LEN_S);
2838         /* get mac address */
2839         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2840         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2841                                            HNS3_CFG_MAC_ADDR_H_M,
2842                                            HNS3_CFG_MAC_ADDR_H_S);
2843
2844         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2845
2846         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2847                                             HNS3_CFG_DEFAULT_SPEED_M,
2848                                             HNS3_CFG_DEFAULT_SPEED_S);
2849         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2850                                            HNS3_CFG_RSS_SIZE_M,
2851                                            HNS3_CFG_RSS_SIZE_S);
2852
2853         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2854                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2855
2856         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2857         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2858
2859         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2860                                             HNS3_CFG_SPEED_ABILITY_M,
2861                                             HNS3_CFG_SPEED_ABILITY_S);
2862         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2863                                         HNS3_CFG_UMV_TBL_SPACE_M,
2864                                         HNS3_CFG_UMV_TBL_SPACE_S);
2865         if (!cfg->umv_space)
2866                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2867
2868         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2869                                                HNS3_CFG_EXT_RSS_SIZE_M,
2870                                                HNS3_CFG_EXT_RSS_SIZE_S);
2871
2872         /*
2873          * Field ext_rss_size_max obtained from firmware will be more flexible
2874          * for future changes and expansions, which is an exponent of 2, instead
2875          * of reading out directly. If this field is not zero, hns3 PF PMD
2876          * driver uses it as rss_size_max under one TC. Device, whose revision
2877          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2878          * maximum number of queues supported under a TC through this field.
2879          */
2880         if (ext_rss_size_max)
2881                 cfg->rss_size_max = 1U << ext_rss_size_max;
2882 }
2883
2884 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2885  * @hw: pointer to struct hns3_hw
2886  * @hcfg: the config structure to be getted
2887  */
2888 static int
2889 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2890 {
2891         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2892         struct hns3_cfg_param_cmd *req;
2893         uint32_t offset;
2894         uint32_t i;
2895         int ret;
2896
2897         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2898                 offset = 0;
2899                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2900                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2901                                           true);
2902                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2903                                i * HNS3_CFG_RD_LEN_BYTES);
2904                 /* Len should be divided by 4 when send to hardware */
2905                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2906                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2907                 req->offset = rte_cpu_to_le_32(offset);
2908         }
2909
2910         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2911         if (ret) {
2912                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2913                 return ret;
2914         }
2915
2916         hns3_parse_cfg(hcfg, desc);
2917
2918         return 0;
2919 }
2920
2921 static int
2922 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2923 {
2924         switch (speed_cmd) {
2925         case HNS3_CFG_SPEED_10M:
2926                 *speed = ETH_SPEED_NUM_10M;
2927                 break;
2928         case HNS3_CFG_SPEED_100M:
2929                 *speed = ETH_SPEED_NUM_100M;
2930                 break;
2931         case HNS3_CFG_SPEED_1G:
2932                 *speed = ETH_SPEED_NUM_1G;
2933                 break;
2934         case HNS3_CFG_SPEED_10G:
2935                 *speed = ETH_SPEED_NUM_10G;
2936                 break;
2937         case HNS3_CFG_SPEED_25G:
2938                 *speed = ETH_SPEED_NUM_25G;
2939                 break;
2940         case HNS3_CFG_SPEED_40G:
2941                 *speed = ETH_SPEED_NUM_40G;
2942                 break;
2943         case HNS3_CFG_SPEED_50G:
2944                 *speed = ETH_SPEED_NUM_50G;
2945                 break;
2946         case HNS3_CFG_SPEED_100G:
2947                 *speed = ETH_SPEED_NUM_100G;
2948                 break;
2949         case HNS3_CFG_SPEED_200G:
2950                 *speed = ETH_SPEED_NUM_200G;
2951                 break;
2952         default:
2953                 return -EINVAL;
2954         }
2955
2956         return 0;
2957 }
2958
2959 static void
2960 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2961 {
2962         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2963         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2964         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2965         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2966         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2967 }
2968
2969 static void
2970 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2971 {
2972         struct hns3_dev_specs_0_cmd *req0;
2973
2974         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2975
2976         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2977         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2978         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2979         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2980         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2981 }
2982
2983 static int
2984 hns3_query_dev_specifications(struct hns3_hw *hw)
2985 {
2986         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2987         int ret;
2988         int i;
2989
2990         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2991                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2992                                           true);
2993                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2994         }
2995         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2996
2997         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2998         if (ret)
2999                 return ret;
3000
3001         hns3_parse_dev_specifications(hw, desc);
3002
3003         return 0;
3004 }
3005
3006 static int
3007 hns3_get_capability(struct hns3_hw *hw)
3008 {
3009         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3010         struct rte_pci_device *pci_dev;
3011         struct hns3_pf *pf = &hns->pf;
3012         struct rte_eth_dev *eth_dev;
3013         uint16_t device_id;
3014         uint8_t revision;
3015         int ret;
3016
3017         eth_dev = &rte_eth_devices[hw->data->port_id];
3018         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3019         device_id = pci_dev->id.device_id;
3020
3021         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3022             device_id == HNS3_DEV_ID_50GE_RDMA ||
3023             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3024             device_id == HNS3_DEV_ID_200G_RDMA)
3025                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3026
3027         /* Get PCI revision id */
3028         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3029                                   HNS3_PCI_REVISION_ID);
3030         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3031                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3032                              ret);
3033                 return -EIO;
3034         }
3035         hw->revision = revision;
3036
3037         if (revision < PCI_REVISION_ID_HIP09_A) {
3038                 hns3_set_default_dev_specifications(hw);
3039                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3040                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3041                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3042                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3043                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3044                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3045                 hw->rss_info.ipv6_sctp_offload_supported = false;
3046                 return 0;
3047         }
3048
3049         ret = hns3_query_dev_specifications(hw);
3050         if (ret) {
3051                 PMD_INIT_LOG(ERR,
3052                              "failed to query dev specifications, ret = %d",
3053                              ret);
3054                 return ret;
3055         }
3056
3057         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3058         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3059         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3060         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3061         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3062         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3063         hw->rss_info.ipv6_sctp_offload_supported = true;
3064
3065         return 0;
3066 }
3067
3068 static int
3069 hns3_get_board_configuration(struct hns3_hw *hw)
3070 {
3071         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3072         struct hns3_pf *pf = &hns->pf;
3073         struct hns3_cfg cfg;
3074         int ret;
3075
3076         ret = hns3_get_board_cfg(hw, &cfg);
3077         if (ret) {
3078                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3079                 return ret;
3080         }
3081
3082         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
3083             !hns3_dev_copper_supported(hw)) {
3084                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
3085                 return -EOPNOTSUPP;
3086         }
3087
3088         hw->mac.media_type = cfg.media_type;
3089         hw->rss_size_max = cfg.rss_size_max;
3090         hw->rss_dis_flag = false;
3091         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3092         hw->mac.phy_addr = cfg.phy_addr;
3093         hw->mac.default_addr_setted = false;
3094         hw->num_tx_desc = cfg.tqp_desc_num;
3095         hw->num_rx_desc = cfg.tqp_desc_num;
3096         hw->dcb_info.num_pg = 1;
3097         hw->dcb_info.hw_pfc_map = 0;
3098
3099         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3100         if (ret) {
3101                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3102                              cfg.default_speed, ret);
3103                 return ret;
3104         }
3105
3106         pf->tc_max = cfg.tc_num;
3107         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3108                 PMD_INIT_LOG(WARNING,
3109                              "Get TC num(%u) from flash, set TC num to 1",
3110                              pf->tc_max);
3111                 pf->tc_max = 1;
3112         }
3113
3114         /* Dev does not support DCB */
3115         if (!hns3_dev_dcb_supported(hw)) {
3116                 pf->tc_max = 1;
3117                 pf->pfc_max = 0;
3118         } else
3119                 pf->pfc_max = pf->tc_max;
3120
3121         hw->dcb_info.num_tc = 1;
3122         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3123                                      hw->tqps_num / hw->dcb_info.num_tc);
3124         hns3_set_bit(hw->hw_tc_map, 0, 1);
3125         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3126
3127         pf->wanted_umv_size = cfg.umv_space;
3128
3129         return ret;
3130 }
3131
3132 static int
3133 hns3_get_configuration(struct hns3_hw *hw)
3134 {
3135         int ret;
3136
3137         ret = hns3_query_function_status(hw);
3138         if (ret) {
3139                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3140                 return ret;
3141         }
3142
3143         /* Get device capability */
3144         ret = hns3_get_capability(hw);
3145         if (ret) {
3146                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3147                 return ret;
3148         }
3149
3150         /* Get pf resource */
3151         ret = hns3_query_pf_resource(hw);
3152         if (ret) {
3153                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3154                 return ret;
3155         }
3156
3157         ret = hns3_get_board_configuration(hw);
3158         if (ret) {
3159                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3160                 return ret;
3161         }
3162
3163         ret = hns3_query_dev_fec_info(hw);
3164         if (ret)
3165                 PMD_INIT_LOG(ERR,
3166                              "failed to query FEC information, ret = %d", ret);
3167
3168         return ret;
3169 }
3170
3171 static int
3172 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3173                       uint16_t tqp_vid, bool is_pf)
3174 {
3175         struct hns3_tqp_map_cmd *req;
3176         struct hns3_cmd_desc desc;
3177         int ret;
3178
3179         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3180
3181         req = (struct hns3_tqp_map_cmd *)desc.data;
3182         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3183         req->tqp_vf = func_id;
3184         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3185         if (!is_pf)
3186                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3187         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3188
3189         ret = hns3_cmd_send(hw, &desc, 1);
3190         if (ret)
3191                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3192
3193         return ret;
3194 }
3195
3196 static int
3197 hns3_map_tqp(struct hns3_hw *hw)
3198 {
3199         int ret;
3200         int i;
3201
3202         /*
3203          * In current version, VF is not supported when PF is driven by DPDK
3204          * driver, so we assign total tqps_num tqps allocated to this port
3205          * to PF.
3206          */
3207         for (i = 0; i < hw->total_tqps_num; i++) {
3208                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3209                 if (ret)
3210                         return ret;
3211         }
3212
3213         return 0;
3214 }
3215
3216 static int
3217 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3218 {
3219         struct hns3_config_mac_speed_dup_cmd *req;
3220         struct hns3_cmd_desc desc;
3221         int ret;
3222
3223         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3224
3225         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3226
3227         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3228
3229         switch (speed) {
3230         case ETH_SPEED_NUM_10M:
3231                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3232                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3233                 break;
3234         case ETH_SPEED_NUM_100M:
3235                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3236                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3237                 break;
3238         case ETH_SPEED_NUM_1G:
3239                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3240                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3241                 break;
3242         case ETH_SPEED_NUM_10G:
3243                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3244                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3245                 break;
3246         case ETH_SPEED_NUM_25G:
3247                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3248                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3249                 break;
3250         case ETH_SPEED_NUM_40G:
3251                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3252                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3253                 break;
3254         case ETH_SPEED_NUM_50G:
3255                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3256                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3257                 break;
3258         case ETH_SPEED_NUM_100G:
3259                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3260                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3261                 break;
3262         case ETH_SPEED_NUM_200G:
3263                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3264                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3265                 break;
3266         default:
3267                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3268                 return -EINVAL;
3269         }
3270
3271         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3272
3273         ret = hns3_cmd_send(hw, &desc, 1);
3274         if (ret)
3275                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3276
3277         return ret;
3278 }
3279
3280 static int
3281 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3282 {
3283         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3284         struct hns3_pf *pf = &hns->pf;
3285         struct hns3_priv_buf *priv;
3286         uint32_t i, total_size;
3287
3288         total_size = pf->pkt_buf_size;
3289
3290         /* alloc tx buffer for all enabled tc */
3291         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3292                 priv = &buf_alloc->priv_buf[i];
3293
3294                 if (hw->hw_tc_map & BIT(i)) {
3295                         if (total_size < pf->tx_buf_size)
3296                                 return -ENOMEM;
3297
3298                         priv->tx_buf_size = pf->tx_buf_size;
3299                 } else
3300                         priv->tx_buf_size = 0;
3301
3302                 total_size -= priv->tx_buf_size;
3303         }
3304
3305         return 0;
3306 }
3307
3308 static int
3309 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3310 {
3311 /* TX buffer size is unit by 128 byte */
3312 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3313 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3314         struct hns3_tx_buff_alloc_cmd *req;
3315         struct hns3_cmd_desc desc;
3316         uint32_t buf_size;
3317         uint32_t i;
3318         int ret;
3319
3320         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3321
3322         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3323         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3324                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3325
3326                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3327                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3328                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3329         }
3330
3331         ret = hns3_cmd_send(hw, &desc, 1);
3332         if (ret)
3333                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3334
3335         return ret;
3336 }
3337
3338 static int
3339 hns3_get_tc_num(struct hns3_hw *hw)
3340 {
3341         int cnt = 0;
3342         uint8_t i;
3343
3344         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3345                 if (hw->hw_tc_map & BIT(i))
3346                         cnt++;
3347         return cnt;
3348 }
3349
3350 static uint32_t
3351 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3352 {
3353         struct hns3_priv_buf *priv;
3354         uint32_t rx_priv = 0;
3355         int i;
3356
3357         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3358                 priv = &buf_alloc->priv_buf[i];
3359                 if (priv->enable)
3360                         rx_priv += priv->buf_size;
3361         }
3362         return rx_priv;
3363 }
3364
3365 static uint32_t
3366 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3367 {
3368         uint32_t total_tx_size = 0;
3369         uint32_t i;
3370
3371         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3372                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3373
3374         return total_tx_size;
3375 }
3376
3377 /* Get the number of pfc enabled TCs, which have private buffer */
3378 static int
3379 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3380 {
3381         struct hns3_priv_buf *priv;
3382         int cnt = 0;
3383         uint8_t i;
3384
3385         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3386                 priv = &buf_alloc->priv_buf[i];
3387                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3388                         cnt++;
3389         }
3390
3391         return cnt;
3392 }
3393
3394 /* Get the number of pfc disabled TCs, which have private buffer */
3395 static int
3396 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3397                          struct hns3_pkt_buf_alloc *buf_alloc)
3398 {
3399         struct hns3_priv_buf *priv;
3400         int cnt = 0;
3401         uint8_t i;
3402
3403         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3404                 priv = &buf_alloc->priv_buf[i];
3405                 if (hw->hw_tc_map & BIT(i) &&
3406                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3407                         cnt++;
3408         }
3409
3410         return cnt;
3411 }
3412
3413 static bool
3414 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3415                   uint32_t rx_all)
3416 {
3417         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3418         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3419         struct hns3_pf *pf = &hns->pf;
3420         uint32_t shared_buf, aligned_mps;
3421         uint32_t rx_priv;
3422         uint8_t tc_num;
3423         uint8_t i;
3424
3425         tc_num = hns3_get_tc_num(hw);
3426         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3427
3428         if (hns3_dev_dcb_supported(hw))
3429                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3430                                         pf->dv_buf_size;
3431         else
3432                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3433                                         + pf->dv_buf_size;
3434
3435         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3436         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3437                              HNS3_BUF_SIZE_UNIT);
3438
3439         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3440         if (rx_all < rx_priv + shared_std)
3441                 return false;
3442
3443         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3444         buf_alloc->s_buf.buf_size = shared_buf;
3445         if (hns3_dev_dcb_supported(hw)) {
3446                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3447                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3448                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3449                                   HNS3_BUF_SIZE_UNIT);
3450         } else {
3451                 buf_alloc->s_buf.self.high =
3452                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3453                 buf_alloc->s_buf.self.low = aligned_mps;
3454         }
3455
3456         if (hns3_dev_dcb_supported(hw)) {
3457                 hi_thrd = shared_buf - pf->dv_buf_size;
3458
3459                 if (tc_num <= NEED_RESERVE_TC_NUM)
3460                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3461                                   BUF_MAX_PERCENT;
3462
3463                 if (tc_num)
3464                         hi_thrd = hi_thrd / tc_num;
3465
3466                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3467                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3468                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3469         } else {
3470                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3471                 lo_thrd = aligned_mps;
3472         }
3473
3474         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3475                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3476                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3477         }
3478
3479         return true;
3480 }
3481
3482 static bool
3483 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3484                      struct hns3_pkt_buf_alloc *buf_alloc)
3485 {
3486         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3487         struct hns3_pf *pf = &hns->pf;
3488         struct hns3_priv_buf *priv;
3489         uint32_t aligned_mps;
3490         uint32_t rx_all;
3491         uint8_t i;
3492
3493         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3494         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3495
3496         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3497                 priv = &buf_alloc->priv_buf[i];
3498
3499                 priv->enable = 0;
3500                 priv->wl.low = 0;
3501                 priv->wl.high = 0;
3502                 priv->buf_size = 0;
3503
3504                 if (!(hw->hw_tc_map & BIT(i)))
3505                         continue;
3506
3507                 priv->enable = 1;
3508                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3509                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3510                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3511                                                 HNS3_BUF_SIZE_UNIT);
3512                 } else {
3513                         priv->wl.low = 0;
3514                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3515                                         aligned_mps;
3516                 }
3517
3518                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3519         }
3520
3521         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3522 }
3523
3524 static bool
3525 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3526                              struct hns3_pkt_buf_alloc *buf_alloc)
3527 {
3528         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3529         struct hns3_pf *pf = &hns->pf;
3530         struct hns3_priv_buf *priv;
3531         int no_pfc_priv_num;
3532         uint32_t rx_all;
3533         uint8_t mask;
3534         int i;
3535
3536         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3537         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3538
3539         /* let the last to be cleared first */
3540         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3541                 priv = &buf_alloc->priv_buf[i];
3542                 mask = BIT((uint8_t)i);
3543
3544                 if (hw->hw_tc_map & mask &&
3545                     !(hw->dcb_info.hw_pfc_map & mask)) {
3546                         /* Clear the no pfc TC private buffer */
3547                         priv->wl.low = 0;
3548                         priv->wl.high = 0;
3549                         priv->buf_size = 0;
3550                         priv->enable = 0;
3551                         no_pfc_priv_num--;
3552                 }
3553
3554                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3555                     no_pfc_priv_num == 0)
3556                         break;
3557         }
3558
3559         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3560 }
3561
3562 static bool
3563 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3564                            struct hns3_pkt_buf_alloc *buf_alloc)
3565 {
3566         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3567         struct hns3_pf *pf = &hns->pf;
3568         struct hns3_priv_buf *priv;
3569         uint32_t rx_all;
3570         int pfc_priv_num;
3571         uint8_t mask;
3572         int i;
3573
3574         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3575         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3576
3577         /* let the last to be cleared first */
3578         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3579                 priv = &buf_alloc->priv_buf[i];
3580                 mask = BIT((uint8_t)i);
3581                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3582                         /* Reduce the number of pfc TC with private buffer */
3583                         priv->wl.low = 0;
3584                         priv->enable = 0;
3585                         priv->wl.high = 0;
3586                         priv->buf_size = 0;
3587                         pfc_priv_num--;
3588                 }
3589                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3590                     pfc_priv_num == 0)
3591                         break;
3592         }
3593
3594         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3595 }
3596
3597 static bool
3598 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3599                           struct hns3_pkt_buf_alloc *buf_alloc)
3600 {
3601 #define COMPENSATE_BUFFER       0x3C00
3602 #define COMPENSATE_HALF_MPS_NUM 5
3603 #define PRIV_WL_GAP             0x1800
3604         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3605         struct hns3_pf *pf = &hns->pf;
3606         uint32_t tc_num = hns3_get_tc_num(hw);
3607         uint32_t half_mps = pf->mps >> 1;
3608         struct hns3_priv_buf *priv;
3609         uint32_t min_rx_priv;
3610         uint32_t rx_priv;
3611         uint8_t i;
3612
3613         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3614         if (tc_num)
3615                 rx_priv = rx_priv / tc_num;
3616
3617         if (tc_num <= NEED_RESERVE_TC_NUM)
3618                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3619
3620         /*
3621          * Minimum value of private buffer in rx direction (min_rx_priv) is
3622          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3623          * buffer if rx_priv is greater than min_rx_priv.
3624          */
3625         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3626                         COMPENSATE_HALF_MPS_NUM * half_mps;
3627         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3628         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3629
3630         if (rx_priv < min_rx_priv)
3631                 return false;
3632
3633         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3634                 priv = &buf_alloc->priv_buf[i];
3635                 priv->enable = 0;
3636                 priv->wl.low = 0;
3637                 priv->wl.high = 0;
3638                 priv->buf_size = 0;
3639
3640                 if (!(hw->hw_tc_map & BIT(i)))
3641                         continue;
3642
3643                 priv->enable = 1;
3644                 priv->buf_size = rx_priv;
3645                 priv->wl.high = rx_priv - pf->dv_buf_size;
3646                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3647         }
3648
3649         buf_alloc->s_buf.buf_size = 0;
3650
3651         return true;
3652 }
3653
3654 /*
3655  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3656  * @hw: pointer to struct hns3_hw
3657  * @buf_alloc: pointer to buffer calculation data
3658  * @return: 0: calculate sucessful, negative: fail
3659  */
3660 static int
3661 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3662 {
3663         /* When DCB is not supported, rx private buffer is not allocated. */
3664         if (!hns3_dev_dcb_supported(hw)) {
3665                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3666                 struct hns3_pf *pf = &hns->pf;
3667                 uint32_t rx_all = pf->pkt_buf_size;
3668
3669                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3670                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3671                         return -ENOMEM;
3672
3673                 return 0;
3674         }
3675
3676         /*
3677          * Try to allocate privated packet buffer for all TCs without share
3678          * buffer.
3679          */
3680         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3681                 return 0;
3682
3683         /*
3684          * Try to allocate privated packet buffer for all TCs with share
3685          * buffer.
3686          */
3687         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3688                 return 0;
3689
3690         /*
3691          * For different application scenes, the enabled port number, TC number
3692          * and no_drop TC number are different. In order to obtain the better
3693          * performance, software could allocate the buffer size and configure
3694          * the waterline by tring to decrease the private buffer size according
3695          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3696          * enabled tc.
3697          */
3698         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3699                 return 0;
3700
3701         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3702                 return 0;
3703
3704         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3705                 return 0;
3706
3707         return -ENOMEM;
3708 }
3709
3710 static int
3711 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3712 {
3713         struct hns3_rx_priv_buff_cmd *req;
3714         struct hns3_cmd_desc desc;
3715         uint32_t buf_size;
3716         int ret;
3717         int i;
3718
3719         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3720         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3721
3722         /* Alloc private buffer TCs */
3723         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3724                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3725
3726                 req->buf_num[i] =
3727                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3728                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3729         }
3730
3731         buf_size = buf_alloc->s_buf.buf_size;
3732         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3733                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3734
3735         ret = hns3_cmd_send(hw, &desc, 1);
3736         if (ret)
3737                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3738
3739         return ret;
3740 }
3741
3742 static int
3743 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3744 {
3745 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3746         struct hns3_rx_priv_wl_buf *req;
3747         struct hns3_priv_buf *priv;
3748         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3749         int i, j;
3750         int ret;
3751
3752         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3753                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3754                                           false);
3755                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3756
3757                 /* The first descriptor set the NEXT bit to 1 */
3758                 if (i == 0)
3759                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3760                 else
3761                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3762
3763                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3764                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3765
3766                         priv = &buf_alloc->priv_buf[idx];
3767                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3768                                                         HNS3_BUF_UNIT_S);
3769                         req->tc_wl[j].high |=
3770                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3771                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3772                                                         HNS3_BUF_UNIT_S);
3773                         req->tc_wl[j].low |=
3774                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3775                 }
3776         }
3777
3778         /* Send 2 descriptor at one time */
3779         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3780         if (ret)
3781                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3782                              ret);
3783         return ret;
3784 }
3785
3786 static int
3787 hns3_common_thrd_config(struct hns3_hw *hw,
3788                         struct hns3_pkt_buf_alloc *buf_alloc)
3789 {
3790 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3791         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3792         struct hns3_rx_com_thrd *req;
3793         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3794         struct hns3_tc_thrd *tc;
3795         int tc_idx;
3796         int i, j;
3797         int ret;
3798
3799         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3800                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3801                                           false);
3802                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3803
3804                 /* The first descriptor set the NEXT bit to 1 */
3805                 if (i == 0)
3806                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3807                 else
3808                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3809
3810                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3811                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3812                         tc = &s_buf->tc_thrd[tc_idx];
3813
3814                         req->com_thrd[j].high =
3815                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3816                         req->com_thrd[j].high |=
3817                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3818                         req->com_thrd[j].low =
3819                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3820                         req->com_thrd[j].low |=
3821                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3822                 }
3823         }
3824
3825         /* Send 2 descriptors at one time */
3826         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3827         if (ret)
3828                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3829
3830         return ret;
3831 }
3832
3833 static int
3834 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3835 {
3836         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3837         struct hns3_rx_com_wl *req;
3838         struct hns3_cmd_desc desc;
3839         int ret;
3840
3841         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3842
3843         req = (struct hns3_rx_com_wl *)desc.data;
3844         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3845         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3846
3847         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3848         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3849
3850         ret = hns3_cmd_send(hw, &desc, 1);
3851         if (ret)
3852                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3853
3854         return ret;
3855 }
3856
3857 int
3858 hns3_buffer_alloc(struct hns3_hw *hw)
3859 {
3860         struct hns3_pkt_buf_alloc pkt_buf;
3861         int ret;
3862
3863         memset(&pkt_buf, 0, sizeof(pkt_buf));
3864         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3865         if (ret) {
3866                 PMD_INIT_LOG(ERR,
3867                              "could not calc tx buffer size for all TCs %d",
3868                              ret);
3869                 return ret;
3870         }
3871
3872         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3873         if (ret) {
3874                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3875                 return ret;
3876         }
3877
3878         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3879         if (ret) {
3880                 PMD_INIT_LOG(ERR,
3881                              "could not calc rx priv buffer size for all TCs %d",
3882                              ret);
3883                 return ret;
3884         }
3885
3886         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3887         if (ret) {
3888                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3889                 return ret;
3890         }
3891
3892         if (hns3_dev_dcb_supported(hw)) {
3893                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3894                 if (ret) {
3895                         PMD_INIT_LOG(ERR,
3896                                      "could not configure rx private waterline %d",
3897                                      ret);
3898                         return ret;
3899                 }
3900
3901                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3902                 if (ret) {
3903                         PMD_INIT_LOG(ERR,
3904                                      "could not configure common threshold %d",
3905                                      ret);
3906                         return ret;
3907                 }
3908         }
3909
3910         ret = hns3_common_wl_config(hw, &pkt_buf);
3911         if (ret)
3912                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3913                              ret);
3914
3915         return ret;
3916 }
3917
3918 static int
3919 hns3_mac_init(struct hns3_hw *hw)
3920 {
3921         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3922         struct hns3_mac *mac = &hw->mac;
3923         struct hns3_pf *pf = &hns->pf;
3924         int ret;
3925
3926         pf->support_sfp_query = true;
3927         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3928         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3929         if (ret) {
3930                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3931                 return ret;
3932         }
3933
3934         mac->link_status = ETH_LINK_DOWN;
3935
3936         return hns3_config_mtu(hw, pf->mps);
3937 }
3938
3939 static int
3940 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3941 {
3942 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3943 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3944 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3945 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3946         int return_status;
3947
3948         if (cmdq_resp) {
3949                 PMD_INIT_LOG(ERR,
3950                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3951                              cmdq_resp);
3952                 return -EIO;
3953         }
3954
3955         switch (resp_code) {
3956         case HNS3_ETHERTYPE_SUCCESS_ADD:
3957         case HNS3_ETHERTYPE_ALREADY_ADD:
3958                 return_status = 0;
3959                 break;
3960         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3961                 PMD_INIT_LOG(ERR,
3962                              "add mac ethertype failed for manager table overflow.");
3963                 return_status = -EIO;
3964                 break;
3965         case HNS3_ETHERTYPE_KEY_CONFLICT:
3966                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3967                 return_status = -EIO;
3968                 break;
3969         default:
3970                 PMD_INIT_LOG(ERR,
3971                              "add mac ethertype failed for undefined, code=%u.",
3972                              resp_code);
3973                 return_status = -EIO;
3974                 break;
3975         }
3976
3977         return return_status;
3978 }
3979
3980 static int
3981 hns3_add_mgr_tbl(struct hns3_hw *hw,
3982                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3983 {
3984         struct hns3_cmd_desc desc;
3985         uint8_t resp_code;
3986         uint16_t retval;
3987         int ret;
3988
3989         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3990         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3991
3992         ret = hns3_cmd_send(hw, &desc, 1);
3993         if (ret) {
3994                 PMD_INIT_LOG(ERR,
3995                              "add mac ethertype failed for cmd_send, ret =%d.",
3996                              ret);
3997                 return ret;
3998         }
3999
4000         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4001         retval = rte_le_to_cpu_16(desc.retval);
4002
4003         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4004 }
4005
4006 static void
4007 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4008                      int *table_item_num)
4009 {
4010         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4011
4012         /*
4013          * In current version, we add one item in management table as below:
4014          * 0x0180C200000E -- LLDP MC address
4015          */
4016         tbl = mgr_table;
4017         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4018         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4019         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4020         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4021         tbl->i_port_bitmap = 0x1;
4022         *table_item_num = 1;
4023 }
4024
4025 static int
4026 hns3_init_mgr_tbl(struct hns3_hw *hw)
4027 {
4028 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4029         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4030         int table_item_num;
4031         int ret;
4032         int i;
4033
4034         memset(mgr_table, 0, sizeof(mgr_table));
4035         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4036         for (i = 0; i < table_item_num; i++) {
4037                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4038                 if (ret) {
4039                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4040                                      ret);
4041                         return ret;
4042                 }
4043         }
4044
4045         return 0;
4046 }
4047
4048 static void
4049 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4050                         bool en_mc, bool en_bc, int vport_id)
4051 {
4052         if (!param)
4053                 return;
4054
4055         memset(param, 0, sizeof(struct hns3_promisc_param));
4056         if (en_uc)
4057                 param->enable = HNS3_PROMISC_EN_UC;
4058         if (en_mc)
4059                 param->enable |= HNS3_PROMISC_EN_MC;
4060         if (en_bc)
4061                 param->enable |= HNS3_PROMISC_EN_BC;
4062         param->vf_id = vport_id;
4063 }
4064
4065 static int
4066 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4067 {
4068         struct hns3_promisc_cfg_cmd *req;
4069         struct hns3_cmd_desc desc;
4070         int ret;
4071
4072         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4073
4074         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4075         req->vf_id = param->vf_id;
4076         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4077             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4078
4079         ret = hns3_cmd_send(hw, &desc, 1);
4080         if (ret)
4081                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4082
4083         return ret;
4084 }
4085
4086 static int
4087 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4088 {
4089         struct hns3_promisc_param param;
4090         bool en_bc_pmc = true;
4091         uint8_t vf_id;
4092
4093         /*
4094          * In current version VF is not supported when PF is driven by DPDK
4095          * driver, just need to configure parameters for PF vport.
4096          */
4097         vf_id = HNS3_PF_FUNC_ID;
4098
4099         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4100         return hns3_cmd_set_promisc_mode(hw, &param);
4101 }
4102
4103 static int
4104 hns3_promisc_init(struct hns3_hw *hw)
4105 {
4106         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4107         struct hns3_pf *pf = &hns->pf;
4108         struct hns3_promisc_param param;
4109         uint16_t func_id;
4110         int ret;
4111
4112         ret = hns3_set_promisc_mode(hw, false, false);
4113         if (ret) {
4114                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4115                 return ret;
4116         }
4117
4118         /*
4119          * In current version VFs are not supported when PF is driven by DPDK
4120          * driver. After PF has been taken over by DPDK, the original VF will
4121          * be invalid. So, there is a possibility of entry residues. It should
4122          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4123          * during init.
4124          */
4125         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4126                 hns3_promisc_param_init(&param, false, false, false, func_id);
4127                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4128                 if (ret) {
4129                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4130                                         " ret = %d", func_id, ret);
4131                         return ret;
4132                 }
4133         }
4134
4135         return 0;
4136 }
4137
4138 static void
4139 hns3_promisc_uninit(struct hns3_hw *hw)
4140 {
4141         struct hns3_promisc_param param;
4142         uint16_t func_id;
4143         int ret;
4144
4145         func_id = HNS3_PF_FUNC_ID;
4146
4147         /*
4148          * In current version VFs are not supported when PF is driven by
4149          * DPDK driver, and VFs' promisc mode status has been cleared during
4150          * init and their status will not change. So just clear PF's promisc
4151          * mode status during uninit.
4152          */
4153         hns3_promisc_param_init(&param, false, false, false, func_id);
4154         ret = hns3_cmd_set_promisc_mode(hw, &param);
4155         if (ret)
4156                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4157                                 " uninit, ret = %d", ret);
4158 }
4159
4160 static int
4161 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4162 {
4163         bool allmulti = dev->data->all_multicast ? true : false;
4164         struct hns3_adapter *hns = dev->data->dev_private;
4165         struct hns3_hw *hw = &hns->hw;
4166         uint64_t offloads;
4167         int err;
4168         int ret;
4169
4170         rte_spinlock_lock(&hw->lock);
4171         ret = hns3_set_promisc_mode(hw, true, true);
4172         if (ret) {
4173                 rte_spinlock_unlock(&hw->lock);
4174                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4175                          ret);
4176                 return ret;
4177         }
4178
4179         /*
4180          * When promiscuous mode was enabled, disable the vlan filter to let
4181          * all packets coming in in the receiving direction.
4182          */
4183         offloads = dev->data->dev_conf.rxmode.offloads;
4184         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4185                 ret = hns3_enable_vlan_filter(hns, false);
4186                 if (ret) {
4187                         hns3_err(hw, "failed to enable promiscuous mode due to "
4188                                      "failure to disable vlan filter, ret = %d",
4189                                  ret);
4190                         err = hns3_set_promisc_mode(hw, false, allmulti);
4191                         if (err)
4192                                 hns3_err(hw, "failed to restore promiscuous "
4193                                          "status after disable vlan filter "
4194                                          "failed during enabling promiscuous "
4195                                          "mode, ret = %d", ret);
4196                 }
4197         }
4198
4199         rte_spinlock_unlock(&hw->lock);
4200
4201         return ret;
4202 }
4203
4204 static int
4205 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4206 {
4207         bool allmulti = dev->data->all_multicast ? true : false;
4208         struct hns3_adapter *hns = dev->data->dev_private;
4209         struct hns3_hw *hw = &hns->hw;
4210         uint64_t offloads;
4211         int err;
4212         int ret;
4213
4214         /* If now in all_multicast mode, must remain in all_multicast mode. */
4215         rte_spinlock_lock(&hw->lock);
4216         ret = hns3_set_promisc_mode(hw, false, allmulti);
4217         if (ret) {
4218                 rte_spinlock_unlock(&hw->lock);
4219                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4220                          ret);
4221                 return ret;
4222         }
4223         /* when promiscuous mode was disabled, restore the vlan filter status */
4224         offloads = dev->data->dev_conf.rxmode.offloads;
4225         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4226                 ret = hns3_enable_vlan_filter(hns, true);
4227                 if (ret) {
4228                         hns3_err(hw, "failed to disable promiscuous mode due to"
4229                                  " failure to restore vlan filter, ret = %d",
4230                                  ret);
4231                         err = hns3_set_promisc_mode(hw, true, true);
4232                         if (err)
4233                                 hns3_err(hw, "failed to restore promiscuous "
4234                                          "status after enabling vlan filter "
4235                                          "failed during disabling promiscuous "
4236                                          "mode, ret = %d", ret);
4237                 }
4238         }
4239         rte_spinlock_unlock(&hw->lock);
4240
4241         return ret;
4242 }
4243
4244 static int
4245 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4246 {
4247         struct hns3_adapter *hns = dev->data->dev_private;
4248         struct hns3_hw *hw = &hns->hw;
4249         int ret;
4250
4251         if (dev->data->promiscuous)
4252                 return 0;
4253
4254         rte_spinlock_lock(&hw->lock);
4255         ret = hns3_set_promisc_mode(hw, false, true);
4256         rte_spinlock_unlock(&hw->lock);
4257         if (ret)
4258                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4259                          ret);
4260
4261         return ret;
4262 }
4263
4264 static int
4265 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4266 {
4267         struct hns3_adapter *hns = dev->data->dev_private;
4268         struct hns3_hw *hw = &hns->hw;
4269         int ret;
4270
4271         /* If now in promiscuous mode, must remain in all_multicast mode. */
4272         if (dev->data->promiscuous)
4273                 return 0;
4274
4275         rte_spinlock_lock(&hw->lock);
4276         ret = hns3_set_promisc_mode(hw, false, false);
4277         rte_spinlock_unlock(&hw->lock);
4278         if (ret)
4279                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4280                          ret);
4281
4282         return ret;
4283 }
4284
4285 static int
4286 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4287 {
4288         struct hns3_hw *hw = &hns->hw;
4289         bool allmulti = hw->data->all_multicast ? true : false;
4290         int ret;
4291
4292         if (hw->data->promiscuous) {
4293                 ret = hns3_set_promisc_mode(hw, true, true);
4294                 if (ret)
4295                         hns3_err(hw, "failed to restore promiscuous mode, "
4296                                  "ret = %d", ret);
4297                 return ret;
4298         }
4299
4300         ret = hns3_set_promisc_mode(hw, false, allmulti);
4301         if (ret)
4302                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4303                          ret);
4304         return ret;
4305 }
4306
4307 static int
4308 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4309 {
4310         struct hns3_sfp_speed_cmd *resp;
4311         struct hns3_cmd_desc desc;
4312         int ret;
4313
4314         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4315         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4316         ret = hns3_cmd_send(hw, &desc, 1);
4317         if (ret == -EOPNOTSUPP) {
4318                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4319                 return ret;
4320         } else if (ret) {
4321                 hns3_err(hw, "get sfp speed failed %d", ret);
4322                 return ret;
4323         }
4324
4325         *speed = resp->sfp_speed;
4326
4327         return 0;
4328 }
4329
4330 static uint8_t
4331 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4332 {
4333         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4334                 duplex = ETH_LINK_FULL_DUPLEX;
4335
4336         return duplex;
4337 }
4338
4339 static int
4340 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4341 {
4342         struct hns3_mac *mac = &hw->mac;
4343         uint32_t cur_speed = mac->link_speed;
4344         int ret;
4345
4346         duplex = hns3_check_speed_dup(duplex, speed);
4347         if (mac->link_speed == speed && mac->link_duplex == duplex)
4348                 return 0;
4349
4350         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4351         if (ret)
4352                 return ret;
4353
4354         mac->link_speed = speed;
4355         ret = hns3_dcb_port_shaper_cfg(hw);
4356         if (ret) {
4357                 hns3_err(hw, "failed to configure port shaper, ret = %d.", ret);
4358                 mac->link_speed = cur_speed;
4359                 return ret;
4360         }
4361
4362         mac->link_duplex = duplex;
4363
4364         return 0;
4365 }
4366
4367 static int
4368 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4369 {
4370         struct hns3_adapter *hns = eth_dev->data->dev_private;
4371         struct hns3_hw *hw = &hns->hw;
4372         struct hns3_pf *pf = &hns->pf;
4373         uint32_t speed;
4374         int ret;
4375
4376         /* If IMP do not support get SFP/qSFP speed, return directly */
4377         if (!pf->support_sfp_query)
4378                 return 0;
4379
4380         ret = hns3_get_sfp_speed(hw, &speed);
4381         if (ret == -EOPNOTSUPP) {
4382                 pf->support_sfp_query = false;
4383                 return ret;
4384         } else if (ret)
4385                 return ret;
4386
4387         if (speed == ETH_SPEED_NUM_NONE)
4388                 return 0; /* do nothing if no SFP */
4389
4390         /* Config full duplex for SFP */
4391         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4392 }
4393
4394 static int
4395 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4396 {
4397         struct hns3_config_mac_mode_cmd *req;
4398         struct hns3_cmd_desc desc;
4399         uint32_t loop_en = 0;
4400         uint8_t val = 0;
4401         int ret;
4402
4403         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4404
4405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4406         if (enable)
4407                 val = 1;
4408         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4409         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4410         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4411         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4412         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4413         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4414         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4415         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4416         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4417         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4418
4419         /*
4420          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4421          * when receiving frames. Otherwise, CRC will be stripped.
4422          */
4423         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4424                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4425         else
4426                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4427         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4428         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4429         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4430         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4431
4432         ret = hns3_cmd_send(hw, &desc, 1);
4433         if (ret)
4434                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4435
4436         return ret;
4437 }
4438
4439 static int
4440 hns3_get_mac_link_status(struct hns3_hw *hw)
4441 {
4442         struct hns3_link_status_cmd *req;
4443         struct hns3_cmd_desc desc;
4444         int link_status;
4445         int ret;
4446
4447         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4448         ret = hns3_cmd_send(hw, &desc, 1);
4449         if (ret) {
4450                 hns3_err(hw, "get link status cmd failed %d", ret);
4451                 return ETH_LINK_DOWN;
4452         }
4453
4454         req = (struct hns3_link_status_cmd *)desc.data;
4455         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4456
4457         return !!link_status;
4458 }
4459
4460 void
4461 hns3_update_link_status(struct hns3_hw *hw)
4462 {
4463         int state;
4464
4465         state = hns3_get_mac_link_status(hw);
4466         if (state != hw->mac.link_status) {
4467                 hw->mac.link_status = state;
4468                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4469         }
4470 }
4471
4472 static void
4473 hns3_service_handler(void *param)
4474 {
4475         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4476         struct hns3_adapter *hns = eth_dev->data->dev_private;
4477         struct hns3_hw *hw = &hns->hw;
4478
4479         if (!hns3_is_reset_pending(hns)) {
4480                 hns3_update_speed_duplex(eth_dev);
4481                 hns3_update_link_status(hw);
4482         } else
4483                 hns3_warn(hw, "Cancel the query when reset is pending");
4484
4485         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4486 }
4487
4488 static int
4489 hns3_init_hardware(struct hns3_adapter *hns)
4490 {
4491         struct hns3_hw *hw = &hns->hw;
4492         int ret;
4493
4494         ret = hns3_map_tqp(hw);
4495         if (ret) {
4496                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4497                 return ret;
4498         }
4499
4500         ret = hns3_init_umv_space(hw);
4501         if (ret) {
4502                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4503                 return ret;
4504         }
4505
4506         ret = hns3_mac_init(hw);
4507         if (ret) {
4508                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4509                 goto err_mac_init;
4510         }
4511
4512         ret = hns3_init_mgr_tbl(hw);
4513         if (ret) {
4514                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4515                 goto err_mac_init;
4516         }
4517
4518         ret = hns3_promisc_init(hw);
4519         if (ret) {
4520                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4521                              ret);
4522                 goto err_mac_init;
4523         }
4524
4525         ret = hns3_init_vlan_config(hns);
4526         if (ret) {
4527                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4528                 goto err_mac_init;
4529         }
4530
4531         ret = hns3_dcb_init(hw);
4532         if (ret) {
4533                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4534                 goto err_mac_init;
4535         }
4536
4537         ret = hns3_init_fd_config(hns);
4538         if (ret) {
4539                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4540                 goto err_mac_init;
4541         }
4542
4543         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4544         if (ret) {
4545                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4546                 goto err_mac_init;
4547         }
4548
4549         ret = hns3_config_gro(hw, false);
4550         if (ret) {
4551                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4552                 goto err_mac_init;
4553         }
4554
4555         /*
4556          * In the initialization clearing the all hardware mapping relationship
4557          * configurations between queues and interrupt vectors is needed, so
4558          * some error caused by the residual configurations, such as the
4559          * unexpected interrupt, can be avoid.
4560          */
4561         ret = hns3_init_ring_with_vector(hw);
4562         if (ret) {
4563                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4564                 goto err_mac_init;
4565         }
4566
4567         return 0;
4568
4569 err_mac_init:
4570         hns3_uninit_umv_space(hw);
4571         return ret;
4572 }
4573
4574 static int
4575 hns3_clear_hw(struct hns3_hw *hw)
4576 {
4577         struct hns3_cmd_desc desc;
4578         int ret;
4579
4580         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4581
4582         ret = hns3_cmd_send(hw, &desc, 1);
4583         if (ret && ret != -EOPNOTSUPP)
4584                 return ret;
4585
4586         return 0;
4587 }
4588
4589 static void
4590 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4591 {
4592         uint32_t val;
4593
4594         /*
4595          * The new firmware support report more hardware error types by
4596          * msix mode. These errors are defined as RAS errors in hardware
4597          * and belong to a different type from the MSI-x errors processed
4598          * by the network driver.
4599          *
4600          * Network driver should open the new error report on initialition
4601          */
4602         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4603         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4604         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4605 }
4606
4607 static int
4608 hns3_init_pf(struct rte_eth_dev *eth_dev)
4609 {
4610         struct rte_device *dev = eth_dev->device;
4611         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4612         struct hns3_adapter *hns = eth_dev->data->dev_private;
4613         struct hns3_hw *hw = &hns->hw;
4614         int ret;
4615
4616         PMD_INIT_FUNC_TRACE();
4617
4618         /* Get hardware io base address from pcie BAR2 IO space */
4619         hw->io_base = pci_dev->mem_resource[2].addr;
4620
4621         /* Firmware command queue initialize */
4622         ret = hns3_cmd_init_queue(hw);
4623         if (ret) {
4624                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4625                 goto err_cmd_init_queue;
4626         }
4627
4628         hns3_clear_all_event_cause(hw);
4629
4630         /* Firmware command initialize */
4631         ret = hns3_cmd_init(hw);
4632         if (ret) {
4633                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4634                 goto err_cmd_init;
4635         }
4636
4637         /*
4638          * To ensure that the hardware environment is clean during
4639          * initialization, the driver actively clear the hardware environment
4640          * during initialization, including PF and corresponding VFs' vlan, mac,
4641          * flow table configurations, etc.
4642          */
4643         ret = hns3_clear_hw(hw);
4644         if (ret) {
4645                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4646                 goto err_cmd_init;
4647         }
4648
4649         hns3_config_all_msix_error(hw, true);
4650
4651         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4652                                          hns3_interrupt_handler,
4653                                          eth_dev);
4654         if (ret) {
4655                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4656                 goto err_intr_callback_register;
4657         }
4658
4659         /* Enable interrupt */
4660         rte_intr_enable(&pci_dev->intr_handle);
4661         hns3_pf_enable_irq0(hw);
4662
4663         /* Get configuration */
4664         ret = hns3_get_configuration(hw);
4665         if (ret) {
4666                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4667                 goto err_get_config;
4668         }
4669
4670         ret = hns3_tqp_stats_init(hw);
4671         if (ret)
4672                 goto err_get_config;
4673
4674         ret = hns3_init_hardware(hns);
4675         if (ret) {
4676                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4677                 goto err_init_hw;
4678         }
4679
4680         /* Initialize flow director filter list & hash */
4681         ret = hns3_fdir_filter_init(hns);
4682         if (ret) {
4683                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4684                 goto err_fdir;
4685         }
4686
4687         hns3_set_default_rss_args(hw);
4688
4689         ret = hns3_enable_hw_error_intr(hns, true);
4690         if (ret) {
4691                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4692                              ret);
4693                 goto err_enable_intr;
4694         }
4695
4696         hns3_tm_conf_init(eth_dev);
4697
4698         return 0;
4699
4700 err_enable_intr:
4701         hns3_fdir_filter_uninit(hns);
4702 err_fdir:
4703         hns3_uninit_umv_space(hw);
4704 err_init_hw:
4705         hns3_tqp_stats_uninit(hw);
4706 err_get_config:
4707         hns3_pf_disable_irq0(hw);
4708         rte_intr_disable(&pci_dev->intr_handle);
4709         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4710                              eth_dev);
4711 err_intr_callback_register:
4712 err_cmd_init:
4713         hns3_cmd_uninit(hw);
4714         hns3_cmd_destroy_queue(hw);
4715 err_cmd_init_queue:
4716         hw->io_base = NULL;
4717
4718         return ret;
4719 }
4720
4721 static void
4722 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4723 {
4724         struct hns3_adapter *hns = eth_dev->data->dev_private;
4725         struct rte_device *dev = eth_dev->device;
4726         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4727         struct hns3_hw *hw = &hns->hw;
4728
4729         PMD_INIT_FUNC_TRACE();
4730
4731         hns3_tm_conf_uninit(eth_dev);
4732         hns3_enable_hw_error_intr(hns, false);
4733         hns3_rss_uninit(hns);
4734         (void)hns3_config_gro(hw, false);
4735         hns3_promisc_uninit(hw);
4736         hns3_fdir_filter_uninit(hns);
4737         hns3_uninit_umv_space(hw);
4738         hns3_tqp_stats_uninit(hw);
4739         hns3_pf_disable_irq0(hw);
4740         rte_intr_disable(&pci_dev->intr_handle);
4741         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4742                              eth_dev);
4743         hns3_config_all_msix_error(hw, false);
4744         hns3_cmd_uninit(hw);
4745         hns3_cmd_destroy_queue(hw);
4746         hw->io_base = NULL;
4747 }
4748
4749 static int
4750 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4751 {
4752         struct hns3_hw *hw = &hns->hw;
4753         int ret;
4754
4755         ret = hns3_dcb_cfg_update(hns);
4756         if (ret)
4757                 return ret;
4758
4759         /*
4760          * The hns3_dcb_cfg_update may configure TM module, so
4761          * hns3_tm_conf_update must called later.
4762          */
4763         ret = hns3_tm_conf_update(hw);
4764         if (ret) {
4765                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4766                 return ret;
4767         }
4768
4769         ret = hns3_init_queues(hns, reset_queue);
4770         if (ret) {
4771                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4772                 return ret;
4773         }
4774
4775         ret = hns3_cfg_mac_mode(hw, true);
4776         if (ret) {
4777                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
4778                 goto err_config_mac_mode;
4779         }
4780         return 0;
4781
4782 err_config_mac_mode:
4783         hns3_dev_release_mbufs(hns);
4784         /*
4785          * Here is exception handling, hns3_reset_all_tqps will have the
4786          * corresponding error message if it is handled incorrectly, so it is
4787          * not necessary to check hns3_reset_all_tqps return value, here keep
4788          * ret as the error code causing the exception.
4789          */
4790         (void)hns3_reset_all_tqps(hns);
4791         return ret;
4792 }
4793
4794 static int
4795 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4796 {
4797         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4798         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4799         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4801         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4802         uint32_t intr_vector;
4803         uint16_t q_id;
4804         int ret;
4805
4806         /*
4807          * hns3 needs a separate interrupt to be used as event interrupt which
4808          * could not be shared with task queue pair, so KERNEL drivers need
4809          * support multiple interrupt vectors.
4810          */
4811         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
4812             !rte_intr_cap_multiple(intr_handle))
4813                 return 0;
4814
4815         rte_intr_disable(intr_handle);
4816         intr_vector = hw->used_rx_queues;
4817         /* creates event fd for each intr vector when MSIX is used */
4818         if (rte_intr_efd_enable(intr_handle, intr_vector))
4819                 return -EINVAL;
4820
4821         if (intr_handle->intr_vec == NULL) {
4822                 intr_handle->intr_vec =
4823                         rte_zmalloc("intr_vec",
4824                                     hw->used_rx_queues * sizeof(int), 0);
4825                 if (intr_handle->intr_vec == NULL) {
4826                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
4827                                         hw->used_rx_queues);
4828                         ret = -ENOMEM;
4829                         goto alloc_intr_vec_error;
4830                 }
4831         }
4832
4833         if (rte_intr_allow_others(intr_handle)) {
4834                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4835                 base = RTE_INTR_VEC_RXTX_OFFSET;
4836         }
4837
4838         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4839                 ret = hns3_bind_ring_with_vector(hw, vec, true,
4840                                                  HNS3_RING_TYPE_RX, q_id);
4841                 if (ret)
4842                         goto bind_vector_error;
4843                 intr_handle->intr_vec[q_id] = vec;
4844                 /*
4845                  * If there are not enough efds (e.g. not enough interrupt),
4846                  * remaining queues will be bond to the last interrupt.
4847                  */
4848                 if (vec < base + intr_handle->nb_efd - 1)
4849                         vec++;
4850         }
4851         rte_intr_enable(intr_handle);
4852         return 0;
4853
4854 bind_vector_error:
4855         rte_free(intr_handle->intr_vec);
4856         intr_handle->intr_vec = NULL;
4857 alloc_intr_vec_error:
4858         rte_intr_efd_disable(intr_handle);
4859         return ret;
4860 }
4861
4862 static int
4863 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4864 {
4865         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4868         uint16_t q_id;
4869         int ret;
4870
4871         if (dev->data->dev_conf.intr_conf.rxq == 0)
4872                 return 0;
4873
4874         if (rte_intr_dp_is_en(intr_handle)) {
4875                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4876                         ret = hns3_bind_ring_with_vector(hw,
4877                                         intr_handle->intr_vec[q_id], true,
4878                                         HNS3_RING_TYPE_RX, q_id);
4879                         if (ret)
4880                                 return ret;
4881                 }
4882         }
4883
4884         return 0;
4885 }
4886
4887 static void
4888 hns3_restore_filter(struct rte_eth_dev *dev)
4889 {
4890         hns3_restore_rss_filter(dev);
4891 }
4892
4893 static int
4894 hns3_dev_start(struct rte_eth_dev *dev)
4895 {
4896         struct hns3_adapter *hns = dev->data->dev_private;
4897         struct hns3_hw *hw = &hns->hw;
4898         int ret;
4899
4900         PMD_INIT_FUNC_TRACE();
4901         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
4902                 return -EBUSY;
4903
4904         rte_spinlock_lock(&hw->lock);
4905         hw->adapter_state = HNS3_NIC_STARTING;
4906
4907         ret = hns3_do_start(hns, true);
4908         if (ret) {
4909                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4910                 rte_spinlock_unlock(&hw->lock);
4911                 return ret;
4912         }
4913         ret = hns3_map_rx_interrupt(dev);
4914         if (ret) {
4915                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4916                 rte_spinlock_unlock(&hw->lock);
4917                 return ret;
4918         }
4919
4920         /*
4921          * There are three register used to control the status of a TQP
4922          * (contains a pair of Tx queue and Rx queue) in the new version network
4923          * engine. One is used to control the enabling of Tx queue, the other is
4924          * used to control the enabling of Rx queue, and the last is the master
4925          * switch used to control the enabling of the tqp. The Tx register and
4926          * TQP register must be enabled at the same time to enable a Tx queue.
4927          * The same applies to the Rx queue. For the older network engine, this
4928          * function only refresh the enabled flag, and it is used to update the
4929          * status of queue in the dpdk framework.
4930          */
4931         ret = hns3_start_all_txqs(dev);
4932         if (ret) {
4933                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4934                 rte_spinlock_unlock(&hw->lock);
4935                 return ret;
4936         }
4937
4938         ret = hns3_start_all_rxqs(dev);
4939         if (ret) {
4940                 hns3_stop_all_txqs(dev);
4941                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4942                 rte_spinlock_unlock(&hw->lock);
4943                 return ret;
4944         }
4945
4946         hw->adapter_state = HNS3_NIC_STARTED;
4947         rte_spinlock_unlock(&hw->lock);
4948
4949         hns3_rx_scattered_calc(dev);
4950         hns3_set_rxtx_function(dev);
4951         hns3_mp_req_start_rxtx(dev);
4952         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4953
4954         hns3_restore_filter(dev);
4955
4956         /* Enable interrupt of all rx queues before enabling queues */
4957         hns3_dev_all_rx_queue_intr_enable(hw, true);
4958
4959         /*
4960          * After finished the initialization, enable tqps to receive/transmit
4961          * packets and refresh all queue status.
4962          */
4963         hns3_start_tqps(hw);
4964
4965         hns3_tm_dev_start_proc(hw);
4966
4967         hns3_info(hw, "hns3 dev start successful!");
4968         return 0;
4969 }
4970
4971 static int
4972 hns3_do_stop(struct hns3_adapter *hns)
4973 {
4974         struct hns3_hw *hw = &hns->hw;
4975         int ret;
4976
4977         ret = hns3_cfg_mac_mode(hw, false);
4978         if (ret)
4979                 return ret;
4980         hw->mac.link_status = ETH_LINK_DOWN;
4981
4982         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4983                 hns3_configure_all_mac_addr(hns, true);
4984                 ret = hns3_reset_all_tqps(hns);
4985                 if (ret) {
4986                         hns3_err(hw, "failed to reset all queues ret = %d.",
4987                                  ret);
4988                         return ret;
4989                 }
4990         }
4991         hw->mac.default_addr_setted = false;
4992         return 0;
4993 }
4994
4995 static void
4996 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4997 {
4998         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4999         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5000         struct hns3_adapter *hns = dev->data->dev_private;
5001         struct hns3_hw *hw = &hns->hw;
5002         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5003         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5004         uint16_t q_id;
5005
5006         if (dev->data->dev_conf.intr_conf.rxq == 0)
5007                 return;
5008
5009         /* unmap the ring with vector */
5010         if (rte_intr_allow_others(intr_handle)) {
5011                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5012                 base = RTE_INTR_VEC_RXTX_OFFSET;
5013         }
5014         if (rte_intr_dp_is_en(intr_handle)) {
5015                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5016                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5017                                                          HNS3_RING_TYPE_RX,
5018                                                          q_id);
5019                         if (vec < base + intr_handle->nb_efd - 1)
5020                                 vec++;
5021                 }
5022         }
5023         /* Clean datapath event and queue/vec mapping */
5024         rte_intr_efd_disable(intr_handle);
5025         if (intr_handle->intr_vec) {
5026                 rte_free(intr_handle->intr_vec);
5027                 intr_handle->intr_vec = NULL;
5028         }
5029 }
5030
5031 static int
5032 hns3_dev_stop(struct rte_eth_dev *dev)
5033 {
5034         struct hns3_adapter *hns = dev->data->dev_private;
5035         struct hns3_hw *hw = &hns->hw;
5036
5037         PMD_INIT_FUNC_TRACE();
5038         dev->data->dev_started = 0;
5039
5040         hw->adapter_state = HNS3_NIC_STOPPING;
5041         hns3_set_rxtx_function(dev);
5042         rte_wmb();
5043         /* Disable datapath on secondary process. */
5044         hns3_mp_req_stop_rxtx(dev);
5045         /* Prevent crashes when queues are still in use. */
5046         rte_delay_ms(hw->tqps_num);
5047
5048         rte_spinlock_lock(&hw->lock);
5049         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5050                 hns3_tm_dev_stop_proc(hw);
5051                 hns3_stop_tqps(hw);
5052                 hns3_do_stop(hns);
5053                 hns3_unmap_rx_interrupt(dev);
5054                 hns3_dev_release_mbufs(hns);
5055                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5056         }
5057         hns3_rx_scattered_reset(dev);
5058         rte_eal_alarm_cancel(hns3_service_handler, dev);
5059         rte_spinlock_unlock(&hw->lock);
5060
5061         return 0;
5062 }
5063
5064 static int
5065 hns3_dev_close(struct rte_eth_dev *eth_dev)
5066 {
5067         struct hns3_adapter *hns = eth_dev->data->dev_private;
5068         struct hns3_hw *hw = &hns->hw;
5069         int ret = 0;
5070
5071         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5072                 rte_free(eth_dev->process_private);
5073                 eth_dev->process_private = NULL;
5074                 return 0;
5075         }
5076
5077         if (hw->adapter_state == HNS3_NIC_STARTED)
5078                 ret = hns3_dev_stop(eth_dev);
5079
5080         hw->adapter_state = HNS3_NIC_CLOSING;
5081         hns3_reset_abort(hns);
5082         hw->adapter_state = HNS3_NIC_CLOSED;
5083
5084         hns3_configure_all_mc_mac_addr(hns, true);
5085         hns3_remove_all_vlan_table(hns);
5086         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5087         hns3_uninit_pf(eth_dev);
5088         hns3_free_all_queues(eth_dev);
5089         rte_free(hw->reset.wait_data);
5090         rte_free(eth_dev->process_private);
5091         eth_dev->process_private = NULL;
5092         hns3_mp_uninit_primary();
5093         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5094
5095         return ret;
5096 }
5097
5098 static int
5099 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5100 {
5101         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5103
5104         fc_conf->pause_time = pf->pause_time;
5105
5106         /* return fc current mode */
5107         switch (hw->current_mode) {
5108         case HNS3_FC_FULL:
5109                 fc_conf->mode = RTE_FC_FULL;
5110                 break;
5111         case HNS3_FC_TX_PAUSE:
5112                 fc_conf->mode = RTE_FC_TX_PAUSE;
5113                 break;
5114         case HNS3_FC_RX_PAUSE:
5115                 fc_conf->mode = RTE_FC_RX_PAUSE;
5116                 break;
5117         case HNS3_FC_NONE:
5118         default:
5119                 fc_conf->mode = RTE_FC_NONE;
5120                 break;
5121         }
5122
5123         return 0;
5124 }
5125
5126 static void
5127 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5128 {
5129         switch (mode) {
5130         case RTE_FC_NONE:
5131                 hw->requested_mode = HNS3_FC_NONE;
5132                 break;
5133         case RTE_FC_RX_PAUSE:
5134                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5135                 break;
5136         case RTE_FC_TX_PAUSE:
5137                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5138                 break;
5139         case RTE_FC_FULL:
5140                 hw->requested_mode = HNS3_FC_FULL;
5141                 break;
5142         default:
5143                 hw->requested_mode = HNS3_FC_NONE;
5144                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5145                           "configured to RTE_FC_NONE", mode);
5146                 break;
5147         }
5148 }
5149
5150 static int
5151 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5152 {
5153         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5154         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5155         int ret;
5156
5157         if (fc_conf->high_water || fc_conf->low_water ||
5158             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5159                 hns3_err(hw, "Unsupported flow control settings specified, "
5160                          "high_water(%u), low_water(%u), send_xon(%u) and "
5161                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5162                          fc_conf->high_water, fc_conf->low_water,
5163                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5164                 return -EINVAL;
5165         }
5166         if (fc_conf->autoneg) {
5167                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5168                 return -EINVAL;
5169         }
5170         if (!fc_conf->pause_time) {
5171                 hns3_err(hw, "Invalid pause time %u setting.",
5172                          fc_conf->pause_time);
5173                 return -EINVAL;
5174         }
5175
5176         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5177             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5178                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5179                          "current_fc_status = %d", hw->current_fc_status);
5180                 return -EOPNOTSUPP;
5181         }
5182
5183         hns3_get_fc_mode(hw, fc_conf->mode);
5184         if (hw->requested_mode == hw->current_mode &&
5185             pf->pause_time == fc_conf->pause_time)
5186                 return 0;
5187
5188         rte_spinlock_lock(&hw->lock);
5189         ret = hns3_fc_enable(dev, fc_conf);
5190         rte_spinlock_unlock(&hw->lock);
5191
5192         return ret;
5193 }
5194
5195 static int
5196 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5197                             struct rte_eth_pfc_conf *pfc_conf)
5198 {
5199         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5201         uint8_t priority;
5202         int ret;
5203
5204         if (!hns3_dev_dcb_supported(hw)) {
5205                 hns3_err(hw, "This port does not support dcb configurations.");
5206                 return -EOPNOTSUPP;
5207         }
5208
5209         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5210             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5211                 hns3_err(hw, "Unsupported flow control settings specified, "
5212                          "high_water(%u), low_water(%u), send_xon(%u) and "
5213                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5214                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5215                          pfc_conf->fc.send_xon,
5216                          pfc_conf->fc.mac_ctrl_frame_fwd);
5217                 return -EINVAL;
5218         }
5219         if (pfc_conf->fc.autoneg) {
5220                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5221                 return -EINVAL;
5222         }
5223         if (pfc_conf->fc.pause_time == 0) {
5224                 hns3_err(hw, "Invalid pause time %u setting.",
5225                          pfc_conf->fc.pause_time);
5226                 return -EINVAL;
5227         }
5228
5229         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5230             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5231                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5232                              "current_fc_status = %d", hw->current_fc_status);
5233                 return -EOPNOTSUPP;
5234         }
5235
5236         priority = pfc_conf->priority;
5237         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5238         if (hw->dcb_info.pfc_en & BIT(priority) &&
5239             hw->requested_mode == hw->current_mode &&
5240             pfc_conf->fc.pause_time == pf->pause_time)
5241                 return 0;
5242
5243         rte_spinlock_lock(&hw->lock);
5244         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5245         rte_spinlock_unlock(&hw->lock);
5246
5247         return ret;
5248 }
5249
5250 static int
5251 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5252 {
5253         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5254         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5255         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5256         int i;
5257
5258         rte_spinlock_lock(&hw->lock);
5259         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5260                 dcb_info->nb_tcs = pf->local_max_tc;
5261         else
5262                 dcb_info->nb_tcs = 1;
5263
5264         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5265                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5266         for (i = 0; i < dcb_info->nb_tcs; i++)
5267                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5268
5269         for (i = 0; i < hw->num_tc; i++) {
5270                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5271                 dcb_info->tc_queue.tc_txq[0][i].base =
5272                                                 hw->tc_queue[i].tqp_offset;
5273                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5274                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5275                                                 hw->tc_queue[i].tqp_count;
5276         }
5277         rte_spinlock_unlock(&hw->lock);
5278
5279         return 0;
5280 }
5281
5282 static int
5283 hns3_reinit_dev(struct hns3_adapter *hns)
5284 {
5285         struct hns3_hw *hw = &hns->hw;
5286         int ret;
5287
5288         ret = hns3_cmd_init(hw);
5289         if (ret) {
5290                 hns3_err(hw, "Failed to init cmd: %d", ret);
5291                 return ret;
5292         }
5293
5294         ret = hns3_reset_all_tqps(hns);
5295         if (ret) {
5296                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5297                 return ret;
5298         }
5299
5300         ret = hns3_init_hardware(hns);
5301         if (ret) {
5302                 hns3_err(hw, "Failed to init hardware: %d", ret);
5303                 return ret;
5304         }
5305
5306         ret = hns3_enable_hw_error_intr(hns, true);
5307         if (ret) {
5308                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5309                              ret);
5310                 return ret;
5311         }
5312         hns3_info(hw, "Reset done, driver initialization finished.");
5313
5314         return 0;
5315 }
5316
5317 static bool
5318 is_pf_reset_done(struct hns3_hw *hw)
5319 {
5320         uint32_t val, reg, reg_bit;
5321
5322         switch (hw->reset.level) {
5323         case HNS3_IMP_RESET:
5324                 reg = HNS3_GLOBAL_RESET_REG;
5325                 reg_bit = HNS3_IMP_RESET_BIT;
5326                 break;
5327         case HNS3_GLOBAL_RESET:
5328                 reg = HNS3_GLOBAL_RESET_REG;
5329                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5330                 break;
5331         case HNS3_FUNC_RESET:
5332                 reg = HNS3_FUN_RST_ING;
5333                 reg_bit = HNS3_FUN_RST_ING_B;
5334                 break;
5335         case HNS3_FLR_RESET:
5336         default:
5337                 hns3_err(hw, "Wait for unsupported reset level: %d",
5338                          hw->reset.level);
5339                 return true;
5340         }
5341         val = hns3_read_dev(hw, reg);
5342         if (hns3_get_bit(val, reg_bit))
5343                 return false;
5344         else
5345                 return true;
5346 }
5347
5348 bool
5349 hns3_is_reset_pending(struct hns3_adapter *hns)
5350 {
5351         struct hns3_hw *hw = &hns->hw;
5352         enum hns3_reset_level reset;
5353
5354         hns3_check_event_cause(hns, NULL);
5355         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5356         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5357                 hns3_warn(hw, "High level reset %d is pending", reset);
5358                 return true;
5359         }
5360         reset = hns3_get_reset_level(hns, &hw->reset.request);
5361         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5362                 hns3_warn(hw, "High level reset %d is request", reset);
5363                 return true;
5364         }
5365         return false;
5366 }
5367
5368 static int
5369 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5370 {
5371         struct hns3_hw *hw = &hns->hw;
5372         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5373         struct timeval tv;
5374
5375         if (wait_data->result == HNS3_WAIT_SUCCESS)
5376                 return 0;
5377         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5378                 gettimeofday(&tv, NULL);
5379                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5380                           tv.tv_sec, tv.tv_usec);
5381                 return -ETIME;
5382         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5383                 return -EAGAIN;
5384
5385         wait_data->hns = hns;
5386         wait_data->check_completion = is_pf_reset_done;
5387         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5388                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5389         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5390         wait_data->count = HNS3_RESET_WAIT_CNT;
5391         wait_data->result = HNS3_WAIT_REQUEST;
5392         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5393         return -EAGAIN;
5394 }
5395
5396 static int
5397 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5398 {
5399         struct hns3_cmd_desc desc;
5400         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5401
5402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5403         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5404         req->fun_reset_vfid = func_id;
5405
5406         return hns3_cmd_send(hw, &desc, 1);
5407 }
5408
5409 static int
5410 hns3_imp_reset_cmd(struct hns3_hw *hw)
5411 {
5412         struct hns3_cmd_desc desc;
5413
5414         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5415         desc.data[0] = 0xeedd;
5416
5417         return hns3_cmd_send(hw, &desc, 1);
5418 }
5419
5420 static void
5421 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5422 {
5423         struct hns3_hw *hw = &hns->hw;
5424         struct timeval tv;
5425         uint32_t val;
5426
5427         gettimeofday(&tv, NULL);
5428         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5429             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5430                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5431                           tv.tv_sec, tv.tv_usec);
5432                 return;
5433         }
5434
5435         switch (reset_level) {
5436         case HNS3_IMP_RESET:
5437                 hns3_imp_reset_cmd(hw);
5438                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5439                           tv.tv_sec, tv.tv_usec);
5440                 break;
5441         case HNS3_GLOBAL_RESET:
5442                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5443                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5444                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5445                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5446                           tv.tv_sec, tv.tv_usec);
5447                 break;
5448         case HNS3_FUNC_RESET:
5449                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5450                           tv.tv_sec, tv.tv_usec);
5451                 /* schedule again to check later */
5452                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5453                 hns3_schedule_reset(hns);
5454                 break;
5455         default:
5456                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5457                 return;
5458         }
5459         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5460 }
5461
5462 static enum hns3_reset_level
5463 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5464 {
5465         struct hns3_hw *hw = &hns->hw;
5466         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5467
5468         /* Return the highest priority reset level amongst all */
5469         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5470                 reset_level = HNS3_IMP_RESET;
5471         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5472                 reset_level = HNS3_GLOBAL_RESET;
5473         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5474                 reset_level = HNS3_FUNC_RESET;
5475         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5476                 reset_level = HNS3_FLR_RESET;
5477
5478         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5479                 return HNS3_NONE_RESET;
5480
5481         return reset_level;
5482 }
5483
5484 static void
5485 hns3_record_imp_error(struct hns3_adapter *hns)
5486 {
5487         struct hns3_hw *hw = &hns->hw;
5488         uint32_t reg_val;
5489
5490         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5491         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5492                 hns3_warn(hw, "Detected IMP RD poison!");
5493                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5494                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5495                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5496         }
5497
5498         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5499                 hns3_warn(hw, "Detected IMP CMDQ error!");
5500                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5501                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5502                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5503         }
5504 }
5505
5506 static int
5507 hns3_prepare_reset(struct hns3_adapter *hns)
5508 {
5509         struct hns3_hw *hw = &hns->hw;
5510         uint32_t reg_val;
5511         int ret;
5512
5513         switch (hw->reset.level) {
5514         case HNS3_FUNC_RESET:
5515                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5516                 if (ret)
5517                         return ret;
5518
5519                 /*
5520                  * After performaning pf reset, it is not necessary to do the
5521                  * mailbox handling or send any command to firmware, because
5522                  * any mailbox handling or command to firmware is only valid
5523                  * after hns3_cmd_init is called.
5524                  */
5525                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5526                 hw->reset.stats.request_cnt++;
5527                 break;
5528         case HNS3_IMP_RESET:
5529                 hns3_record_imp_error(hns);
5530                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5531                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5532                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5533                 break;
5534         default:
5535                 break;
5536         }
5537         return 0;
5538 }
5539
5540 static int
5541 hns3_set_rst_done(struct hns3_hw *hw)
5542 {
5543         struct hns3_pf_rst_done_cmd *req;
5544         struct hns3_cmd_desc desc;
5545
5546         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5547         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5548         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5549         return hns3_cmd_send(hw, &desc, 1);
5550 }
5551
5552 static int
5553 hns3_stop_service(struct hns3_adapter *hns)
5554 {
5555         struct hns3_hw *hw = &hns->hw;
5556         struct rte_eth_dev *eth_dev;
5557
5558         eth_dev = &rte_eth_devices[hw->data->port_id];
5559         if (hw->adapter_state == HNS3_NIC_STARTED)
5560                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5561         hw->mac.link_status = ETH_LINK_DOWN;
5562
5563         hns3_set_rxtx_function(eth_dev);
5564         rte_wmb();
5565         /* Disable datapath on secondary process. */
5566         hns3_mp_req_stop_rxtx(eth_dev);
5567         rte_delay_ms(hw->tqps_num);
5568
5569         rte_spinlock_lock(&hw->lock);
5570         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5571             hw->adapter_state == HNS3_NIC_STOPPING) {
5572                 hns3_enable_all_queues(hw, false);
5573                 hns3_do_stop(hns);
5574                 hw->reset.mbuf_deferred_free = true;
5575         } else
5576                 hw->reset.mbuf_deferred_free = false;
5577
5578         /*
5579          * It is cumbersome for hardware to pick-and-choose entries for deletion
5580          * from table space. Hence, for function reset software intervention is
5581          * required to delete the entries
5582          */
5583         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5584                 hns3_configure_all_mc_mac_addr(hns, true);
5585         rte_spinlock_unlock(&hw->lock);
5586
5587         return 0;
5588 }
5589
5590 static int
5591 hns3_start_service(struct hns3_adapter *hns)
5592 {
5593         struct hns3_hw *hw = &hns->hw;
5594         struct rte_eth_dev *eth_dev;
5595
5596         if (hw->reset.level == HNS3_IMP_RESET ||
5597             hw->reset.level == HNS3_GLOBAL_RESET)
5598                 hns3_set_rst_done(hw);
5599         eth_dev = &rte_eth_devices[hw->data->port_id];
5600         hns3_set_rxtx_function(eth_dev);
5601         hns3_mp_req_start_rxtx(eth_dev);
5602         if (hw->adapter_state == HNS3_NIC_STARTED) {
5603                 hns3_service_handler(eth_dev);
5604
5605                 /* Enable interrupt of all rx queues before enabling queues */
5606                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5607                 /*
5608                  * Enable state of each rxq and txq will be recovered after
5609                  * reset, so we need to restore them before enable all tqps;
5610                  */
5611                 hns3_restore_tqp_enable_state(hw);
5612                 /*
5613                  * When finished the initialization, enable queues to receive
5614                  * and transmit packets.
5615                  */
5616                 hns3_enable_all_queues(hw, true);
5617         }
5618
5619         return 0;
5620 }
5621
5622 static int
5623 hns3_restore_conf(struct hns3_adapter *hns)
5624 {
5625         struct hns3_hw *hw = &hns->hw;
5626         int ret;
5627
5628         ret = hns3_configure_all_mac_addr(hns, false);
5629         if (ret)
5630                 return ret;
5631
5632         ret = hns3_configure_all_mc_mac_addr(hns, false);
5633         if (ret)
5634                 goto err_mc_mac;
5635
5636         ret = hns3_dev_promisc_restore(hns);
5637         if (ret)
5638                 goto err_promisc;
5639
5640         ret = hns3_restore_vlan_table(hns);
5641         if (ret)
5642                 goto err_promisc;
5643
5644         ret = hns3_restore_vlan_conf(hns);
5645         if (ret)
5646                 goto err_promisc;
5647
5648         ret = hns3_restore_all_fdir_filter(hns);
5649         if (ret)
5650                 goto err_promisc;
5651
5652         ret = hns3_restore_rx_interrupt(hw);
5653         if (ret)
5654                 goto err_promisc;
5655
5656         ret = hns3_restore_gro_conf(hw);
5657         if (ret)
5658                 goto err_promisc;
5659
5660         ret = hns3_restore_fec(hw);
5661         if (ret)
5662                 goto err_promisc;
5663
5664         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5665                 ret = hns3_do_start(hns, false);
5666                 if (ret)
5667                         goto err_promisc;
5668                 hns3_info(hw, "hns3 dev restart successful!");
5669         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5670                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5671         return 0;
5672
5673 err_promisc:
5674         hns3_configure_all_mc_mac_addr(hns, true);
5675 err_mc_mac:
5676         hns3_configure_all_mac_addr(hns, true);
5677         return ret;
5678 }
5679
5680 static void
5681 hns3_reset_service(void *param)
5682 {
5683         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5684         struct hns3_hw *hw = &hns->hw;
5685         enum hns3_reset_level reset_level;
5686         struct timeval tv_delta;
5687         struct timeval tv_start;
5688         struct timeval tv;
5689         uint64_t msec;
5690         int ret;
5691
5692         /*
5693          * The interrupt is not triggered within the delay time.
5694          * The interrupt may have been lost. It is necessary to handle
5695          * the interrupt to recover from the error.
5696          */
5697         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5698                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5699                 hns3_err(hw, "Handling interrupts in delayed tasks");
5700                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5701                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5702                 if (reset_level == HNS3_NONE_RESET) {
5703                         hns3_err(hw, "No reset level is set, try IMP reset");
5704                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5705                 }
5706         }
5707         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5708
5709         /*
5710          * Check if there is any ongoing reset in the hardware. This status can
5711          * be checked from reset_pending. If there is then, we need to wait for
5712          * hardware to complete reset.
5713          *    a. If we are able to figure out in reasonable time that hardware
5714          *       has fully resetted then, we can proceed with driver, client
5715          *       reset.
5716          *    b. else, we can come back later to check this status so re-sched
5717          *       now.
5718          */
5719         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5720         if (reset_level != HNS3_NONE_RESET) {
5721                 gettimeofday(&tv_start, NULL);
5722                 ret = hns3_reset_process(hns, reset_level);
5723                 gettimeofday(&tv, NULL);
5724                 timersub(&tv, &tv_start, &tv_delta);
5725                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5726                        tv_delta.tv_usec / USEC_PER_MSEC;
5727                 if (msec > HNS3_RESET_PROCESS_MS)
5728                         hns3_err(hw, "%d handle long time delta %" PRIx64
5729                                      " ms time=%ld.%.6ld",
5730                                  hw->reset.level, msec,
5731                                  tv.tv_sec, tv.tv_usec);
5732                 if (ret == -EAGAIN)
5733                         return;
5734         }
5735
5736         /* Check if we got any *new* reset requests to be honored */
5737         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5738         if (reset_level != HNS3_NONE_RESET)
5739                 hns3_msix_process(hns, reset_level);
5740 }
5741
5742 static unsigned int
5743 hns3_get_speed_capa_num(uint16_t device_id)
5744 {
5745         unsigned int num;
5746
5747         switch (device_id) {
5748         case HNS3_DEV_ID_25GE:
5749         case HNS3_DEV_ID_25GE_RDMA:
5750                 num = 2;
5751                 break;
5752         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5753         case HNS3_DEV_ID_200G_RDMA:
5754                 num = 1;
5755                 break;
5756         default:
5757                 num = 0;
5758                 break;
5759         }
5760
5761         return num;
5762 }
5763
5764 static int
5765 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
5766                         uint16_t device_id)
5767 {
5768         switch (device_id) {
5769         case HNS3_DEV_ID_25GE:
5770         /* fallthrough */
5771         case HNS3_DEV_ID_25GE_RDMA:
5772                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
5773                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
5774
5775                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
5776                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
5777                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
5778                 break;
5779         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5780                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
5781                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
5782                 break;
5783         case HNS3_DEV_ID_200G_RDMA:
5784                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
5785                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
5786                 break;
5787         default:
5788                 return -ENOTSUP;
5789         }
5790
5791         return 0;
5792 }
5793
5794 static int
5795 hns3_fec_get_capability(struct rte_eth_dev *dev,
5796                         struct rte_eth_fec_capa *speed_fec_capa,
5797                         unsigned int num)
5798 {
5799         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5801         uint16_t device_id = pci_dev->id.device_id;
5802         unsigned int capa_num;
5803         int ret;
5804
5805         capa_num = hns3_get_speed_capa_num(device_id);
5806         if (capa_num == 0) {
5807                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
5808                          device_id);
5809                 return -ENOTSUP;
5810         }
5811
5812         if (speed_fec_capa == NULL || num < capa_num)
5813                 return capa_num;
5814
5815         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
5816         if (ret)
5817                 return -ENOTSUP;
5818
5819         return capa_num;
5820 }
5821
5822 static int
5823 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
5824 {
5825         struct hns3_config_fec_cmd *req;
5826         struct hns3_cmd_desc desc;
5827         int ret;
5828
5829         /*
5830          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
5831          * in device of link speed
5832          * below 10 Gbps.
5833          */
5834         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
5835                 *state = 0;
5836                 return 0;
5837         }
5838
5839         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
5840         req = (struct hns3_config_fec_cmd *)desc.data;
5841         ret = hns3_cmd_send(hw, &desc, 1);
5842         if (ret) {
5843                 hns3_err(hw, "get current fec auto state failed, ret = %d",
5844                          ret);
5845                 return ret;
5846         }
5847
5848         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
5849         return 0;
5850 }
5851
5852 static int
5853 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
5854 {
5855 #define QUERY_ACTIVE_SPEED      1
5856         struct hns3_sfp_speed_cmd *resp;
5857         uint32_t tmp_fec_capa;
5858         uint8_t auto_state;
5859         struct hns3_cmd_desc desc;
5860         int ret;
5861
5862         /*
5863          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
5864          * configured FEC mode is returned.
5865          * If link is up, current FEC mode is returned.
5866          */
5867         if (hw->mac.link_status == ETH_LINK_DOWN) {
5868                 ret = get_current_fec_auto_state(hw, &auto_state);
5869                 if (ret)
5870                         return ret;
5871
5872                 if (auto_state == 0x1) {
5873                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
5874                         return 0;
5875                 }
5876         }
5877
5878         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
5879         resp = (struct hns3_sfp_speed_cmd *)desc.data;
5880         resp->query_type = QUERY_ACTIVE_SPEED;
5881
5882         ret = hns3_cmd_send(hw, &desc, 1);
5883         if (ret == -EOPNOTSUPP) {
5884                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
5885                 return ret;
5886         } else if (ret) {
5887                 hns3_err(hw, "get FEC failed, ret = %d", ret);
5888                 return ret;
5889         }
5890
5891         /*
5892          * FEC mode order defined in hns3 hardware is inconsistend with
5893          * that defined in the ethdev library. So the sequence needs
5894          * to be converted.
5895          */
5896         switch (resp->active_fec) {
5897         case HNS3_HW_FEC_MODE_NOFEC:
5898                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5899                 break;
5900         case HNS3_HW_FEC_MODE_BASER:
5901                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
5902                 break;
5903         case HNS3_HW_FEC_MODE_RS:
5904                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
5905                 break;
5906         default:
5907                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
5908                 break;
5909         }
5910
5911         *fec_capa = tmp_fec_capa;
5912         return 0;
5913 }
5914
5915 static int
5916 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
5917 {
5918         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5919
5920         return hns3_fec_get_internal(hw, fec_capa);
5921 }
5922
5923 static int
5924 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
5925 {
5926         struct hns3_config_fec_cmd *req;
5927         struct hns3_cmd_desc desc;
5928         int ret;
5929
5930         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
5931
5932         req = (struct hns3_config_fec_cmd *)desc.data;
5933         switch (mode) {
5934         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
5935                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5936                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
5937                 break;
5938         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
5939                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5940                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
5941                 break;
5942         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
5943                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
5944                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
5945                 break;
5946         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
5947                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
5948                 break;
5949         default:
5950                 return 0;
5951         }
5952         ret = hns3_cmd_send(hw, &desc, 1);
5953         if (ret)
5954                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
5955
5956         return ret;
5957 }
5958
5959 static uint32_t
5960 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
5961 {
5962         struct hns3_mac *mac = &hw->mac;
5963         uint32_t cur_capa;
5964
5965         switch (mac->link_speed) {
5966         case ETH_SPEED_NUM_10G:
5967                 cur_capa = fec_capa[1].capa;
5968                 break;
5969         case ETH_SPEED_NUM_25G:
5970         case ETH_SPEED_NUM_100G:
5971         case ETH_SPEED_NUM_200G:
5972                 cur_capa = fec_capa[0].capa;
5973                 break;
5974         default:
5975                 cur_capa = 0;
5976                 break;
5977         }
5978
5979         return cur_capa;
5980 }
5981
5982 static bool
5983 is_fec_mode_one_bit_set(uint32_t mode)
5984 {
5985         int cnt = 0;
5986         uint8_t i;
5987
5988         for (i = 0; i < sizeof(mode); i++)
5989                 if (mode >> i & 0x1)
5990                         cnt++;
5991
5992         return cnt == 1 ? true : false;
5993 }
5994
5995 static int
5996 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
5997 {
5998 #define FEC_CAPA_NUM 2
5999         struct hns3_adapter *hns = dev->data->dev_private;
6000         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6001         struct hns3_pf *pf = &hns->pf;
6002
6003         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6004         uint32_t cur_capa;
6005         uint32_t num = FEC_CAPA_NUM;
6006         int ret;
6007
6008         ret = hns3_fec_get_capability(dev, fec_capa, num);
6009         if (ret < 0)
6010                 return ret;
6011
6012         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6013         if (!is_fec_mode_one_bit_set(mode))
6014                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6015                              "FEC mode should be only one bit set", mode);
6016
6017         /*
6018          * Check whether the configured mode is within the FEC capability.
6019          * If not, the configured mode will not be supported.
6020          */
6021         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6022         if (!(cur_capa & mode)) {
6023                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6024                 return -EINVAL;
6025         }
6026
6027         ret = hns3_set_fec_hw(hw, mode);
6028         if (ret)
6029                 return ret;
6030
6031         pf->fec_mode = mode;
6032         return 0;
6033 }
6034
6035 static int
6036 hns3_restore_fec(struct hns3_hw *hw)
6037 {
6038         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6039         struct hns3_pf *pf = &hns->pf;
6040         uint32_t mode = pf->fec_mode;
6041         int ret;
6042
6043         ret = hns3_set_fec_hw(hw, mode);
6044         if (ret)
6045                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6046                          mode, ret);
6047
6048         return ret;
6049 }
6050
6051 static int
6052 hns3_query_dev_fec_info(struct hns3_hw *hw)
6053 {
6054         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6055         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6056         int ret;
6057
6058         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6059         if (ret)
6060                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6061
6062         return ret;
6063 }
6064
6065 static const struct eth_dev_ops hns3_eth_dev_ops = {
6066         .dev_configure      = hns3_dev_configure,
6067         .dev_start          = hns3_dev_start,
6068         .dev_stop           = hns3_dev_stop,
6069         .dev_close          = hns3_dev_close,
6070         .promiscuous_enable = hns3_dev_promiscuous_enable,
6071         .promiscuous_disable = hns3_dev_promiscuous_disable,
6072         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6073         .allmulticast_disable = hns3_dev_allmulticast_disable,
6074         .mtu_set            = hns3_dev_mtu_set,
6075         .stats_get          = hns3_stats_get,
6076         .stats_reset        = hns3_stats_reset,
6077         .xstats_get         = hns3_dev_xstats_get,
6078         .xstats_get_names   = hns3_dev_xstats_get_names,
6079         .xstats_reset       = hns3_dev_xstats_reset,
6080         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6081         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6082         .dev_infos_get          = hns3_dev_infos_get,
6083         .fw_version_get         = hns3_fw_version_get,
6084         .rx_queue_setup         = hns3_rx_queue_setup,
6085         .tx_queue_setup         = hns3_tx_queue_setup,
6086         .rx_queue_release       = hns3_dev_rx_queue_release,
6087         .tx_queue_release       = hns3_dev_tx_queue_release,
6088         .rx_queue_start         = hns3_dev_rx_queue_start,
6089         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6090         .tx_queue_start         = hns3_dev_tx_queue_start,
6091         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6092         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6093         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6094         .rxq_info_get           = hns3_rxq_info_get,
6095         .txq_info_get           = hns3_txq_info_get,
6096         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6097         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6098         .flow_ctrl_get          = hns3_flow_ctrl_get,
6099         .flow_ctrl_set          = hns3_flow_ctrl_set,
6100         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6101         .mac_addr_add           = hns3_add_mac_addr,
6102         .mac_addr_remove        = hns3_remove_mac_addr,
6103         .mac_addr_set           = hns3_set_default_mac_addr,
6104         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6105         .link_update            = hns3_dev_link_update,
6106         .rss_hash_update        = hns3_dev_rss_hash_update,
6107         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6108         .reta_update            = hns3_dev_rss_reta_update,
6109         .reta_query             = hns3_dev_rss_reta_query,
6110         .filter_ctrl            = hns3_dev_filter_ctrl,
6111         .vlan_filter_set        = hns3_vlan_filter_set,
6112         .vlan_tpid_set          = hns3_vlan_tpid_set,
6113         .vlan_offload_set       = hns3_vlan_offload_set,
6114         .vlan_pvid_set          = hns3_vlan_pvid_set,
6115         .get_reg                = hns3_get_regs,
6116         .get_dcb_info           = hns3_get_dcb_info,
6117         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6118         .fec_get_capability     = hns3_fec_get_capability,
6119         .fec_get                = hns3_fec_get,
6120         .fec_set                = hns3_fec_set,
6121         .tm_ops_get             = hns3_tm_ops_get,
6122 };
6123
6124 static const struct hns3_reset_ops hns3_reset_ops = {
6125         .reset_service       = hns3_reset_service,
6126         .stop_service        = hns3_stop_service,
6127         .prepare_reset       = hns3_prepare_reset,
6128         .wait_hardware_ready = hns3_wait_hardware_ready,
6129         .reinit_dev          = hns3_reinit_dev,
6130         .restore_conf        = hns3_restore_conf,
6131         .start_service       = hns3_start_service,
6132 };
6133
6134 static int
6135 hns3_dev_init(struct rte_eth_dev *eth_dev)
6136 {
6137         struct hns3_adapter *hns = eth_dev->data->dev_private;
6138         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6139         struct rte_ether_addr *eth_addr;
6140         struct hns3_hw *hw = &hns->hw;
6141         int ret;
6142
6143         PMD_INIT_FUNC_TRACE();
6144
6145         eth_dev->process_private = (struct hns3_process_private *)
6146             rte_zmalloc_socket("hns3_filter_list",
6147                                sizeof(struct hns3_process_private),
6148                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6149         if (eth_dev->process_private == NULL) {
6150                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6151                 return -ENOMEM;
6152         }
6153         /* initialize flow filter lists */
6154         hns3_filterlist_init(eth_dev);
6155
6156         hns3_set_rxtx_function(eth_dev);
6157         eth_dev->dev_ops = &hns3_eth_dev_ops;
6158         eth_dev->rx_queue_count = hns3_rx_queue_count;
6159         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6160                 ret = hns3_mp_init_secondary();
6161                 if (ret) {
6162                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6163                                      "process, ret = %d", ret);
6164                         goto err_mp_init_secondary;
6165                 }
6166
6167                 hw->secondary_cnt++;
6168                 return 0;
6169         }
6170
6171         ret = hns3_mp_init_primary();
6172         if (ret) {
6173                 PMD_INIT_LOG(ERR,
6174                              "Failed to init for primary process, ret = %d",
6175                              ret);
6176                 goto err_mp_init_primary;
6177         }
6178
6179         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6180         hns->is_vf = false;
6181         hw->data = eth_dev->data;
6182
6183         /*
6184          * Set default max packet size according to the mtu
6185          * default vale in DPDK frame.
6186          */
6187         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6188
6189         ret = hns3_reset_init(hw);
6190         if (ret)
6191                 goto err_init_reset;
6192         hw->reset.ops = &hns3_reset_ops;
6193
6194         ret = hns3_init_pf(eth_dev);
6195         if (ret) {
6196                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6197                 goto err_init_pf;
6198         }
6199
6200         /* Allocate memory for storing MAC addresses */
6201         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6202                                                sizeof(struct rte_ether_addr) *
6203                                                HNS3_UC_MACADDR_NUM, 0);
6204         if (eth_dev->data->mac_addrs == NULL) {
6205                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6206                              "to store MAC addresses",
6207                              sizeof(struct rte_ether_addr) *
6208                              HNS3_UC_MACADDR_NUM);
6209                 ret = -ENOMEM;
6210                 goto err_rte_zmalloc;
6211         }
6212
6213         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6214         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6215                 rte_eth_random_addr(hw->mac.mac_addr);
6216                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6217                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6218                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6219                           "unicast address, using random MAC address %s",
6220                           mac_str);
6221         }
6222         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6223                             &eth_dev->data->mac_addrs[0]);
6224
6225         hw->adapter_state = HNS3_NIC_INITIALIZED;
6226
6227         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
6228                 hns3_err(hw, "Reschedule reset service after dev_init");
6229                 hns3_schedule_reset(hns);
6230         } else {
6231                 /* IMP will wait ready flag before reset */
6232                 hns3_notify_reset_ready(hw, false);
6233         }
6234
6235         hns3_info(hw, "hns3 dev initialization successful!");
6236         return 0;
6237
6238 err_rte_zmalloc:
6239         hns3_uninit_pf(eth_dev);
6240
6241 err_init_pf:
6242         rte_free(hw->reset.wait_data);
6243
6244 err_init_reset:
6245         hns3_mp_uninit_primary();
6246
6247 err_mp_init_primary:
6248 err_mp_init_secondary:
6249         eth_dev->dev_ops = NULL;
6250         eth_dev->rx_pkt_burst = NULL;
6251         eth_dev->tx_pkt_burst = NULL;
6252         eth_dev->tx_pkt_prepare = NULL;
6253         rte_free(eth_dev->process_private);
6254         eth_dev->process_private = NULL;
6255         return ret;
6256 }
6257
6258 static int
6259 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6260 {
6261         struct hns3_adapter *hns = eth_dev->data->dev_private;
6262         struct hns3_hw *hw = &hns->hw;
6263
6264         PMD_INIT_FUNC_TRACE();
6265
6266         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6267                 return -EPERM;
6268
6269         if (hw->adapter_state < HNS3_NIC_CLOSING)
6270                 hns3_dev_close(eth_dev);
6271
6272         hw->adapter_state = HNS3_NIC_REMOVED;
6273         return 0;
6274 }
6275
6276 static int
6277 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6278                    struct rte_pci_device *pci_dev)
6279 {
6280         return rte_eth_dev_pci_generic_probe(pci_dev,
6281                                              sizeof(struct hns3_adapter),
6282                                              hns3_dev_init);
6283 }
6284
6285 static int
6286 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6287 {
6288         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6289 }
6290
6291 static const struct rte_pci_id pci_id_hns3_map[] = {
6292         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6293         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6294         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6295         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6296         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6297         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6298         { .vendor_id = 0, }, /* sentinel */
6299 };
6300
6301 static struct rte_pci_driver rte_hns3_pmd = {
6302         .id_table = pci_id_hns3_map,
6303         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6304         .probe = eth_hns3_pci_probe,
6305         .remove = eth_hns3_pci_remove,
6306 };
6307
6308 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6309 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6310 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6311 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6312 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);