1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 HiSilicon Limited.
6 #include <rte_bus_pci.h>
7 #include <ethdev_pci.h>
9 #include <rte_kvargs.h>
11 #include "hns3_ethdev.h"
12 #include "hns3_logs.h"
13 #include "hns3_rxtx.h"
14 #include "hns3_intr.h"
15 #include "hns3_regs.h"
19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
22 #define HNS3_SERVICE_INTERVAL 1000000 /* us */
23 #define HNS3_SERVICE_QUICK_INTERVAL 10
24 #define HNS3_INVALID_PVID 0xFFFF
26 #define HNS3_FILTER_TYPE_VF 0
27 #define HNS3_FILTER_TYPE_PORT 1
28 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
29 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
30 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
31 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
32 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
33 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
34 | HNS3_FILTER_FE_ROCE_EGRESS_B)
35 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
36 | HNS3_FILTER_FE_ROCE_INGRESS_B)
38 /* Reset related Registers */
39 #define HNS3_GLOBAL_RESET_BIT 0
40 #define HNS3_CORE_RESET_BIT 1
41 #define HNS3_IMP_RESET_BIT 2
42 #define HNS3_FUN_RST_ING_B 0
44 #define HNS3_VECTOR0_IMP_RESET_INT_B 1
45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
46 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U
47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
49 #define HNS3_RESET_WAIT_MS 100
50 #define HNS3_RESET_WAIT_CNT 200
52 /* FEC mode order defined in HNS3 hardware */
53 #define HNS3_HW_FEC_MODE_NOFEC 0
54 #define HNS3_HW_FEC_MODE_BASER 1
55 #define HNS3_HW_FEC_MODE_RS 2
58 HNS3_VECTOR0_EVENT_RST,
59 HNS3_VECTOR0_EVENT_MBX,
60 HNS3_VECTOR0_EVENT_ERR,
61 HNS3_VECTOR0_EVENT_PTP,
62 HNS3_VECTOR0_EVENT_OTHER,
65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
66 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
67 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
68 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
70 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
71 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
72 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
73 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
75 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
76 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
77 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
79 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
80 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
81 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
82 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
84 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
85 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
86 RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
88 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
89 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
90 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
99 static bool hns3_update_link_status(struct hns3_hw *hw);
101 static int hns3_add_mc_addr(struct hns3_hw *hw,
102 struct rte_ether_addr *mac_addr);
103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
104 struct rte_ether_addr *mac_addr);
105 static int hns3_restore_fec(struct hns3_hw *hw);
106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
107 static int hns3_do_stop(struct hns3_adapter *hns);
109 void hns3_ether_format_addr(char *buf, uint16_t size,
110 const struct rte_ether_addr *ether_addr)
112 snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
113 ether_addr->addr_bytes[0],
114 ether_addr->addr_bytes[4],
115 ether_addr->addr_bytes[5]);
119 hns3_pf_disable_irq0(struct hns3_hw *hw)
121 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
125 hns3_pf_enable_irq0(struct hns3_hw *hw)
127 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
130 static enum hns3_evt_cause
131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
134 struct hns3_hw *hw = &hns->hw;
136 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
137 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
138 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
140 hw->reset.stats.imp_cnt++;
141 hns3_warn(hw, "IMP reset detected, clear reset status");
143 hns3_schedule_delayed_reset(hns);
144 hns3_warn(hw, "IMP reset detected, don't clear reset status");
147 return HNS3_VECTOR0_EVENT_RST;
150 static enum hns3_evt_cause
151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
154 struct hns3_hw *hw = &hns->hw;
156 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
157 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
158 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
160 hw->reset.stats.global_cnt++;
161 hns3_warn(hw, "Global reset detected, clear reset status");
163 hns3_schedule_delayed_reset(hns);
165 "Global reset detected, don't clear reset status");
168 return HNS3_VECTOR0_EVENT_RST;
171 static enum hns3_evt_cause
172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
174 struct hns3_hw *hw = &hns->hw;
175 uint32_t vector0_int_stats;
176 uint32_t cmdq_src_val;
177 uint32_t hw_err_src_reg;
179 enum hns3_evt_cause ret;
182 /* fetch the events from their corresponding regs */
183 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
184 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
185 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
187 is_delay = clearval == NULL ? true : false;
189 * Assumption: If by any chance reset and mailbox events are reported
190 * together then we will only process reset event and defer the
191 * processing of the mailbox events. Since, we would have not cleared
192 * RX CMDQ event this time we would receive again another interrupt
193 * from H/W just for the mailbox.
195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
196 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
201 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
202 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
206 /* Check for vector0 1588 event source */
207 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
208 val = BIT(HNS3_VECTOR0_1588_INT_B);
209 ret = HNS3_VECTOR0_EVENT_PTP;
213 /* check for vector0 msix event source */
214 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
215 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
216 val = vector0_int_stats | hw_err_src_reg;
217 ret = HNS3_VECTOR0_EVENT_ERR;
221 /* check for vector0 mailbox(=CMDQ RX) event source */
222 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
223 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
225 ret = HNS3_VECTOR0_EVENT_MBX;
229 val = vector0_int_stats;
230 ret = HNS3_VECTOR0_EVENT_OTHER;
239 hns3_is_1588_event_type(uint32_t event_type)
241 return (event_type == HNS3_VECTOR0_EVENT_PTP);
245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
247 if (event_type == HNS3_VECTOR0_EVENT_RST ||
248 hns3_is_1588_event_type(event_type))
249 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
250 else if (event_type == HNS3_VECTOR0_EVENT_MBX)
251 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
255 hns3_clear_all_event_cause(struct hns3_hw *hw)
257 uint32_t vector0_int_stats;
258 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
260 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
261 hns3_warn(hw, "Probe during IMP reset interrupt");
263 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
264 hns3_warn(hw, "Probe during Global reset interrupt");
266 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
267 BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
268 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
269 BIT(HNS3_VECTOR0_CORERESET_INT_B));
270 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
271 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
272 BIT(HNS3_VECTOR0_1588_INT_B));
276 hns3_handle_mac_tnl(struct hns3_hw *hw)
278 struct hns3_cmd_desc desc;
282 /* query and clear mac tnl interruptions */
283 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
284 ret = hns3_cmd_send(hw, &desc, 1);
286 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
290 status = rte_le_to_cpu_32(desc.data[0]);
292 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
293 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
295 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
296 ret = hns3_cmd_send(hw, &desc, 1);
298 hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
304 hns3_interrupt_handler(void *param)
306 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
307 struct hns3_adapter *hns = dev->data->dev_private;
308 struct hns3_hw *hw = &hns->hw;
309 enum hns3_evt_cause event_cause;
310 uint32_t clearval = 0;
311 uint32_t vector0_int;
315 /* Disable interrupt */
316 hns3_pf_disable_irq0(hw);
318 event_cause = hns3_check_event_cause(hns, &clearval);
319 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
320 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
321 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
322 /* vector 0 interrupt is shared with reset and mailbox source events. */
323 if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
324 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
325 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
326 vector0_int, ras_int, cmdq_int);
327 hns3_handle_msix_error(hns, &hw->reset.request);
328 hns3_handle_ras_error(hns, &hw->reset.request);
329 hns3_handle_mac_tnl(hw);
330 hns3_schedule_reset(hns);
331 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
332 hns3_warn(hw, "received reset interrupt");
333 hns3_schedule_reset(hns);
334 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
335 hns3_dev_handle_mbx_msg(hw);
337 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
338 "ras_int_stat:0x%x cmdq_int_stat:0x%x",
339 vector0_int, ras_int, cmdq_int);
342 hns3_clear_event_cause(hw, event_cause, clearval);
343 /* Enable interrupt if it is not cause by reset */
344 hns3_pf_enable_irq0(hw);
348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
350 #define HNS3_VLAN_ID_OFFSET_STEP 160
351 #define HNS3_VLAN_BYTE_SIZE 8
352 struct hns3_vlan_filter_pf_cfg_cmd *req;
353 struct hns3_hw *hw = &hns->hw;
354 uint8_t vlan_offset_byte_val;
355 struct hns3_cmd_desc desc;
356 uint8_t vlan_offset_byte;
357 uint8_t vlan_offset_base;
360 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
362 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
363 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
365 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
367 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
368 req->vlan_offset = vlan_offset_base;
369 req->vlan_cfg = on ? 0 : 1;
370 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
372 ret = hns3_cmd_send(hw, &desc, 1);
374 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
383 struct hns3_user_vlan_table *vlan_entry;
384 struct hns3_pf *pf = &hns->pf;
386 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
387 if (vlan_entry->vlan_id == vlan_id) {
388 if (vlan_entry->hd_tbl_status)
389 hns3_set_port_vlan_filter(hns, vlan_id, 0);
390 LIST_REMOVE(vlan_entry, next);
391 rte_free(vlan_entry);
398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
401 struct hns3_user_vlan_table *vlan_entry;
402 struct hns3_hw *hw = &hns->hw;
403 struct hns3_pf *pf = &hns->pf;
405 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
406 if (vlan_entry->vlan_id == vlan_id)
410 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
411 if (vlan_entry == NULL) {
412 hns3_err(hw, "Failed to malloc hns3 vlan table");
416 vlan_entry->hd_tbl_status = writen_to_tbl;
417 vlan_entry->vlan_id = vlan_id;
419 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
423 hns3_restore_vlan_table(struct hns3_adapter *hns)
425 struct hns3_user_vlan_table *vlan_entry;
426 struct hns3_hw *hw = &hns->hw;
427 struct hns3_pf *pf = &hns->pf;
431 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
432 return hns3_vlan_pvid_configure(hns,
433 hw->port_base_vlan_cfg.pvid, 1);
435 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
436 if (vlan_entry->hd_tbl_status) {
437 vlan_id = vlan_entry->vlan_id;
438 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
450 struct hns3_hw *hw = &hns->hw;
451 bool writen_to_tbl = false;
455 * When vlan filter is enabled, hardware regards packets without vlan
456 * as packets with vlan 0. So, to receive packets without vlan, vlan id
457 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
459 if (on == 0 && vlan_id == 0)
463 * When port base vlan enabled, we use port base vlan as the vlan
464 * filter condition. In this case, we don't update vlan filter table
465 * when user add new vlan or remove exist vlan, just update the
466 * vlan list. The vlan id in vlan list will be writen in vlan filter
467 * table until port base vlan disabled
469 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
470 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
471 writen_to_tbl = true;
476 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
478 hns3_rm_dev_vlan_table(hns, vlan_id);
484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
486 struct hns3_adapter *hns = dev->data->dev_private;
487 struct hns3_hw *hw = &hns->hw;
490 rte_spinlock_lock(&hw->lock);
491 ret = hns3_vlan_filter_configure(hns, vlan_id, on);
492 rte_spinlock_unlock(&hw->lock);
497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
500 struct hns3_rx_vlan_type_cfg_cmd *rx_req;
501 struct hns3_tx_vlan_type_cfg_cmd *tx_req;
502 struct hns3_hw *hw = &hns->hw;
503 struct hns3_cmd_desc desc;
506 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
507 vlan_type != ETH_VLAN_TYPE_OUTER)) {
508 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
512 if (tpid != RTE_ETHER_TYPE_VLAN) {
513 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
517 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
518 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
520 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
521 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
522 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
523 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
524 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
525 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
526 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
527 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
530 ret = hns3_cmd_send(hw, &desc, 1);
532 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
537 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
539 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
540 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
541 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
543 ret = hns3_cmd_send(hw, &desc, 1);
545 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
554 struct hns3_adapter *hns = dev->data->dev_private;
555 struct hns3_hw *hw = &hns->hw;
558 rte_spinlock_lock(&hw->lock);
559 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
560 rte_spinlock_unlock(&hw->lock);
565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
566 struct hns3_rx_vtag_cfg *vcfg)
568 struct hns3_vport_vtag_rx_cfg_cmd *req;
569 struct hns3_hw *hw = &hns->hw;
570 struct hns3_cmd_desc desc;
575 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
577 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
578 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
579 vcfg->strip_tag1_en ? 1 : 0);
580 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
581 vcfg->strip_tag2_en ? 1 : 0);
582 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
583 vcfg->vlan1_vlan_prionly ? 1 : 0);
584 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
585 vcfg->vlan2_vlan_prionly ? 1 : 0);
587 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
588 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
589 vcfg->strip_tag1_discard_en ? 1 : 0);
590 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
591 vcfg->strip_tag2_discard_en ? 1 : 0);
593 * In current version VF is not supported when PF is driven by DPDK
594 * driver, just need to configure parameters for PF vport.
596 vport_id = HNS3_PF_FUNC_ID;
597 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
598 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
599 req->vf_bitmap[req->vf_offset] = bitmap;
601 ret = hns3_cmd_send(hw, &desc, 1);
603 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
609 struct hns3_rx_vtag_cfg *vcfg)
611 struct hns3_pf *pf = &hns->pf;
612 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
617 struct hns3_tx_vtag_cfg *vcfg)
619 struct hns3_pf *pf = &hns->pf;
620 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
626 struct hns3_rx_vtag_cfg rxvlan_cfg;
627 struct hns3_hw *hw = &hns->hw;
630 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
631 rxvlan_cfg.strip_tag1_en = false;
632 rxvlan_cfg.strip_tag2_en = enable;
633 rxvlan_cfg.strip_tag2_discard_en = false;
635 rxvlan_cfg.strip_tag1_en = enable;
636 rxvlan_cfg.strip_tag2_en = true;
637 rxvlan_cfg.strip_tag2_discard_en = true;
640 rxvlan_cfg.strip_tag1_discard_en = false;
641 rxvlan_cfg.vlan1_vlan_prionly = false;
642 rxvlan_cfg.vlan2_vlan_prionly = false;
643 rxvlan_cfg.rx_vlan_offload_en = enable;
645 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
647 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
651 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
658 uint8_t fe_type, bool filter_en, uint8_t vf_id)
660 struct hns3_vlan_filter_ctrl_cmd *req;
661 struct hns3_cmd_desc desc;
664 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
666 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
667 req->vlan_type = vlan_type;
668 req->vlan_fe = filter_en ? fe_type : 0;
671 ret = hns3_cmd_send(hw, &desc, 1);
673 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
679 hns3_vlan_filter_init(struct hns3_adapter *hns)
681 struct hns3_hw *hw = &hns->hw;
684 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
685 HNS3_FILTER_FE_EGRESS, false,
688 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
692 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
693 HNS3_FILTER_FE_INGRESS, false,
696 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
704 struct hns3_hw *hw = &hns->hw;
707 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
708 HNS3_FILTER_FE_INGRESS, enable,
711 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
712 enable ? "enable" : "disable", ret);
718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
720 struct hns3_adapter *hns = dev->data->dev_private;
721 struct hns3_hw *hw = &hns->hw;
722 struct rte_eth_rxmode *rxmode;
723 unsigned int tmp_mask;
727 rte_spinlock_lock(&hw->lock);
728 rxmode = &dev->data->dev_conf.rxmode;
729 tmp_mask = (unsigned int)mask;
730 if (tmp_mask & ETH_VLAN_FILTER_MASK) {
731 /* ignore vlan filter configuration during promiscuous mode */
732 if (!dev->data->promiscuous) {
733 /* Enable or disable VLAN filter */
734 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
737 ret = hns3_enable_vlan_filter(hns, enable);
739 rte_spinlock_unlock(&hw->lock);
740 hns3_err(hw, "failed to %s rx filter, ret = %d",
741 enable ? "enable" : "disable", ret);
747 if (tmp_mask & ETH_VLAN_STRIP_MASK) {
748 /* Enable or disable VLAN stripping */
749 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
752 ret = hns3_en_hw_strip_rxvtag(hns, enable);
754 rte_spinlock_unlock(&hw->lock);
755 hns3_err(hw, "failed to %s rx strip, ret = %d",
756 enable ? "enable" : "disable", ret);
761 rte_spinlock_unlock(&hw->lock);
767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
768 struct hns3_tx_vtag_cfg *vcfg)
770 struct hns3_vport_vtag_tx_cfg_cmd *req;
771 struct hns3_cmd_desc desc;
772 struct hns3_hw *hw = &hns->hw;
777 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
779 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
780 req->def_vlan_tag1 = vcfg->default_tag1;
781 req->def_vlan_tag2 = vcfg->default_tag2;
782 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
783 vcfg->accept_tag1 ? 1 : 0);
784 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
785 vcfg->accept_untag1 ? 1 : 0);
786 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
787 vcfg->accept_tag2 ? 1 : 0);
788 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
789 vcfg->accept_untag2 ? 1 : 0);
790 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
791 vcfg->insert_tag1_en ? 1 : 0);
792 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
793 vcfg->insert_tag2_en ? 1 : 0);
794 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
796 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
797 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
798 vcfg->tag_shift_mode_en ? 1 : 0);
801 * In current version VF is not supported when PF is driven by DPDK
802 * driver, just need to configure parameters for PF vport.
804 vport_id = HNS3_PF_FUNC_ID;
805 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
806 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
807 req->vf_bitmap[req->vf_offset] = bitmap;
809 ret = hns3_cmd_send(hw, &desc, 1);
811 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
820 struct hns3_hw *hw = &hns->hw;
821 struct hns3_tx_vtag_cfg txvlan_cfg;
824 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
825 txvlan_cfg.accept_tag1 = true;
826 txvlan_cfg.insert_tag1_en = false;
827 txvlan_cfg.default_tag1 = 0;
829 txvlan_cfg.accept_tag1 =
830 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
831 txvlan_cfg.insert_tag1_en = true;
832 txvlan_cfg.default_tag1 = pvid;
835 txvlan_cfg.accept_untag1 = true;
836 txvlan_cfg.accept_tag2 = true;
837 txvlan_cfg.accept_untag2 = true;
838 txvlan_cfg.insert_tag2_en = false;
839 txvlan_cfg.default_tag2 = 0;
840 txvlan_cfg.tag_shift_mode_en = true;
842 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
844 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
849 hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
857 struct hns3_user_vlan_table *vlan_entry;
858 struct hns3_pf *pf = &hns->pf;
860 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
861 if (vlan_entry->hd_tbl_status) {
862 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
863 vlan_entry->hd_tbl_status = false;
868 vlan_entry = LIST_FIRST(&pf->vlan_list);
870 LIST_REMOVE(vlan_entry, next);
871 rte_free(vlan_entry);
872 vlan_entry = LIST_FIRST(&pf->vlan_list);
878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
880 struct hns3_user_vlan_table *vlan_entry;
881 struct hns3_pf *pf = &hns->pf;
883 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
884 if (!vlan_entry->hd_tbl_status) {
885 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
886 vlan_entry->hd_tbl_status = true;
892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
894 struct hns3_hw *hw = &hns->hw;
897 hns3_rm_all_vlan_table(hns, true);
898 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
899 ret = hns3_set_port_vlan_filter(hns,
900 hw->port_base_vlan_cfg.pvid, 0);
902 hns3_err(hw, "Failed to remove all vlan table, ret =%d",
910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
911 uint16_t port_base_vlan_state, uint16_t new_pvid)
913 struct hns3_hw *hw = &hns->hw;
917 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
918 old_pvid = hw->port_base_vlan_cfg.pvid;
919 if (old_pvid != HNS3_INVALID_PVID) {
920 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
922 hns3_err(hw, "failed to remove old pvid %u, "
923 "ret = %d", old_pvid, ret);
928 hns3_rm_all_vlan_table(hns, false);
929 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
931 hns3_err(hw, "failed to add new pvid %u, ret = %d",
936 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
938 hns3_err(hw, "failed to remove pvid %u, ret = %d",
943 hns3_add_all_vlan_table(hns);
949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
951 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
952 struct hns3_rx_vtag_cfg rx_vlan_cfg;
956 rx_strip_en = old_cfg->rx_vlan_offload_en;
958 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
959 rx_vlan_cfg.strip_tag2_en = true;
960 rx_vlan_cfg.strip_tag2_discard_en = true;
962 rx_vlan_cfg.strip_tag1_en = false;
963 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
964 rx_vlan_cfg.strip_tag2_discard_en = false;
966 rx_vlan_cfg.strip_tag1_discard_en = false;
967 rx_vlan_cfg.vlan1_vlan_prionly = false;
968 rx_vlan_cfg.vlan2_vlan_prionly = false;
969 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
971 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
975 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
982 struct hns3_hw *hw = &hns->hw;
983 uint16_t port_base_vlan_state;
986 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
987 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
988 hns3_warn(hw, "Invalid operation! As current pvid set "
989 "is %u, disable pvid %u is invalid",
990 hw->port_base_vlan_cfg.pvid, pvid);
994 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
995 HNS3_PORT_BASE_VLAN_DISABLE;
996 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
998 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
1003 ret = hns3_en_pvid_strip(hns, on);
1005 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1010 if (pvid == HNS3_INVALID_PVID)
1012 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1014 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1020 hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1026 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1028 struct hns3_adapter *hns = dev->data->dev_private;
1029 struct hns3_hw *hw = &hns->hw;
1030 bool pvid_en_state_change;
1031 uint16_t pvid_state;
1034 if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1035 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1036 RTE_ETHER_MAX_VLAN_ID);
1041 * If PVID configuration state change, should refresh the PVID
1042 * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1044 pvid_state = hw->port_base_vlan_cfg.state;
1045 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1046 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1047 pvid_en_state_change = false;
1049 pvid_en_state_change = true;
1051 rte_spinlock_lock(&hw->lock);
1052 ret = hns3_vlan_pvid_configure(hns, pvid, on);
1053 rte_spinlock_unlock(&hw->lock);
1057 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1058 * need be processed by PMD driver.
1060 if (pvid_en_state_change &&
1061 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1062 hns3_update_all_queues_pvid_proc_en(hw);
1068 hns3_default_vlan_config(struct hns3_adapter *hns)
1070 struct hns3_hw *hw = &hns->hw;
1074 * When vlan filter is enabled, hardware regards packets without vlan
1075 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1076 * table, packets without vlan won't be received. So, add vlan 0 as
1079 ret = hns3_vlan_filter_configure(hns, 0, 1);
1081 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1086 hns3_init_vlan_config(struct hns3_adapter *hns)
1088 struct hns3_hw *hw = &hns->hw;
1092 * This function can be called in the initialization and reset process,
1093 * when in reset process, it means that hardware had been reseted
1094 * successfully and we need to restore the hardware configuration to
1095 * ensure that the hardware configuration remains unchanged before and
1098 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1099 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1100 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1103 ret = hns3_vlan_filter_init(hns);
1105 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1109 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1110 RTE_ETHER_TYPE_VLAN);
1112 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1117 * When in the reinit dev stage of the reset process, the following
1118 * vlan-related configurations may differ from those at initialization,
1119 * we will restore configurations to hardware in hns3_restore_vlan_table
1120 * and hns3_restore_vlan_conf later.
1122 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1123 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1125 hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1129 ret = hns3_en_hw_strip_rxvtag(hns, false);
1131 hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1137 return hns3_default_vlan_config(hns);
1141 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1143 struct hns3_pf *pf = &hns->pf;
1144 struct hns3_hw *hw = &hns->hw;
1149 if (!hw->data->promiscuous) {
1150 /* restore vlan filter states */
1151 offloads = hw->data->dev_conf.rxmode.offloads;
1152 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1153 ret = hns3_enable_vlan_filter(hns, enable);
1155 hns3_err(hw, "failed to restore vlan rx filter conf, "
1161 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1163 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1167 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1169 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1175 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1177 struct hns3_adapter *hns = dev->data->dev_private;
1178 struct rte_eth_dev_data *data = dev->data;
1179 struct rte_eth_txmode *txmode;
1180 struct hns3_hw *hw = &hns->hw;
1184 txmode = &data->dev_conf.txmode;
1185 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1187 "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1188 "configuration is not supported! Ignore these two "
1189 "parameters: hw_vlan_reject_tagged(%u), "
1190 "hw_vlan_reject_untagged(%u)",
1191 txmode->hw_vlan_reject_tagged,
1192 txmode->hw_vlan_reject_untagged);
1194 /* Apply vlan offload setting */
1195 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1196 ret = hns3_vlan_offload_set(dev, mask);
1198 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1204 * If pvid config is not set in rte_eth_conf, driver needn't to set
1205 * VLAN pvid related configuration to hardware.
1207 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1210 /* Apply pvid setting */
1211 ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1212 txmode->hw_vlan_insert_pvid);
1214 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1221 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1222 unsigned int tso_mss_max)
1224 struct hns3_cfg_tso_status_cmd *req;
1225 struct hns3_cmd_desc desc;
1228 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1230 req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1233 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1235 req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1238 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1240 req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1242 return hns3_cmd_send(hw, &desc, 1);
1246 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1247 uint16_t *allocated_size, bool is_alloc)
1249 struct hns3_umv_spc_alc_cmd *req;
1250 struct hns3_cmd_desc desc;
1253 req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1254 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1255 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1256 req->space_size = rte_cpu_to_le_32(space_size);
1258 ret = hns3_cmd_send(hw, &desc, 1);
1260 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1261 is_alloc ? "allocate" : "free", ret);
1265 if (is_alloc && allocated_size)
1266 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1272 hns3_init_umv_space(struct hns3_hw *hw)
1274 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1275 struct hns3_pf *pf = &hns->pf;
1276 uint16_t allocated_size = 0;
1279 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1284 if (allocated_size < pf->wanted_umv_size)
1285 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1286 pf->wanted_umv_size, allocated_size);
1288 pf->max_umv_size = (!!allocated_size) ? allocated_size :
1289 pf->wanted_umv_size;
1290 pf->used_umv_size = 0;
1295 hns3_uninit_umv_space(struct hns3_hw *hw)
1297 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1298 struct hns3_pf *pf = &hns->pf;
1301 if (pf->max_umv_size == 0)
1304 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1308 pf->max_umv_size = 0;
1314 hns3_is_umv_space_full(struct hns3_hw *hw)
1316 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1317 struct hns3_pf *pf = &hns->pf;
1320 is_full = (pf->used_umv_size >= pf->max_umv_size);
1326 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1328 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329 struct hns3_pf *pf = &hns->pf;
1332 if (pf->used_umv_size > 0)
1333 pf->used_umv_size--;
1335 pf->used_umv_size++;
1339 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1340 const uint8_t *addr, bool is_mc)
1342 const unsigned char *mac_addr = addr;
1343 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1344 ((uint32_t)mac_addr[2] << 16) |
1345 ((uint32_t)mac_addr[1] << 8) |
1346 (uint32_t)mac_addr[0];
1347 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1349 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1351 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1352 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1353 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1356 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1357 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1361 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1363 enum hns3_mac_vlan_tbl_opcode op)
1366 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1371 if (op == HNS3_MAC_VLAN_ADD) {
1372 if (resp_code == 0 || resp_code == 1) {
1374 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1375 hns3_err(hw, "add mac addr failed for uc_overflow");
1377 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1378 hns3_err(hw, "add mac addr failed for mc_overflow");
1382 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1385 } else if (op == HNS3_MAC_VLAN_REMOVE) {
1386 if (resp_code == 0) {
1388 } else if (resp_code == 1) {
1389 hns3_dbg(hw, "remove mac addr failed for miss");
1393 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1396 } else if (op == HNS3_MAC_VLAN_LKUP) {
1397 if (resp_code == 0) {
1399 } else if (resp_code == 1) {
1400 hns3_dbg(hw, "lookup mac addr failed for miss");
1404 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1409 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1416 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1417 struct hns3_mac_vlan_tbl_entry_cmd *req,
1418 struct hns3_cmd_desc *desc, bool is_mc)
1424 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1426 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1427 memcpy(desc[0].data, req,
1428 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1429 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1431 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1432 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1434 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1436 memcpy(desc[0].data, req,
1437 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1438 ret = hns3_cmd_send(hw, desc, 1);
1441 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1445 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1446 retval = rte_le_to_cpu_16(desc[0].retval);
1448 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1449 HNS3_MAC_VLAN_LKUP);
1453 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1454 struct hns3_mac_vlan_tbl_entry_cmd *req,
1455 struct hns3_cmd_desc *mc_desc)
1462 if (mc_desc == NULL) {
1463 struct hns3_cmd_desc desc;
1465 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1466 memcpy(desc.data, req,
1467 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1468 ret = hns3_cmd_send(hw, &desc, 1);
1469 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1470 retval = rte_le_to_cpu_16(desc.retval);
1472 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1475 hns3_cmd_reuse_desc(&mc_desc[0], false);
1476 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1477 hns3_cmd_reuse_desc(&mc_desc[1], false);
1478 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1479 hns3_cmd_reuse_desc(&mc_desc[2], false);
1480 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1481 memcpy(mc_desc[0].data, req,
1482 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1483 mc_desc[0].retval = 0;
1484 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1485 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1486 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1488 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1493 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1501 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1502 struct hns3_mac_vlan_tbl_entry_cmd *req)
1504 struct hns3_cmd_desc desc;
1509 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1511 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1513 ret = hns3_cmd_send(hw, &desc, 1);
1515 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1518 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1519 retval = rte_le_to_cpu_16(desc.retval);
1521 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1522 HNS3_MAC_VLAN_REMOVE);
1526 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1528 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1529 struct hns3_mac_vlan_tbl_entry_cmd req;
1530 struct hns3_pf *pf = &hns->pf;
1531 struct hns3_cmd_desc desc[3];
1532 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1533 uint16_t egress_port = 0;
1537 /* check if mac addr is valid */
1538 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1539 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1541 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1546 memset(&req, 0, sizeof(req));
1549 * In current version VF is not supported when PF is driven by DPDK
1550 * driver, just need to configure parameters for PF vport.
1552 vf_id = HNS3_PF_FUNC_ID;
1553 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1554 HNS3_MAC_EPORT_VFID_S, vf_id);
1556 req.egress_port = rte_cpu_to_le_16(egress_port);
1558 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1561 * Lookup the mac address in the mac_vlan table, and add
1562 * it if the entry is inexistent. Repeated unicast entry
1563 * is not allowed in the mac vlan table.
1565 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1566 if (ret == -ENOENT) {
1567 if (!hns3_is_umv_space_full(hw)) {
1568 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1570 hns3_update_umv_space(hw, false);
1574 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1579 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1581 /* check if we just hit the duplicate */
1583 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1587 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1594 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1596 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1597 struct rte_ether_addr *addr;
1601 for (i = 0; i < hw->mc_addrs_num; i++) {
1602 addr = &hw->mc_addrs[i];
1603 /* Check if there are duplicate addresses */
1604 if (rte_is_same_ether_addr(addr, mac_addr)) {
1605 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1607 hns3_err(hw, "failed to add mc mac addr, same addrs"
1608 "(%s) is added by the set_mc_mac_addr_list "
1614 ret = hns3_add_mc_addr(hw, mac_addr);
1616 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1618 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1625 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1627 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1630 ret = hns3_remove_mc_addr(hw, mac_addr);
1632 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1641 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1642 uint32_t idx, __rte_unused uint32_t pool)
1644 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1648 rte_spinlock_lock(&hw->lock);
1651 * In hns3 network engine adding UC and MC mac address with different
1652 * commands with firmware. We need to determine whether the input
1653 * address is a UC or a MC address to call different commands.
1654 * By the way, it is recommended calling the API function named
1655 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1656 * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1657 * may affect the specifications of UC mac addresses.
1659 if (rte_is_multicast_ether_addr(mac_addr))
1660 ret = hns3_add_mc_addr_common(hw, mac_addr);
1662 ret = hns3_add_uc_addr_common(hw, mac_addr);
1665 rte_spinlock_unlock(&hw->lock);
1666 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1668 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1674 hw->mac.default_addr_setted = true;
1675 rte_spinlock_unlock(&hw->lock);
1681 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1683 struct hns3_mac_vlan_tbl_entry_cmd req;
1684 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1687 /* check if mac addr is valid */
1688 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1689 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1691 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1696 memset(&req, 0, sizeof(req));
1697 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1698 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1699 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1700 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1703 hns3_update_umv_space(hw, true);
1709 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1711 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 /* index will be checked by upper level rte interface */
1713 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1714 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1717 rte_spinlock_lock(&hw->lock);
1719 if (rte_is_multicast_ether_addr(mac_addr))
1720 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1722 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1723 rte_spinlock_unlock(&hw->lock);
1725 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1727 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1733 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1734 struct rte_ether_addr *mac_addr)
1736 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 struct rte_ether_addr *oaddr;
1738 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1739 bool default_addr_setted;
1740 bool rm_succes = false;
1744 * It has been guaranteed that input parameter named mac_addr is valid
1745 * address in the rte layer of DPDK framework.
1747 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1748 default_addr_setted = hw->mac.default_addr_setted;
1749 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1752 rte_spinlock_lock(&hw->lock);
1753 if (default_addr_setted) {
1754 ret = hns3_remove_uc_addr_common(hw, oaddr);
1756 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1758 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1765 ret = hns3_add_uc_addr_common(hw, mac_addr);
1767 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1769 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1770 goto err_add_uc_addr;
1773 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1775 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1776 goto err_pause_addr_cfg;
1779 rte_ether_addr_copy(mac_addr,
1780 (struct rte_ether_addr *)hw->mac.mac_addr);
1781 hw->mac.default_addr_setted = true;
1782 rte_spinlock_unlock(&hw->lock);
1787 ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1789 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1792 "Failed to roll back to del setted mac addr(%s): %d",
1798 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1800 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803 "Failed to restore old uc mac addr(%s): %d",
1805 hw->mac.default_addr_setted = false;
1808 rte_spinlock_unlock(&hw->lock);
1814 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1816 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1817 struct hns3_hw *hw = &hns->hw;
1818 struct rte_ether_addr *addr;
1823 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1824 addr = &hw->data->mac_addrs[i];
1825 if (rte_is_zero_ether_addr(addr))
1827 if (rte_is_multicast_ether_addr(addr))
1828 ret = del ? hns3_remove_mc_addr(hw, addr) :
1829 hns3_add_mc_addr(hw, addr);
1831 ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1832 hns3_add_uc_addr_common(hw, addr);
1836 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1838 hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1839 "ret = %d.", del ? "remove" : "restore",
1847 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1849 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1853 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1854 word_num = vfid / 32;
1855 bit_num = vfid % 32;
1857 desc[1].data[word_num] &=
1858 rte_cpu_to_le_32(~(1UL << bit_num));
1860 desc[1].data[word_num] |=
1861 rte_cpu_to_le_32(1UL << bit_num);
1863 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1864 bit_num = vfid % 32;
1866 desc[2].data[word_num] &=
1867 rte_cpu_to_le_32(~(1UL << bit_num));
1869 desc[2].data[word_num] |=
1870 rte_cpu_to_le_32(1UL << bit_num);
1875 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1877 struct hns3_mac_vlan_tbl_entry_cmd req;
1878 struct hns3_cmd_desc desc[3];
1879 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1883 /* Check if mac addr is valid */
1884 if (!rte_is_multicast_ether_addr(mac_addr)) {
1885 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1887 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1892 memset(&req, 0, sizeof(req));
1893 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1894 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1895 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1897 /* This mac addr do not exist, add new entry for it */
1898 memset(desc[0].data, 0, sizeof(desc[0].data));
1899 memset(desc[1].data, 0, sizeof(desc[0].data));
1900 memset(desc[2].data, 0, sizeof(desc[0].data));
1904 * In current version VF is not supported when PF is driven by DPDK
1905 * driver, just need to configure parameters for PF vport.
1907 vf_id = HNS3_PF_FUNC_ID;
1908 hns3_update_desc_vfid(desc, vf_id, false);
1909 ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1912 hns3_err(hw, "mc mac vlan table is full");
1913 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1915 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1922 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1924 struct hns3_mac_vlan_tbl_entry_cmd req;
1925 struct hns3_cmd_desc desc[3];
1926 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1930 /* Check if mac addr is valid */
1931 if (!rte_is_multicast_ether_addr(mac_addr)) {
1932 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1934 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1939 memset(&req, 0, sizeof(req));
1940 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1941 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1942 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1945 * This mac addr exist, remove this handle's VFID for it.
1946 * In current version VF is not supported when PF is driven by
1947 * DPDK driver, just need to configure parameters for PF vport.
1949 vf_id = HNS3_PF_FUNC_ID;
1950 hns3_update_desc_vfid(desc, vf_id, true);
1952 /* All the vfid is zero, so need to delete this entry */
1953 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1954 } else if (ret == -ENOENT) {
1955 /* This mac addr doesn't exist. */
1960 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1962 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1969 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1970 struct rte_ether_addr *mc_addr_set,
1971 uint32_t nb_mc_addr)
1973 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1974 struct rte_ether_addr *addr;
1978 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1979 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1980 "invalid. valid range: 0~%d",
1981 nb_mc_addr, HNS3_MC_MACADDR_NUM);
1985 /* Check if input mac addresses are valid */
1986 for (i = 0; i < nb_mc_addr; i++) {
1987 addr = &mc_addr_set[i];
1988 if (!rte_is_multicast_ether_addr(addr)) {
1989 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1992 "failed to set mc mac addr, addr(%s) invalid.",
1997 /* Check if there are duplicate addresses */
1998 for (j = i + 1; j < nb_mc_addr; j++) {
1999 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2000 hns3_ether_format_addr(mac_str,
2001 RTE_ETHER_ADDR_FMT_SIZE,
2003 hns3_err(hw, "failed to set mc mac addr, "
2004 "addrs invalid. two same addrs(%s).",
2011 * Check if there are duplicate addresses between mac_addrs
2014 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2015 if (rte_is_same_ether_addr(addr,
2016 &hw->data->mac_addrs[j])) {
2017 hns3_ether_format_addr(mac_str,
2018 RTE_ETHER_ADDR_FMT_SIZE,
2020 hns3_err(hw, "failed to set mc mac addr, "
2021 "addrs invalid. addrs(%s) has already "
2022 "configured in mac_addr add API",
2033 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2034 struct rte_ether_addr *mc_addr_set,
2036 struct rte_ether_addr *reserved_addr_list,
2037 int *reserved_addr_num,
2038 struct rte_ether_addr *add_addr_list,
2040 struct rte_ether_addr *rm_addr_list,
2043 struct rte_ether_addr *addr;
2044 int current_addr_num;
2045 int reserved_num = 0;
2053 /* Calculate the mc mac address list that should be removed */
2054 current_addr_num = hw->mc_addrs_num;
2055 for (i = 0; i < current_addr_num; i++) {
2056 addr = &hw->mc_addrs[i];
2058 for (j = 0; j < mc_addr_num; j++) {
2059 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2066 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2069 rte_ether_addr_copy(addr,
2070 &reserved_addr_list[reserved_num]);
2075 /* Calculate the mc mac address list that should be added */
2076 for (i = 0; i < mc_addr_num; i++) {
2077 addr = &mc_addr_set[i];
2079 for (j = 0; j < current_addr_num; j++) {
2080 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2087 rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2092 /* Reorder the mc mac address list maintained by driver */
2093 for (i = 0; i < reserved_num; i++)
2094 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2096 for (i = 0; i < rm_num; i++) {
2097 num = reserved_num + i;
2098 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2101 *reserved_addr_num = reserved_num;
2102 *add_addr_num = add_num;
2103 *rm_addr_num = rm_num;
2107 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2108 struct rte_ether_addr *mc_addr_set,
2109 uint32_t nb_mc_addr)
2111 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2113 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2114 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2115 struct rte_ether_addr *addr;
2116 int reserved_addr_num;
2124 /* Check if input parameters are valid */
2125 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2129 rte_spinlock_lock(&hw->lock);
2132 * Calculate the mc mac address lists those should be removed and be
2133 * added, Reorder the mc mac address list maintained by driver.
2135 mc_addr_num = (int)nb_mc_addr;
2136 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2137 reserved_addr_list, &reserved_addr_num,
2138 add_addr_list, &add_addr_num,
2139 rm_addr_list, &rm_addr_num);
2141 /* Remove mc mac addresses */
2142 for (i = 0; i < rm_addr_num; i++) {
2143 num = rm_addr_num - i - 1;
2144 addr = &rm_addr_list[num];
2145 ret = hns3_remove_mc_addr(hw, addr);
2147 rte_spinlock_unlock(&hw->lock);
2153 /* Add mc mac addresses */
2154 for (i = 0; i < add_addr_num; i++) {
2155 addr = &add_addr_list[i];
2156 ret = hns3_add_mc_addr(hw, addr);
2158 rte_spinlock_unlock(&hw->lock);
2162 num = reserved_addr_num + i;
2163 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2166 rte_spinlock_unlock(&hw->lock);
2172 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2174 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2175 struct hns3_hw *hw = &hns->hw;
2176 struct rte_ether_addr *addr;
2181 for (i = 0; i < hw->mc_addrs_num; i++) {
2182 addr = &hw->mc_addrs[i];
2183 if (!rte_is_multicast_ether_addr(addr))
2186 ret = hns3_remove_mc_addr(hw, addr);
2188 ret = hns3_add_mc_addr(hw, addr);
2191 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2193 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2194 del ? "Remove" : "Restore", mac_str, ret);
2201 hns3_check_mq_mode(struct rte_eth_dev *dev)
2203 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2204 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2205 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2207 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2208 struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2213 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2214 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2216 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2217 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2218 "rx_mq_mode = %d", rx_mq_mode);
2222 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2223 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2224 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2225 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2226 rx_mq_mode, tx_mq_mode);
2230 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2231 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2232 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2233 dcb_rx_conf->nb_tcs, pf->tc_max);
2237 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2238 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2239 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2240 "nb_tcs(%d) != %d or %d in rx direction.",
2241 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2245 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2246 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2247 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2251 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2252 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2253 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2254 "is not equal to one in tx direction.",
2255 i, dcb_rx_conf->dcb_tc[i]);
2258 if (dcb_rx_conf->dcb_tc[i] > max_tc)
2259 max_tc = dcb_rx_conf->dcb_tc[i];
2262 num_tc = max_tc + 1;
2263 if (num_tc > dcb_rx_conf->nb_tcs) {
2264 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2265 num_tc, dcb_rx_conf->nb_tcs);
2274 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2276 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278 if (!hns3_dev_dcb_supported(hw)) {
2279 hns3_err(hw, "this port does not support dcb configurations.");
2283 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2284 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2288 /* Check multiple queue mode */
2289 return hns3_check_mq_mode(dev);
2293 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2294 enum hns3_ring_type queue_type, uint16_t queue_id)
2296 struct hns3_cmd_desc desc;
2297 struct hns3_ctrl_vector_chain_cmd *req =
2298 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2299 enum hns3_cmd_status status;
2300 enum hns3_opcode_type op;
2301 uint16_t tqp_type_and_id = 0;
2305 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2306 hns3_cmd_setup_basic_desc(&desc, op, false);
2307 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2308 HNS3_TQP_INT_ID_L_S);
2309 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2310 HNS3_TQP_INT_ID_H_S);
2312 if (queue_type == HNS3_RING_TYPE_RX)
2313 gl = HNS3_RING_GL_RX;
2315 gl = HNS3_RING_GL_TX;
2319 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2321 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2322 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2324 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2325 req->int_cause_num = 1;
2326 status = hns3_cmd_send(hw, &desc, 1);
2328 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2329 en ? "Map" : "Unmap", queue_id, vector_id, status);
2337 hns3_init_ring_with_vector(struct hns3_hw *hw)
2344 * In hns3 network engine, vector 0 is always the misc interrupt of this
2345 * function, vector 1~N can be used respectively for the queues of the
2346 * function. Tx and Rx queues with the same number share the interrupt
2347 * vector. In the initialization clearing the all hardware mapping
2348 * relationship configurations between queues and interrupt vectors is
2349 * needed, so some error caused by the residual configurations, such as
2350 * the unexpected Tx interrupt, can be avoid.
2352 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2353 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2354 vec = vec - 1; /* the last interrupt is reserved */
2355 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2356 for (i = 0; i < hw->intr_tqps_num; i++) {
2358 * Set gap limiter/rate limiter/quanity limiter algorithm
2359 * configuration for interrupt coalesce of queue's interrupt.
2361 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2362 HNS3_TQP_INTR_GL_DEFAULT);
2363 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2364 HNS3_TQP_INTR_GL_DEFAULT);
2365 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2367 * QL(quantity limiter) is not used currently, just set 0 to
2370 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2372 ret = hns3_bind_ring_with_vector(hw, vec, false,
2373 HNS3_RING_TYPE_TX, i);
2375 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2376 "vector: %u, ret=%d", i, vec, ret);
2380 ret = hns3_bind_ring_with_vector(hw, vec, false,
2381 HNS3_RING_TYPE_RX, i);
2383 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2384 "vector: %u, ret=%d", i, vec, ret);
2393 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2395 struct hns3_adapter *hns = dev->data->dev_private;
2396 struct hns3_hw *hw = &hns->hw;
2397 uint32_t max_rx_pkt_len;
2401 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2405 * If jumbo frames are enabled, MTU needs to be refreshed
2406 * according to the maximum RX packet length.
2408 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2409 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2410 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2411 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2412 "and no more than %u when jumbo frame enabled.",
2413 (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2414 (uint16_t)HNS3_MAX_FRAME_LEN);
2418 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2419 ret = hns3_dev_mtu_set(dev, mtu);
2422 dev->data->mtu = mtu;
2428 hns3_dev_configure(struct rte_eth_dev *dev)
2430 struct hns3_adapter *hns = dev->data->dev_private;
2431 struct rte_eth_conf *conf = &dev->data->dev_conf;
2432 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2433 struct hns3_hw *hw = &hns->hw;
2434 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2435 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2436 struct rte_eth_rss_conf rss_conf;
2440 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2443 * Some versions of hardware network engine does not support
2444 * individually enable/disable/reset the Tx or Rx queue. These devices
2445 * must enable/disable/reset Tx and Rx queues at the same time. When the
2446 * numbers of Tx queues allocated by upper applications are not equal to
2447 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2448 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2449 * work as usual. But these fake queues are imperceptible, and can not
2450 * be used by upper applications.
2452 if (!hns3_dev_indep_txrx_supported(hw)) {
2453 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2455 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2461 hw->adapter_state = HNS3_NIC_CONFIGURING;
2462 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2463 hns3_err(hw, "setting link speed/duplex not supported");
2468 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2469 ret = hns3_check_dcb_cfg(dev);
2474 /* When RSS is not configured, redirect the packet queue 0 */
2475 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2476 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2477 rss_conf = conf->rx_adv_conf.rss_conf;
2478 hw->rss_dis_flag = false;
2479 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2484 ret = hns3_refresh_mtu(dev, conf);
2488 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2492 ret = hns3_dev_configure_vlan(dev);
2496 /* config hardware GRO */
2497 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2498 ret = hns3_config_gro(hw, gro_en);
2502 hns->rx_simple_allowed = true;
2503 hns->rx_vec_allowed = true;
2504 hns->tx_simple_allowed = true;
2505 hns->tx_vec_allowed = true;
2507 hns3_init_rx_ptype_tble(dev);
2508 hw->adapter_state = HNS3_NIC_CONFIGURED;
2513 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2514 hw->adapter_state = HNS3_NIC_INITIALIZED;
2520 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2522 struct hns3_config_max_frm_size_cmd *req;
2523 struct hns3_cmd_desc desc;
2525 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2527 req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2528 req->max_frm_size = rte_cpu_to_le_16(new_mps);
2529 req->min_frm_size = RTE_ETHER_MIN_LEN;
2531 return hns3_cmd_send(hw, &desc, 1);
2535 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2537 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2538 uint16_t original_mps = hns->pf.mps;
2542 ret = hns3_set_mac_mtu(hw, mps);
2544 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2549 ret = hns3_buffer_alloc(hw);
2551 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2558 err = hns3_set_mac_mtu(hw, original_mps);
2560 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2563 hns->pf.mps = original_mps;
2569 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2571 struct hns3_adapter *hns = dev->data->dev_private;
2572 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2573 struct hns3_hw *hw = &hns->hw;
2574 bool is_jumbo_frame;
2577 if (dev->data->dev_started) {
2578 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2579 "before configuration", dev->data->port_id);
2583 rte_spinlock_lock(&hw->lock);
2584 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2585 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2588 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2589 * assign to "uint16_t" type variable.
2591 ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2593 rte_spinlock_unlock(&hw->lock);
2594 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2595 dev->data->port_id, mtu, ret);
2600 dev->data->dev_conf.rxmode.offloads |=
2601 DEV_RX_OFFLOAD_JUMBO_FRAME;
2603 dev->data->dev_conf.rxmode.offloads &=
2604 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2605 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2606 rte_spinlock_unlock(&hw->lock);
2612 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2614 struct hns3_adapter *hns = eth_dev->data->dev_private;
2615 struct hns3_hw *hw = &hns->hw;
2616 uint16_t queue_num = hw->tqps_num;
2619 * In interrupt mode, 'max_rx_queues' is set based on the number of
2620 * MSI-X interrupt resources of the hardware.
2622 if (hw->data->dev_conf.intr_conf.rxq == 1)
2623 queue_num = hw->intr_tqps_num;
2625 info->max_rx_queues = queue_num;
2626 info->max_tx_queues = hw->tqps_num;
2627 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2628 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2629 info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2630 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2631 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2632 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2633 DEV_RX_OFFLOAD_TCP_CKSUM |
2634 DEV_RX_OFFLOAD_UDP_CKSUM |
2635 DEV_RX_OFFLOAD_SCTP_CKSUM |
2636 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2637 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2638 DEV_RX_OFFLOAD_KEEP_CRC |
2639 DEV_RX_OFFLOAD_SCATTER |
2640 DEV_RX_OFFLOAD_VLAN_STRIP |
2641 DEV_RX_OFFLOAD_VLAN_FILTER |
2642 DEV_RX_OFFLOAD_JUMBO_FRAME |
2643 DEV_RX_OFFLOAD_RSS_HASH |
2644 DEV_RX_OFFLOAD_TCP_LRO);
2645 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2646 DEV_TX_OFFLOAD_IPV4_CKSUM |
2647 DEV_TX_OFFLOAD_TCP_CKSUM |
2648 DEV_TX_OFFLOAD_UDP_CKSUM |
2649 DEV_TX_OFFLOAD_SCTP_CKSUM |
2650 DEV_TX_OFFLOAD_MULTI_SEGS |
2651 DEV_TX_OFFLOAD_TCP_TSO |
2652 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2653 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2654 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2655 DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2656 hns3_txvlan_cap_get(hw));
2658 if (hns3_dev_outer_udp_cksum_supported(hw))
2659 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2661 if (hns3_dev_indep_txrx_supported(hw))
2662 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2663 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2665 if (hns3_dev_ptp_supported(hw))
2666 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2668 info->rx_desc_lim = (struct rte_eth_desc_lim) {
2669 .nb_max = HNS3_MAX_RING_DESC,
2670 .nb_min = HNS3_MIN_RING_DESC,
2671 .nb_align = HNS3_ALIGN_RING_DESC,
2674 info->tx_desc_lim = (struct rte_eth_desc_lim) {
2675 .nb_max = HNS3_MAX_RING_DESC,
2676 .nb_min = HNS3_MIN_RING_DESC,
2677 .nb_align = HNS3_ALIGN_RING_DESC,
2678 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2679 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2682 info->default_rxconf = (struct rte_eth_rxconf) {
2683 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2685 * If there are no available Rx buffer descriptors, incoming
2686 * packets are always dropped by hardware based on hns3 network
2692 info->default_txconf = (struct rte_eth_txconf) {
2693 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2697 info->vmdq_queue_num = 0;
2699 info->reta_size = hw->rss_ind_tbl_size;
2700 info->hash_key_size = HNS3_RSS_KEY_SIZE;
2701 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2703 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2704 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2705 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2706 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2707 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2708 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2714 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2717 struct hns3_adapter *hns = eth_dev->data->dev_private;
2718 struct hns3_hw *hw = &hns->hw;
2719 uint32_t version = hw->fw_version;
2722 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2723 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2724 HNS3_FW_VERSION_BYTE3_S),
2725 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2726 HNS3_FW_VERSION_BYTE2_S),
2727 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2728 HNS3_FW_VERSION_BYTE1_S),
2729 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2730 HNS3_FW_VERSION_BYTE0_S));
2731 ret += 1; /* add the size of '\0' */
2732 if (fw_size < (uint32_t)ret)
2739 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2741 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2743 (void)hns3_update_link_status(hw);
2745 return hns3_update_link_info(eth_dev);
2749 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2750 struct rte_eth_link *new_link)
2752 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2753 struct hns3_mac *mac = &hw->mac;
2755 switch (mac->link_speed) {
2756 case ETH_SPEED_NUM_10M:
2757 case ETH_SPEED_NUM_100M:
2758 case ETH_SPEED_NUM_1G:
2759 case ETH_SPEED_NUM_10G:
2760 case ETH_SPEED_NUM_25G:
2761 case ETH_SPEED_NUM_40G:
2762 case ETH_SPEED_NUM_50G:
2763 case ETH_SPEED_NUM_100G:
2764 case ETH_SPEED_NUM_200G:
2765 new_link->link_speed = mac->link_speed;
2768 if (mac->link_status)
2769 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2771 new_link->link_speed = ETH_SPEED_NUM_NONE;
2775 new_link->link_duplex = mac->link_duplex;
2776 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2777 new_link->link_autoneg =
2778 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2782 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2784 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */
2785 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */
2787 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2788 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2789 struct hns3_mac *mac = &hw->mac;
2790 struct rte_eth_link new_link;
2794 ret = hns3_update_port_link_info(eth_dev);
2796 mac->link_status = ETH_LINK_DOWN;
2797 hns3_err(hw, "failed to get port link info, ret = %d.",
2802 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2805 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2806 } while (retry_cnt--);
2808 memset(&new_link, 0, sizeof(new_link));
2809 hns3_setup_linkstatus(eth_dev, &new_link);
2811 return rte_eth_linkstatus_set(eth_dev, &new_link);
2815 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2817 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2818 struct hns3_pf *pf = &hns->pf;
2820 if (!(status->pf_state & HNS3_PF_STATE_DONE))
2823 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2829 hns3_query_function_status(struct hns3_hw *hw)
2831 #define HNS3_QUERY_MAX_CNT 10
2832 #define HNS3_QUERY_SLEEP_MSCOEND 1
2833 struct hns3_func_status_cmd *req;
2834 struct hns3_cmd_desc desc;
2838 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2839 req = (struct hns3_func_status_cmd *)desc.data;
2842 ret = hns3_cmd_send(hw, &desc, 1);
2844 PMD_INIT_LOG(ERR, "query function status failed %d",
2849 /* Check pf reset is done */
2853 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2854 } while (timeout++ < HNS3_QUERY_MAX_CNT);
2856 return hns3_parse_func_status(hw, req);
2860 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2862 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2863 struct hns3_pf *pf = &hns->pf;
2865 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2867 * The total_tqps_num obtained from firmware is maximum tqp
2868 * numbers of this port, which should be used for PF and VFs.
2869 * There is no need for pf to have so many tqp numbers in
2870 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2871 * coming from config file, is assigned to maximum queue number
2872 * for the PF of this port by user. So users can modify the
2873 * maximum queue number of PF according to their own application
2874 * scenarios, which is more flexible to use. In addition, many
2875 * memories can be saved due to allocating queue statistics
2876 * room according to the actual number of queues required. The
2877 * maximum queue number of PF for network engine with
2878 * revision_id greater than 0x30 is assigned by config file.
2880 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2881 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2882 "must be greater than 0.",
2883 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2887 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2888 hw->total_tqps_num);
2891 * Due to the limitation on the number of PF interrupts
2892 * available, the maximum queue number assigned to PF on
2893 * the network engine with revision_id 0x21 is 64.
2895 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2896 HNS3_MAX_TQP_NUM_HIP08_PF);
2903 hns3_query_pf_resource(struct hns3_hw *hw)
2905 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2906 struct hns3_pf *pf = &hns->pf;
2907 struct hns3_pf_res_cmd *req;
2908 struct hns3_cmd_desc desc;
2911 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2912 ret = hns3_cmd_send(hw, &desc, 1);
2914 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2918 req = (struct hns3_pf_res_cmd *)desc.data;
2919 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2920 rte_le_to_cpu_16(req->ext_tqp_num);
2921 ret = hns3_get_pf_max_tqp_num(hw);
2925 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2926 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2928 if (req->tx_buf_size)
2930 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2932 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2934 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2936 if (req->dv_buf_size)
2938 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2940 pf->dv_buf_size = HNS3_DEFAULT_DV;
2942 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2945 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2946 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2952 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2954 struct hns3_cfg_param_cmd *req;
2955 uint64_t mac_addr_tmp_high;
2956 uint8_t ext_rss_size_max;
2957 uint64_t mac_addr_tmp;
2960 req = (struct hns3_cfg_param_cmd *)desc[0].data;
2962 /* get the configuration */
2963 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2964 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2965 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2966 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2967 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2968 HNS3_CFG_TQP_DESC_N_M,
2969 HNS3_CFG_TQP_DESC_N_S);
2971 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2972 HNS3_CFG_PHY_ADDR_M,
2973 HNS3_CFG_PHY_ADDR_S);
2974 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2975 HNS3_CFG_MEDIA_TP_M,
2976 HNS3_CFG_MEDIA_TP_S);
2977 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2978 HNS3_CFG_RX_BUF_LEN_M,
2979 HNS3_CFG_RX_BUF_LEN_S);
2980 /* get mac address */
2981 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2982 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2983 HNS3_CFG_MAC_ADDR_H_M,
2984 HNS3_CFG_MAC_ADDR_H_S);
2986 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2988 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2989 HNS3_CFG_DEFAULT_SPEED_M,
2990 HNS3_CFG_DEFAULT_SPEED_S);
2991 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2992 HNS3_CFG_RSS_SIZE_M,
2993 HNS3_CFG_RSS_SIZE_S);
2995 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2996 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2998 req = (struct hns3_cfg_param_cmd *)desc[1].data;
2999 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3001 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3002 HNS3_CFG_SPEED_ABILITY_M,
3003 HNS3_CFG_SPEED_ABILITY_S);
3004 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3005 HNS3_CFG_UMV_TBL_SPACE_M,
3006 HNS3_CFG_UMV_TBL_SPACE_S);
3007 if (!cfg->umv_space)
3008 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3010 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3011 HNS3_CFG_EXT_RSS_SIZE_M,
3012 HNS3_CFG_EXT_RSS_SIZE_S);
3015 * Field ext_rss_size_max obtained from firmware will be more flexible
3016 * for future changes and expansions, which is an exponent of 2, instead
3017 * of reading out directly. If this field is not zero, hns3 PF PMD
3018 * driver uses it as rss_size_max under one TC. Device, whose revision
3019 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3020 * maximum number of queues supported under a TC through this field.
3022 if (ext_rss_size_max)
3023 cfg->rss_size_max = 1U << ext_rss_size_max;
3026 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3027 * @hw: pointer to struct hns3_hw
3028 * @hcfg: the config structure to be getted
3031 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3033 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3034 struct hns3_cfg_param_cmd *req;
3039 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3041 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3042 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3044 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3045 i * HNS3_CFG_RD_LEN_BYTES);
3046 /* Len should be divided by 4 when send to hardware */
3047 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3048 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3049 req->offset = rte_cpu_to_le_32(offset);
3052 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3054 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3058 hns3_parse_cfg(hcfg, desc);
3064 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3066 switch (speed_cmd) {
3067 case HNS3_CFG_SPEED_10M:
3068 *speed = ETH_SPEED_NUM_10M;
3070 case HNS3_CFG_SPEED_100M:
3071 *speed = ETH_SPEED_NUM_100M;
3073 case HNS3_CFG_SPEED_1G:
3074 *speed = ETH_SPEED_NUM_1G;
3076 case HNS3_CFG_SPEED_10G:
3077 *speed = ETH_SPEED_NUM_10G;
3079 case HNS3_CFG_SPEED_25G:
3080 *speed = ETH_SPEED_NUM_25G;
3082 case HNS3_CFG_SPEED_40G:
3083 *speed = ETH_SPEED_NUM_40G;
3085 case HNS3_CFG_SPEED_50G:
3086 *speed = ETH_SPEED_NUM_50G;
3088 case HNS3_CFG_SPEED_100G:
3089 *speed = ETH_SPEED_NUM_100G;
3091 case HNS3_CFG_SPEED_200G:
3092 *speed = ETH_SPEED_NUM_200G;
3102 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3104 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3105 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3106 hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3107 hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3108 hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3112 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3114 struct hns3_dev_specs_0_cmd *req0;
3116 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3118 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3119 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3120 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3121 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3122 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3126 hns3_check_dev_specifications(struct hns3_hw *hw)
3128 if (hw->rss_ind_tbl_size == 0 ||
3129 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3130 hns3_err(hw, "the size of hash lookup table configured (%u)"
3131 " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3132 HNS3_RSS_IND_TBL_SIZE_MAX);
3140 hns3_query_dev_specifications(struct hns3_hw *hw)
3142 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3146 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3147 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3149 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3151 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3153 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3157 hns3_parse_dev_specifications(hw, desc);
3159 return hns3_check_dev_specifications(hw);
3163 hns3_get_capability(struct hns3_hw *hw)
3165 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3166 struct rte_pci_device *pci_dev;
3167 struct hns3_pf *pf = &hns->pf;
3168 struct rte_eth_dev *eth_dev;
3173 eth_dev = &rte_eth_devices[hw->data->port_id];
3174 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3175 device_id = pci_dev->id.device_id;
3177 if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3178 device_id == HNS3_DEV_ID_50GE_RDMA ||
3179 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3180 device_id == HNS3_DEV_ID_200G_RDMA)
3181 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3183 /* Get PCI revision id */
3184 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3185 HNS3_PCI_REVISION_ID);
3186 if (ret != HNS3_PCI_REVISION_ID_LEN) {
3187 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3191 hw->revision = revision;
3193 if (revision < PCI_REVISION_ID_HIP09_A) {
3194 hns3_set_default_dev_specifications(hw);
3195 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3196 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3197 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3198 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3199 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3200 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3201 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3202 hw->rss_info.ipv6_sctp_offload_supported = false;
3203 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3207 ret = hns3_query_dev_specifications(hw);
3210 "failed to query dev specifications, ret = %d",
3215 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3216 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3217 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3218 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3219 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3220 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3221 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3222 hw->rss_info.ipv6_sctp_offload_supported = true;
3223 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3229 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3233 switch (media_type) {
3234 case HNS3_MEDIA_TYPE_COPPER:
3235 if (!hns3_dev_copper_supported(hw)) {
3237 "Media type is copper, not supported.");
3243 case HNS3_MEDIA_TYPE_FIBER:
3246 case HNS3_MEDIA_TYPE_BACKPLANE:
3247 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3251 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3260 hns3_get_board_configuration(struct hns3_hw *hw)
3262 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3263 struct hns3_pf *pf = &hns->pf;
3264 struct hns3_cfg cfg;
3267 ret = hns3_get_board_cfg(hw, &cfg);
3269 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3273 ret = hns3_check_media_type(hw, cfg.media_type);
3277 hw->mac.media_type = cfg.media_type;
3278 hw->rss_size_max = cfg.rss_size_max;
3279 hw->rss_dis_flag = false;
3280 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3281 hw->mac.phy_addr = cfg.phy_addr;
3282 hw->mac.default_addr_setted = false;
3283 hw->num_tx_desc = cfg.tqp_desc_num;
3284 hw->num_rx_desc = cfg.tqp_desc_num;
3285 hw->dcb_info.num_pg = 1;
3286 hw->dcb_info.hw_pfc_map = 0;
3288 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3290 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3291 cfg.default_speed, ret);
3295 pf->tc_max = cfg.tc_num;
3296 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3297 PMD_INIT_LOG(WARNING,
3298 "Get TC num(%u) from flash, set TC num to 1",
3303 /* Dev does not support DCB */
3304 if (!hns3_dev_dcb_supported(hw)) {
3308 pf->pfc_max = pf->tc_max;
3310 hw->dcb_info.num_tc = 1;
3311 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3312 hw->tqps_num / hw->dcb_info.num_tc);
3313 hns3_set_bit(hw->hw_tc_map, 0, 1);
3314 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3316 pf->wanted_umv_size = cfg.umv_space;
3322 hns3_get_configuration(struct hns3_hw *hw)
3326 ret = hns3_query_function_status(hw);
3328 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3332 /* Get device capability */
3333 ret = hns3_get_capability(hw);
3335 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3339 /* Get pf resource */
3340 ret = hns3_query_pf_resource(hw);
3342 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3346 ret = hns3_get_board_configuration(hw);
3348 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3352 ret = hns3_query_dev_fec_info(hw);
3355 "failed to query FEC information, ret = %d", ret);
3361 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3362 uint16_t tqp_vid, bool is_pf)
3364 struct hns3_tqp_map_cmd *req;
3365 struct hns3_cmd_desc desc;
3368 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3370 req = (struct hns3_tqp_map_cmd *)desc.data;
3371 req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3372 req->tqp_vf = func_id;
3373 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3375 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3376 req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3378 ret = hns3_cmd_send(hw, &desc, 1);
3380 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3386 hns3_map_tqp(struct hns3_hw *hw)
3392 * In current version, VF is not supported when PF is driven by DPDK
3393 * driver, so we assign total tqps_num tqps allocated to this port
3396 for (i = 0; i < hw->total_tqps_num; i++) {
3397 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3406 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3408 struct hns3_config_mac_speed_dup_cmd *req;
3409 struct hns3_cmd_desc desc;
3412 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3414 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3416 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3419 case ETH_SPEED_NUM_10M:
3420 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3421 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3423 case ETH_SPEED_NUM_100M:
3424 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3425 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3427 case ETH_SPEED_NUM_1G:
3428 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3429 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3431 case ETH_SPEED_NUM_10G:
3432 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3433 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3435 case ETH_SPEED_NUM_25G:
3436 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3437 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3439 case ETH_SPEED_NUM_40G:
3440 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3441 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3443 case ETH_SPEED_NUM_50G:
3444 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3445 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3447 case ETH_SPEED_NUM_100G:
3448 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3449 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3451 case ETH_SPEED_NUM_200G:
3452 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3453 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3456 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3460 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3462 ret = hns3_cmd_send(hw, &desc, 1);
3464 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3470 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3472 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3473 struct hns3_pf *pf = &hns->pf;
3474 struct hns3_priv_buf *priv;
3475 uint32_t i, total_size;
3477 total_size = pf->pkt_buf_size;
3479 /* alloc tx buffer for all enabled tc */
3480 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3481 priv = &buf_alloc->priv_buf[i];
3483 if (hw->hw_tc_map & BIT(i)) {
3484 if (total_size < pf->tx_buf_size)
3487 priv->tx_buf_size = pf->tx_buf_size;
3489 priv->tx_buf_size = 0;
3491 total_size -= priv->tx_buf_size;
3498 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3500 /* TX buffer size is unit by 128 byte */
3501 #define HNS3_BUF_SIZE_UNIT_SHIFT 7
3502 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15)
3503 struct hns3_tx_buff_alloc_cmd *req;
3504 struct hns3_cmd_desc desc;
3509 req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3511 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3512 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3513 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3515 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3516 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3517 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3520 ret = hns3_cmd_send(hw, &desc, 1);
3522 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3528 hns3_get_tc_num(struct hns3_hw *hw)
3533 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3534 if (hw->hw_tc_map & BIT(i))
3540 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3542 struct hns3_priv_buf *priv;
3543 uint32_t rx_priv = 0;
3546 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3547 priv = &buf_alloc->priv_buf[i];
3549 rx_priv += priv->buf_size;
3555 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3557 uint32_t total_tx_size = 0;
3560 for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3561 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3563 return total_tx_size;
3566 /* Get the number of pfc enabled TCs, which have private buffer */
3568 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3570 struct hns3_priv_buf *priv;
3574 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3575 priv = &buf_alloc->priv_buf[i];
3576 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3583 /* Get the number of pfc disabled TCs, which have private buffer */
3585 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3586 struct hns3_pkt_buf_alloc *buf_alloc)
3588 struct hns3_priv_buf *priv;
3592 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3593 priv = &buf_alloc->priv_buf[i];
3594 if (hw->hw_tc_map & BIT(i) &&
3595 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3603 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3606 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3607 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3608 struct hns3_pf *pf = &hns->pf;
3609 uint32_t shared_buf, aligned_mps;
3614 tc_num = hns3_get_tc_num(hw);
3615 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3617 if (hns3_dev_dcb_supported(hw))
3618 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3621 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3624 shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3625 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3626 HNS3_BUF_SIZE_UNIT);
3628 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3629 if (rx_all < rx_priv + shared_std)
3632 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3633 buf_alloc->s_buf.buf_size = shared_buf;
3634 if (hns3_dev_dcb_supported(hw)) {
3635 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3636 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3637 - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3638 HNS3_BUF_SIZE_UNIT);
3640 buf_alloc->s_buf.self.high =
3641 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3642 buf_alloc->s_buf.self.low = aligned_mps;
3645 if (hns3_dev_dcb_supported(hw)) {
3646 hi_thrd = shared_buf - pf->dv_buf_size;
3648 if (tc_num <= NEED_RESERVE_TC_NUM)
3649 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3653 hi_thrd = hi_thrd / tc_num;
3655 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3656 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3657 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3659 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3660 lo_thrd = aligned_mps;
3663 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3664 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3665 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3672 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3673 struct hns3_pkt_buf_alloc *buf_alloc)
3675 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3676 struct hns3_pf *pf = &hns->pf;
3677 struct hns3_priv_buf *priv;
3678 uint32_t aligned_mps;
3682 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3683 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3685 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3686 priv = &buf_alloc->priv_buf[i];
3693 if (!(hw->hw_tc_map & BIT(i)))
3697 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3698 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3699 priv->wl.high = roundup(priv->wl.low + aligned_mps,
3700 HNS3_BUF_SIZE_UNIT);
3703 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3707 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3710 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3714 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3715 struct hns3_pkt_buf_alloc *buf_alloc)
3717 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3718 struct hns3_pf *pf = &hns->pf;
3719 struct hns3_priv_buf *priv;
3720 int no_pfc_priv_num;
3725 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3726 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3728 /* let the last to be cleared first */
3729 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3730 priv = &buf_alloc->priv_buf[i];
3731 mask = BIT((uint8_t)i);
3733 if (hw->hw_tc_map & mask &&
3734 !(hw->dcb_info.hw_pfc_map & mask)) {
3735 /* Clear the no pfc TC private buffer */
3743 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3744 no_pfc_priv_num == 0)
3748 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3752 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3753 struct hns3_pkt_buf_alloc *buf_alloc)
3755 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3756 struct hns3_pf *pf = &hns->pf;
3757 struct hns3_priv_buf *priv;
3763 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3764 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3766 /* let the last to be cleared first */
3767 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3768 priv = &buf_alloc->priv_buf[i];
3769 mask = BIT((uint8_t)i);
3770 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3771 /* Reduce the number of pfc TC with private buffer */
3778 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3783 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3787 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3788 struct hns3_pkt_buf_alloc *buf_alloc)
3790 #define COMPENSATE_BUFFER 0x3C00
3791 #define COMPENSATE_HALF_MPS_NUM 5
3792 #define PRIV_WL_GAP 0x1800
3793 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3794 struct hns3_pf *pf = &hns->pf;
3795 uint32_t tc_num = hns3_get_tc_num(hw);
3796 uint32_t half_mps = pf->mps >> 1;
3797 struct hns3_priv_buf *priv;
3798 uint32_t min_rx_priv;
3802 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3804 rx_priv = rx_priv / tc_num;
3806 if (tc_num <= NEED_RESERVE_TC_NUM)
3807 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3810 * Minimum value of private buffer in rx direction (min_rx_priv) is
3811 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3812 * buffer if rx_priv is greater than min_rx_priv.
3814 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3815 COMPENSATE_HALF_MPS_NUM * half_mps;
3816 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3817 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3819 if (rx_priv < min_rx_priv)
3822 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3823 priv = &buf_alloc->priv_buf[i];
3829 if (!(hw->hw_tc_map & BIT(i)))
3833 priv->buf_size = rx_priv;
3834 priv->wl.high = rx_priv - pf->dv_buf_size;
3835 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3838 buf_alloc->s_buf.buf_size = 0;
3844 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3845 * @hw: pointer to struct hns3_hw
3846 * @buf_alloc: pointer to buffer calculation data
3847 * @return: 0: calculate sucessful, negative: fail
3850 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3852 /* When DCB is not supported, rx private buffer is not allocated. */
3853 if (!hns3_dev_dcb_supported(hw)) {
3854 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3855 struct hns3_pf *pf = &hns->pf;
3856 uint32_t rx_all = pf->pkt_buf_size;
3858 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3859 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3866 * Try to allocate privated packet buffer for all TCs without share
3869 if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3873 * Try to allocate privated packet buffer for all TCs with share
3876 if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3880 * For different application scenes, the enabled port number, TC number
3881 * and no_drop TC number are different. In order to obtain the better
3882 * performance, software could allocate the buffer size and configure
3883 * the waterline by tring to decrease the private buffer size according
3884 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3887 if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3890 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3893 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3900 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3902 struct hns3_rx_priv_buff_cmd *req;
3903 struct hns3_cmd_desc desc;
3908 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3909 req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3911 /* Alloc private buffer TCs */
3912 for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3913 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3916 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3917 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3920 buf_size = buf_alloc->s_buf.buf_size;
3921 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3922 (1 << HNS3_TC0_PRI_BUF_EN_B));
3924 ret = hns3_cmd_send(hw, &desc, 1);
3926 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3932 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3934 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3935 struct hns3_rx_priv_wl_buf *req;
3936 struct hns3_priv_buf *priv;
3937 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3941 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3942 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3944 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3946 /* The first descriptor set the NEXT bit to 1 */
3948 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3950 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3952 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3953 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3955 priv = &buf_alloc->priv_buf[idx];
3956 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3958 req->tc_wl[j].high |=
3959 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3960 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3962 req->tc_wl[j].low |=
3963 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3967 /* Send 2 descriptor at one time */
3968 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3970 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3976 hns3_common_thrd_config(struct hns3_hw *hw,
3977 struct hns3_pkt_buf_alloc *buf_alloc)
3979 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3980 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3981 struct hns3_rx_com_thrd *req;
3982 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3983 struct hns3_tc_thrd *tc;
3988 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3989 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3991 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3993 /* The first descriptor set the NEXT bit to 1 */
3995 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3997 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3999 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4000 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4001 tc = &s_buf->tc_thrd[tc_idx];
4003 req->com_thrd[j].high =
4004 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4005 req->com_thrd[j].high |=
4006 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4007 req->com_thrd[j].low =
4008 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4009 req->com_thrd[j].low |=
4010 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4014 /* Send 2 descriptors at one time */
4015 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4017 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4023 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4025 struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4026 struct hns3_rx_com_wl *req;
4027 struct hns3_cmd_desc desc;
4030 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4032 req = (struct hns3_rx_com_wl *)desc.data;
4033 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4034 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4036 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4037 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4039 ret = hns3_cmd_send(hw, &desc, 1);
4041 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4047 hns3_buffer_alloc(struct hns3_hw *hw)
4049 struct hns3_pkt_buf_alloc pkt_buf;
4052 memset(&pkt_buf, 0, sizeof(pkt_buf));
4053 ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4056 "could not calc tx buffer size for all TCs %d",
4061 ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4063 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4067 ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4070 "could not calc rx priv buffer size for all TCs %d",
4075 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4077 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4081 if (hns3_dev_dcb_supported(hw)) {
4082 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4085 "could not configure rx private waterline %d",
4090 ret = hns3_common_thrd_config(hw, &pkt_buf);
4093 "could not configure common threshold %d",
4099 ret = hns3_common_wl_config(hw, &pkt_buf);
4101 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4108 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4110 struct hns3_firmware_compat_cmd *req;
4111 struct hns3_cmd_desc desc;
4112 uint32_t compat = 0;
4114 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4115 req = (struct hns3_firmware_compat_cmd *)desc.data;
4118 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4119 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4120 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4121 hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4124 req->compat = rte_cpu_to_le_32(compat);
4126 return hns3_cmd_send(hw, &desc, 1);
4130 hns3_mac_init(struct hns3_hw *hw)
4132 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4133 struct hns3_mac *mac = &hw->mac;
4134 struct hns3_pf *pf = &hns->pf;
4137 pf->support_sfp_query = true;
4138 mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4139 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4141 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4145 mac->link_status = ETH_LINK_DOWN;
4147 return hns3_config_mtu(hw, pf->mps);
4151 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4153 #define HNS3_ETHERTYPE_SUCCESS_ADD 0
4154 #define HNS3_ETHERTYPE_ALREADY_ADD 1
4155 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2
4156 #define HNS3_ETHERTYPE_KEY_CONFLICT 3
4161 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4166 switch (resp_code) {
4167 case HNS3_ETHERTYPE_SUCCESS_ADD:
4168 case HNS3_ETHERTYPE_ALREADY_ADD:
4171 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4173 "add mac ethertype failed for manager table overflow.");
4174 return_status = -EIO;
4176 case HNS3_ETHERTYPE_KEY_CONFLICT:
4177 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4178 return_status = -EIO;
4182 "add mac ethertype failed for undefined, code=%u.",
4184 return_status = -EIO;
4188 return return_status;
4192 hns3_add_mgr_tbl(struct hns3_hw *hw,
4193 const struct hns3_mac_mgr_tbl_entry_cmd *req)
4195 struct hns3_cmd_desc desc;
4200 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4201 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4203 ret = hns3_cmd_send(hw, &desc, 1);
4206 "add mac ethertype failed for cmd_send, ret =%d.",
4211 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4212 retval = rte_le_to_cpu_16(desc.retval);
4214 return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4218 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4219 int *table_item_num)
4221 struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4224 * In current version, we add one item in management table as below:
4225 * 0x0180C200000E -- LLDP MC address
4228 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4229 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4230 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4231 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4232 tbl->i_port_bitmap = 0x1;
4233 *table_item_num = 1;
4237 hns3_init_mgr_tbl(struct hns3_hw *hw)
4239 #define HNS_MAC_MGR_TBL_MAX_SIZE 16
4240 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4245 memset(mgr_table, 0, sizeof(mgr_table));
4246 hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4247 for (i = 0; i < table_item_num; i++) {
4248 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4250 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4260 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4261 bool en_mc, bool en_bc, int vport_id)
4266 memset(param, 0, sizeof(struct hns3_promisc_param));
4268 param->enable = HNS3_PROMISC_EN_UC;
4270 param->enable |= HNS3_PROMISC_EN_MC;
4272 param->enable |= HNS3_PROMISC_EN_BC;
4273 param->vf_id = vport_id;
4277 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4279 struct hns3_promisc_cfg_cmd *req;
4280 struct hns3_cmd_desc desc;
4283 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4285 req = (struct hns3_promisc_cfg_cmd *)desc.data;
4286 req->vf_id = param->vf_id;
4287 req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4288 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4290 ret = hns3_cmd_send(hw, &desc, 1);
4292 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4298 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4300 struct hns3_promisc_param param;
4301 bool en_bc_pmc = true;
4305 * In current version VF is not supported when PF is driven by DPDK
4306 * driver, just need to configure parameters for PF vport.
4308 vf_id = HNS3_PF_FUNC_ID;
4310 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4311 return hns3_cmd_set_promisc_mode(hw, ¶m);
4315 hns3_promisc_init(struct hns3_hw *hw)
4317 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4318 struct hns3_pf *pf = &hns->pf;
4319 struct hns3_promisc_param param;
4323 ret = hns3_set_promisc_mode(hw, false, false);
4325 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4330 * In current version VFs are not supported when PF is driven by DPDK
4331 * driver. After PF has been taken over by DPDK, the original VF will
4332 * be invalid. So, there is a possibility of entry residues. It should
4333 * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4336 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4337 hns3_promisc_param_init(¶m, false, false, false, func_id);
4338 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4340 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4341 " ret = %d", func_id, ret);
4350 hns3_promisc_uninit(struct hns3_hw *hw)
4352 struct hns3_promisc_param param;
4356 func_id = HNS3_PF_FUNC_ID;
4359 * In current version VFs are not supported when PF is driven by
4360 * DPDK driver, and VFs' promisc mode status has been cleared during
4361 * init and their status will not change. So just clear PF's promisc
4362 * mode status during uninit.
4364 hns3_promisc_param_init(¶m, false, false, false, func_id);
4365 ret = hns3_cmd_set_promisc_mode(hw, ¶m);
4367 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4368 " uninit, ret = %d", ret);
4372 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4374 bool allmulti = dev->data->all_multicast ? true : false;
4375 struct hns3_adapter *hns = dev->data->dev_private;
4376 struct hns3_hw *hw = &hns->hw;
4381 rte_spinlock_lock(&hw->lock);
4382 ret = hns3_set_promisc_mode(hw, true, true);
4384 rte_spinlock_unlock(&hw->lock);
4385 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4391 * When promiscuous mode was enabled, disable the vlan filter to let
4392 * all packets coming in in the receiving direction.
4394 offloads = dev->data->dev_conf.rxmode.offloads;
4395 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4396 ret = hns3_enable_vlan_filter(hns, false);
4398 hns3_err(hw, "failed to enable promiscuous mode due to "
4399 "failure to disable vlan filter, ret = %d",
4401 err = hns3_set_promisc_mode(hw, false, allmulti);
4403 hns3_err(hw, "failed to restore promiscuous "
4404 "status after disable vlan filter "
4405 "failed during enabling promiscuous "
4406 "mode, ret = %d", ret);
4410 rte_spinlock_unlock(&hw->lock);
4416 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4418 bool allmulti = dev->data->all_multicast ? true : false;
4419 struct hns3_adapter *hns = dev->data->dev_private;
4420 struct hns3_hw *hw = &hns->hw;
4425 /* If now in all_multicast mode, must remain in all_multicast mode. */
4426 rte_spinlock_lock(&hw->lock);
4427 ret = hns3_set_promisc_mode(hw, false, allmulti);
4429 rte_spinlock_unlock(&hw->lock);
4430 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4434 /* when promiscuous mode was disabled, restore the vlan filter status */
4435 offloads = dev->data->dev_conf.rxmode.offloads;
4436 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4437 ret = hns3_enable_vlan_filter(hns, true);
4439 hns3_err(hw, "failed to disable promiscuous mode due to"
4440 " failure to restore vlan filter, ret = %d",
4442 err = hns3_set_promisc_mode(hw, true, true);
4444 hns3_err(hw, "failed to restore promiscuous "
4445 "status after enabling vlan filter "
4446 "failed during disabling promiscuous "
4447 "mode, ret = %d", ret);
4450 rte_spinlock_unlock(&hw->lock);
4456 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4458 struct hns3_adapter *hns = dev->data->dev_private;
4459 struct hns3_hw *hw = &hns->hw;
4462 if (dev->data->promiscuous)
4465 rte_spinlock_lock(&hw->lock);
4466 ret = hns3_set_promisc_mode(hw, false, true);
4467 rte_spinlock_unlock(&hw->lock);
4469 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4476 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4478 struct hns3_adapter *hns = dev->data->dev_private;
4479 struct hns3_hw *hw = &hns->hw;
4482 /* If now in promiscuous mode, must remain in all_multicast mode. */
4483 if (dev->data->promiscuous)
4486 rte_spinlock_lock(&hw->lock);
4487 ret = hns3_set_promisc_mode(hw, false, false);
4488 rte_spinlock_unlock(&hw->lock);
4490 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4497 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4499 struct hns3_hw *hw = &hns->hw;
4500 bool allmulti = hw->data->all_multicast ? true : false;
4503 if (hw->data->promiscuous) {
4504 ret = hns3_set_promisc_mode(hw, true, true);
4506 hns3_err(hw, "failed to restore promiscuous mode, "
4511 ret = hns3_set_promisc_mode(hw, false, allmulti);
4513 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4519 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4521 struct hns3_sfp_speed_cmd *resp;
4522 struct hns3_cmd_desc desc;
4525 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4526 resp = (struct hns3_sfp_speed_cmd *)desc.data;
4527 ret = hns3_cmd_send(hw, &desc, 1);
4528 if (ret == -EOPNOTSUPP) {
4529 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4532 hns3_err(hw, "get sfp speed failed %d", ret);
4536 *speed = resp->sfp_speed;
4542 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4544 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4545 duplex = ETH_LINK_FULL_DUPLEX;
4551 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4553 struct hns3_mac *mac = &hw->mac;
4556 duplex = hns3_check_speed_dup(duplex, speed);
4557 if (mac->link_speed == speed && mac->link_duplex == duplex)
4560 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4564 ret = hns3_port_shaper_update(hw, speed);
4568 mac->link_speed = speed;
4569 mac->link_duplex = duplex;
4575 hns3_update_fiber_link_info(struct hns3_hw *hw)
4577 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4581 /* If IMP do not support get SFP/qSFP speed, return directly */
4582 if (!pf->support_sfp_query)
4585 ret = hns3_get_sfp_speed(hw, &speed);
4586 if (ret == -EOPNOTSUPP) {
4587 pf->support_sfp_query = false;
4592 if (speed == ETH_SPEED_NUM_NONE)
4593 return 0; /* do nothing if no SFP */
4595 /* Config full duplex for SFP */
4596 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4600 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4602 struct hns3_phy_params_bd0_cmd *req;
4604 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4605 mac->link_speed = rte_le_to_cpu_32(req->speed);
4606 mac->link_duplex = hns3_get_bit(req->duplex,
4607 HNS3_PHY_DUPLEX_CFG_B);
4608 mac->link_autoneg = hns3_get_bit(req->autoneg,
4609 HNS3_PHY_AUTONEG_CFG_B);
4610 mac->supported_capa = rte_le_to_cpu_32(req->supported);
4611 mac->advertising = rte_le_to_cpu_32(req->advertising);
4612 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4613 mac->support_autoneg = !!(mac->supported_capa &
4614 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4618 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4620 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4624 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4625 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4627 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4629 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4631 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4633 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4637 hns3_parse_phy_params(desc, mac);
4643 hns3_update_phy_link_info(struct hns3_hw *hw)
4645 struct hns3_mac *mac = &hw->mac;
4646 struct hns3_mac mac_info;
4649 memset(&mac_info, 0, sizeof(struct hns3_mac));
4650 ret = hns3_get_phy_params(hw, &mac_info);
4654 if (mac_info.link_speed != mac->link_speed) {
4655 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4660 mac->link_speed = mac_info.link_speed;
4661 mac->link_duplex = mac_info.link_duplex;
4662 mac->link_autoneg = mac_info.link_autoneg;
4663 mac->supported_capa = mac_info.supported_capa;
4664 mac->advertising = mac_info.advertising;
4665 mac->lp_advertising = mac_info.lp_advertising;
4666 mac->support_autoneg = mac_info.support_autoneg;
4672 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4674 struct hns3_adapter *hns = eth_dev->data->dev_private;
4675 struct hns3_hw *hw = &hns->hw;
4678 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4679 ret = hns3_update_phy_link_info(hw);
4680 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4681 ret = hns3_update_fiber_link_info(hw);
4687 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4689 struct hns3_config_mac_mode_cmd *req;
4690 struct hns3_cmd_desc desc;
4691 uint32_t loop_en = 0;
4695 req = (struct hns3_config_mac_mode_cmd *)desc.data;
4697 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4700 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4701 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4702 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4703 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4704 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4705 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4706 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4707 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4708 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4709 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4712 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4713 * when receiving frames. Otherwise, CRC will be stripped.
4715 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4716 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4718 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4719 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4720 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4721 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4722 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4724 ret = hns3_cmd_send(hw, &desc, 1);
4726 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4732 hns3_get_mac_link_status(struct hns3_hw *hw)
4734 struct hns3_link_status_cmd *req;
4735 struct hns3_cmd_desc desc;
4739 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4740 ret = hns3_cmd_send(hw, &desc, 1);
4742 hns3_err(hw, "get link status cmd failed %d", ret);
4743 return ETH_LINK_DOWN;
4746 req = (struct hns3_link_status_cmd *)desc.data;
4747 link_status = req->status & HNS3_LINK_STATUS_UP_M;
4749 return !!link_status;
4753 hns3_update_link_status(struct hns3_hw *hw)
4757 state = hns3_get_mac_link_status(hw);
4758 if (state != hw->mac.link_status) {
4759 hw->mac.link_status = state;
4760 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4761 hns3_config_mac_tnl_int(hw,
4762 state == ETH_LINK_UP ? true : false);
4770 * Current, the PF driver get link status by two ways:
4771 * 1) Periodic polling in the intr thread context, driver call
4772 * hns3_update_link_status to update link status.
4773 * 2) Firmware report async interrupt, driver process the event in the intr
4774 * thread context, and call hns3_update_link_status to update link status.
4776 * If detect link status changed, driver need report LSE. One method is add the
4777 * report LSE logic in hns3_update_link_status.
4779 * But the PF driver ops(link_update) also call hns3_update_link_status to
4780 * update link status.
4781 * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4782 * bonding application.
4784 * So add the one new API which used only in intr thread context.
4787 hns3_update_link_status_and_event(struct hns3_hw *hw)
4789 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4790 bool changed = hns3_update_link_status(hw);
4792 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4796 hns3_service_handler(void *param)
4798 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4799 struct hns3_adapter *hns = eth_dev->data->dev_private;
4800 struct hns3_hw *hw = &hns->hw;
4802 if (!hns3_is_reset_pending(hns)) {
4803 hns3_update_link_status_and_event(hw);
4804 hns3_update_link_info(eth_dev);
4806 hns3_warn(hw, "Cancel the query when reset is pending");
4809 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4813 hns3_init_hardware(struct hns3_adapter *hns)
4815 struct hns3_hw *hw = &hns->hw;
4818 ret = hns3_map_tqp(hw);
4820 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4824 ret = hns3_init_umv_space(hw);
4826 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4830 ret = hns3_mac_init(hw);
4832 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4836 ret = hns3_init_mgr_tbl(hw);
4838 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4842 ret = hns3_promisc_init(hw);
4844 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4849 ret = hns3_init_vlan_config(hns);
4851 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4855 ret = hns3_dcb_init(hw);
4857 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4861 ret = hns3_init_fd_config(hns);
4863 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4867 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4869 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4873 ret = hns3_config_gro(hw, false);
4875 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4880 * In the initialization clearing the all hardware mapping relationship
4881 * configurations between queues and interrupt vectors is needed, so
4882 * some error caused by the residual configurations, such as the
4883 * unexpected interrupt, can be avoid.
4885 ret = hns3_init_ring_with_vector(hw);
4887 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4892 * Requiring firmware to enable some features, driver can
4893 * still work without it.
4895 ret = hns3_firmware_compat_config(hw, true);
4897 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4898 "supported, ret = %d.", ret);
4903 hns3_uninit_umv_space(hw);
4908 hns3_clear_hw(struct hns3_hw *hw)
4910 struct hns3_cmd_desc desc;
4913 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4915 ret = hns3_cmd_send(hw, &desc, 1);
4916 if (ret && ret != -EOPNOTSUPP)
4923 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4928 * The new firmware support report more hardware error types by
4929 * msix mode. These errors are defined as RAS errors in hardware
4930 * and belong to a different type from the MSI-x errors processed
4931 * by the network driver.
4933 * Network driver should open the new error report on initialition
4935 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4936 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4937 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4941 hns3_init_pf(struct rte_eth_dev *eth_dev)
4943 struct rte_device *dev = eth_dev->device;
4944 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4945 struct hns3_adapter *hns = eth_dev->data->dev_private;
4946 struct hns3_hw *hw = &hns->hw;
4949 PMD_INIT_FUNC_TRACE();
4951 /* Get hardware io base address from pcie BAR2 IO space */
4952 hw->io_base = pci_dev->mem_resource[2].addr;
4954 /* Firmware command queue initialize */
4955 ret = hns3_cmd_init_queue(hw);
4957 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4958 goto err_cmd_init_queue;
4961 hns3_clear_all_event_cause(hw);
4963 /* Firmware command initialize */
4964 ret = hns3_cmd_init(hw);
4966 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4971 * To ensure that the hardware environment is clean during
4972 * initialization, the driver actively clear the hardware environment
4973 * during initialization, including PF and corresponding VFs' vlan, mac,
4974 * flow table configurations, etc.
4976 ret = hns3_clear_hw(hw);
4978 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4982 /* Hardware statistics of imissed registers cleared. */
4983 ret = hns3_update_imissed_stats(hw, true);
4985 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4989 hns3_config_all_msix_error(hw, true);
4991 ret = rte_intr_callback_register(&pci_dev->intr_handle,
4992 hns3_interrupt_handler,
4995 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4996 goto err_intr_callback_register;
4999 ret = hns3_ptp_init(hw);
5001 goto err_get_config;
5003 /* Enable interrupt */
5004 rte_intr_enable(&pci_dev->intr_handle);
5005 hns3_pf_enable_irq0(hw);
5007 /* Get configuration */
5008 ret = hns3_get_configuration(hw);
5010 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5011 goto err_get_config;
5014 ret = hns3_tqp_stats_init(hw);
5016 goto err_get_config;
5018 ret = hns3_init_hardware(hns);
5020 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5024 /* Initialize flow director filter list & hash */
5025 ret = hns3_fdir_filter_init(hns);
5027 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5031 hns3_rss_set_default_args(hw);
5033 ret = hns3_enable_hw_error_intr(hns, true);
5035 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5037 goto err_enable_intr;
5040 hns3_tm_conf_init(eth_dev);
5045 hns3_fdir_filter_uninit(hns);
5047 (void)hns3_firmware_compat_config(hw, false);
5048 hns3_uninit_umv_space(hw);
5050 hns3_tqp_stats_uninit(hw);
5052 hns3_pf_disable_irq0(hw);
5053 rte_intr_disable(&pci_dev->intr_handle);
5054 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5056 err_intr_callback_register:
5058 hns3_cmd_uninit(hw);
5059 hns3_cmd_destroy_queue(hw);
5067 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5069 struct hns3_adapter *hns = eth_dev->data->dev_private;
5070 struct rte_device *dev = eth_dev->device;
5071 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5072 struct hns3_hw *hw = &hns->hw;
5074 PMD_INIT_FUNC_TRACE();
5076 hns3_tm_conf_uninit(eth_dev);
5077 hns3_enable_hw_error_intr(hns, false);
5078 hns3_rss_uninit(hns);
5079 (void)hns3_config_gro(hw, false);
5080 hns3_promisc_uninit(hw);
5081 hns3_fdir_filter_uninit(hns);
5082 (void)hns3_firmware_compat_config(hw, false);
5083 hns3_uninit_umv_space(hw);
5084 hns3_tqp_stats_uninit(hw);
5085 hns3_config_mac_tnl_int(hw, false);
5086 hns3_pf_disable_irq0(hw);
5087 rte_intr_disable(&pci_dev->intr_handle);
5088 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5090 hns3_config_all_msix_error(hw, false);
5091 hns3_cmd_uninit(hw);
5092 hns3_cmd_destroy_queue(hw);
5097 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5099 struct hns3_hw *hw = &hns->hw;
5102 ret = hns3_dcb_cfg_update(hns);
5107 * The hns3_dcb_cfg_update may configure TM module, so
5108 * hns3_tm_conf_update must called later.
5110 ret = hns3_tm_conf_update(hw);
5112 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5116 hns3_enable_rxd_adv_layout(hw);
5118 ret = hns3_init_queues(hns, reset_queue);
5120 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5124 ret = hns3_cfg_mac_mode(hw, true);
5126 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5127 goto err_config_mac_mode;
5131 err_config_mac_mode:
5132 hns3_dev_release_mbufs(hns);
5134 * Here is exception handling, hns3_reset_all_tqps will have the
5135 * corresponding error message if it is handled incorrectly, so it is
5136 * not necessary to check hns3_reset_all_tqps return value, here keep
5137 * ret as the error code causing the exception.
5139 (void)hns3_reset_all_tqps(hns);
5144 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5146 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5147 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5148 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5149 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5150 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5151 uint32_t intr_vector;
5156 * hns3 needs a separate interrupt to be used as event interrupt which
5157 * could not be shared with task queue pair, so KERNEL drivers need
5158 * support multiple interrupt vectors.
5160 if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5161 !rte_intr_cap_multiple(intr_handle))
5164 rte_intr_disable(intr_handle);
5165 intr_vector = hw->used_rx_queues;
5166 /* creates event fd for each intr vector when MSIX is used */
5167 if (rte_intr_efd_enable(intr_handle, intr_vector))
5170 if (intr_handle->intr_vec == NULL) {
5171 intr_handle->intr_vec =
5172 rte_zmalloc("intr_vec",
5173 hw->used_rx_queues * sizeof(int), 0);
5174 if (intr_handle->intr_vec == NULL) {
5175 hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5176 hw->used_rx_queues);
5178 goto alloc_intr_vec_error;
5182 if (rte_intr_allow_others(intr_handle)) {
5183 vec = RTE_INTR_VEC_RXTX_OFFSET;
5184 base = RTE_INTR_VEC_RXTX_OFFSET;
5187 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5188 ret = hns3_bind_ring_with_vector(hw, vec, true,
5189 HNS3_RING_TYPE_RX, q_id);
5191 goto bind_vector_error;
5192 intr_handle->intr_vec[q_id] = vec;
5194 * If there are not enough efds (e.g. not enough interrupt),
5195 * remaining queues will be bond to the last interrupt.
5197 if (vec < base + intr_handle->nb_efd - 1)
5200 rte_intr_enable(intr_handle);
5204 rte_free(intr_handle->intr_vec);
5205 intr_handle->intr_vec = NULL;
5206 alloc_intr_vec_error:
5207 rte_intr_efd_disable(intr_handle);
5212 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5214 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5215 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5216 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5220 if (dev->data->dev_conf.intr_conf.rxq == 0)
5223 if (rte_intr_dp_is_en(intr_handle)) {
5224 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5225 ret = hns3_bind_ring_with_vector(hw,
5226 intr_handle->intr_vec[q_id], true,
5227 HNS3_RING_TYPE_RX, q_id);
5237 hns3_restore_filter(struct rte_eth_dev *dev)
5239 hns3_restore_rss_filter(dev);
5243 hns3_dev_start(struct rte_eth_dev *dev)
5245 struct hns3_adapter *hns = dev->data->dev_private;
5246 struct hns3_hw *hw = &hns->hw;
5249 PMD_INIT_FUNC_TRACE();
5250 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5253 rte_spinlock_lock(&hw->lock);
5254 hw->adapter_state = HNS3_NIC_STARTING;
5256 ret = hns3_do_start(hns, true);
5258 hw->adapter_state = HNS3_NIC_CONFIGURED;
5259 rte_spinlock_unlock(&hw->lock);
5262 ret = hns3_map_rx_interrupt(dev);
5264 goto map_rx_inter_err;
5267 * There are three register used to control the status of a TQP
5268 * (contains a pair of Tx queue and Rx queue) in the new version network
5269 * engine. One is used to control the enabling of Tx queue, the other is
5270 * used to control the enabling of Rx queue, and the last is the master
5271 * switch used to control the enabling of the tqp. The Tx register and
5272 * TQP register must be enabled at the same time to enable a Tx queue.
5273 * The same applies to the Rx queue. For the older network engine, this
5274 * function only refresh the enabled flag, and it is used to update the
5275 * status of queue in the dpdk framework.
5277 ret = hns3_start_all_txqs(dev);
5279 goto map_rx_inter_err;
5281 ret = hns3_start_all_rxqs(dev);
5283 goto start_all_rxqs_fail;
5285 hw->adapter_state = HNS3_NIC_STARTED;
5286 rte_spinlock_unlock(&hw->lock);
5288 hns3_rx_scattered_calc(dev);
5289 hns3_set_rxtx_function(dev);
5290 hns3_mp_req_start_rxtx(dev);
5291 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5293 hns3_restore_filter(dev);
5295 /* Enable interrupt of all rx queues before enabling queues */
5296 hns3_dev_all_rx_queue_intr_enable(hw, true);
5299 * After finished the initialization, enable tqps to receive/transmit
5300 * packets and refresh all queue status.
5302 hns3_start_tqps(hw);
5304 hns3_tm_dev_start_proc(hw);
5306 hns3_info(hw, "hns3 dev start successful!");
5310 start_all_rxqs_fail:
5311 hns3_stop_all_txqs(dev);
5313 (void)hns3_do_stop(hns);
5314 hw->adapter_state = HNS3_NIC_CONFIGURED;
5315 rte_spinlock_unlock(&hw->lock);
5321 hns3_do_stop(struct hns3_adapter *hns)
5323 struct hns3_hw *hw = &hns->hw;
5327 * The "hns3_do_stop" function will also be called by .stop_service to
5328 * prepare reset. At the time of global or IMP reset, the command cannot
5329 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5330 * accessed during the reset process. So the mbuf can not be released
5331 * during reset and is required to be released after the reset is
5334 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0)
5335 hns3_dev_release_mbufs(hns);
5337 ret = hns3_cfg_mac_mode(hw, false);
5340 hw->mac.link_status = ETH_LINK_DOWN;
5342 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5343 hns3_configure_all_mac_addr(hns, true);
5344 ret = hns3_reset_all_tqps(hns);
5346 hns3_err(hw, "failed to reset all queues ret = %d.",
5351 hw->mac.default_addr_setted = false;
5356 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5358 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5359 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5360 struct hns3_adapter *hns = dev->data->dev_private;
5361 struct hns3_hw *hw = &hns->hw;
5362 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5363 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5366 if (dev->data->dev_conf.intr_conf.rxq == 0)
5369 /* unmap the ring with vector */
5370 if (rte_intr_allow_others(intr_handle)) {
5371 vec = RTE_INTR_VEC_RXTX_OFFSET;
5372 base = RTE_INTR_VEC_RXTX_OFFSET;
5374 if (rte_intr_dp_is_en(intr_handle)) {
5375 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5376 (void)hns3_bind_ring_with_vector(hw, vec, false,
5379 if (vec < base + intr_handle->nb_efd - 1)
5383 /* Clean datapath event and queue/vec mapping */
5384 rte_intr_efd_disable(intr_handle);
5385 if (intr_handle->intr_vec) {
5386 rte_free(intr_handle->intr_vec);
5387 intr_handle->intr_vec = NULL;
5392 hns3_dev_stop(struct rte_eth_dev *dev)
5394 struct hns3_adapter *hns = dev->data->dev_private;
5395 struct hns3_hw *hw = &hns->hw;
5397 PMD_INIT_FUNC_TRACE();
5398 dev->data->dev_started = 0;
5400 hw->adapter_state = HNS3_NIC_STOPPING;
5401 hns3_set_rxtx_function(dev);
5403 /* Disable datapath on secondary process. */
5404 hns3_mp_req_stop_rxtx(dev);
5405 /* Prevent crashes when queues are still in use. */
5406 rte_delay_ms(hw->tqps_num);
5408 rte_spinlock_lock(&hw->lock);
5409 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5410 hns3_tm_dev_stop_proc(hw);
5411 hns3_config_mac_tnl_int(hw, false);
5414 hns3_unmap_rx_interrupt(dev);
5415 hw->adapter_state = HNS3_NIC_CONFIGURED;
5417 hns3_rx_scattered_reset(dev);
5418 rte_eal_alarm_cancel(hns3_service_handler, dev);
5419 rte_spinlock_unlock(&hw->lock);
5425 hns3_dev_close(struct rte_eth_dev *eth_dev)
5427 struct hns3_adapter *hns = eth_dev->data->dev_private;
5428 struct hns3_hw *hw = &hns->hw;
5431 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5432 rte_free(eth_dev->process_private);
5433 eth_dev->process_private = NULL;
5437 if (hw->adapter_state == HNS3_NIC_STARTED)
5438 ret = hns3_dev_stop(eth_dev);
5440 hw->adapter_state = HNS3_NIC_CLOSING;
5441 hns3_reset_abort(hns);
5442 hw->adapter_state = HNS3_NIC_CLOSED;
5444 hns3_configure_all_mc_mac_addr(hns, true);
5445 hns3_remove_all_vlan_table(hns);
5446 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5447 hns3_uninit_pf(eth_dev);
5448 hns3_free_all_queues(eth_dev);
5449 rte_free(hw->reset.wait_data);
5450 rte_free(eth_dev->process_private);
5451 eth_dev->process_private = NULL;
5452 hns3_mp_uninit_primary();
5453 hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5459 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5461 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5464 fc_conf->pause_time = pf->pause_time;
5466 /* return fc current mode */
5467 switch (hw->current_mode) {
5469 fc_conf->mode = RTE_FC_FULL;
5471 case HNS3_FC_TX_PAUSE:
5472 fc_conf->mode = RTE_FC_TX_PAUSE;
5474 case HNS3_FC_RX_PAUSE:
5475 fc_conf->mode = RTE_FC_RX_PAUSE;
5479 fc_conf->mode = RTE_FC_NONE;
5487 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5491 hw->requested_mode = HNS3_FC_NONE;
5493 case RTE_FC_RX_PAUSE:
5494 hw->requested_mode = HNS3_FC_RX_PAUSE;
5496 case RTE_FC_TX_PAUSE:
5497 hw->requested_mode = HNS3_FC_TX_PAUSE;
5500 hw->requested_mode = HNS3_FC_FULL;
5503 hw->requested_mode = HNS3_FC_NONE;
5504 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5505 "configured to RTE_FC_NONE", mode);
5511 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5513 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5514 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5517 if (fc_conf->high_water || fc_conf->low_water ||
5518 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5519 hns3_err(hw, "Unsupported flow control settings specified, "
5520 "high_water(%u), low_water(%u), send_xon(%u) and "
5521 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5522 fc_conf->high_water, fc_conf->low_water,
5523 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5526 if (fc_conf->autoneg) {
5527 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5530 if (!fc_conf->pause_time) {
5531 hns3_err(hw, "Invalid pause time %u setting.",
5532 fc_conf->pause_time);
5536 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5537 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5538 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5539 "current_fc_status = %d", hw->current_fc_status);
5543 hns3_get_fc_mode(hw, fc_conf->mode);
5544 if (hw->requested_mode == hw->current_mode &&
5545 pf->pause_time == fc_conf->pause_time)
5548 rte_spinlock_lock(&hw->lock);
5549 ret = hns3_fc_enable(dev, fc_conf);
5550 rte_spinlock_unlock(&hw->lock);
5556 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5557 struct rte_eth_pfc_conf *pfc_conf)
5559 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5560 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5564 if (!hns3_dev_dcb_supported(hw)) {
5565 hns3_err(hw, "This port does not support dcb configurations.");
5569 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5570 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5571 hns3_err(hw, "Unsupported flow control settings specified, "
5572 "high_water(%u), low_water(%u), send_xon(%u) and "
5573 "mac_ctrl_frame_fwd(%u) must be set to '0'",
5574 pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5575 pfc_conf->fc.send_xon,
5576 pfc_conf->fc.mac_ctrl_frame_fwd);
5579 if (pfc_conf->fc.autoneg) {
5580 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5583 if (pfc_conf->fc.pause_time == 0) {
5584 hns3_err(hw, "Invalid pause time %u setting.",
5585 pfc_conf->fc.pause_time);
5589 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5590 hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5591 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5592 "current_fc_status = %d", hw->current_fc_status);
5596 priority = pfc_conf->priority;
5597 hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5598 if (hw->dcb_info.pfc_en & BIT(priority) &&
5599 hw->requested_mode == hw->current_mode &&
5600 pfc_conf->fc.pause_time == pf->pause_time)
5603 rte_spinlock_lock(&hw->lock);
5604 ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5605 rte_spinlock_unlock(&hw->lock);
5611 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5613 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5615 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5618 rte_spinlock_lock(&hw->lock);
5619 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5620 dcb_info->nb_tcs = pf->local_max_tc;
5622 dcb_info->nb_tcs = 1;
5624 for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5625 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5626 for (i = 0; i < dcb_info->nb_tcs; i++)
5627 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5629 for (i = 0; i < hw->num_tc; i++) {
5630 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5631 dcb_info->tc_queue.tc_txq[0][i].base =
5632 hw->tc_queue[i].tqp_offset;
5633 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5634 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5635 hw->tc_queue[i].tqp_count;
5637 rte_spinlock_unlock(&hw->lock);
5643 hns3_reinit_dev(struct hns3_adapter *hns)
5645 struct hns3_hw *hw = &hns->hw;
5648 ret = hns3_cmd_init(hw);
5650 hns3_err(hw, "Failed to init cmd: %d", ret);
5654 ret = hns3_reset_all_tqps(hns);
5656 hns3_err(hw, "Failed to reset all queues: %d", ret);
5660 ret = hns3_init_hardware(hns);
5662 hns3_err(hw, "Failed to init hardware: %d", ret);
5666 ret = hns3_enable_hw_error_intr(hns, true);
5668 hns3_err(hw, "fail to enable hw error interrupts: %d",
5672 hns3_info(hw, "Reset done, driver initialization finished.");
5678 is_pf_reset_done(struct hns3_hw *hw)
5680 uint32_t val, reg, reg_bit;
5682 switch (hw->reset.level) {
5683 case HNS3_IMP_RESET:
5684 reg = HNS3_GLOBAL_RESET_REG;
5685 reg_bit = HNS3_IMP_RESET_BIT;
5687 case HNS3_GLOBAL_RESET:
5688 reg = HNS3_GLOBAL_RESET_REG;
5689 reg_bit = HNS3_GLOBAL_RESET_BIT;
5691 case HNS3_FUNC_RESET:
5692 reg = HNS3_FUN_RST_ING;
5693 reg_bit = HNS3_FUN_RST_ING_B;
5695 case HNS3_FLR_RESET:
5697 hns3_err(hw, "Wait for unsupported reset level: %d",
5701 val = hns3_read_dev(hw, reg);
5702 if (hns3_get_bit(val, reg_bit))
5709 hns3_is_reset_pending(struct hns3_adapter *hns)
5711 struct hns3_hw *hw = &hns->hw;
5712 enum hns3_reset_level reset;
5714 hns3_check_event_cause(hns, NULL);
5715 reset = hns3_get_reset_level(hns, &hw->reset.pending);
5716 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5717 hns3_warn(hw, "High level reset %d is pending", reset);
5720 reset = hns3_get_reset_level(hns, &hw->reset.request);
5721 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5722 hns3_warn(hw, "High level reset %d is request", reset);
5729 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5731 struct hns3_hw *hw = &hns->hw;
5732 struct hns3_wait_data *wait_data = hw->reset.wait_data;
5735 if (wait_data->result == HNS3_WAIT_SUCCESS)
5737 else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5738 gettimeofday(&tv, NULL);
5739 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5740 tv.tv_sec, tv.tv_usec);
5742 } else if (wait_data->result == HNS3_WAIT_REQUEST)
5745 wait_data->hns = hns;
5746 wait_data->check_completion = is_pf_reset_done;
5747 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5748 HNS3_RESET_WAIT_MS + get_timeofday_ms();
5749 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5750 wait_data->count = HNS3_RESET_WAIT_CNT;
5751 wait_data->result = HNS3_WAIT_REQUEST;
5752 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5757 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5759 struct hns3_cmd_desc desc;
5760 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5762 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5763 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5764 req->fun_reset_vfid = func_id;
5766 return hns3_cmd_send(hw, &desc, 1);
5770 hns3_imp_reset_cmd(struct hns3_hw *hw)
5772 struct hns3_cmd_desc desc;
5774 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5775 desc.data[0] = 0xeedd;
5777 return hns3_cmd_send(hw, &desc, 1);
5781 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5783 struct hns3_hw *hw = &hns->hw;
5787 gettimeofday(&tv, NULL);
5788 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5789 hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5790 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5791 tv.tv_sec, tv.tv_usec);
5795 switch (reset_level) {
5796 case HNS3_IMP_RESET:
5797 hns3_imp_reset_cmd(hw);
5798 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5799 tv.tv_sec, tv.tv_usec);
5801 case HNS3_GLOBAL_RESET:
5802 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5803 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5804 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5805 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5806 tv.tv_sec, tv.tv_usec);
5808 case HNS3_FUNC_RESET:
5809 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5810 tv.tv_sec, tv.tv_usec);
5811 /* schedule again to check later */
5812 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5813 hns3_schedule_reset(hns);
5816 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5819 hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5822 static enum hns3_reset_level
5823 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5825 struct hns3_hw *hw = &hns->hw;
5826 enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5828 /* Return the highest priority reset level amongst all */
5829 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5830 reset_level = HNS3_IMP_RESET;
5831 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5832 reset_level = HNS3_GLOBAL_RESET;
5833 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5834 reset_level = HNS3_FUNC_RESET;
5835 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5836 reset_level = HNS3_FLR_RESET;
5838 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5839 return HNS3_NONE_RESET;
5845 hns3_record_imp_error(struct hns3_adapter *hns)
5847 struct hns3_hw *hw = &hns->hw;
5850 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5851 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5852 hns3_warn(hw, "Detected IMP RD poison!");
5853 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5854 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5857 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5858 hns3_warn(hw, "Detected IMP CMDQ error!");
5859 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5860 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5865 hns3_prepare_reset(struct hns3_adapter *hns)
5867 struct hns3_hw *hw = &hns->hw;
5871 switch (hw->reset.level) {
5872 case HNS3_FUNC_RESET:
5873 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5878 * After performaning pf reset, it is not necessary to do the
5879 * mailbox handling or send any command to firmware, because
5880 * any mailbox handling or command to firmware is only valid
5881 * after hns3_cmd_init is called.
5883 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5884 hw->reset.stats.request_cnt++;
5886 case HNS3_IMP_RESET:
5887 hns3_record_imp_error(hns);
5888 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5889 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5890 BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5899 hns3_set_rst_done(struct hns3_hw *hw)
5901 struct hns3_pf_rst_done_cmd *req;
5902 struct hns3_cmd_desc desc;
5904 req = (struct hns3_pf_rst_done_cmd *)desc.data;
5905 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5906 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5907 return hns3_cmd_send(hw, &desc, 1);
5911 hns3_stop_service(struct hns3_adapter *hns)
5913 struct hns3_hw *hw = &hns->hw;
5914 struct rte_eth_dev *eth_dev;
5916 eth_dev = &rte_eth_devices[hw->data->port_id];
5917 if (hw->adapter_state == HNS3_NIC_STARTED) {
5918 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5919 hns3_update_link_status_and_event(hw);
5921 hw->mac.link_status = ETH_LINK_DOWN;
5923 hns3_set_rxtx_function(eth_dev);
5925 /* Disable datapath on secondary process. */
5926 hns3_mp_req_stop_rxtx(eth_dev);
5927 rte_delay_ms(hw->tqps_num);
5929 rte_spinlock_lock(&hw->lock);
5930 if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5931 hw->adapter_state == HNS3_NIC_STOPPING) {
5932 hns3_enable_all_queues(hw, false);
5934 hw->reset.mbuf_deferred_free = true;
5936 hw->reset.mbuf_deferred_free = false;
5939 * It is cumbersome for hardware to pick-and-choose entries for deletion
5940 * from table space. Hence, for function reset software intervention is
5941 * required to delete the entries
5943 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5944 hns3_configure_all_mc_mac_addr(hns, true);
5945 rte_spinlock_unlock(&hw->lock);
5951 hns3_start_service(struct hns3_adapter *hns)
5953 struct hns3_hw *hw = &hns->hw;
5954 struct rte_eth_dev *eth_dev;
5956 if (hw->reset.level == HNS3_IMP_RESET ||
5957 hw->reset.level == HNS3_GLOBAL_RESET)
5958 hns3_set_rst_done(hw);
5959 eth_dev = &rte_eth_devices[hw->data->port_id];
5960 hns3_set_rxtx_function(eth_dev);
5961 hns3_mp_req_start_rxtx(eth_dev);
5962 if (hw->adapter_state == HNS3_NIC_STARTED) {
5964 * This API parent function already hold the hns3_hw.lock, the
5965 * hns3_service_handler may report lse, in bonding application
5966 * it will call driver's ops which may acquire the hns3_hw.lock
5967 * again, thus lead to deadlock.
5968 * We defer calls hns3_service_handler to avoid the deadlock.
5970 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5971 hns3_service_handler, eth_dev);
5973 /* Enable interrupt of all rx queues before enabling queues */
5974 hns3_dev_all_rx_queue_intr_enable(hw, true);
5976 * Enable state of each rxq and txq will be recovered after
5977 * reset, so we need to restore them before enable all tqps;
5979 hns3_restore_tqp_enable_state(hw);
5981 * When finished the initialization, enable queues to receive
5982 * and transmit packets.
5984 hns3_enable_all_queues(hw, true);
5991 hns3_restore_conf(struct hns3_adapter *hns)
5993 struct hns3_hw *hw = &hns->hw;
5996 ret = hns3_configure_all_mac_addr(hns, false);
6000 ret = hns3_configure_all_mc_mac_addr(hns, false);
6004 ret = hns3_dev_promisc_restore(hns);
6008 ret = hns3_restore_vlan_table(hns);
6012 ret = hns3_restore_vlan_conf(hns);
6016 ret = hns3_restore_all_fdir_filter(hns);
6020 ret = hns3_restore_ptp(hns);
6024 ret = hns3_restore_rx_interrupt(hw);
6028 ret = hns3_restore_gro_conf(hw);
6032 ret = hns3_restore_fec(hw);
6036 if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6037 ret = hns3_do_start(hns, false);
6040 hns3_info(hw, "hns3 dev restart successful!");
6041 } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6042 hw->adapter_state = HNS3_NIC_CONFIGURED;
6046 hns3_configure_all_mc_mac_addr(hns, true);
6048 hns3_configure_all_mac_addr(hns, true);
6053 hns3_reset_service(void *param)
6055 struct hns3_adapter *hns = (struct hns3_adapter *)param;
6056 struct hns3_hw *hw = &hns->hw;
6057 enum hns3_reset_level reset_level;
6058 struct timeval tv_delta;
6059 struct timeval tv_start;
6065 * The interrupt is not triggered within the delay time.
6066 * The interrupt may have been lost. It is necessary to handle
6067 * the interrupt to recover from the error.
6069 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6070 SCHEDULE_DEFERRED) {
6071 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6073 hns3_err(hw, "Handling interrupts in delayed tasks");
6074 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6075 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6076 if (reset_level == HNS3_NONE_RESET) {
6077 hns3_err(hw, "No reset level is set, try IMP reset");
6078 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6081 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6084 * Check if there is any ongoing reset in the hardware. This status can
6085 * be checked from reset_pending. If there is then, we need to wait for
6086 * hardware to complete reset.
6087 * a. If we are able to figure out in reasonable time that hardware
6088 * has fully resetted then, we can proceed with driver, client
6090 * b. else, we can come back later to check this status so re-sched
6093 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6094 if (reset_level != HNS3_NONE_RESET) {
6095 gettimeofday(&tv_start, NULL);
6096 ret = hns3_reset_process(hns, reset_level);
6097 gettimeofday(&tv, NULL);
6098 timersub(&tv, &tv_start, &tv_delta);
6099 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6100 tv_delta.tv_usec / USEC_PER_MSEC;
6101 if (msec > HNS3_RESET_PROCESS_MS)
6102 hns3_err(hw, "%d handle long time delta %" PRIx64
6103 " ms time=%ld.%.6ld",
6104 hw->reset.level, msec,
6105 tv.tv_sec, tv.tv_usec);
6110 /* Check if we got any *new* reset requests to be honored */
6111 reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6112 if (reset_level != HNS3_NONE_RESET)
6113 hns3_msix_process(hns, reset_level);
6117 hns3_get_speed_capa_num(uint16_t device_id)
6121 switch (device_id) {
6122 case HNS3_DEV_ID_25GE:
6123 case HNS3_DEV_ID_25GE_RDMA:
6126 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6127 case HNS3_DEV_ID_200G_RDMA:
6139 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6142 switch (device_id) {
6143 case HNS3_DEV_ID_25GE:
6145 case HNS3_DEV_ID_25GE_RDMA:
6146 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6147 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6149 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6150 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6151 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6153 case HNS3_DEV_ID_100G_RDMA_MACSEC:
6154 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6155 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6157 case HNS3_DEV_ID_200G_RDMA:
6158 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6159 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6169 hns3_fec_get_capability(struct rte_eth_dev *dev,
6170 struct rte_eth_fec_capa *speed_fec_capa,
6173 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6174 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6175 uint16_t device_id = pci_dev->id.device_id;
6176 unsigned int capa_num;
6179 capa_num = hns3_get_speed_capa_num(device_id);
6180 if (capa_num == 0) {
6181 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6186 if (speed_fec_capa == NULL || num < capa_num)
6189 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6197 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6199 struct hns3_config_fec_cmd *req;
6200 struct hns3_cmd_desc desc;
6204 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6205 * in device of link speed
6208 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6213 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6214 req = (struct hns3_config_fec_cmd *)desc.data;
6215 ret = hns3_cmd_send(hw, &desc, 1);
6217 hns3_err(hw, "get current fec auto state failed, ret = %d",
6222 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6227 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6229 #define QUERY_ACTIVE_SPEED 1
6230 struct hns3_sfp_speed_cmd *resp;
6231 uint32_t tmp_fec_capa;
6233 struct hns3_cmd_desc desc;
6237 * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6238 * configured FEC mode is returned.
6239 * If link is up, current FEC mode is returned.
6241 if (hw->mac.link_status == ETH_LINK_DOWN) {
6242 ret = get_current_fec_auto_state(hw, &auto_state);
6246 if (auto_state == 0x1) {
6247 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6252 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6253 resp = (struct hns3_sfp_speed_cmd *)desc.data;
6254 resp->query_type = QUERY_ACTIVE_SPEED;
6256 ret = hns3_cmd_send(hw, &desc, 1);
6257 if (ret == -EOPNOTSUPP) {
6258 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6261 hns3_err(hw, "get FEC failed, ret = %d", ret);
6266 * FEC mode order defined in hns3 hardware is inconsistend with
6267 * that defined in the ethdev library. So the sequence needs
6270 switch (resp->active_fec) {
6271 case HNS3_HW_FEC_MODE_NOFEC:
6272 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6274 case HNS3_HW_FEC_MODE_BASER:
6275 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6277 case HNS3_HW_FEC_MODE_RS:
6278 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6281 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6285 *fec_capa = tmp_fec_capa;
6290 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6292 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6294 return hns3_fec_get_internal(hw, fec_capa);
6298 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6300 struct hns3_config_fec_cmd *req;
6301 struct hns3_cmd_desc desc;
6304 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6306 req = (struct hns3_config_fec_cmd *)desc.data;
6308 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6309 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6310 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6312 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6313 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6314 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6316 case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6317 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6318 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6320 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6321 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6326 ret = hns3_cmd_send(hw, &desc, 1);
6328 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6334 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6336 struct hns3_mac *mac = &hw->mac;
6339 switch (mac->link_speed) {
6340 case ETH_SPEED_NUM_10G:
6341 cur_capa = fec_capa[1].capa;
6343 case ETH_SPEED_NUM_25G:
6344 case ETH_SPEED_NUM_100G:
6345 case ETH_SPEED_NUM_200G:
6346 cur_capa = fec_capa[0].capa;
6357 is_fec_mode_one_bit_set(uint32_t mode)
6362 for (i = 0; i < sizeof(mode); i++)
6363 if (mode >> i & 0x1)
6366 return cnt == 1 ? true : false;
6370 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6372 #define FEC_CAPA_NUM 2
6373 struct hns3_adapter *hns = dev->data->dev_private;
6374 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6375 struct hns3_pf *pf = &hns->pf;
6377 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6379 uint32_t num = FEC_CAPA_NUM;
6382 ret = hns3_fec_get_capability(dev, fec_capa, num);
6386 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6387 if (!is_fec_mode_one_bit_set(mode))
6388 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6389 "FEC mode should be only one bit set", mode);
6392 * Check whether the configured mode is within the FEC capability.
6393 * If not, the configured mode will not be supported.
6395 cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6396 if (!(cur_capa & mode)) {
6397 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6401 ret = hns3_set_fec_hw(hw, mode);
6405 pf->fec_mode = mode;
6410 hns3_restore_fec(struct hns3_hw *hw)
6412 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6413 struct hns3_pf *pf = &hns->pf;
6414 uint32_t mode = pf->fec_mode;
6417 ret = hns3_set_fec_hw(hw, mode);
6419 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6426 hns3_query_dev_fec_info(struct hns3_hw *hw)
6428 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6429 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6432 ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6434 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6440 hns3_optical_module_existed(struct hns3_hw *hw)
6442 struct hns3_cmd_desc desc;
6446 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6447 ret = hns3_cmd_send(hw, &desc, 1);
6450 "fail to get optical module exist state, ret = %d.\n",
6454 existed = !!desc.data[0];
6460 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6461 uint32_t len, uint8_t *data)
6463 #define HNS3_SFP_INFO_CMD_NUM 6
6464 #define HNS3_SFP_INFO_MAX_LEN \
6465 (HNS3_SFP_INFO_BD0_LEN + \
6466 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6467 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6468 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6474 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6475 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6477 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6478 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6481 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6482 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6483 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6484 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6486 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6488 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6493 /* The data format in BD0 is different with the others. */
6494 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6495 memcpy(data, sfp_info_bd0->data, copy_len);
6496 read_len = copy_len;
6498 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6499 if (read_len >= len)
6502 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6503 memcpy(data + read_len, desc[i].data, copy_len);
6504 read_len += copy_len;
6507 return (int)read_len;
6511 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6512 struct rte_dev_eeprom_info *info)
6514 struct hns3_adapter *hns = dev->data->dev_private;
6515 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6516 uint32_t offset = info->offset;
6517 uint32_t len = info->length;
6518 uint8_t *data = info->data;
6519 uint32_t read_len = 0;
6521 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6524 if (!hns3_optical_module_existed(hw)) {
6525 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6529 while (read_len < len) {
6531 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6543 hns3_get_module_info(struct rte_eth_dev *dev,
6544 struct rte_eth_dev_module_info *modinfo)
6546 #define HNS3_SFF8024_ID_SFP 0x03
6547 #define HNS3_SFF8024_ID_QSFP_8438 0x0c
6548 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d
6549 #define HNS3_SFF8024_ID_QSFP28_8636 0x11
6550 #define HNS3_SFF_8636_V1_3 0x03
6551 struct hns3_adapter *hns = dev->data->dev_private;
6552 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6553 struct rte_dev_eeprom_info info;
6554 struct hns3_sfp_type sfp_type;
6557 memset(&sfp_type, 0, sizeof(sfp_type));
6558 memset(&info, 0, sizeof(info));
6559 info.data = (uint8_t *)&sfp_type;
6560 info.length = sizeof(sfp_type);
6561 ret = hns3_get_module_eeprom(dev, &info);
6565 switch (sfp_type.type) {
6566 case HNS3_SFF8024_ID_SFP:
6567 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6568 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6570 case HNS3_SFF8024_ID_QSFP_8438:
6571 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6572 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6574 case HNS3_SFF8024_ID_QSFP_8436_8636:
6575 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6576 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6577 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6579 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6580 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6583 case HNS3_SFF8024_ID_QSFP28_8636:
6584 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6585 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6588 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6589 sfp_type.type, sfp_type.ext_type);
6597 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6599 uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6603 if (strcmp(value, "vec") == 0)
6604 hint = HNS3_IO_FUNC_HINT_VEC;
6605 else if (strcmp(value, "sve") == 0)
6606 hint = HNS3_IO_FUNC_HINT_SVE;
6607 else if (strcmp(value, "simple") == 0)
6608 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6609 else if (strcmp(value, "common") == 0)
6610 hint = HNS3_IO_FUNC_HINT_COMMON;
6612 /* If the hint is valid then update output parameters */
6613 if (hint != HNS3_IO_FUNC_HINT_NONE)
6614 *(uint32_t *)extra_args = hint;
6620 hns3_get_io_hint_func_name(uint32_t hint)
6623 case HNS3_IO_FUNC_HINT_VEC:
6625 case HNS3_IO_FUNC_HINT_SVE:
6627 case HNS3_IO_FUNC_HINT_SIMPLE:
6629 case HNS3_IO_FUNC_HINT_COMMON:
6637 hns3_parse_devargs(struct rte_eth_dev *dev)
6639 struct hns3_adapter *hns = dev->data->dev_private;
6640 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6641 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6642 struct hns3_hw *hw = &hns->hw;
6643 struct rte_kvargs *kvlist;
6645 if (dev->device->devargs == NULL)
6648 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6652 rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6653 &hns3_parse_io_hint_func, &rx_func_hint);
6654 rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6655 &hns3_parse_io_hint_func, &tx_func_hint);
6656 rte_kvargs_free(kvlist);
6658 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6659 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6660 hns3_get_io_hint_func_name(rx_func_hint));
6661 hns->rx_func_hint = rx_func_hint;
6662 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6663 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6664 hns3_get_io_hint_func_name(tx_func_hint));
6665 hns->tx_func_hint = tx_func_hint;
6668 static const struct eth_dev_ops hns3_eth_dev_ops = {
6669 .dev_configure = hns3_dev_configure,
6670 .dev_start = hns3_dev_start,
6671 .dev_stop = hns3_dev_stop,
6672 .dev_close = hns3_dev_close,
6673 .promiscuous_enable = hns3_dev_promiscuous_enable,
6674 .promiscuous_disable = hns3_dev_promiscuous_disable,
6675 .allmulticast_enable = hns3_dev_allmulticast_enable,
6676 .allmulticast_disable = hns3_dev_allmulticast_disable,
6677 .mtu_set = hns3_dev_mtu_set,
6678 .stats_get = hns3_stats_get,
6679 .stats_reset = hns3_stats_reset,
6680 .xstats_get = hns3_dev_xstats_get,
6681 .xstats_get_names = hns3_dev_xstats_get_names,
6682 .xstats_reset = hns3_dev_xstats_reset,
6683 .xstats_get_by_id = hns3_dev_xstats_get_by_id,
6684 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6685 .dev_infos_get = hns3_dev_infos_get,
6686 .fw_version_get = hns3_fw_version_get,
6687 .rx_queue_setup = hns3_rx_queue_setup,
6688 .tx_queue_setup = hns3_tx_queue_setup,
6689 .rx_queue_release = hns3_dev_rx_queue_release,
6690 .tx_queue_release = hns3_dev_tx_queue_release,
6691 .rx_queue_start = hns3_dev_rx_queue_start,
6692 .rx_queue_stop = hns3_dev_rx_queue_stop,
6693 .tx_queue_start = hns3_dev_tx_queue_start,
6694 .tx_queue_stop = hns3_dev_tx_queue_stop,
6695 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable,
6696 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable,
6697 .rxq_info_get = hns3_rxq_info_get,
6698 .txq_info_get = hns3_txq_info_get,
6699 .rx_burst_mode_get = hns3_rx_burst_mode_get,
6700 .tx_burst_mode_get = hns3_tx_burst_mode_get,
6701 .flow_ctrl_get = hns3_flow_ctrl_get,
6702 .flow_ctrl_set = hns3_flow_ctrl_set,
6703 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6704 .mac_addr_add = hns3_add_mac_addr,
6705 .mac_addr_remove = hns3_remove_mac_addr,
6706 .mac_addr_set = hns3_set_default_mac_addr,
6707 .set_mc_addr_list = hns3_set_mc_mac_addr_list,
6708 .link_update = hns3_dev_link_update,
6709 .rss_hash_update = hns3_dev_rss_hash_update,
6710 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get,
6711 .reta_update = hns3_dev_rss_reta_update,
6712 .reta_query = hns3_dev_rss_reta_query,
6713 .flow_ops_get = hns3_dev_flow_ops_get,
6714 .vlan_filter_set = hns3_vlan_filter_set,
6715 .vlan_tpid_set = hns3_vlan_tpid_set,
6716 .vlan_offload_set = hns3_vlan_offload_set,
6717 .vlan_pvid_set = hns3_vlan_pvid_set,
6718 .get_reg = hns3_get_regs,
6719 .get_module_info = hns3_get_module_info,
6720 .get_module_eeprom = hns3_get_module_eeprom,
6721 .get_dcb_info = hns3_get_dcb_info,
6722 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6723 .fec_get_capability = hns3_fec_get_capability,
6724 .fec_get = hns3_fec_get,
6725 .fec_set = hns3_fec_set,
6726 .tm_ops_get = hns3_tm_ops_get,
6727 .tx_done_cleanup = hns3_tx_done_cleanup,
6728 .timesync_enable = hns3_timesync_enable,
6729 .timesync_disable = hns3_timesync_disable,
6730 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6731 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6732 .timesync_adjust_time = hns3_timesync_adjust_time,
6733 .timesync_read_time = hns3_timesync_read_time,
6734 .timesync_write_time = hns3_timesync_write_time,
6737 static const struct hns3_reset_ops hns3_reset_ops = {
6738 .reset_service = hns3_reset_service,
6739 .stop_service = hns3_stop_service,
6740 .prepare_reset = hns3_prepare_reset,
6741 .wait_hardware_ready = hns3_wait_hardware_ready,
6742 .reinit_dev = hns3_reinit_dev,
6743 .restore_conf = hns3_restore_conf,
6744 .start_service = hns3_start_service,
6748 hns3_dev_init(struct rte_eth_dev *eth_dev)
6750 struct hns3_adapter *hns = eth_dev->data->dev_private;
6751 char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6752 struct rte_ether_addr *eth_addr;
6753 struct hns3_hw *hw = &hns->hw;
6756 PMD_INIT_FUNC_TRACE();
6758 eth_dev->process_private = (struct hns3_process_private *)
6759 rte_zmalloc_socket("hns3_filter_list",
6760 sizeof(struct hns3_process_private),
6761 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6762 if (eth_dev->process_private == NULL) {
6763 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6766 /* initialize flow filter lists */
6767 hns3_filterlist_init(eth_dev);
6769 hns3_set_rxtx_function(eth_dev);
6770 eth_dev->dev_ops = &hns3_eth_dev_ops;
6771 eth_dev->rx_queue_count = hns3_rx_queue_count;
6772 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6773 ret = hns3_mp_init_secondary();
6775 PMD_INIT_LOG(ERR, "Failed to init for secondary "
6776 "process, ret = %d", ret);
6777 goto err_mp_init_secondary;
6780 hw->secondary_cnt++;
6784 ret = hns3_mp_init_primary();
6787 "Failed to init for primary process, ret = %d",
6789 goto err_mp_init_primary;
6792 hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6794 hw->data = eth_dev->data;
6795 hns3_parse_devargs(eth_dev);
6798 * Set default max packet size according to the mtu
6799 * default vale in DPDK frame.
6801 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6803 ret = hns3_reset_init(hw);
6805 goto err_init_reset;
6806 hw->reset.ops = &hns3_reset_ops;
6808 ret = hns3_init_pf(eth_dev);
6810 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6814 /* Allocate memory for storing MAC addresses */
6815 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6816 sizeof(struct rte_ether_addr) *
6817 HNS3_UC_MACADDR_NUM, 0);
6818 if (eth_dev->data->mac_addrs == NULL) {
6819 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6820 "to store MAC addresses",
6821 sizeof(struct rte_ether_addr) *
6822 HNS3_UC_MACADDR_NUM);
6824 goto err_rte_zmalloc;
6827 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6828 if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6829 rte_eth_random_addr(hw->mac.mac_addr);
6830 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6831 (struct rte_ether_addr *)hw->mac.mac_addr);
6832 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6833 "unicast address, using random MAC address %s",
6836 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6837 ð_dev->data->mac_addrs[0]);
6839 hw->adapter_state = HNS3_NIC_INITIALIZED;
6841 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6843 hns3_err(hw, "Reschedule reset service after dev_init");
6844 hns3_schedule_reset(hns);
6846 /* IMP will wait ready flag before reset */
6847 hns3_notify_reset_ready(hw, false);
6850 hns3_info(hw, "hns3 dev initialization successful!");
6854 hns3_uninit_pf(eth_dev);
6857 rte_free(hw->reset.wait_data);
6860 hns3_mp_uninit_primary();
6862 err_mp_init_primary:
6863 err_mp_init_secondary:
6864 eth_dev->dev_ops = NULL;
6865 eth_dev->rx_pkt_burst = NULL;
6866 eth_dev->rx_descriptor_status = NULL;
6867 eth_dev->tx_pkt_burst = NULL;
6868 eth_dev->tx_pkt_prepare = NULL;
6869 eth_dev->tx_descriptor_status = NULL;
6870 rte_free(eth_dev->process_private);
6871 eth_dev->process_private = NULL;
6876 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6878 struct hns3_adapter *hns = eth_dev->data->dev_private;
6879 struct hns3_hw *hw = &hns->hw;
6881 PMD_INIT_FUNC_TRACE();
6883 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6884 rte_free(eth_dev->process_private);
6885 eth_dev->process_private = NULL;
6889 if (hw->adapter_state < HNS3_NIC_CLOSING)
6890 hns3_dev_close(eth_dev);
6892 hw->adapter_state = HNS3_NIC_REMOVED;
6897 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6898 struct rte_pci_device *pci_dev)
6900 return rte_eth_dev_pci_generic_probe(pci_dev,
6901 sizeof(struct hns3_adapter),
6906 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6908 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6911 static const struct rte_pci_id pci_id_hns3_map[] = {
6912 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6913 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6914 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6915 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6916 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6917 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6918 { .vendor_id = 0, }, /* sentinel */
6921 static struct rte_pci_driver rte_hns3_pmd = {
6922 .id_table = pci_id_hns3_map,
6923 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6924 .probe = eth_hns3_pci_probe,
6925 .remove = eth_hns3_pci_remove,
6928 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6929 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6930 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6931 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6932 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6933 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6934 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6935 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);