drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_OTHER,
  62 };
  63
  64 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  65         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  68
  69         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  73
  74         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  77
  78         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  82
  83         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  86
  87         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  90 };
  91
  92 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  93                                                  uint64_t *levels);
  94 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  95 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  96                                     int on);
  97 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  98 static bool hns3_update_link_status(struct hns3_hw *hw);
  99
 100 static int hns3_add_mc_addr(struct hns3_hw *hw,
 101                             struct rte_ether_addr *mac_addr);
 102 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 103                             struct rte_ether_addr *mac_addr);
 104 static int hns3_restore_fec(struct hns3_hw *hw);
 105 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 106 static int hns3_do_stop(struct hns3_adapter *hns);
 107
 108 void hns3_ether_format_addr(char *buf, uint16_t size,
 109                             const struct rte_ether_addr *ether_addr)
 110 {
 111         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 112                 ether_addr->addr_bytes[0],
 113                 ether_addr->addr_bytes[4],
 114                 ether_addr->addr_bytes[5]);
 115 }
 116
 117 static void
 118 hns3_pf_disable_irq0(struct hns3_hw *hw)
 119 {
 120         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 121 }
 122
 123 static void
 124 hns3_pf_enable_irq0(struct hns3_hw *hw)
 125 {
 126         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 127 }
 128
 129 static enum hns3_evt_cause
 130 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 131                           uint32_t *vec_val)
 132 {
 133         struct hns3_hw *hw = &hns->hw;
 134
 135         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 136         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 137         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 138         if (!is_delay) {
 139                 hw->reset.stats.imp_cnt++;
 140                 hns3_warn(hw, "IMP reset detected, clear reset status");
 141         } else {
 142                 hns3_schedule_delayed_reset(hns);
 143                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 144         }
 145
 146         return HNS3_VECTOR0_EVENT_RST;
 147 }
 148
 149 static enum hns3_evt_cause
 150 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 151                              uint32_t *vec_val)
 152 {
 153         struct hns3_hw *hw = &hns->hw;
 154
 155         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 156         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 157         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 158         if (!is_delay) {
 159                 hw->reset.stats.global_cnt++;
 160                 hns3_warn(hw, "Global reset detected, clear reset status");
 161         } else {
 162                 hns3_schedule_delayed_reset(hns);
 163                 hns3_warn(hw,
 164                           "Global reset detected, don't clear reset status");
 165         }
 166
 167         return HNS3_VECTOR0_EVENT_RST;
 168 }
 169
 170 static enum hns3_evt_cause
 171 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 172 {
 173         struct hns3_hw *hw = &hns->hw;
 174         uint32_t vector0_int_stats;
 175         uint32_t cmdq_src_val;
 176         uint32_t hw_err_src_reg;
 177         uint32_t val;
 178         enum hns3_evt_cause ret;
 179         bool is_delay;
 180
 181         /* fetch the events from their corresponding regs */
 182         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 183         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 184         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 185
 186         is_delay = clearval == NULL ? true : false;
 187         /*
 188          * Assumption: If by any chance reset and mailbox events are reported
 189          * together then we will only process reset event and defer the
 190          * processing of the mailbox events. Since, we would have not cleared
 191          * RX CMDQ event this time we would receive again another interrupt
 192          * from H/W just for the mailbox.
 193          */
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 195                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 196                 goto out;
 197         }
 198
 199         /* Global reset */
 200         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 201                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 202                 goto out;
 203         }
 204
 205         /* check for vector0 msix event source */
 206         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 207             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 208                 val = vector0_int_stats | hw_err_src_reg;
 209                 ret = HNS3_VECTOR0_EVENT_ERR;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 mailbox(=CMDQ RX) event source */
 214         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 215                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 216                 val = cmdq_src_val;
 217                 ret = HNS3_VECTOR0_EVENT_MBX;
 218                 goto out;
 219         }
 220
 221         val = vector0_int_stats;
 222         ret = HNS3_VECTOR0_EVENT_OTHER;
 223 out:
 224
 225         if (clearval)
 226                 *clearval = val;
 227         return ret;
 228 }
 229
 230 static void
 231 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 232 {
 233         if (event_type == HNS3_VECTOR0_EVENT_RST)
 234                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 235         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 236                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 237 }
 238
 239 static void
 240 hns3_clear_all_event_cause(struct hns3_hw *hw)
 241 {
 242         uint32_t vector0_int_stats;
 243         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 244
 245         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 246                 hns3_warn(hw, "Probe during IMP reset interrupt");
 247
 248         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 249                 hns3_warn(hw, "Probe during Global reset interrupt");
 250
 251         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 252                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 253                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 254                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 255         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 256 }
 257
 258 static void
 259 hns3_handle_mac_tnl(struct hns3_hw *hw)
 260 {
 261         struct hns3_cmd_desc desc;
 262         uint32_t status;
 263         int ret;
 264
 265         /* query and clear mac tnl interruptions */
 266         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 267         ret = hns3_cmd_send(hw, &desc, 1);
 268         if (ret) {
 269                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 270                 return;
 271         }
 272
 273         status = rte_le_to_cpu_32(desc.data[0]);
 274         if (status) {
 275                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 276                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 277                                           false);
 278                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 279                 ret = hns3_cmd_send(hw, &desc, 1);
 280                 if (ret)
 281                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 282                                  ret);
 283         }
 284 }
 285
 286 static void
 287 hns3_interrupt_handler(void *param)
 288 {
 289         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 290         struct hns3_adapter *hns = dev->data->dev_private;
 291         struct hns3_hw *hw = &hns->hw;
 292         enum hns3_evt_cause event_cause;
 293         uint32_t clearval = 0;
 294         uint32_t vector0_int;
 295         uint32_t ras_int;
 296         uint32_t cmdq_int;
 297
 298         /* Disable interrupt */
 299         hns3_pf_disable_irq0(hw);
 300
 301         event_cause = hns3_check_event_cause(hns, &clearval);
 302         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 303         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 304         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 305         /* vector 0 interrupt is shared with reset and mailbox source events. */
 306         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 307                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 308                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 309                           vector0_int, ras_int, cmdq_int);
 310                 hns3_handle_msix_error(hns, &hw->reset.request);
 311                 hns3_handle_ras_error(hns, &hw->reset.request);
 312                 hns3_handle_mac_tnl(hw);
 313                 hns3_schedule_reset(hns);
 314         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 315                 hns3_warn(hw, "received reset interrupt");
 316                 hns3_schedule_reset(hns);
 317         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 318                 hns3_dev_handle_mbx_msg(hw);
 319         } else {
 320                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 321                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 322                           vector0_int, ras_int, cmdq_int);
 323         }
 324
 325         hns3_clear_event_cause(hw, event_cause, clearval);
 326         /* Enable interrupt if it is not cause by reset */
 327         hns3_pf_enable_irq0(hw);
 328 }
 329
 330 static int
 331 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 332 {
 333 #define HNS3_VLAN_ID_OFFSET_STEP        160
 334 #define HNS3_VLAN_BYTE_SIZE             8
 335         struct hns3_vlan_filter_pf_cfg_cmd *req;
 336         struct hns3_hw *hw = &hns->hw;
 337         uint8_t vlan_offset_byte_val;
 338         struct hns3_cmd_desc desc;
 339         uint8_t vlan_offset_byte;
 340         uint8_t vlan_offset_base;
 341         int ret;
 342
 343         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 344
 345         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 346         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 347                            HNS3_VLAN_BYTE_SIZE;
 348         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 349
 350         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 351         req->vlan_offset = vlan_offset_base;
 352         req->vlan_cfg = on ? 0 : 1;
 353         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 354
 355         ret = hns3_cmd_send(hw, &desc, 1);
 356         if (ret)
 357                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 358                          vlan_id, ret);
 359
 360         return ret;
 361 }
 362
 363 static void
 364 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 365 {
 366         struct hns3_user_vlan_table *vlan_entry;
 367         struct hns3_pf *pf = &hns->pf;
 368
 369         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 370                 if (vlan_entry->vlan_id == vlan_id) {
 371                         if (vlan_entry->hd_tbl_status)
 372                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 373                         LIST_REMOVE(vlan_entry, next);
 374                         rte_free(vlan_entry);
 375                         break;
 376                 }
 377         }
 378 }
 379
 380 static void
 381 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 382                         bool writen_to_tbl)
 383 {
 384         struct hns3_user_vlan_table *vlan_entry;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_pf *pf = &hns->pf;
 387
 388         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 389                 if (vlan_entry->vlan_id == vlan_id)
 390                         return;
 391         }
 392
 393         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 394         if (vlan_entry == NULL) {
 395                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 396                 return;
 397         }
 398
 399         vlan_entry->hd_tbl_status = writen_to_tbl;
 400         vlan_entry->vlan_id = vlan_id;
 401
 402         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 403 }
 404
 405 static int
 406 hns3_restore_vlan_table(struct hns3_adapter *hns)
 407 {
 408         struct hns3_user_vlan_table *vlan_entry;
 409         struct hns3_hw *hw = &hns->hw;
 410         struct hns3_pf *pf = &hns->pf;
 411         uint16_t vlan_id;
 412         int ret = 0;
 413
 414         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 415                 return hns3_vlan_pvid_configure(hns,
 416                                                 hw->port_base_vlan_cfg.pvid, 1);
 417
 418         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 419                 if (vlan_entry->hd_tbl_status) {
 420                         vlan_id = vlan_entry->vlan_id;
 421                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 422                         if (ret)
 423                                 break;
 424                 }
 425         }
 426
 427         return ret;
 428 }
 429
 430 static int
 431 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 432 {
 433         struct hns3_hw *hw = &hns->hw;
 434         bool writen_to_tbl = false;
 435         int ret = 0;
 436
 437         /*
 438          * When vlan filter is enabled, hardware regards packets without vlan
 439          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 440          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 441          */
 442         if (on == 0 && vlan_id == 0)
 443                 return 0;
 444
 445         /*
 446          * When port base vlan enabled, we use port base vlan as the vlan
 447          * filter condition. In this case, we don't update vlan filter table
 448          * when user add new vlan or remove exist vlan, just update the
 449          * vlan list. The vlan id in vlan list will be writen in vlan filter
 450          * table until port base vlan disabled
 451          */
 452         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 453                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 454                 writen_to_tbl = true;
 455         }
 456
 457         if (ret == 0) {
 458                 if (on)
 459                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 460                 else
 461                         hns3_rm_dev_vlan_table(hns, vlan_id);
 462         }
 463         return ret;
 464 }
 465
 466 static int
 467 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 468 {
 469         struct hns3_adapter *hns = dev->data->dev_private;
 470         struct hns3_hw *hw = &hns->hw;
 471         int ret;
 472
 473         rte_spinlock_lock(&hw->lock);
 474         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 475         rte_spinlock_unlock(&hw->lock);
 476         return ret;
 477 }
 478
 479 static int
 480 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 481                          uint16_t tpid)
 482 {
 483         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 484         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 485         struct hns3_hw *hw = &hns->hw;
 486         struct hns3_cmd_desc desc;
 487         int ret;
 488
 489         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 490              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 491                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 492                 return -EINVAL;
 493         }
 494
 495         if (tpid != RTE_ETHER_TYPE_VLAN) {
 496                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 497                 return -EINVAL;
 498         }
 499
 500         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 501         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 502
 503         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 504                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 505                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 506         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 507                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 508                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 509                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 510                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 511         }
 512
 513         ret = hns3_cmd_send(hw, &desc, 1);
 514         if (ret) {
 515                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 516                          ret);
 517                 return ret;
 518         }
 519
 520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 521
 522         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 523         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 524         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 525
 526         ret = hns3_cmd_send(hw, &desc, 1);
 527         if (ret)
 528                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 529                          ret);
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 535                    uint16_t tpid)
 536 {
 537         struct hns3_adapter *hns = dev->data->dev_private;
 538         struct hns3_hw *hw = &hns->hw;
 539         int ret;
 540
 541         rte_spinlock_lock(&hw->lock);
 542         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 543         rte_spinlock_unlock(&hw->lock);
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 549                              struct hns3_rx_vtag_cfg *vcfg)
 550 {
 551         struct hns3_vport_vtag_rx_cfg_cmd *req;
 552         struct hns3_hw *hw = &hns->hw;
 553         struct hns3_cmd_desc desc;
 554         uint16_t vport_id;
 555         uint8_t bitmap;
 556         int ret;
 557
 558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 559
 560         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 561         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 562                      vcfg->strip_tag1_en ? 1 : 0);
 563         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 564                      vcfg->strip_tag2_en ? 1 : 0);
 565         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 566                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 567         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 568                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 569
 570         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 571         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 572                      vcfg->strip_tag1_discard_en ? 1 : 0);
 573         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 574                      vcfg->strip_tag2_discard_en ? 1 : 0);
 575         /*
 576          * In current version VF is not supported when PF is driven by DPDK
 577          * driver, just need to configure parameters for PF vport.
 578          */
 579         vport_id = HNS3_PF_FUNC_ID;
 580         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 581         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 582         req->vf_bitmap[req->vf_offset] = bitmap;
 583
 584         ret = hns3_cmd_send(hw, &desc, 1);
 585         if (ret)
 586                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 587         return ret;
 588 }
 589
 590 static void
 591 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 592                            struct hns3_rx_vtag_cfg *vcfg)
 593 {
 594         struct hns3_pf *pf = &hns->pf;
 595         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 596 }
 597
 598 static void
 599 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 600                            struct hns3_tx_vtag_cfg *vcfg)
 601 {
 602         struct hns3_pf *pf = &hns->pf;
 603         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 604 }
 605
 606 static int
 607 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 608 {
 609         struct hns3_rx_vtag_cfg rxvlan_cfg;
 610         struct hns3_hw *hw = &hns->hw;
 611         int ret;
 612
 613         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 614                 rxvlan_cfg.strip_tag1_en = false;
 615                 rxvlan_cfg.strip_tag2_en = enable;
 616                 rxvlan_cfg.strip_tag2_discard_en = false;
 617         } else {
 618                 rxvlan_cfg.strip_tag1_en = enable;
 619                 rxvlan_cfg.strip_tag2_en = true;
 620                 rxvlan_cfg.strip_tag2_discard_en = true;
 621         }
 622
 623         rxvlan_cfg.strip_tag1_discard_en = false;
 624         rxvlan_cfg.vlan1_vlan_prionly = false;
 625         rxvlan_cfg.vlan2_vlan_prionly = false;
 626         rxvlan_cfg.rx_vlan_offload_en = enable;
 627
 628         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 629         if (ret) {
 630                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 631                 return ret;
 632         }
 633
 634         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 635
 636         return ret;
 637 }
 638
 639 static int
 640 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 641                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 642 {
 643         struct hns3_vlan_filter_ctrl_cmd *req;
 644         struct hns3_cmd_desc desc;
 645         int ret;
 646
 647         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 648
 649         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 650         req->vlan_type = vlan_type;
 651         req->vlan_fe = filter_en ? fe_type : 0;
 652         req->vf_id = vf_id;
 653
 654         ret = hns3_cmd_send(hw, &desc, 1);
 655         if (ret)
 656                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 657
 658         return ret;
 659 }
 660
 661 static int
 662 hns3_vlan_filter_init(struct hns3_adapter *hns)
 663 {
 664         struct hns3_hw *hw = &hns->hw;
 665         int ret;
 666
 667         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 668                                         HNS3_FILTER_FE_EGRESS, false,
 669                                         HNS3_PF_FUNC_ID);
 670         if (ret) {
 671                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 672                 return ret;
 673         }
 674
 675         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 676                                         HNS3_FILTER_FE_INGRESS, false,
 677                                         HNS3_PF_FUNC_ID);
 678         if (ret)
 679                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 680
 681         return ret;
 682 }
 683
 684 static int
 685 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 686 {
 687         struct hns3_hw *hw = &hns->hw;
 688         int ret;
 689
 690         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 691                                         HNS3_FILTER_FE_INGRESS, enable,
 692                                         HNS3_PF_FUNC_ID);
 693         if (ret)
 694                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 695                          enable ? "enable" : "disable", ret);
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 702 {
 703         struct hns3_adapter *hns = dev->data->dev_private;
 704         struct hns3_hw *hw = &hns->hw;
 705         struct rte_eth_rxmode *rxmode;
 706         unsigned int tmp_mask;
 707         bool enable;
 708         int ret = 0;
 709
 710         rte_spinlock_lock(&hw->lock);
 711         rxmode = &dev->data->dev_conf.rxmode;
 712         tmp_mask = (unsigned int)mask;
 713         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 714                 /* ignore vlan filter configuration during promiscuous mode */
 715                 if (!dev->data->promiscuous) {
 716                         /* Enable or disable VLAN filter */
 717                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 718                                  true : false;
 719
 720                         ret = hns3_enable_vlan_filter(hns, enable);
 721                         if (ret) {
 722                                 rte_spinlock_unlock(&hw->lock);
 723                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 724                                          enable ? "enable" : "disable", ret);
 725                                 return ret;
 726                         }
 727                 }
 728         }
 729
 730         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 731                 /* Enable or disable VLAN stripping */
 732                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 733                     true : false;
 734
 735                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 736                 if (ret) {
 737                         rte_spinlock_unlock(&hw->lock);
 738                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 739                                  enable ? "enable" : "disable", ret);
 740                         return ret;
 741                 }
 742         }
 743
 744         rte_spinlock_unlock(&hw->lock);
 745
 746         return ret;
 747 }
 748
 749 static int
 750 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 751                              struct hns3_tx_vtag_cfg *vcfg)
 752 {
 753         struct hns3_vport_vtag_tx_cfg_cmd *req;
 754         struct hns3_cmd_desc desc;
 755         struct hns3_hw *hw = &hns->hw;
 756         uint16_t vport_id;
 757         uint8_t bitmap;
 758         int ret;
 759
 760         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 761
 762         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 763         req->def_vlan_tag1 = vcfg->default_tag1;
 764         req->def_vlan_tag2 = vcfg->default_tag2;
 765         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 766                      vcfg->accept_tag1 ? 1 : 0);
 767         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 768                      vcfg->accept_untag1 ? 1 : 0);
 769         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 770                      vcfg->accept_tag2 ? 1 : 0);
 771         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 772                      vcfg->accept_untag2 ? 1 : 0);
 773         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 774                      vcfg->insert_tag1_en ? 1 : 0);
 775         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 776                      vcfg->insert_tag2_en ? 1 : 0);
 777         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 778
 779         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 781                      vcfg->tag_shift_mode_en ? 1 : 0);
 782
 783         /*
 784          * In current version VF is not supported when PF is driven by DPDK
 785          * driver, just need to configure parameters for PF vport.
 786          */
 787         vport_id = HNS3_PF_FUNC_ID;
 788         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 789         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 790         req->vf_bitmap[req->vf_offset] = bitmap;
 791
 792         ret = hns3_cmd_send(hw, &desc, 1);
 793         if (ret)
 794                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 795
 796         return ret;
 797 }
 798
 799 static int
 800 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 801                      uint16_t pvid)
 802 {
 803         struct hns3_hw *hw = &hns->hw;
 804         struct hns3_tx_vtag_cfg txvlan_cfg;
 805         int ret;
 806
 807         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 808                 txvlan_cfg.accept_tag1 = true;
 809                 txvlan_cfg.insert_tag1_en = false;
 810                 txvlan_cfg.default_tag1 = 0;
 811         } else {
 812                 txvlan_cfg.accept_tag1 =
 813                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 814                 txvlan_cfg.insert_tag1_en = true;
 815                 txvlan_cfg.default_tag1 = pvid;
 816         }
 817
 818         txvlan_cfg.accept_untag1 = true;
 819         txvlan_cfg.accept_tag2 = true;
 820         txvlan_cfg.accept_untag2 = true;
 821         txvlan_cfg.insert_tag2_en = false;
 822         txvlan_cfg.default_tag2 = 0;
 823         txvlan_cfg.tag_shift_mode_en = true;
 824
 825         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 826         if (ret) {
 827                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 828                          ret);
 829                 return ret;
 830         }
 831
 832         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 833         return ret;
 834 }
 835
 836
 837 static void
 838 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 839 {
 840         struct hns3_user_vlan_table *vlan_entry;
 841         struct hns3_pf *pf = &hns->pf;
 842
 843         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 844                 if (vlan_entry->hd_tbl_status) {
 845                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 846                         vlan_entry->hd_tbl_status = false;
 847                 }
 848         }
 849
 850         if (is_del_list) {
 851                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 852                 while (vlan_entry) {
 853                         LIST_REMOVE(vlan_entry, next);
 854                         rte_free(vlan_entry);
 855                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 856                 }
 857         }
 858 }
 859
 860 static void
 861 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 862 {
 863         struct hns3_user_vlan_table *vlan_entry;
 864         struct hns3_pf *pf = &hns->pf;
 865
 866         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 867                 if (!vlan_entry->hd_tbl_status) {
 868                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 869                         vlan_entry->hd_tbl_status = true;
 870                 }
 871         }
 872 }
 873
 874 static void
 875 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 876 {
 877         struct hns3_hw *hw = &hns->hw;
 878         int ret;
 879
 880         hns3_rm_all_vlan_table(hns, true);
 881         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 882                 ret = hns3_set_port_vlan_filter(hns,
 883                                                 hw->port_base_vlan_cfg.pvid, 0);
 884                 if (ret) {
 885                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 886                                  ret);
 887                         return;
 888                 }
 889         }
 890 }
 891
 892 static int
 893 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 894                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 895 {
 896         struct hns3_hw *hw = &hns->hw;
 897         uint16_t old_pvid;
 898         int ret;
 899
 900         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 901                 old_pvid = hw->port_base_vlan_cfg.pvid;
 902                 if (old_pvid != HNS3_INVALID_PVID) {
 903                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 904                         if (ret) {
 905                                 hns3_err(hw, "failed to remove old pvid %u, "
 906                                                 "ret = %d", old_pvid, ret);
 907                                 return ret;
 908                         }
 909                 }
 910
 911                 hns3_rm_all_vlan_table(hns, false);
 912                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 913                 if (ret) {
 914                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 915                                         new_pvid, ret);
 916                         return ret;
 917                 }
 918         } else {
 919                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 920                 if (ret) {
 921                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 922                                         new_pvid, ret);
 923                         return ret;
 924                 }
 925
 926                 hns3_add_all_vlan_table(hns);
 927         }
 928         return 0;
 929 }
 930
 931 static int
 932 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 933 {
 934         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 935         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 936         bool rx_strip_en;
 937         int ret;
 938
 939         rx_strip_en = old_cfg->rx_vlan_offload_en;
 940         if (on) {
 941                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 942                 rx_vlan_cfg.strip_tag2_en = true;
 943                 rx_vlan_cfg.strip_tag2_discard_en = true;
 944         } else {
 945                 rx_vlan_cfg.strip_tag1_en = false;
 946                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 947                 rx_vlan_cfg.strip_tag2_discard_en = false;
 948         }
 949         rx_vlan_cfg.strip_tag1_discard_en = false;
 950         rx_vlan_cfg.vlan1_vlan_prionly = false;
 951         rx_vlan_cfg.vlan2_vlan_prionly = false;
 952         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 953
 954         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 955         if (ret)
 956                 return ret;
 957
 958         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 959         return ret;
 960 }
 961
 962 static int
 963 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 964 {
 965         struct hns3_hw *hw = &hns->hw;
 966         uint16_t port_base_vlan_state;
 967         int ret;
 968
 969         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 970                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 971                         hns3_warn(hw, "Invalid operation! As current pvid set "
 972                                   "is %u, disable pvid %u is invalid",
 973                                   hw->port_base_vlan_cfg.pvid, pvid);
 974                 return 0;
 975         }
 976
 977         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 978                                     HNS3_PORT_BASE_VLAN_DISABLE;
 979         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 980         if (ret) {
 981                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 982                          ret);
 983                 return ret;
 984         }
 985
 986         ret = hns3_en_pvid_strip(hns, on);
 987         if (ret) {
 988                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 989                          "ret = %d", ret);
 990                 return ret;
 991         }
 992
 993         if (pvid == HNS3_INVALID_PVID)
 994                 goto out;
 995         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 996         if (ret) {
 997                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 998                          ret);
 999                 return ret;
1000         }
1001
1002 out:
1003         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1004         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1005         return ret;
1006 }
1007
1008 static int
1009 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1010 {
1011         struct hns3_adapter *hns = dev->data->dev_private;
1012         struct hns3_hw *hw = &hns->hw;
1013         bool pvid_en_state_change;
1014         uint16_t pvid_state;
1015         int ret;
1016
1017         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1018                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1019                          RTE_ETHER_MAX_VLAN_ID);
1020                 return -EINVAL;
1021         }
1022
1023         /*
1024          * If PVID configuration state change, should refresh the PVID
1025          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1026          */
1027         pvid_state = hw->port_base_vlan_cfg.state;
1028         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1029             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1030                 pvid_en_state_change = false;
1031         else
1032                 pvid_en_state_change = true;
1033
1034         rte_spinlock_lock(&hw->lock);
1035         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1036         rte_spinlock_unlock(&hw->lock);
1037         if (ret)
1038                 return ret;
1039         /*
1040          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1041          * need be processed by PMD driver.
1042          */
1043         if (pvid_en_state_change &&
1044             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1045                 hns3_update_all_queues_pvid_proc_en(hw);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 hns3_default_vlan_config(struct hns3_adapter *hns)
1052 {
1053         struct hns3_hw *hw = &hns->hw;
1054         int ret;
1055
1056         /*
1057          * When vlan filter is enabled, hardware regards packets without vlan
1058          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1059          * table, packets without vlan won't be received. So, add vlan 0 as
1060          * the default vlan.
1061          */
1062         ret = hns3_vlan_filter_configure(hns, 0, 1);
1063         if (ret)
1064                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1065         return ret;
1066 }
1067
1068 static int
1069 hns3_init_vlan_config(struct hns3_adapter *hns)
1070 {
1071         struct hns3_hw *hw = &hns->hw;
1072         int ret;
1073
1074         /*
1075          * This function can be called in the initialization and reset process,
1076          * when in reset process, it means that hardware had been reseted
1077          * successfully and we need to restore the hardware configuration to
1078          * ensure that the hardware configuration remains unchanged before and
1079          * after reset.
1080          */
1081         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1082                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1083                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1084         }
1085
1086         ret = hns3_vlan_filter_init(hns);
1087         if (ret) {
1088                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1089                 return ret;
1090         }
1091
1092         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1093                                        RTE_ETHER_TYPE_VLAN);
1094         if (ret) {
1095                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1096                 return ret;
1097         }
1098
1099         /*
1100          * When in the reinit dev stage of the reset process, the following
1101          * vlan-related configurations may differ from those at initialization,
1102          * we will restore configurations to hardware in hns3_restore_vlan_table
1103          * and hns3_restore_vlan_conf later.
1104          */
1105         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1106                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1107                 if (ret) {
1108                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1109                         return ret;
1110                 }
1111
1112                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1113                 if (ret) {
1114                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1115                                  ret);
1116                         return ret;
1117                 }
1118         }
1119
1120         return hns3_default_vlan_config(hns);
1121 }
1122
1123 static int
1124 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1125 {
1126         struct hns3_pf *pf = &hns->pf;
1127         struct hns3_hw *hw = &hns->hw;
1128         uint64_t offloads;
1129         bool enable;
1130         int ret;
1131
1132         if (!hw->data->promiscuous) {
1133                 /* restore vlan filter states */
1134                 offloads = hw->data->dev_conf.rxmode.offloads;
1135                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1136                 ret = hns3_enable_vlan_filter(hns, enable);
1137                 if (ret) {
1138                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1139                                  "ret = %d", ret);
1140                         return ret;
1141                 }
1142         }
1143
1144         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1145         if (ret) {
1146                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1147                 return ret;
1148         }
1149
1150         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1151         if (ret)
1152                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1153
1154         return ret;
1155 }
1156
1157 static int
1158 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1159 {
1160         struct hns3_adapter *hns = dev->data->dev_private;
1161         struct rte_eth_dev_data *data = dev->data;
1162         struct rte_eth_txmode *txmode;
1163         struct hns3_hw *hw = &hns->hw;
1164         int mask;
1165         int ret;
1166
1167         txmode = &data->dev_conf.txmode;
1168         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1169                 hns3_warn(hw,
1170                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1171                           "configuration is not supported! Ignore these two "
1172                           "parameters: hw_vlan_reject_tagged(%u), "
1173                           "hw_vlan_reject_untagged(%u)",
1174                           txmode->hw_vlan_reject_tagged,
1175                           txmode->hw_vlan_reject_untagged);
1176
1177         /* Apply vlan offload setting */
1178         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1179         ret = hns3_vlan_offload_set(dev, mask);
1180         if (ret) {
1181                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1182                          ret);
1183                 return ret;
1184         }
1185
1186         /*
1187          * If pvid config is not set in rte_eth_conf, driver needn't to set
1188          * VLAN pvid related configuration to hardware.
1189          */
1190         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1191                 return 0;
1192
1193         /* Apply pvid setting */
1194         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1195                                  txmode->hw_vlan_insert_pvid);
1196         if (ret)
1197                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1198                          txmode->pvid, ret);
1199
1200         return ret;
1201 }
1202
1203 static int
1204 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1205                 unsigned int tso_mss_max)
1206 {
1207         struct hns3_cfg_tso_status_cmd *req;
1208         struct hns3_cmd_desc desc;
1209         uint16_t tso_mss;
1210
1211         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1212
1213         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1214
1215         tso_mss = 0;
1216         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1217                        tso_mss_min);
1218         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1219
1220         tso_mss = 0;
1221         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1222                        tso_mss_max);
1223         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1224
1225         return hns3_cmd_send(hw, &desc, 1);
1226 }
1227
1228 static int
1229 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1230                    uint16_t *allocated_size, bool is_alloc)
1231 {
1232         struct hns3_umv_spc_alc_cmd *req;
1233         struct hns3_cmd_desc desc;
1234         int ret;
1235
1236         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1237         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1238         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1239         req->space_size = rte_cpu_to_le_32(space_size);
1240
1241         ret = hns3_cmd_send(hw, &desc, 1);
1242         if (ret) {
1243                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1244                              is_alloc ? "allocate" : "free", ret);
1245                 return ret;
1246         }
1247
1248         if (is_alloc && allocated_size)
1249                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1250
1251         return 0;
1252 }
1253
1254 static int
1255 hns3_init_umv_space(struct hns3_hw *hw)
1256 {
1257         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1258         struct hns3_pf *pf = &hns->pf;
1259         uint16_t allocated_size = 0;
1260         int ret;
1261
1262         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1263                                  true);
1264         if (ret)
1265                 return ret;
1266
1267         if (allocated_size < pf->wanted_umv_size)
1268                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1269                              pf->wanted_umv_size, allocated_size);
1270
1271         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1272                                                 pf->wanted_umv_size;
1273         pf->used_umv_size = 0;
1274         return 0;
1275 }
1276
1277 static int
1278 hns3_uninit_umv_space(struct hns3_hw *hw)
1279 {
1280         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1281         struct hns3_pf *pf = &hns->pf;
1282         int ret;
1283
1284         if (pf->max_umv_size == 0)
1285                 return 0;
1286
1287         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1288         if (ret)
1289                 return ret;
1290
1291         pf->max_umv_size = 0;
1292
1293         return 0;
1294 }
1295
1296 static bool
1297 hns3_is_umv_space_full(struct hns3_hw *hw)
1298 {
1299         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1300         struct hns3_pf *pf = &hns->pf;
1301         bool is_full;
1302
1303         is_full = (pf->used_umv_size >= pf->max_umv_size);
1304
1305         return is_full;
1306 }
1307
1308 static void
1309 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313
1314         if (is_free) {
1315                 if (pf->used_umv_size > 0)
1316                         pf->used_umv_size--;
1317         } else
1318                 pf->used_umv_size++;
1319 }
1320
1321 static void
1322 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1323                       const uint8_t *addr, bool is_mc)
1324 {
1325         const unsigned char *mac_addr = addr;
1326         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1327                             ((uint32_t)mac_addr[2] << 16) |
1328                             ((uint32_t)mac_addr[1] << 8) |
1329                             (uint32_t)mac_addr[0];
1330         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1331
1332         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1333         if (is_mc) {
1334                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1335                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1336                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1337         }
1338
1339         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1340         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1341 }
1342
1343 static int
1344 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1345                              uint8_t resp_code,
1346                              enum hns3_mac_vlan_tbl_opcode op)
1347 {
1348         if (cmdq_resp) {
1349                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1350                          cmdq_resp);
1351                 return -EIO;
1352         }
1353
1354         if (op == HNS3_MAC_VLAN_ADD) {
1355                 if (resp_code == 0 || resp_code == 1) {
1356                         return 0;
1357                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1358                         hns3_err(hw, "add mac addr failed for uc_overflow");
1359                         return -ENOSPC;
1360                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1361                         hns3_err(hw, "add mac addr failed for mc_overflow");
1362                         return -ENOSPC;
1363                 }
1364
1365                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1366                          resp_code);
1367                 return -EIO;
1368         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1369                 if (resp_code == 0) {
1370                         return 0;
1371                 } else if (resp_code == 1) {
1372                         hns3_dbg(hw, "remove mac addr failed for miss");
1373                         return -ENOENT;
1374                 }
1375
1376                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1377                          resp_code);
1378                 return -EIO;
1379         } else if (op == HNS3_MAC_VLAN_LKUP) {
1380                 if (resp_code == 0) {
1381                         return 0;
1382                 } else if (resp_code == 1) {
1383                         hns3_dbg(hw, "lookup mac addr failed for miss");
1384                         return -ENOENT;
1385                 }
1386
1387                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1388                          resp_code);
1389                 return -EIO;
1390         }
1391
1392         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1393                  op);
1394
1395         return -EINVAL;
1396 }
1397
1398 static int
1399 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1400                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1401                          struct hns3_cmd_desc *desc, bool is_mc)
1402 {
1403         uint8_t resp_code;
1404         uint16_t retval;
1405         int ret;
1406
1407         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1408         if (is_mc) {
1409                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1410                 memcpy(desc[0].data, req,
1411                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1412                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1413                                           true);
1414                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1415                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1416                                           true);
1417                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1418         } else {
1419                 memcpy(desc[0].data, req,
1420                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1421                 ret = hns3_cmd_send(hw, desc, 1);
1422         }
1423         if (ret) {
1424                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1425                          ret);
1426                 return ret;
1427         }
1428         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1429         retval = rte_le_to_cpu_16(desc[0].retval);
1430
1431         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1432                                             HNS3_MAC_VLAN_LKUP);
1433 }
1434
1435 static int
1436 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1437                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1438                       struct hns3_cmd_desc *mc_desc)
1439 {
1440         uint8_t resp_code;
1441         uint16_t retval;
1442         int cfg_status;
1443         int ret;
1444
1445         if (mc_desc == NULL) {
1446                 struct hns3_cmd_desc desc;
1447
1448                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1449                 memcpy(desc.data, req,
1450                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451                 ret = hns3_cmd_send(hw, &desc, 1);
1452                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1453                 retval = rte_le_to_cpu_16(desc.retval);
1454
1455                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1456                                                           HNS3_MAC_VLAN_ADD);
1457         } else {
1458                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1459                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1460                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1461                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1462                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1463                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1464                 memcpy(mc_desc[0].data, req,
1465                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1466                 mc_desc[0].retval = 0;
1467                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1468                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1469                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1470
1471                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1472                                                           HNS3_MAC_VLAN_ADD);
1473         }
1474
1475         if (ret) {
1476                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1477                 return ret;
1478         }
1479
1480         return cfg_status;
1481 }
1482
1483 static int
1484 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1485                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1486 {
1487         struct hns3_cmd_desc desc;
1488         uint8_t resp_code;
1489         uint16_t retval;
1490         int ret;
1491
1492         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1493
1494         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1495
1496         ret = hns3_cmd_send(hw, &desc, 1);
1497         if (ret) {
1498                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1499                 return ret;
1500         }
1501         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1502         retval = rte_le_to_cpu_16(desc.retval);
1503
1504         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1505                                             HNS3_MAC_VLAN_REMOVE);
1506 }
1507
1508 static int
1509 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1510 {
1511         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1512         struct hns3_mac_vlan_tbl_entry_cmd req;
1513         struct hns3_pf *pf = &hns->pf;
1514         struct hns3_cmd_desc desc[3];
1515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1516         uint16_t egress_port = 0;
1517         uint8_t vf_id;
1518         int ret;
1519
1520         /* check if mac addr is valid */
1521         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1522                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1523                                       mac_addr);
1524                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1525                          mac_str);
1526                 return -EINVAL;
1527         }
1528
1529         memset(&req, 0, sizeof(req));
1530
1531         /*
1532          * In current version VF is not supported when PF is driven by DPDK
1533          * driver, just need to configure parameters for PF vport.
1534          */
1535         vf_id = HNS3_PF_FUNC_ID;
1536         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1537                        HNS3_MAC_EPORT_VFID_S, vf_id);
1538
1539         req.egress_port = rte_cpu_to_le_16(egress_port);
1540
1541         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1542
1543         /*
1544          * Lookup the mac address in the mac_vlan table, and add
1545          * it if the entry is inexistent. Repeated unicast entry
1546          * is not allowed in the mac vlan table.
1547          */
1548         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1549         if (ret == -ENOENT) {
1550                 if (!hns3_is_umv_space_full(hw)) {
1551                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1552                         if (!ret)
1553                                 hns3_update_umv_space(hw, false);
1554                         return ret;
1555                 }
1556
1557                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1558
1559                 return -ENOSPC;
1560         }
1561
1562         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1563
1564         /* check if we just hit the duplicate */
1565         if (ret == 0) {
1566                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1567                 return 0;
1568         }
1569
1570         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1571                  mac_str);
1572
1573         return ret;
1574 }
1575
1576 static int
1577 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1578 {
1579         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1580         struct rte_ether_addr *addr;
1581         int ret;
1582         int i;
1583
1584         for (i = 0; i < hw->mc_addrs_num; i++) {
1585                 addr = &hw->mc_addrs[i];
1586                 /* Check if there are duplicate addresses */
1587                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1588                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1589                                               addr);
1590                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1591                                  "(%s) is added by the set_mc_mac_addr_list "
1592                                  "API", mac_str);
1593                         return -EINVAL;
1594                 }
1595         }
1596
1597         ret = hns3_add_mc_addr(hw, mac_addr);
1598         if (ret) {
1599                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1600                                       mac_addr);
1601                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1602                          mac_str, ret);
1603         }
1604         return ret;
1605 }
1606
1607 static int
1608 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 {
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         int ret;
1612
1613         ret = hns3_remove_mc_addr(hw, mac_addr);
1614         if (ret) {
1615                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1616                                       mac_addr);
1617                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1618                          mac_str, ret);
1619         }
1620         return ret;
1621 }
1622
1623 static int
1624 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1625                   uint32_t idx, __rte_unused uint32_t pool)
1626 {
1627         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         int ret;
1630
1631         rte_spinlock_lock(&hw->lock);
1632
1633         /*
1634          * In hns3 network engine adding UC and MC mac address with different
1635          * commands with firmware. We need to determine whether the input
1636          * address is a UC or a MC address to call different commands.
1637          * By the way, it is recommended calling the API function named
1638          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1639          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1640          * may affect the specifications of UC mac addresses.
1641          */
1642         if (rte_is_multicast_ether_addr(mac_addr))
1643                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1644         else
1645                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1646
1647         if (ret) {
1648                 rte_spinlock_unlock(&hw->lock);
1649                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1650                                       mac_addr);
1651                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1652                          ret);
1653                 return ret;
1654         }
1655
1656         if (idx == 0)
1657                 hw->mac.default_addr_setted = true;
1658         rte_spinlock_unlock(&hw->lock);
1659
1660         return ret;
1661 }
1662
1663 static int
1664 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1665 {
1666         struct hns3_mac_vlan_tbl_entry_cmd req;
1667         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1668         int ret;
1669
1670         /* check if mac addr is valid */
1671         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1672                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1673                                       mac_addr);
1674                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1675                          mac_str);
1676                 return -EINVAL;
1677         }
1678
1679         memset(&req, 0, sizeof(req));
1680         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1681         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1682         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1683         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1684                 return 0;
1685         else if (ret == 0)
1686                 hns3_update_umv_space(hw, true);
1687
1688         return ret;
1689 }
1690
1691 static void
1692 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1693 {
1694         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         /* index will be checked by upper level rte interface */
1696         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1697         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698         int ret;
1699
1700         rte_spinlock_lock(&hw->lock);
1701
1702         if (rte_is_multicast_ether_addr(mac_addr))
1703                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1704         else
1705                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1706         rte_spinlock_unlock(&hw->lock);
1707         if (ret) {
1708                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1709                                       mac_addr);
1710                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1711                          ret);
1712         }
1713 }
1714
1715 static int
1716 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1717                           struct rte_ether_addr *mac_addr)
1718 {
1719         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720         struct rte_ether_addr *oaddr;
1721         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1722         bool default_addr_setted;
1723         bool rm_succes = false;
1724         int ret, ret_val;
1725
1726         /*
1727          * It has been guaranteed that input parameter named mac_addr is valid
1728          * address in the rte layer of DPDK framework.
1729          */
1730         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1731         default_addr_setted = hw->mac.default_addr_setted;
1732         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1733                 return 0;
1734
1735         rte_spinlock_lock(&hw->lock);
1736         if (default_addr_setted) {
1737                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1738                 if (ret) {
1739                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                               oaddr);
1741                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1742                                   mac_str, ret);
1743                         rm_succes = false;
1744                 } else
1745                         rm_succes = true;
1746         }
1747
1748         ret = hns3_add_uc_addr_common(hw, mac_addr);
1749         if (ret) {
1750                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1751                                       mac_addr);
1752                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1753                 goto err_add_uc_addr;
1754         }
1755
1756         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1757         if (ret) {
1758                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1759                 goto err_pause_addr_cfg;
1760         }
1761
1762         rte_ether_addr_copy(mac_addr,
1763                             (struct rte_ether_addr *)hw->mac.mac_addr);
1764         hw->mac.default_addr_setted = true;
1765         rte_spinlock_unlock(&hw->lock);
1766
1767         return 0;
1768
1769 err_pause_addr_cfg:
1770         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1771         if (ret_val) {
1772                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1773                                       mac_addr);
1774                 hns3_warn(hw,
1775                           "Failed to roll back to del setted mac addr(%s): %d",
1776                           mac_str, ret_val);
1777         }
1778
1779 err_add_uc_addr:
1780         if (rm_succes) {
1781                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1782                 if (ret_val) {
1783                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1784                                               oaddr);
1785                         hns3_warn(hw,
1786                                   "Failed to restore old uc mac addr(%s): %d",
1787                                   mac_str, ret_val);
1788                         hw->mac.default_addr_setted = false;
1789                 }
1790         }
1791         rte_spinlock_unlock(&hw->lock);
1792
1793         return ret;
1794 }
1795
1796 static int
1797 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1798 {
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         struct hns3_hw *hw = &hns->hw;
1801         struct rte_ether_addr *addr;
1802         int err = 0;
1803         int ret;
1804         int i;
1805
1806         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1807                 addr = &hw->data->mac_addrs[i];
1808                 if (rte_is_zero_ether_addr(addr))
1809                         continue;
1810                 if (rte_is_multicast_ether_addr(addr))
1811                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1812                               hns3_add_mc_addr(hw, addr);
1813                 else
1814                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1815                               hns3_add_uc_addr_common(hw, addr);
1816
1817                 if (ret) {
1818                         err = ret;
1819                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1820                                               addr);
1821                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1822                                  "ret = %d.", del ? "remove" : "restore",
1823                                  mac_str, i, ret);
1824                 }
1825         }
1826         return err;
1827 }
1828
1829 static void
1830 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1831 {
1832 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1833         uint8_t word_num;
1834         uint8_t bit_num;
1835
1836         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1837                 word_num = vfid / 32;
1838                 bit_num = vfid % 32;
1839                 if (clr)
1840                         desc[1].data[word_num] &=
1841                             rte_cpu_to_le_32(~(1UL << bit_num));
1842                 else
1843                         desc[1].data[word_num] |=
1844                             rte_cpu_to_le_32(1UL << bit_num);
1845         } else {
1846                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1847                 bit_num = vfid % 32;
1848                 if (clr)
1849                         desc[2].data[word_num] &=
1850                             rte_cpu_to_le_32(~(1UL << bit_num));
1851                 else
1852                         desc[2].data[word_num] |=
1853                             rte_cpu_to_le_32(1UL << bit_num);
1854         }
1855 }
1856
1857 static int
1858 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1859 {
1860         struct hns3_mac_vlan_tbl_entry_cmd req;
1861         struct hns3_cmd_desc desc[3];
1862         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1863         uint8_t vf_id;
1864         int ret;
1865
1866         /* Check if mac addr is valid */
1867         if (!rte_is_multicast_ether_addr(mac_addr)) {
1868                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1869                                       mac_addr);
1870                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1871                          mac_str);
1872                 return -EINVAL;
1873         }
1874
1875         memset(&req, 0, sizeof(req));
1876         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1877         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1878         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1879         if (ret) {
1880                 /* This mac addr do not exist, add new entry for it */
1881                 memset(desc[0].data, 0, sizeof(desc[0].data));
1882                 memset(desc[1].data, 0, sizeof(desc[0].data));
1883                 memset(desc[2].data, 0, sizeof(desc[0].data));
1884         }
1885
1886         /*
1887          * In current version VF is not supported when PF is driven by DPDK
1888          * driver, just need to configure parameters for PF vport.
1889          */
1890         vf_id = HNS3_PF_FUNC_ID;
1891         hns3_update_desc_vfid(desc, vf_id, false);
1892         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1893         if (ret) {
1894                 if (ret == -ENOSPC)
1895                         hns3_err(hw, "mc mac vlan table is full");
1896                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1897                                       mac_addr);
1898                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1899         }
1900
1901         return ret;
1902 }
1903
1904 static int
1905 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1906 {
1907         struct hns3_mac_vlan_tbl_entry_cmd req;
1908         struct hns3_cmd_desc desc[3];
1909         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1910         uint8_t vf_id;
1911         int ret;
1912
1913         /* Check if mac addr is valid */
1914         if (!rte_is_multicast_ether_addr(mac_addr)) {
1915                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1916                                       mac_addr);
1917                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1918                          mac_str);
1919                 return -EINVAL;
1920         }
1921
1922         memset(&req, 0, sizeof(req));
1923         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1924         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1925         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1926         if (ret == 0) {
1927                 /*
1928                  * This mac addr exist, remove this handle's VFID for it.
1929                  * In current version VF is not supported when PF is driven by
1930                  * DPDK driver, just need to configure parameters for PF vport.
1931                  */
1932                 vf_id = HNS3_PF_FUNC_ID;
1933                 hns3_update_desc_vfid(desc, vf_id, true);
1934
1935                 /* All the vfid is zero, so need to delete this entry */
1936                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1937         } else if (ret == -ENOENT) {
1938                 /* This mac addr doesn't exist. */
1939                 return 0;
1940         }
1941
1942         if (ret) {
1943                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1944                                       mac_addr);
1945                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1946         }
1947
1948         return ret;
1949 }
1950
1951 static int
1952 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1953                            struct rte_ether_addr *mc_addr_set,
1954                            uint32_t nb_mc_addr)
1955 {
1956         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1957         struct rte_ether_addr *addr;
1958         uint32_t i;
1959         uint32_t j;
1960
1961         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1962                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1963                          "invalid. valid range: 0~%d",
1964                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1965                 return -EINVAL;
1966         }
1967
1968         /* Check if input mac addresses are valid */
1969         for (i = 0; i < nb_mc_addr; i++) {
1970                 addr = &mc_addr_set[i];
1971                 if (!rte_is_multicast_ether_addr(addr)) {
1972                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1973                                               addr);
1974                         hns3_err(hw,
1975                                  "failed to set mc mac addr, addr(%s) invalid.",
1976                                  mac_str);
1977                         return -EINVAL;
1978                 }
1979
1980                 /* Check if there are duplicate addresses */
1981                 for (j = i + 1; j < nb_mc_addr; j++) {
1982                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1983                                 hns3_ether_format_addr(mac_str,
1984                                                       RTE_ETHER_ADDR_FMT_SIZE,
1985                                                       addr);
1986                                 hns3_err(hw, "failed to set mc mac addr, "
1987                                          "addrs invalid. two same addrs(%s).",
1988                                          mac_str);
1989                                 return -EINVAL;
1990                         }
1991                 }
1992
1993                 /*
1994                  * Check if there are duplicate addresses between mac_addrs
1995                  * and mc_addr_set
1996                  */
1997                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1998                         if (rte_is_same_ether_addr(addr,
1999                                                    &hw->data->mac_addrs[j])) {
2000                                 hns3_ether_format_addr(mac_str,
2001                                                       RTE_ETHER_ADDR_FMT_SIZE,
2002                                                       addr);
2003                                 hns3_err(hw, "failed to set mc mac addr, "
2004                                          "addrs invalid. addrs(%s) has already "
2005                                          "configured in mac_addr add API",
2006                                          mac_str);
2007                                 return -EINVAL;
2008                         }
2009                 }
2010         }
2011
2012         return 0;
2013 }
2014
2015 static void
2016 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2017                            struct rte_ether_addr *mc_addr_set,
2018                            int mc_addr_num,
2019                            struct rte_ether_addr *reserved_addr_list,
2020                            int *reserved_addr_num,
2021                            struct rte_ether_addr *add_addr_list,
2022                            int *add_addr_num,
2023                            struct rte_ether_addr *rm_addr_list,
2024                            int *rm_addr_num)
2025 {
2026         struct rte_ether_addr *addr;
2027         int current_addr_num;
2028         int reserved_num = 0;
2029         int add_num = 0;
2030         int rm_num = 0;
2031         int num;
2032         int i;
2033         int j;
2034         bool same_addr;
2035
2036         /* Calculate the mc mac address list that should be removed */
2037         current_addr_num = hw->mc_addrs_num;
2038         for (i = 0; i < current_addr_num; i++) {
2039                 addr = &hw->mc_addrs[i];
2040                 same_addr = false;
2041                 for (j = 0; j < mc_addr_num; j++) {
2042                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2043                                 same_addr = true;
2044                                 break;
2045                         }
2046                 }
2047
2048                 if (!same_addr) {
2049                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2050                         rm_num++;
2051                 } else {
2052                         rte_ether_addr_copy(addr,
2053                                             &reserved_addr_list[reserved_num]);
2054                         reserved_num++;
2055                 }
2056         }
2057
2058         /* Calculate the mc mac address list that should be added */
2059         for (i = 0; i < mc_addr_num; i++) {
2060                 addr = &mc_addr_set[i];
2061                 same_addr = false;
2062                 for (j = 0; j < current_addr_num; j++) {
2063                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2064                                 same_addr = true;
2065                                 break;
2066                         }
2067                 }
2068
2069                 if (!same_addr) {
2070                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2071                         add_num++;
2072                 }
2073         }
2074
2075         /* Reorder the mc mac address list maintained by driver */
2076         for (i = 0; i < reserved_num; i++)
2077                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2078
2079         for (i = 0; i < rm_num; i++) {
2080                 num = reserved_num + i;
2081                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2082         }
2083
2084         *reserved_addr_num = reserved_num;
2085         *add_addr_num = add_num;
2086         *rm_addr_num = rm_num;
2087 }
2088
2089 static int
2090 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2091                           struct rte_ether_addr *mc_addr_set,
2092                           uint32_t nb_mc_addr)
2093 {
2094         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2096         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2097         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2098         struct rte_ether_addr *addr;
2099         int reserved_addr_num;
2100         int add_addr_num;
2101         int rm_addr_num;
2102         int mc_addr_num;
2103         int num;
2104         int ret;
2105         int i;
2106
2107         /* Check if input parameters are valid */
2108         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2109         if (ret)
2110                 return ret;
2111
2112         rte_spinlock_lock(&hw->lock);
2113
2114         /*
2115          * Calculate the mc mac address lists those should be removed and be
2116          * added, Reorder the mc mac address list maintained by driver.
2117          */
2118         mc_addr_num = (int)nb_mc_addr;
2119         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2120                                    reserved_addr_list, &reserved_addr_num,
2121                                    add_addr_list, &add_addr_num,
2122                                    rm_addr_list, &rm_addr_num);
2123
2124         /* Remove mc mac addresses */
2125         for (i = 0; i < rm_addr_num; i++) {
2126                 num = rm_addr_num - i - 1;
2127                 addr = &rm_addr_list[num];
2128                 ret = hns3_remove_mc_addr(hw, addr);
2129                 if (ret) {
2130                         rte_spinlock_unlock(&hw->lock);
2131                         return ret;
2132                 }
2133                 hw->mc_addrs_num--;
2134         }
2135
2136         /* Add mc mac addresses */
2137         for (i = 0; i < add_addr_num; i++) {
2138                 addr = &add_addr_list[i];
2139                 ret = hns3_add_mc_addr(hw, addr);
2140                 if (ret) {
2141                         rte_spinlock_unlock(&hw->lock);
2142                         return ret;
2143                 }
2144
2145                 num = reserved_addr_num + i;
2146                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2147                 hw->mc_addrs_num++;
2148         }
2149         rte_spinlock_unlock(&hw->lock);
2150
2151         return 0;
2152 }
2153
2154 static int
2155 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2156 {
2157         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2158         struct hns3_hw *hw = &hns->hw;
2159         struct rte_ether_addr *addr;
2160         int err = 0;
2161         int ret;
2162         int i;
2163
2164         for (i = 0; i < hw->mc_addrs_num; i++) {
2165                 addr = &hw->mc_addrs[i];
2166                 if (!rte_is_multicast_ether_addr(addr))
2167                         continue;
2168                 if (del)
2169                         ret = hns3_remove_mc_addr(hw, addr);
2170                 else
2171                         ret = hns3_add_mc_addr(hw, addr);
2172                 if (ret) {
2173                         err = ret;
2174                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2175                                               addr);
2176                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2177                                  del ? "Remove" : "Restore", mac_str, ret);
2178                 }
2179         }
2180         return err;
2181 }
2182
2183 static int
2184 hns3_check_mq_mode(struct rte_eth_dev *dev)
2185 {
2186         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2187         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2188         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2190         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2191         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2192         uint8_t num_tc;
2193         int max_tc = 0;
2194         int i;
2195
2196         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2197         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2198
2199         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2200                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2201                          "rx_mq_mode = %d", rx_mq_mode);
2202                 return -EINVAL;
2203         }
2204
2205         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2206             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2207                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2208                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2209                          rx_mq_mode, tx_mq_mode);
2210                 return -EINVAL;
2211         }
2212
2213         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2214                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2215                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2216                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2217                         return -EINVAL;
2218                 }
2219
2220                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2221                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2222                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2223                                  "nb_tcs(%d) != %d or %d in rx direction.",
2224                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2225                         return -EINVAL;
2226                 }
2227
2228                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2229                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2230                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2231                         return -EINVAL;
2232                 }
2233
2234                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2235                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2236                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2237                                          "is not equal to one in tx direction.",
2238                                          i, dcb_rx_conf->dcb_tc[i]);
2239                                 return -EINVAL;
2240                         }
2241                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2242                                 max_tc = dcb_rx_conf->dcb_tc[i];
2243                 }
2244
2245                 num_tc = max_tc + 1;
2246                 if (num_tc > dcb_rx_conf->nb_tcs) {
2247                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2248                                  num_tc, dcb_rx_conf->nb_tcs);
2249                         return -EINVAL;
2250                 }
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int
2257 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2258 {
2259         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260
2261         if (!hns3_dev_dcb_supported(hw)) {
2262                 hns3_err(hw, "this port does not support dcb configurations.");
2263                 return -EOPNOTSUPP;
2264         }
2265
2266         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2267                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2268                 return -EOPNOTSUPP;
2269         }
2270
2271         /* Check multiple queue mode */
2272         return hns3_check_mq_mode(dev);
2273 }
2274
2275 static int
2276 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2277                            enum hns3_ring_type queue_type, uint16_t queue_id)
2278 {
2279         struct hns3_cmd_desc desc;
2280         struct hns3_ctrl_vector_chain_cmd *req =
2281                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2282         enum hns3_cmd_status status;
2283         enum hns3_opcode_type op;
2284         uint16_t tqp_type_and_id = 0;
2285         uint16_t type;
2286         uint16_t gl;
2287
2288         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2289         hns3_cmd_setup_basic_desc(&desc, op, false);
2290         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2291                                               HNS3_TQP_INT_ID_L_S);
2292         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2293                                               HNS3_TQP_INT_ID_H_S);
2294
2295         if (queue_type == HNS3_RING_TYPE_RX)
2296                 gl = HNS3_RING_GL_RX;
2297         else
2298                 gl = HNS3_RING_GL_TX;
2299
2300         type = queue_type;
2301
2302         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2303                        type);
2304         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2305         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2306                        gl);
2307         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2308         req->int_cause_num = 1;
2309         status = hns3_cmd_send(hw, &desc, 1);
2310         if (status) {
2311                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2312                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2313                 return status;
2314         }
2315
2316         return 0;
2317 }
2318
2319 static int
2320 hns3_init_ring_with_vector(struct hns3_hw *hw)
2321 {
2322         uint16_t vec;
2323         int ret;
2324         int i;
2325
2326         /*
2327          * In hns3 network engine, vector 0 is always the misc interrupt of this
2328          * function, vector 1~N can be used respectively for the queues of the
2329          * function. Tx and Rx queues with the same number share the interrupt
2330          * vector. In the initialization clearing the all hardware mapping
2331          * relationship configurations between queues and interrupt vectors is
2332          * needed, so some error caused by the residual configurations, such as
2333          * the unexpected Tx interrupt, can be avoid.
2334          */
2335         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2336         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2337                 vec = vec - 1; /* the last interrupt is reserved */
2338         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2339         for (i = 0; i < hw->intr_tqps_num; i++) {
2340                 /*
2341                  * Set gap limiter/rate limiter/quanity limiter algorithm
2342                  * configuration for interrupt coalesce of queue's interrupt.
2343                  */
2344                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2345                                        HNS3_TQP_INTR_GL_DEFAULT);
2346                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2347                                        HNS3_TQP_INTR_GL_DEFAULT);
2348                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2349                 /*
2350                  * QL(quantity limiter) is not used currently, just set 0 to
2351                  * close it.
2352                  */
2353                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2354
2355                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2356                                                  HNS3_RING_TYPE_TX, i);
2357                 if (ret) {
2358                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2359                                           "vector: %u, ret=%d", i, vec, ret);
2360                         return ret;
2361                 }
2362
2363                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2364                                                  HNS3_RING_TYPE_RX, i);
2365                 if (ret) {
2366                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2367                                           "vector: %u, ret=%d", i, vec, ret);
2368                         return ret;
2369                 }
2370         }
2371
2372         return 0;
2373 }
2374
2375 static int
2376 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2377 {
2378         struct hns3_adapter *hns = dev->data->dev_private;
2379         struct hns3_hw *hw = &hns->hw;
2380         uint32_t max_rx_pkt_len;
2381         uint16_t mtu;
2382         int ret;
2383
2384         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2385                 return 0;
2386
2387         /*
2388          * If jumbo frames are enabled, MTU needs to be refreshed
2389          * according to the maximum RX packet length.
2390          */
2391         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2392         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2393             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2394                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2395                          "and no more than %u when jumbo frame enabled.",
2396                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2397                          (uint16_t)HNS3_MAX_FRAME_LEN);
2398                 return -EINVAL;
2399         }
2400
2401         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2402         ret = hns3_dev_mtu_set(dev, mtu);
2403         if (ret)
2404                 return ret;
2405         dev->data->mtu = mtu;
2406
2407         return 0;
2408 }
2409
2410 static int
2411 hns3_dev_configure(struct rte_eth_dev *dev)
2412 {
2413         struct hns3_adapter *hns = dev->data->dev_private;
2414         struct rte_eth_conf *conf = &dev->data->dev_conf;
2415         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2416         struct hns3_hw *hw = &hns->hw;
2417         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2418         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2419         struct rte_eth_rss_conf rss_conf;
2420         bool gro_en;
2421         int ret;
2422
2423         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2424
2425         /*
2426          * Some versions of hardware network engine does not support
2427          * individually enable/disable/reset the Tx or Rx queue. These devices
2428          * must enable/disable/reset Tx and Rx queues at the same time. When the
2429          * numbers of Tx queues allocated by upper applications are not equal to
2430          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2431          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2432          * work as usual. But these fake queues are imperceptible, and can not
2433          * be used by upper applications.
2434          */
2435         if (!hns3_dev_indep_txrx_supported(hw)) {
2436                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2437                 if (ret) {
2438                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2439                                  ret);
2440                         return ret;
2441                 }
2442         }
2443
2444         hw->adapter_state = HNS3_NIC_CONFIGURING;
2445         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2446                 hns3_err(hw, "setting link speed/duplex not supported");
2447                 ret = -EINVAL;
2448                 goto cfg_err;
2449         }
2450
2451         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2452                 ret = hns3_check_dcb_cfg(dev);
2453                 if (ret)
2454                         goto cfg_err;
2455         }
2456
2457         /* When RSS is not configured, redirect the packet queue 0 */
2458         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2459                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2460                 rss_conf = conf->rx_adv_conf.rss_conf;
2461                 hw->rss_dis_flag = false;
2462                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2463                 if (ret)
2464                         goto cfg_err;
2465         }
2466
2467         ret = hns3_refresh_mtu(dev, conf);
2468         if (ret)
2469                 goto cfg_err;
2470
2471         ret = hns3_dev_configure_vlan(dev);
2472         if (ret)
2473                 goto cfg_err;
2474
2475         /* config hardware GRO */
2476         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2477         ret = hns3_config_gro(hw, gro_en);
2478         if (ret)
2479                 goto cfg_err;
2480
2481         hns->rx_simple_allowed = true;
2482         hns->rx_vec_allowed = true;
2483         hns->tx_simple_allowed = true;
2484         hns->tx_vec_allowed = true;
2485
2486         hns3_init_rx_ptype_tble(dev);
2487         hw->adapter_state = HNS3_NIC_CONFIGURED;
2488
2489         return 0;
2490
2491 cfg_err:
2492         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2493         hw->adapter_state = HNS3_NIC_INITIALIZED;
2494
2495         return ret;
2496 }
2497
2498 static int
2499 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2500 {
2501         struct hns3_config_max_frm_size_cmd *req;
2502         struct hns3_cmd_desc desc;
2503
2504         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2505
2506         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2507         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2508         req->min_frm_size = RTE_ETHER_MIN_LEN;
2509
2510         return hns3_cmd_send(hw, &desc, 1);
2511 }
2512
2513 static int
2514 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2515 {
2516         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2517         uint16_t original_mps = hns->pf.mps;
2518         int err;
2519         int ret;
2520
2521         ret = hns3_set_mac_mtu(hw, mps);
2522         if (ret) {
2523                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2524                 return ret;
2525         }
2526
2527         hns->pf.mps = mps;
2528         ret = hns3_buffer_alloc(hw);
2529         if (ret) {
2530                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2531                 goto rollback;
2532         }
2533
2534         return 0;
2535
2536 rollback:
2537         err = hns3_set_mac_mtu(hw, original_mps);
2538         if (err) {
2539                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2540                 return ret;
2541         }
2542         hns->pf.mps = original_mps;
2543
2544         return ret;
2545 }
2546
2547 static int
2548 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2549 {
2550         struct hns3_adapter *hns = dev->data->dev_private;
2551         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2552         struct hns3_hw *hw = &hns->hw;
2553         bool is_jumbo_frame;
2554         int ret;
2555
2556         if (dev->data->dev_started) {
2557                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2558                          "before configuration", dev->data->port_id);
2559                 return -EBUSY;
2560         }
2561
2562         rte_spinlock_lock(&hw->lock);
2563         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2564         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2565
2566         /*
2567          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2568          * assign to "uint16_t" type variable.
2569          */
2570         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2571         if (ret) {
2572                 rte_spinlock_unlock(&hw->lock);
2573                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2574                          dev->data->port_id, mtu, ret);
2575                 return ret;
2576         }
2577
2578         if (is_jumbo_frame)
2579                 dev->data->dev_conf.rxmode.offloads |=
2580                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2581         else
2582                 dev->data->dev_conf.rxmode.offloads &=
2583                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2584         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2585         rte_spinlock_unlock(&hw->lock);
2586
2587         return 0;
2588 }
2589
2590 int
2591 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2592 {
2593         struct hns3_adapter *hns = eth_dev->data->dev_private;
2594         struct hns3_hw *hw = &hns->hw;
2595         uint16_t queue_num = hw->tqps_num;
2596
2597         /*
2598          * In interrupt mode, 'max_rx_queues' is set based on the number of
2599          * MSI-X interrupt resources of the hardware.
2600          */
2601         if (hw->data->dev_conf.intr_conf.rxq == 1)
2602                 queue_num = hw->intr_tqps_num;
2603
2604         info->max_rx_queues = queue_num;
2605         info->max_tx_queues = hw->tqps_num;
2606         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2607         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2608         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2609         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2610         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2611         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2612                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2613                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2614                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2615                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2616                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2617                                  DEV_RX_OFFLOAD_KEEP_CRC |
2618                                  DEV_RX_OFFLOAD_SCATTER |
2619                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2620                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2621                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2622                                  DEV_RX_OFFLOAD_RSS_HASH |
2623                                  DEV_RX_OFFLOAD_TCP_LRO);
2624         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2625                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2626                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2627                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2628                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2629                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2630                                  DEV_TX_OFFLOAD_TCP_TSO |
2631                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2632                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2633                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2634                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2635                                  hns3_txvlan_cap_get(hw));
2636
2637         if (hns3_dev_outer_udp_cksum_supported(hw))
2638                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2639
2640         if (hns3_dev_indep_txrx_supported(hw))
2641                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2642                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2643
2644         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2645                 .nb_max = HNS3_MAX_RING_DESC,
2646                 .nb_min = HNS3_MIN_RING_DESC,
2647                 .nb_align = HNS3_ALIGN_RING_DESC,
2648         };
2649
2650         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2651                 .nb_max = HNS3_MAX_RING_DESC,
2652                 .nb_min = HNS3_MIN_RING_DESC,
2653                 .nb_align = HNS3_ALIGN_RING_DESC,
2654                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2655                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2656         };
2657
2658         info->default_rxconf = (struct rte_eth_rxconf) {
2659                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2660                 /*
2661                  * If there are no available Rx buffer descriptors, incoming
2662                  * packets are always dropped by hardware based on hns3 network
2663                  * engine.
2664                  */
2665                 .rx_drop_en = 1,
2666                 .offloads = 0,
2667         };
2668         info->default_txconf = (struct rte_eth_txconf) {
2669                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2670                 .offloads = 0,
2671         };
2672
2673         info->vmdq_queue_num = 0;
2674
2675         info->reta_size = hw->rss_ind_tbl_size;
2676         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2677         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2678
2679         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2680         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2681         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2682         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2683         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2684         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2685
2686         return 0;
2687 }
2688
2689 static int
2690 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2691                     size_t fw_size)
2692 {
2693         struct hns3_adapter *hns = eth_dev->data->dev_private;
2694         struct hns3_hw *hw = &hns->hw;
2695         uint32_t version = hw->fw_version;
2696         int ret;
2697
2698         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2699                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2700                                       HNS3_FW_VERSION_BYTE3_S),
2701                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2702                                       HNS3_FW_VERSION_BYTE2_S),
2703                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2704                                       HNS3_FW_VERSION_BYTE1_S),
2705                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2706                                       HNS3_FW_VERSION_BYTE0_S));
2707         ret += 1; /* add the size of '\0' */
2708         if (fw_size < (uint32_t)ret)
2709                 return ret;
2710         else
2711                 return 0;
2712 }
2713
2714 static int
2715 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2716 {
2717         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2718
2719         (void)hns3_update_link_status(hw);
2720
2721         return hns3_update_link_info(eth_dev);
2722 }
2723
2724 static void
2725 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2726                       struct rte_eth_link *new_link)
2727 {
2728         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2729         struct hns3_mac *mac = &hw->mac;
2730
2731         switch (mac->link_speed) {
2732         case ETH_SPEED_NUM_10M:
2733         case ETH_SPEED_NUM_100M:
2734         case ETH_SPEED_NUM_1G:
2735         case ETH_SPEED_NUM_10G:
2736         case ETH_SPEED_NUM_25G:
2737         case ETH_SPEED_NUM_40G:
2738         case ETH_SPEED_NUM_50G:
2739         case ETH_SPEED_NUM_100G:
2740         case ETH_SPEED_NUM_200G:
2741                 new_link->link_speed = mac->link_speed;
2742                 break;
2743         default:
2744                 if (mac->link_status)
2745                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2746                 else
2747                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2748                 break;
2749         }
2750
2751         new_link->link_duplex = mac->link_duplex;
2752         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2753         new_link->link_autoneg =
2754             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2755 }
2756
2757 static int
2758 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2759                      __rte_unused int wait_to_complete)
2760 {
2761         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2762         struct hns3_mac *mac = &hw->mac;
2763         struct rte_eth_link new_link;
2764         int ret;
2765
2766         ret = hns3_update_port_link_info(eth_dev);
2767         if (ret) {
2768                 mac->link_status = ETH_LINK_DOWN;
2769                 hns3_err(hw, "failed to get port link info, ret = %d.", ret);
2770         }
2771
2772         memset(&new_link, 0, sizeof(new_link));
2773         hns3_setup_linkstatus(eth_dev, &new_link);
2774
2775         return rte_eth_linkstatus_set(eth_dev, &new_link);
2776 }
2777
2778 static int
2779 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2780 {
2781         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2782         struct hns3_pf *pf = &hns->pf;
2783
2784         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2785                 return -EINVAL;
2786
2787         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2788
2789         return 0;
2790 }
2791
2792 static int
2793 hns3_query_function_status(struct hns3_hw *hw)
2794 {
2795 #define HNS3_QUERY_MAX_CNT              10
2796 #define HNS3_QUERY_SLEEP_MSCOEND        1
2797         struct hns3_func_status_cmd *req;
2798         struct hns3_cmd_desc desc;
2799         int timeout = 0;
2800         int ret;
2801
2802         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2803         req = (struct hns3_func_status_cmd *)desc.data;
2804
2805         do {
2806                 ret = hns3_cmd_send(hw, &desc, 1);
2807                 if (ret) {
2808                         PMD_INIT_LOG(ERR, "query function status failed %d",
2809                                      ret);
2810                         return ret;
2811                 }
2812
2813                 /* Check pf reset is done */
2814                 if (req->pf_state)
2815                         break;
2816
2817                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2818         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2819
2820         return hns3_parse_func_status(hw, req);
2821 }
2822
2823 static int
2824 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2825 {
2826         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2827         struct hns3_pf *pf = &hns->pf;
2828
2829         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2830                 /*
2831                  * The total_tqps_num obtained from firmware is maximum tqp
2832                  * numbers of this port, which should be used for PF and VFs.
2833                  * There is no need for pf to have so many tqp numbers in
2834                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2835                  * coming from config file, is assigned to maximum queue number
2836                  * for the PF of this port by user. So users can modify the
2837                  * maximum queue number of PF according to their own application
2838                  * scenarios, which is more flexible to use. In addition, many
2839                  * memories can be saved due to allocating queue statistics
2840                  * room according to the actual number of queues required. The
2841                  * maximum queue number of PF for network engine with
2842                  * revision_id greater than 0x30 is assigned by config file.
2843                  */
2844                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2845                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2846                                  "must be greater than 0.",
2847                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2848                         return -EINVAL;
2849                 }
2850
2851                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2852                                        hw->total_tqps_num);
2853         } else {
2854                 /*
2855                  * Due to the limitation on the number of PF interrupts
2856                  * available, the maximum queue number assigned to PF on
2857                  * the network engine with revision_id 0x21 is 64.
2858                  */
2859                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2860                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2861         }
2862
2863         return 0;
2864 }
2865
2866 static int
2867 hns3_query_pf_resource(struct hns3_hw *hw)
2868 {
2869         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2870         struct hns3_pf *pf = &hns->pf;
2871         struct hns3_pf_res_cmd *req;
2872         struct hns3_cmd_desc desc;
2873         int ret;
2874
2875         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2876         ret = hns3_cmd_send(hw, &desc, 1);
2877         if (ret) {
2878                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2879                 return ret;
2880         }
2881
2882         req = (struct hns3_pf_res_cmd *)desc.data;
2883         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2884                              rte_le_to_cpu_16(req->ext_tqp_num);
2885         ret = hns3_get_pf_max_tqp_num(hw);
2886         if (ret)
2887                 return ret;
2888
2889         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2890         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2891
2892         if (req->tx_buf_size)
2893                 pf->tx_buf_size =
2894                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2895         else
2896                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2897
2898         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2899
2900         if (req->dv_buf_size)
2901                 pf->dv_buf_size =
2902                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2903         else
2904                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2905
2906         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2907
2908         hw->num_msi =
2909                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2910                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2911
2912         return 0;
2913 }
2914
2915 static void
2916 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2917 {
2918         struct hns3_cfg_param_cmd *req;
2919         uint64_t mac_addr_tmp_high;
2920         uint8_t ext_rss_size_max;
2921         uint64_t mac_addr_tmp;
2922         uint32_t i;
2923
2924         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2925
2926         /* get the configuration */
2927         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2928                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2929         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2930                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2931         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2932                                            HNS3_CFG_TQP_DESC_N_M,
2933                                            HNS3_CFG_TQP_DESC_N_S);
2934
2935         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2936                                        HNS3_CFG_PHY_ADDR_M,
2937                                        HNS3_CFG_PHY_ADDR_S);
2938         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2939                                          HNS3_CFG_MEDIA_TP_M,
2940                                          HNS3_CFG_MEDIA_TP_S);
2941         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2942                                          HNS3_CFG_RX_BUF_LEN_M,
2943                                          HNS3_CFG_RX_BUF_LEN_S);
2944         /* get mac address */
2945         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2946         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2947                                            HNS3_CFG_MAC_ADDR_H_M,
2948                                            HNS3_CFG_MAC_ADDR_H_S);
2949
2950         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2951
2952         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2953                                             HNS3_CFG_DEFAULT_SPEED_M,
2954                                             HNS3_CFG_DEFAULT_SPEED_S);
2955         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2956                                            HNS3_CFG_RSS_SIZE_M,
2957                                            HNS3_CFG_RSS_SIZE_S);
2958
2959         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2960                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2961
2962         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2963         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2964
2965         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2966                                             HNS3_CFG_SPEED_ABILITY_M,
2967                                             HNS3_CFG_SPEED_ABILITY_S);
2968         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2969                                         HNS3_CFG_UMV_TBL_SPACE_M,
2970                                         HNS3_CFG_UMV_TBL_SPACE_S);
2971         if (!cfg->umv_space)
2972                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2973
2974         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2975                                                HNS3_CFG_EXT_RSS_SIZE_M,
2976                                                HNS3_CFG_EXT_RSS_SIZE_S);
2977
2978         /*
2979          * Field ext_rss_size_max obtained from firmware will be more flexible
2980          * for future changes and expansions, which is an exponent of 2, instead
2981          * of reading out directly. If this field is not zero, hns3 PF PMD
2982          * driver uses it as rss_size_max under one TC. Device, whose revision
2983          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2984          * maximum number of queues supported under a TC through this field.
2985          */
2986         if (ext_rss_size_max)
2987                 cfg->rss_size_max = 1U << ext_rss_size_max;
2988 }
2989
2990 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2991  * @hw: pointer to struct hns3_hw
2992  * @hcfg: the config structure to be getted
2993  */
2994 static int
2995 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2996 {
2997         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2998         struct hns3_cfg_param_cmd *req;
2999         uint32_t offset;
3000         uint32_t i;
3001         int ret;
3002
3003         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3004                 offset = 0;
3005                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3006                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3007                                           true);
3008                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3009                                i * HNS3_CFG_RD_LEN_BYTES);
3010                 /* Len should be divided by 4 when send to hardware */
3011                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3012                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3013                 req->offset = rte_cpu_to_le_32(offset);
3014         }
3015
3016         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3017         if (ret) {
3018                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3019                 return ret;
3020         }
3021
3022         hns3_parse_cfg(hcfg, desc);
3023
3024         return 0;
3025 }
3026
3027 static int
3028 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3029 {
3030         switch (speed_cmd) {
3031         case HNS3_CFG_SPEED_10M:
3032                 *speed = ETH_SPEED_NUM_10M;
3033                 break;
3034         case HNS3_CFG_SPEED_100M:
3035                 *speed = ETH_SPEED_NUM_100M;
3036                 break;
3037         case HNS3_CFG_SPEED_1G:
3038                 *speed = ETH_SPEED_NUM_1G;
3039                 break;
3040         case HNS3_CFG_SPEED_10G:
3041                 *speed = ETH_SPEED_NUM_10G;
3042                 break;
3043         case HNS3_CFG_SPEED_25G:
3044                 *speed = ETH_SPEED_NUM_25G;
3045                 break;
3046         case HNS3_CFG_SPEED_40G:
3047                 *speed = ETH_SPEED_NUM_40G;
3048                 break;
3049         case HNS3_CFG_SPEED_50G:
3050                 *speed = ETH_SPEED_NUM_50G;
3051                 break;
3052         case HNS3_CFG_SPEED_100G:
3053                 *speed = ETH_SPEED_NUM_100G;
3054                 break;
3055         case HNS3_CFG_SPEED_200G:
3056                 *speed = ETH_SPEED_NUM_200G;
3057                 break;
3058         default:
3059                 return -EINVAL;
3060         }
3061
3062         return 0;
3063 }
3064
3065 static void
3066 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3067 {
3068         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3069         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3070         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3071         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3072         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3073 }
3074
3075 static void
3076 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3077 {
3078         struct hns3_dev_specs_0_cmd *req0;
3079
3080         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3081
3082         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3083         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3084         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3085         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3086         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3087 }
3088
3089 static int
3090 hns3_check_dev_specifications(struct hns3_hw *hw)
3091 {
3092         if (hw->rss_ind_tbl_size == 0 ||
3093             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3094                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3095                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3096                               HNS3_RSS_IND_TBL_SIZE_MAX);
3097                 return -EINVAL;
3098         }
3099
3100         return 0;
3101 }
3102
3103 static int
3104 hns3_query_dev_specifications(struct hns3_hw *hw)
3105 {
3106         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3107         int ret;
3108         int i;
3109
3110         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3111                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3112                                           true);
3113                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3114         }
3115         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3116
3117         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3118         if (ret)
3119                 return ret;
3120
3121         hns3_parse_dev_specifications(hw, desc);
3122
3123         return hns3_check_dev_specifications(hw);
3124 }
3125
3126 static int
3127 hns3_get_capability(struct hns3_hw *hw)
3128 {
3129         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3130         struct rte_pci_device *pci_dev;
3131         struct hns3_pf *pf = &hns->pf;
3132         struct rte_eth_dev *eth_dev;
3133         uint16_t device_id;
3134         uint8_t revision;
3135         int ret;
3136
3137         eth_dev = &rte_eth_devices[hw->data->port_id];
3138         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3139         device_id = pci_dev->id.device_id;
3140
3141         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3142             device_id == HNS3_DEV_ID_50GE_RDMA ||
3143             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3144             device_id == HNS3_DEV_ID_200G_RDMA)
3145                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3146
3147         /* Get PCI revision id */
3148         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3149                                   HNS3_PCI_REVISION_ID);
3150         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3151                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3152                              ret);
3153                 return -EIO;
3154         }
3155         hw->revision = revision;
3156
3157         if (revision < PCI_REVISION_ID_HIP09_A) {
3158                 hns3_set_default_dev_specifications(hw);
3159                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3160                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3161                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3162                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3163                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3164                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3165                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3166                 hw->rss_info.ipv6_sctp_offload_supported = false;
3167                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3168                 return 0;
3169         }
3170
3171         ret = hns3_query_dev_specifications(hw);
3172         if (ret) {
3173                 PMD_INIT_LOG(ERR,
3174                              "failed to query dev specifications, ret = %d",
3175                              ret);
3176                 return ret;
3177         }
3178
3179         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3180         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3181         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3182         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3183         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3184         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3185         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3186         hw->rss_info.ipv6_sctp_offload_supported = true;
3187         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3188
3189         return 0;
3190 }
3191
3192 static int
3193 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3194 {
3195         int ret;
3196
3197         switch (media_type) {
3198         case HNS3_MEDIA_TYPE_COPPER:
3199                 if (!hns3_dev_copper_supported(hw)) {
3200                         PMD_INIT_LOG(ERR,
3201                                      "Media type is copper, not supported.");
3202                         ret = -EOPNOTSUPP;
3203                 } else {
3204                         ret = 0;
3205                 }
3206                 break;
3207         case HNS3_MEDIA_TYPE_FIBER:
3208                 ret = 0;
3209                 break;
3210         case HNS3_MEDIA_TYPE_BACKPLANE:
3211                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3212                 ret = -EOPNOTSUPP;
3213                 break;
3214         default:
3215                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3216                 ret = -EINVAL;
3217                 break;
3218         }
3219
3220         return ret;
3221 }
3222
3223 static int
3224 hns3_get_board_configuration(struct hns3_hw *hw)
3225 {
3226         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3227         struct hns3_pf *pf = &hns->pf;
3228         struct hns3_cfg cfg;
3229         int ret;
3230
3231         ret = hns3_get_board_cfg(hw, &cfg);
3232         if (ret) {
3233                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3234                 return ret;
3235         }
3236
3237         ret = hns3_check_media_type(hw, cfg.media_type);
3238         if (ret)
3239                 return ret;
3240
3241         hw->mac.media_type = cfg.media_type;
3242         hw->rss_size_max = cfg.rss_size_max;
3243         hw->rss_dis_flag = false;
3244         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3245         hw->mac.phy_addr = cfg.phy_addr;
3246         hw->mac.default_addr_setted = false;
3247         hw->num_tx_desc = cfg.tqp_desc_num;
3248         hw->num_rx_desc = cfg.tqp_desc_num;
3249         hw->dcb_info.num_pg = 1;
3250         hw->dcb_info.hw_pfc_map = 0;
3251
3252         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3253         if (ret) {
3254                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3255                              cfg.default_speed, ret);
3256                 return ret;
3257         }
3258
3259         pf->tc_max = cfg.tc_num;
3260         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3261                 PMD_INIT_LOG(WARNING,
3262                              "Get TC num(%u) from flash, set TC num to 1",
3263                              pf->tc_max);
3264                 pf->tc_max = 1;
3265         }
3266
3267         /* Dev does not support DCB */
3268         if (!hns3_dev_dcb_supported(hw)) {
3269                 pf->tc_max = 1;
3270                 pf->pfc_max = 0;
3271         } else
3272                 pf->pfc_max = pf->tc_max;
3273
3274         hw->dcb_info.num_tc = 1;
3275         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3276                                      hw->tqps_num / hw->dcb_info.num_tc);
3277         hns3_set_bit(hw->hw_tc_map, 0, 1);
3278         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3279
3280         pf->wanted_umv_size = cfg.umv_space;
3281
3282         return ret;
3283 }
3284
3285 static int
3286 hns3_get_configuration(struct hns3_hw *hw)
3287 {
3288         int ret;
3289
3290         ret = hns3_query_function_status(hw);
3291         if (ret) {
3292                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3293                 return ret;
3294         }
3295
3296         /* Get device capability */
3297         ret = hns3_get_capability(hw);
3298         if (ret) {
3299                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3300                 return ret;
3301         }
3302
3303         /* Get pf resource */
3304         ret = hns3_query_pf_resource(hw);
3305         if (ret) {
3306                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3307                 return ret;
3308         }
3309
3310         ret = hns3_get_board_configuration(hw);
3311         if (ret) {
3312                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3313                 return ret;
3314         }
3315
3316         ret = hns3_query_dev_fec_info(hw);
3317         if (ret)
3318                 PMD_INIT_LOG(ERR,
3319                              "failed to query FEC information, ret = %d", ret);
3320
3321         return ret;
3322 }
3323
3324 static int
3325 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3326                       uint16_t tqp_vid, bool is_pf)
3327 {
3328         struct hns3_tqp_map_cmd *req;
3329         struct hns3_cmd_desc desc;
3330         int ret;
3331
3332         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3333
3334         req = (struct hns3_tqp_map_cmd *)desc.data;
3335         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3336         req->tqp_vf = func_id;
3337         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3338         if (!is_pf)
3339                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3340         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3341
3342         ret = hns3_cmd_send(hw, &desc, 1);
3343         if (ret)
3344                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3345
3346         return ret;
3347 }
3348
3349 static int
3350 hns3_map_tqp(struct hns3_hw *hw)
3351 {
3352         int ret;
3353         int i;
3354
3355         /*
3356          * In current version, VF is not supported when PF is driven by DPDK
3357          * driver, so we assign total tqps_num tqps allocated to this port
3358          * to PF.
3359          */
3360         for (i = 0; i < hw->total_tqps_num; i++) {
3361                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3362                 if (ret)
3363                         return ret;
3364         }
3365
3366         return 0;
3367 }
3368
3369 static int
3370 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3371 {
3372         struct hns3_config_mac_speed_dup_cmd *req;
3373         struct hns3_cmd_desc desc;
3374         int ret;
3375
3376         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3377
3378         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3379
3380         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3381
3382         switch (speed) {
3383         case ETH_SPEED_NUM_10M:
3384                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3385                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3386                 break;
3387         case ETH_SPEED_NUM_100M:
3388                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3389                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3390                 break;
3391         case ETH_SPEED_NUM_1G:
3392                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3393                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3394                 break;
3395         case ETH_SPEED_NUM_10G:
3396                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3397                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3398                 break;
3399         case ETH_SPEED_NUM_25G:
3400                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3401                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3402                 break;
3403         case ETH_SPEED_NUM_40G:
3404                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3405                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3406                 break;
3407         case ETH_SPEED_NUM_50G:
3408                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3409                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3410                 break;
3411         case ETH_SPEED_NUM_100G:
3412                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3413                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3414                 break;
3415         case ETH_SPEED_NUM_200G:
3416                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3417                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3418                 break;
3419         default:
3420                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3421                 return -EINVAL;
3422         }
3423
3424         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3425
3426         ret = hns3_cmd_send(hw, &desc, 1);
3427         if (ret)
3428                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3429
3430         return ret;
3431 }
3432
3433 static int
3434 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3435 {
3436         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3437         struct hns3_pf *pf = &hns->pf;
3438         struct hns3_priv_buf *priv;
3439         uint32_t i, total_size;
3440
3441         total_size = pf->pkt_buf_size;
3442
3443         /* alloc tx buffer for all enabled tc */
3444         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3445                 priv = &buf_alloc->priv_buf[i];
3446
3447                 if (hw->hw_tc_map & BIT(i)) {
3448                         if (total_size < pf->tx_buf_size)
3449                                 return -ENOMEM;
3450
3451                         priv->tx_buf_size = pf->tx_buf_size;
3452                 } else
3453                         priv->tx_buf_size = 0;
3454
3455                 total_size -= priv->tx_buf_size;
3456         }
3457
3458         return 0;
3459 }
3460
3461 static int
3462 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3463 {
3464 /* TX buffer size is unit by 128 byte */
3465 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3466 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3467         struct hns3_tx_buff_alloc_cmd *req;
3468         struct hns3_cmd_desc desc;
3469         uint32_t buf_size;
3470         uint32_t i;
3471         int ret;
3472
3473         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3474
3475         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3476         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3477                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3478
3479                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3480                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3481                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3482         }
3483
3484         ret = hns3_cmd_send(hw, &desc, 1);
3485         if (ret)
3486                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3487
3488         return ret;
3489 }
3490
3491 static int
3492 hns3_get_tc_num(struct hns3_hw *hw)
3493 {
3494         int cnt = 0;
3495         uint8_t i;
3496
3497         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3498                 if (hw->hw_tc_map & BIT(i))
3499                         cnt++;
3500         return cnt;
3501 }
3502
3503 static uint32_t
3504 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3505 {
3506         struct hns3_priv_buf *priv;
3507         uint32_t rx_priv = 0;
3508         int i;
3509
3510         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3511                 priv = &buf_alloc->priv_buf[i];
3512                 if (priv->enable)
3513                         rx_priv += priv->buf_size;
3514         }
3515         return rx_priv;
3516 }
3517
3518 static uint32_t
3519 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3520 {
3521         uint32_t total_tx_size = 0;
3522         uint32_t i;
3523
3524         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3525                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3526
3527         return total_tx_size;
3528 }
3529
3530 /* Get the number of pfc enabled TCs, which have private buffer */
3531 static int
3532 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3533 {
3534         struct hns3_priv_buf *priv;
3535         int cnt = 0;
3536         uint8_t i;
3537
3538         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3539                 priv = &buf_alloc->priv_buf[i];
3540                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3541                         cnt++;
3542         }
3543
3544         return cnt;
3545 }
3546
3547 /* Get the number of pfc disabled TCs, which have private buffer */
3548 static int
3549 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3550                          struct hns3_pkt_buf_alloc *buf_alloc)
3551 {
3552         struct hns3_priv_buf *priv;
3553         int cnt = 0;
3554         uint8_t i;
3555
3556         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3557                 priv = &buf_alloc->priv_buf[i];
3558                 if (hw->hw_tc_map & BIT(i) &&
3559                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3560                         cnt++;
3561         }
3562
3563         return cnt;
3564 }
3565
3566 static bool
3567 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3568                   uint32_t rx_all)
3569 {
3570         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3571         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3572         struct hns3_pf *pf = &hns->pf;
3573         uint32_t shared_buf, aligned_mps;
3574         uint32_t rx_priv;
3575         uint8_t tc_num;
3576         uint8_t i;
3577
3578         tc_num = hns3_get_tc_num(hw);
3579         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3580
3581         if (hns3_dev_dcb_supported(hw))
3582                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3583                                         pf->dv_buf_size;
3584         else
3585                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3586                                         + pf->dv_buf_size;
3587
3588         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3589         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3590                              HNS3_BUF_SIZE_UNIT);
3591
3592         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3593         if (rx_all < rx_priv + shared_std)
3594                 return false;
3595
3596         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3597         buf_alloc->s_buf.buf_size = shared_buf;
3598         if (hns3_dev_dcb_supported(hw)) {
3599                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3600                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3601                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3602                                   HNS3_BUF_SIZE_UNIT);
3603         } else {
3604                 buf_alloc->s_buf.self.high =
3605                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3606                 buf_alloc->s_buf.self.low = aligned_mps;
3607         }
3608
3609         if (hns3_dev_dcb_supported(hw)) {
3610                 hi_thrd = shared_buf - pf->dv_buf_size;
3611
3612                 if (tc_num <= NEED_RESERVE_TC_NUM)
3613                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3614                                   BUF_MAX_PERCENT;
3615
3616                 if (tc_num)
3617                         hi_thrd = hi_thrd / tc_num;
3618
3619                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3620                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3621                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3622         } else {
3623                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3624                 lo_thrd = aligned_mps;
3625         }
3626
3627         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3628                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3629                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3630         }
3631
3632         return true;
3633 }
3634
3635 static bool
3636 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3637                      struct hns3_pkt_buf_alloc *buf_alloc)
3638 {
3639         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3640         struct hns3_pf *pf = &hns->pf;
3641         struct hns3_priv_buf *priv;
3642         uint32_t aligned_mps;
3643         uint32_t rx_all;
3644         uint8_t i;
3645
3646         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3647         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3648
3649         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3650                 priv = &buf_alloc->priv_buf[i];
3651
3652                 priv->enable = 0;
3653                 priv->wl.low = 0;
3654                 priv->wl.high = 0;
3655                 priv->buf_size = 0;
3656
3657                 if (!(hw->hw_tc_map & BIT(i)))
3658                         continue;
3659
3660                 priv->enable = 1;
3661                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3662                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3663                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3664                                                 HNS3_BUF_SIZE_UNIT);
3665                 } else {
3666                         priv->wl.low = 0;
3667                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3668                                         aligned_mps;
3669                 }
3670
3671                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3672         }
3673
3674         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3675 }
3676
3677 static bool
3678 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3679                              struct hns3_pkt_buf_alloc *buf_alloc)
3680 {
3681         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3682         struct hns3_pf *pf = &hns->pf;
3683         struct hns3_priv_buf *priv;
3684         int no_pfc_priv_num;
3685         uint32_t rx_all;
3686         uint8_t mask;
3687         int i;
3688
3689         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3690         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3691
3692         /* let the last to be cleared first */
3693         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3694                 priv = &buf_alloc->priv_buf[i];
3695                 mask = BIT((uint8_t)i);
3696
3697                 if (hw->hw_tc_map & mask &&
3698                     !(hw->dcb_info.hw_pfc_map & mask)) {
3699                         /* Clear the no pfc TC private buffer */
3700                         priv->wl.low = 0;
3701                         priv->wl.high = 0;
3702                         priv->buf_size = 0;
3703                         priv->enable = 0;
3704                         no_pfc_priv_num--;
3705                 }
3706
3707                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3708                     no_pfc_priv_num == 0)
3709                         break;
3710         }
3711
3712         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3713 }
3714
3715 static bool
3716 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3717                            struct hns3_pkt_buf_alloc *buf_alloc)
3718 {
3719         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3720         struct hns3_pf *pf = &hns->pf;
3721         struct hns3_priv_buf *priv;
3722         uint32_t rx_all;
3723         int pfc_priv_num;
3724         uint8_t mask;
3725         int i;
3726
3727         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3728         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3729
3730         /* let the last to be cleared first */
3731         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3732                 priv = &buf_alloc->priv_buf[i];
3733                 mask = BIT((uint8_t)i);
3734                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3735                         /* Reduce the number of pfc TC with private buffer */
3736                         priv->wl.low = 0;
3737                         priv->enable = 0;
3738                         priv->wl.high = 0;
3739                         priv->buf_size = 0;
3740                         pfc_priv_num--;
3741                 }
3742                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3743                     pfc_priv_num == 0)
3744                         break;
3745         }
3746
3747         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3748 }
3749
3750 static bool
3751 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3752                           struct hns3_pkt_buf_alloc *buf_alloc)
3753 {
3754 #define COMPENSATE_BUFFER       0x3C00
3755 #define COMPENSATE_HALF_MPS_NUM 5
3756 #define PRIV_WL_GAP             0x1800
3757         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3758         struct hns3_pf *pf = &hns->pf;
3759         uint32_t tc_num = hns3_get_tc_num(hw);
3760         uint32_t half_mps = pf->mps >> 1;
3761         struct hns3_priv_buf *priv;
3762         uint32_t min_rx_priv;
3763         uint32_t rx_priv;
3764         uint8_t i;
3765
3766         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3767         if (tc_num)
3768                 rx_priv = rx_priv / tc_num;
3769
3770         if (tc_num <= NEED_RESERVE_TC_NUM)
3771                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3772
3773         /*
3774          * Minimum value of private buffer in rx direction (min_rx_priv) is
3775          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3776          * buffer if rx_priv is greater than min_rx_priv.
3777          */
3778         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3779                         COMPENSATE_HALF_MPS_NUM * half_mps;
3780         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3781         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3782
3783         if (rx_priv < min_rx_priv)
3784                 return false;
3785
3786         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3787                 priv = &buf_alloc->priv_buf[i];
3788                 priv->enable = 0;
3789                 priv->wl.low = 0;
3790                 priv->wl.high = 0;
3791                 priv->buf_size = 0;
3792
3793                 if (!(hw->hw_tc_map & BIT(i)))
3794                         continue;
3795
3796                 priv->enable = 1;
3797                 priv->buf_size = rx_priv;
3798                 priv->wl.high = rx_priv - pf->dv_buf_size;
3799                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3800         }
3801
3802         buf_alloc->s_buf.buf_size = 0;
3803
3804         return true;
3805 }
3806
3807 /*
3808  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3809  * @hw: pointer to struct hns3_hw
3810  * @buf_alloc: pointer to buffer calculation data
3811  * @return: 0: calculate sucessful, negative: fail
3812  */
3813 static int
3814 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3815 {
3816         /* When DCB is not supported, rx private buffer is not allocated. */
3817         if (!hns3_dev_dcb_supported(hw)) {
3818                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3819                 struct hns3_pf *pf = &hns->pf;
3820                 uint32_t rx_all = pf->pkt_buf_size;
3821
3822                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3823                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3824                         return -ENOMEM;
3825
3826                 return 0;
3827         }
3828
3829         /*
3830          * Try to allocate privated packet buffer for all TCs without share
3831          * buffer.
3832          */
3833         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3834                 return 0;
3835
3836         /*
3837          * Try to allocate privated packet buffer for all TCs with share
3838          * buffer.
3839          */
3840         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3841                 return 0;
3842
3843         /*
3844          * For different application scenes, the enabled port number, TC number
3845          * and no_drop TC number are different. In order to obtain the better
3846          * performance, software could allocate the buffer size and configure
3847          * the waterline by tring to decrease the private buffer size according
3848          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3849          * enabled tc.
3850          */
3851         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3852                 return 0;
3853
3854         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3855                 return 0;
3856
3857         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3858                 return 0;
3859
3860         return -ENOMEM;
3861 }
3862
3863 static int
3864 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3865 {
3866         struct hns3_rx_priv_buff_cmd *req;
3867         struct hns3_cmd_desc desc;
3868         uint32_t buf_size;
3869         int ret;
3870         int i;
3871
3872         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3873         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3874
3875         /* Alloc private buffer TCs */
3876         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3877                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3878
3879                 req->buf_num[i] =
3880                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3881                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3882         }
3883
3884         buf_size = buf_alloc->s_buf.buf_size;
3885         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3886                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3887
3888         ret = hns3_cmd_send(hw, &desc, 1);
3889         if (ret)
3890                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3891
3892         return ret;
3893 }
3894
3895 static int
3896 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3897 {
3898 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3899         struct hns3_rx_priv_wl_buf *req;
3900         struct hns3_priv_buf *priv;
3901         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3902         int i, j;
3903         int ret;
3904
3905         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3906                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3907                                           false);
3908                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3909
3910                 /* The first descriptor set the NEXT bit to 1 */
3911                 if (i == 0)
3912                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3913                 else
3914                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3915
3916                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3917                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3918
3919                         priv = &buf_alloc->priv_buf[idx];
3920                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3921                                                         HNS3_BUF_UNIT_S);
3922                         req->tc_wl[j].high |=
3923                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3924                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3925                                                         HNS3_BUF_UNIT_S);
3926                         req->tc_wl[j].low |=
3927                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3928                 }
3929         }
3930
3931         /* Send 2 descriptor at one time */
3932         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3933         if (ret)
3934                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3935                              ret);
3936         return ret;
3937 }
3938
3939 static int
3940 hns3_common_thrd_config(struct hns3_hw *hw,
3941                         struct hns3_pkt_buf_alloc *buf_alloc)
3942 {
3943 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3944         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3945         struct hns3_rx_com_thrd *req;
3946         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3947         struct hns3_tc_thrd *tc;
3948         int tc_idx;
3949         int i, j;
3950         int ret;
3951
3952         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3953                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3954                                           false);
3955                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3956
3957                 /* The first descriptor set the NEXT bit to 1 */
3958                 if (i == 0)
3959                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3960                 else
3961                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3962
3963                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3964                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3965                         tc = &s_buf->tc_thrd[tc_idx];
3966
3967                         req->com_thrd[j].high =
3968                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3969                         req->com_thrd[j].high |=
3970                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3971                         req->com_thrd[j].low =
3972                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3973                         req->com_thrd[j].low |=
3974                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3975                 }
3976         }
3977
3978         /* Send 2 descriptors at one time */
3979         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3980         if (ret)
3981                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3982
3983         return ret;
3984 }
3985
3986 static int
3987 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3988 {
3989         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3990         struct hns3_rx_com_wl *req;
3991         struct hns3_cmd_desc desc;
3992         int ret;
3993
3994         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3995
3996         req = (struct hns3_rx_com_wl *)desc.data;
3997         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3998         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3999
4000         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4001         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4002
4003         ret = hns3_cmd_send(hw, &desc, 1);
4004         if (ret)
4005                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4006
4007         return ret;
4008 }
4009
4010 int
4011 hns3_buffer_alloc(struct hns3_hw *hw)
4012 {
4013         struct hns3_pkt_buf_alloc pkt_buf;
4014         int ret;
4015
4016         memset(&pkt_buf, 0, sizeof(pkt_buf));
4017         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4018         if (ret) {
4019                 PMD_INIT_LOG(ERR,
4020                              "could not calc tx buffer size for all TCs %d",
4021                              ret);
4022                 return ret;
4023         }
4024
4025         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4026         if (ret) {
4027                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4028                 return ret;
4029         }
4030
4031         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4032         if (ret) {
4033                 PMD_INIT_LOG(ERR,
4034                              "could not calc rx priv buffer size for all TCs %d",
4035                              ret);
4036                 return ret;
4037         }
4038
4039         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4040         if (ret) {
4041                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4042                 return ret;
4043         }
4044
4045         if (hns3_dev_dcb_supported(hw)) {
4046                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4047                 if (ret) {
4048                         PMD_INIT_LOG(ERR,
4049                                      "could not configure rx private waterline %d",
4050                                      ret);
4051                         return ret;
4052                 }
4053
4054                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4055                 if (ret) {
4056                         PMD_INIT_LOG(ERR,
4057                                      "could not configure common threshold %d",
4058                                      ret);
4059                         return ret;
4060                 }
4061         }
4062
4063         ret = hns3_common_wl_config(hw, &pkt_buf);
4064         if (ret)
4065                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4066                              ret);
4067
4068         return ret;
4069 }
4070
4071 static int
4072 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
4073 {
4074         struct hns3_firmware_compat_cmd *req;
4075         struct hns3_cmd_desc desc;
4076         uint32_t compat = 0;
4077
4078         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
4079         req = (struct hns3_firmware_compat_cmd *)desc.data;
4080
4081         if (is_init) {
4082                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4083                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4084                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4085                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4086         }
4087
4088         req->compat = rte_cpu_to_le_32(compat);
4089
4090         return hns3_cmd_send(hw, &desc, 1);
4091 }
4092
4093 static int
4094 hns3_mac_init(struct hns3_hw *hw)
4095 {
4096         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4097         struct hns3_mac *mac = &hw->mac;
4098         struct hns3_pf *pf = &hns->pf;
4099         int ret;
4100
4101         pf->support_sfp_query = true;
4102         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4103         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4104         if (ret) {
4105                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4106                 return ret;
4107         }
4108
4109         mac->link_status = ETH_LINK_DOWN;
4110
4111         return hns3_config_mtu(hw, pf->mps);
4112 }
4113
4114 static int
4115 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4116 {
4117 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4118 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4119 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4120 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4121         int return_status;
4122
4123         if (cmdq_resp) {
4124                 PMD_INIT_LOG(ERR,
4125                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4126                              cmdq_resp);
4127                 return -EIO;
4128         }
4129
4130         switch (resp_code) {
4131         case HNS3_ETHERTYPE_SUCCESS_ADD:
4132         case HNS3_ETHERTYPE_ALREADY_ADD:
4133                 return_status = 0;
4134                 break;
4135         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4136                 PMD_INIT_LOG(ERR,
4137                              "add mac ethertype failed for manager table overflow.");
4138                 return_status = -EIO;
4139                 break;
4140         case HNS3_ETHERTYPE_KEY_CONFLICT:
4141                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4142                 return_status = -EIO;
4143                 break;
4144         default:
4145                 PMD_INIT_LOG(ERR,
4146                              "add mac ethertype failed for undefined, code=%u.",
4147                              resp_code);
4148                 return_status = -EIO;
4149                 break;
4150         }
4151
4152         return return_status;
4153 }
4154
4155 static int
4156 hns3_add_mgr_tbl(struct hns3_hw *hw,
4157                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4158 {
4159         struct hns3_cmd_desc desc;
4160         uint8_t resp_code;
4161         uint16_t retval;
4162         int ret;
4163
4164         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4165         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4166
4167         ret = hns3_cmd_send(hw, &desc, 1);
4168         if (ret) {
4169                 PMD_INIT_LOG(ERR,
4170                              "add mac ethertype failed for cmd_send, ret =%d.",
4171                              ret);
4172                 return ret;
4173         }
4174
4175         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4176         retval = rte_le_to_cpu_16(desc.retval);
4177
4178         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4179 }
4180
4181 static void
4182 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4183                      int *table_item_num)
4184 {
4185         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4186
4187         /*
4188          * In current version, we add one item in management table as below:
4189          * 0x0180C200000E -- LLDP MC address
4190          */
4191         tbl = mgr_table;
4192         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4193         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4194         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4195         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4196         tbl->i_port_bitmap = 0x1;
4197         *table_item_num = 1;
4198 }
4199
4200 static int
4201 hns3_init_mgr_tbl(struct hns3_hw *hw)
4202 {
4203 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4204         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4205         int table_item_num;
4206         int ret;
4207         int i;
4208
4209         memset(mgr_table, 0, sizeof(mgr_table));
4210         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4211         for (i = 0; i < table_item_num; i++) {
4212                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4213                 if (ret) {
4214                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4215                                      ret);
4216                         return ret;
4217                 }
4218         }
4219
4220         return 0;
4221 }
4222
4223 static void
4224 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4225                         bool en_mc, bool en_bc, int vport_id)
4226 {
4227         if (!param)
4228                 return;
4229
4230         memset(param, 0, sizeof(struct hns3_promisc_param));
4231         if (en_uc)
4232                 param->enable = HNS3_PROMISC_EN_UC;
4233         if (en_mc)
4234                 param->enable |= HNS3_PROMISC_EN_MC;
4235         if (en_bc)
4236                 param->enable |= HNS3_PROMISC_EN_BC;
4237         param->vf_id = vport_id;
4238 }
4239
4240 static int
4241 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4242 {
4243         struct hns3_promisc_cfg_cmd *req;
4244         struct hns3_cmd_desc desc;
4245         int ret;
4246
4247         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4248
4249         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4250         req->vf_id = param->vf_id;
4251         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4252             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4253
4254         ret = hns3_cmd_send(hw, &desc, 1);
4255         if (ret)
4256                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4257
4258         return ret;
4259 }
4260
4261 static int
4262 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4263 {
4264         struct hns3_promisc_param param;
4265         bool en_bc_pmc = true;
4266         uint8_t vf_id;
4267
4268         /*
4269          * In current version VF is not supported when PF is driven by DPDK
4270          * driver, just need to configure parameters for PF vport.
4271          */
4272         vf_id = HNS3_PF_FUNC_ID;
4273
4274         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4275         return hns3_cmd_set_promisc_mode(hw, &param);
4276 }
4277
4278 static int
4279 hns3_promisc_init(struct hns3_hw *hw)
4280 {
4281         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4282         struct hns3_pf *pf = &hns->pf;
4283         struct hns3_promisc_param param;
4284         uint16_t func_id;
4285         int ret;
4286
4287         ret = hns3_set_promisc_mode(hw, false, false);
4288         if (ret) {
4289                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4290                 return ret;
4291         }
4292
4293         /*
4294          * In current version VFs are not supported when PF is driven by DPDK
4295          * driver. After PF has been taken over by DPDK, the original VF will
4296          * be invalid. So, there is a possibility of entry residues. It should
4297          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4298          * during init.
4299          */
4300         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4301                 hns3_promisc_param_init(&param, false, false, false, func_id);
4302                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4303                 if (ret) {
4304                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4305                                         " ret = %d", func_id, ret);
4306                         return ret;
4307                 }
4308         }
4309
4310         return 0;
4311 }
4312
4313 static void
4314 hns3_promisc_uninit(struct hns3_hw *hw)
4315 {
4316         struct hns3_promisc_param param;
4317         uint16_t func_id;
4318         int ret;
4319
4320         func_id = HNS3_PF_FUNC_ID;
4321
4322         /*
4323          * In current version VFs are not supported when PF is driven by
4324          * DPDK driver, and VFs' promisc mode status has been cleared during
4325          * init and their status will not change. So just clear PF's promisc
4326          * mode status during uninit.
4327          */
4328         hns3_promisc_param_init(&param, false, false, false, func_id);
4329         ret = hns3_cmd_set_promisc_mode(hw, &param);
4330         if (ret)
4331                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4332                                 " uninit, ret = %d", ret);
4333 }
4334
4335 static int
4336 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4337 {
4338         bool allmulti = dev->data->all_multicast ? true : false;
4339         struct hns3_adapter *hns = dev->data->dev_private;
4340         struct hns3_hw *hw = &hns->hw;
4341         uint64_t offloads;
4342         int err;
4343         int ret;
4344
4345         rte_spinlock_lock(&hw->lock);
4346         ret = hns3_set_promisc_mode(hw, true, true);
4347         if (ret) {
4348                 rte_spinlock_unlock(&hw->lock);
4349                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4350                          ret);
4351                 return ret;
4352         }
4353
4354         /*
4355          * When promiscuous mode was enabled, disable the vlan filter to let
4356          * all packets coming in in the receiving direction.
4357          */
4358         offloads = dev->data->dev_conf.rxmode.offloads;
4359         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4360                 ret = hns3_enable_vlan_filter(hns, false);
4361                 if (ret) {
4362                         hns3_err(hw, "failed to enable promiscuous mode due to "
4363                                      "failure to disable vlan filter, ret = %d",
4364                                  ret);
4365                         err = hns3_set_promisc_mode(hw, false, allmulti);
4366                         if (err)
4367                                 hns3_err(hw, "failed to restore promiscuous "
4368                                          "status after disable vlan filter "
4369                                          "failed during enabling promiscuous "
4370                                          "mode, ret = %d", ret);
4371                 }
4372         }
4373
4374         rte_spinlock_unlock(&hw->lock);
4375
4376         return ret;
4377 }
4378
4379 static int
4380 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4381 {
4382         bool allmulti = dev->data->all_multicast ? true : false;
4383         struct hns3_adapter *hns = dev->data->dev_private;
4384         struct hns3_hw *hw = &hns->hw;
4385         uint64_t offloads;
4386         int err;
4387         int ret;
4388
4389         /* If now in all_multicast mode, must remain in all_multicast mode. */
4390         rte_spinlock_lock(&hw->lock);
4391         ret = hns3_set_promisc_mode(hw, false, allmulti);
4392         if (ret) {
4393                 rte_spinlock_unlock(&hw->lock);
4394                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4395                          ret);
4396                 return ret;
4397         }
4398         /* when promiscuous mode was disabled, restore the vlan filter status */
4399         offloads = dev->data->dev_conf.rxmode.offloads;
4400         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4401                 ret = hns3_enable_vlan_filter(hns, true);
4402                 if (ret) {
4403                         hns3_err(hw, "failed to disable promiscuous mode due to"
4404                                  " failure to restore vlan filter, ret = %d",
4405                                  ret);
4406                         err = hns3_set_promisc_mode(hw, true, true);
4407                         if (err)
4408                                 hns3_err(hw, "failed to restore promiscuous "
4409                                          "status after enabling vlan filter "
4410                                          "failed during disabling promiscuous "
4411                                          "mode, ret = %d", ret);
4412                 }
4413         }
4414         rte_spinlock_unlock(&hw->lock);
4415
4416         return ret;
4417 }
4418
4419 static int
4420 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4421 {
4422         struct hns3_adapter *hns = dev->data->dev_private;
4423         struct hns3_hw *hw = &hns->hw;
4424         int ret;
4425
4426         if (dev->data->promiscuous)
4427                 return 0;
4428
4429         rte_spinlock_lock(&hw->lock);
4430         ret = hns3_set_promisc_mode(hw, false, true);
4431         rte_spinlock_unlock(&hw->lock);
4432         if (ret)
4433                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4434                          ret);
4435
4436         return ret;
4437 }
4438
4439 static int
4440 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4441 {
4442         struct hns3_adapter *hns = dev->data->dev_private;
4443         struct hns3_hw *hw = &hns->hw;
4444         int ret;
4445
4446         /* If now in promiscuous mode, must remain in all_multicast mode. */
4447         if (dev->data->promiscuous)
4448                 return 0;
4449
4450         rte_spinlock_lock(&hw->lock);
4451         ret = hns3_set_promisc_mode(hw, false, false);
4452         rte_spinlock_unlock(&hw->lock);
4453         if (ret)
4454                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4455                          ret);
4456
4457         return ret;
4458 }
4459
4460 static int
4461 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4462 {
4463         struct hns3_hw *hw = &hns->hw;
4464         bool allmulti = hw->data->all_multicast ? true : false;
4465         int ret;
4466
4467         if (hw->data->promiscuous) {
4468                 ret = hns3_set_promisc_mode(hw, true, true);
4469                 if (ret)
4470                         hns3_err(hw, "failed to restore promiscuous mode, "
4471                                  "ret = %d", ret);
4472                 return ret;
4473         }
4474
4475         ret = hns3_set_promisc_mode(hw, false, allmulti);
4476         if (ret)
4477                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4478                          ret);
4479         return ret;
4480 }
4481
4482 static int
4483 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4484 {
4485         struct hns3_sfp_speed_cmd *resp;
4486         struct hns3_cmd_desc desc;
4487         int ret;
4488
4489         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4490         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4491         ret = hns3_cmd_send(hw, &desc, 1);
4492         if (ret == -EOPNOTSUPP) {
4493                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4494                 return ret;
4495         } else if (ret) {
4496                 hns3_err(hw, "get sfp speed failed %d", ret);
4497                 return ret;
4498         }
4499
4500         *speed = resp->sfp_speed;
4501
4502         return 0;
4503 }
4504
4505 static uint8_t
4506 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4507 {
4508         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4509                 duplex = ETH_LINK_FULL_DUPLEX;
4510
4511         return duplex;
4512 }
4513
4514 static int
4515 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4516 {
4517         struct hns3_mac *mac = &hw->mac;
4518         int ret;
4519
4520         duplex = hns3_check_speed_dup(duplex, speed);
4521         if (mac->link_speed == speed && mac->link_duplex == duplex)
4522                 return 0;
4523
4524         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4525         if (ret)
4526                 return ret;
4527
4528         ret = hns3_port_shaper_update(hw, speed);
4529         if (ret)
4530                 return ret;
4531
4532         mac->link_speed = speed;
4533         mac->link_duplex = duplex;
4534
4535         return 0;
4536 }
4537
4538 static int
4539 hns3_update_fiber_link_info(struct hns3_hw *hw)
4540 {
4541         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4542         uint32_t speed;
4543         int ret;
4544
4545         /* If IMP do not support get SFP/qSFP speed, return directly */
4546         if (!pf->support_sfp_query)
4547                 return 0;
4548
4549         ret = hns3_get_sfp_speed(hw, &speed);
4550         if (ret == -EOPNOTSUPP) {
4551                 pf->support_sfp_query = false;
4552                 return ret;
4553         } else if (ret)
4554                 return ret;
4555
4556         if (speed == ETH_SPEED_NUM_NONE)
4557                 return 0; /* do nothing if no SFP */
4558
4559         /* Config full duplex for SFP */
4560         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4561 }
4562
4563 static void
4564 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4565 {
4566         struct hns3_phy_params_bd0_cmd *req;
4567
4568         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4569         mac->link_speed = rte_le_to_cpu_32(req->speed);
4570         mac->link_duplex = hns3_get_bit(req->duplex,
4571                                            HNS3_PHY_DUPLEX_CFG_B);
4572         mac->link_autoneg = hns3_get_bit(req->autoneg,
4573                                            HNS3_PHY_AUTONEG_CFG_B);
4574         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4575         mac->advertising = rte_le_to_cpu_32(req->advertising);
4576         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4577         mac->support_autoneg = !!(mac->supported_capa &
4578                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4579 }
4580
4581 static int
4582 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4583 {
4584         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4585         uint16_t i;
4586         int ret;
4587
4588         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4589                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4590                                           true);
4591                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4592         }
4593         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4594
4595         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4596         if (ret) {
4597                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4598                 return ret;
4599         }
4600
4601         hns3_parse_phy_params(desc, mac);
4602
4603         return 0;
4604 }
4605
4606 static int
4607 hns3_update_phy_link_info(struct hns3_hw *hw)
4608 {
4609         struct hns3_mac *mac = &hw->mac;
4610         struct hns3_mac mac_info;
4611         int ret;
4612
4613         memset(&mac_info, 0, sizeof(struct hns3_mac));
4614         ret = hns3_get_phy_params(hw, &mac_info);
4615         if (ret)
4616                 return ret;
4617
4618         if (mac_info.link_speed != mac->link_speed) {
4619                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4620                 if (ret)
4621                         return ret;
4622         }
4623
4624         mac->link_speed = mac_info.link_speed;
4625         mac->link_duplex = mac_info.link_duplex;
4626         mac->link_autoneg = mac_info.link_autoneg;
4627         mac->supported_capa = mac_info.supported_capa;
4628         mac->advertising = mac_info.advertising;
4629         mac->lp_advertising = mac_info.lp_advertising;
4630         mac->support_autoneg = mac_info.support_autoneg;
4631
4632         return 0;
4633 }
4634
4635 static int
4636 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4637 {
4638         struct hns3_adapter *hns = eth_dev->data->dev_private;
4639         struct hns3_hw *hw = &hns->hw;
4640         int ret = 0;
4641
4642         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4643                 ret = hns3_update_phy_link_info(hw);
4644         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4645                 ret = hns3_update_fiber_link_info(hw);
4646
4647         return ret;
4648 }
4649
4650 static int
4651 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4652 {
4653         struct hns3_config_mac_mode_cmd *req;
4654         struct hns3_cmd_desc desc;
4655         uint32_t loop_en = 0;
4656         uint8_t val = 0;
4657         int ret;
4658
4659         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4660
4661         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4662         if (enable)
4663                 val = 1;
4664         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4665         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4666         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4667         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4668         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4669         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4670         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4671         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4672         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4673         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4674
4675         /*
4676          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4677          * when receiving frames. Otherwise, CRC will be stripped.
4678          */
4679         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4680                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4681         else
4682                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4683         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4684         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4685         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4686         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4687
4688         ret = hns3_cmd_send(hw, &desc, 1);
4689         if (ret)
4690                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4691
4692         return ret;
4693 }
4694
4695 static int
4696 hns3_get_mac_link_status(struct hns3_hw *hw)
4697 {
4698         struct hns3_link_status_cmd *req;
4699         struct hns3_cmd_desc desc;
4700         int link_status;
4701         int ret;
4702
4703         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4704         ret = hns3_cmd_send(hw, &desc, 1);
4705         if (ret) {
4706                 hns3_err(hw, "get link status cmd failed %d", ret);
4707                 return ETH_LINK_DOWN;
4708         }
4709
4710         req = (struct hns3_link_status_cmd *)desc.data;
4711         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4712
4713         return !!link_status;
4714 }
4715
4716 static bool
4717 hns3_update_link_status(struct hns3_hw *hw)
4718 {
4719         int state;
4720
4721         state = hns3_get_mac_link_status(hw);
4722         if (state != hw->mac.link_status) {
4723                 hw->mac.link_status = state;
4724                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4725                 hns3_config_mac_tnl_int(hw,
4726                                         state == ETH_LINK_UP ? true : false);
4727                 return true;
4728         }
4729
4730         return false;
4731 }
4732
4733 /*
4734  * Current, the PF driver get link status by two ways:
4735  * 1) Periodic polling in the intr thread context, driver call
4736  *    hns3_update_link_status to update link status.
4737  * 2) Firmware report async interrupt, driver process the event in the intr
4738  *    thread context, and call hns3_update_link_status to update link status.
4739  *
4740  * If detect link status changed, driver need report LSE. One method is add the
4741  * report LSE logic in hns3_update_link_status.
4742  *
4743  * But the PF driver ops(link_update) also call hns3_update_link_status to
4744  * update link status.
4745  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4746  * bonding application.
4747  *
4748  * So add the one new API which used only in intr thread context.
4749  */
4750 void
4751 hns3_update_link_status_and_event(struct hns3_hw *hw)
4752 {
4753         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4754         bool changed = hns3_update_link_status(hw);
4755         if (changed)
4756                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4757 }
4758
4759 static void
4760 hns3_service_handler(void *param)
4761 {
4762         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4763         struct hns3_adapter *hns = eth_dev->data->dev_private;
4764         struct hns3_hw *hw = &hns->hw;
4765
4766         if (!hns3_is_reset_pending(hns)) {
4767                 hns3_update_link_status_and_event(hw);
4768                 hns3_update_link_info(eth_dev);
4769         } else {
4770                 hns3_warn(hw, "Cancel the query when reset is pending");
4771         }
4772
4773         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4774 }
4775
4776 static int
4777 hns3_init_hardware(struct hns3_adapter *hns)
4778 {
4779         struct hns3_hw *hw = &hns->hw;
4780         int ret;
4781
4782         ret = hns3_map_tqp(hw);
4783         if (ret) {
4784                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4785                 return ret;
4786         }
4787
4788         ret = hns3_init_umv_space(hw);
4789         if (ret) {
4790                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4791                 return ret;
4792         }
4793
4794         ret = hns3_mac_init(hw);
4795         if (ret) {
4796                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4797                 goto err_mac_init;
4798         }
4799
4800         ret = hns3_init_mgr_tbl(hw);
4801         if (ret) {
4802                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4803                 goto err_mac_init;
4804         }
4805
4806         ret = hns3_promisc_init(hw);
4807         if (ret) {
4808                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4809                              ret);
4810                 goto err_mac_init;
4811         }
4812
4813         ret = hns3_init_vlan_config(hns);
4814         if (ret) {
4815                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4816                 goto err_mac_init;
4817         }
4818
4819         ret = hns3_dcb_init(hw);
4820         if (ret) {
4821                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4822                 goto err_mac_init;
4823         }
4824
4825         ret = hns3_init_fd_config(hns);
4826         if (ret) {
4827                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4828                 goto err_mac_init;
4829         }
4830
4831         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4832         if (ret) {
4833                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4834                 goto err_mac_init;
4835         }
4836
4837         ret = hns3_config_gro(hw, false);
4838         if (ret) {
4839                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4840                 goto err_mac_init;
4841         }
4842
4843         /*
4844          * In the initialization clearing the all hardware mapping relationship
4845          * configurations between queues and interrupt vectors is needed, so
4846          * some error caused by the residual configurations, such as the
4847          * unexpected interrupt, can be avoid.
4848          */
4849         ret = hns3_init_ring_with_vector(hw);
4850         if (ret) {
4851                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4852                 goto err_mac_init;
4853         }
4854
4855         /*
4856          * Requiring firmware to enable some features, driver can
4857          * still work without it.
4858          */
4859         ret = hns3_firmware_compat_config(hw, true);
4860         if (ret)
4861                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4862                              "supported, ret = %d.", ret);
4863
4864         return 0;
4865
4866 err_mac_init:
4867         hns3_uninit_umv_space(hw);
4868         return ret;
4869 }
4870
4871 static int
4872 hns3_clear_hw(struct hns3_hw *hw)
4873 {
4874         struct hns3_cmd_desc desc;
4875         int ret;
4876
4877         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4878
4879         ret = hns3_cmd_send(hw, &desc, 1);
4880         if (ret && ret != -EOPNOTSUPP)
4881                 return ret;
4882
4883         return 0;
4884 }
4885
4886 static void
4887 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4888 {
4889         uint32_t val;
4890
4891         /*
4892          * The new firmware support report more hardware error types by
4893          * msix mode. These errors are defined as RAS errors in hardware
4894          * and belong to a different type from the MSI-x errors processed
4895          * by the network driver.
4896          *
4897          * Network driver should open the new error report on initialition
4898          */
4899         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4900         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4901         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4902 }
4903
4904 static int
4905 hns3_init_pf(struct rte_eth_dev *eth_dev)
4906 {
4907         struct rte_device *dev = eth_dev->device;
4908         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4909         struct hns3_adapter *hns = eth_dev->data->dev_private;
4910         struct hns3_hw *hw = &hns->hw;
4911         int ret;
4912
4913         PMD_INIT_FUNC_TRACE();
4914
4915         /* Get hardware io base address from pcie BAR2 IO space */
4916         hw->io_base = pci_dev->mem_resource[2].addr;
4917
4918         /* Firmware command queue initialize */
4919         ret = hns3_cmd_init_queue(hw);
4920         if (ret) {
4921                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4922                 goto err_cmd_init_queue;
4923         }
4924
4925         hns3_clear_all_event_cause(hw);
4926
4927         /* Firmware command initialize */
4928         ret = hns3_cmd_init(hw);
4929         if (ret) {
4930                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4931                 goto err_cmd_init;
4932         }
4933
4934         /*
4935          * To ensure that the hardware environment is clean during
4936          * initialization, the driver actively clear the hardware environment
4937          * during initialization, including PF and corresponding VFs' vlan, mac,
4938          * flow table configurations, etc.
4939          */
4940         ret = hns3_clear_hw(hw);
4941         if (ret) {
4942                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4943                 goto err_cmd_init;
4944         }
4945
4946         /* Hardware statistics of imissed registers cleared. */
4947         ret = hns3_update_imissed_stats(hw, true);
4948         if (ret) {
4949                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4950                 return ret;
4951         }
4952
4953         hns3_config_all_msix_error(hw, true);
4954
4955         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4956                                          hns3_interrupt_handler,
4957                                          eth_dev);
4958         if (ret) {
4959                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4960                 goto err_intr_callback_register;
4961         }
4962
4963         /* Enable interrupt */
4964         rte_intr_enable(&pci_dev->intr_handle);
4965         hns3_pf_enable_irq0(hw);
4966
4967         /* Get configuration */
4968         ret = hns3_get_configuration(hw);
4969         if (ret) {
4970                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4971                 goto err_get_config;
4972         }
4973
4974         ret = hns3_tqp_stats_init(hw);
4975         if (ret)
4976                 goto err_get_config;
4977
4978         ret = hns3_init_hardware(hns);
4979         if (ret) {
4980                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4981                 goto err_init_hw;
4982         }
4983
4984         /* Initialize flow director filter list & hash */
4985         ret = hns3_fdir_filter_init(hns);
4986         if (ret) {
4987                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4988                 goto err_fdir;
4989         }
4990
4991         hns3_rss_set_default_args(hw);
4992
4993         ret = hns3_enable_hw_error_intr(hns, true);
4994         if (ret) {
4995                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4996                              ret);
4997                 goto err_enable_intr;
4998         }
4999
5000         hns3_tm_conf_init(eth_dev);
5001
5002         return 0;
5003
5004 err_enable_intr:
5005         hns3_fdir_filter_uninit(hns);
5006 err_fdir:
5007         (void)hns3_firmware_compat_config(hw, false);
5008         hns3_uninit_umv_space(hw);
5009 err_init_hw:
5010         hns3_tqp_stats_uninit(hw);
5011 err_get_config:
5012         hns3_pf_disable_irq0(hw);
5013         rte_intr_disable(&pci_dev->intr_handle);
5014         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5015                              eth_dev);
5016 err_intr_callback_register:
5017 err_cmd_init:
5018         hns3_cmd_uninit(hw);
5019         hns3_cmd_destroy_queue(hw);
5020 err_cmd_init_queue:
5021         hw->io_base = NULL;
5022
5023         return ret;
5024 }
5025
5026 static void
5027 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5028 {
5029         struct hns3_adapter *hns = eth_dev->data->dev_private;
5030         struct rte_device *dev = eth_dev->device;
5031         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5032         struct hns3_hw *hw = &hns->hw;
5033
5034         PMD_INIT_FUNC_TRACE();
5035
5036         hns3_tm_conf_uninit(eth_dev);
5037         hns3_enable_hw_error_intr(hns, false);
5038         hns3_rss_uninit(hns);
5039         (void)hns3_config_gro(hw, false);
5040         hns3_promisc_uninit(hw);
5041         hns3_fdir_filter_uninit(hns);
5042         (void)hns3_firmware_compat_config(hw, false);
5043         hns3_uninit_umv_space(hw);
5044         hns3_tqp_stats_uninit(hw);
5045         hns3_config_mac_tnl_int(hw, false);
5046         hns3_pf_disable_irq0(hw);
5047         rte_intr_disable(&pci_dev->intr_handle);
5048         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5049                              eth_dev);
5050         hns3_config_all_msix_error(hw, false);
5051         hns3_cmd_uninit(hw);
5052         hns3_cmd_destroy_queue(hw);
5053         hw->io_base = NULL;
5054 }
5055
5056 static int
5057 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5058 {
5059         struct hns3_hw *hw = &hns->hw;
5060         int ret;
5061
5062         ret = hns3_dcb_cfg_update(hns);
5063         if (ret)
5064                 return ret;
5065
5066         /*
5067          * The hns3_dcb_cfg_update may configure TM module, so
5068          * hns3_tm_conf_update must called later.
5069          */
5070         ret = hns3_tm_conf_update(hw);
5071         if (ret) {
5072                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5073                 return ret;
5074         }
5075
5076         hns3_enable_rxd_adv_layout(hw);
5077
5078         ret = hns3_init_queues(hns, reset_queue);
5079         if (ret) {
5080                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5081                 return ret;
5082         }
5083
5084         ret = hns3_cfg_mac_mode(hw, true);
5085         if (ret) {
5086                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5087                 goto err_config_mac_mode;
5088         }
5089         return 0;
5090
5091 err_config_mac_mode:
5092         hns3_dev_release_mbufs(hns);
5093         /*
5094          * Here is exception handling, hns3_reset_all_tqps will have the
5095          * corresponding error message if it is handled incorrectly, so it is
5096          * not necessary to check hns3_reset_all_tqps return value, here keep
5097          * ret as the error code causing the exception.
5098          */
5099         (void)hns3_reset_all_tqps(hns);
5100         return ret;
5101 }
5102
5103 static int
5104 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5105 {
5106         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5108         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5110         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5111         uint32_t intr_vector;
5112         uint16_t q_id;
5113         int ret;
5114
5115         /*
5116          * hns3 needs a separate interrupt to be used as event interrupt which
5117          * could not be shared with task queue pair, so KERNEL drivers need
5118          * support multiple interrupt vectors.
5119          */
5120         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5121             !rte_intr_cap_multiple(intr_handle))
5122                 return 0;
5123
5124         rte_intr_disable(intr_handle);
5125         intr_vector = hw->used_rx_queues;
5126         /* creates event fd for each intr vector when MSIX is used */
5127         if (rte_intr_efd_enable(intr_handle, intr_vector))
5128                 return -EINVAL;
5129
5130         if (intr_handle->intr_vec == NULL) {
5131                 intr_handle->intr_vec =
5132                         rte_zmalloc("intr_vec",
5133                                     hw->used_rx_queues * sizeof(int), 0);
5134                 if (intr_handle->intr_vec == NULL) {
5135                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5136                                         hw->used_rx_queues);
5137                         ret = -ENOMEM;
5138                         goto alloc_intr_vec_error;
5139                 }
5140         }
5141
5142         if (rte_intr_allow_others(intr_handle)) {
5143                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5144                 base = RTE_INTR_VEC_RXTX_OFFSET;
5145         }
5146
5147         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5148                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5149                                                  HNS3_RING_TYPE_RX, q_id);
5150                 if (ret)
5151                         goto bind_vector_error;
5152                 intr_handle->intr_vec[q_id] = vec;
5153                 /*
5154                  * If there are not enough efds (e.g. not enough interrupt),
5155                  * remaining queues will be bond to the last interrupt.
5156                  */
5157                 if (vec < base + intr_handle->nb_efd - 1)
5158                         vec++;
5159         }
5160         rte_intr_enable(intr_handle);
5161         return 0;
5162
5163 bind_vector_error:
5164         rte_free(intr_handle->intr_vec);
5165         intr_handle->intr_vec = NULL;
5166 alloc_intr_vec_error:
5167         rte_intr_efd_disable(intr_handle);
5168         return ret;
5169 }
5170
5171 static int
5172 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5173 {
5174         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5175         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5176         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5177         uint16_t q_id;
5178         int ret;
5179
5180         if (dev->data->dev_conf.intr_conf.rxq == 0)
5181                 return 0;
5182
5183         if (rte_intr_dp_is_en(intr_handle)) {
5184                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5185                         ret = hns3_bind_ring_with_vector(hw,
5186                                         intr_handle->intr_vec[q_id], true,
5187                                         HNS3_RING_TYPE_RX, q_id);
5188                         if (ret)
5189                                 return ret;
5190                 }
5191         }
5192
5193         return 0;
5194 }
5195
5196 static void
5197 hns3_restore_filter(struct rte_eth_dev *dev)
5198 {
5199         hns3_restore_rss_filter(dev);
5200 }
5201
5202 static int
5203 hns3_dev_start(struct rte_eth_dev *dev)
5204 {
5205         struct hns3_adapter *hns = dev->data->dev_private;
5206         struct hns3_hw *hw = &hns->hw;
5207         int ret;
5208
5209         PMD_INIT_FUNC_TRACE();
5210         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5211                 return -EBUSY;
5212
5213         rte_spinlock_lock(&hw->lock);
5214         hw->adapter_state = HNS3_NIC_STARTING;
5215
5216         ret = hns3_do_start(hns, true);
5217         if (ret) {
5218                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5219                 rte_spinlock_unlock(&hw->lock);
5220                 return ret;
5221         }
5222         ret = hns3_map_rx_interrupt(dev);
5223         if (ret)
5224                 goto map_rx_inter_err;
5225
5226         /*
5227          * There are three register used to control the status of a TQP
5228          * (contains a pair of Tx queue and Rx queue) in the new version network
5229          * engine. One is used to control the enabling of Tx queue, the other is
5230          * used to control the enabling of Rx queue, and the last is the master
5231          * switch used to control the enabling of the tqp. The Tx register and
5232          * TQP register must be enabled at the same time to enable a Tx queue.
5233          * The same applies to the Rx queue. For the older network engine, this
5234          * function only refresh the enabled flag, and it is used to update the
5235          * status of queue in the dpdk framework.
5236          */
5237         ret = hns3_start_all_txqs(dev);
5238         if (ret)
5239                 goto map_rx_inter_err;
5240
5241         ret = hns3_start_all_rxqs(dev);
5242         if (ret)
5243                 goto start_all_rxqs_fail;
5244
5245         hw->adapter_state = HNS3_NIC_STARTED;
5246         rte_spinlock_unlock(&hw->lock);
5247
5248         hns3_rx_scattered_calc(dev);
5249         hns3_set_rxtx_function(dev);
5250         hns3_mp_req_start_rxtx(dev);
5251         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5252
5253         hns3_restore_filter(dev);
5254
5255         /* Enable interrupt of all rx queues before enabling queues */
5256         hns3_dev_all_rx_queue_intr_enable(hw, true);
5257
5258         /*
5259          * After finished the initialization, enable tqps to receive/transmit
5260          * packets and refresh all queue status.
5261          */
5262         hns3_start_tqps(hw);
5263
5264         hns3_tm_dev_start_proc(hw);
5265
5266         hns3_info(hw, "hns3 dev start successful!");
5267
5268         return 0;
5269
5270 start_all_rxqs_fail:
5271         hns3_stop_all_txqs(dev);
5272 map_rx_inter_err:
5273         (void)hns3_do_stop(hns);
5274         hw->adapter_state = HNS3_NIC_CONFIGURED;
5275         rte_spinlock_unlock(&hw->lock);
5276
5277         return ret;
5278 }
5279
5280 static int
5281 hns3_do_stop(struct hns3_adapter *hns)
5282 {
5283         struct hns3_hw *hw = &hns->hw;
5284         int ret;
5285
5286         /*
5287          * The "hns3_do_stop" function will also be called by .stop_service to
5288          * prepare reset. At the time of global or IMP reset, the command cannot
5289          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5290          * accessed during the reset process. So the mbuf can not be released
5291          * during reset and is required to be released after the reset is
5292          * completed.
5293          */
5294         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5295                 hns3_dev_release_mbufs(hns);
5296
5297         ret = hns3_cfg_mac_mode(hw, false);
5298         if (ret)
5299                 return ret;
5300         hw->mac.link_status = ETH_LINK_DOWN;
5301
5302         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5303                 hns3_configure_all_mac_addr(hns, true);
5304                 ret = hns3_reset_all_tqps(hns);
5305                 if (ret) {
5306                         hns3_err(hw, "failed to reset all queues ret = %d.",
5307                                  ret);
5308                         return ret;
5309                 }
5310         }
5311         hw->mac.default_addr_setted = false;
5312         return 0;
5313 }
5314
5315 static void
5316 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5317 {
5318         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5319         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5320         struct hns3_adapter *hns = dev->data->dev_private;
5321         struct hns3_hw *hw = &hns->hw;
5322         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5323         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5324         uint16_t q_id;
5325
5326         if (dev->data->dev_conf.intr_conf.rxq == 0)
5327                 return;
5328
5329         /* unmap the ring with vector */
5330         if (rte_intr_allow_others(intr_handle)) {
5331                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5332                 base = RTE_INTR_VEC_RXTX_OFFSET;
5333         }
5334         if (rte_intr_dp_is_en(intr_handle)) {
5335                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5336                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5337                                                          HNS3_RING_TYPE_RX,
5338                                                          q_id);
5339                         if (vec < base + intr_handle->nb_efd - 1)
5340                                 vec++;
5341                 }
5342         }
5343         /* Clean datapath event and queue/vec mapping */
5344         rte_intr_efd_disable(intr_handle);
5345         if (intr_handle->intr_vec) {
5346                 rte_free(intr_handle->intr_vec);
5347                 intr_handle->intr_vec = NULL;
5348         }
5349 }
5350
5351 static int
5352 hns3_dev_stop(struct rte_eth_dev *dev)
5353 {
5354         struct hns3_adapter *hns = dev->data->dev_private;
5355         struct hns3_hw *hw = &hns->hw;
5356
5357         PMD_INIT_FUNC_TRACE();
5358         dev->data->dev_started = 0;
5359
5360         hw->adapter_state = HNS3_NIC_STOPPING;
5361         hns3_set_rxtx_function(dev);
5362         rte_wmb();
5363         /* Disable datapath on secondary process. */
5364         hns3_mp_req_stop_rxtx(dev);
5365         /* Prevent crashes when queues are still in use. */
5366         rte_delay_ms(hw->tqps_num);
5367
5368         rte_spinlock_lock(&hw->lock);
5369         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5370                 hns3_tm_dev_stop_proc(hw);
5371                 hns3_config_mac_tnl_int(hw, false);
5372                 hns3_stop_tqps(hw);
5373                 hns3_do_stop(hns);
5374                 hns3_unmap_rx_interrupt(dev);
5375                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5376         }
5377         hns3_rx_scattered_reset(dev);
5378         rte_eal_alarm_cancel(hns3_service_handler, dev);
5379         rte_spinlock_unlock(&hw->lock);
5380
5381         return 0;
5382 }
5383
5384 static int
5385 hns3_dev_close(struct rte_eth_dev *eth_dev)
5386 {
5387         struct hns3_adapter *hns = eth_dev->data->dev_private;
5388         struct hns3_hw *hw = &hns->hw;
5389         int ret = 0;
5390
5391         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5392                 rte_free(eth_dev->process_private);
5393                 eth_dev->process_private = NULL;
5394                 return 0;
5395         }
5396
5397         if (hw->adapter_state == HNS3_NIC_STARTED)
5398                 ret = hns3_dev_stop(eth_dev);
5399
5400         hw->adapter_state = HNS3_NIC_CLOSING;
5401         hns3_reset_abort(hns);
5402         hw->adapter_state = HNS3_NIC_CLOSED;
5403
5404         hns3_configure_all_mc_mac_addr(hns, true);
5405         hns3_remove_all_vlan_table(hns);
5406         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5407         hns3_uninit_pf(eth_dev);
5408         hns3_free_all_queues(eth_dev);
5409         rte_free(hw->reset.wait_data);
5410         rte_free(eth_dev->process_private);
5411         eth_dev->process_private = NULL;
5412         hns3_mp_uninit_primary();
5413         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5414
5415         return ret;
5416 }
5417
5418 static int
5419 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5420 {
5421         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5422         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5423
5424         fc_conf->pause_time = pf->pause_time;
5425
5426         /* return fc current mode */
5427         switch (hw->current_mode) {
5428         case HNS3_FC_FULL:
5429                 fc_conf->mode = RTE_FC_FULL;
5430                 break;
5431         case HNS3_FC_TX_PAUSE:
5432                 fc_conf->mode = RTE_FC_TX_PAUSE;
5433                 break;
5434         case HNS3_FC_RX_PAUSE:
5435                 fc_conf->mode = RTE_FC_RX_PAUSE;
5436                 break;
5437         case HNS3_FC_NONE:
5438         default:
5439                 fc_conf->mode = RTE_FC_NONE;
5440                 break;
5441         }
5442
5443         return 0;
5444 }
5445
5446 static void
5447 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5448 {
5449         switch (mode) {
5450         case RTE_FC_NONE:
5451                 hw->requested_mode = HNS3_FC_NONE;
5452                 break;
5453         case RTE_FC_RX_PAUSE:
5454                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5455                 break;
5456         case RTE_FC_TX_PAUSE:
5457                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5458                 break;
5459         case RTE_FC_FULL:
5460                 hw->requested_mode = HNS3_FC_FULL;
5461                 break;
5462         default:
5463                 hw->requested_mode = HNS3_FC_NONE;
5464                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5465                           "configured to RTE_FC_NONE", mode);
5466                 break;
5467         }
5468 }
5469
5470 static int
5471 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5472 {
5473         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5475         int ret;
5476
5477         if (fc_conf->high_water || fc_conf->low_water ||
5478             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5479                 hns3_err(hw, "Unsupported flow control settings specified, "
5480                          "high_water(%u), low_water(%u), send_xon(%u) and "
5481                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5482                          fc_conf->high_water, fc_conf->low_water,
5483                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5484                 return -EINVAL;
5485         }
5486         if (fc_conf->autoneg) {
5487                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5488                 return -EINVAL;
5489         }
5490         if (!fc_conf->pause_time) {
5491                 hns3_err(hw, "Invalid pause time %u setting.",
5492                          fc_conf->pause_time);
5493                 return -EINVAL;
5494         }
5495
5496         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5497             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5498                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5499                          "current_fc_status = %d", hw->current_fc_status);
5500                 return -EOPNOTSUPP;
5501         }
5502
5503         hns3_get_fc_mode(hw, fc_conf->mode);
5504         if (hw->requested_mode == hw->current_mode &&
5505             pf->pause_time == fc_conf->pause_time)
5506                 return 0;
5507
5508         rte_spinlock_lock(&hw->lock);
5509         ret = hns3_fc_enable(dev, fc_conf);
5510         rte_spinlock_unlock(&hw->lock);
5511
5512         return ret;
5513 }
5514
5515 static int
5516 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5517                             struct rte_eth_pfc_conf *pfc_conf)
5518 {
5519         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5520         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5521         uint8_t priority;
5522         int ret;
5523
5524         if (!hns3_dev_dcb_supported(hw)) {
5525                 hns3_err(hw, "This port does not support dcb configurations.");
5526                 return -EOPNOTSUPP;
5527         }
5528
5529         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5530             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5531                 hns3_err(hw, "Unsupported flow control settings specified, "
5532                          "high_water(%u), low_water(%u), send_xon(%u) and "
5533                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5534                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5535                          pfc_conf->fc.send_xon,
5536                          pfc_conf->fc.mac_ctrl_frame_fwd);
5537                 return -EINVAL;
5538         }
5539         if (pfc_conf->fc.autoneg) {
5540                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5541                 return -EINVAL;
5542         }
5543         if (pfc_conf->fc.pause_time == 0) {
5544                 hns3_err(hw, "Invalid pause time %u setting.",
5545                          pfc_conf->fc.pause_time);
5546                 return -EINVAL;
5547         }
5548
5549         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5550             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5551                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5552                              "current_fc_status = %d", hw->current_fc_status);
5553                 return -EOPNOTSUPP;
5554         }
5555
5556         priority = pfc_conf->priority;
5557         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5558         if (hw->dcb_info.pfc_en & BIT(priority) &&
5559             hw->requested_mode == hw->current_mode &&
5560             pfc_conf->fc.pause_time == pf->pause_time)
5561                 return 0;
5562
5563         rte_spinlock_lock(&hw->lock);
5564         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5565         rte_spinlock_unlock(&hw->lock);
5566
5567         return ret;
5568 }
5569
5570 static int
5571 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5572 {
5573         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5574         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5575         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5576         int i;
5577
5578         rte_spinlock_lock(&hw->lock);
5579         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5580                 dcb_info->nb_tcs = pf->local_max_tc;
5581         else
5582                 dcb_info->nb_tcs = 1;
5583
5584         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5585                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5586         for (i = 0; i < dcb_info->nb_tcs; i++)
5587                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5588
5589         for (i = 0; i < hw->num_tc; i++) {
5590                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5591                 dcb_info->tc_queue.tc_txq[0][i].base =
5592                                                 hw->tc_queue[i].tqp_offset;
5593                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5594                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5595                                                 hw->tc_queue[i].tqp_count;
5596         }
5597         rte_spinlock_unlock(&hw->lock);
5598
5599         return 0;
5600 }
5601
5602 static int
5603 hns3_reinit_dev(struct hns3_adapter *hns)
5604 {
5605         struct hns3_hw *hw = &hns->hw;
5606         int ret;
5607
5608         ret = hns3_cmd_init(hw);
5609         if (ret) {
5610                 hns3_err(hw, "Failed to init cmd: %d", ret);
5611                 return ret;
5612         }
5613
5614         ret = hns3_reset_all_tqps(hns);
5615         if (ret) {
5616                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5617                 return ret;
5618         }
5619
5620         ret = hns3_init_hardware(hns);
5621         if (ret) {
5622                 hns3_err(hw, "Failed to init hardware: %d", ret);
5623                 return ret;
5624         }
5625
5626         ret = hns3_enable_hw_error_intr(hns, true);
5627         if (ret) {
5628                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5629                              ret);
5630                 return ret;
5631         }
5632         hns3_info(hw, "Reset done, driver initialization finished.");
5633
5634         return 0;
5635 }
5636
5637 static bool
5638 is_pf_reset_done(struct hns3_hw *hw)
5639 {
5640         uint32_t val, reg, reg_bit;
5641
5642         switch (hw->reset.level) {
5643         case HNS3_IMP_RESET:
5644                 reg = HNS3_GLOBAL_RESET_REG;
5645                 reg_bit = HNS3_IMP_RESET_BIT;
5646                 break;
5647         case HNS3_GLOBAL_RESET:
5648                 reg = HNS3_GLOBAL_RESET_REG;
5649                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5650                 break;
5651         case HNS3_FUNC_RESET:
5652                 reg = HNS3_FUN_RST_ING;
5653                 reg_bit = HNS3_FUN_RST_ING_B;
5654                 break;
5655         case HNS3_FLR_RESET:
5656         default:
5657                 hns3_err(hw, "Wait for unsupported reset level: %d",
5658                          hw->reset.level);
5659                 return true;
5660         }
5661         val = hns3_read_dev(hw, reg);
5662         if (hns3_get_bit(val, reg_bit))
5663                 return false;
5664         else
5665                 return true;
5666 }
5667
5668 bool
5669 hns3_is_reset_pending(struct hns3_adapter *hns)
5670 {
5671         struct hns3_hw *hw = &hns->hw;
5672         enum hns3_reset_level reset;
5673
5674         hns3_check_event_cause(hns, NULL);
5675         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5676         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5677                 hns3_warn(hw, "High level reset %d is pending", reset);
5678                 return true;
5679         }
5680         reset = hns3_get_reset_level(hns, &hw->reset.request);
5681         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5682                 hns3_warn(hw, "High level reset %d is request", reset);
5683                 return true;
5684         }
5685         return false;
5686 }
5687
5688 static int
5689 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5690 {
5691         struct hns3_hw *hw = &hns->hw;
5692         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5693         struct timeval tv;
5694
5695         if (wait_data->result == HNS3_WAIT_SUCCESS)
5696                 return 0;
5697         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5698                 gettimeofday(&tv, NULL);
5699                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5700                           tv.tv_sec, tv.tv_usec);
5701                 return -ETIME;
5702         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5703                 return -EAGAIN;
5704
5705         wait_data->hns = hns;
5706         wait_data->check_completion = is_pf_reset_done;
5707         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5708                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5709         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5710         wait_data->count = HNS3_RESET_WAIT_CNT;
5711         wait_data->result = HNS3_WAIT_REQUEST;
5712         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5713         return -EAGAIN;
5714 }
5715
5716 static int
5717 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5718 {
5719         struct hns3_cmd_desc desc;
5720         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5721
5722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5723         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5724         req->fun_reset_vfid = func_id;
5725
5726         return hns3_cmd_send(hw, &desc, 1);
5727 }
5728
5729 static int
5730 hns3_imp_reset_cmd(struct hns3_hw *hw)
5731 {
5732         struct hns3_cmd_desc desc;
5733
5734         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5735         desc.data[0] = 0xeedd;
5736
5737         return hns3_cmd_send(hw, &desc, 1);
5738 }
5739
5740 static void
5741 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5742 {
5743         struct hns3_hw *hw = &hns->hw;
5744         struct timeval tv;
5745         uint32_t val;
5746
5747         gettimeofday(&tv, NULL);
5748         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5749             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5750                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5751                           tv.tv_sec, tv.tv_usec);
5752                 return;
5753         }
5754
5755         switch (reset_level) {
5756         case HNS3_IMP_RESET:
5757                 hns3_imp_reset_cmd(hw);
5758                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5759                           tv.tv_sec, tv.tv_usec);
5760                 break;
5761         case HNS3_GLOBAL_RESET:
5762                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5763                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5764                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5765                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5766                           tv.tv_sec, tv.tv_usec);
5767                 break;
5768         case HNS3_FUNC_RESET:
5769                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5770                           tv.tv_sec, tv.tv_usec);
5771                 /* schedule again to check later */
5772                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5773                 hns3_schedule_reset(hns);
5774                 break;
5775         default:
5776                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5777                 return;
5778         }
5779         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5780 }
5781
5782 static enum hns3_reset_level
5783 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5784 {
5785         struct hns3_hw *hw = &hns->hw;
5786         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5787
5788         /* Return the highest priority reset level amongst all */
5789         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5790                 reset_level = HNS3_IMP_RESET;
5791         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5792                 reset_level = HNS3_GLOBAL_RESET;
5793         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5794                 reset_level = HNS3_FUNC_RESET;
5795         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5796                 reset_level = HNS3_FLR_RESET;
5797
5798         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5799                 return HNS3_NONE_RESET;
5800
5801         return reset_level;
5802 }
5803
5804 static void
5805 hns3_record_imp_error(struct hns3_adapter *hns)
5806 {
5807         struct hns3_hw *hw = &hns->hw;
5808         uint32_t reg_val;
5809
5810         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5811         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5812                 hns3_warn(hw, "Detected IMP RD poison!");
5813                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5814                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5815         }
5816
5817         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5818                 hns3_warn(hw, "Detected IMP CMDQ error!");
5819                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5820                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5821         }
5822 }
5823
5824 static int
5825 hns3_prepare_reset(struct hns3_adapter *hns)
5826 {
5827         struct hns3_hw *hw = &hns->hw;
5828         uint32_t reg_val;
5829         int ret;
5830
5831         switch (hw->reset.level) {
5832         case HNS3_FUNC_RESET:
5833                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5834                 if (ret)
5835                         return ret;
5836
5837                 /*
5838                  * After performaning pf reset, it is not necessary to do the
5839                  * mailbox handling or send any command to firmware, because
5840                  * any mailbox handling or command to firmware is only valid
5841                  * after hns3_cmd_init is called.
5842                  */
5843                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5844                 hw->reset.stats.request_cnt++;
5845                 break;
5846         case HNS3_IMP_RESET:
5847                 hns3_record_imp_error(hns);
5848                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5849                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5850                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5851                 break;
5852         default:
5853                 break;
5854         }
5855         return 0;
5856 }
5857
5858 static int
5859 hns3_set_rst_done(struct hns3_hw *hw)
5860 {
5861         struct hns3_pf_rst_done_cmd *req;
5862         struct hns3_cmd_desc desc;
5863
5864         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5865         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5866         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5867         return hns3_cmd_send(hw, &desc, 1);
5868 }
5869
5870 static int
5871 hns3_stop_service(struct hns3_adapter *hns)
5872 {
5873         struct hns3_hw *hw = &hns->hw;
5874         struct rte_eth_dev *eth_dev;
5875
5876         eth_dev = &rte_eth_devices[hw->data->port_id];
5877         if (hw->adapter_state == HNS3_NIC_STARTED) {
5878                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5879                 hns3_update_link_status_and_event(hw);
5880         }
5881         hw->mac.link_status = ETH_LINK_DOWN;
5882
5883         hns3_set_rxtx_function(eth_dev);
5884         rte_wmb();
5885         /* Disable datapath on secondary process. */
5886         hns3_mp_req_stop_rxtx(eth_dev);
5887         rte_delay_ms(hw->tqps_num);
5888
5889         rte_spinlock_lock(&hw->lock);
5890         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5891             hw->adapter_state == HNS3_NIC_STOPPING) {
5892                 hns3_enable_all_queues(hw, false);
5893                 hns3_do_stop(hns);
5894                 hw->reset.mbuf_deferred_free = true;
5895         } else
5896                 hw->reset.mbuf_deferred_free = false;
5897
5898         /*
5899          * It is cumbersome for hardware to pick-and-choose entries for deletion
5900          * from table space. Hence, for function reset software intervention is
5901          * required to delete the entries
5902          */
5903         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5904                 hns3_configure_all_mc_mac_addr(hns, true);
5905         rte_spinlock_unlock(&hw->lock);
5906
5907         return 0;
5908 }
5909
5910 static int
5911 hns3_start_service(struct hns3_adapter *hns)
5912 {
5913         struct hns3_hw *hw = &hns->hw;
5914         struct rte_eth_dev *eth_dev;
5915
5916         if (hw->reset.level == HNS3_IMP_RESET ||
5917             hw->reset.level == HNS3_GLOBAL_RESET)
5918                 hns3_set_rst_done(hw);
5919         eth_dev = &rte_eth_devices[hw->data->port_id];
5920         hns3_set_rxtx_function(eth_dev);
5921         hns3_mp_req_start_rxtx(eth_dev);
5922         if (hw->adapter_state == HNS3_NIC_STARTED) {
5923                 /*
5924                  * This API parent function already hold the hns3_hw.lock, the
5925                  * hns3_service_handler may report lse, in bonding application
5926                  * it will call driver's ops which may acquire the hns3_hw.lock
5927                  * again, thus lead to deadlock.
5928                  * We defer calls hns3_service_handler to avoid the deadlock.
5929                  */
5930                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5931                                   hns3_service_handler, eth_dev);
5932
5933                 /* Enable interrupt of all rx queues before enabling queues */
5934                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5935                 /*
5936                  * Enable state of each rxq and txq will be recovered after
5937                  * reset, so we need to restore them before enable all tqps;
5938                  */
5939                 hns3_restore_tqp_enable_state(hw);
5940                 /*
5941                  * When finished the initialization, enable queues to receive
5942                  * and transmit packets.
5943                  */
5944                 hns3_enable_all_queues(hw, true);
5945         }
5946
5947         return 0;
5948 }
5949
5950 static int
5951 hns3_restore_conf(struct hns3_adapter *hns)
5952 {
5953         struct hns3_hw *hw = &hns->hw;
5954         int ret;
5955
5956         ret = hns3_configure_all_mac_addr(hns, false);
5957         if (ret)
5958                 return ret;
5959
5960         ret = hns3_configure_all_mc_mac_addr(hns, false);
5961         if (ret)
5962                 goto err_mc_mac;
5963
5964         ret = hns3_dev_promisc_restore(hns);
5965         if (ret)
5966                 goto err_promisc;
5967
5968         ret = hns3_restore_vlan_table(hns);
5969         if (ret)
5970                 goto err_promisc;
5971
5972         ret = hns3_restore_vlan_conf(hns);
5973         if (ret)
5974                 goto err_promisc;
5975
5976         ret = hns3_restore_all_fdir_filter(hns);
5977         if (ret)
5978                 goto err_promisc;
5979
5980         ret = hns3_restore_rx_interrupt(hw);
5981         if (ret)
5982                 goto err_promisc;
5983
5984         ret = hns3_restore_gro_conf(hw);
5985         if (ret)
5986                 goto err_promisc;
5987
5988         ret = hns3_restore_fec(hw);
5989         if (ret)
5990                 goto err_promisc;
5991
5992         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5993                 ret = hns3_do_start(hns, false);
5994                 if (ret)
5995                         goto err_promisc;
5996                 hns3_info(hw, "hns3 dev restart successful!");
5997         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5998                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5999         return 0;
6000
6001 err_promisc:
6002         hns3_configure_all_mc_mac_addr(hns, true);
6003 err_mc_mac:
6004         hns3_configure_all_mac_addr(hns, true);
6005         return ret;
6006 }
6007
6008 static void
6009 hns3_reset_service(void *param)
6010 {
6011         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6012         struct hns3_hw *hw = &hns->hw;
6013         enum hns3_reset_level reset_level;
6014         struct timeval tv_delta;
6015         struct timeval tv_start;
6016         struct timeval tv;
6017         uint64_t msec;
6018         int ret;
6019
6020         /*
6021          * The interrupt is not triggered within the delay time.
6022          * The interrupt may have been lost. It is necessary to handle
6023          * the interrupt to recover from the error.
6024          */
6025         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6026                             SCHEDULE_DEFERRED) {
6027                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6028                                   __ATOMIC_RELAXED);
6029                 hns3_err(hw, "Handling interrupts in delayed tasks");
6030                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6031                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6032                 if (reset_level == HNS3_NONE_RESET) {
6033                         hns3_err(hw, "No reset level is set, try IMP reset");
6034                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6035                 }
6036         }
6037         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6038
6039         /*
6040          * Check if there is any ongoing reset in the hardware. This status can
6041          * be checked from reset_pending. If there is then, we need to wait for
6042          * hardware to complete reset.
6043          *    a. If we are able to figure out in reasonable time that hardware
6044          *       has fully resetted then, we can proceed with driver, client
6045          *       reset.
6046          *    b. else, we can come back later to check this status so re-sched
6047          *       now.
6048          */
6049         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6050         if (reset_level != HNS3_NONE_RESET) {
6051                 gettimeofday(&tv_start, NULL);
6052                 ret = hns3_reset_process(hns, reset_level);
6053                 gettimeofday(&tv, NULL);
6054                 timersub(&tv, &tv_start, &tv_delta);
6055                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6056                        tv_delta.tv_usec / USEC_PER_MSEC;
6057                 if (msec > HNS3_RESET_PROCESS_MS)
6058                         hns3_err(hw, "%d handle long time delta %" PRIx64
6059                                      " ms time=%ld.%.6ld",
6060                                  hw->reset.level, msec,
6061                                  tv.tv_sec, tv.tv_usec);
6062                 if (ret == -EAGAIN)
6063                         return;
6064         }
6065
6066         /* Check if we got any *new* reset requests to be honored */
6067         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6068         if (reset_level != HNS3_NONE_RESET)
6069                 hns3_msix_process(hns, reset_level);
6070 }
6071
6072 static unsigned int
6073 hns3_get_speed_capa_num(uint16_t device_id)
6074 {
6075         unsigned int num;
6076
6077         switch (device_id) {
6078         case HNS3_DEV_ID_25GE:
6079         case HNS3_DEV_ID_25GE_RDMA:
6080                 num = 2;
6081                 break;
6082         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6083         case HNS3_DEV_ID_200G_RDMA:
6084                 num = 1;
6085                 break;
6086         default:
6087                 num = 0;
6088                 break;
6089         }
6090
6091         return num;
6092 }
6093
6094 static int
6095 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6096                         uint16_t device_id)
6097 {
6098         switch (device_id) {
6099         case HNS3_DEV_ID_25GE:
6100         /* fallthrough */
6101         case HNS3_DEV_ID_25GE_RDMA:
6102                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6103                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6104
6105                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6106                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6107                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6108                 break;
6109         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6110                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6111                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6112                 break;
6113         case HNS3_DEV_ID_200G_RDMA:
6114                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6115                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6116                 break;
6117         default:
6118                 return -ENOTSUP;
6119         }
6120
6121         return 0;
6122 }
6123
6124 static int
6125 hns3_fec_get_capability(struct rte_eth_dev *dev,
6126                         struct rte_eth_fec_capa *speed_fec_capa,
6127                         unsigned int num)
6128 {
6129         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6130         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6131         uint16_t device_id = pci_dev->id.device_id;
6132         unsigned int capa_num;
6133         int ret;
6134
6135         capa_num = hns3_get_speed_capa_num(device_id);
6136         if (capa_num == 0) {
6137                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6138                          device_id);
6139                 return -ENOTSUP;
6140         }
6141
6142         if (speed_fec_capa == NULL || num < capa_num)
6143                 return capa_num;
6144
6145         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6146         if (ret)
6147                 return -ENOTSUP;
6148
6149         return capa_num;
6150 }
6151
6152 static int
6153 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6154 {
6155         struct hns3_config_fec_cmd *req;
6156         struct hns3_cmd_desc desc;
6157         int ret;
6158
6159         /*
6160          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6161          * in device of link speed
6162          * below 10 Gbps.
6163          */
6164         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6165                 *state = 0;
6166                 return 0;
6167         }
6168
6169         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6170         req = (struct hns3_config_fec_cmd *)desc.data;
6171         ret = hns3_cmd_send(hw, &desc, 1);
6172         if (ret) {
6173                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6174                          ret);
6175                 return ret;
6176         }
6177
6178         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6179         return 0;
6180 }
6181
6182 static int
6183 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6184 {
6185 #define QUERY_ACTIVE_SPEED      1
6186         struct hns3_sfp_speed_cmd *resp;
6187         uint32_t tmp_fec_capa;
6188         uint8_t auto_state;
6189         struct hns3_cmd_desc desc;
6190         int ret;
6191
6192         /*
6193          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6194          * configured FEC mode is returned.
6195          * If link is up, current FEC mode is returned.
6196          */
6197         if (hw->mac.link_status == ETH_LINK_DOWN) {
6198                 ret = get_current_fec_auto_state(hw, &auto_state);
6199                 if (ret)
6200                         return ret;
6201
6202                 if (auto_state == 0x1) {
6203                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6204                         return 0;
6205                 }
6206         }
6207
6208         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6209         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6210         resp->query_type = QUERY_ACTIVE_SPEED;
6211
6212         ret = hns3_cmd_send(hw, &desc, 1);
6213         if (ret == -EOPNOTSUPP) {
6214                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6215                 return ret;
6216         } else if (ret) {
6217                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6218                 return ret;
6219         }
6220
6221         /*
6222          * FEC mode order defined in hns3 hardware is inconsistend with
6223          * that defined in the ethdev library. So the sequence needs
6224          * to be converted.
6225          */
6226         switch (resp->active_fec) {
6227         case HNS3_HW_FEC_MODE_NOFEC:
6228                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6229                 break;
6230         case HNS3_HW_FEC_MODE_BASER:
6231                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6232                 break;
6233         case HNS3_HW_FEC_MODE_RS:
6234                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6235                 break;
6236         default:
6237                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6238                 break;
6239         }
6240
6241         *fec_capa = tmp_fec_capa;
6242         return 0;
6243 }
6244
6245 static int
6246 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6247 {
6248         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6249
6250         return hns3_fec_get_internal(hw, fec_capa);
6251 }
6252
6253 static int
6254 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6255 {
6256         struct hns3_config_fec_cmd *req;
6257         struct hns3_cmd_desc desc;
6258         int ret;
6259
6260         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6261
6262         req = (struct hns3_config_fec_cmd *)desc.data;
6263         switch (mode) {
6264         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6265                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6266                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6267                 break;
6268         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6269                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6270                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6271                 break;
6272         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6273                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6274                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6275                 break;
6276         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6277                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6278                 break;
6279         default:
6280                 return 0;
6281         }
6282         ret = hns3_cmd_send(hw, &desc, 1);
6283         if (ret)
6284                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6285
6286         return ret;
6287 }
6288
6289 static uint32_t
6290 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6291 {
6292         struct hns3_mac *mac = &hw->mac;
6293         uint32_t cur_capa;
6294
6295         switch (mac->link_speed) {
6296         case ETH_SPEED_NUM_10G:
6297                 cur_capa = fec_capa[1].capa;
6298                 break;
6299         case ETH_SPEED_NUM_25G:
6300         case ETH_SPEED_NUM_100G:
6301         case ETH_SPEED_NUM_200G:
6302                 cur_capa = fec_capa[0].capa;
6303                 break;
6304         default:
6305                 cur_capa = 0;
6306                 break;
6307         }
6308
6309         return cur_capa;
6310 }
6311
6312 static bool
6313 is_fec_mode_one_bit_set(uint32_t mode)
6314 {
6315         int cnt = 0;
6316         uint8_t i;
6317
6318         for (i = 0; i < sizeof(mode); i++)
6319                 if (mode >> i & 0x1)
6320                         cnt++;
6321
6322         return cnt == 1 ? true : false;
6323 }
6324
6325 static int
6326 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6327 {
6328 #define FEC_CAPA_NUM 2
6329         struct hns3_adapter *hns = dev->data->dev_private;
6330         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6331         struct hns3_pf *pf = &hns->pf;
6332
6333         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6334         uint32_t cur_capa;
6335         uint32_t num = FEC_CAPA_NUM;
6336         int ret;
6337
6338         ret = hns3_fec_get_capability(dev, fec_capa, num);
6339         if (ret < 0)
6340                 return ret;
6341
6342         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6343         if (!is_fec_mode_one_bit_set(mode))
6344                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6345                              "FEC mode should be only one bit set", mode);
6346
6347         /*
6348          * Check whether the configured mode is within the FEC capability.
6349          * If not, the configured mode will not be supported.
6350          */
6351         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6352         if (!(cur_capa & mode)) {
6353                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6354                 return -EINVAL;
6355         }
6356
6357         ret = hns3_set_fec_hw(hw, mode);
6358         if (ret)
6359                 return ret;
6360
6361         pf->fec_mode = mode;
6362         return 0;
6363 }
6364
6365 static int
6366 hns3_restore_fec(struct hns3_hw *hw)
6367 {
6368         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6369         struct hns3_pf *pf = &hns->pf;
6370         uint32_t mode = pf->fec_mode;
6371         int ret;
6372
6373         ret = hns3_set_fec_hw(hw, mode);
6374         if (ret)
6375                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6376                          mode, ret);
6377
6378         return ret;
6379 }
6380
6381 static int
6382 hns3_query_dev_fec_info(struct hns3_hw *hw)
6383 {
6384         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6385         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6386         int ret;
6387
6388         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6389         if (ret)
6390                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6391
6392         return ret;
6393 }
6394
6395 static bool
6396 hns3_optical_module_existed(struct hns3_hw *hw)
6397 {
6398         struct hns3_cmd_desc desc;
6399         bool existed;
6400         int ret;
6401
6402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6403         ret = hns3_cmd_send(hw, &desc, 1);
6404         if (ret) {
6405                 hns3_err(hw,
6406                          "fail to get optical module exist state, ret = %d.\n",
6407                          ret);
6408                 return false;
6409         }
6410         existed = !!desc.data[0];
6411
6412         return existed;
6413 }
6414
6415 static int
6416 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6417                                 uint32_t len, uint8_t *data)
6418 {
6419 #define HNS3_SFP_INFO_CMD_NUM 6
6420 #define HNS3_SFP_INFO_MAX_LEN \
6421         (HNS3_SFP_INFO_BD0_LEN + \
6422         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6423         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6424         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6425         uint16_t read_len;
6426         uint16_t copy_len;
6427         int ret;
6428         int i;
6429
6430         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6431                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6432                                           true);
6433                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6434                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6435         }
6436
6437         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6438         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6439         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6440         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6441
6442         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6443         if (ret) {
6444                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6445                                 ret);
6446                 return ret;
6447         }
6448
6449         /* The data format in BD0 is different with the others. */
6450         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6451         memcpy(data, sfp_info_bd0->data, copy_len);
6452         read_len = copy_len;
6453
6454         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6455                 if (read_len >= len)
6456                         break;
6457
6458                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6459                 memcpy(data + read_len, desc[i].data, copy_len);
6460                 read_len += copy_len;
6461         }
6462
6463         return (int)read_len;
6464 }
6465
6466 static int
6467 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6468                        struct rte_dev_eeprom_info *info)
6469 {
6470         struct hns3_adapter *hns = dev->data->dev_private;
6471         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6472         uint32_t offset = info->offset;
6473         uint32_t len = info->length;
6474         uint8_t *data = info->data;
6475         uint32_t read_len = 0;
6476
6477         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6478                 return -ENOTSUP;
6479
6480         if (!hns3_optical_module_existed(hw)) {
6481                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6482                 return -EIO;
6483         }
6484
6485         while (read_len < len) {
6486                 int ret;
6487                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6488                                                   len - read_len,
6489                                                   data + read_len);
6490                 if (ret < 0)
6491                         return -EIO;
6492                 read_len += ret;
6493         }
6494
6495         return 0;
6496 }
6497
6498 static int
6499 hns3_get_module_info(struct rte_eth_dev *dev,
6500                      struct rte_eth_dev_module_info *modinfo)
6501 {
6502 #define HNS3_SFF8024_ID_SFP             0x03
6503 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6504 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6505 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6506 #define HNS3_SFF_8636_V1_3              0x03
6507         struct hns3_adapter *hns = dev->data->dev_private;
6508         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6509         struct rte_dev_eeprom_info info;
6510         struct hns3_sfp_type sfp_type;
6511         int ret;
6512
6513         memset(&sfp_type, 0, sizeof(sfp_type));
6514         memset(&info, 0, sizeof(info));
6515         info.data = (uint8_t *)&sfp_type;
6516         info.length = sizeof(sfp_type);
6517         ret = hns3_get_module_eeprom(dev, &info);
6518         if (ret)
6519                 return ret;
6520
6521         switch (sfp_type.type) {
6522         case HNS3_SFF8024_ID_SFP:
6523                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6524                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6525                 break;
6526         case HNS3_SFF8024_ID_QSFP_8438:
6527                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6528                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6529                 break;
6530         case HNS3_SFF8024_ID_QSFP_8436_8636:
6531                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6532                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6533                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6534                 } else {
6535                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6536                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6537                 }
6538                 break;
6539         case HNS3_SFF8024_ID_QSFP28_8636:
6540                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6541                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6542                 break;
6543         default:
6544                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6545                          sfp_type.type, sfp_type.ext_type);
6546                 return -EINVAL;
6547         }
6548
6549         return 0;
6550 }
6551
6552 static int
6553 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
6554 {
6555         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
6556
6557         RTE_SET_USED(key);
6558
6559         if (strcmp(value, "vec") == 0)
6560                 hint = HNS3_IO_FUNC_HINT_VEC;
6561         else if (strcmp(value, "sve") == 0)
6562                 hint = HNS3_IO_FUNC_HINT_SVE;
6563         else if (strcmp(value, "simple") == 0)
6564                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
6565         else if (strcmp(value, "common") == 0)
6566                 hint = HNS3_IO_FUNC_HINT_COMMON;
6567
6568         /* If the hint is valid then update output parameters */
6569         if (hint != HNS3_IO_FUNC_HINT_NONE)
6570                 *(uint32_t *)extra_args = hint;
6571
6572         return 0;
6573 }
6574
6575 static const char *
6576 hns3_get_io_hint_func_name(uint32_t hint)
6577 {
6578         switch (hint) {
6579         case HNS3_IO_FUNC_HINT_VEC:
6580                 return "vec";
6581         case HNS3_IO_FUNC_HINT_SVE:
6582                 return "sve";
6583         case HNS3_IO_FUNC_HINT_SIMPLE:
6584                 return "simple";
6585         case HNS3_IO_FUNC_HINT_COMMON:
6586                 return "common";
6587         default:
6588                 return "none";
6589         }
6590 }
6591
6592 void
6593 hns3_parse_devargs(struct rte_eth_dev *dev)
6594 {
6595         struct hns3_adapter *hns = dev->data->dev_private;
6596         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6597         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
6598         struct hns3_hw *hw = &hns->hw;
6599         struct rte_kvargs *kvlist;
6600
6601         if (dev->device->devargs == NULL)
6602                 return;
6603
6604         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
6605         if (!kvlist)
6606                 return;
6607
6608         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
6609                            &hns3_parse_io_hint_func, &rx_func_hint);
6610         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
6611                            &hns3_parse_io_hint_func, &tx_func_hint);
6612         rte_kvargs_free(kvlist);
6613
6614         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6615                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
6616                           hns3_get_io_hint_func_name(rx_func_hint));
6617         hns->rx_func_hint = rx_func_hint;
6618         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
6619                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
6620                           hns3_get_io_hint_func_name(tx_func_hint));
6621         hns->tx_func_hint = tx_func_hint;
6622 }
6623
6624 static const struct eth_dev_ops hns3_eth_dev_ops = {
6625         .dev_configure      = hns3_dev_configure,
6626         .dev_start          = hns3_dev_start,
6627         .dev_stop           = hns3_dev_stop,
6628         .dev_close          = hns3_dev_close,
6629         .promiscuous_enable = hns3_dev_promiscuous_enable,
6630         .promiscuous_disable = hns3_dev_promiscuous_disable,
6631         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6632         .allmulticast_disable = hns3_dev_allmulticast_disable,
6633         .mtu_set            = hns3_dev_mtu_set,
6634         .stats_get          = hns3_stats_get,
6635         .stats_reset        = hns3_stats_reset,
6636         .xstats_get         = hns3_dev_xstats_get,
6637         .xstats_get_names   = hns3_dev_xstats_get_names,
6638         .xstats_reset       = hns3_dev_xstats_reset,
6639         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6640         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6641         .dev_infos_get          = hns3_dev_infos_get,
6642         .fw_version_get         = hns3_fw_version_get,
6643         .rx_queue_setup         = hns3_rx_queue_setup,
6644         .tx_queue_setup         = hns3_tx_queue_setup,
6645         .rx_queue_release       = hns3_dev_rx_queue_release,
6646         .tx_queue_release       = hns3_dev_tx_queue_release,
6647         .rx_queue_start         = hns3_dev_rx_queue_start,
6648         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6649         .tx_queue_start         = hns3_dev_tx_queue_start,
6650         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6651         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6652         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6653         .rxq_info_get           = hns3_rxq_info_get,
6654         .txq_info_get           = hns3_txq_info_get,
6655         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6656         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6657         .flow_ctrl_get          = hns3_flow_ctrl_get,
6658         .flow_ctrl_set          = hns3_flow_ctrl_set,
6659         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6660         .mac_addr_add           = hns3_add_mac_addr,
6661         .mac_addr_remove        = hns3_remove_mac_addr,
6662         .mac_addr_set           = hns3_set_default_mac_addr,
6663         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6664         .link_update            = hns3_dev_link_update,
6665         .rss_hash_update        = hns3_dev_rss_hash_update,
6666         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6667         .reta_update            = hns3_dev_rss_reta_update,
6668         .reta_query             = hns3_dev_rss_reta_query,
6669         .flow_ops_get           = hns3_dev_flow_ops_get,
6670         .vlan_filter_set        = hns3_vlan_filter_set,
6671         .vlan_tpid_set          = hns3_vlan_tpid_set,
6672         .vlan_offload_set       = hns3_vlan_offload_set,
6673         .vlan_pvid_set          = hns3_vlan_pvid_set,
6674         .get_reg                = hns3_get_regs,
6675         .get_module_info        = hns3_get_module_info,
6676         .get_module_eeprom      = hns3_get_module_eeprom,
6677         .get_dcb_info           = hns3_get_dcb_info,
6678         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6679         .fec_get_capability     = hns3_fec_get_capability,
6680         .fec_get                = hns3_fec_get,
6681         .fec_set                = hns3_fec_set,
6682         .tm_ops_get             = hns3_tm_ops_get,
6683         .tx_done_cleanup        = hns3_tx_done_cleanup,
6684 };
6685
6686 static const struct hns3_reset_ops hns3_reset_ops = {
6687         .reset_service       = hns3_reset_service,
6688         .stop_service        = hns3_stop_service,
6689         .prepare_reset       = hns3_prepare_reset,
6690         .wait_hardware_ready = hns3_wait_hardware_ready,
6691         .reinit_dev          = hns3_reinit_dev,
6692         .restore_conf        = hns3_restore_conf,
6693         .start_service       = hns3_start_service,
6694 };
6695
6696 static int
6697 hns3_dev_init(struct rte_eth_dev *eth_dev)
6698 {
6699         struct hns3_adapter *hns = eth_dev->data->dev_private;
6700         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6701         struct rte_ether_addr *eth_addr;
6702         struct hns3_hw *hw = &hns->hw;
6703         int ret;
6704
6705         PMD_INIT_FUNC_TRACE();
6706
6707         eth_dev->process_private = (struct hns3_process_private *)
6708             rte_zmalloc_socket("hns3_filter_list",
6709                                sizeof(struct hns3_process_private),
6710                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6711         if (eth_dev->process_private == NULL) {
6712                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6713                 return -ENOMEM;
6714         }
6715         /* initialize flow filter lists */
6716         hns3_filterlist_init(eth_dev);
6717
6718         hns3_set_rxtx_function(eth_dev);
6719         eth_dev->dev_ops = &hns3_eth_dev_ops;
6720         eth_dev->rx_queue_count = hns3_rx_queue_count;
6721         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6722                 ret = hns3_mp_init_secondary();
6723                 if (ret) {
6724                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6725                                      "process, ret = %d", ret);
6726                         goto err_mp_init_secondary;
6727                 }
6728
6729                 hw->secondary_cnt++;
6730                 return 0;
6731         }
6732
6733         ret = hns3_mp_init_primary();
6734         if (ret) {
6735                 PMD_INIT_LOG(ERR,
6736                              "Failed to init for primary process, ret = %d",
6737                              ret);
6738                 goto err_mp_init_primary;
6739         }
6740
6741         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6742         hns->is_vf = false;
6743         hw->data = eth_dev->data;
6744         hns3_parse_devargs(eth_dev);
6745
6746         /*
6747          * Set default max packet size according to the mtu
6748          * default vale in DPDK frame.
6749          */
6750         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6751
6752         ret = hns3_reset_init(hw);
6753         if (ret)
6754                 goto err_init_reset;
6755         hw->reset.ops = &hns3_reset_ops;
6756
6757         ret = hns3_init_pf(eth_dev);
6758         if (ret) {
6759                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6760                 goto err_init_pf;
6761         }
6762
6763         /* Allocate memory for storing MAC addresses */
6764         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6765                                                sizeof(struct rte_ether_addr) *
6766                                                HNS3_UC_MACADDR_NUM, 0);
6767         if (eth_dev->data->mac_addrs == NULL) {
6768                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6769                              "to store MAC addresses",
6770                              sizeof(struct rte_ether_addr) *
6771                              HNS3_UC_MACADDR_NUM);
6772                 ret = -ENOMEM;
6773                 goto err_rte_zmalloc;
6774         }
6775
6776         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6777         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6778                 rte_eth_random_addr(hw->mac.mac_addr);
6779                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6780                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6781                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6782                           "unicast address, using random MAC address %s",
6783                           mac_str);
6784         }
6785         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6786                             &eth_dev->data->mac_addrs[0]);
6787
6788         hw->adapter_state = HNS3_NIC_INITIALIZED;
6789
6790         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6791                             SCHEDULE_PENDING) {
6792                 hns3_err(hw, "Reschedule reset service after dev_init");
6793                 hns3_schedule_reset(hns);
6794         } else {
6795                 /* IMP will wait ready flag before reset */
6796                 hns3_notify_reset_ready(hw, false);
6797         }
6798
6799         hns3_info(hw, "hns3 dev initialization successful!");
6800         return 0;
6801
6802 err_rte_zmalloc:
6803         hns3_uninit_pf(eth_dev);
6804
6805 err_init_pf:
6806         rte_free(hw->reset.wait_data);
6807
6808 err_init_reset:
6809         hns3_mp_uninit_primary();
6810
6811 err_mp_init_primary:
6812 err_mp_init_secondary:
6813         eth_dev->dev_ops = NULL;
6814         eth_dev->rx_pkt_burst = NULL;
6815         eth_dev->rx_descriptor_status = NULL;
6816         eth_dev->tx_pkt_burst = NULL;
6817         eth_dev->tx_pkt_prepare = NULL;
6818         eth_dev->tx_descriptor_status = NULL;
6819         rte_free(eth_dev->process_private);
6820         eth_dev->process_private = NULL;
6821         return ret;
6822 }
6823
6824 static int
6825 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6826 {
6827         struct hns3_adapter *hns = eth_dev->data->dev_private;
6828         struct hns3_hw *hw = &hns->hw;
6829
6830         PMD_INIT_FUNC_TRACE();
6831
6832         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6833                 rte_free(eth_dev->process_private);
6834                 eth_dev->process_private = NULL;
6835                 return 0;
6836         }
6837
6838         if (hw->adapter_state < HNS3_NIC_CLOSING)
6839                 hns3_dev_close(eth_dev);
6840
6841         hw->adapter_state = HNS3_NIC_REMOVED;
6842         return 0;
6843 }
6844
6845 static int
6846 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6847                    struct rte_pci_device *pci_dev)
6848 {
6849         return rte_eth_dev_pci_generic_probe(pci_dev,
6850                                              sizeof(struct hns3_adapter),
6851                                              hns3_dev_init);
6852 }
6853
6854 static int
6855 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6856 {
6857         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6858 }
6859
6860 static const struct rte_pci_id pci_id_hns3_map[] = {
6861         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6862         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6863         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6864         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6865         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6866         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6867         { .vendor_id = 0, }, /* sentinel */
6868 };
6869
6870 static struct rte_pci_driver rte_hns3_pmd = {
6871         .id_table = pci_id_hns3_map,
6872         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6873         .probe = eth_hns3_pci_probe,
6874         .remove = eth_hns3_pci_remove,
6875 };
6876
6877 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6878 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6879 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6880 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6881                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6882                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
6883 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6884 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);