drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVALID_PVID               0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  60 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  62
  63 #define HNS3_RESET_WAIT_MS      100
  64 #define HNS3_RESET_WAIT_CNT     200
  65
  66 enum hns3_evt_cause {
  67         HNS3_VECTOR0_EVENT_RST,
  68         HNS3_VECTOR0_EVENT_MBX,
  69         HNS3_VECTOR0_EVENT_ERR,
  70         HNS3_VECTOR0_EVENT_OTHER,
  71 };
  72
  73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  74                                                  uint64_t *levels);
  75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  77                                     int on);
  78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  79
  80 static int hns3_add_mc_addr(struct hns3_hw *hw,
  81                             struct rte_ether_addr *mac_addr);
  82 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84
  85 static void
  86 hns3_pf_disable_irq0(struct hns3_hw *hw)
  87 {
  88         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  89 }
  90
  91 static void
  92 hns3_pf_enable_irq0(struct hns3_hw *hw)
  93 {
  94         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  95 }
  96
  97 static enum hns3_evt_cause
  98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  99 {
 100         struct hns3_hw *hw = &hns->hw;
 101         uint32_t vector0_int_stats;
 102         uint32_t cmdq_src_val;
 103         uint32_t hw_err_src_reg;
 104         uint32_t val;
 105         enum hns3_evt_cause ret;
 106
 107         /* fetch the events from their corresponding regs */
 108         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 109         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 110         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 154             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 155                 val = vector0_int_stats | hw_err_src_reg;
 156                 ret = HNS3_VECTOR0_EVENT_ERR;
 157                 goto out;
 158         }
 159
 160         /* check for vector0 mailbox(=CMDQ RX) event source */
 161         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 162                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 163                 val = cmdq_src_val;
 164                 ret = HNS3_VECTOR0_EVENT_MBX;
 165                 goto out;
 166         }
 167
 168         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 169                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 170                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 171         val = vector0_int_stats;
 172         ret = HNS3_VECTOR0_EVENT_OTHER;
 173 out:
 174
 175         if (clearval)
 176                 *clearval = val;
 177         return ret;
 178 }
 179
 180 static void
 181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 182 {
 183         if (event_type == HNS3_VECTOR0_EVENT_RST)
 184                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 185         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 186                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 187 }
 188
 189 static void
 190 hns3_clear_all_event_cause(struct hns3_hw *hw)
 191 {
 192         uint32_t vector0_int_stats;
 193         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 194
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 196                 hns3_warn(hw, "Probe during IMP reset interrupt");
 197
 198         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 199                 hns3_warn(hw, "Probe during Global reset interrupt");
 200
 201         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 202                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 204                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 205         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 206 }
 207
 208 static void
 209 hns3_interrupt_handler(void *param)
 210 {
 211         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 212         struct hns3_adapter *hns = dev->data->dev_private;
 213         struct hns3_hw *hw = &hns->hw;
 214         enum hns3_evt_cause event_cause;
 215         uint32_t clearval = 0;
 216
 217         /* Disable interrupt */
 218         hns3_pf_disable_irq0(hw);
 219
 220         event_cause = hns3_check_event_cause(hns, &clearval);
 221
 222         /* vector 0 interrupt is shared with reset and mailbox source events. */
 223         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 224                 hns3_warn(hw, "Received err interrupt");
 225                 hns3_handle_msix_error(hns, &hw->reset.request);
 226                 hns3_handle_ras_error(hns, &hw->reset.request);
 227                 hns3_schedule_reset(hns);
 228         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 229                 hns3_warn(hw, "Received reset interrupt");
 230                 hns3_schedule_reset(hns);
 231         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 232                 hns3_dev_handle_mbx_msg(hw);
 233         else
 234                 hns3_err(hw, "Received unknown event");
 235
 236         hns3_clear_event_cause(hw, event_cause, clearval);
 237         /* Enable interrupt if it is not cause by reset */
 238         hns3_pf_enable_irq0(hw);
 239 }
 240
 241 static int
 242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 243 {
 244 #define HNS3_VLAN_ID_OFFSET_STEP        160
 245 #define HNS3_VLAN_BYTE_SIZE             8
 246         struct hns3_vlan_filter_pf_cfg_cmd *req;
 247         struct hns3_hw *hw = &hns->hw;
 248         uint8_t vlan_offset_byte_val;
 249         struct hns3_cmd_desc desc;
 250         uint8_t vlan_offset_byte;
 251         uint8_t vlan_offset_base;
 252         int ret;
 253
 254         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 255
 256         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 257         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 258                            HNS3_VLAN_BYTE_SIZE;
 259         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 260
 261         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 262         req->vlan_offset = vlan_offset_base;
 263         req->vlan_cfg = on ? 0 : 1;
 264         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 265
 266         ret = hns3_cmd_send(hw, &desc, 1);
 267         if (ret)
 268                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 269                          vlan_id, ret);
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 276 {
 277         struct hns3_user_vlan_table *vlan_entry;
 278         struct hns3_pf *pf = &hns->pf;
 279
 280         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 281                 if (vlan_entry->vlan_id == vlan_id) {
 282                         if (vlan_entry->hd_tbl_status)
 283                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 284                         LIST_REMOVE(vlan_entry, next);
 285                         rte_free(vlan_entry);
 286                         break;
 287                 }
 288         }
 289 }
 290
 291 static void
 292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 293                         bool writen_to_tbl)
 294 {
 295         struct hns3_user_vlan_table *vlan_entry;
 296         struct hns3_hw *hw = &hns->hw;
 297         struct hns3_pf *pf = &hns->pf;
 298
 299         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 300                 if (vlan_entry->vlan_id == vlan_id)
 301                         return;
 302         }
 303
 304         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 305         if (vlan_entry == NULL) {
 306                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 307                 return;
 308         }
 309
 310         vlan_entry->hd_tbl_status = writen_to_tbl;
 311         vlan_entry->vlan_id = vlan_id;
 312
 313         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 314 }
 315
 316 static int
 317 hns3_restore_vlan_table(struct hns3_adapter *hns)
 318 {
 319         struct hns3_user_vlan_table *vlan_entry;
 320         struct hns3_hw *hw = &hns->hw;
 321         struct hns3_pf *pf = &hns->pf;
 322         uint16_t vlan_id;
 323         int ret = 0;
 324
 325         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 326                 return hns3_vlan_pvid_configure(hns,
 327                                                 hw->port_base_vlan_cfg.pvid, 1);
 328
 329         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 330                 if (vlan_entry->hd_tbl_status) {
 331                         vlan_id = vlan_entry->vlan_id;
 332                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 333                         if (ret)
 334                                 break;
 335                 }
 336         }
 337
 338         return ret;
 339 }
 340
 341 static int
 342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 343 {
 344         struct hns3_hw *hw = &hns->hw;
 345         bool writen_to_tbl = false;
 346         int ret = 0;
 347
 348         /*
 349          * When vlan filter is enabled, hardware regards packets without vlan
 350          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 351          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 352          */
 353         if (on == 0 && vlan_id == 0)
 354                 return 0;
 355
 356         /*
 357          * When port base vlan enabled, we use port base vlan as the vlan
 358          * filter condition. In this case, we don't update vlan filter table
 359          * when user add new vlan or remove exist vlan, just update the
 360          * vlan list. The vlan id in vlan list will be writen in vlan filter
 361          * table until port base vlan disabled
 362          */
 363         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 364                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 365                 writen_to_tbl = true;
 366         }
 367
 368         if (ret == 0) {
 369                 if (on)
 370                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 371                 else
 372                         hns3_rm_dev_vlan_table(hns, vlan_id);
 373         }
 374         return ret;
 375 }
 376
 377 static int
 378 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 379 {
 380         struct hns3_adapter *hns = dev->data->dev_private;
 381         struct hns3_hw *hw = &hns->hw;
 382         int ret;
 383
 384         rte_spinlock_lock(&hw->lock);
 385         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 386         rte_spinlock_unlock(&hw->lock);
 387         return ret;
 388 }
 389
 390 static int
 391 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 392                          uint16_t tpid)
 393 {
 394         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 395         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 396         struct hns3_hw *hw = &hns->hw;
 397         struct hns3_cmd_desc desc;
 398         int ret;
 399
 400         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 401              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 402                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 403                 return -EINVAL;
 404         }
 405
 406         if (tpid != RTE_ETHER_TYPE_VLAN) {
 407                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 408                 return -EINVAL;
 409         }
 410
 411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 412         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 413
 414         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 415                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 416                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 417         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 418                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 419                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 420                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 421                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 422         }
 423
 424         ret = hns3_cmd_send(hw, &desc, 1);
 425         if (ret) {
 426                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 427                          ret);
 428                 return ret;
 429         }
 430
 431         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 432
 433         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 434         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 435         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 436
 437         ret = hns3_cmd_send(hw, &desc, 1);
 438         if (ret)
 439                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 440                          ret);
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 446                    uint16_t tpid)
 447 {
 448         struct hns3_adapter *hns = dev->data->dev_private;
 449         struct hns3_hw *hw = &hns->hw;
 450         int ret;
 451
 452         rte_spinlock_lock(&hw->lock);
 453         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 454         rte_spinlock_unlock(&hw->lock);
 455         return ret;
 456 }
 457
 458 static int
 459 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 460                              struct hns3_rx_vtag_cfg *vcfg)
 461 {
 462         struct hns3_vport_vtag_rx_cfg_cmd *req;
 463         struct hns3_hw *hw = &hns->hw;
 464         struct hns3_cmd_desc desc;
 465         uint16_t vport_id;
 466         uint8_t bitmap;
 467         int ret;
 468
 469         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 470
 471         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 473                      vcfg->strip_tag1_en ? 1 : 0);
 474         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 475                      vcfg->strip_tag2_en ? 1 : 0);
 476         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 477                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 478         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 479                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 480
 481         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 482         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 483                      vcfg->strip_tag1_discard_en ? 1 : 0);
 484         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 485                      vcfg->strip_tag2_discard_en ? 1 : 0);
 486         /*
 487          * In current version VF is not supported when PF is driven by DPDK
 488          * driver, just need to configure parameters for PF vport.
 489          */
 490         vport_id = HNS3_PF_FUNC_ID;
 491         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 492         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 493         req->vf_bitmap[req->vf_offset] = bitmap;
 494
 495         ret = hns3_cmd_send(hw, &desc, 1);
 496         if (ret)
 497                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 498         return ret;
 499 }
 500
 501 static void
 502 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 503                            struct hns3_rx_vtag_cfg *vcfg)
 504 {
 505         struct hns3_pf *pf = &hns->pf;
 506         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 507 }
 508
 509 static void
 510 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 511                            struct hns3_tx_vtag_cfg *vcfg)
 512 {
 513         struct hns3_pf *pf = &hns->pf;
 514         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 515 }
 516
 517 static int
 518 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 519 {
 520         struct hns3_rx_vtag_cfg rxvlan_cfg;
 521         struct hns3_hw *hw = &hns->hw;
 522         int ret;
 523
 524         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 525                 rxvlan_cfg.strip_tag1_en = false;
 526                 rxvlan_cfg.strip_tag2_en = enable;
 527                 rxvlan_cfg.strip_tag2_discard_en = false;
 528         } else {
 529                 rxvlan_cfg.strip_tag1_en = enable;
 530                 rxvlan_cfg.strip_tag2_en = true;
 531                 rxvlan_cfg.strip_tag2_discard_en = true;
 532         }
 533
 534         rxvlan_cfg.strip_tag1_discard_en = false;
 535         rxvlan_cfg.vlan1_vlan_prionly = false;
 536         rxvlan_cfg.vlan2_vlan_prionly = false;
 537         rxvlan_cfg.rx_vlan_offload_en = enable;
 538
 539         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 540         if (ret) {
 541                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 542                 return ret;
 543         }
 544
 545         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 546
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 552                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 553 {
 554         struct hns3_vlan_filter_ctrl_cmd *req;
 555         struct hns3_cmd_desc desc;
 556         int ret;
 557
 558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 559
 560         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 561         req->vlan_type = vlan_type;
 562         req->vlan_fe = filter_en ? fe_type : 0;
 563         req->vf_id = vf_id;
 564
 565         ret = hns3_cmd_send(hw, &desc, 1);
 566         if (ret)
 567                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 568
 569         return ret;
 570 }
 571
 572 static int
 573 hns3_vlan_filter_init(struct hns3_adapter *hns)
 574 {
 575         struct hns3_hw *hw = &hns->hw;
 576         int ret;
 577
 578         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 579                                         HNS3_FILTER_FE_EGRESS, false,
 580                                         HNS3_PF_FUNC_ID);
 581         if (ret) {
 582                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 583                 return ret;
 584         }
 585
 586         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 587                                         HNS3_FILTER_FE_INGRESS, false,
 588                                         HNS3_PF_FUNC_ID);
 589         if (ret)
 590                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 591
 592         return ret;
 593 }
 594
 595 static int
 596 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 597 {
 598         struct hns3_hw *hw = &hns->hw;
 599         int ret;
 600
 601         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 602                                         HNS3_FILTER_FE_INGRESS, enable,
 603                                         HNS3_PF_FUNC_ID);
 604         if (ret)
 605                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 606                          enable ? "enable" : "disable", ret);
 607
 608         return ret;
 609 }
 610
 611 static int
 612 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 613 {
 614         struct hns3_adapter *hns = dev->data->dev_private;
 615         struct hns3_hw *hw = &hns->hw;
 616         struct rte_eth_rxmode *rxmode;
 617         unsigned int tmp_mask;
 618         bool enable;
 619         int ret = 0;
 620
 621         rte_spinlock_lock(&hw->lock);
 622         rxmode = &dev->data->dev_conf.rxmode;
 623         tmp_mask = (unsigned int)mask;
 624         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 625                 /* ignore vlan filter configuration during promiscuous mode */
 626                 if (!dev->data->promiscuous) {
 627                         /* Enable or disable VLAN filter */
 628                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 629                                  true : false;
 630
 631                         ret = hns3_enable_vlan_filter(hns, enable);
 632                         if (ret) {
 633                                 rte_spinlock_unlock(&hw->lock);
 634                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 635                                          enable ? "enable" : "disable", ret);
 636                                 return ret;
 637                         }
 638                 }
 639         }
 640
 641         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 642                 /* Enable or disable VLAN stripping */
 643                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 644                     true : false;
 645
 646                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 647                 if (ret) {
 648                         rte_spinlock_unlock(&hw->lock);
 649                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 650                                  enable ? "enable" : "disable", ret);
 651                         return ret;
 652                 }
 653         }
 654
 655         rte_spinlock_unlock(&hw->lock);
 656
 657         return ret;
 658 }
 659
 660 static int
 661 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 662                              struct hns3_tx_vtag_cfg *vcfg)
 663 {
 664         struct hns3_vport_vtag_tx_cfg_cmd *req;
 665         struct hns3_cmd_desc desc;
 666         struct hns3_hw *hw = &hns->hw;
 667         uint16_t vport_id;
 668         uint8_t bitmap;
 669         int ret;
 670
 671         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 672
 673         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 674         req->def_vlan_tag1 = vcfg->default_tag1;
 675         req->def_vlan_tag2 = vcfg->default_tag2;
 676         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 677                      vcfg->accept_tag1 ? 1 : 0);
 678         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 679                      vcfg->accept_untag1 ? 1 : 0);
 680         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 681                      vcfg->accept_tag2 ? 1 : 0);
 682         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 683                      vcfg->accept_untag2 ? 1 : 0);
 684         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 685                      vcfg->insert_tag1_en ? 1 : 0);
 686         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 687                      vcfg->insert_tag2_en ? 1 : 0);
 688         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 689
 690         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 691         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 692                      vcfg->tag_shift_mode_en ? 1 : 0);
 693
 694         /*
 695          * In current version VF is not supported when PF is driven by DPDK
 696          * driver, just need to configure parameters for PF vport.
 697          */
 698         vport_id = HNS3_PF_FUNC_ID;
 699         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 700         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 701         req->vf_bitmap[req->vf_offset] = bitmap;
 702
 703         ret = hns3_cmd_send(hw, &desc, 1);
 704         if (ret)
 705                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 706
 707         return ret;
 708 }
 709
 710 static int
 711 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 712                      uint16_t pvid)
 713 {
 714         struct hns3_hw *hw = &hns->hw;
 715         struct hns3_tx_vtag_cfg txvlan_cfg;
 716         int ret;
 717
 718         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 719                 txvlan_cfg.accept_tag1 = true;
 720                 txvlan_cfg.insert_tag1_en = false;
 721                 txvlan_cfg.default_tag1 = 0;
 722         } else {
 723                 txvlan_cfg.accept_tag1 =
 724                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 725                 txvlan_cfg.insert_tag1_en = true;
 726                 txvlan_cfg.default_tag1 = pvid;
 727         }
 728
 729         txvlan_cfg.accept_untag1 = true;
 730         txvlan_cfg.accept_tag2 = true;
 731         txvlan_cfg.accept_untag2 = true;
 732         txvlan_cfg.insert_tag2_en = false;
 733         txvlan_cfg.default_tag2 = 0;
 734         txvlan_cfg.tag_shift_mode_en = true;
 735
 736         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 737         if (ret) {
 738                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 739                          ret);
 740                 return ret;
 741         }
 742
 743         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 744         return ret;
 745 }
 746
 747
 748 static void
 749 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 750 {
 751         struct hns3_user_vlan_table *vlan_entry;
 752         struct hns3_pf *pf = &hns->pf;
 753
 754         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 755                 if (vlan_entry->hd_tbl_status) {
 756                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 757                         vlan_entry->hd_tbl_status = false;
 758                 }
 759         }
 760
 761         if (is_del_list) {
 762                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 763                 while (vlan_entry) {
 764                         LIST_REMOVE(vlan_entry, next);
 765                         rte_free(vlan_entry);
 766                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 767                 }
 768         }
 769 }
 770
 771 static void
 772 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_user_vlan_table *vlan_entry;
 775         struct hns3_pf *pf = &hns->pf;
 776
 777         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 778                 if (!vlan_entry->hd_tbl_status) {
 779                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 780                         vlan_entry->hd_tbl_status = true;
 781                 }
 782         }
 783 }
 784
 785 static void
 786 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 787 {
 788         struct hns3_hw *hw = &hns->hw;
 789         int ret;
 790
 791         hns3_rm_all_vlan_table(hns, true);
 792         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 793                 ret = hns3_set_port_vlan_filter(hns,
 794                                                 hw->port_base_vlan_cfg.pvid, 0);
 795                 if (ret) {
 796                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 797                                  ret);
 798                         return;
 799                 }
 800         }
 801 }
 802
 803 static int
 804 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 805                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 806 {
 807         struct hns3_hw *hw = &hns->hw;
 808         uint16_t old_pvid;
 809         int ret;
 810
 811         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 812                 old_pvid = hw->port_base_vlan_cfg.pvid;
 813                 if (old_pvid != HNS3_INVALID_PVID) {
 814                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 815                         if (ret) {
 816                                 hns3_err(hw, "failed to remove old pvid %u, "
 817                                                 "ret = %d", old_pvid, ret);
 818                                 return ret;
 819                         }
 820                 }
 821
 822                 hns3_rm_all_vlan_table(hns, false);
 823                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 824                 if (ret) {
 825                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 826                                         new_pvid, ret);
 827                         return ret;
 828                 }
 829         } else {
 830                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 831                 if (ret) {
 832                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 833                                         new_pvid, ret);
 834                         return ret;
 835                 }
 836
 837                 hns3_add_all_vlan_table(hns);
 838         }
 839         return 0;
 840 }
 841
 842 static int
 843 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 844 {
 845         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 846         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 847         bool rx_strip_en;
 848         int ret;
 849
 850         rx_strip_en = old_cfg->rx_vlan_offload_en;
 851         if (on) {
 852                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 853                 rx_vlan_cfg.strip_tag2_en = true;
 854                 rx_vlan_cfg.strip_tag2_discard_en = true;
 855         } else {
 856                 rx_vlan_cfg.strip_tag1_en = false;
 857                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 858                 rx_vlan_cfg.strip_tag2_discard_en = false;
 859         }
 860         rx_vlan_cfg.strip_tag1_discard_en = false;
 861         rx_vlan_cfg.vlan1_vlan_prionly = false;
 862         rx_vlan_cfg.vlan2_vlan_prionly = false;
 863         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 864
 865         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 866         if (ret)
 867                 return ret;
 868
 869         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 870         return ret;
 871 }
 872
 873 static int
 874 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 875 {
 876         struct hns3_hw *hw = &hns->hw;
 877         uint16_t port_base_vlan_state;
 878         int ret;
 879
 880         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 881                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 882                         hns3_warn(hw, "Invalid operation! As current pvid set "
 883                                   "is %u, disable pvid %u is invalid",
 884                                   hw->port_base_vlan_cfg.pvid, pvid);
 885                 return 0;
 886         }
 887
 888         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 889                                     HNS3_PORT_BASE_VLAN_DISABLE;
 890         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 891         if (ret) {
 892                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 893                          ret);
 894                 return ret;
 895         }
 896
 897         ret = hns3_en_pvid_strip(hns, on);
 898         if (ret) {
 899                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 900                          "ret = %d", ret);
 901                 return ret;
 902         }
 903
 904         if (pvid == HNS3_INVALID_PVID)
 905                 goto out;
 906         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 907         if (ret) {
 908                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 909                          ret);
 910                 return ret;
 911         }
 912
 913 out:
 914         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 915         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 916         return ret;
 917 }
 918
 919 static int
 920 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 921 {
 922         struct hns3_adapter *hns = dev->data->dev_private;
 923         struct hns3_hw *hw = &hns->hw;
 924         bool pvid_en_state_change;
 925         uint16_t pvid_state;
 926         int ret;
 927
 928         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 929                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 930                          RTE_ETHER_MAX_VLAN_ID);
 931                 return -EINVAL;
 932         }
 933
 934         /*
 935          * If PVID configuration state change, should refresh the PVID
 936          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 937          */
 938         pvid_state = hw->port_base_vlan_cfg.state;
 939         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 940             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 941                 pvid_en_state_change = false;
 942         else
 943                 pvid_en_state_change = true;
 944
 945         rte_spinlock_lock(&hw->lock);
 946         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 947         rte_spinlock_unlock(&hw->lock);
 948         if (ret)
 949                 return ret;
 950         /*
 951          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
 952          * need be processed by PMD driver.
 953          */
 954         if (pvid_en_state_change &&
 955             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
 956                 hns3_update_all_queues_pvid_proc_en(hw);
 957
 958         return 0;
 959 }
 960
 961 static int
 962 hns3_default_vlan_config(struct hns3_adapter *hns)
 963 {
 964         struct hns3_hw *hw = &hns->hw;
 965         int ret;
 966
 967         /*
 968          * When vlan filter is enabled, hardware regards packets without vlan
 969          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
 970          * table, packets without vlan won't be received. So, add vlan 0 as
 971          * the default vlan.
 972          */
 973         ret = hns3_vlan_filter_configure(hns, 0, 1);
 974         if (ret)
 975                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_init_vlan_config(struct hns3_adapter *hns)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         int ret;
 984
 985         /*
 986          * This function can be called in the initialization and reset process,
 987          * when in reset process, it means that hardware had been reseted
 988          * successfully and we need to restore the hardware configuration to
 989          * ensure that the hardware configuration remains unchanged before and
 990          * after reset.
 991          */
 992         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 993                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 994                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
 995         }
 996
 997         ret = hns3_vlan_filter_init(hns);
 998         if (ret) {
 999                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1004                                        RTE_ETHER_TYPE_VLAN);
1005         if (ret) {
1006                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1007                 return ret;
1008         }
1009
1010         /*
1011          * When in the reinit dev stage of the reset process, the following
1012          * vlan-related configurations may differ from those at initialization,
1013          * we will restore configurations to hardware in hns3_restore_vlan_table
1014          * and hns3_restore_vlan_conf later.
1015          */
1016         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1017                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1018                 if (ret) {
1019                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1020                         return ret;
1021                 }
1022
1023                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1024                 if (ret) {
1025                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1026                                  ret);
1027                         return ret;
1028                 }
1029         }
1030
1031         return hns3_default_vlan_config(hns);
1032 }
1033
1034 static int
1035 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1036 {
1037         struct hns3_pf *pf = &hns->pf;
1038         struct hns3_hw *hw = &hns->hw;
1039         uint64_t offloads;
1040         bool enable;
1041         int ret;
1042
1043         if (!hw->data->promiscuous) {
1044                 /* restore vlan filter states */
1045                 offloads = hw->data->dev_conf.rxmode.offloads;
1046                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1047                 ret = hns3_enable_vlan_filter(hns, enable);
1048                 if (ret) {
1049                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1050                                  "ret = %d", ret);
1051                         return ret;
1052                 }
1053         }
1054
1055         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1056         if (ret) {
1057                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1058                 return ret;
1059         }
1060
1061         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1062         if (ret)
1063                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1064
1065         return ret;
1066 }
1067
1068 static int
1069 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1070 {
1071         struct hns3_adapter *hns = dev->data->dev_private;
1072         struct rte_eth_dev_data *data = dev->data;
1073         struct rte_eth_txmode *txmode;
1074         struct hns3_hw *hw = &hns->hw;
1075         int mask;
1076         int ret;
1077
1078         txmode = &data->dev_conf.txmode;
1079         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1080                 hns3_warn(hw,
1081                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1082                           "configuration is not supported! Ignore these two "
1083                           "parameters: hw_vlan_reject_tagged(%d), "
1084                           "hw_vlan_reject_untagged(%d)",
1085                           txmode->hw_vlan_reject_tagged,
1086                           txmode->hw_vlan_reject_untagged);
1087
1088         /* Apply vlan offload setting */
1089         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1090         ret = hns3_vlan_offload_set(dev, mask);
1091         if (ret) {
1092                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1093                          ret);
1094                 return ret;
1095         }
1096
1097         /*
1098          * If pvid config is not set in rte_eth_conf, driver needn't to set
1099          * VLAN pvid related configuration to hardware.
1100          */
1101         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1102                 return 0;
1103
1104         /* Apply pvid setting */
1105         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1106                                  txmode->hw_vlan_insert_pvid);
1107         if (ret)
1108                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1109                          txmode->pvid, ret);
1110
1111         return ret;
1112 }
1113
1114 static int
1115 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1116                 unsigned int tso_mss_max)
1117 {
1118         struct hns3_cfg_tso_status_cmd *req;
1119         struct hns3_cmd_desc desc;
1120         uint16_t tso_mss;
1121
1122         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1123
1124         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1125
1126         tso_mss = 0;
1127         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1128                        tso_mss_min);
1129         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1130
1131         tso_mss = 0;
1132         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1133                        tso_mss_max);
1134         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1135
1136         return hns3_cmd_send(hw, &desc, 1);
1137 }
1138
1139 static int
1140 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1141                    uint16_t *allocated_size, bool is_alloc)
1142 {
1143         struct hns3_umv_spc_alc_cmd *req;
1144         struct hns3_cmd_desc desc;
1145         int ret;
1146
1147         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1148         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1149         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1150         req->space_size = rte_cpu_to_le_32(space_size);
1151
1152         ret = hns3_cmd_send(hw, &desc, 1);
1153         if (ret) {
1154                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1155                              is_alloc ? "allocate" : "free", ret);
1156                 return ret;
1157         }
1158
1159         if (is_alloc && allocated_size)
1160                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1161
1162         return 0;
1163 }
1164
1165 static int
1166 hns3_init_umv_space(struct hns3_hw *hw)
1167 {
1168         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169         struct hns3_pf *pf = &hns->pf;
1170         uint16_t allocated_size = 0;
1171         int ret;
1172
1173         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1174                                  true);
1175         if (ret)
1176                 return ret;
1177
1178         if (allocated_size < pf->wanted_umv_size)
1179                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1180                              pf->wanted_umv_size, allocated_size);
1181
1182         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1183                                                 pf->wanted_umv_size;
1184         pf->used_umv_size = 0;
1185         return 0;
1186 }
1187
1188 static int
1189 hns3_uninit_umv_space(struct hns3_hw *hw)
1190 {
1191         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1192         struct hns3_pf *pf = &hns->pf;
1193         int ret;
1194
1195         if (pf->max_umv_size == 0)
1196                 return 0;
1197
1198         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1199         if (ret)
1200                 return ret;
1201
1202         pf->max_umv_size = 0;
1203
1204         return 0;
1205 }
1206
1207 static bool
1208 hns3_is_umv_space_full(struct hns3_hw *hw)
1209 {
1210         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1211         struct hns3_pf *pf = &hns->pf;
1212         bool is_full;
1213
1214         is_full = (pf->used_umv_size >= pf->max_umv_size);
1215
1216         return is_full;
1217 }
1218
1219 static void
1220 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1221 {
1222         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1223         struct hns3_pf *pf = &hns->pf;
1224
1225         if (is_free) {
1226                 if (pf->used_umv_size > 0)
1227                         pf->used_umv_size--;
1228         } else
1229                 pf->used_umv_size++;
1230 }
1231
1232 static void
1233 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1234                       const uint8_t *addr, bool is_mc)
1235 {
1236         const unsigned char *mac_addr = addr;
1237         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1238                             ((uint32_t)mac_addr[2] << 16) |
1239                             ((uint32_t)mac_addr[1] << 8) |
1240                             (uint32_t)mac_addr[0];
1241         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1242
1243         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1244         if (is_mc) {
1245                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1246                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1247                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1248         }
1249
1250         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1251         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1252 }
1253
1254 static int
1255 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1256                              uint8_t resp_code,
1257                              enum hns3_mac_vlan_tbl_opcode op)
1258 {
1259         if (cmdq_resp) {
1260                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1261                          cmdq_resp);
1262                 return -EIO;
1263         }
1264
1265         if (op == HNS3_MAC_VLAN_ADD) {
1266                 if (resp_code == 0 || resp_code == 1) {
1267                         return 0;
1268                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1269                         hns3_err(hw, "add mac addr failed for uc_overflow");
1270                         return -ENOSPC;
1271                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1272                         hns3_err(hw, "add mac addr failed for mc_overflow");
1273                         return -ENOSPC;
1274                 }
1275
1276                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1277                          resp_code);
1278                 return -EIO;
1279         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1280                 if (resp_code == 0) {
1281                         return 0;
1282                 } else if (resp_code == 1) {
1283                         hns3_dbg(hw, "remove mac addr failed for miss");
1284                         return -ENOENT;
1285                 }
1286
1287                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1288                          resp_code);
1289                 return -EIO;
1290         } else if (op == HNS3_MAC_VLAN_LKUP) {
1291                 if (resp_code == 0) {
1292                         return 0;
1293                 } else if (resp_code == 1) {
1294                         hns3_dbg(hw, "lookup mac addr failed for miss");
1295                         return -ENOENT;
1296                 }
1297
1298                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1299                          resp_code);
1300                 return -EIO;
1301         }
1302
1303         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1304                  op);
1305
1306         return -EINVAL;
1307 }
1308
1309 static int
1310 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1311                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1312                          struct hns3_cmd_desc *desc, bool is_mc)
1313 {
1314         uint8_t resp_code;
1315         uint16_t retval;
1316         int ret;
1317
1318         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1319         if (is_mc) {
1320                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1321                 memcpy(desc[0].data, req,
1322                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1323                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1324                                           true);
1325                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1326                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1327                                           true);
1328                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1329         } else {
1330                 memcpy(desc[0].data, req,
1331                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1332                 ret = hns3_cmd_send(hw, desc, 1);
1333         }
1334         if (ret) {
1335                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1336                          ret);
1337                 return ret;
1338         }
1339         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1340         retval = rte_le_to_cpu_16(desc[0].retval);
1341
1342         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343                                             HNS3_MAC_VLAN_LKUP);
1344 }
1345
1346 static int
1347 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1348                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1349                       struct hns3_cmd_desc *mc_desc)
1350 {
1351         uint8_t resp_code;
1352         uint16_t retval;
1353         int cfg_status;
1354         int ret;
1355
1356         if (mc_desc == NULL) {
1357                 struct hns3_cmd_desc desc;
1358
1359                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1360                 memcpy(desc.data, req,
1361                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1362                 ret = hns3_cmd_send(hw, &desc, 1);
1363                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1364                 retval = rte_le_to_cpu_16(desc.retval);
1365
1366                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1367                                                           HNS3_MAC_VLAN_ADD);
1368         } else {
1369                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1370                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1371                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1372                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1373                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1374                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1375                 memcpy(mc_desc[0].data, req,
1376                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1377                 mc_desc[0].retval = 0;
1378                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1379                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1380                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1381
1382                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1383                                                           HNS3_MAC_VLAN_ADD);
1384         }
1385
1386         if (ret) {
1387                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1388                 return ret;
1389         }
1390
1391         return cfg_status;
1392 }
1393
1394 static int
1395 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1396                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1397 {
1398         struct hns3_cmd_desc desc;
1399         uint8_t resp_code;
1400         uint16_t retval;
1401         int ret;
1402
1403         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1404
1405         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1406
1407         ret = hns3_cmd_send(hw, &desc, 1);
1408         if (ret) {
1409                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1410                 return ret;
1411         }
1412         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1413         retval = rte_le_to_cpu_16(desc.retval);
1414
1415         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1416                                             HNS3_MAC_VLAN_REMOVE);
1417 }
1418
1419 static int
1420 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1421 {
1422         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1423         struct hns3_mac_vlan_tbl_entry_cmd req;
1424         struct hns3_pf *pf = &hns->pf;
1425         struct hns3_cmd_desc desc[3];
1426         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1427         uint16_t egress_port = 0;
1428         uint8_t vf_id;
1429         int ret;
1430
1431         /* check if mac addr is valid */
1432         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1433                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1434                                       mac_addr);
1435                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1436                          mac_str);
1437                 return -EINVAL;
1438         }
1439
1440         memset(&req, 0, sizeof(req));
1441
1442         /*
1443          * In current version VF is not supported when PF is driven by DPDK
1444          * driver, just need to configure parameters for PF vport.
1445          */
1446         vf_id = HNS3_PF_FUNC_ID;
1447         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1448                        HNS3_MAC_EPORT_VFID_S, vf_id);
1449
1450         req.egress_port = rte_cpu_to_le_16(egress_port);
1451
1452         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1453
1454         /*
1455          * Lookup the mac address in the mac_vlan table, and add
1456          * it if the entry is inexistent. Repeated unicast entry
1457          * is not allowed in the mac vlan table.
1458          */
1459         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1460         if (ret == -ENOENT) {
1461                 if (!hns3_is_umv_space_full(hw)) {
1462                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1463                         if (!ret)
1464                                 hns3_update_umv_space(hw, false);
1465                         return ret;
1466                 }
1467
1468                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1469
1470                 return -ENOSPC;
1471         }
1472
1473         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1474
1475         /* check if we just hit the duplicate */
1476         if (ret == 0) {
1477                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1478                 return 0;
1479         }
1480
1481         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1482                  mac_str);
1483
1484         return ret;
1485 }
1486
1487 static int
1488 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1489 {
1490         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1491         struct rte_ether_addr *addr;
1492         int ret;
1493         int i;
1494
1495         for (i = 0; i < hw->mc_addrs_num; i++) {
1496                 addr = &hw->mc_addrs[i];
1497                 /* Check if there are duplicate addresses */
1498                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1499                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1500                                               addr);
1501                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1502                                  "(%s) is added by the set_mc_mac_addr_list "
1503                                  "API", mac_str);
1504                         return -EINVAL;
1505                 }
1506         }
1507
1508         ret = hns3_add_mc_addr(hw, mac_addr);
1509         if (ret) {
1510                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1511                                       mac_addr);
1512                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1513                          mac_str, ret);
1514         }
1515         return ret;
1516 }
1517
1518 static int
1519 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1520 {
1521         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1522         int ret;
1523
1524         ret = hns3_remove_mc_addr(hw, mac_addr);
1525         if (ret) {
1526                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1527                                       mac_addr);
1528                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1529                          mac_str, ret);
1530         }
1531         return ret;
1532 }
1533
1534 static int
1535 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1536                   uint32_t idx, __rte_unused uint32_t pool)
1537 {
1538         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1540         int ret;
1541
1542         rte_spinlock_lock(&hw->lock);
1543
1544         /*
1545          * In hns3 network engine adding UC and MC mac address with different
1546          * commands with firmware. We need to determine whether the input
1547          * address is a UC or a MC address to call different commands.
1548          * By the way, it is recommended calling the API function named
1549          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1550          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1551          * may affect the specifications of UC mac addresses.
1552          */
1553         if (rte_is_multicast_ether_addr(mac_addr))
1554                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1555         else
1556                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1557
1558         if (ret) {
1559                 rte_spinlock_unlock(&hw->lock);
1560                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1561                                       mac_addr);
1562                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1563                          ret);
1564                 return ret;
1565         }
1566
1567         if (idx == 0)
1568                 hw->mac.default_addr_setted = true;
1569         rte_spinlock_unlock(&hw->lock);
1570
1571         return ret;
1572 }
1573
1574 static int
1575 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1576 {
1577         struct hns3_mac_vlan_tbl_entry_cmd req;
1578         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1579         int ret;
1580
1581         /* check if mac addr is valid */
1582         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1583                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1584                                       mac_addr);
1585                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1586                          mac_str);
1587                 return -EINVAL;
1588         }
1589
1590         memset(&req, 0, sizeof(req));
1591         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1592         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1593         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1594         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1595                 return 0;
1596         else if (ret == 0)
1597                 hns3_update_umv_space(hw, true);
1598
1599         return ret;
1600 }
1601
1602 static void
1603 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1604 {
1605         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         /* index will be checked by upper level rte interface */
1607         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1608         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609         int ret;
1610
1611         rte_spinlock_lock(&hw->lock);
1612
1613         if (rte_is_multicast_ether_addr(mac_addr))
1614                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1615         else
1616                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1617         rte_spinlock_unlock(&hw->lock);
1618         if (ret) {
1619                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                       mac_addr);
1621                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1622                          ret);
1623         }
1624 }
1625
1626 static int
1627 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1628                           struct rte_ether_addr *mac_addr)
1629 {
1630         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct rte_ether_addr *oaddr;
1632         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1633         bool default_addr_setted;
1634         bool rm_succes = false;
1635         int ret, ret_val;
1636
1637         /*
1638          * It has been guaranteed that input parameter named mac_addr is valid
1639          * address in the rte layer of DPDK framework.
1640          */
1641         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1642         default_addr_setted = hw->mac.default_addr_setted;
1643         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1644                 return 0;
1645
1646         rte_spinlock_lock(&hw->lock);
1647         if (default_addr_setted) {
1648                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1649                 if (ret) {
1650                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1651                                               oaddr);
1652                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1653                                   mac_str, ret);
1654                         rm_succes = false;
1655                 } else
1656                         rm_succes = true;
1657         }
1658
1659         ret = hns3_add_uc_addr_common(hw, mac_addr);
1660         if (ret) {
1661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1662                                       mac_addr);
1663                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1664                 goto err_add_uc_addr;
1665         }
1666
1667         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1668         if (ret) {
1669                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1670                 goto err_pause_addr_cfg;
1671         }
1672
1673         rte_ether_addr_copy(mac_addr,
1674                             (struct rte_ether_addr *)hw->mac.mac_addr);
1675         hw->mac.default_addr_setted = true;
1676         rte_spinlock_unlock(&hw->lock);
1677
1678         return 0;
1679
1680 err_pause_addr_cfg:
1681         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1682         if (ret_val) {
1683                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1684                                       mac_addr);
1685                 hns3_warn(hw,
1686                           "Failed to roll back to del setted mac addr(%s): %d",
1687                           mac_str, ret_val);
1688         }
1689
1690 err_add_uc_addr:
1691         if (rm_succes) {
1692                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1693                 if (ret_val) {
1694                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1695                                               oaddr);
1696                         hns3_warn(hw,
1697                                   "Failed to restore old uc mac addr(%s): %d",
1698                                   mac_str, ret_val);
1699                         hw->mac.default_addr_setted = false;
1700                 }
1701         }
1702         rte_spinlock_unlock(&hw->lock);
1703
1704         return ret;
1705 }
1706
1707 static int
1708 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1709 {
1710         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1711         struct hns3_hw *hw = &hns->hw;
1712         struct rte_ether_addr *addr;
1713         int err = 0;
1714         int ret;
1715         int i;
1716
1717         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1718                 addr = &hw->data->mac_addrs[i];
1719                 if (rte_is_zero_ether_addr(addr))
1720                         continue;
1721                 if (rte_is_multicast_ether_addr(addr))
1722                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1723                               hns3_add_mc_addr(hw, addr);
1724                 else
1725                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1726                               hns3_add_uc_addr_common(hw, addr);
1727
1728                 if (ret) {
1729                         err = ret;
1730                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1731                                               addr);
1732                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1733                                  "ret = %d.", del ? "remove" : "restore",
1734                                  mac_str, i, ret);
1735                 }
1736         }
1737         return err;
1738 }
1739
1740 static void
1741 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1742 {
1743 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1744         uint8_t word_num;
1745         uint8_t bit_num;
1746
1747         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1748                 word_num = vfid / 32;
1749                 bit_num = vfid % 32;
1750                 if (clr)
1751                         desc[1].data[word_num] &=
1752                             rte_cpu_to_le_32(~(1UL << bit_num));
1753                 else
1754                         desc[1].data[word_num] |=
1755                             rte_cpu_to_le_32(1UL << bit_num);
1756         } else {
1757                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1758                 bit_num = vfid % 32;
1759                 if (clr)
1760                         desc[2].data[word_num] &=
1761                             rte_cpu_to_le_32(~(1UL << bit_num));
1762                 else
1763                         desc[2].data[word_num] |=
1764                             rte_cpu_to_le_32(1UL << bit_num);
1765         }
1766 }
1767
1768 static int
1769 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1770 {
1771         struct hns3_mac_vlan_tbl_entry_cmd req;
1772         struct hns3_cmd_desc desc[3];
1773         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1774         uint8_t vf_id;
1775         int ret;
1776
1777         /* Check if mac addr is valid */
1778         if (!rte_is_multicast_ether_addr(mac_addr)) {
1779                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780                                       mac_addr);
1781                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1782                          mac_str);
1783                 return -EINVAL;
1784         }
1785
1786         memset(&req, 0, sizeof(req));
1787         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1788         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1789         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1790         if (ret) {
1791                 /* This mac addr do not exist, add new entry for it */
1792                 memset(desc[0].data, 0, sizeof(desc[0].data));
1793                 memset(desc[1].data, 0, sizeof(desc[0].data));
1794                 memset(desc[2].data, 0, sizeof(desc[0].data));
1795         }
1796
1797         /*
1798          * In current version VF is not supported when PF is driven by DPDK
1799          * driver, just need to configure parameters for PF vport.
1800          */
1801         vf_id = HNS3_PF_FUNC_ID;
1802         hns3_update_desc_vfid(desc, vf_id, false);
1803         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1804         if (ret) {
1805                 if (ret == -ENOSPC)
1806                         hns3_err(hw, "mc mac vlan table is full");
1807                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1808                                       mac_addr);
1809                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1810         }
1811
1812         return ret;
1813 }
1814
1815 static int
1816 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1817 {
1818         struct hns3_mac_vlan_tbl_entry_cmd req;
1819         struct hns3_cmd_desc desc[3];
1820         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1821         uint8_t vf_id;
1822         int ret;
1823
1824         /* Check if mac addr is valid */
1825         if (!rte_is_multicast_ether_addr(mac_addr)) {
1826                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1827                                       mac_addr);
1828                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1829                          mac_str);
1830                 return -EINVAL;
1831         }
1832
1833         memset(&req, 0, sizeof(req));
1834         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1835         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1836         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1837         if (ret == 0) {
1838                 /*
1839                  * This mac addr exist, remove this handle's VFID for it.
1840                  * In current version VF is not supported when PF is driven by
1841                  * DPDK driver, just need to configure parameters for PF vport.
1842                  */
1843                 vf_id = HNS3_PF_FUNC_ID;
1844                 hns3_update_desc_vfid(desc, vf_id, true);
1845
1846                 /* All the vfid is zero, so need to delete this entry */
1847                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1848         } else if (ret == -ENOENT) {
1849                 /* This mac addr doesn't exist. */
1850                 return 0;
1851         }
1852
1853         if (ret) {
1854                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1855                                       mac_addr);
1856                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1857         }
1858
1859         return ret;
1860 }
1861
1862 static int
1863 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1864                            struct rte_ether_addr *mc_addr_set,
1865                            uint32_t nb_mc_addr)
1866 {
1867         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1868         struct rte_ether_addr *addr;
1869         uint32_t i;
1870         uint32_t j;
1871
1872         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1873                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1874                          "invalid. valid range: 0~%d",
1875                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1876                 return -EINVAL;
1877         }
1878
1879         /* Check if input mac addresses are valid */
1880         for (i = 0; i < nb_mc_addr; i++) {
1881                 addr = &mc_addr_set[i];
1882                 if (!rte_is_multicast_ether_addr(addr)) {
1883                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1884                                               addr);
1885                         hns3_err(hw,
1886                                  "failed to set mc mac addr, addr(%s) invalid.",
1887                                  mac_str);
1888                         return -EINVAL;
1889                 }
1890
1891                 /* Check if there are duplicate addresses */
1892                 for (j = i + 1; j < nb_mc_addr; j++) {
1893                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1894                                 rte_ether_format_addr(mac_str,
1895                                                       RTE_ETHER_ADDR_FMT_SIZE,
1896                                                       addr);
1897                                 hns3_err(hw, "failed to set mc mac addr, "
1898                                          "addrs invalid. two same addrs(%s).",
1899                                          mac_str);
1900                                 return -EINVAL;
1901                         }
1902                 }
1903
1904                 /*
1905                  * Check if there are duplicate addresses between mac_addrs
1906                  * and mc_addr_set
1907                  */
1908                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1909                         if (rte_is_same_ether_addr(addr,
1910                                                    &hw->data->mac_addrs[j])) {
1911                                 rte_ether_format_addr(mac_str,
1912                                                       RTE_ETHER_ADDR_FMT_SIZE,
1913                                                       addr);
1914                                 hns3_err(hw, "failed to set mc mac addr, "
1915                                          "addrs invalid. addrs(%s) has already "
1916                                          "configured in mac_addr add API",
1917                                          mac_str);
1918                                 return -EINVAL;
1919                         }
1920                 }
1921         }
1922
1923         return 0;
1924 }
1925
1926 static void
1927 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1928                            struct rte_ether_addr *mc_addr_set,
1929                            int mc_addr_num,
1930                            struct rte_ether_addr *reserved_addr_list,
1931                            int *reserved_addr_num,
1932                            struct rte_ether_addr *add_addr_list,
1933                            int *add_addr_num,
1934                            struct rte_ether_addr *rm_addr_list,
1935                            int *rm_addr_num)
1936 {
1937         struct rte_ether_addr *addr;
1938         int current_addr_num;
1939         int reserved_num = 0;
1940         int add_num = 0;
1941         int rm_num = 0;
1942         int num;
1943         int i;
1944         int j;
1945         bool same_addr;
1946
1947         /* Calculate the mc mac address list that should be removed */
1948         current_addr_num = hw->mc_addrs_num;
1949         for (i = 0; i < current_addr_num; i++) {
1950                 addr = &hw->mc_addrs[i];
1951                 same_addr = false;
1952                 for (j = 0; j < mc_addr_num; j++) {
1953                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1954                                 same_addr = true;
1955                                 break;
1956                         }
1957                 }
1958
1959                 if (!same_addr) {
1960                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1961                         rm_num++;
1962                 } else {
1963                         rte_ether_addr_copy(addr,
1964                                             &reserved_addr_list[reserved_num]);
1965                         reserved_num++;
1966                 }
1967         }
1968
1969         /* Calculate the mc mac address list that should be added */
1970         for (i = 0; i < mc_addr_num; i++) {
1971                 addr = &mc_addr_set[i];
1972                 same_addr = false;
1973                 for (j = 0; j < current_addr_num; j++) {
1974                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1975                                 same_addr = true;
1976                                 break;
1977                         }
1978                 }
1979
1980                 if (!same_addr) {
1981                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1982                         add_num++;
1983                 }
1984         }
1985
1986         /* Reorder the mc mac address list maintained by driver */
1987         for (i = 0; i < reserved_num; i++)
1988                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1989
1990         for (i = 0; i < rm_num; i++) {
1991                 num = reserved_num + i;
1992                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1993         }
1994
1995         *reserved_addr_num = reserved_num;
1996         *add_addr_num = add_num;
1997         *rm_addr_num = rm_num;
1998 }
1999
2000 static int
2001 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2002                           struct rte_ether_addr *mc_addr_set,
2003                           uint32_t nb_mc_addr)
2004 {
2005         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2007         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2008         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2009         struct rte_ether_addr *addr;
2010         int reserved_addr_num;
2011         int add_addr_num;
2012         int rm_addr_num;
2013         int mc_addr_num;
2014         int num;
2015         int ret;
2016         int i;
2017
2018         /* Check if input parameters are valid */
2019         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2020         if (ret)
2021                 return ret;
2022
2023         rte_spinlock_lock(&hw->lock);
2024
2025         /*
2026          * Calculate the mc mac address lists those should be removed and be
2027          * added, Reorder the mc mac address list maintained by driver.
2028          */
2029         mc_addr_num = (int)nb_mc_addr;
2030         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2031                                    reserved_addr_list, &reserved_addr_num,
2032                                    add_addr_list, &add_addr_num,
2033                                    rm_addr_list, &rm_addr_num);
2034
2035         /* Remove mc mac addresses */
2036         for (i = 0; i < rm_addr_num; i++) {
2037                 num = rm_addr_num - i - 1;
2038                 addr = &rm_addr_list[num];
2039                 ret = hns3_remove_mc_addr(hw, addr);
2040                 if (ret) {
2041                         rte_spinlock_unlock(&hw->lock);
2042                         return ret;
2043                 }
2044                 hw->mc_addrs_num--;
2045         }
2046
2047         /* Add mc mac addresses */
2048         for (i = 0; i < add_addr_num; i++) {
2049                 addr = &add_addr_list[i];
2050                 ret = hns3_add_mc_addr(hw, addr);
2051                 if (ret) {
2052                         rte_spinlock_unlock(&hw->lock);
2053                         return ret;
2054                 }
2055
2056                 num = reserved_addr_num + i;
2057                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2058                 hw->mc_addrs_num++;
2059         }
2060         rte_spinlock_unlock(&hw->lock);
2061
2062         return 0;
2063 }
2064
2065 static int
2066 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2067 {
2068         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2069         struct hns3_hw *hw = &hns->hw;
2070         struct rte_ether_addr *addr;
2071         int err = 0;
2072         int ret;
2073         int i;
2074
2075         for (i = 0; i < hw->mc_addrs_num; i++) {
2076                 addr = &hw->mc_addrs[i];
2077                 if (!rte_is_multicast_ether_addr(addr))
2078                         continue;
2079                 if (del)
2080                         ret = hns3_remove_mc_addr(hw, addr);
2081                 else
2082                         ret = hns3_add_mc_addr(hw, addr);
2083                 if (ret) {
2084                         err = ret;
2085                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2086                                               addr);
2087                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2088                                  del ? "Remove" : "Restore", mac_str, ret);
2089                 }
2090         }
2091         return err;
2092 }
2093
2094 static int
2095 hns3_check_mq_mode(struct rte_eth_dev *dev)
2096 {
2097         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2098         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2099         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2102         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2103         uint8_t num_tc;
2104         int max_tc = 0;
2105         int i;
2106
2107         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2108         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2109
2110         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2111                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2112                          "rx_mq_mode = %d", rx_mq_mode);
2113                 return -EINVAL;
2114         }
2115
2116         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2117             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2118                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2119                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2120                          rx_mq_mode, tx_mq_mode);
2121                 return -EINVAL;
2122         }
2123
2124         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2125                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2126                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2127                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2128                         return -EINVAL;
2129                 }
2130
2131                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2132                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2133                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2134                                  "nb_tcs(%d) != %d or %d in rx direction.",
2135                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2136                         return -EINVAL;
2137                 }
2138
2139                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2140                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2141                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2142                         return -EINVAL;
2143                 }
2144
2145                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2146                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2147                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2148                                          "is not equal to one in tx direction.",
2149                                          i, dcb_rx_conf->dcb_tc[i]);
2150                                 return -EINVAL;
2151                         }
2152                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2153                                 max_tc = dcb_rx_conf->dcb_tc[i];
2154                 }
2155
2156                 num_tc = max_tc + 1;
2157                 if (num_tc > dcb_rx_conf->nb_tcs) {
2158                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2159                                  num_tc, dcb_rx_conf->nb_tcs);
2160                         return -EINVAL;
2161                 }
2162         }
2163
2164         return 0;
2165 }
2166
2167 static int
2168 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2169 {
2170         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171
2172         if (!hns3_dev_dcb_supported(hw)) {
2173                 hns3_err(hw, "this port does not support dcb configurations.");
2174                 return -EOPNOTSUPP;
2175         }
2176
2177         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2178                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2179                 return -EOPNOTSUPP;
2180         }
2181
2182         /* Check multiple queue mode */
2183         return hns3_check_mq_mode(dev);
2184 }
2185
2186 static int
2187 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2188                            enum hns3_ring_type queue_type, uint16_t queue_id)
2189 {
2190         struct hns3_cmd_desc desc;
2191         struct hns3_ctrl_vector_chain_cmd *req =
2192                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2193         enum hns3_cmd_status status;
2194         enum hns3_opcode_type op;
2195         uint16_t tqp_type_and_id = 0;
2196         const char *op_str;
2197         uint16_t type;
2198         uint16_t gl;
2199
2200         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2201         hns3_cmd_setup_basic_desc(&desc, op, false);
2202         req->int_vector_id = vector_id;
2203
2204         if (queue_type == HNS3_RING_TYPE_RX)
2205                 gl = HNS3_RING_GL_RX;
2206         else
2207                 gl = HNS3_RING_GL_TX;
2208
2209         type = queue_type;
2210
2211         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2212                        type);
2213         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2214         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2215                        gl);
2216         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2217         req->int_cause_num = 1;
2218         op_str = mmap ? "Map" : "Unmap";
2219         status = hns3_cmd_send(hw, &desc, 1);
2220         if (status) {
2221                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2222                          op_str, queue_id, req->int_vector_id, status);
2223                 return status;
2224         }
2225
2226         return 0;
2227 }
2228
2229 static int
2230 hns3_init_ring_with_vector(struct hns3_hw *hw)
2231 {
2232         uint16_t vec;
2233         int ret;
2234         int i;
2235
2236         /*
2237          * In hns3 network engine, vector 0 is always the misc interrupt of this
2238          * function, vector 1~N can be used respectively for the queues of the
2239          * function. Tx and Rx queues with the same number share the interrupt
2240          * vector. In the initialization clearing the all hardware mapping
2241          * relationship configurations between queues and interrupt vectors is
2242          * needed, so some error caused by the residual configurations, such as
2243          * the unexpected Tx interrupt, can be avoid.
2244          */
2245         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2246         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2247                 vec = vec - 1; /* the last interrupt is reserved */
2248         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2249         for (i = 0; i < hw->intr_tqps_num; i++) {
2250                 /*
2251                  * Set gap limiter/rate limiter/quanity limiter algorithm
2252                  * configuration for interrupt coalesce of queue's interrupt.
2253                  */
2254                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2255                                        HNS3_TQP_INTR_GL_DEFAULT);
2256                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2257                                        HNS3_TQP_INTR_GL_DEFAULT);
2258                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2259                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2260
2261                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2262                                                  HNS3_RING_TYPE_TX, i);
2263                 if (ret) {
2264                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2265                                           "vector: %d, ret=%d", i, vec, ret);
2266                         return ret;
2267                 }
2268
2269                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2270                                                  HNS3_RING_TYPE_RX, i);
2271                 if (ret) {
2272                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2273                                           "vector: %d, ret=%d", i, vec, ret);
2274                         return ret;
2275                 }
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int
2282 hns3_dev_configure(struct rte_eth_dev *dev)
2283 {
2284         struct hns3_adapter *hns = dev->data->dev_private;
2285         struct rte_eth_conf *conf = &dev->data->dev_conf;
2286         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2287         struct hns3_hw *hw = &hns->hw;
2288         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2289         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2290         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2291         struct rte_eth_rss_conf rss_conf;
2292         uint16_t mtu;
2293         bool gro_en;
2294         int ret;
2295
2296         /*
2297          * Hardware does not support individually enable/disable/reset the Tx or
2298          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2299          * and Rx queues at the same time. When the numbers of Tx queues
2300          * allocated by upper applications are not equal to the numbers of Rx
2301          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2302          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2303          * these fake queues are imperceptible, and can not be used by upper
2304          * applications.
2305          */
2306         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2307         if (ret) {
2308                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2309                 return ret;
2310         }
2311
2312         hw->adapter_state = HNS3_NIC_CONFIGURING;
2313         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2314                 hns3_err(hw, "setting link speed/duplex not supported");
2315                 ret = -EINVAL;
2316                 goto cfg_err;
2317         }
2318
2319         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2320                 ret = hns3_check_dcb_cfg(dev);
2321                 if (ret)
2322                         goto cfg_err;
2323         }
2324
2325         /* When RSS is not configured, redirect the packet queue 0 */
2326         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2327                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2328                 rss_conf = conf->rx_adv_conf.rss_conf;
2329                 hw->rss_dis_flag = false;
2330                 if (rss_conf.rss_key == NULL) {
2331                         rss_conf.rss_key = rss_cfg->key;
2332                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2333                 }
2334
2335                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2336                 if (ret)
2337                         goto cfg_err;
2338         }
2339
2340         /*
2341          * If jumbo frames are enabled, MTU needs to be refreshed
2342          * according to the maximum RX packet length.
2343          */
2344         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2345                 /*
2346                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2347                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2348                  * can safely assign to "uint16_t" type variable.
2349                  */
2350                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2351                 ret = hns3_dev_mtu_set(dev, mtu);
2352                 if (ret)
2353                         goto cfg_err;
2354                 dev->data->mtu = mtu;
2355         }
2356
2357         ret = hns3_dev_configure_vlan(dev);
2358         if (ret)
2359                 goto cfg_err;
2360
2361         /* config hardware GRO */
2362         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2363         ret = hns3_config_gro(hw, gro_en);
2364         if (ret)
2365                 goto cfg_err;
2366
2367         hns->rx_simple_allowed = true;
2368         hns->rx_vec_allowed = true;
2369         hns->tx_simple_allowed = true;
2370         hns->tx_vec_allowed = true;
2371
2372         hns3_init_rx_ptype_tble(dev);
2373         hw->adapter_state = HNS3_NIC_CONFIGURED;
2374
2375         return 0;
2376
2377 cfg_err:
2378         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2379         hw->adapter_state = HNS3_NIC_INITIALIZED;
2380
2381         return ret;
2382 }
2383
2384 static int
2385 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2386 {
2387         struct hns3_config_max_frm_size_cmd *req;
2388         struct hns3_cmd_desc desc;
2389
2390         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2391
2392         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2393         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2394         req->min_frm_size = RTE_ETHER_MIN_LEN;
2395
2396         return hns3_cmd_send(hw, &desc, 1);
2397 }
2398
2399 static int
2400 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2401 {
2402         int ret;
2403
2404         ret = hns3_set_mac_mtu(hw, mps);
2405         if (ret) {
2406                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2407                 return ret;
2408         }
2409
2410         ret = hns3_buffer_alloc(hw);
2411         if (ret)
2412                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2413
2414         return ret;
2415 }
2416
2417 static int
2418 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2419 {
2420         struct hns3_adapter *hns = dev->data->dev_private;
2421         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2422         struct hns3_hw *hw = &hns->hw;
2423         bool is_jumbo_frame;
2424         int ret;
2425
2426         if (dev->data->dev_started) {
2427                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2428                          "before configuration", dev->data->port_id);
2429                 return -EBUSY;
2430         }
2431
2432         rte_spinlock_lock(&hw->lock);
2433         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2434         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2435
2436         /*
2437          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2438          * assign to "uint16_t" type variable.
2439          */
2440         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2441         if (ret) {
2442                 rte_spinlock_unlock(&hw->lock);
2443                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2444                          dev->data->port_id, mtu, ret);
2445                 return ret;
2446         }
2447         hns->pf.mps = (uint16_t)frame_size;
2448         if (is_jumbo_frame)
2449                 dev->data->dev_conf.rxmode.offloads |=
2450                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2451         else
2452                 dev->data->dev_conf.rxmode.offloads &=
2453                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2454         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2455         rte_spinlock_unlock(&hw->lock);
2456
2457         return 0;
2458 }
2459
2460 static int
2461 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2462 {
2463         struct hns3_adapter *hns = eth_dev->data->dev_private;
2464         struct hns3_hw *hw = &hns->hw;
2465         uint16_t queue_num = hw->tqps_num;
2466
2467         /*
2468          * In interrupt mode, 'max_rx_queues' is set based on the number of
2469          * MSI-X interrupt resources of the hardware.
2470          */
2471         if (hw->data->dev_conf.intr_conf.rxq == 1)
2472                 queue_num = hw->intr_tqps_num;
2473
2474         info->max_rx_queues = queue_num;
2475         info->max_tx_queues = hw->tqps_num;
2476         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2477         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2478         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2479         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2480         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2481         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2482                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2483                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2484                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2485                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2486                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2487                                  DEV_RX_OFFLOAD_KEEP_CRC |
2488                                  DEV_RX_OFFLOAD_SCATTER |
2489                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2490                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2491                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2492                                  DEV_RX_OFFLOAD_RSS_HASH |
2493                                  DEV_RX_OFFLOAD_TCP_LRO);
2494         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2495                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2496                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2497                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2498                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2499                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2500                                  DEV_TX_OFFLOAD_TCP_TSO |
2501                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2502                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2503                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2504                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2505                                  hns3_txvlan_cap_get(hw));
2506
2507         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2508                 .nb_max = HNS3_MAX_RING_DESC,
2509                 .nb_min = HNS3_MIN_RING_DESC,
2510                 .nb_align = HNS3_ALIGN_RING_DESC,
2511         };
2512
2513         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2514                 .nb_max = HNS3_MAX_RING_DESC,
2515                 .nb_min = HNS3_MIN_RING_DESC,
2516                 .nb_align = HNS3_ALIGN_RING_DESC,
2517                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2518                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2519         };
2520
2521         info->default_rxconf = (struct rte_eth_rxconf) {
2522                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2523                 /*
2524                  * If there are no available Rx buffer descriptors, incoming
2525                  * packets are always dropped by hardware based on hns3 network
2526                  * engine.
2527                  */
2528                 .rx_drop_en = 1,
2529                 .offloads = 0,
2530         };
2531         info->default_txconf = (struct rte_eth_txconf) {
2532                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2533                 .offloads = 0,
2534         };
2535
2536         info->vmdq_queue_num = 0;
2537
2538         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2539         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2540         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2541
2542         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2543         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2544         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2545         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2546         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2547         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2548
2549         return 0;
2550 }
2551
2552 static int
2553 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2554                     size_t fw_size)
2555 {
2556         struct hns3_adapter *hns = eth_dev->data->dev_private;
2557         struct hns3_hw *hw = &hns->hw;
2558         uint32_t version = hw->fw_version;
2559         int ret;
2560
2561         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2562                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2563                                       HNS3_FW_VERSION_BYTE3_S),
2564                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2565                                       HNS3_FW_VERSION_BYTE2_S),
2566                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2567                                       HNS3_FW_VERSION_BYTE1_S),
2568                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2569                                       HNS3_FW_VERSION_BYTE0_S));
2570         ret += 1; /* add the size of '\0' */
2571         if (fw_size < (uint32_t)ret)
2572                 return ret;
2573         else
2574                 return 0;
2575 }
2576
2577 static int
2578 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2579                      __rte_unused int wait_to_complete)
2580 {
2581         struct hns3_adapter *hns = eth_dev->data->dev_private;
2582         struct hns3_hw *hw = &hns->hw;
2583         struct hns3_mac *mac = &hw->mac;
2584         struct rte_eth_link new_link;
2585
2586         if (!hns3_is_reset_pending(hns)) {
2587                 hns3_update_speed_duplex(eth_dev);
2588                 hns3_update_link_status(hw);
2589         }
2590
2591         memset(&new_link, 0, sizeof(new_link));
2592         switch (mac->link_speed) {
2593         case ETH_SPEED_NUM_10M:
2594         case ETH_SPEED_NUM_100M:
2595         case ETH_SPEED_NUM_1G:
2596         case ETH_SPEED_NUM_10G:
2597         case ETH_SPEED_NUM_25G:
2598         case ETH_SPEED_NUM_40G:
2599         case ETH_SPEED_NUM_50G:
2600         case ETH_SPEED_NUM_100G:
2601         case ETH_SPEED_NUM_200G:
2602                 new_link.link_speed = mac->link_speed;
2603                 break;
2604         default:
2605                 new_link.link_speed = ETH_SPEED_NUM_100M;
2606                 break;
2607         }
2608
2609         new_link.link_duplex = mac->link_duplex;
2610         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2611         new_link.link_autoneg =
2612             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2613
2614         return rte_eth_linkstatus_set(eth_dev, &new_link);
2615 }
2616
2617 static int
2618 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2619 {
2620         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2621         struct hns3_pf *pf = &hns->pf;
2622
2623         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2624                 return -EINVAL;
2625
2626         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2627
2628         return 0;
2629 }
2630
2631 static int
2632 hns3_query_function_status(struct hns3_hw *hw)
2633 {
2634 #define HNS3_QUERY_MAX_CNT              10
2635 #define HNS3_QUERY_SLEEP_MSCOEND        1
2636         struct hns3_func_status_cmd *req;
2637         struct hns3_cmd_desc desc;
2638         int timeout = 0;
2639         int ret;
2640
2641         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2642         req = (struct hns3_func_status_cmd *)desc.data;
2643
2644         do {
2645                 ret = hns3_cmd_send(hw, &desc, 1);
2646                 if (ret) {
2647                         PMD_INIT_LOG(ERR, "query function status failed %d",
2648                                      ret);
2649                         return ret;
2650                 }
2651
2652                 /* Check pf reset is done */
2653                 if (req->pf_state)
2654                         break;
2655
2656                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2657         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2658
2659         return hns3_parse_func_status(hw, req);
2660 }
2661
2662 static int
2663 hns3_query_pf_resource(struct hns3_hw *hw)
2664 {
2665         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2666         struct hns3_pf *pf = &hns->pf;
2667         struct hns3_pf_res_cmd *req;
2668         struct hns3_cmd_desc desc;
2669         int ret;
2670
2671         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2672         ret = hns3_cmd_send(hw, &desc, 1);
2673         if (ret) {
2674                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2675                 return ret;
2676         }
2677
2678         req = (struct hns3_pf_res_cmd *)desc.data;
2679         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2680         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2681         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2682         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2683
2684         if (req->tx_buf_size)
2685                 pf->tx_buf_size =
2686                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2687         else
2688                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2689
2690         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2691
2692         if (req->dv_buf_size)
2693                 pf->dv_buf_size =
2694                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2695         else
2696                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2697
2698         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2699
2700         hw->num_msi =
2701                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2702                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2703
2704         return 0;
2705 }
2706
2707 static void
2708 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2709 {
2710         struct hns3_cfg_param_cmd *req;
2711         uint64_t mac_addr_tmp_high;
2712         uint64_t mac_addr_tmp;
2713         uint32_t i;
2714
2715         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2716
2717         /* get the configuration */
2718         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2719                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2720         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2721                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2722         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2723                                            HNS3_CFG_TQP_DESC_N_M,
2724                                            HNS3_CFG_TQP_DESC_N_S);
2725
2726         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2727                                        HNS3_CFG_PHY_ADDR_M,
2728                                        HNS3_CFG_PHY_ADDR_S);
2729         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2730                                          HNS3_CFG_MEDIA_TP_M,
2731                                          HNS3_CFG_MEDIA_TP_S);
2732         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2733                                          HNS3_CFG_RX_BUF_LEN_M,
2734                                          HNS3_CFG_RX_BUF_LEN_S);
2735         /* get mac address */
2736         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2737         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2738                                            HNS3_CFG_MAC_ADDR_H_M,
2739                                            HNS3_CFG_MAC_ADDR_H_S);
2740
2741         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2742
2743         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2744                                             HNS3_CFG_DEFAULT_SPEED_M,
2745                                             HNS3_CFG_DEFAULT_SPEED_S);
2746         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2747                                            HNS3_CFG_RSS_SIZE_M,
2748                                            HNS3_CFG_RSS_SIZE_S);
2749
2750         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2751                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2752
2753         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2754         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2755
2756         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2757                                             HNS3_CFG_SPEED_ABILITY_M,
2758                                             HNS3_CFG_SPEED_ABILITY_S);
2759         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2760                                         HNS3_CFG_UMV_TBL_SPACE_M,
2761                                         HNS3_CFG_UMV_TBL_SPACE_S);
2762         if (!cfg->umv_space)
2763                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2764 }
2765
2766 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2767  * @hw: pointer to struct hns3_hw
2768  * @hcfg: the config structure to be getted
2769  */
2770 static int
2771 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2772 {
2773         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2774         struct hns3_cfg_param_cmd *req;
2775         uint32_t offset;
2776         uint32_t i;
2777         int ret;
2778
2779         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2780                 offset = 0;
2781                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2782                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2783                                           true);
2784                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2785                                i * HNS3_CFG_RD_LEN_BYTES);
2786                 /* Len should be divided by 4 when send to hardware */
2787                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2788                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2789                 req->offset = rte_cpu_to_le_32(offset);
2790         }
2791
2792         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2793         if (ret) {
2794                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2795                 return ret;
2796         }
2797
2798         hns3_parse_cfg(hcfg, desc);
2799
2800         return 0;
2801 }
2802
2803 static int
2804 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2805 {
2806         switch (speed_cmd) {
2807         case HNS3_CFG_SPEED_10M:
2808                 *speed = ETH_SPEED_NUM_10M;
2809                 break;
2810         case HNS3_CFG_SPEED_100M:
2811                 *speed = ETH_SPEED_NUM_100M;
2812                 break;
2813         case HNS3_CFG_SPEED_1G:
2814                 *speed = ETH_SPEED_NUM_1G;
2815                 break;
2816         case HNS3_CFG_SPEED_10G:
2817                 *speed = ETH_SPEED_NUM_10G;
2818                 break;
2819         case HNS3_CFG_SPEED_25G:
2820                 *speed = ETH_SPEED_NUM_25G;
2821                 break;
2822         case HNS3_CFG_SPEED_40G:
2823                 *speed = ETH_SPEED_NUM_40G;
2824                 break;
2825         case HNS3_CFG_SPEED_50G:
2826                 *speed = ETH_SPEED_NUM_50G;
2827                 break;
2828         case HNS3_CFG_SPEED_100G:
2829                 *speed = ETH_SPEED_NUM_100G;
2830                 break;
2831         case HNS3_CFG_SPEED_200G:
2832                 *speed = ETH_SPEED_NUM_200G;
2833                 break;
2834         default:
2835                 return -EINVAL;
2836         }
2837
2838         return 0;
2839 }
2840
2841 static void
2842 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2843 {
2844         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2845         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2846         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2847         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2848 }
2849
2850 static void
2851 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2852 {
2853         struct hns3_dev_specs_0_cmd *req0;
2854
2855         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2856
2857         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2858         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2859         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2860         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2861 }
2862
2863 static int
2864 hns3_query_dev_specifications(struct hns3_hw *hw)
2865 {
2866         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2867         int ret;
2868         int i;
2869
2870         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2871                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2872                                           true);
2873                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2874         }
2875         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2876
2877         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2878         if (ret)
2879                 return ret;
2880
2881         hns3_parse_dev_specifications(hw, desc);
2882
2883         return 0;
2884 }
2885
2886 static int
2887 hns3_get_capability(struct hns3_hw *hw)
2888 {
2889         struct rte_pci_device *pci_dev;
2890         struct rte_eth_dev *eth_dev;
2891         uint16_t device_id;
2892         uint8_t revision;
2893         int ret;
2894
2895         eth_dev = &rte_eth_devices[hw->data->port_id];
2896         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2897         device_id = pci_dev->id.device_id;
2898
2899         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2900             device_id == HNS3_DEV_ID_50GE_RDMA ||
2901             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2902             device_id == HNS3_DEV_ID_200G_RDMA)
2903                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2904
2905         /* Get PCI revision id */
2906         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2907                                   HNS3_PCI_REVISION_ID);
2908         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2909                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2910                              ret);
2911                 return -EIO;
2912         }
2913         hw->revision = revision;
2914
2915         if (revision < PCI_REVISION_ID_HIP09_A) {
2916                 hns3_set_default_dev_specifications(hw);
2917                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2918                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
2919                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2920                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2921                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2922                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2923                 return 0;
2924         }
2925
2926         ret = hns3_query_dev_specifications(hw);
2927         if (ret) {
2928                 PMD_INIT_LOG(ERR,
2929                              "failed to query dev specifications, ret = %d",
2930                              ret);
2931                 return ret;
2932         }
2933
2934         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2935         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
2936         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2937         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2938         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2939         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2940
2941         return 0;
2942 }
2943
2944 static int
2945 hns3_get_board_configuration(struct hns3_hw *hw)
2946 {
2947         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2948         struct hns3_pf *pf = &hns->pf;
2949         struct hns3_cfg cfg;
2950         int ret;
2951
2952         ret = hns3_get_board_cfg(hw, &cfg);
2953         if (ret) {
2954                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2955                 return ret;
2956         }
2957
2958         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER &&
2959             !hns3_dev_copper_supported(hw)) {
2960                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2961                 return -EOPNOTSUPP;
2962         }
2963
2964         hw->mac.media_type = cfg.media_type;
2965         hw->rss_size_max = cfg.rss_size_max;
2966         hw->rss_dis_flag = false;
2967         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2968         hw->mac.phy_addr = cfg.phy_addr;
2969         hw->mac.default_addr_setted = false;
2970         hw->num_tx_desc = cfg.tqp_desc_num;
2971         hw->num_rx_desc = cfg.tqp_desc_num;
2972         hw->dcb_info.num_pg = 1;
2973         hw->dcb_info.hw_pfc_map = 0;
2974
2975         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2976         if (ret) {
2977                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2978                              cfg.default_speed, ret);
2979                 return ret;
2980         }
2981
2982         pf->tc_max = cfg.tc_num;
2983         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2984                 PMD_INIT_LOG(WARNING,
2985                              "Get TC num(%u) from flash, set TC num to 1",
2986                              pf->tc_max);
2987                 pf->tc_max = 1;
2988         }
2989
2990         /* Dev does not support DCB */
2991         if (!hns3_dev_dcb_supported(hw)) {
2992                 pf->tc_max = 1;
2993                 pf->pfc_max = 0;
2994         } else
2995                 pf->pfc_max = pf->tc_max;
2996
2997         hw->dcb_info.num_tc = 1;
2998         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2999                                      hw->tqps_num / hw->dcb_info.num_tc);
3000         hns3_set_bit(hw->hw_tc_map, 0, 1);
3001         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3002
3003         pf->wanted_umv_size = cfg.umv_space;
3004
3005         return ret;
3006 }
3007
3008 static int
3009 hns3_get_configuration(struct hns3_hw *hw)
3010 {
3011         int ret;
3012
3013         ret = hns3_query_function_status(hw);
3014         if (ret) {
3015                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3016                 return ret;
3017         }
3018
3019         /* Get device capability */
3020         ret = hns3_get_capability(hw);
3021         if (ret) {
3022                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3023                 return ret;
3024         }
3025
3026         /* Get pf resource */
3027         ret = hns3_query_pf_resource(hw);
3028         if (ret) {
3029                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3030                 return ret;
3031         }
3032
3033         ret = hns3_get_board_configuration(hw);
3034         if (ret)
3035                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
3036
3037         return ret;
3038 }
3039
3040 static int
3041 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3042                       uint16_t tqp_vid, bool is_pf)
3043 {
3044         struct hns3_tqp_map_cmd *req;
3045         struct hns3_cmd_desc desc;
3046         int ret;
3047
3048         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3049
3050         req = (struct hns3_tqp_map_cmd *)desc.data;
3051         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3052         req->tqp_vf = func_id;
3053         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3054         if (!is_pf)
3055                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3056         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3057
3058         ret = hns3_cmd_send(hw, &desc, 1);
3059         if (ret)
3060                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3061
3062         return ret;
3063 }
3064
3065 static int
3066 hns3_map_tqp(struct hns3_hw *hw)
3067 {
3068         uint16_t tqps_num = hw->total_tqps_num;
3069         uint16_t func_id;
3070         uint16_t tqp_id;
3071         bool is_pf;
3072         int num;
3073         int ret;
3074         int i;
3075
3076         /*
3077          * In current version VF is not supported when PF is driven by DPDK
3078          * driver, so we allocate tqps to PF as much as possible.
3079          */
3080         tqp_id = 0;
3081         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
3082         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
3083                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
3084                 for (i = 0;
3085                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
3086                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
3087                                                     is_pf);
3088                         if (ret)
3089                                 return ret;
3090                 }
3091         }
3092
3093         return 0;
3094 }
3095
3096 static int
3097 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3098 {
3099         struct hns3_config_mac_speed_dup_cmd *req;
3100         struct hns3_cmd_desc desc;
3101         int ret;
3102
3103         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3104
3105         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3106
3107         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3108
3109         switch (speed) {
3110         case ETH_SPEED_NUM_10M:
3111                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3112                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3113                 break;
3114         case ETH_SPEED_NUM_100M:
3115                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3116                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3117                 break;
3118         case ETH_SPEED_NUM_1G:
3119                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3120                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3121                 break;
3122         case ETH_SPEED_NUM_10G:
3123                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3124                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3125                 break;
3126         case ETH_SPEED_NUM_25G:
3127                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3128                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3129                 break;
3130         case ETH_SPEED_NUM_40G:
3131                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3132                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3133                 break;
3134         case ETH_SPEED_NUM_50G:
3135                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3136                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3137                 break;
3138         case ETH_SPEED_NUM_100G:
3139                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3140                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3141                 break;
3142         case ETH_SPEED_NUM_200G:
3143                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3144                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3145                 break;
3146         default:
3147                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3148                 return -EINVAL;
3149         }
3150
3151         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3152
3153         ret = hns3_cmd_send(hw, &desc, 1);
3154         if (ret)
3155                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3156
3157         return ret;
3158 }
3159
3160 static int
3161 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3162 {
3163         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3164         struct hns3_pf *pf = &hns->pf;
3165         struct hns3_priv_buf *priv;
3166         uint32_t i, total_size;
3167
3168         total_size = pf->pkt_buf_size;
3169
3170         /* alloc tx buffer for all enabled tc */
3171         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3172                 priv = &buf_alloc->priv_buf[i];
3173
3174                 if (hw->hw_tc_map & BIT(i)) {
3175                         if (total_size < pf->tx_buf_size)
3176                                 return -ENOMEM;
3177
3178                         priv->tx_buf_size = pf->tx_buf_size;
3179                 } else
3180                         priv->tx_buf_size = 0;
3181
3182                 total_size -= priv->tx_buf_size;
3183         }
3184
3185         return 0;
3186 }
3187
3188 static int
3189 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3190 {
3191 /* TX buffer size is unit by 128 byte */
3192 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3193 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3194         struct hns3_tx_buff_alloc_cmd *req;
3195         struct hns3_cmd_desc desc;
3196         uint32_t buf_size;
3197         uint32_t i;
3198         int ret;
3199
3200         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3201
3202         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3203         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3204                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3205
3206                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3207                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3208                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3209         }
3210
3211         ret = hns3_cmd_send(hw, &desc, 1);
3212         if (ret)
3213                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3214
3215         return ret;
3216 }
3217
3218 static int
3219 hns3_get_tc_num(struct hns3_hw *hw)
3220 {
3221         int cnt = 0;
3222         uint8_t i;
3223
3224         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3225                 if (hw->hw_tc_map & BIT(i))
3226                         cnt++;
3227         return cnt;
3228 }
3229
3230 static uint32_t
3231 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3232 {
3233         struct hns3_priv_buf *priv;
3234         uint32_t rx_priv = 0;
3235         int i;
3236
3237         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3238                 priv = &buf_alloc->priv_buf[i];
3239                 if (priv->enable)
3240                         rx_priv += priv->buf_size;
3241         }
3242         return rx_priv;
3243 }
3244
3245 static uint32_t
3246 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3247 {
3248         uint32_t total_tx_size = 0;
3249         uint32_t i;
3250
3251         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3252                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3253
3254         return total_tx_size;
3255 }
3256
3257 /* Get the number of pfc enabled TCs, which have private buffer */
3258 static int
3259 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3260 {
3261         struct hns3_priv_buf *priv;
3262         int cnt = 0;
3263         uint8_t i;
3264
3265         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3266                 priv = &buf_alloc->priv_buf[i];
3267                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3268                         cnt++;
3269         }
3270
3271         return cnt;
3272 }
3273
3274 /* Get the number of pfc disabled TCs, which have private buffer */
3275 static int
3276 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3277                          struct hns3_pkt_buf_alloc *buf_alloc)
3278 {
3279         struct hns3_priv_buf *priv;
3280         int cnt = 0;
3281         uint8_t i;
3282
3283         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3284                 priv = &buf_alloc->priv_buf[i];
3285                 if (hw->hw_tc_map & BIT(i) &&
3286                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3287                         cnt++;
3288         }
3289
3290         return cnt;
3291 }
3292
3293 static bool
3294 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3295                   uint32_t rx_all)
3296 {
3297         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3298         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3299         struct hns3_pf *pf = &hns->pf;
3300         uint32_t shared_buf, aligned_mps;
3301         uint32_t rx_priv;
3302         uint8_t tc_num;
3303         uint8_t i;
3304
3305         tc_num = hns3_get_tc_num(hw);
3306         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3307
3308         if (hns3_dev_dcb_supported(hw))
3309                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3310                                         pf->dv_buf_size;
3311         else
3312                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3313                                         + pf->dv_buf_size;
3314
3315         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3316         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3317                              HNS3_BUF_SIZE_UNIT);
3318
3319         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3320         if (rx_all < rx_priv + shared_std)
3321                 return false;
3322
3323         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3324         buf_alloc->s_buf.buf_size = shared_buf;
3325         if (hns3_dev_dcb_supported(hw)) {
3326                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3327                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3328                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3329                                   HNS3_BUF_SIZE_UNIT);
3330         } else {
3331                 buf_alloc->s_buf.self.high =
3332                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3333                 buf_alloc->s_buf.self.low = aligned_mps;
3334         }
3335
3336         if (hns3_dev_dcb_supported(hw)) {
3337                 hi_thrd = shared_buf - pf->dv_buf_size;
3338
3339                 if (tc_num <= NEED_RESERVE_TC_NUM)
3340                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3341                                         / BUF_MAX_PERCENT;
3342
3343                 if (tc_num)
3344                         hi_thrd = hi_thrd / tc_num;
3345
3346                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3347                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3348                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3349         } else {
3350                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3351                 lo_thrd = aligned_mps;
3352         }
3353
3354         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3355                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3356                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3357         }
3358
3359         return true;
3360 }
3361
3362 static bool
3363 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3364                      struct hns3_pkt_buf_alloc *buf_alloc)
3365 {
3366         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3367         struct hns3_pf *pf = &hns->pf;
3368         struct hns3_priv_buf *priv;
3369         uint32_t aligned_mps;
3370         uint32_t rx_all;
3371         uint8_t i;
3372
3373         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3374         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3375
3376         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3377                 priv = &buf_alloc->priv_buf[i];
3378
3379                 priv->enable = 0;
3380                 priv->wl.low = 0;
3381                 priv->wl.high = 0;
3382                 priv->buf_size = 0;
3383
3384                 if (!(hw->hw_tc_map & BIT(i)))
3385                         continue;
3386
3387                 priv->enable = 1;
3388                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3389                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3390                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3391                                                 HNS3_BUF_SIZE_UNIT);
3392                 } else {
3393                         priv->wl.low = 0;
3394                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3395                                         aligned_mps;
3396                 }
3397
3398                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3399         }
3400
3401         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3402 }
3403
3404 static bool
3405 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3406                              struct hns3_pkt_buf_alloc *buf_alloc)
3407 {
3408         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3409         struct hns3_pf *pf = &hns->pf;
3410         struct hns3_priv_buf *priv;
3411         int no_pfc_priv_num;
3412         uint32_t rx_all;
3413         uint8_t mask;
3414         int i;
3415
3416         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3417         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3418
3419         /* let the last to be cleared first */
3420         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3421                 priv = &buf_alloc->priv_buf[i];
3422                 mask = BIT((uint8_t)i);
3423
3424                 if (hw->hw_tc_map & mask &&
3425                     !(hw->dcb_info.hw_pfc_map & mask)) {
3426                         /* Clear the no pfc TC private buffer */
3427                         priv->wl.low = 0;
3428                         priv->wl.high = 0;
3429                         priv->buf_size = 0;
3430                         priv->enable = 0;
3431                         no_pfc_priv_num--;
3432                 }
3433
3434                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3435                     no_pfc_priv_num == 0)
3436                         break;
3437         }
3438
3439         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3440 }
3441
3442 static bool
3443 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3444                            struct hns3_pkt_buf_alloc *buf_alloc)
3445 {
3446         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3447         struct hns3_pf *pf = &hns->pf;
3448         struct hns3_priv_buf *priv;
3449         uint32_t rx_all;
3450         int pfc_priv_num;
3451         uint8_t mask;
3452         int i;
3453
3454         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3455         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3456
3457         /* let the last to be cleared first */
3458         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3459                 priv = &buf_alloc->priv_buf[i];
3460                 mask = BIT((uint8_t)i);
3461
3462                 if (hw->hw_tc_map & mask &&
3463                     hw->dcb_info.hw_pfc_map & mask) {
3464                         /* Reduce the number of pfc TC with private buffer */
3465                         priv->wl.low = 0;
3466                         priv->enable = 0;
3467                         priv->wl.high = 0;
3468                         priv->buf_size = 0;
3469                         pfc_priv_num--;
3470                 }
3471                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3472                     pfc_priv_num == 0)
3473                         break;
3474         }
3475
3476         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3477 }
3478
3479 static bool
3480 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3481                           struct hns3_pkt_buf_alloc *buf_alloc)
3482 {
3483 #define COMPENSATE_BUFFER       0x3C00
3484 #define COMPENSATE_HALF_MPS_NUM 5
3485 #define PRIV_WL_GAP             0x1800
3486         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3487         struct hns3_pf *pf = &hns->pf;
3488         uint32_t tc_num = hns3_get_tc_num(hw);
3489         uint32_t half_mps = pf->mps >> 1;
3490         struct hns3_priv_buf *priv;
3491         uint32_t min_rx_priv;
3492         uint32_t rx_priv;
3493         uint8_t i;
3494
3495         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3496         if (tc_num)
3497                 rx_priv = rx_priv / tc_num;
3498
3499         if (tc_num <= NEED_RESERVE_TC_NUM)
3500                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3501
3502         /*
3503          * Minimum value of private buffer in rx direction (min_rx_priv) is
3504          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3505          * buffer if rx_priv is greater than min_rx_priv.
3506          */
3507         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3508                         COMPENSATE_HALF_MPS_NUM * half_mps;
3509         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3510         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3511
3512         if (rx_priv < min_rx_priv)
3513                 return false;
3514
3515         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3516                 priv = &buf_alloc->priv_buf[i];
3517
3518                 priv->enable = 0;
3519                 priv->wl.low = 0;
3520                 priv->wl.high = 0;
3521                 priv->buf_size = 0;
3522
3523                 if (!(hw->hw_tc_map & BIT(i)))
3524                         continue;
3525
3526                 priv->enable = 1;
3527                 priv->buf_size = rx_priv;
3528                 priv->wl.high = rx_priv - pf->dv_buf_size;
3529                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3530         }
3531
3532         buf_alloc->s_buf.buf_size = 0;
3533
3534         return true;
3535 }
3536
3537 /*
3538  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3539  * @hw: pointer to struct hns3_hw
3540  * @buf_alloc: pointer to buffer calculation data
3541  * @return: 0: calculate sucessful, negative: fail
3542  */
3543 static int
3544 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3545 {
3546         /* When DCB is not supported, rx private buffer is not allocated. */
3547         if (!hns3_dev_dcb_supported(hw)) {
3548                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3549                 struct hns3_pf *pf = &hns->pf;
3550                 uint32_t rx_all = pf->pkt_buf_size;
3551
3552                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3553                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3554                         return -ENOMEM;
3555
3556                 return 0;
3557         }
3558
3559         /*
3560          * Try to allocate privated packet buffer for all TCs without share
3561          * buffer.
3562          */
3563         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3564                 return 0;
3565
3566         /*
3567          * Try to allocate privated packet buffer for all TCs with share
3568          * buffer.
3569          */
3570         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3571                 return 0;
3572
3573         /*
3574          * For different application scenes, the enabled port number, TC number
3575          * and no_drop TC number are different. In order to obtain the better
3576          * performance, software could allocate the buffer size and configure
3577          * the waterline by tring to decrease the private buffer size according
3578          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3579          * enabled tc.
3580          */
3581         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3582                 return 0;
3583
3584         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3585                 return 0;
3586
3587         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3588                 return 0;
3589
3590         return -ENOMEM;
3591 }
3592
3593 static int
3594 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3595 {
3596         struct hns3_rx_priv_buff_cmd *req;
3597         struct hns3_cmd_desc desc;
3598         uint32_t buf_size;
3599         int ret;
3600         int i;
3601
3602         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3603         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3604
3605         /* Alloc private buffer TCs */
3606         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3607                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3608
3609                 req->buf_num[i] =
3610                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3611                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3612         }
3613
3614         buf_size = buf_alloc->s_buf.buf_size;
3615         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3616                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3617
3618         ret = hns3_cmd_send(hw, &desc, 1);
3619         if (ret)
3620                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3621
3622         return ret;
3623 }
3624
3625 static int
3626 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3627 {
3628 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3629         struct hns3_rx_priv_wl_buf *req;
3630         struct hns3_priv_buf *priv;
3631         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3632         int i, j;
3633         int ret;
3634
3635         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3636                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3637                                           false);
3638                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3639
3640                 /* The first descriptor set the NEXT bit to 1 */
3641                 if (i == 0)
3642                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3643                 else
3644                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3645
3646                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3647                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3648
3649                         priv = &buf_alloc->priv_buf[idx];
3650                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3651                                                         HNS3_BUF_UNIT_S);
3652                         req->tc_wl[j].high |=
3653                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3654                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3655                                                         HNS3_BUF_UNIT_S);
3656                         req->tc_wl[j].low |=
3657                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3658                 }
3659         }
3660
3661         /* Send 2 descriptor at one time */
3662         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3663         if (ret)
3664                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3665                              ret);
3666         return ret;
3667 }
3668
3669 static int
3670 hns3_common_thrd_config(struct hns3_hw *hw,
3671                         struct hns3_pkt_buf_alloc *buf_alloc)
3672 {
3673 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3674         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3675         struct hns3_rx_com_thrd *req;
3676         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3677         struct hns3_tc_thrd *tc;
3678         int tc_idx;
3679         int i, j;
3680         int ret;
3681
3682         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3683                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3684                                           false);
3685                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3686
3687                 /* The first descriptor set the NEXT bit to 1 */
3688                 if (i == 0)
3689                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3690                 else
3691                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3692
3693                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3694                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3695                         tc = &s_buf->tc_thrd[tc_idx];
3696
3697                         req->com_thrd[j].high =
3698                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3699                         req->com_thrd[j].high |=
3700                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3701                         req->com_thrd[j].low =
3702                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3703                         req->com_thrd[j].low |=
3704                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3705                 }
3706         }
3707
3708         /* Send 2 descriptors at one time */
3709         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3710         if (ret)
3711                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3712
3713         return ret;
3714 }
3715
3716 static int
3717 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3718 {
3719         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3720         struct hns3_rx_com_wl *req;
3721         struct hns3_cmd_desc desc;
3722         int ret;
3723
3724         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3725
3726         req = (struct hns3_rx_com_wl *)desc.data;
3727         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3728         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3729
3730         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3731         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3732
3733         ret = hns3_cmd_send(hw, &desc, 1);
3734         if (ret)
3735                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3736
3737         return ret;
3738 }
3739
3740 int
3741 hns3_buffer_alloc(struct hns3_hw *hw)
3742 {
3743         struct hns3_pkt_buf_alloc pkt_buf;
3744         int ret;
3745
3746         memset(&pkt_buf, 0, sizeof(pkt_buf));
3747         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3748         if (ret) {
3749                 PMD_INIT_LOG(ERR,
3750                              "could not calc tx buffer size for all TCs %d",
3751                              ret);
3752                 return ret;
3753         }
3754
3755         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3756         if (ret) {
3757                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3758                 return ret;
3759         }
3760
3761         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3762         if (ret) {
3763                 PMD_INIT_LOG(ERR,
3764                              "could not calc rx priv buffer size for all TCs %d",
3765                              ret);
3766                 return ret;
3767         }
3768
3769         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3770         if (ret) {
3771                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3772                 return ret;
3773         }
3774
3775         if (hns3_dev_dcb_supported(hw)) {
3776                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3777                 if (ret) {
3778                         PMD_INIT_LOG(ERR,
3779                                      "could not configure rx private waterline %d",
3780                                      ret);
3781                         return ret;
3782                 }
3783
3784                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3785                 if (ret) {
3786                         PMD_INIT_LOG(ERR,
3787                                      "could not configure common threshold %d",
3788                                      ret);
3789                         return ret;
3790                 }
3791         }
3792
3793         ret = hns3_common_wl_config(hw, &pkt_buf);
3794         if (ret)
3795                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3796                              ret);
3797
3798         return ret;
3799 }
3800
3801 static int
3802 hns3_mac_init(struct hns3_hw *hw)
3803 {
3804         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3805         struct hns3_mac *mac = &hw->mac;
3806         struct hns3_pf *pf = &hns->pf;
3807         int ret;
3808
3809         pf->support_sfp_query = true;
3810         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3811         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3812         if (ret) {
3813                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3814                 return ret;
3815         }
3816
3817         mac->link_status = ETH_LINK_DOWN;
3818
3819         return hns3_config_mtu(hw, pf->mps);
3820 }
3821
3822 static int
3823 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3824 {
3825 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3826 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3827 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3828 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3829         int return_status;
3830
3831         if (cmdq_resp) {
3832                 PMD_INIT_LOG(ERR,
3833                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3834                              cmdq_resp);
3835                 return -EIO;
3836         }
3837
3838         switch (resp_code) {
3839         case HNS3_ETHERTYPE_SUCCESS_ADD:
3840         case HNS3_ETHERTYPE_ALREADY_ADD:
3841                 return_status = 0;
3842                 break;
3843         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3844                 PMD_INIT_LOG(ERR,
3845                              "add mac ethertype failed for manager table overflow.");
3846                 return_status = -EIO;
3847                 break;
3848         case HNS3_ETHERTYPE_KEY_CONFLICT:
3849                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3850                 return_status = -EIO;
3851                 break;
3852         default:
3853                 PMD_INIT_LOG(ERR,
3854                              "add mac ethertype failed for undefined, code=%d.",
3855                              resp_code);
3856                 return_status = -EIO;
3857                 break;
3858         }
3859
3860         return return_status;
3861 }
3862
3863 static int
3864 hns3_add_mgr_tbl(struct hns3_hw *hw,
3865                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3866 {
3867         struct hns3_cmd_desc desc;
3868         uint8_t resp_code;
3869         uint16_t retval;
3870         int ret;
3871
3872         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3873         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3874
3875         ret = hns3_cmd_send(hw, &desc, 1);
3876         if (ret) {
3877                 PMD_INIT_LOG(ERR,
3878                              "add mac ethertype failed for cmd_send, ret =%d.",
3879                              ret);
3880                 return ret;
3881         }
3882
3883         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3884         retval = rte_le_to_cpu_16(desc.retval);
3885
3886         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3887 }
3888
3889 static void
3890 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3891                      int *table_item_num)
3892 {
3893         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3894
3895         /*
3896          * In current version, we add one item in management table as below:
3897          * 0x0180C200000E -- LLDP MC address
3898          */
3899         tbl = mgr_table;
3900         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3901         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3902         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3903         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3904         tbl->i_port_bitmap = 0x1;
3905         *table_item_num = 1;
3906 }
3907
3908 static int
3909 hns3_init_mgr_tbl(struct hns3_hw *hw)
3910 {
3911 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3912         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3913         int table_item_num;
3914         int ret;
3915         int i;
3916
3917         memset(mgr_table, 0, sizeof(mgr_table));
3918         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3919         for (i = 0; i < table_item_num; i++) {
3920                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3921                 if (ret) {
3922                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3923                                      ret);
3924                         return ret;
3925                 }
3926         }
3927
3928         return 0;
3929 }
3930
3931 static void
3932 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3933                         bool en_mc, bool en_bc, int vport_id)
3934 {
3935         if (!param)
3936                 return;
3937
3938         memset(param, 0, sizeof(struct hns3_promisc_param));
3939         if (en_uc)
3940                 param->enable = HNS3_PROMISC_EN_UC;
3941         if (en_mc)
3942                 param->enable |= HNS3_PROMISC_EN_MC;
3943         if (en_bc)
3944                 param->enable |= HNS3_PROMISC_EN_BC;
3945         param->vf_id = vport_id;
3946 }
3947
3948 static int
3949 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3950 {
3951         struct hns3_promisc_cfg_cmd *req;
3952         struct hns3_cmd_desc desc;
3953         int ret;
3954
3955         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3956
3957         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3958         req->vf_id = param->vf_id;
3959         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3960             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3961
3962         ret = hns3_cmd_send(hw, &desc, 1);
3963         if (ret)
3964                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3965
3966         return ret;
3967 }
3968
3969 static int
3970 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3971 {
3972         struct hns3_promisc_param param;
3973         bool en_bc_pmc = true;
3974         uint8_t vf_id;
3975
3976         /*
3977          * In current version VF is not supported when PF is driven by DPDK
3978          * driver, just need to configure parameters for PF vport.
3979          */
3980         vf_id = HNS3_PF_FUNC_ID;
3981
3982         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3983         return hns3_cmd_set_promisc_mode(hw, &param);
3984 }
3985
3986 static int
3987 hns3_promisc_init(struct hns3_hw *hw)
3988 {
3989         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3990         struct hns3_pf *pf = &hns->pf;
3991         struct hns3_promisc_param param;
3992         uint16_t func_id;
3993         int ret;
3994
3995         ret = hns3_set_promisc_mode(hw, false, false);
3996         if (ret) {
3997                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3998                 return ret;
3999         }
4000
4001         /*
4002          * In current version VFs are not supported when PF is driven by DPDK
4003          * driver. After PF has been taken over by DPDK, the original VF will
4004          * be invalid. So, there is a possibility of entry residues. It should
4005          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4006          * during init.
4007          */
4008         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4009                 hns3_promisc_param_init(&param, false, false, false, func_id);
4010                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4011                 if (ret) {
4012                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
4013                                         " ret = %d", func_id, ret);
4014                         return ret;
4015                 }
4016         }
4017
4018         return 0;
4019 }
4020
4021 static void
4022 hns3_promisc_uninit(struct hns3_hw *hw)
4023 {
4024         struct hns3_promisc_param param;
4025         uint16_t func_id;
4026         int ret;
4027
4028         func_id = HNS3_PF_FUNC_ID;
4029
4030         /*
4031          * In current version VFs are not supported when PF is driven by
4032          * DPDK driver, and VFs' promisc mode status has been cleared during
4033          * init and their status will not change. So just clear PF's promisc
4034          * mode status during uninit.
4035          */
4036         hns3_promisc_param_init(&param, false, false, false, func_id);
4037         ret = hns3_cmd_set_promisc_mode(hw, &param);
4038         if (ret)
4039                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4040                                 " uninit, ret = %d", ret);
4041 }
4042
4043 static int
4044 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4045 {
4046         bool allmulti = dev->data->all_multicast ? true : false;
4047         struct hns3_adapter *hns = dev->data->dev_private;
4048         struct hns3_hw *hw = &hns->hw;
4049         uint64_t offloads;
4050         int err;
4051         int ret;
4052
4053         rte_spinlock_lock(&hw->lock);
4054         ret = hns3_set_promisc_mode(hw, true, true);
4055         if (ret) {
4056                 rte_spinlock_unlock(&hw->lock);
4057                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4058                          ret);
4059                 return ret;
4060         }
4061
4062         /*
4063          * When promiscuous mode was enabled, disable the vlan filter to let
4064          * all packets coming in in the receiving direction.
4065          */
4066         offloads = dev->data->dev_conf.rxmode.offloads;
4067         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4068                 ret = hns3_enable_vlan_filter(hns, false);
4069                 if (ret) {
4070                         hns3_err(hw, "failed to enable promiscuous mode due to "
4071                                      "failure to disable vlan filter, ret = %d",
4072                                  ret);
4073                         err = hns3_set_promisc_mode(hw, false, allmulti);
4074                         if (err)
4075                                 hns3_err(hw, "failed to restore promiscuous "
4076                                          "status after disable vlan filter "
4077                                          "failed during enabling promiscuous "
4078                                          "mode, ret = %d", ret);
4079                 }
4080         }
4081
4082         rte_spinlock_unlock(&hw->lock);
4083
4084         return ret;
4085 }
4086
4087 static int
4088 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4089 {
4090         bool allmulti = dev->data->all_multicast ? true : false;
4091         struct hns3_adapter *hns = dev->data->dev_private;
4092         struct hns3_hw *hw = &hns->hw;
4093         uint64_t offloads;
4094         int err;
4095         int ret;
4096
4097         /* If now in all_multicast mode, must remain in all_multicast mode. */
4098         rte_spinlock_lock(&hw->lock);
4099         ret = hns3_set_promisc_mode(hw, false, allmulti);
4100         if (ret) {
4101                 rte_spinlock_unlock(&hw->lock);
4102                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4103                          ret);
4104                 return ret;
4105         }
4106         /* when promiscuous mode was disabled, restore the vlan filter status */
4107         offloads = dev->data->dev_conf.rxmode.offloads;
4108         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4109                 ret = hns3_enable_vlan_filter(hns, true);
4110                 if (ret) {
4111                         hns3_err(hw, "failed to disable promiscuous mode due to"
4112                                  " failure to restore vlan filter, ret = %d",
4113                                  ret);
4114                         err = hns3_set_promisc_mode(hw, true, true);
4115                         if (err)
4116                                 hns3_err(hw, "failed to restore promiscuous "
4117                                          "status after enabling vlan filter "
4118                                          "failed during disabling promiscuous "
4119                                          "mode, ret = %d", ret);
4120                 }
4121         }
4122         rte_spinlock_unlock(&hw->lock);
4123
4124         return ret;
4125 }
4126
4127 static int
4128 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4129 {
4130         struct hns3_adapter *hns = dev->data->dev_private;
4131         struct hns3_hw *hw = &hns->hw;
4132         int ret;
4133
4134         if (dev->data->promiscuous)
4135                 return 0;
4136
4137         rte_spinlock_lock(&hw->lock);
4138         ret = hns3_set_promisc_mode(hw, false, true);
4139         rte_spinlock_unlock(&hw->lock);
4140         if (ret)
4141                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4142                          ret);
4143
4144         return ret;
4145 }
4146
4147 static int
4148 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4149 {
4150         struct hns3_adapter *hns = dev->data->dev_private;
4151         struct hns3_hw *hw = &hns->hw;
4152         int ret;
4153
4154         /* If now in promiscuous mode, must remain in all_multicast mode. */
4155         if (dev->data->promiscuous)
4156                 return 0;
4157
4158         rte_spinlock_lock(&hw->lock);
4159         ret = hns3_set_promisc_mode(hw, false, false);
4160         rte_spinlock_unlock(&hw->lock);
4161         if (ret)
4162                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4163                          ret);
4164
4165         return ret;
4166 }
4167
4168 static int
4169 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4170 {
4171         struct hns3_hw *hw = &hns->hw;
4172         bool allmulti = hw->data->all_multicast ? true : false;
4173         int ret;
4174
4175         if (hw->data->promiscuous) {
4176                 ret = hns3_set_promisc_mode(hw, true, true);
4177                 if (ret)
4178                         hns3_err(hw, "failed to restore promiscuous mode, "
4179                                  "ret = %d", ret);
4180                 return ret;
4181         }
4182
4183         ret = hns3_set_promisc_mode(hw, false, allmulti);
4184         if (ret)
4185                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4186                          ret);
4187         return ret;
4188 }
4189
4190 static int
4191 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4192 {
4193         struct hns3_sfp_speed_cmd *resp;
4194         struct hns3_cmd_desc desc;
4195         int ret;
4196
4197         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4198         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4199         ret = hns3_cmd_send(hw, &desc, 1);
4200         if (ret == -EOPNOTSUPP) {
4201                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4202                 return ret;
4203         } else if (ret) {
4204                 hns3_err(hw, "get sfp speed failed %d", ret);
4205                 return ret;
4206         }
4207
4208         *speed = resp->sfp_speed;
4209
4210         return 0;
4211 }
4212
4213 static uint8_t
4214 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4215 {
4216         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4217                 duplex = ETH_LINK_FULL_DUPLEX;
4218
4219         return duplex;
4220 }
4221
4222 static int
4223 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4224 {
4225         struct hns3_mac *mac = &hw->mac;
4226         int ret;
4227
4228         duplex = hns3_check_speed_dup(duplex, speed);
4229         if (mac->link_speed == speed && mac->link_duplex == duplex)
4230                 return 0;
4231
4232         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4233         if (ret)
4234                 return ret;
4235
4236         mac->link_speed = speed;
4237         mac->link_duplex = duplex;
4238
4239         return 0;
4240 }
4241
4242 static int
4243 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4244 {
4245         struct hns3_adapter *hns = eth_dev->data->dev_private;
4246         struct hns3_hw *hw = &hns->hw;
4247         struct hns3_pf *pf = &hns->pf;
4248         uint32_t speed;
4249         int ret;
4250
4251         /* If IMP do not support get SFP/qSFP speed, return directly */
4252         if (!pf->support_sfp_query)
4253                 return 0;
4254
4255         ret = hns3_get_sfp_speed(hw, &speed);
4256         if (ret == -EOPNOTSUPP) {
4257                 pf->support_sfp_query = false;
4258                 return ret;
4259         } else if (ret)
4260                 return ret;
4261
4262         if (speed == ETH_SPEED_NUM_NONE)
4263                 return 0; /* do nothing if no SFP */
4264
4265         /* Config full duplex for SFP */
4266         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4267 }
4268
4269 static int
4270 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4271 {
4272         struct hns3_config_mac_mode_cmd *req;
4273         struct hns3_cmd_desc desc;
4274         uint32_t loop_en = 0;
4275         uint8_t val = 0;
4276         int ret;
4277
4278         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4279
4280         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4281         if (enable)
4282                 val = 1;
4283         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4284         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4285         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4286         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4287         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4288         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4289         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4290         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4291         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4292         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4293
4294         /*
4295          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4296          * when receiving frames. Otherwise, CRC will be stripped.
4297          */
4298         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4299                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4300         else
4301                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4302         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4303         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4304         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4305         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4306
4307         ret = hns3_cmd_send(hw, &desc, 1);
4308         if (ret)
4309                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4310
4311         return ret;
4312 }
4313
4314 static int
4315 hns3_get_mac_link_status(struct hns3_hw *hw)
4316 {
4317         struct hns3_link_status_cmd *req;
4318         struct hns3_cmd_desc desc;
4319         int link_status;
4320         int ret;
4321
4322         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4323         ret = hns3_cmd_send(hw, &desc, 1);
4324         if (ret) {
4325                 hns3_err(hw, "get link status cmd failed %d", ret);
4326                 return ETH_LINK_DOWN;
4327         }
4328
4329         req = (struct hns3_link_status_cmd *)desc.data;
4330         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4331
4332         return !!link_status;
4333 }
4334
4335 void
4336 hns3_update_link_status(struct hns3_hw *hw)
4337 {
4338         int state;
4339
4340         state = hns3_get_mac_link_status(hw);
4341         if (state != hw->mac.link_status) {
4342                 hw->mac.link_status = state;
4343                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4344         }
4345 }
4346
4347 static void
4348 hns3_service_handler(void *param)
4349 {
4350         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4351         struct hns3_adapter *hns = eth_dev->data->dev_private;
4352         struct hns3_hw *hw = &hns->hw;
4353
4354         if (!hns3_is_reset_pending(hns)) {
4355                 hns3_update_speed_duplex(eth_dev);
4356                 hns3_update_link_status(hw);
4357         } else
4358                 hns3_warn(hw, "Cancel the query when reset is pending");
4359
4360         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4361 }
4362
4363 static int
4364 hns3_init_hardware(struct hns3_adapter *hns)
4365 {
4366         struct hns3_hw *hw = &hns->hw;
4367         int ret;
4368
4369         ret = hns3_map_tqp(hw);
4370         if (ret) {
4371                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4372                 return ret;
4373         }
4374
4375         ret = hns3_init_umv_space(hw);
4376         if (ret) {
4377                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4378                 return ret;
4379         }
4380
4381         ret = hns3_mac_init(hw);
4382         if (ret) {
4383                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4384                 goto err_mac_init;
4385         }
4386
4387         ret = hns3_init_mgr_tbl(hw);
4388         if (ret) {
4389                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4390                 goto err_mac_init;
4391         }
4392
4393         ret = hns3_promisc_init(hw);
4394         if (ret) {
4395                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4396                              ret);
4397                 goto err_mac_init;
4398         }
4399
4400         ret = hns3_init_vlan_config(hns);
4401         if (ret) {
4402                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4403                 goto err_mac_init;
4404         }
4405
4406         ret = hns3_dcb_init(hw);
4407         if (ret) {
4408                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4409                 goto err_mac_init;
4410         }
4411
4412         ret = hns3_init_fd_config(hns);
4413         if (ret) {
4414                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4415                 goto err_mac_init;
4416         }
4417
4418         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4419         if (ret) {
4420                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4421                 goto err_mac_init;
4422         }
4423
4424         ret = hns3_config_gro(hw, false);
4425         if (ret) {
4426                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4427                 goto err_mac_init;
4428         }
4429
4430         /*
4431          * In the initialization clearing the all hardware mapping relationship
4432          * configurations between queues and interrupt vectors is needed, so
4433          * some error caused by the residual configurations, such as the
4434          * unexpected interrupt, can be avoid.
4435          */
4436         ret = hns3_init_ring_with_vector(hw);
4437         if (ret) {
4438                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4439                 goto err_mac_init;
4440         }
4441
4442         return 0;
4443
4444 err_mac_init:
4445         hns3_uninit_umv_space(hw);
4446         return ret;
4447 }
4448
4449 static int
4450 hns3_clear_hw(struct hns3_hw *hw)
4451 {
4452         struct hns3_cmd_desc desc;
4453         int ret;
4454
4455         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4456
4457         ret = hns3_cmd_send(hw, &desc, 1);
4458         if (ret && ret != -EOPNOTSUPP)
4459                 return ret;
4460
4461         return 0;
4462 }
4463
4464 static void
4465 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4466 {
4467         uint32_t val;
4468
4469         /*
4470          * The new firmware support report more hardware error types by
4471          * msix mode. These errors are defined as RAS errors in hardware
4472          * and belong to a different type from the MSI-x errors processed
4473          * by the network driver.
4474          *
4475          * Network driver should open the new error report on initialition
4476          */
4477         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4478         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4479         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4480 }
4481
4482 static int
4483 hns3_init_pf(struct rte_eth_dev *eth_dev)
4484 {
4485         struct rte_device *dev = eth_dev->device;
4486         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4487         struct hns3_adapter *hns = eth_dev->data->dev_private;
4488         struct hns3_hw *hw = &hns->hw;
4489         int ret;
4490
4491         PMD_INIT_FUNC_TRACE();
4492
4493         /* Get hardware io base address from pcie BAR2 IO space */
4494         hw->io_base = pci_dev->mem_resource[2].addr;
4495
4496         /* Firmware command queue initialize */
4497         ret = hns3_cmd_init_queue(hw);
4498         if (ret) {
4499                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4500                 goto err_cmd_init_queue;
4501         }
4502
4503         hns3_clear_all_event_cause(hw);
4504
4505         /* Firmware command initialize */
4506         ret = hns3_cmd_init(hw);
4507         if (ret) {
4508                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4509                 goto err_cmd_init;
4510         }
4511
4512         /*
4513          * To ensure that the hardware environment is clean during
4514          * initialization, the driver actively clear the hardware environment
4515          * during initialization, including PF and corresponding VFs' vlan, mac,
4516          * flow table configurations, etc.
4517          */
4518         ret = hns3_clear_hw(hw);
4519         if (ret) {
4520                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4521                 goto err_cmd_init;
4522         }
4523
4524         hns3_config_all_msix_error(hw, true);
4525
4526         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4527                                          hns3_interrupt_handler,
4528                                          eth_dev);
4529         if (ret) {
4530                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4531                 goto err_intr_callback_register;
4532         }
4533
4534         /* Enable interrupt */
4535         rte_intr_enable(&pci_dev->intr_handle);
4536         hns3_pf_enable_irq0(hw);
4537
4538         /* Get configuration */
4539         ret = hns3_get_configuration(hw);
4540         if (ret) {
4541                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4542                 goto err_get_config;
4543         }
4544
4545         ret = hns3_init_hardware(hns);
4546         if (ret) {
4547                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4548                 goto err_get_config;
4549         }
4550
4551         /* Initialize flow director filter list & hash */
4552         ret = hns3_fdir_filter_init(hns);
4553         if (ret) {
4554                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4555                 goto err_hw_init;
4556         }
4557
4558         hns3_set_default_rss_args(hw);
4559
4560         ret = hns3_enable_hw_error_intr(hns, true);
4561         if (ret) {
4562                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4563                              ret);
4564                 goto err_fdir;
4565         }
4566
4567         return 0;
4568
4569 err_fdir:
4570         hns3_fdir_filter_uninit(hns);
4571 err_hw_init:
4572         hns3_uninit_umv_space(hw);
4573
4574 err_get_config:
4575         hns3_pf_disable_irq0(hw);
4576         rte_intr_disable(&pci_dev->intr_handle);
4577         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4578                              eth_dev);
4579 err_intr_callback_register:
4580 err_cmd_init:
4581         hns3_cmd_uninit(hw);
4582         hns3_cmd_destroy_queue(hw);
4583 err_cmd_init_queue:
4584         hw->io_base = NULL;
4585
4586         return ret;
4587 }
4588
4589 static void
4590 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4591 {
4592         struct hns3_adapter *hns = eth_dev->data->dev_private;
4593         struct rte_device *dev = eth_dev->device;
4594         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4595         struct hns3_hw *hw = &hns->hw;
4596
4597         PMD_INIT_FUNC_TRACE();
4598
4599         hns3_enable_hw_error_intr(hns, false);
4600         hns3_rss_uninit(hns);
4601         (void)hns3_config_gro(hw, false);
4602         hns3_promisc_uninit(hw);
4603         hns3_fdir_filter_uninit(hns);
4604         hns3_uninit_umv_space(hw);
4605         hns3_pf_disable_irq0(hw);
4606         rte_intr_disable(&pci_dev->intr_handle);
4607         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4608                              eth_dev);
4609         hns3_config_all_msix_error(hw, false);
4610         hns3_cmd_uninit(hw);
4611         hns3_cmd_destroy_queue(hw);
4612         hw->io_base = NULL;
4613 }
4614
4615 static int
4616 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4617 {
4618         struct hns3_hw *hw = &hns->hw;
4619         int ret;
4620
4621         ret = hns3_dcb_cfg_update(hns);
4622         if (ret)
4623                 return ret;
4624
4625         /* Enable queues */
4626         ret = hns3_start_queues(hns, reset_queue);
4627         if (ret) {
4628                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4629                 return ret;
4630         }
4631
4632         /* Enable MAC */
4633         ret = hns3_cfg_mac_mode(hw, true);
4634         if (ret) {
4635                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4636                 goto err_config_mac_mode;
4637         }
4638         return 0;
4639
4640 err_config_mac_mode:
4641         hns3_stop_queues(hns, true);
4642         return ret;
4643 }
4644
4645 static int
4646 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4647 {
4648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4649         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4650         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4652         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4653         uint32_t intr_vector;
4654         uint16_t q_id;
4655         int ret;
4656
4657         if (dev->data->dev_conf.intr_conf.rxq == 0)
4658                 return 0;
4659
4660         /* disable uio/vfio intr/eventfd mapping */
4661         rte_intr_disable(intr_handle);
4662
4663         /* check and configure queue intr-vector mapping */
4664         if (rte_intr_cap_multiple(intr_handle) ||
4665             !RTE_ETH_DEV_SRIOV(dev).active) {
4666                 intr_vector = hw->used_rx_queues;
4667                 /* creates event fd for each intr vector when MSIX is used */
4668                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4669                         return -EINVAL;
4670         }
4671         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4672                 intr_handle->intr_vec =
4673                         rte_zmalloc("intr_vec",
4674                                     hw->used_rx_queues * sizeof(int), 0);
4675                 if (intr_handle->intr_vec == NULL) {
4676                         hns3_err(hw, "Failed to allocate %d rx_queues"
4677                                      " intr_vec", hw->used_rx_queues);
4678                         ret = -ENOMEM;
4679                         goto alloc_intr_vec_error;
4680                 }
4681         }
4682
4683         if (rte_intr_allow_others(intr_handle)) {
4684                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4685                 base = RTE_INTR_VEC_RXTX_OFFSET;
4686         }
4687         if (rte_intr_dp_is_en(intr_handle)) {
4688                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4689                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4690                                                          HNS3_RING_TYPE_RX,
4691                                                          q_id);
4692                         if (ret)
4693                                 goto bind_vector_error;
4694                         intr_handle->intr_vec[q_id] = vec;
4695                         if (vec < base + intr_handle->nb_efd - 1)
4696                                 vec++;
4697                 }
4698         }
4699         rte_intr_enable(intr_handle);
4700         return 0;
4701
4702 bind_vector_error:
4703         rte_intr_efd_disable(intr_handle);
4704         if (intr_handle->intr_vec) {
4705                 free(intr_handle->intr_vec);
4706                 intr_handle->intr_vec = NULL;
4707         }
4708         return ret;
4709 alloc_intr_vec_error:
4710         rte_intr_efd_disable(intr_handle);
4711         return ret;
4712 }
4713
4714 static int
4715 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4716 {
4717         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4718         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4720         uint16_t q_id;
4721         int ret;
4722
4723         if (dev->data->dev_conf.intr_conf.rxq == 0)
4724                 return 0;
4725
4726         if (rte_intr_dp_is_en(intr_handle)) {
4727                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4728                         ret = hns3_bind_ring_with_vector(hw,
4729                                         intr_handle->intr_vec[q_id], true,
4730                                         HNS3_RING_TYPE_RX, q_id);
4731                         if (ret)
4732                                 return ret;
4733                 }
4734         }
4735
4736         return 0;
4737 }
4738
4739 static void
4740 hns3_restore_filter(struct rte_eth_dev *dev)
4741 {
4742         hns3_restore_rss_filter(dev);
4743 }
4744
4745 static int
4746 hns3_dev_start(struct rte_eth_dev *dev)
4747 {
4748         struct hns3_adapter *hns = dev->data->dev_private;
4749         struct hns3_hw *hw = &hns->hw;
4750         int ret;
4751
4752         PMD_INIT_FUNC_TRACE();
4753         if (rte_atomic16_read(&hw->reset.resetting))
4754                 return -EBUSY;
4755
4756         rte_spinlock_lock(&hw->lock);
4757         hw->adapter_state = HNS3_NIC_STARTING;
4758
4759         ret = hns3_do_start(hns, true);
4760         if (ret) {
4761                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4762                 rte_spinlock_unlock(&hw->lock);
4763                 return ret;
4764         }
4765         ret = hns3_map_rx_interrupt(dev);
4766         if (ret) {
4767                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4768                 rte_spinlock_unlock(&hw->lock);
4769                 return ret;
4770         }
4771
4772         hw->adapter_state = HNS3_NIC_STARTED;
4773         rte_spinlock_unlock(&hw->lock);
4774
4775         hns3_rx_scattered_calc(dev);
4776         hns3_set_rxtx_function(dev);
4777         hns3_mp_req_start_rxtx(dev);
4778         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4779
4780         hns3_restore_filter(dev);
4781
4782         /* Enable interrupt of all rx queues before enabling queues */
4783         hns3_dev_all_rx_queue_intr_enable(hw, true);
4784         /*
4785          * When finished the initialization, enable queues to receive/transmit
4786          * packets.
4787          */
4788         hns3_enable_all_queues(hw, true);
4789
4790         hns3_info(hw, "hns3 dev start successful!");
4791         return 0;
4792 }
4793
4794 static int
4795 hns3_do_stop(struct hns3_adapter *hns)
4796 {
4797         struct hns3_hw *hw = &hns->hw;
4798         bool reset_queue;
4799         int ret;
4800
4801         ret = hns3_cfg_mac_mode(hw, false);
4802         if (ret)
4803                 return ret;
4804         hw->mac.link_status = ETH_LINK_DOWN;
4805
4806         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4807                 hns3_configure_all_mac_addr(hns, true);
4808                 reset_queue = true;
4809         } else
4810                 reset_queue = false;
4811         hw->mac.default_addr_setted = false;
4812         return hns3_stop_queues(hns, reset_queue);
4813 }
4814
4815 static void
4816 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4817 {
4818         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4819         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4820         struct hns3_adapter *hns = dev->data->dev_private;
4821         struct hns3_hw *hw = &hns->hw;
4822         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4823         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4824         uint16_t q_id;
4825
4826         if (dev->data->dev_conf.intr_conf.rxq == 0)
4827                 return;
4828
4829         /* unmap the ring with vector */
4830         if (rte_intr_allow_others(intr_handle)) {
4831                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4832                 base = RTE_INTR_VEC_RXTX_OFFSET;
4833         }
4834         if (rte_intr_dp_is_en(intr_handle)) {
4835                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4836                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4837                                                          HNS3_RING_TYPE_RX,
4838                                                          q_id);
4839                         if (vec < base + intr_handle->nb_efd - 1)
4840                                 vec++;
4841                 }
4842         }
4843         /* Clean datapath event and queue/vec mapping */
4844         rte_intr_efd_disable(intr_handle);
4845         if (intr_handle->intr_vec) {
4846                 rte_free(intr_handle->intr_vec);
4847                 intr_handle->intr_vec = NULL;
4848         }
4849 }
4850
4851 static void
4852 hns3_dev_stop(struct rte_eth_dev *dev)
4853 {
4854         struct hns3_adapter *hns = dev->data->dev_private;
4855         struct hns3_hw *hw = &hns->hw;
4856
4857         PMD_INIT_FUNC_TRACE();
4858
4859         hw->adapter_state = HNS3_NIC_STOPPING;
4860         hns3_set_rxtx_function(dev);
4861         rte_wmb();
4862         /* Disable datapath on secondary process. */
4863         hns3_mp_req_stop_rxtx(dev);
4864         /* Prevent crashes when queues are still in use. */
4865         rte_delay_ms(hw->tqps_num);
4866
4867         rte_spinlock_lock(&hw->lock);
4868         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4869                 hns3_do_stop(hns);
4870                 hns3_unmap_rx_interrupt(dev);
4871                 hns3_dev_release_mbufs(hns);
4872                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4873         }
4874         hns3_rx_scattered_reset(dev);
4875         rte_eal_alarm_cancel(hns3_service_handler, dev);
4876         rte_spinlock_unlock(&hw->lock);
4877 }
4878
4879 static int
4880 hns3_dev_close(struct rte_eth_dev *eth_dev)
4881 {
4882         struct hns3_adapter *hns = eth_dev->data->dev_private;
4883         struct hns3_hw *hw = &hns->hw;
4884
4885         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4886                 rte_free(eth_dev->process_private);
4887                 eth_dev->process_private = NULL;
4888                 return 0;
4889         }
4890
4891         if (hw->adapter_state == HNS3_NIC_STARTED)
4892                 hns3_dev_stop(eth_dev);
4893
4894         hw->adapter_state = HNS3_NIC_CLOSING;
4895         hns3_reset_abort(hns);
4896         hw->adapter_state = HNS3_NIC_CLOSED;
4897
4898         hns3_configure_all_mc_mac_addr(hns, true);
4899         hns3_remove_all_vlan_table(hns);
4900         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4901         hns3_uninit_pf(eth_dev);
4902         hns3_free_all_queues(eth_dev);
4903         rte_free(hw->reset.wait_data);
4904         rte_free(eth_dev->process_private);
4905         eth_dev->process_private = NULL;
4906         hns3_mp_uninit_primary();
4907         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4908
4909         return 0;
4910 }
4911
4912 static int
4913 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4914 {
4915         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4916         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4917
4918         fc_conf->pause_time = pf->pause_time;
4919
4920         /* return fc current mode */
4921         switch (hw->current_mode) {
4922         case HNS3_FC_FULL:
4923                 fc_conf->mode = RTE_FC_FULL;
4924                 break;
4925         case HNS3_FC_TX_PAUSE:
4926                 fc_conf->mode = RTE_FC_TX_PAUSE;
4927                 break;
4928         case HNS3_FC_RX_PAUSE:
4929                 fc_conf->mode = RTE_FC_RX_PAUSE;
4930                 break;
4931         case HNS3_FC_NONE:
4932         default:
4933                 fc_conf->mode = RTE_FC_NONE;
4934                 break;
4935         }
4936
4937         return 0;
4938 }
4939
4940 static void
4941 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4942 {
4943         switch (mode) {
4944         case RTE_FC_NONE:
4945                 hw->requested_mode = HNS3_FC_NONE;
4946                 break;
4947         case RTE_FC_RX_PAUSE:
4948                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4949                 break;
4950         case RTE_FC_TX_PAUSE:
4951                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4952                 break;
4953         case RTE_FC_FULL:
4954                 hw->requested_mode = HNS3_FC_FULL;
4955                 break;
4956         default:
4957                 hw->requested_mode = HNS3_FC_NONE;
4958                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4959                           "configured to RTE_FC_NONE", mode);
4960                 break;
4961         }
4962 }
4963
4964 static int
4965 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4966 {
4967         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4969         int ret;
4970
4971         if (fc_conf->high_water || fc_conf->low_water ||
4972             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4973                 hns3_err(hw, "Unsupported flow control settings specified, "
4974                          "high_water(%u), low_water(%u), send_xon(%u) and "
4975                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4976                          fc_conf->high_water, fc_conf->low_water,
4977                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4978                 return -EINVAL;
4979         }
4980         if (fc_conf->autoneg) {
4981                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4982                 return -EINVAL;
4983         }
4984         if (!fc_conf->pause_time) {
4985                 hns3_err(hw, "Invalid pause time %d setting.",
4986                          fc_conf->pause_time);
4987                 return -EINVAL;
4988         }
4989
4990         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4991             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4992                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4993                          "current_fc_status = %d", hw->current_fc_status);
4994                 return -EOPNOTSUPP;
4995         }
4996
4997         hns3_get_fc_mode(hw, fc_conf->mode);
4998         if (hw->requested_mode == hw->current_mode &&
4999             pf->pause_time == fc_conf->pause_time)
5000                 return 0;
5001
5002         rte_spinlock_lock(&hw->lock);
5003         ret = hns3_fc_enable(dev, fc_conf);
5004         rte_spinlock_unlock(&hw->lock);
5005
5006         return ret;
5007 }
5008
5009 static int
5010 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5011                             struct rte_eth_pfc_conf *pfc_conf)
5012 {
5013         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5015         uint8_t priority;
5016         int ret;
5017
5018         if (!hns3_dev_dcb_supported(hw)) {
5019                 hns3_err(hw, "This port does not support dcb configurations.");
5020                 return -EOPNOTSUPP;
5021         }
5022
5023         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5024             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5025                 hns3_err(hw, "Unsupported flow control settings specified, "
5026                          "high_water(%u), low_water(%u), send_xon(%u) and "
5027                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5028                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5029                          pfc_conf->fc.send_xon,
5030                          pfc_conf->fc.mac_ctrl_frame_fwd);
5031                 return -EINVAL;
5032         }
5033         if (pfc_conf->fc.autoneg) {
5034                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5035                 return -EINVAL;
5036         }
5037         if (pfc_conf->fc.pause_time == 0) {
5038                 hns3_err(hw, "Invalid pause time %d setting.",
5039                          pfc_conf->fc.pause_time);
5040                 return -EINVAL;
5041         }
5042
5043         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5044             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5045                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5046                              "current_fc_status = %d", hw->current_fc_status);
5047                 return -EOPNOTSUPP;
5048         }
5049
5050         priority = pfc_conf->priority;
5051         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5052         if (hw->dcb_info.pfc_en & BIT(priority) &&
5053             hw->requested_mode == hw->current_mode &&
5054             pfc_conf->fc.pause_time == pf->pause_time)
5055                 return 0;
5056
5057         rte_spinlock_lock(&hw->lock);
5058         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5059         rte_spinlock_unlock(&hw->lock);
5060
5061         return ret;
5062 }
5063
5064 static int
5065 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5066 {
5067         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5069         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5070         int i;
5071
5072         rte_spinlock_lock(&hw->lock);
5073         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5074                 dcb_info->nb_tcs = pf->local_max_tc;
5075         else
5076                 dcb_info->nb_tcs = 1;
5077
5078         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5079                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5080         for (i = 0; i < dcb_info->nb_tcs; i++)
5081                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5082
5083         for (i = 0; i < hw->num_tc; i++) {
5084                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5085                 dcb_info->tc_queue.tc_txq[0][i].base =
5086                                                 hw->tc_queue[i].tqp_offset;
5087                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5088                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5089                                                 hw->tc_queue[i].tqp_count;
5090         }
5091         rte_spinlock_unlock(&hw->lock);
5092
5093         return 0;
5094 }
5095
5096 static int
5097 hns3_reinit_dev(struct hns3_adapter *hns)
5098 {
5099         struct hns3_hw *hw = &hns->hw;
5100         int ret;
5101
5102         ret = hns3_cmd_init(hw);
5103         if (ret) {
5104                 hns3_err(hw, "Failed to init cmd: %d", ret);
5105                 return ret;
5106         }
5107
5108         ret = hns3_reset_all_queues(hns);
5109         if (ret) {
5110                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5111                 return ret;
5112         }
5113
5114         ret = hns3_init_hardware(hns);
5115         if (ret) {
5116                 hns3_err(hw, "Failed to init hardware: %d", ret);
5117                 return ret;
5118         }
5119
5120         ret = hns3_enable_hw_error_intr(hns, true);
5121         if (ret) {
5122                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5123                              ret);
5124                 return ret;
5125         }
5126         hns3_info(hw, "Reset done, driver initialization finished.");
5127
5128         return 0;
5129 }
5130
5131 static bool
5132 is_pf_reset_done(struct hns3_hw *hw)
5133 {
5134         uint32_t val, reg, reg_bit;
5135
5136         switch (hw->reset.level) {
5137         case HNS3_IMP_RESET:
5138                 reg = HNS3_GLOBAL_RESET_REG;
5139                 reg_bit = HNS3_IMP_RESET_BIT;
5140                 break;
5141         case HNS3_GLOBAL_RESET:
5142                 reg = HNS3_GLOBAL_RESET_REG;
5143                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5144                 break;
5145         case HNS3_FUNC_RESET:
5146                 reg = HNS3_FUN_RST_ING;
5147                 reg_bit = HNS3_FUN_RST_ING_B;
5148                 break;
5149         case HNS3_FLR_RESET:
5150         default:
5151                 hns3_err(hw, "Wait for unsupported reset level: %d",
5152                          hw->reset.level);
5153                 return true;
5154         }
5155         val = hns3_read_dev(hw, reg);
5156         if (hns3_get_bit(val, reg_bit))
5157                 return false;
5158         else
5159                 return true;
5160 }
5161
5162 bool
5163 hns3_is_reset_pending(struct hns3_adapter *hns)
5164 {
5165         struct hns3_hw *hw = &hns->hw;
5166         enum hns3_reset_level reset;
5167
5168         hns3_check_event_cause(hns, NULL);
5169         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5170         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5171                 hns3_warn(hw, "High level reset %d is pending", reset);
5172                 return true;
5173         }
5174         reset = hns3_get_reset_level(hns, &hw->reset.request);
5175         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5176                 hns3_warn(hw, "High level reset %d is request", reset);
5177                 return true;
5178         }
5179         return false;
5180 }
5181
5182 static int
5183 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5184 {
5185         struct hns3_hw *hw = &hns->hw;
5186         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5187         struct timeval tv;
5188
5189         if (wait_data->result == HNS3_WAIT_SUCCESS)
5190                 return 0;
5191         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5192                 gettimeofday(&tv, NULL);
5193                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5194                           tv.tv_sec, tv.tv_usec);
5195                 return -ETIME;
5196         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5197                 return -EAGAIN;
5198
5199         wait_data->hns = hns;
5200         wait_data->check_completion = is_pf_reset_done;
5201         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5202                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5203         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5204         wait_data->count = HNS3_RESET_WAIT_CNT;
5205         wait_data->result = HNS3_WAIT_REQUEST;
5206         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5207         return -EAGAIN;
5208 }
5209
5210 static int
5211 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5212 {
5213         struct hns3_cmd_desc desc;
5214         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5215
5216         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5217         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5218         req->fun_reset_vfid = func_id;
5219
5220         return hns3_cmd_send(hw, &desc, 1);
5221 }
5222
5223 static int
5224 hns3_imp_reset_cmd(struct hns3_hw *hw)
5225 {
5226         struct hns3_cmd_desc desc;
5227
5228         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5229         desc.data[0] = 0xeedd;
5230
5231         return hns3_cmd_send(hw, &desc, 1);
5232 }
5233
5234 static void
5235 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5236 {
5237         struct hns3_hw *hw = &hns->hw;
5238         struct timeval tv;
5239         uint32_t val;
5240
5241         gettimeofday(&tv, NULL);
5242         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5243             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5244                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5245                           tv.tv_sec, tv.tv_usec);
5246                 return;
5247         }
5248
5249         switch (reset_level) {
5250         case HNS3_IMP_RESET:
5251                 hns3_imp_reset_cmd(hw);
5252                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5253                           tv.tv_sec, tv.tv_usec);
5254                 break;
5255         case HNS3_GLOBAL_RESET:
5256                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5257                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5258                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5259                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5260                           tv.tv_sec, tv.tv_usec);
5261                 break;
5262         case HNS3_FUNC_RESET:
5263                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5264                           tv.tv_sec, tv.tv_usec);
5265                 /* schedule again to check later */
5266                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5267                 hns3_schedule_reset(hns);
5268                 break;
5269         default:
5270                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5271                 return;
5272         }
5273         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5274 }
5275
5276 static enum hns3_reset_level
5277 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5278 {
5279         struct hns3_hw *hw = &hns->hw;
5280         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5281
5282         /* Return the highest priority reset level amongst all */
5283         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5284                 reset_level = HNS3_IMP_RESET;
5285         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5286                 reset_level = HNS3_GLOBAL_RESET;
5287         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5288                 reset_level = HNS3_FUNC_RESET;
5289         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5290                 reset_level = HNS3_FLR_RESET;
5291
5292         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5293                 return HNS3_NONE_RESET;
5294
5295         return reset_level;
5296 }
5297
5298 static void
5299 hns3_record_imp_error(struct hns3_adapter *hns)
5300 {
5301         struct hns3_hw *hw = &hns->hw;
5302         uint32_t reg_val;
5303
5304         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5305         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5306                 hns3_warn(hw, "Detected IMP RD poison!");
5307                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5308                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5309                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5310         }
5311
5312         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5313                 hns3_warn(hw, "Detected IMP CMDQ error!");
5314                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5315                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5316                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5317         }
5318 }
5319
5320 static int
5321 hns3_prepare_reset(struct hns3_adapter *hns)
5322 {
5323         struct hns3_hw *hw = &hns->hw;
5324         uint32_t reg_val;
5325         int ret;
5326
5327         switch (hw->reset.level) {
5328         case HNS3_FUNC_RESET:
5329                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5330                 if (ret)
5331                         return ret;
5332
5333                 /*
5334                  * After performaning pf reset, it is not necessary to do the
5335                  * mailbox handling or send any command to firmware, because
5336                  * any mailbox handling or command to firmware is only valid
5337                  * after hns3_cmd_init is called.
5338                  */
5339                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5340                 hw->reset.stats.request_cnt++;
5341                 break;
5342         case HNS3_IMP_RESET:
5343                 hns3_record_imp_error(hns);
5344                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5345                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5346                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5347                 break;
5348         default:
5349                 break;
5350         }
5351         return 0;
5352 }
5353
5354 static int
5355 hns3_set_rst_done(struct hns3_hw *hw)
5356 {
5357         struct hns3_pf_rst_done_cmd *req;
5358         struct hns3_cmd_desc desc;
5359
5360         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5361         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5362         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5363         return hns3_cmd_send(hw, &desc, 1);
5364 }
5365
5366 static int
5367 hns3_stop_service(struct hns3_adapter *hns)
5368 {
5369         struct hns3_hw *hw = &hns->hw;
5370         struct rte_eth_dev *eth_dev;
5371
5372         eth_dev = &rte_eth_devices[hw->data->port_id];
5373         if (hw->adapter_state == HNS3_NIC_STARTED)
5374                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5375         hw->mac.link_status = ETH_LINK_DOWN;
5376
5377         hns3_set_rxtx_function(eth_dev);
5378         rte_wmb();
5379         /* Disable datapath on secondary process. */
5380         hns3_mp_req_stop_rxtx(eth_dev);
5381         rte_delay_ms(hw->tqps_num);
5382
5383         rte_spinlock_lock(&hw->lock);
5384         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5385             hw->adapter_state == HNS3_NIC_STOPPING) {
5386                 hns3_do_stop(hns);
5387                 hw->reset.mbuf_deferred_free = true;
5388         } else
5389                 hw->reset.mbuf_deferred_free = false;
5390
5391         /*
5392          * It is cumbersome for hardware to pick-and-choose entries for deletion
5393          * from table space. Hence, for function reset software intervention is
5394          * required to delete the entries
5395          */
5396         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5397                 hns3_configure_all_mc_mac_addr(hns, true);
5398         rte_spinlock_unlock(&hw->lock);
5399
5400         return 0;
5401 }
5402
5403 static int
5404 hns3_start_service(struct hns3_adapter *hns)
5405 {
5406         struct hns3_hw *hw = &hns->hw;
5407         struct rte_eth_dev *eth_dev;
5408
5409         if (hw->reset.level == HNS3_IMP_RESET ||
5410             hw->reset.level == HNS3_GLOBAL_RESET)
5411                 hns3_set_rst_done(hw);
5412         eth_dev = &rte_eth_devices[hw->data->port_id];
5413         hns3_set_rxtx_function(eth_dev);
5414         hns3_mp_req_start_rxtx(eth_dev);
5415         if (hw->adapter_state == HNS3_NIC_STARTED) {
5416                 hns3_service_handler(eth_dev);
5417
5418                 /* Enable interrupt of all rx queues before enabling queues */
5419                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5420                 /*
5421                  * When finished the initialization, enable queues to receive
5422                  * and transmit packets.
5423                  */
5424                 hns3_enable_all_queues(hw, true);
5425         }
5426
5427         return 0;
5428 }
5429
5430 static int
5431 hns3_restore_conf(struct hns3_adapter *hns)
5432 {
5433         struct hns3_hw *hw = &hns->hw;
5434         int ret;
5435
5436         ret = hns3_configure_all_mac_addr(hns, false);
5437         if (ret)
5438                 return ret;
5439
5440         ret = hns3_configure_all_mc_mac_addr(hns, false);
5441         if (ret)
5442                 goto err_mc_mac;
5443
5444         ret = hns3_dev_promisc_restore(hns);
5445         if (ret)
5446                 goto err_promisc;
5447
5448         ret = hns3_restore_vlan_table(hns);
5449         if (ret)
5450                 goto err_promisc;
5451
5452         ret = hns3_restore_vlan_conf(hns);
5453         if (ret)
5454                 goto err_promisc;
5455
5456         ret = hns3_restore_all_fdir_filter(hns);
5457         if (ret)
5458                 goto err_promisc;
5459
5460         ret = hns3_restore_rx_interrupt(hw);
5461         if (ret)
5462                 goto err_promisc;
5463
5464         ret = hns3_restore_gro_conf(hw);
5465         if (ret)
5466                 goto err_promisc;
5467
5468         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5469                 ret = hns3_do_start(hns, false);
5470                 if (ret)
5471                         goto err_promisc;
5472                 hns3_info(hw, "hns3 dev restart successful!");
5473         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5474                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5475         return 0;
5476
5477 err_promisc:
5478         hns3_configure_all_mc_mac_addr(hns, true);
5479 err_mc_mac:
5480         hns3_configure_all_mac_addr(hns, true);
5481         return ret;
5482 }
5483
5484 static void
5485 hns3_reset_service(void *param)
5486 {
5487         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5488         struct hns3_hw *hw = &hns->hw;
5489         enum hns3_reset_level reset_level;
5490         struct timeval tv_delta;
5491         struct timeval tv_start;
5492         struct timeval tv;
5493         uint64_t msec;
5494         int ret;
5495
5496         /*
5497          * The interrupt is not triggered within the delay time.
5498          * The interrupt may have been lost. It is necessary to handle
5499          * the interrupt to recover from the error.
5500          */
5501         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5502                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5503                 hns3_err(hw, "Handling interrupts in delayed tasks");
5504                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5505                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5506                 if (reset_level == HNS3_NONE_RESET) {
5507                         hns3_err(hw, "No reset level is set, try IMP reset");
5508                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5509                 }
5510         }
5511         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5512
5513         /*
5514          * Check if there is any ongoing reset in the hardware. This status can
5515          * be checked from reset_pending. If there is then, we need to wait for
5516          * hardware to complete reset.
5517          *    a. If we are able to figure out in reasonable time that hardware
5518          *       has fully resetted then, we can proceed with driver, client
5519          *       reset.
5520          *    b. else, we can come back later to check this status so re-sched
5521          *       now.
5522          */
5523         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5524         if (reset_level != HNS3_NONE_RESET) {
5525                 gettimeofday(&tv_start, NULL);
5526                 ret = hns3_reset_process(hns, reset_level);
5527                 gettimeofday(&tv, NULL);
5528                 timersub(&tv, &tv_start, &tv_delta);
5529                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5530                        tv_delta.tv_usec / USEC_PER_MSEC;
5531                 if (msec > HNS3_RESET_PROCESS_MS)
5532                         hns3_err(hw, "%d handle long time delta %" PRIx64
5533                                      " ms time=%ld.%.6ld",
5534                                  hw->reset.level, msec,
5535                                  tv.tv_sec, tv.tv_usec);
5536                 if (ret == -EAGAIN)
5537                         return;
5538         }
5539
5540         /* Check if we got any *new* reset requests to be honored */
5541         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5542         if (reset_level != HNS3_NONE_RESET)
5543                 hns3_msix_process(hns, reset_level);
5544 }
5545
5546 static const struct eth_dev_ops hns3_eth_dev_ops = {
5547         .dev_configure      = hns3_dev_configure,
5548         .dev_start          = hns3_dev_start,
5549         .dev_stop           = hns3_dev_stop,
5550         .dev_close          = hns3_dev_close,
5551         .promiscuous_enable = hns3_dev_promiscuous_enable,
5552         .promiscuous_disable = hns3_dev_promiscuous_disable,
5553         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5554         .allmulticast_disable = hns3_dev_allmulticast_disable,
5555         .mtu_set            = hns3_dev_mtu_set,
5556         .stats_get          = hns3_stats_get,
5557         .stats_reset        = hns3_stats_reset,
5558         .xstats_get         = hns3_dev_xstats_get,
5559         .xstats_get_names   = hns3_dev_xstats_get_names,
5560         .xstats_reset       = hns3_dev_xstats_reset,
5561         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5562         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5563         .dev_infos_get          = hns3_dev_infos_get,
5564         .fw_version_get         = hns3_fw_version_get,
5565         .rx_queue_setup         = hns3_rx_queue_setup,
5566         .tx_queue_setup         = hns3_tx_queue_setup,
5567         .rx_queue_release       = hns3_dev_rx_queue_release,
5568         .tx_queue_release       = hns3_dev_tx_queue_release,
5569         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5570         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5571         .rxq_info_get           = hns3_rxq_info_get,
5572         .txq_info_get           = hns3_txq_info_get,
5573         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
5574         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
5575         .flow_ctrl_get          = hns3_flow_ctrl_get,
5576         .flow_ctrl_set          = hns3_flow_ctrl_set,
5577         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5578         .mac_addr_add           = hns3_add_mac_addr,
5579         .mac_addr_remove        = hns3_remove_mac_addr,
5580         .mac_addr_set           = hns3_set_default_mac_addr,
5581         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5582         .link_update            = hns3_dev_link_update,
5583         .rss_hash_update        = hns3_dev_rss_hash_update,
5584         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5585         .reta_update            = hns3_dev_rss_reta_update,
5586         .reta_query             = hns3_dev_rss_reta_query,
5587         .filter_ctrl            = hns3_dev_filter_ctrl,
5588         .vlan_filter_set        = hns3_vlan_filter_set,
5589         .vlan_tpid_set          = hns3_vlan_tpid_set,
5590         .vlan_offload_set       = hns3_vlan_offload_set,
5591         .vlan_pvid_set          = hns3_vlan_pvid_set,
5592         .get_reg                = hns3_get_regs,
5593         .get_dcb_info           = hns3_get_dcb_info,
5594         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5595 };
5596
5597 static const struct hns3_reset_ops hns3_reset_ops = {
5598         .reset_service       = hns3_reset_service,
5599         .stop_service        = hns3_stop_service,
5600         .prepare_reset       = hns3_prepare_reset,
5601         .wait_hardware_ready = hns3_wait_hardware_ready,
5602         .reinit_dev          = hns3_reinit_dev,
5603         .restore_conf        = hns3_restore_conf,
5604         .start_service       = hns3_start_service,
5605 };
5606
5607 static int
5608 hns3_dev_init(struct rte_eth_dev *eth_dev)
5609 {
5610         struct hns3_adapter *hns = eth_dev->data->dev_private;
5611         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
5612         struct rte_ether_addr *eth_addr;
5613         struct hns3_hw *hw = &hns->hw;
5614         int ret;
5615
5616         PMD_INIT_FUNC_TRACE();
5617
5618         eth_dev->process_private = (struct hns3_process_private *)
5619             rte_zmalloc_socket("hns3_filter_list",
5620                                sizeof(struct hns3_process_private),
5621                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5622         if (eth_dev->process_private == NULL) {
5623                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5624                 return -ENOMEM;
5625         }
5626         /* initialize flow filter lists */
5627         hns3_filterlist_init(eth_dev);
5628
5629         hns3_set_rxtx_function(eth_dev);
5630         eth_dev->dev_ops = &hns3_eth_dev_ops;
5631         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5632                 ret = hns3_mp_init_secondary();
5633                 if (ret) {
5634                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
5635                                      "process, ret = %d", ret);
5636                         goto err_mp_init_secondary;
5637                 }
5638
5639                 hw->secondary_cnt++;
5640                 return 0;
5641         }
5642
5643         ret = hns3_mp_init_primary();
5644         if (ret) {
5645                 PMD_INIT_LOG(ERR,
5646                              "Failed to init for primary process, ret = %d",
5647                              ret);
5648                 goto err_mp_init_primary;
5649         }
5650
5651         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5652         hns->is_vf = false;
5653         hw->data = eth_dev->data;
5654
5655         /*
5656          * Set default max packet size according to the mtu
5657          * default vale in DPDK frame.
5658          */
5659         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5660
5661         ret = hns3_reset_init(hw);
5662         if (ret)
5663                 goto err_init_reset;
5664         hw->reset.ops = &hns3_reset_ops;
5665
5666         ret = hns3_init_pf(eth_dev);
5667         if (ret) {
5668                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5669                 goto err_init_pf;
5670         }
5671
5672         /* Allocate memory for storing MAC addresses */
5673         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5674                                                sizeof(struct rte_ether_addr) *
5675                                                HNS3_UC_MACADDR_NUM, 0);
5676         if (eth_dev->data->mac_addrs == NULL) {
5677                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5678                              "to store MAC addresses",
5679                              sizeof(struct rte_ether_addr) *
5680                              HNS3_UC_MACADDR_NUM);
5681                 ret = -ENOMEM;
5682                 goto err_rte_zmalloc;
5683         }
5684
5685         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
5686         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
5687                 rte_eth_random_addr(hw->mac.mac_addr);
5688                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
5689                                 (struct rte_ether_addr *)hw->mac.mac_addr);
5690                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
5691                           "unicast address, using random MAC address %s",
5692                           mac_str);
5693         }
5694         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5695                             &eth_dev->data->mac_addrs[0]);
5696
5697         hw->adapter_state = HNS3_NIC_INITIALIZED;
5698
5699         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5700                 hns3_err(hw, "Reschedule reset service after dev_init");
5701                 hns3_schedule_reset(hns);
5702         } else {
5703                 /* IMP will wait ready flag before reset */
5704                 hns3_notify_reset_ready(hw, false);
5705         }
5706
5707         hns3_info(hw, "hns3 dev initialization successful!");
5708         return 0;
5709
5710 err_rte_zmalloc:
5711         hns3_uninit_pf(eth_dev);
5712
5713 err_init_pf:
5714         rte_free(hw->reset.wait_data);
5715
5716 err_init_reset:
5717         hns3_mp_uninit_primary();
5718
5719 err_mp_init_primary:
5720 err_mp_init_secondary:
5721         eth_dev->dev_ops = NULL;
5722         eth_dev->rx_pkt_burst = NULL;
5723         eth_dev->tx_pkt_burst = NULL;
5724         eth_dev->tx_pkt_prepare = NULL;
5725         rte_free(eth_dev->process_private);
5726         eth_dev->process_private = NULL;
5727         return ret;
5728 }
5729
5730 static int
5731 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5732 {
5733         struct hns3_adapter *hns = eth_dev->data->dev_private;
5734         struct hns3_hw *hw = &hns->hw;
5735
5736         PMD_INIT_FUNC_TRACE();
5737
5738         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5739                 return -EPERM;
5740
5741         eth_dev->dev_ops = NULL;
5742         eth_dev->rx_pkt_burst = NULL;
5743         eth_dev->tx_pkt_burst = NULL;
5744         eth_dev->tx_pkt_prepare = NULL;
5745         if (hw->adapter_state < HNS3_NIC_CLOSING)
5746                 hns3_dev_close(eth_dev);
5747
5748         hw->adapter_state = HNS3_NIC_REMOVED;
5749         return 0;
5750 }
5751
5752 static int
5753 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5754                    struct rte_pci_device *pci_dev)
5755 {
5756         return rte_eth_dev_pci_generic_probe(pci_dev,
5757                                              sizeof(struct hns3_adapter),
5758                                              hns3_dev_init);
5759 }
5760
5761 static int
5762 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5763 {
5764         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5765 }
5766
5767 static const struct rte_pci_id pci_id_hns3_map[] = {
5768         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5769         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5770         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5771         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5772         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5773         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
5774         { .vendor_id = 0, /* sentinel */ },
5775 };
5776
5777 static struct rte_pci_driver rte_hns3_pmd = {
5778         .id_table = pci_id_hns3_map,
5779         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5780         .probe = eth_hns3_pci_probe,
5781         .remove = eth_hns3_pci_remove,
5782 };
5783
5784 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5785 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5786 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5787 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5788 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);