drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_logs.h"
  12 #include "hns3_rxtx.h"
  13 #include "hns3_intr.h"
  14 #include "hns3_regs.h"
  15 #include "hns3_dcb.h"
  16 #include "hns3_mp.h"
  17
  18 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  19 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  20
  21 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  22 #define HNS3_SERVICE_QUICK_INTERVAL     10
  23 #define HNS3_INVALID_PVID               0xFFFF
  24
  25 #define HNS3_FILTER_TYPE_VF             0
  26 #define HNS3_FILTER_TYPE_PORT           1
  27 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  28 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  29 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  30 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  31 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  32 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  33                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  34 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  35                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  36
  37 /* Reset related Registers */
  38 #define HNS3_GLOBAL_RESET_BIT           0
  39 #define HNS3_CORE_RESET_BIT             1
  40 #define HNS3_IMP_RESET_BIT              2
  41 #define HNS3_FUN_RST_ING_B              0
  42
  43 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  44 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  45 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  46 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  47
  48 #define HNS3_RESET_WAIT_MS      100
  49 #define HNS3_RESET_WAIT_CNT     200
  50
  51 /* FEC mode order defined in HNS3 hardware */
  52 #define HNS3_HW_FEC_MODE_NOFEC  0
  53 #define HNS3_HW_FEC_MODE_BASER  1
  54 #define HNS3_HW_FEC_MODE_RS     2
  55
  56 enum hns3_evt_cause {
  57         HNS3_VECTOR0_EVENT_RST,
  58         HNS3_VECTOR0_EVENT_MBX,
  59         HNS3_VECTOR0_EVENT_ERR,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_addr(struct hns3_hw *hw,
 100                             struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105 static int hns3_do_stop(struct hns3_adapter *hns);
 106
 107 void hns3_ether_format_addr(char *buf, uint16_t size,
 108                             const struct rte_ether_addr *ether_addr)
 109 {
 110         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 111                 ether_addr->addr_bytes[0],
 112                 ether_addr->addr_bytes[4],
 113                 ether_addr->addr_bytes[5]);
 114 }
 115
 116 static void
 117 hns3_pf_disable_irq0(struct hns3_hw *hw)
 118 {
 119         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 120 }
 121
 122 static void
 123 hns3_pf_enable_irq0(struct hns3_hw *hw)
 124 {
 125         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 126 }
 127
 128 static enum hns3_evt_cause
 129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 130                           uint32_t *vec_val)
 131 {
 132         struct hns3_hw *hw = &hns->hw;
 133
 134         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 135         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 136         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 137         if (!is_delay) {
 138                 hw->reset.stats.imp_cnt++;
 139                 hns3_warn(hw, "IMP reset detected, clear reset status");
 140         } else {
 141                 hns3_schedule_delayed_reset(hns);
 142                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 143         }
 144
 145         return HNS3_VECTOR0_EVENT_RST;
 146 }
 147
 148 static enum hns3_evt_cause
 149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 150                              uint32_t *vec_val)
 151 {
 152         struct hns3_hw *hw = &hns->hw;
 153
 154         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 155         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 156         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 157         if (!is_delay) {
 158                 hw->reset.stats.global_cnt++;
 159                 hns3_warn(hw, "Global reset detected, clear reset status");
 160         } else {
 161                 hns3_schedule_delayed_reset(hns);
 162                 hns3_warn(hw,
 163                           "Global reset detected, don't clear reset status");
 164         }
 165
 166         return HNS3_VECTOR0_EVENT_RST;
 167 }
 168
 169 static enum hns3_evt_cause
 170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 171 {
 172         struct hns3_hw *hw = &hns->hw;
 173         uint32_t vector0_int_stats;
 174         uint32_t cmdq_src_val;
 175         uint32_t hw_err_src_reg;
 176         uint32_t val;
 177         enum hns3_evt_cause ret;
 178         bool is_delay;
 179
 180         /* fetch the events from their corresponding regs */
 181         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 182         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 183         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 184
 185         is_delay = clearval == NULL ? true : false;
 186         /*
 187          * Assumption: If by any chance reset and mailbox events are reported
 188          * together then we will only process reset event and defer the
 189          * processing of the mailbox events. Since, we would have not cleared
 190          * RX CMDQ event this time we would receive again another interrupt
 191          * from H/W just for the mailbox.
 192          */
 193         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 194                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 195                 goto out;
 196         }
 197
 198         /* Global reset */
 199         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 200                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 201                 goto out;
 202         }
 203
 204         /* check for vector0 msix event source */
 205         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 206             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 207                 val = vector0_int_stats | hw_err_src_reg;
 208                 ret = HNS3_VECTOR0_EVENT_ERR;
 209                 goto out;
 210         }
 211
 212         /* check for vector0 mailbox(=CMDQ RX) event source */
 213         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 214                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 215                 val = cmdq_src_val;
 216                 ret = HNS3_VECTOR0_EVENT_MBX;
 217                 goto out;
 218         }
 219
 220         if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
 221                 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
 222                           vector0_int_stats, cmdq_src_val, hw_err_src_reg);
 223         val = vector0_int_stats;
 224         ret = HNS3_VECTOR0_EVENT_OTHER;
 225 out:
 226
 227         if (clearval)
 228                 *clearval = val;
 229         return ret;
 230 }
 231
 232 static void
 233 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 234 {
 235         if (event_type == HNS3_VECTOR0_EVENT_RST)
 236                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 237         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 238                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 239 }
 240
 241 static void
 242 hns3_clear_all_event_cause(struct hns3_hw *hw)
 243 {
 244         uint32_t vector0_int_stats;
 245         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 246
 247         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 248                 hns3_warn(hw, "Probe during IMP reset interrupt");
 249
 250         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 251                 hns3_warn(hw, "Probe during Global reset interrupt");
 252
 253         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 254                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 255                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 256                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 257         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 258 }
 259
 260 static void
 261 hns3_interrupt_handler(void *param)
 262 {
 263         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 264         struct hns3_adapter *hns = dev->data->dev_private;
 265         struct hns3_hw *hw = &hns->hw;
 266         enum hns3_evt_cause event_cause;
 267         uint32_t clearval = 0;
 268
 269         /* Disable interrupt */
 270         hns3_pf_disable_irq0(hw);
 271
 272         event_cause = hns3_check_event_cause(hns, &clearval);
 273         /* vector 0 interrupt is shared with reset and mailbox source events. */
 274         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 275                 hns3_warn(hw, "Received err interrupt");
 276                 hns3_handle_msix_error(hns, &hw->reset.request);
 277                 hns3_handle_ras_error(hns, &hw->reset.request);
 278                 hns3_schedule_reset(hns);
 279         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 280                 hns3_warn(hw, "Received reset interrupt");
 281                 hns3_schedule_reset(hns);
 282         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 283                 hns3_dev_handle_mbx_msg(hw);
 284         else
 285                 hns3_err(hw, "Received unknown event");
 286
 287         hns3_clear_event_cause(hw, event_cause, clearval);
 288         /* Enable interrupt if it is not cause by reset */
 289         hns3_pf_enable_irq0(hw);
 290 }
 291
 292 static int
 293 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 294 {
 295 #define HNS3_VLAN_ID_OFFSET_STEP        160
 296 #define HNS3_VLAN_BYTE_SIZE             8
 297         struct hns3_vlan_filter_pf_cfg_cmd *req;
 298         struct hns3_hw *hw = &hns->hw;
 299         uint8_t vlan_offset_byte_val;
 300         struct hns3_cmd_desc desc;
 301         uint8_t vlan_offset_byte;
 302         uint8_t vlan_offset_base;
 303         int ret;
 304
 305         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 306
 307         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 308         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 309                            HNS3_VLAN_BYTE_SIZE;
 310         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 311
 312         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 313         req->vlan_offset = vlan_offset_base;
 314         req->vlan_cfg = on ? 0 : 1;
 315         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 316
 317         ret = hns3_cmd_send(hw, &desc, 1);
 318         if (ret)
 319                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 320                          vlan_id, ret);
 321
 322         return ret;
 323 }
 324
 325 static void
 326 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 327 {
 328         struct hns3_user_vlan_table *vlan_entry;
 329         struct hns3_pf *pf = &hns->pf;
 330
 331         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 332                 if (vlan_entry->vlan_id == vlan_id) {
 333                         if (vlan_entry->hd_tbl_status)
 334                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 335                         LIST_REMOVE(vlan_entry, next);
 336                         rte_free(vlan_entry);
 337                         break;
 338                 }
 339         }
 340 }
 341
 342 static void
 343 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 344                         bool writen_to_tbl)
 345 {
 346         struct hns3_user_vlan_table *vlan_entry;
 347         struct hns3_hw *hw = &hns->hw;
 348         struct hns3_pf *pf = &hns->pf;
 349
 350         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 351                 if (vlan_entry->vlan_id == vlan_id)
 352                         return;
 353         }
 354
 355         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 356         if (vlan_entry == NULL) {
 357                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 358                 return;
 359         }
 360
 361         vlan_entry->hd_tbl_status = writen_to_tbl;
 362         vlan_entry->vlan_id = vlan_id;
 363
 364         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 365 }
 366
 367 static int
 368 hns3_restore_vlan_table(struct hns3_adapter *hns)
 369 {
 370         struct hns3_user_vlan_table *vlan_entry;
 371         struct hns3_hw *hw = &hns->hw;
 372         struct hns3_pf *pf = &hns->pf;
 373         uint16_t vlan_id;
 374         int ret = 0;
 375
 376         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 377                 return hns3_vlan_pvid_configure(hns,
 378                                                 hw->port_base_vlan_cfg.pvid, 1);
 379
 380         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 381                 if (vlan_entry->hd_tbl_status) {
 382                         vlan_id = vlan_entry->vlan_id;
 383                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 384                         if (ret)
 385                                 break;
 386                 }
 387         }
 388
 389         return ret;
 390 }
 391
 392 static int
 393 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 394 {
 395         struct hns3_hw *hw = &hns->hw;
 396         bool writen_to_tbl = false;
 397         int ret = 0;
 398
 399         /*
 400          * When vlan filter is enabled, hardware regards packets without vlan
 401          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 402          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 403          */
 404         if (on == 0 && vlan_id == 0)
 405                 return 0;
 406
 407         /*
 408          * When port base vlan enabled, we use port base vlan as the vlan
 409          * filter condition. In this case, we don't update vlan filter table
 410          * when user add new vlan or remove exist vlan, just update the
 411          * vlan list. The vlan id in vlan list will be writen in vlan filter
 412          * table until port base vlan disabled
 413          */
 414         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 415                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 416                 writen_to_tbl = true;
 417         }
 418
 419         if (ret == 0) {
 420                 if (on)
 421                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 422                 else
 423                         hns3_rm_dev_vlan_table(hns, vlan_id);
 424         }
 425         return ret;
 426 }
 427
 428 static int
 429 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 430 {
 431         struct hns3_adapter *hns = dev->data->dev_private;
 432         struct hns3_hw *hw = &hns->hw;
 433         int ret;
 434
 435         rte_spinlock_lock(&hw->lock);
 436         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 437         rte_spinlock_unlock(&hw->lock);
 438         return ret;
 439 }
 440
 441 static int
 442 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 443                          uint16_t tpid)
 444 {
 445         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 446         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 447         struct hns3_hw *hw = &hns->hw;
 448         struct hns3_cmd_desc desc;
 449         int ret;
 450
 451         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 452              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 453                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 454                 return -EINVAL;
 455         }
 456
 457         if (tpid != RTE_ETHER_TYPE_VLAN) {
 458                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 459                 return -EINVAL;
 460         }
 461
 462         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 463         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 464
 465         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 466                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 467                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 468         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 469                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 470                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 471                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 472                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 473         }
 474
 475         ret = hns3_cmd_send(hw, &desc, 1);
 476         if (ret) {
 477                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 478                          ret);
 479                 return ret;
 480         }
 481
 482         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 483
 484         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 485         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 486         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 487
 488         ret = hns3_cmd_send(hw, &desc, 1);
 489         if (ret)
 490                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 491                          ret);
 492         return ret;
 493 }
 494
 495 static int
 496 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 497                    uint16_t tpid)
 498 {
 499         struct hns3_adapter *hns = dev->data->dev_private;
 500         struct hns3_hw *hw = &hns->hw;
 501         int ret;
 502
 503         rte_spinlock_lock(&hw->lock);
 504         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 505         rte_spinlock_unlock(&hw->lock);
 506         return ret;
 507 }
 508
 509 static int
 510 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 511                              struct hns3_rx_vtag_cfg *vcfg)
 512 {
 513         struct hns3_vport_vtag_rx_cfg_cmd *req;
 514         struct hns3_hw *hw = &hns->hw;
 515         struct hns3_cmd_desc desc;
 516         uint16_t vport_id;
 517         uint8_t bitmap;
 518         int ret;
 519
 520         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 521
 522         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 523         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 524                      vcfg->strip_tag1_en ? 1 : 0);
 525         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 526                      vcfg->strip_tag2_en ? 1 : 0);
 527         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 528                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 529         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 530                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 531
 532         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 533         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 534                      vcfg->strip_tag1_discard_en ? 1 : 0);
 535         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 536                      vcfg->strip_tag2_discard_en ? 1 : 0);
 537         /*
 538          * In current version VF is not supported when PF is driven by DPDK
 539          * driver, just need to configure parameters for PF vport.
 540          */
 541         vport_id = HNS3_PF_FUNC_ID;
 542         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 543         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 544         req->vf_bitmap[req->vf_offset] = bitmap;
 545
 546         ret = hns3_cmd_send(hw, &desc, 1);
 547         if (ret)
 548                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 549         return ret;
 550 }
 551
 552 static void
 553 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 554                            struct hns3_rx_vtag_cfg *vcfg)
 555 {
 556         struct hns3_pf *pf = &hns->pf;
 557         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 558 }
 559
 560 static void
 561 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 562                            struct hns3_tx_vtag_cfg *vcfg)
 563 {
 564         struct hns3_pf *pf = &hns->pf;
 565         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 566 }
 567
 568 static int
 569 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 570 {
 571         struct hns3_rx_vtag_cfg rxvlan_cfg;
 572         struct hns3_hw *hw = &hns->hw;
 573         int ret;
 574
 575         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 576                 rxvlan_cfg.strip_tag1_en = false;
 577                 rxvlan_cfg.strip_tag2_en = enable;
 578                 rxvlan_cfg.strip_tag2_discard_en = false;
 579         } else {
 580                 rxvlan_cfg.strip_tag1_en = enable;
 581                 rxvlan_cfg.strip_tag2_en = true;
 582                 rxvlan_cfg.strip_tag2_discard_en = true;
 583         }
 584
 585         rxvlan_cfg.strip_tag1_discard_en = false;
 586         rxvlan_cfg.vlan1_vlan_prionly = false;
 587         rxvlan_cfg.vlan2_vlan_prionly = false;
 588         rxvlan_cfg.rx_vlan_offload_en = enable;
 589
 590         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 591         if (ret) {
 592                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 593                 return ret;
 594         }
 595
 596         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 597
 598         return ret;
 599 }
 600
 601 static int
 602 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 603                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 604 {
 605         struct hns3_vlan_filter_ctrl_cmd *req;
 606         struct hns3_cmd_desc desc;
 607         int ret;
 608
 609         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 610
 611         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 612         req->vlan_type = vlan_type;
 613         req->vlan_fe = filter_en ? fe_type : 0;
 614         req->vf_id = vf_id;
 615
 616         ret = hns3_cmd_send(hw, &desc, 1);
 617         if (ret)
 618                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 619
 620         return ret;
 621 }
 622
 623 static int
 624 hns3_vlan_filter_init(struct hns3_adapter *hns)
 625 {
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 630                                         HNS3_FILTER_FE_EGRESS, false,
 631                                         HNS3_PF_FUNC_ID);
 632         if (ret) {
 633                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 634                 return ret;
 635         }
 636
 637         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 638                                         HNS3_FILTER_FE_INGRESS, false,
 639                                         HNS3_PF_FUNC_ID);
 640         if (ret)
 641                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 642
 643         return ret;
 644 }
 645
 646 static int
 647 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 648 {
 649         struct hns3_hw *hw = &hns->hw;
 650         int ret;
 651
 652         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 653                                         HNS3_FILTER_FE_INGRESS, enable,
 654                                         HNS3_PF_FUNC_ID);
 655         if (ret)
 656                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 657                          enable ? "enable" : "disable", ret);
 658
 659         return ret;
 660 }
 661
 662 static int
 663 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 664 {
 665         struct hns3_adapter *hns = dev->data->dev_private;
 666         struct hns3_hw *hw = &hns->hw;
 667         struct rte_eth_rxmode *rxmode;
 668         unsigned int tmp_mask;
 669         bool enable;
 670         int ret = 0;
 671
 672         rte_spinlock_lock(&hw->lock);
 673         rxmode = &dev->data->dev_conf.rxmode;
 674         tmp_mask = (unsigned int)mask;
 675         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 676                 /* ignore vlan filter configuration during promiscuous mode */
 677                 if (!dev->data->promiscuous) {
 678                         /* Enable or disable VLAN filter */
 679                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 680                                  true : false;
 681
 682                         ret = hns3_enable_vlan_filter(hns, enable);
 683                         if (ret) {
 684                                 rte_spinlock_unlock(&hw->lock);
 685                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 686                                          enable ? "enable" : "disable", ret);
 687                                 return ret;
 688                         }
 689                 }
 690         }
 691
 692         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 693                 /* Enable or disable VLAN stripping */
 694                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 695                     true : false;
 696
 697                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 698                 if (ret) {
 699                         rte_spinlock_unlock(&hw->lock);
 700                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 701                                  enable ? "enable" : "disable", ret);
 702                         return ret;
 703                 }
 704         }
 705
 706         rte_spinlock_unlock(&hw->lock);
 707
 708         return ret;
 709 }
 710
 711 static int
 712 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 713                              struct hns3_tx_vtag_cfg *vcfg)
 714 {
 715         struct hns3_vport_vtag_tx_cfg_cmd *req;
 716         struct hns3_cmd_desc desc;
 717         struct hns3_hw *hw = &hns->hw;
 718         uint16_t vport_id;
 719         uint8_t bitmap;
 720         int ret;
 721
 722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 723
 724         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 725         req->def_vlan_tag1 = vcfg->default_tag1;
 726         req->def_vlan_tag2 = vcfg->default_tag2;
 727         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 728                      vcfg->accept_tag1 ? 1 : 0);
 729         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 730                      vcfg->accept_untag1 ? 1 : 0);
 731         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 732                      vcfg->accept_tag2 ? 1 : 0);
 733         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 734                      vcfg->accept_untag2 ? 1 : 0);
 735         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 736                      vcfg->insert_tag1_en ? 1 : 0);
 737         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 738                      vcfg->insert_tag2_en ? 1 : 0);
 739         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 740
 741         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 742         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 743                      vcfg->tag_shift_mode_en ? 1 : 0);
 744
 745         /*
 746          * In current version VF is not supported when PF is driven by DPDK
 747          * driver, just need to configure parameters for PF vport.
 748          */
 749         vport_id = HNS3_PF_FUNC_ID;
 750         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 751         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 752         req->vf_bitmap[req->vf_offset] = bitmap;
 753
 754         ret = hns3_cmd_send(hw, &desc, 1);
 755         if (ret)
 756                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 757
 758         return ret;
 759 }
 760
 761 static int
 762 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 763                      uint16_t pvid)
 764 {
 765         struct hns3_hw *hw = &hns->hw;
 766         struct hns3_tx_vtag_cfg txvlan_cfg;
 767         int ret;
 768
 769         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 770                 txvlan_cfg.accept_tag1 = true;
 771                 txvlan_cfg.insert_tag1_en = false;
 772                 txvlan_cfg.default_tag1 = 0;
 773         } else {
 774                 txvlan_cfg.accept_tag1 =
 775                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 776                 txvlan_cfg.insert_tag1_en = true;
 777                 txvlan_cfg.default_tag1 = pvid;
 778         }
 779
 780         txvlan_cfg.accept_untag1 = true;
 781         txvlan_cfg.accept_tag2 = true;
 782         txvlan_cfg.accept_untag2 = true;
 783         txvlan_cfg.insert_tag2_en = false;
 784         txvlan_cfg.default_tag2 = 0;
 785         txvlan_cfg.tag_shift_mode_en = true;
 786
 787         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 788         if (ret) {
 789                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 790                          ret);
 791                 return ret;
 792         }
 793
 794         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 795         return ret;
 796 }
 797
 798
 799 static void
 800 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 801 {
 802         struct hns3_user_vlan_table *vlan_entry;
 803         struct hns3_pf *pf = &hns->pf;
 804
 805         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 806                 if (vlan_entry->hd_tbl_status) {
 807                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 808                         vlan_entry->hd_tbl_status = false;
 809                 }
 810         }
 811
 812         if (is_del_list) {
 813                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 814                 while (vlan_entry) {
 815                         LIST_REMOVE(vlan_entry, next);
 816                         rte_free(vlan_entry);
 817                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 818                 }
 819         }
 820 }
 821
 822 static void
 823 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 824 {
 825         struct hns3_user_vlan_table *vlan_entry;
 826         struct hns3_pf *pf = &hns->pf;
 827
 828         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 829                 if (!vlan_entry->hd_tbl_status) {
 830                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 831                         vlan_entry->hd_tbl_status = true;
 832                 }
 833         }
 834 }
 835
 836 static void
 837 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 838 {
 839         struct hns3_hw *hw = &hns->hw;
 840         int ret;
 841
 842         hns3_rm_all_vlan_table(hns, true);
 843         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 844                 ret = hns3_set_port_vlan_filter(hns,
 845                                                 hw->port_base_vlan_cfg.pvid, 0);
 846                 if (ret) {
 847                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 848                                  ret);
 849                         return;
 850                 }
 851         }
 852 }
 853
 854 static int
 855 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 856                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 857 {
 858         struct hns3_hw *hw = &hns->hw;
 859         uint16_t old_pvid;
 860         int ret;
 861
 862         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 863                 old_pvid = hw->port_base_vlan_cfg.pvid;
 864                 if (old_pvid != HNS3_INVALID_PVID) {
 865                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 866                         if (ret) {
 867                                 hns3_err(hw, "failed to remove old pvid %u, "
 868                                                 "ret = %d", old_pvid, ret);
 869                                 return ret;
 870                         }
 871                 }
 872
 873                 hns3_rm_all_vlan_table(hns, false);
 874                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 875                 if (ret) {
 876                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 877                                         new_pvid, ret);
 878                         return ret;
 879                 }
 880         } else {
 881                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 882                 if (ret) {
 883                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 884                                         new_pvid, ret);
 885                         return ret;
 886                 }
 887
 888                 hns3_add_all_vlan_table(hns);
 889         }
 890         return 0;
 891 }
 892
 893 static int
 894 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 895 {
 896         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 897         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 898         bool rx_strip_en;
 899         int ret;
 900
 901         rx_strip_en = old_cfg->rx_vlan_offload_en;
 902         if (on) {
 903                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 904                 rx_vlan_cfg.strip_tag2_en = true;
 905                 rx_vlan_cfg.strip_tag2_discard_en = true;
 906         } else {
 907                 rx_vlan_cfg.strip_tag1_en = false;
 908                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 909                 rx_vlan_cfg.strip_tag2_discard_en = false;
 910         }
 911         rx_vlan_cfg.strip_tag1_discard_en = false;
 912         rx_vlan_cfg.vlan1_vlan_prionly = false;
 913         rx_vlan_cfg.vlan2_vlan_prionly = false;
 914         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 915
 916         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 917         if (ret)
 918                 return ret;
 919
 920         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 921         return ret;
 922 }
 923
 924 static int
 925 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 926 {
 927         struct hns3_hw *hw = &hns->hw;
 928         uint16_t port_base_vlan_state;
 929         int ret;
 930
 931         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 932                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 933                         hns3_warn(hw, "Invalid operation! As current pvid set "
 934                                   "is %u, disable pvid %u is invalid",
 935                                   hw->port_base_vlan_cfg.pvid, pvid);
 936                 return 0;
 937         }
 938
 939         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 940                                     HNS3_PORT_BASE_VLAN_DISABLE;
 941         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 942         if (ret) {
 943                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 944                          ret);
 945                 return ret;
 946         }
 947
 948         ret = hns3_en_pvid_strip(hns, on);
 949         if (ret) {
 950                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 951                          "ret = %d", ret);
 952                 return ret;
 953         }
 954
 955         if (pvid == HNS3_INVALID_PVID)
 956                 goto out;
 957         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
 958         if (ret) {
 959                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
 960                          ret);
 961                 return ret;
 962         }
 963
 964 out:
 965         hw->port_base_vlan_cfg.state = port_base_vlan_state;
 966         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
 967         return ret;
 968 }
 969
 970 static int
 971 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 972 {
 973         struct hns3_adapter *hns = dev->data->dev_private;
 974         struct hns3_hw *hw = &hns->hw;
 975         bool pvid_en_state_change;
 976         uint16_t pvid_state;
 977         int ret;
 978
 979         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 980                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 981                          RTE_ETHER_MAX_VLAN_ID);
 982                 return -EINVAL;
 983         }
 984
 985         /*
 986          * If PVID configuration state change, should refresh the PVID
 987          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
 988          */
 989         pvid_state = hw->port_base_vlan_cfg.state;
 990         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
 991             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
 992                 pvid_en_state_change = false;
 993         else
 994                 pvid_en_state_change = true;
 995
 996         rte_spinlock_lock(&hw->lock);
 997         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 998         rte_spinlock_unlock(&hw->lock);
 999         if (ret)
1000                 return ret;
1001         /*
1002          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1003          * need be processed by PMD driver.
1004          */
1005         if (pvid_en_state_change &&
1006             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1007                 hns3_update_all_queues_pvid_proc_en(hw);
1008
1009         return 0;
1010 }
1011
1012 static int
1013 hns3_default_vlan_config(struct hns3_adapter *hns)
1014 {
1015         struct hns3_hw *hw = &hns->hw;
1016         int ret;
1017
1018         /*
1019          * When vlan filter is enabled, hardware regards packets without vlan
1020          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1021          * table, packets without vlan won't be received. So, add vlan 0 as
1022          * the default vlan.
1023          */
1024         ret = hns3_vlan_filter_configure(hns, 0, 1);
1025         if (ret)
1026                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1027         return ret;
1028 }
1029
1030 static int
1031 hns3_init_vlan_config(struct hns3_adapter *hns)
1032 {
1033         struct hns3_hw *hw = &hns->hw;
1034         int ret;
1035
1036         /*
1037          * This function can be called in the initialization and reset process,
1038          * when in reset process, it means that hardware had been reseted
1039          * successfully and we need to restore the hardware configuration to
1040          * ensure that the hardware configuration remains unchanged before and
1041          * after reset.
1042          */
1043         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1044                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1045                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1046         }
1047
1048         ret = hns3_vlan_filter_init(hns);
1049         if (ret) {
1050                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1051                 return ret;
1052         }
1053
1054         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1055                                        RTE_ETHER_TYPE_VLAN);
1056         if (ret) {
1057                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1058                 return ret;
1059         }
1060
1061         /*
1062          * When in the reinit dev stage of the reset process, the following
1063          * vlan-related configurations may differ from those at initialization,
1064          * we will restore configurations to hardware in hns3_restore_vlan_table
1065          * and hns3_restore_vlan_conf later.
1066          */
1067         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1068                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1069                 if (ret) {
1070                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1071                         return ret;
1072                 }
1073
1074                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1075                 if (ret) {
1076                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1077                                  ret);
1078                         return ret;
1079                 }
1080         }
1081
1082         return hns3_default_vlan_config(hns);
1083 }
1084
1085 static int
1086 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1087 {
1088         struct hns3_pf *pf = &hns->pf;
1089         struct hns3_hw *hw = &hns->hw;
1090         uint64_t offloads;
1091         bool enable;
1092         int ret;
1093
1094         if (!hw->data->promiscuous) {
1095                 /* restore vlan filter states */
1096                 offloads = hw->data->dev_conf.rxmode.offloads;
1097                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1098                 ret = hns3_enable_vlan_filter(hns, enable);
1099                 if (ret) {
1100                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1101                                  "ret = %d", ret);
1102                         return ret;
1103                 }
1104         }
1105
1106         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1107         if (ret) {
1108                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1109                 return ret;
1110         }
1111
1112         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1113         if (ret)
1114                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1115
1116         return ret;
1117 }
1118
1119 static int
1120 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1121 {
1122         struct hns3_adapter *hns = dev->data->dev_private;
1123         struct rte_eth_dev_data *data = dev->data;
1124         struct rte_eth_txmode *txmode;
1125         struct hns3_hw *hw = &hns->hw;
1126         int mask;
1127         int ret;
1128
1129         txmode = &data->dev_conf.txmode;
1130         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1131                 hns3_warn(hw,
1132                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1133                           "configuration is not supported! Ignore these two "
1134                           "parameters: hw_vlan_reject_tagged(%u), "
1135                           "hw_vlan_reject_untagged(%u)",
1136                           txmode->hw_vlan_reject_tagged,
1137                           txmode->hw_vlan_reject_untagged);
1138
1139         /* Apply vlan offload setting */
1140         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1141         ret = hns3_vlan_offload_set(dev, mask);
1142         if (ret) {
1143                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1144                          ret);
1145                 return ret;
1146         }
1147
1148         /*
1149          * If pvid config is not set in rte_eth_conf, driver needn't to set
1150          * VLAN pvid related configuration to hardware.
1151          */
1152         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1153                 return 0;
1154
1155         /* Apply pvid setting */
1156         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1157                                  txmode->hw_vlan_insert_pvid);
1158         if (ret)
1159                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1160                          txmode->pvid, ret);
1161
1162         return ret;
1163 }
1164
1165 static int
1166 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1167                 unsigned int tso_mss_max)
1168 {
1169         struct hns3_cfg_tso_status_cmd *req;
1170         struct hns3_cmd_desc desc;
1171         uint16_t tso_mss;
1172
1173         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1174
1175         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1176
1177         tso_mss = 0;
1178         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1179                        tso_mss_min);
1180         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1181
1182         tso_mss = 0;
1183         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1184                        tso_mss_max);
1185         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1186
1187         return hns3_cmd_send(hw, &desc, 1);
1188 }
1189
1190 static int
1191 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1192                    uint16_t *allocated_size, bool is_alloc)
1193 {
1194         struct hns3_umv_spc_alc_cmd *req;
1195         struct hns3_cmd_desc desc;
1196         int ret;
1197
1198         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1199         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1200         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1201         req->space_size = rte_cpu_to_le_32(space_size);
1202
1203         ret = hns3_cmd_send(hw, &desc, 1);
1204         if (ret) {
1205                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1206                              is_alloc ? "allocate" : "free", ret);
1207                 return ret;
1208         }
1209
1210         if (is_alloc && allocated_size)
1211                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1212
1213         return 0;
1214 }
1215
1216 static int
1217 hns3_init_umv_space(struct hns3_hw *hw)
1218 {
1219         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1220         struct hns3_pf *pf = &hns->pf;
1221         uint16_t allocated_size = 0;
1222         int ret;
1223
1224         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1225                                  true);
1226         if (ret)
1227                 return ret;
1228
1229         if (allocated_size < pf->wanted_umv_size)
1230                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1231                              pf->wanted_umv_size, allocated_size);
1232
1233         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1234                                                 pf->wanted_umv_size;
1235         pf->used_umv_size = 0;
1236         return 0;
1237 }
1238
1239 static int
1240 hns3_uninit_umv_space(struct hns3_hw *hw)
1241 {
1242         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1243         struct hns3_pf *pf = &hns->pf;
1244         int ret;
1245
1246         if (pf->max_umv_size == 0)
1247                 return 0;
1248
1249         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1250         if (ret)
1251                 return ret;
1252
1253         pf->max_umv_size = 0;
1254
1255         return 0;
1256 }
1257
1258 static bool
1259 hns3_is_umv_space_full(struct hns3_hw *hw)
1260 {
1261         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1262         struct hns3_pf *pf = &hns->pf;
1263         bool is_full;
1264
1265         is_full = (pf->used_umv_size >= pf->max_umv_size);
1266
1267         return is_full;
1268 }
1269
1270 static void
1271 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1272 {
1273         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1274         struct hns3_pf *pf = &hns->pf;
1275
1276         if (is_free) {
1277                 if (pf->used_umv_size > 0)
1278                         pf->used_umv_size--;
1279         } else
1280                 pf->used_umv_size++;
1281 }
1282
1283 static void
1284 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1285                       const uint8_t *addr, bool is_mc)
1286 {
1287         const unsigned char *mac_addr = addr;
1288         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1289                             ((uint32_t)mac_addr[2] << 16) |
1290                             ((uint32_t)mac_addr[1] << 8) |
1291                             (uint32_t)mac_addr[0];
1292         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1293
1294         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1295         if (is_mc) {
1296                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1297                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1298                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1299         }
1300
1301         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1302         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1303 }
1304
1305 static int
1306 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1307                              uint8_t resp_code,
1308                              enum hns3_mac_vlan_tbl_opcode op)
1309 {
1310         if (cmdq_resp) {
1311                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1312                          cmdq_resp);
1313                 return -EIO;
1314         }
1315
1316         if (op == HNS3_MAC_VLAN_ADD) {
1317                 if (resp_code == 0 || resp_code == 1) {
1318                         return 0;
1319                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1320                         hns3_err(hw, "add mac addr failed for uc_overflow");
1321                         return -ENOSPC;
1322                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1323                         hns3_err(hw, "add mac addr failed for mc_overflow");
1324                         return -ENOSPC;
1325                 }
1326
1327                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1328                          resp_code);
1329                 return -EIO;
1330         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1331                 if (resp_code == 0) {
1332                         return 0;
1333                 } else if (resp_code == 1) {
1334                         hns3_dbg(hw, "remove mac addr failed for miss");
1335                         return -ENOENT;
1336                 }
1337
1338                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1339                          resp_code);
1340                 return -EIO;
1341         } else if (op == HNS3_MAC_VLAN_LKUP) {
1342                 if (resp_code == 0) {
1343                         return 0;
1344                 } else if (resp_code == 1) {
1345                         hns3_dbg(hw, "lookup mac addr failed for miss");
1346                         return -ENOENT;
1347                 }
1348
1349                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1350                          resp_code);
1351                 return -EIO;
1352         }
1353
1354         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1355                  op);
1356
1357         return -EINVAL;
1358 }
1359
1360 static int
1361 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1362                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1363                          struct hns3_cmd_desc *desc, bool is_mc)
1364 {
1365         uint8_t resp_code;
1366         uint16_t retval;
1367         int ret;
1368
1369         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1370         if (is_mc) {
1371                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1372                 memcpy(desc[0].data, req,
1373                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1374                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1375                                           true);
1376                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1377                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1378                                           true);
1379                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1380         } else {
1381                 memcpy(desc[0].data, req,
1382                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1383                 ret = hns3_cmd_send(hw, desc, 1);
1384         }
1385         if (ret) {
1386                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1387                          ret);
1388                 return ret;
1389         }
1390         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1391         retval = rte_le_to_cpu_16(desc[0].retval);
1392
1393         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1394                                             HNS3_MAC_VLAN_LKUP);
1395 }
1396
1397 static int
1398 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1399                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1400                       struct hns3_cmd_desc *mc_desc)
1401 {
1402         uint8_t resp_code;
1403         uint16_t retval;
1404         int cfg_status;
1405         int ret;
1406
1407         if (mc_desc == NULL) {
1408                 struct hns3_cmd_desc desc;
1409
1410                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1411                 memcpy(desc.data, req,
1412                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1413                 ret = hns3_cmd_send(hw, &desc, 1);
1414                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1415                 retval = rte_le_to_cpu_16(desc.retval);
1416
1417                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1418                                                           HNS3_MAC_VLAN_ADD);
1419         } else {
1420                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1421                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1422                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1423                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1424                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1425                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1426                 memcpy(mc_desc[0].data, req,
1427                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1428                 mc_desc[0].retval = 0;
1429                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1430                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1431                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1432
1433                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1434                                                           HNS3_MAC_VLAN_ADD);
1435         }
1436
1437         if (ret) {
1438                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1439                 return ret;
1440         }
1441
1442         return cfg_status;
1443 }
1444
1445 static int
1446 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1447                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1448 {
1449         struct hns3_cmd_desc desc;
1450         uint8_t resp_code;
1451         uint16_t retval;
1452         int ret;
1453
1454         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1455
1456         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1457
1458         ret = hns3_cmd_send(hw, &desc, 1);
1459         if (ret) {
1460                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1461                 return ret;
1462         }
1463         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1464         retval = rte_le_to_cpu_16(desc.retval);
1465
1466         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1467                                             HNS3_MAC_VLAN_REMOVE);
1468 }
1469
1470 static int
1471 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1472 {
1473         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1474         struct hns3_mac_vlan_tbl_entry_cmd req;
1475         struct hns3_pf *pf = &hns->pf;
1476         struct hns3_cmd_desc desc[3];
1477         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1478         uint16_t egress_port = 0;
1479         uint8_t vf_id;
1480         int ret;
1481
1482         /* check if mac addr is valid */
1483         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1484                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1485                                       mac_addr);
1486                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1487                          mac_str);
1488                 return -EINVAL;
1489         }
1490
1491         memset(&req, 0, sizeof(req));
1492
1493         /*
1494          * In current version VF is not supported when PF is driven by DPDK
1495          * driver, just need to configure parameters for PF vport.
1496          */
1497         vf_id = HNS3_PF_FUNC_ID;
1498         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1499                        HNS3_MAC_EPORT_VFID_S, vf_id);
1500
1501         req.egress_port = rte_cpu_to_le_16(egress_port);
1502
1503         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1504
1505         /*
1506          * Lookup the mac address in the mac_vlan table, and add
1507          * it if the entry is inexistent. Repeated unicast entry
1508          * is not allowed in the mac vlan table.
1509          */
1510         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1511         if (ret == -ENOENT) {
1512                 if (!hns3_is_umv_space_full(hw)) {
1513                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1514                         if (!ret)
1515                                 hns3_update_umv_space(hw, false);
1516                         return ret;
1517                 }
1518
1519                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1520
1521                 return -ENOSPC;
1522         }
1523
1524         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1525
1526         /* check if we just hit the duplicate */
1527         if (ret == 0) {
1528                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1529                 return 0;
1530         }
1531
1532         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1533                  mac_str);
1534
1535         return ret;
1536 }
1537
1538 static int
1539 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1540 {
1541         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1542         struct rte_ether_addr *addr;
1543         int ret;
1544         int i;
1545
1546         for (i = 0; i < hw->mc_addrs_num; i++) {
1547                 addr = &hw->mc_addrs[i];
1548                 /* Check if there are duplicate addresses */
1549                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1550                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1551                                               addr);
1552                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1553                                  "(%s) is added by the set_mc_mac_addr_list "
1554                                  "API", mac_str);
1555                         return -EINVAL;
1556                 }
1557         }
1558
1559         ret = hns3_add_mc_addr(hw, mac_addr);
1560         if (ret) {
1561                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562                                       mac_addr);
1563                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1564                          mac_str, ret);
1565         }
1566         return ret;
1567 }
1568
1569 static int
1570 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1571 {
1572         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1573         int ret;
1574
1575         ret = hns3_remove_mc_addr(hw, mac_addr);
1576         if (ret) {
1577                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1578                                       mac_addr);
1579                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1580                          mac_str, ret);
1581         }
1582         return ret;
1583 }
1584
1585 static int
1586 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1587                   uint32_t idx, __rte_unused uint32_t pool)
1588 {
1589         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1591         int ret;
1592
1593         rte_spinlock_lock(&hw->lock);
1594
1595         /*
1596          * In hns3 network engine adding UC and MC mac address with different
1597          * commands with firmware. We need to determine whether the input
1598          * address is a UC or a MC address to call different commands.
1599          * By the way, it is recommended calling the API function named
1600          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1601          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1602          * may affect the specifications of UC mac addresses.
1603          */
1604         if (rte_is_multicast_ether_addr(mac_addr))
1605                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1606         else
1607                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1608
1609         if (ret) {
1610                 rte_spinlock_unlock(&hw->lock);
1611                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1612                                       mac_addr);
1613                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1614                          ret);
1615                 return ret;
1616         }
1617
1618         if (idx == 0)
1619                 hw->mac.default_addr_setted = true;
1620         rte_spinlock_unlock(&hw->lock);
1621
1622         return ret;
1623 }
1624
1625 static int
1626 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1627 {
1628         struct hns3_mac_vlan_tbl_entry_cmd req;
1629         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1630         int ret;
1631
1632         /* check if mac addr is valid */
1633         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1634                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635                                       mac_addr);
1636                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1637                          mac_str);
1638                 return -EINVAL;
1639         }
1640
1641         memset(&req, 0, sizeof(req));
1642         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1643         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1644         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1645         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1646                 return 0;
1647         else if (ret == 0)
1648                 hns3_update_umv_space(hw, true);
1649
1650         return ret;
1651 }
1652
1653 static void
1654 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1655 {
1656         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         /* index will be checked by upper level rte interface */
1658         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         int ret;
1661
1662         rte_spinlock_lock(&hw->lock);
1663
1664         if (rte_is_multicast_ether_addr(mac_addr))
1665                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1666         else
1667                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1668         rte_spinlock_unlock(&hw->lock);
1669         if (ret) {
1670                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1671                                       mac_addr);
1672                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1673                          ret);
1674         }
1675 }
1676
1677 static int
1678 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1679                           struct rte_ether_addr *mac_addr)
1680 {
1681         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682         struct rte_ether_addr *oaddr;
1683         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1684         bool default_addr_setted;
1685         bool rm_succes = false;
1686         int ret, ret_val;
1687
1688         /*
1689          * It has been guaranteed that input parameter named mac_addr is valid
1690          * address in the rte layer of DPDK framework.
1691          */
1692         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1693         default_addr_setted = hw->mac.default_addr_setted;
1694         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1695                 return 0;
1696
1697         rte_spinlock_lock(&hw->lock);
1698         if (default_addr_setted) {
1699                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1700                 if (ret) {
1701                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1702                                               oaddr);
1703                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1704                                   mac_str, ret);
1705                         rm_succes = false;
1706                 } else
1707                         rm_succes = true;
1708         }
1709
1710         ret = hns3_add_uc_addr_common(hw, mac_addr);
1711         if (ret) {
1712                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1713                                       mac_addr);
1714                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1715                 goto err_add_uc_addr;
1716         }
1717
1718         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1719         if (ret) {
1720                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1721                 goto err_pause_addr_cfg;
1722         }
1723
1724         rte_ether_addr_copy(mac_addr,
1725                             (struct rte_ether_addr *)hw->mac.mac_addr);
1726         hw->mac.default_addr_setted = true;
1727         rte_spinlock_unlock(&hw->lock);
1728
1729         return 0;
1730
1731 err_pause_addr_cfg:
1732         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1733         if (ret_val) {
1734                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1735                                       mac_addr);
1736                 hns3_warn(hw,
1737                           "Failed to roll back to del setted mac addr(%s): %d",
1738                           mac_str, ret_val);
1739         }
1740
1741 err_add_uc_addr:
1742         if (rm_succes) {
1743                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1744                 if (ret_val) {
1745                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1746                                               oaddr);
1747                         hns3_warn(hw,
1748                                   "Failed to restore old uc mac addr(%s): %d",
1749                                   mac_str, ret_val);
1750                         hw->mac.default_addr_setted = false;
1751                 }
1752         }
1753         rte_spinlock_unlock(&hw->lock);
1754
1755         return ret;
1756 }
1757
1758 static int
1759 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1760 {
1761         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1762         struct hns3_hw *hw = &hns->hw;
1763         struct rte_ether_addr *addr;
1764         int err = 0;
1765         int ret;
1766         int i;
1767
1768         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1769                 addr = &hw->data->mac_addrs[i];
1770                 if (rte_is_zero_ether_addr(addr))
1771                         continue;
1772                 if (rte_is_multicast_ether_addr(addr))
1773                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1774                               hns3_add_mc_addr(hw, addr);
1775                 else
1776                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1777                               hns3_add_uc_addr_common(hw, addr);
1778
1779                 if (ret) {
1780                         err = ret;
1781                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                               addr);
1783                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1784                                  "ret = %d.", del ? "remove" : "restore",
1785                                  mac_str, i, ret);
1786                 }
1787         }
1788         return err;
1789 }
1790
1791 static void
1792 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1793 {
1794 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1795         uint8_t word_num;
1796         uint8_t bit_num;
1797
1798         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1799                 word_num = vfid / 32;
1800                 bit_num = vfid % 32;
1801                 if (clr)
1802                         desc[1].data[word_num] &=
1803                             rte_cpu_to_le_32(~(1UL << bit_num));
1804                 else
1805                         desc[1].data[word_num] |=
1806                             rte_cpu_to_le_32(1UL << bit_num);
1807         } else {
1808                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1809                 bit_num = vfid % 32;
1810                 if (clr)
1811                         desc[2].data[word_num] &=
1812                             rte_cpu_to_le_32(~(1UL << bit_num));
1813                 else
1814                         desc[2].data[word_num] |=
1815                             rte_cpu_to_le_32(1UL << bit_num);
1816         }
1817 }
1818
1819 static int
1820 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1821 {
1822         struct hns3_mac_vlan_tbl_entry_cmd req;
1823         struct hns3_cmd_desc desc[3];
1824         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1825         uint8_t vf_id;
1826         int ret;
1827
1828         /* Check if mac addr is valid */
1829         if (!rte_is_multicast_ether_addr(mac_addr)) {
1830                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1831                                       mac_addr);
1832                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1833                          mac_str);
1834                 return -EINVAL;
1835         }
1836
1837         memset(&req, 0, sizeof(req));
1838         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1839         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1840         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1841         if (ret) {
1842                 /* This mac addr do not exist, add new entry for it */
1843                 memset(desc[0].data, 0, sizeof(desc[0].data));
1844                 memset(desc[1].data, 0, sizeof(desc[0].data));
1845                 memset(desc[2].data, 0, sizeof(desc[0].data));
1846         }
1847
1848         /*
1849          * In current version VF is not supported when PF is driven by DPDK
1850          * driver, just need to configure parameters for PF vport.
1851          */
1852         vf_id = HNS3_PF_FUNC_ID;
1853         hns3_update_desc_vfid(desc, vf_id, false);
1854         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1855         if (ret) {
1856                 if (ret == -ENOSPC)
1857                         hns3_err(hw, "mc mac vlan table is full");
1858                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1859                                       mac_addr);
1860                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1861         }
1862
1863         return ret;
1864 }
1865
1866 static int
1867 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1868 {
1869         struct hns3_mac_vlan_tbl_entry_cmd req;
1870         struct hns3_cmd_desc desc[3];
1871         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1872         uint8_t vf_id;
1873         int ret;
1874
1875         /* Check if mac addr is valid */
1876         if (!rte_is_multicast_ether_addr(mac_addr)) {
1877                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1878                                       mac_addr);
1879                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1880                          mac_str);
1881                 return -EINVAL;
1882         }
1883
1884         memset(&req, 0, sizeof(req));
1885         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1886         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1887         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1888         if (ret == 0) {
1889                 /*
1890                  * This mac addr exist, remove this handle's VFID for it.
1891                  * In current version VF is not supported when PF is driven by
1892                  * DPDK driver, just need to configure parameters for PF vport.
1893                  */
1894                 vf_id = HNS3_PF_FUNC_ID;
1895                 hns3_update_desc_vfid(desc, vf_id, true);
1896
1897                 /* All the vfid is zero, so need to delete this entry */
1898                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1899         } else if (ret == -ENOENT) {
1900                 /* This mac addr doesn't exist. */
1901                 return 0;
1902         }
1903
1904         if (ret) {
1905                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1906                                       mac_addr);
1907                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1908         }
1909
1910         return ret;
1911 }
1912
1913 static int
1914 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1915                            struct rte_ether_addr *mc_addr_set,
1916                            uint32_t nb_mc_addr)
1917 {
1918         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1919         struct rte_ether_addr *addr;
1920         uint32_t i;
1921         uint32_t j;
1922
1923         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1924                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1925                          "invalid. valid range: 0~%d",
1926                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1927                 return -EINVAL;
1928         }
1929
1930         /* Check if input mac addresses are valid */
1931         for (i = 0; i < nb_mc_addr; i++) {
1932                 addr = &mc_addr_set[i];
1933                 if (!rte_is_multicast_ether_addr(addr)) {
1934                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1935                                               addr);
1936                         hns3_err(hw,
1937                                  "failed to set mc mac addr, addr(%s) invalid.",
1938                                  mac_str);
1939                         return -EINVAL;
1940                 }
1941
1942                 /* Check if there are duplicate addresses */
1943                 for (j = i + 1; j < nb_mc_addr; j++) {
1944                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1945                                 hns3_ether_format_addr(mac_str,
1946                                                       RTE_ETHER_ADDR_FMT_SIZE,
1947                                                       addr);
1948                                 hns3_err(hw, "failed to set mc mac addr, "
1949                                          "addrs invalid. two same addrs(%s).",
1950                                          mac_str);
1951                                 return -EINVAL;
1952                         }
1953                 }
1954
1955                 /*
1956                  * Check if there are duplicate addresses between mac_addrs
1957                  * and mc_addr_set
1958                  */
1959                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1960                         if (rte_is_same_ether_addr(addr,
1961                                                    &hw->data->mac_addrs[j])) {
1962                                 hns3_ether_format_addr(mac_str,
1963                                                       RTE_ETHER_ADDR_FMT_SIZE,
1964                                                       addr);
1965                                 hns3_err(hw, "failed to set mc mac addr, "
1966                                          "addrs invalid. addrs(%s) has already "
1967                                          "configured in mac_addr add API",
1968                                          mac_str);
1969                                 return -EINVAL;
1970                         }
1971                 }
1972         }
1973
1974         return 0;
1975 }
1976
1977 static void
1978 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1979                            struct rte_ether_addr *mc_addr_set,
1980                            int mc_addr_num,
1981                            struct rte_ether_addr *reserved_addr_list,
1982                            int *reserved_addr_num,
1983                            struct rte_ether_addr *add_addr_list,
1984                            int *add_addr_num,
1985                            struct rte_ether_addr *rm_addr_list,
1986                            int *rm_addr_num)
1987 {
1988         struct rte_ether_addr *addr;
1989         int current_addr_num;
1990         int reserved_num = 0;
1991         int add_num = 0;
1992         int rm_num = 0;
1993         int num;
1994         int i;
1995         int j;
1996         bool same_addr;
1997
1998         /* Calculate the mc mac address list that should be removed */
1999         current_addr_num = hw->mc_addrs_num;
2000         for (i = 0; i < current_addr_num; i++) {
2001                 addr = &hw->mc_addrs[i];
2002                 same_addr = false;
2003                 for (j = 0; j < mc_addr_num; j++) {
2004                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2005                                 same_addr = true;
2006                                 break;
2007                         }
2008                 }
2009
2010                 if (!same_addr) {
2011                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2012                         rm_num++;
2013                 } else {
2014                         rte_ether_addr_copy(addr,
2015                                             &reserved_addr_list[reserved_num]);
2016                         reserved_num++;
2017                 }
2018         }
2019
2020         /* Calculate the mc mac address list that should be added */
2021         for (i = 0; i < mc_addr_num; i++) {
2022                 addr = &mc_addr_set[i];
2023                 same_addr = false;
2024                 for (j = 0; j < current_addr_num; j++) {
2025                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2026                                 same_addr = true;
2027                                 break;
2028                         }
2029                 }
2030
2031                 if (!same_addr) {
2032                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2033                         add_num++;
2034                 }
2035         }
2036
2037         /* Reorder the mc mac address list maintained by driver */
2038         for (i = 0; i < reserved_num; i++)
2039                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2040
2041         for (i = 0; i < rm_num; i++) {
2042                 num = reserved_num + i;
2043                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2044         }
2045
2046         *reserved_addr_num = reserved_num;
2047         *add_addr_num = add_num;
2048         *rm_addr_num = rm_num;
2049 }
2050
2051 static int
2052 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2053                           struct rte_ether_addr *mc_addr_set,
2054                           uint32_t nb_mc_addr)
2055 {
2056         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2058         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2059         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2060         struct rte_ether_addr *addr;
2061         int reserved_addr_num;
2062         int add_addr_num;
2063         int rm_addr_num;
2064         int mc_addr_num;
2065         int num;
2066         int ret;
2067         int i;
2068
2069         /* Check if input parameters are valid */
2070         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2071         if (ret)
2072                 return ret;
2073
2074         rte_spinlock_lock(&hw->lock);
2075
2076         /*
2077          * Calculate the mc mac address lists those should be removed and be
2078          * added, Reorder the mc mac address list maintained by driver.
2079          */
2080         mc_addr_num = (int)nb_mc_addr;
2081         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2082                                    reserved_addr_list, &reserved_addr_num,
2083                                    add_addr_list, &add_addr_num,
2084                                    rm_addr_list, &rm_addr_num);
2085
2086         /* Remove mc mac addresses */
2087         for (i = 0; i < rm_addr_num; i++) {
2088                 num = rm_addr_num - i - 1;
2089                 addr = &rm_addr_list[num];
2090                 ret = hns3_remove_mc_addr(hw, addr);
2091                 if (ret) {
2092                         rte_spinlock_unlock(&hw->lock);
2093                         return ret;
2094                 }
2095                 hw->mc_addrs_num--;
2096         }
2097
2098         /* Add mc mac addresses */
2099         for (i = 0; i < add_addr_num; i++) {
2100                 addr = &add_addr_list[i];
2101                 ret = hns3_add_mc_addr(hw, addr);
2102                 if (ret) {
2103                         rte_spinlock_unlock(&hw->lock);
2104                         return ret;
2105                 }
2106
2107                 num = reserved_addr_num + i;
2108                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2109                 hw->mc_addrs_num++;
2110         }
2111         rte_spinlock_unlock(&hw->lock);
2112
2113         return 0;
2114 }
2115
2116 static int
2117 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2118 {
2119         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2120         struct hns3_hw *hw = &hns->hw;
2121         struct rte_ether_addr *addr;
2122         int err = 0;
2123         int ret;
2124         int i;
2125
2126         for (i = 0; i < hw->mc_addrs_num; i++) {
2127                 addr = &hw->mc_addrs[i];
2128                 if (!rte_is_multicast_ether_addr(addr))
2129                         continue;
2130                 if (del)
2131                         ret = hns3_remove_mc_addr(hw, addr);
2132                 else
2133                         ret = hns3_add_mc_addr(hw, addr);
2134                 if (ret) {
2135                         err = ret;
2136                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2137                                               addr);
2138                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2139                                  del ? "Remove" : "Restore", mac_str, ret);
2140                 }
2141         }
2142         return err;
2143 }
2144
2145 static int
2146 hns3_check_mq_mode(struct rte_eth_dev *dev)
2147 {
2148         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2149         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2150         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2153         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2154         uint8_t num_tc;
2155         int max_tc = 0;
2156         int i;
2157
2158         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2159         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2160
2161         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2162                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2163                          "rx_mq_mode = %d", rx_mq_mode);
2164                 return -EINVAL;
2165         }
2166
2167         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2168             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2169                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2170                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2171                          rx_mq_mode, tx_mq_mode);
2172                 return -EINVAL;
2173         }
2174
2175         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2176                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2177                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2178                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2179                         return -EINVAL;
2180                 }
2181
2182                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2183                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2184                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2185                                  "nb_tcs(%d) != %d or %d in rx direction.",
2186                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2187                         return -EINVAL;
2188                 }
2189
2190                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2191                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2192                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2193                         return -EINVAL;
2194                 }
2195
2196                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2197                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2198                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2199                                          "is not equal to one in tx direction.",
2200                                          i, dcb_rx_conf->dcb_tc[i]);
2201                                 return -EINVAL;
2202                         }
2203                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2204                                 max_tc = dcb_rx_conf->dcb_tc[i];
2205                 }
2206
2207                 num_tc = max_tc + 1;
2208                 if (num_tc > dcb_rx_conf->nb_tcs) {
2209                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2210                                  num_tc, dcb_rx_conf->nb_tcs);
2211                         return -EINVAL;
2212                 }
2213         }
2214
2215         return 0;
2216 }
2217
2218 static int
2219 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2220 {
2221         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222
2223         if (!hns3_dev_dcb_supported(hw)) {
2224                 hns3_err(hw, "this port does not support dcb configurations.");
2225                 return -EOPNOTSUPP;
2226         }
2227
2228         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2229                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2230                 return -EOPNOTSUPP;
2231         }
2232
2233         /* Check multiple queue mode */
2234         return hns3_check_mq_mode(dev);
2235 }
2236
2237 static int
2238 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2239                            enum hns3_ring_type queue_type, uint16_t queue_id)
2240 {
2241         struct hns3_cmd_desc desc;
2242         struct hns3_ctrl_vector_chain_cmd *req =
2243                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2244         enum hns3_cmd_status status;
2245         enum hns3_opcode_type op;
2246         uint16_t tqp_type_and_id = 0;
2247         uint16_t type;
2248         uint16_t gl;
2249
2250         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2251         hns3_cmd_setup_basic_desc(&desc, op, false);
2252         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2253                                               HNS3_TQP_INT_ID_L_S);
2254         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2255                                               HNS3_TQP_INT_ID_H_S);
2256
2257         if (queue_type == HNS3_RING_TYPE_RX)
2258                 gl = HNS3_RING_GL_RX;
2259         else
2260                 gl = HNS3_RING_GL_TX;
2261
2262         type = queue_type;
2263
2264         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2265                        type);
2266         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2267         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2268                        gl);
2269         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2270         req->int_cause_num = 1;
2271         status = hns3_cmd_send(hw, &desc, 1);
2272         if (status) {
2273                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, status is %d.",
2274                          en ? "Map" : "Unmap", queue_id, vector_id, status);
2275                 return status;
2276         }
2277
2278         return 0;
2279 }
2280
2281 static int
2282 hns3_init_ring_with_vector(struct hns3_hw *hw)
2283 {
2284         uint16_t vec;
2285         int ret;
2286         int i;
2287
2288         /*
2289          * In hns3 network engine, vector 0 is always the misc interrupt of this
2290          * function, vector 1~N can be used respectively for the queues of the
2291          * function. Tx and Rx queues with the same number share the interrupt
2292          * vector. In the initialization clearing the all hardware mapping
2293          * relationship configurations between queues and interrupt vectors is
2294          * needed, so some error caused by the residual configurations, such as
2295          * the unexpected Tx interrupt, can be avoid.
2296          */
2297         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2298         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2299                 vec = vec - 1; /* the last interrupt is reserved */
2300         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2301         for (i = 0; i < hw->intr_tqps_num; i++) {
2302                 /*
2303                  * Set gap limiter/rate limiter/quanity limiter algorithm
2304                  * configuration for interrupt coalesce of queue's interrupt.
2305                  */
2306                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2307                                        HNS3_TQP_INTR_GL_DEFAULT);
2308                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2309                                        HNS3_TQP_INTR_GL_DEFAULT);
2310                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2311                 /*
2312                  * QL(quantity limiter) is not used currently, just set 0 to
2313                  * close it.
2314                  */
2315                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2316
2317                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2318                                                  HNS3_RING_TYPE_TX, i);
2319                 if (ret) {
2320                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2321                                           "vector: %u, ret=%d", i, vec, ret);
2322                         return ret;
2323                 }
2324
2325                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2326                                                  HNS3_RING_TYPE_RX, i);
2327                 if (ret) {
2328                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2329                                           "vector: %u, ret=%d", i, vec, ret);
2330                         return ret;
2331                 }
2332         }
2333
2334         return 0;
2335 }
2336
2337 static int
2338 hns3_dev_configure(struct rte_eth_dev *dev)
2339 {
2340         struct hns3_adapter *hns = dev->data->dev_private;
2341         struct rte_eth_conf *conf = &dev->data->dev_conf;
2342         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2343         struct hns3_hw *hw = &hns->hw;
2344         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2345         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2346         struct rte_eth_rss_conf rss_conf;
2347         uint32_t max_rx_pkt_len;
2348         uint16_t mtu;
2349         bool gro_en;
2350         int ret;
2351
2352         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2353
2354         /*
2355          * Some versions of hardware network engine does not support
2356          * individually enable/disable/reset the Tx or Rx queue. These devices
2357          * must enable/disable/reset Tx and Rx queues at the same time. When the
2358          * numbers of Tx queues allocated by upper applications are not equal to
2359          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2360          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2361          * work as usual. But these fake queues are imperceptible, and can not
2362          * be used by upper applications.
2363          */
2364         if (!hns3_dev_indep_txrx_supported(hw)) {
2365                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2366                 if (ret) {
2367                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2368                                  ret);
2369                         return ret;
2370                 }
2371         }
2372
2373         hw->adapter_state = HNS3_NIC_CONFIGURING;
2374         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2375                 hns3_err(hw, "setting link speed/duplex not supported");
2376                 ret = -EINVAL;
2377                 goto cfg_err;
2378         }
2379
2380         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2381                 ret = hns3_check_dcb_cfg(dev);
2382                 if (ret)
2383                         goto cfg_err;
2384         }
2385
2386         /* When RSS is not configured, redirect the packet queue 0 */
2387         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2388                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2389                 rss_conf = conf->rx_adv_conf.rss_conf;
2390                 hw->rss_dis_flag = false;
2391                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2392                 if (ret)
2393                         goto cfg_err;
2394         }
2395
2396         /*
2397          * If jumbo frames are enabled, MTU needs to be refreshed
2398          * according to the maximum RX packet length.
2399          */
2400         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2401                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2402                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2403                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2404                         hns3_err(hw, "maximum Rx packet length must be greater "
2405                                  "than %u and less than %u when jumbo frame enabled.",
2406                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2407                                  (uint16_t)HNS3_MAX_FRAME_LEN);
2408                         ret = -EINVAL;
2409                         goto cfg_err;
2410                 }
2411
2412                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2413                 ret = hns3_dev_mtu_set(dev, mtu);
2414                 if (ret)
2415                         goto cfg_err;
2416                 dev->data->mtu = mtu;
2417         }
2418
2419         ret = hns3_dev_configure_vlan(dev);
2420         if (ret)
2421                 goto cfg_err;
2422
2423         /* config hardware GRO */
2424         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2425         ret = hns3_config_gro(hw, gro_en);
2426         if (ret)
2427                 goto cfg_err;
2428
2429         hns->rx_simple_allowed = true;
2430         hns->rx_vec_allowed = true;
2431         hns->tx_simple_allowed = true;
2432         hns->tx_vec_allowed = true;
2433
2434         hns3_init_rx_ptype_tble(dev);
2435         hw->adapter_state = HNS3_NIC_CONFIGURED;
2436
2437         return 0;
2438
2439 cfg_err:
2440         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2441         hw->adapter_state = HNS3_NIC_INITIALIZED;
2442
2443         return ret;
2444 }
2445
2446 static int
2447 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2448 {
2449         struct hns3_config_max_frm_size_cmd *req;
2450         struct hns3_cmd_desc desc;
2451
2452         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2453
2454         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2455         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2456         req->min_frm_size = RTE_ETHER_MIN_LEN;
2457
2458         return hns3_cmd_send(hw, &desc, 1);
2459 }
2460
2461 static int
2462 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2463 {
2464         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2465         uint16_t original_mps = hns->pf.mps;
2466         int err;
2467         int ret;
2468
2469         ret = hns3_set_mac_mtu(hw, mps);
2470         if (ret) {
2471                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2472                 return ret;
2473         }
2474
2475         hns->pf.mps = mps;
2476         ret = hns3_buffer_alloc(hw);
2477         if (ret) {
2478                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2479                 goto rollback;
2480         }
2481
2482         return 0;
2483
2484 rollback:
2485         err = hns3_set_mac_mtu(hw, original_mps);
2486         if (err) {
2487                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2488                 return ret;
2489         }
2490         hns->pf.mps = original_mps;
2491
2492         return ret;
2493 }
2494
2495 static int
2496 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2497 {
2498         struct hns3_adapter *hns = dev->data->dev_private;
2499         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2500         struct hns3_hw *hw = &hns->hw;
2501         bool is_jumbo_frame;
2502         int ret;
2503
2504         if (dev->data->dev_started) {
2505                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2506                          "before configuration", dev->data->port_id);
2507                 return -EBUSY;
2508         }
2509
2510         rte_spinlock_lock(&hw->lock);
2511         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2512         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2513
2514         /*
2515          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2516          * assign to "uint16_t" type variable.
2517          */
2518         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2519         if (ret) {
2520                 rte_spinlock_unlock(&hw->lock);
2521                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2522                          dev->data->port_id, mtu, ret);
2523                 return ret;
2524         }
2525
2526         if (is_jumbo_frame)
2527                 dev->data->dev_conf.rxmode.offloads |=
2528                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2529         else
2530                 dev->data->dev_conf.rxmode.offloads &=
2531                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2532         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2533         rte_spinlock_unlock(&hw->lock);
2534
2535         return 0;
2536 }
2537
2538 int
2539 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2540 {
2541         struct hns3_adapter *hns = eth_dev->data->dev_private;
2542         struct hns3_hw *hw = &hns->hw;
2543         uint16_t queue_num = hw->tqps_num;
2544
2545         /*
2546          * In interrupt mode, 'max_rx_queues' is set based on the number of
2547          * MSI-X interrupt resources of the hardware.
2548          */
2549         if (hw->data->dev_conf.intr_conf.rxq == 1)
2550                 queue_num = hw->intr_tqps_num;
2551
2552         info->max_rx_queues = queue_num;
2553         info->max_tx_queues = hw->tqps_num;
2554         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2555         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2556         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2557         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2558         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2559         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2560                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2561                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2562                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2563                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2564                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2565                                  DEV_RX_OFFLOAD_KEEP_CRC |
2566                                  DEV_RX_OFFLOAD_SCATTER |
2567                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2568                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2569                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2570                                  DEV_RX_OFFLOAD_RSS_HASH |
2571                                  DEV_RX_OFFLOAD_TCP_LRO);
2572         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2573                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2574                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2575                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2576                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2577                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2578                                  DEV_TX_OFFLOAD_TCP_TSO |
2579                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2580                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2581                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2582                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2583                                  hns3_txvlan_cap_get(hw));
2584
2585         if (hns3_dev_indep_txrx_supported(hw))
2586                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2587                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2588
2589         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2590                 .nb_max = HNS3_MAX_RING_DESC,
2591                 .nb_min = HNS3_MIN_RING_DESC,
2592                 .nb_align = HNS3_ALIGN_RING_DESC,
2593         };
2594
2595         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2596                 .nb_max = HNS3_MAX_RING_DESC,
2597                 .nb_min = HNS3_MIN_RING_DESC,
2598                 .nb_align = HNS3_ALIGN_RING_DESC,
2599                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2600                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2601         };
2602
2603         info->default_rxconf = (struct rte_eth_rxconf) {
2604                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2605                 /*
2606                  * If there are no available Rx buffer descriptors, incoming
2607                  * packets are always dropped by hardware based on hns3 network
2608                  * engine.
2609                  */
2610                 .rx_drop_en = 1,
2611                 .offloads = 0,
2612         };
2613         info->default_txconf = (struct rte_eth_txconf) {
2614                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2615                 .offloads = 0,
2616         };
2617
2618         info->vmdq_queue_num = 0;
2619
2620         info->reta_size = hw->rss_ind_tbl_size;
2621         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2622         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2623
2624         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2625         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2626         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2627         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2628         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2629         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2630
2631         return 0;
2632 }
2633
2634 static int
2635 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2636                     size_t fw_size)
2637 {
2638         struct hns3_adapter *hns = eth_dev->data->dev_private;
2639         struct hns3_hw *hw = &hns->hw;
2640         uint32_t version = hw->fw_version;
2641         int ret;
2642
2643         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2644                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2645                                       HNS3_FW_VERSION_BYTE3_S),
2646                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2647                                       HNS3_FW_VERSION_BYTE2_S),
2648                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2649                                       HNS3_FW_VERSION_BYTE1_S),
2650                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2651                                       HNS3_FW_VERSION_BYTE0_S));
2652         ret += 1; /* add the size of '\0' */
2653         if (fw_size < (uint32_t)ret)
2654                 return ret;
2655         else
2656                 return 0;
2657 }
2658
2659 static int
2660 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2661                      __rte_unused int wait_to_complete)
2662 {
2663         struct hns3_adapter *hns = eth_dev->data->dev_private;
2664         struct hns3_hw *hw = &hns->hw;
2665         struct hns3_mac *mac = &hw->mac;
2666         struct rte_eth_link new_link;
2667
2668         if (!hns3_is_reset_pending(hns)) {
2669                 hns3_update_link_status(hw);
2670                 hns3_update_link_info(eth_dev);
2671         }
2672
2673         memset(&new_link, 0, sizeof(new_link));
2674         switch (mac->link_speed) {
2675         case ETH_SPEED_NUM_10M:
2676         case ETH_SPEED_NUM_100M:
2677         case ETH_SPEED_NUM_1G:
2678         case ETH_SPEED_NUM_10G:
2679         case ETH_SPEED_NUM_25G:
2680         case ETH_SPEED_NUM_40G:
2681         case ETH_SPEED_NUM_50G:
2682         case ETH_SPEED_NUM_100G:
2683         case ETH_SPEED_NUM_200G:
2684                 new_link.link_speed = mac->link_speed;
2685                 break;
2686         default:
2687                 new_link.link_speed = ETH_SPEED_NUM_100M;
2688                 break;
2689         }
2690
2691         new_link.link_duplex = mac->link_duplex;
2692         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2693         new_link.link_autoneg =
2694             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2695
2696         return rte_eth_linkstatus_set(eth_dev, &new_link);
2697 }
2698
2699 static int
2700 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2701 {
2702         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2703         struct hns3_pf *pf = &hns->pf;
2704
2705         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2706                 return -EINVAL;
2707
2708         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2709
2710         return 0;
2711 }
2712
2713 static int
2714 hns3_query_function_status(struct hns3_hw *hw)
2715 {
2716 #define HNS3_QUERY_MAX_CNT              10
2717 #define HNS3_QUERY_SLEEP_MSCOEND        1
2718         struct hns3_func_status_cmd *req;
2719         struct hns3_cmd_desc desc;
2720         int timeout = 0;
2721         int ret;
2722
2723         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2724         req = (struct hns3_func_status_cmd *)desc.data;
2725
2726         do {
2727                 ret = hns3_cmd_send(hw, &desc, 1);
2728                 if (ret) {
2729                         PMD_INIT_LOG(ERR, "query function status failed %d",
2730                                      ret);
2731                         return ret;
2732                 }
2733
2734                 /* Check pf reset is done */
2735                 if (req->pf_state)
2736                         break;
2737
2738                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2739         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2740
2741         return hns3_parse_func_status(hw, req);
2742 }
2743
2744 static int
2745 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2746 {
2747         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2748         struct hns3_pf *pf = &hns->pf;
2749
2750         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2751                 /*
2752                  * The total_tqps_num obtained from firmware is maximum tqp
2753                  * numbers of this port, which should be used for PF and VFs.
2754                  * There is no need for pf to have so many tqp numbers in
2755                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2756                  * coming from config file, is assigned to maximum queue number
2757                  * for the PF of this port by user. So users can modify the
2758                  * maximum queue number of PF according to their own application
2759                  * scenarios, which is more flexible to use. In addition, many
2760                  * memories can be saved due to allocating queue statistics
2761                  * room according to the actual number of queues required. The
2762                  * maximum queue number of PF for network engine with
2763                  * revision_id greater than 0x30 is assigned by config file.
2764                  */
2765                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2766                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2767                                  "must be greater than 0.",
2768                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2769                         return -EINVAL;
2770                 }
2771
2772                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2773                                        hw->total_tqps_num);
2774         } else {
2775                 /*
2776                  * Due to the limitation on the number of PF interrupts
2777                  * available, the maximum queue number assigned to PF on
2778                  * the network engine with revision_id 0x21 is 64.
2779                  */
2780                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2781                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2782         }
2783
2784         return 0;
2785 }
2786
2787 static int
2788 hns3_query_pf_resource(struct hns3_hw *hw)
2789 {
2790         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2791         struct hns3_pf *pf = &hns->pf;
2792         struct hns3_pf_res_cmd *req;
2793         struct hns3_cmd_desc desc;
2794         int ret;
2795
2796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2797         ret = hns3_cmd_send(hw, &desc, 1);
2798         if (ret) {
2799                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2800                 return ret;
2801         }
2802
2803         req = (struct hns3_pf_res_cmd *)desc.data;
2804         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2805                              rte_le_to_cpu_16(req->ext_tqp_num);
2806         ret = hns3_get_pf_max_tqp_num(hw);
2807         if (ret)
2808                 return ret;
2809
2810         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2811         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2812
2813         if (req->tx_buf_size)
2814                 pf->tx_buf_size =
2815                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2816         else
2817                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2818
2819         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2820
2821         if (req->dv_buf_size)
2822                 pf->dv_buf_size =
2823                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2824         else
2825                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2826
2827         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2828
2829         hw->num_msi =
2830                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2831                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2832
2833         return 0;
2834 }
2835
2836 static void
2837 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2838 {
2839         struct hns3_cfg_param_cmd *req;
2840         uint64_t mac_addr_tmp_high;
2841         uint8_t ext_rss_size_max;
2842         uint64_t mac_addr_tmp;
2843         uint32_t i;
2844
2845         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2846
2847         /* get the configuration */
2848         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2849                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2850         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2851                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2852         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2853                                            HNS3_CFG_TQP_DESC_N_M,
2854                                            HNS3_CFG_TQP_DESC_N_S);
2855
2856         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2857                                        HNS3_CFG_PHY_ADDR_M,
2858                                        HNS3_CFG_PHY_ADDR_S);
2859         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2860                                          HNS3_CFG_MEDIA_TP_M,
2861                                          HNS3_CFG_MEDIA_TP_S);
2862         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2863                                          HNS3_CFG_RX_BUF_LEN_M,
2864                                          HNS3_CFG_RX_BUF_LEN_S);
2865         /* get mac address */
2866         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2867         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2868                                            HNS3_CFG_MAC_ADDR_H_M,
2869                                            HNS3_CFG_MAC_ADDR_H_S);
2870
2871         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2872
2873         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2874                                             HNS3_CFG_DEFAULT_SPEED_M,
2875                                             HNS3_CFG_DEFAULT_SPEED_S);
2876         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2877                                            HNS3_CFG_RSS_SIZE_M,
2878                                            HNS3_CFG_RSS_SIZE_S);
2879
2880         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2881                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2882
2883         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2884         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2885
2886         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2887                                             HNS3_CFG_SPEED_ABILITY_M,
2888                                             HNS3_CFG_SPEED_ABILITY_S);
2889         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2890                                         HNS3_CFG_UMV_TBL_SPACE_M,
2891                                         HNS3_CFG_UMV_TBL_SPACE_S);
2892         if (!cfg->umv_space)
2893                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2894
2895         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2896                                                HNS3_CFG_EXT_RSS_SIZE_M,
2897                                                HNS3_CFG_EXT_RSS_SIZE_S);
2898
2899         /*
2900          * Field ext_rss_size_max obtained from firmware will be more flexible
2901          * for future changes and expansions, which is an exponent of 2, instead
2902          * of reading out directly. If this field is not zero, hns3 PF PMD
2903          * driver uses it as rss_size_max under one TC. Device, whose revision
2904          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2905          * maximum number of queues supported under a TC through this field.
2906          */
2907         if (ext_rss_size_max)
2908                 cfg->rss_size_max = 1U << ext_rss_size_max;
2909 }
2910
2911 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2912  * @hw: pointer to struct hns3_hw
2913  * @hcfg: the config structure to be getted
2914  */
2915 static int
2916 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2917 {
2918         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2919         struct hns3_cfg_param_cmd *req;
2920         uint32_t offset;
2921         uint32_t i;
2922         int ret;
2923
2924         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2925                 offset = 0;
2926                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2927                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2928                                           true);
2929                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2930                                i * HNS3_CFG_RD_LEN_BYTES);
2931                 /* Len should be divided by 4 when send to hardware */
2932                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2933                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2934                 req->offset = rte_cpu_to_le_32(offset);
2935         }
2936
2937         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2938         if (ret) {
2939                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2940                 return ret;
2941         }
2942
2943         hns3_parse_cfg(hcfg, desc);
2944
2945         return 0;
2946 }
2947
2948 static int
2949 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2950 {
2951         switch (speed_cmd) {
2952         case HNS3_CFG_SPEED_10M:
2953                 *speed = ETH_SPEED_NUM_10M;
2954                 break;
2955         case HNS3_CFG_SPEED_100M:
2956                 *speed = ETH_SPEED_NUM_100M;
2957                 break;
2958         case HNS3_CFG_SPEED_1G:
2959                 *speed = ETH_SPEED_NUM_1G;
2960                 break;
2961         case HNS3_CFG_SPEED_10G:
2962                 *speed = ETH_SPEED_NUM_10G;
2963                 break;
2964         case HNS3_CFG_SPEED_25G:
2965                 *speed = ETH_SPEED_NUM_25G;
2966                 break;
2967         case HNS3_CFG_SPEED_40G:
2968                 *speed = ETH_SPEED_NUM_40G;
2969                 break;
2970         case HNS3_CFG_SPEED_50G:
2971                 *speed = ETH_SPEED_NUM_50G;
2972                 break;
2973         case HNS3_CFG_SPEED_100G:
2974                 *speed = ETH_SPEED_NUM_100G;
2975                 break;
2976         case HNS3_CFG_SPEED_200G:
2977                 *speed = ETH_SPEED_NUM_200G;
2978                 break;
2979         default:
2980                 return -EINVAL;
2981         }
2982
2983         return 0;
2984 }
2985
2986 static void
2987 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2988 {
2989         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2990         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2991         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2992         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2993         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2994 }
2995
2996 static void
2997 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2998 {
2999         struct hns3_dev_specs_0_cmd *req0;
3000
3001         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3002
3003         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3004         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3005         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3006         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3007         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3008 }
3009
3010 static int
3011 hns3_check_dev_specifications(struct hns3_hw *hw)
3012 {
3013         if (hw->rss_ind_tbl_size == 0 ||
3014             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3015                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3016                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3017                               HNS3_RSS_IND_TBL_SIZE_MAX);
3018                 return -EINVAL;
3019         }
3020
3021         return 0;
3022 }
3023
3024 static int
3025 hns3_query_dev_specifications(struct hns3_hw *hw)
3026 {
3027         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3028         int ret;
3029         int i;
3030
3031         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3032                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3033                                           true);
3034                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3035         }
3036         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3037
3038         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3039         if (ret)
3040                 return ret;
3041
3042         hns3_parse_dev_specifications(hw, desc);
3043
3044         return hns3_check_dev_specifications(hw);
3045 }
3046
3047 static int
3048 hns3_get_capability(struct hns3_hw *hw)
3049 {
3050         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3051         struct rte_pci_device *pci_dev;
3052         struct hns3_pf *pf = &hns->pf;
3053         struct rte_eth_dev *eth_dev;
3054         uint16_t device_id;
3055         uint8_t revision;
3056         int ret;
3057
3058         eth_dev = &rte_eth_devices[hw->data->port_id];
3059         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3060         device_id = pci_dev->id.device_id;
3061
3062         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3063             device_id == HNS3_DEV_ID_50GE_RDMA ||
3064             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3065             device_id == HNS3_DEV_ID_200G_RDMA)
3066                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3067
3068         /* Get PCI revision id */
3069         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3070                                   HNS3_PCI_REVISION_ID);
3071         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3072                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3073                              ret);
3074                 return -EIO;
3075         }
3076         hw->revision = revision;
3077
3078         if (revision < PCI_REVISION_ID_HIP09_A) {
3079                 hns3_set_default_dev_specifications(hw);
3080                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3081                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3082                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3083                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3084                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3085                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3086                 hw->rss_info.ipv6_sctp_offload_supported = false;
3087                 return 0;
3088         }
3089
3090         ret = hns3_query_dev_specifications(hw);
3091         if (ret) {
3092                 PMD_INIT_LOG(ERR,
3093                              "failed to query dev specifications, ret = %d",
3094                              ret);
3095                 return ret;
3096         }
3097
3098         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3099         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3100         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3101         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3102         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3103         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3104         hw->rss_info.ipv6_sctp_offload_supported = true;
3105
3106         return 0;
3107 }
3108
3109 static int
3110 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3111 {
3112         int ret;
3113
3114         switch (media_type) {
3115         case HNS3_MEDIA_TYPE_COPPER:
3116                 if (!hns3_dev_copper_supported(hw)) {
3117                         PMD_INIT_LOG(ERR,
3118                                      "Media type is copper, not supported.");
3119                         ret = -EOPNOTSUPP;
3120                 } else {
3121                         ret = 0;
3122                 }
3123                 break;
3124         case HNS3_MEDIA_TYPE_FIBER:
3125                 ret = 0;
3126                 break;
3127         case HNS3_MEDIA_TYPE_BACKPLANE:
3128                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3129                 ret = -EOPNOTSUPP;
3130                 break;
3131         default:
3132                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3133                 ret = -EINVAL;
3134                 break;
3135         }
3136
3137         return ret;
3138 }
3139
3140 static int
3141 hns3_get_board_configuration(struct hns3_hw *hw)
3142 {
3143         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3144         struct hns3_pf *pf = &hns->pf;
3145         struct hns3_cfg cfg;
3146         int ret;
3147
3148         ret = hns3_get_board_cfg(hw, &cfg);
3149         if (ret) {
3150                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3151                 return ret;
3152         }
3153
3154         ret = hns3_check_media_type(hw, cfg.media_type);
3155         if (ret)
3156                 return ret;
3157
3158         hw->mac.media_type = cfg.media_type;
3159         hw->rss_size_max = cfg.rss_size_max;
3160         hw->rss_dis_flag = false;
3161         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3162         hw->mac.phy_addr = cfg.phy_addr;
3163         hw->mac.default_addr_setted = false;
3164         hw->num_tx_desc = cfg.tqp_desc_num;
3165         hw->num_rx_desc = cfg.tqp_desc_num;
3166         hw->dcb_info.num_pg = 1;
3167         hw->dcb_info.hw_pfc_map = 0;
3168
3169         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3170         if (ret) {
3171                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3172                              cfg.default_speed, ret);
3173                 return ret;
3174         }
3175
3176         pf->tc_max = cfg.tc_num;
3177         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3178                 PMD_INIT_LOG(WARNING,
3179                              "Get TC num(%u) from flash, set TC num to 1",
3180                              pf->tc_max);
3181                 pf->tc_max = 1;
3182         }
3183
3184         /* Dev does not support DCB */
3185         if (!hns3_dev_dcb_supported(hw)) {
3186                 pf->tc_max = 1;
3187                 pf->pfc_max = 0;
3188         } else
3189                 pf->pfc_max = pf->tc_max;
3190
3191         hw->dcb_info.num_tc = 1;
3192         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3193                                      hw->tqps_num / hw->dcb_info.num_tc);
3194         hns3_set_bit(hw->hw_tc_map, 0, 1);
3195         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3196
3197         pf->wanted_umv_size = cfg.umv_space;
3198
3199         return ret;
3200 }
3201
3202 static int
3203 hns3_get_configuration(struct hns3_hw *hw)
3204 {
3205         int ret;
3206
3207         ret = hns3_query_function_status(hw);
3208         if (ret) {
3209                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3210                 return ret;
3211         }
3212
3213         /* Get device capability */
3214         ret = hns3_get_capability(hw);
3215         if (ret) {
3216                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3217                 return ret;
3218         }
3219
3220         /* Get pf resource */
3221         ret = hns3_query_pf_resource(hw);
3222         if (ret) {
3223                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3224                 return ret;
3225         }
3226
3227         ret = hns3_get_board_configuration(hw);
3228         if (ret) {
3229                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3230                 return ret;
3231         }
3232
3233         ret = hns3_query_dev_fec_info(hw);
3234         if (ret)
3235                 PMD_INIT_LOG(ERR,
3236                              "failed to query FEC information, ret = %d", ret);
3237
3238         return ret;
3239 }
3240
3241 static int
3242 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3243                       uint16_t tqp_vid, bool is_pf)
3244 {
3245         struct hns3_tqp_map_cmd *req;
3246         struct hns3_cmd_desc desc;
3247         int ret;
3248
3249         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3250
3251         req = (struct hns3_tqp_map_cmd *)desc.data;
3252         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3253         req->tqp_vf = func_id;
3254         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3255         if (!is_pf)
3256                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3257         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3258
3259         ret = hns3_cmd_send(hw, &desc, 1);
3260         if (ret)
3261                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3262
3263         return ret;
3264 }
3265
3266 static int
3267 hns3_map_tqp(struct hns3_hw *hw)
3268 {
3269         int ret;
3270         int i;
3271
3272         /*
3273          * In current version, VF is not supported when PF is driven by DPDK
3274          * driver, so we assign total tqps_num tqps allocated to this port
3275          * to PF.
3276          */
3277         for (i = 0; i < hw->total_tqps_num; i++) {
3278                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3279                 if (ret)
3280                         return ret;
3281         }
3282
3283         return 0;
3284 }
3285
3286 static int
3287 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3288 {
3289         struct hns3_config_mac_speed_dup_cmd *req;
3290         struct hns3_cmd_desc desc;
3291         int ret;
3292
3293         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3294
3295         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3296
3297         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3298
3299         switch (speed) {
3300         case ETH_SPEED_NUM_10M:
3301                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3302                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3303                 break;
3304         case ETH_SPEED_NUM_100M:
3305                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3306                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3307                 break;
3308         case ETH_SPEED_NUM_1G:
3309                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3310                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3311                 break;
3312         case ETH_SPEED_NUM_10G:
3313                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3314                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3315                 break;
3316         case ETH_SPEED_NUM_25G:
3317                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3318                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3319                 break;
3320         case ETH_SPEED_NUM_40G:
3321                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3322                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3323                 break;
3324         case ETH_SPEED_NUM_50G:
3325                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3326                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3327                 break;
3328         case ETH_SPEED_NUM_100G:
3329                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3330                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3331                 break;
3332         case ETH_SPEED_NUM_200G:
3333                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3334                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3335                 break;
3336         default:
3337                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3338                 return -EINVAL;
3339         }
3340
3341         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3342
3343         ret = hns3_cmd_send(hw, &desc, 1);
3344         if (ret)
3345                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3346
3347         return ret;
3348 }
3349
3350 static int
3351 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3352 {
3353         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3354         struct hns3_pf *pf = &hns->pf;
3355         struct hns3_priv_buf *priv;
3356         uint32_t i, total_size;
3357
3358         total_size = pf->pkt_buf_size;
3359
3360         /* alloc tx buffer for all enabled tc */
3361         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3362                 priv = &buf_alloc->priv_buf[i];
3363
3364                 if (hw->hw_tc_map & BIT(i)) {
3365                         if (total_size < pf->tx_buf_size)
3366                                 return -ENOMEM;
3367
3368                         priv->tx_buf_size = pf->tx_buf_size;
3369                 } else
3370                         priv->tx_buf_size = 0;
3371
3372                 total_size -= priv->tx_buf_size;
3373         }
3374
3375         return 0;
3376 }
3377
3378 static int
3379 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3380 {
3381 /* TX buffer size is unit by 128 byte */
3382 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3383 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3384         struct hns3_tx_buff_alloc_cmd *req;
3385         struct hns3_cmd_desc desc;
3386         uint32_t buf_size;
3387         uint32_t i;
3388         int ret;
3389
3390         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3391
3392         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3393         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3394                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3395
3396                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3397                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3398                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3399         }
3400
3401         ret = hns3_cmd_send(hw, &desc, 1);
3402         if (ret)
3403                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3404
3405         return ret;
3406 }
3407
3408 static int
3409 hns3_get_tc_num(struct hns3_hw *hw)
3410 {
3411         int cnt = 0;
3412         uint8_t i;
3413
3414         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3415                 if (hw->hw_tc_map & BIT(i))
3416                         cnt++;
3417         return cnt;
3418 }
3419
3420 static uint32_t
3421 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3422 {
3423         struct hns3_priv_buf *priv;
3424         uint32_t rx_priv = 0;
3425         int i;
3426
3427         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3428                 priv = &buf_alloc->priv_buf[i];
3429                 if (priv->enable)
3430                         rx_priv += priv->buf_size;
3431         }
3432         return rx_priv;
3433 }
3434
3435 static uint32_t
3436 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3437 {
3438         uint32_t total_tx_size = 0;
3439         uint32_t i;
3440
3441         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3442                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3443
3444         return total_tx_size;
3445 }
3446
3447 /* Get the number of pfc enabled TCs, which have private buffer */
3448 static int
3449 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3450 {
3451         struct hns3_priv_buf *priv;
3452         int cnt = 0;
3453         uint8_t i;
3454
3455         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3456                 priv = &buf_alloc->priv_buf[i];
3457                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3458                         cnt++;
3459         }
3460
3461         return cnt;
3462 }
3463
3464 /* Get the number of pfc disabled TCs, which have private buffer */
3465 static int
3466 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3467                          struct hns3_pkt_buf_alloc *buf_alloc)
3468 {
3469         struct hns3_priv_buf *priv;
3470         int cnt = 0;
3471         uint8_t i;
3472
3473         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3474                 priv = &buf_alloc->priv_buf[i];
3475                 if (hw->hw_tc_map & BIT(i) &&
3476                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3477                         cnt++;
3478         }
3479
3480         return cnt;
3481 }
3482
3483 static bool
3484 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3485                   uint32_t rx_all)
3486 {
3487         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3488         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3489         struct hns3_pf *pf = &hns->pf;
3490         uint32_t shared_buf, aligned_mps;
3491         uint32_t rx_priv;
3492         uint8_t tc_num;
3493         uint8_t i;
3494
3495         tc_num = hns3_get_tc_num(hw);
3496         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3497
3498         if (hns3_dev_dcb_supported(hw))
3499                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3500                                         pf->dv_buf_size;
3501         else
3502                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3503                                         + pf->dv_buf_size;
3504
3505         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3506         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3507                              HNS3_BUF_SIZE_UNIT);
3508
3509         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3510         if (rx_all < rx_priv + shared_std)
3511                 return false;
3512
3513         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3514         buf_alloc->s_buf.buf_size = shared_buf;
3515         if (hns3_dev_dcb_supported(hw)) {
3516                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3517                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3518                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3519                                   HNS3_BUF_SIZE_UNIT);
3520         } else {
3521                 buf_alloc->s_buf.self.high =
3522                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3523                 buf_alloc->s_buf.self.low = aligned_mps;
3524         }
3525
3526         if (hns3_dev_dcb_supported(hw)) {
3527                 hi_thrd = shared_buf - pf->dv_buf_size;
3528
3529                 if (tc_num <= NEED_RESERVE_TC_NUM)
3530                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3531                                   BUF_MAX_PERCENT;
3532
3533                 if (tc_num)
3534                         hi_thrd = hi_thrd / tc_num;
3535
3536                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3537                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3538                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3539         } else {
3540                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3541                 lo_thrd = aligned_mps;
3542         }
3543
3544         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3545                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3546                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3547         }
3548
3549         return true;
3550 }
3551
3552 static bool
3553 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3554                      struct hns3_pkt_buf_alloc *buf_alloc)
3555 {
3556         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3557         struct hns3_pf *pf = &hns->pf;
3558         struct hns3_priv_buf *priv;
3559         uint32_t aligned_mps;
3560         uint32_t rx_all;
3561         uint8_t i;
3562
3563         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3564         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3565
3566         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3567                 priv = &buf_alloc->priv_buf[i];
3568
3569                 priv->enable = 0;
3570                 priv->wl.low = 0;
3571                 priv->wl.high = 0;
3572                 priv->buf_size = 0;
3573
3574                 if (!(hw->hw_tc_map & BIT(i)))
3575                         continue;
3576
3577                 priv->enable = 1;
3578                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3579                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3580                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3581                                                 HNS3_BUF_SIZE_UNIT);
3582                 } else {
3583                         priv->wl.low = 0;
3584                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3585                                         aligned_mps;
3586                 }
3587
3588                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3589         }
3590
3591         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3592 }
3593
3594 static bool
3595 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3596                              struct hns3_pkt_buf_alloc *buf_alloc)
3597 {
3598         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3599         struct hns3_pf *pf = &hns->pf;
3600         struct hns3_priv_buf *priv;
3601         int no_pfc_priv_num;
3602         uint32_t rx_all;
3603         uint8_t mask;
3604         int i;
3605
3606         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3607         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3608
3609         /* let the last to be cleared first */
3610         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3611                 priv = &buf_alloc->priv_buf[i];
3612                 mask = BIT((uint8_t)i);
3613
3614                 if (hw->hw_tc_map & mask &&
3615                     !(hw->dcb_info.hw_pfc_map & mask)) {
3616                         /* Clear the no pfc TC private buffer */
3617                         priv->wl.low = 0;
3618                         priv->wl.high = 0;
3619                         priv->buf_size = 0;
3620                         priv->enable = 0;
3621                         no_pfc_priv_num--;
3622                 }
3623
3624                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3625                     no_pfc_priv_num == 0)
3626                         break;
3627         }
3628
3629         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3630 }
3631
3632 static bool
3633 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3634                            struct hns3_pkt_buf_alloc *buf_alloc)
3635 {
3636         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3637         struct hns3_pf *pf = &hns->pf;
3638         struct hns3_priv_buf *priv;
3639         uint32_t rx_all;
3640         int pfc_priv_num;
3641         uint8_t mask;
3642         int i;
3643
3644         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3645         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3646
3647         /* let the last to be cleared first */
3648         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3649                 priv = &buf_alloc->priv_buf[i];
3650                 mask = BIT((uint8_t)i);
3651                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3652                         /* Reduce the number of pfc TC with private buffer */
3653                         priv->wl.low = 0;
3654                         priv->enable = 0;
3655                         priv->wl.high = 0;
3656                         priv->buf_size = 0;
3657                         pfc_priv_num--;
3658                 }
3659                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3660                     pfc_priv_num == 0)
3661                         break;
3662         }
3663
3664         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3665 }
3666
3667 static bool
3668 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3669                           struct hns3_pkt_buf_alloc *buf_alloc)
3670 {
3671 #define COMPENSATE_BUFFER       0x3C00
3672 #define COMPENSATE_HALF_MPS_NUM 5
3673 #define PRIV_WL_GAP             0x1800
3674         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3675         struct hns3_pf *pf = &hns->pf;
3676         uint32_t tc_num = hns3_get_tc_num(hw);
3677         uint32_t half_mps = pf->mps >> 1;
3678         struct hns3_priv_buf *priv;
3679         uint32_t min_rx_priv;
3680         uint32_t rx_priv;
3681         uint8_t i;
3682
3683         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3684         if (tc_num)
3685                 rx_priv = rx_priv / tc_num;
3686
3687         if (tc_num <= NEED_RESERVE_TC_NUM)
3688                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3689
3690         /*
3691          * Minimum value of private buffer in rx direction (min_rx_priv) is
3692          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3693          * buffer if rx_priv is greater than min_rx_priv.
3694          */
3695         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3696                         COMPENSATE_HALF_MPS_NUM * half_mps;
3697         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3698         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3699
3700         if (rx_priv < min_rx_priv)
3701                 return false;
3702
3703         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3704                 priv = &buf_alloc->priv_buf[i];
3705                 priv->enable = 0;
3706                 priv->wl.low = 0;
3707                 priv->wl.high = 0;
3708                 priv->buf_size = 0;
3709
3710                 if (!(hw->hw_tc_map & BIT(i)))
3711                         continue;
3712
3713                 priv->enable = 1;
3714                 priv->buf_size = rx_priv;
3715                 priv->wl.high = rx_priv - pf->dv_buf_size;
3716                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3717         }
3718
3719         buf_alloc->s_buf.buf_size = 0;
3720
3721         return true;
3722 }
3723
3724 /*
3725  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3726  * @hw: pointer to struct hns3_hw
3727  * @buf_alloc: pointer to buffer calculation data
3728  * @return: 0: calculate sucessful, negative: fail
3729  */
3730 static int
3731 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3732 {
3733         /* When DCB is not supported, rx private buffer is not allocated. */
3734         if (!hns3_dev_dcb_supported(hw)) {
3735                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3736                 struct hns3_pf *pf = &hns->pf;
3737                 uint32_t rx_all = pf->pkt_buf_size;
3738
3739                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3740                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3741                         return -ENOMEM;
3742
3743                 return 0;
3744         }
3745
3746         /*
3747          * Try to allocate privated packet buffer for all TCs without share
3748          * buffer.
3749          */
3750         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3751                 return 0;
3752
3753         /*
3754          * Try to allocate privated packet buffer for all TCs with share
3755          * buffer.
3756          */
3757         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3758                 return 0;
3759
3760         /*
3761          * For different application scenes, the enabled port number, TC number
3762          * and no_drop TC number are different. In order to obtain the better
3763          * performance, software could allocate the buffer size and configure
3764          * the waterline by tring to decrease the private buffer size according
3765          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3766          * enabled tc.
3767          */
3768         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3769                 return 0;
3770
3771         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3772                 return 0;
3773
3774         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3775                 return 0;
3776
3777         return -ENOMEM;
3778 }
3779
3780 static int
3781 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3782 {
3783         struct hns3_rx_priv_buff_cmd *req;
3784         struct hns3_cmd_desc desc;
3785         uint32_t buf_size;
3786         int ret;
3787         int i;
3788
3789         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3790         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3791
3792         /* Alloc private buffer TCs */
3793         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3794                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3795
3796                 req->buf_num[i] =
3797                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3798                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3799         }
3800
3801         buf_size = buf_alloc->s_buf.buf_size;
3802         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3803                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3804
3805         ret = hns3_cmd_send(hw, &desc, 1);
3806         if (ret)
3807                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3808
3809         return ret;
3810 }
3811
3812 static int
3813 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3814 {
3815 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3816         struct hns3_rx_priv_wl_buf *req;
3817         struct hns3_priv_buf *priv;
3818         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3819         int i, j;
3820         int ret;
3821
3822         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3823                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3824                                           false);
3825                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3826
3827                 /* The first descriptor set the NEXT bit to 1 */
3828                 if (i == 0)
3829                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3830                 else
3831                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3832
3833                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3834                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3835
3836                         priv = &buf_alloc->priv_buf[idx];
3837                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3838                                                         HNS3_BUF_UNIT_S);
3839                         req->tc_wl[j].high |=
3840                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3841                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3842                                                         HNS3_BUF_UNIT_S);
3843                         req->tc_wl[j].low |=
3844                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3845                 }
3846         }
3847
3848         /* Send 2 descriptor at one time */
3849         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3850         if (ret)
3851                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3852                              ret);
3853         return ret;
3854 }
3855
3856 static int
3857 hns3_common_thrd_config(struct hns3_hw *hw,
3858                         struct hns3_pkt_buf_alloc *buf_alloc)
3859 {
3860 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3861         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3862         struct hns3_rx_com_thrd *req;
3863         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3864         struct hns3_tc_thrd *tc;
3865         int tc_idx;
3866         int i, j;
3867         int ret;
3868
3869         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3870                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3871                                           false);
3872                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3873
3874                 /* The first descriptor set the NEXT bit to 1 */
3875                 if (i == 0)
3876                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3877                 else
3878                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3879
3880                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3881                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3882                         tc = &s_buf->tc_thrd[tc_idx];
3883
3884                         req->com_thrd[j].high =
3885                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3886                         req->com_thrd[j].high |=
3887                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3888                         req->com_thrd[j].low =
3889                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3890                         req->com_thrd[j].low |=
3891                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3892                 }
3893         }
3894
3895         /* Send 2 descriptors at one time */
3896         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3897         if (ret)
3898                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3899
3900         return ret;
3901 }
3902
3903 static int
3904 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3905 {
3906         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3907         struct hns3_rx_com_wl *req;
3908         struct hns3_cmd_desc desc;
3909         int ret;
3910
3911         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3912
3913         req = (struct hns3_rx_com_wl *)desc.data;
3914         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3915         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3916
3917         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3918         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3919
3920         ret = hns3_cmd_send(hw, &desc, 1);
3921         if (ret)
3922                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3923
3924         return ret;
3925 }
3926
3927 int
3928 hns3_buffer_alloc(struct hns3_hw *hw)
3929 {
3930         struct hns3_pkt_buf_alloc pkt_buf;
3931         int ret;
3932
3933         memset(&pkt_buf, 0, sizeof(pkt_buf));
3934         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3935         if (ret) {
3936                 PMD_INIT_LOG(ERR,
3937                              "could not calc tx buffer size for all TCs %d",
3938                              ret);
3939                 return ret;
3940         }
3941
3942         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3943         if (ret) {
3944                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3945                 return ret;
3946         }
3947
3948         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3949         if (ret) {
3950                 PMD_INIT_LOG(ERR,
3951                              "could not calc rx priv buffer size for all TCs %d",
3952                              ret);
3953                 return ret;
3954         }
3955
3956         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3957         if (ret) {
3958                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3959                 return ret;
3960         }
3961
3962         if (hns3_dev_dcb_supported(hw)) {
3963                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3964                 if (ret) {
3965                         PMD_INIT_LOG(ERR,
3966                                      "could not configure rx private waterline %d",
3967                                      ret);
3968                         return ret;
3969                 }
3970
3971                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3972                 if (ret) {
3973                         PMD_INIT_LOG(ERR,
3974                                      "could not configure common threshold %d",
3975                                      ret);
3976                         return ret;
3977                 }
3978         }
3979
3980         ret = hns3_common_wl_config(hw, &pkt_buf);
3981         if (ret)
3982                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3983                              ret);
3984
3985         return ret;
3986 }
3987
3988 static int
3989 hns3_firmware_compat_config(struct hns3_hw *hw, bool is_init)
3990 {
3991         struct hns3_firmware_compat_cmd *req;
3992         struct hns3_cmd_desc desc;
3993         uint32_t compat = 0;
3994
3995         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_FIRMWARE_COMPAT_CFG, false);
3996         req = (struct hns3_firmware_compat_cmd *)desc.data;
3997
3998         if (is_init) {
3999                 hns3_set_bit(compat, HNS3_LINK_EVENT_REPORT_EN_B, 1);
4000                 hns3_set_bit(compat, HNS3_NCSI_ERROR_REPORT_EN_B, 0);
4001                 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4002                         hns3_set_bit(compat, HNS3_FIRMWARE_PHY_DRIVER_EN_B, 1);
4003         }
4004
4005         req->compat = rte_cpu_to_le_32(compat);
4006
4007         return hns3_cmd_send(hw, &desc, 1);
4008 }
4009
4010 static int
4011 hns3_mac_init(struct hns3_hw *hw)
4012 {
4013         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4014         struct hns3_mac *mac = &hw->mac;
4015         struct hns3_pf *pf = &hns->pf;
4016         int ret;
4017
4018         pf->support_sfp_query = true;
4019         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4020         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4021         if (ret) {
4022                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4023                 return ret;
4024         }
4025
4026         mac->link_status = ETH_LINK_DOWN;
4027
4028         return hns3_config_mtu(hw, pf->mps);
4029 }
4030
4031 static int
4032 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4033 {
4034 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4035 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4036 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4037 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4038         int return_status;
4039
4040         if (cmdq_resp) {
4041                 PMD_INIT_LOG(ERR,
4042                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4043                              cmdq_resp);
4044                 return -EIO;
4045         }
4046
4047         switch (resp_code) {
4048         case HNS3_ETHERTYPE_SUCCESS_ADD:
4049         case HNS3_ETHERTYPE_ALREADY_ADD:
4050                 return_status = 0;
4051                 break;
4052         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4053                 PMD_INIT_LOG(ERR,
4054                              "add mac ethertype failed for manager table overflow.");
4055                 return_status = -EIO;
4056                 break;
4057         case HNS3_ETHERTYPE_KEY_CONFLICT:
4058                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4059                 return_status = -EIO;
4060                 break;
4061         default:
4062                 PMD_INIT_LOG(ERR,
4063                              "add mac ethertype failed for undefined, code=%u.",
4064                              resp_code);
4065                 return_status = -EIO;
4066                 break;
4067         }
4068
4069         return return_status;
4070 }
4071
4072 static int
4073 hns3_add_mgr_tbl(struct hns3_hw *hw,
4074                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4075 {
4076         struct hns3_cmd_desc desc;
4077         uint8_t resp_code;
4078         uint16_t retval;
4079         int ret;
4080
4081         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4082         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4083
4084         ret = hns3_cmd_send(hw, &desc, 1);
4085         if (ret) {
4086                 PMD_INIT_LOG(ERR,
4087                              "add mac ethertype failed for cmd_send, ret =%d.",
4088                              ret);
4089                 return ret;
4090         }
4091
4092         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4093         retval = rte_le_to_cpu_16(desc.retval);
4094
4095         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4096 }
4097
4098 static void
4099 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4100                      int *table_item_num)
4101 {
4102         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4103
4104         /*
4105          * In current version, we add one item in management table as below:
4106          * 0x0180C200000E -- LLDP MC address
4107          */
4108         tbl = mgr_table;
4109         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4110         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4111         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4112         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4113         tbl->i_port_bitmap = 0x1;
4114         *table_item_num = 1;
4115 }
4116
4117 static int
4118 hns3_init_mgr_tbl(struct hns3_hw *hw)
4119 {
4120 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4121         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4122         int table_item_num;
4123         int ret;
4124         int i;
4125
4126         memset(mgr_table, 0, sizeof(mgr_table));
4127         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4128         for (i = 0; i < table_item_num; i++) {
4129                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4130                 if (ret) {
4131                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4132                                      ret);
4133                         return ret;
4134                 }
4135         }
4136
4137         return 0;
4138 }
4139
4140 static void
4141 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4142                         bool en_mc, bool en_bc, int vport_id)
4143 {
4144         if (!param)
4145                 return;
4146
4147         memset(param, 0, sizeof(struct hns3_promisc_param));
4148         if (en_uc)
4149                 param->enable = HNS3_PROMISC_EN_UC;
4150         if (en_mc)
4151                 param->enable |= HNS3_PROMISC_EN_MC;
4152         if (en_bc)
4153                 param->enable |= HNS3_PROMISC_EN_BC;
4154         param->vf_id = vport_id;
4155 }
4156
4157 static int
4158 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4159 {
4160         struct hns3_promisc_cfg_cmd *req;
4161         struct hns3_cmd_desc desc;
4162         int ret;
4163
4164         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4165
4166         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4167         req->vf_id = param->vf_id;
4168         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4169             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4170
4171         ret = hns3_cmd_send(hw, &desc, 1);
4172         if (ret)
4173                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4174
4175         return ret;
4176 }
4177
4178 static int
4179 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4180 {
4181         struct hns3_promisc_param param;
4182         bool en_bc_pmc = true;
4183         uint8_t vf_id;
4184
4185         /*
4186          * In current version VF is not supported when PF is driven by DPDK
4187          * driver, just need to configure parameters for PF vport.
4188          */
4189         vf_id = HNS3_PF_FUNC_ID;
4190
4191         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4192         return hns3_cmd_set_promisc_mode(hw, &param);
4193 }
4194
4195 static int
4196 hns3_promisc_init(struct hns3_hw *hw)
4197 {
4198         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4199         struct hns3_pf *pf = &hns->pf;
4200         struct hns3_promisc_param param;
4201         uint16_t func_id;
4202         int ret;
4203
4204         ret = hns3_set_promisc_mode(hw, false, false);
4205         if (ret) {
4206                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4207                 return ret;
4208         }
4209
4210         /*
4211          * In current version VFs are not supported when PF is driven by DPDK
4212          * driver. After PF has been taken over by DPDK, the original VF will
4213          * be invalid. So, there is a possibility of entry residues. It should
4214          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4215          * during init.
4216          */
4217         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4218                 hns3_promisc_param_init(&param, false, false, false, func_id);
4219                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4220                 if (ret) {
4221                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4222                                         " ret = %d", func_id, ret);
4223                         return ret;
4224                 }
4225         }
4226
4227         return 0;
4228 }
4229
4230 static void
4231 hns3_promisc_uninit(struct hns3_hw *hw)
4232 {
4233         struct hns3_promisc_param param;
4234         uint16_t func_id;
4235         int ret;
4236
4237         func_id = HNS3_PF_FUNC_ID;
4238
4239         /*
4240          * In current version VFs are not supported when PF is driven by
4241          * DPDK driver, and VFs' promisc mode status has been cleared during
4242          * init and their status will not change. So just clear PF's promisc
4243          * mode status during uninit.
4244          */
4245         hns3_promisc_param_init(&param, false, false, false, func_id);
4246         ret = hns3_cmd_set_promisc_mode(hw, &param);
4247         if (ret)
4248                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4249                                 " uninit, ret = %d", ret);
4250 }
4251
4252 static int
4253 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4254 {
4255         bool allmulti = dev->data->all_multicast ? true : false;
4256         struct hns3_adapter *hns = dev->data->dev_private;
4257         struct hns3_hw *hw = &hns->hw;
4258         uint64_t offloads;
4259         int err;
4260         int ret;
4261
4262         rte_spinlock_lock(&hw->lock);
4263         ret = hns3_set_promisc_mode(hw, true, true);
4264         if (ret) {
4265                 rte_spinlock_unlock(&hw->lock);
4266                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4267                          ret);
4268                 return ret;
4269         }
4270
4271         /*
4272          * When promiscuous mode was enabled, disable the vlan filter to let
4273          * all packets coming in in the receiving direction.
4274          */
4275         offloads = dev->data->dev_conf.rxmode.offloads;
4276         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4277                 ret = hns3_enable_vlan_filter(hns, false);
4278                 if (ret) {
4279                         hns3_err(hw, "failed to enable promiscuous mode due to "
4280                                      "failure to disable vlan filter, ret = %d",
4281                                  ret);
4282                         err = hns3_set_promisc_mode(hw, false, allmulti);
4283                         if (err)
4284                                 hns3_err(hw, "failed to restore promiscuous "
4285                                          "status after disable vlan filter "
4286                                          "failed during enabling promiscuous "
4287                                          "mode, ret = %d", ret);
4288                 }
4289         }
4290
4291         rte_spinlock_unlock(&hw->lock);
4292
4293         return ret;
4294 }
4295
4296 static int
4297 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4298 {
4299         bool allmulti = dev->data->all_multicast ? true : false;
4300         struct hns3_adapter *hns = dev->data->dev_private;
4301         struct hns3_hw *hw = &hns->hw;
4302         uint64_t offloads;
4303         int err;
4304         int ret;
4305
4306         /* If now in all_multicast mode, must remain in all_multicast mode. */
4307         rte_spinlock_lock(&hw->lock);
4308         ret = hns3_set_promisc_mode(hw, false, allmulti);
4309         if (ret) {
4310                 rte_spinlock_unlock(&hw->lock);
4311                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4312                          ret);
4313                 return ret;
4314         }
4315         /* when promiscuous mode was disabled, restore the vlan filter status */
4316         offloads = dev->data->dev_conf.rxmode.offloads;
4317         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4318                 ret = hns3_enable_vlan_filter(hns, true);
4319                 if (ret) {
4320                         hns3_err(hw, "failed to disable promiscuous mode due to"
4321                                  " failure to restore vlan filter, ret = %d",
4322                                  ret);
4323                         err = hns3_set_promisc_mode(hw, true, true);
4324                         if (err)
4325                                 hns3_err(hw, "failed to restore promiscuous "
4326                                          "status after enabling vlan filter "
4327                                          "failed during disabling promiscuous "
4328                                          "mode, ret = %d", ret);
4329                 }
4330         }
4331         rte_spinlock_unlock(&hw->lock);
4332
4333         return ret;
4334 }
4335
4336 static int
4337 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4338 {
4339         struct hns3_adapter *hns = dev->data->dev_private;
4340         struct hns3_hw *hw = &hns->hw;
4341         int ret;
4342
4343         if (dev->data->promiscuous)
4344                 return 0;
4345
4346         rte_spinlock_lock(&hw->lock);
4347         ret = hns3_set_promisc_mode(hw, false, true);
4348         rte_spinlock_unlock(&hw->lock);
4349         if (ret)
4350                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4351                          ret);
4352
4353         return ret;
4354 }
4355
4356 static int
4357 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4358 {
4359         struct hns3_adapter *hns = dev->data->dev_private;
4360         struct hns3_hw *hw = &hns->hw;
4361         int ret;
4362
4363         /* If now in promiscuous mode, must remain in all_multicast mode. */
4364         if (dev->data->promiscuous)
4365                 return 0;
4366
4367         rte_spinlock_lock(&hw->lock);
4368         ret = hns3_set_promisc_mode(hw, false, false);
4369         rte_spinlock_unlock(&hw->lock);
4370         if (ret)
4371                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4372                          ret);
4373
4374         return ret;
4375 }
4376
4377 static int
4378 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4379 {
4380         struct hns3_hw *hw = &hns->hw;
4381         bool allmulti = hw->data->all_multicast ? true : false;
4382         int ret;
4383
4384         if (hw->data->promiscuous) {
4385                 ret = hns3_set_promisc_mode(hw, true, true);
4386                 if (ret)
4387                         hns3_err(hw, "failed to restore promiscuous mode, "
4388                                  "ret = %d", ret);
4389                 return ret;
4390         }
4391
4392         ret = hns3_set_promisc_mode(hw, false, allmulti);
4393         if (ret)
4394                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4395                          ret);
4396         return ret;
4397 }
4398
4399 static int
4400 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4401 {
4402         struct hns3_sfp_speed_cmd *resp;
4403         struct hns3_cmd_desc desc;
4404         int ret;
4405
4406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4407         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4408         ret = hns3_cmd_send(hw, &desc, 1);
4409         if (ret == -EOPNOTSUPP) {
4410                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4411                 return ret;
4412         } else if (ret) {
4413                 hns3_err(hw, "get sfp speed failed %d", ret);
4414                 return ret;
4415         }
4416
4417         *speed = resp->sfp_speed;
4418
4419         return 0;
4420 }
4421
4422 static uint8_t
4423 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4424 {
4425         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4426                 duplex = ETH_LINK_FULL_DUPLEX;
4427
4428         return duplex;
4429 }
4430
4431 static int
4432 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4433 {
4434         struct hns3_mac *mac = &hw->mac;
4435         int ret;
4436
4437         duplex = hns3_check_speed_dup(duplex, speed);
4438         if (mac->link_speed == speed && mac->link_duplex == duplex)
4439                 return 0;
4440
4441         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4442         if (ret)
4443                 return ret;
4444
4445         ret = hns3_port_shaper_update(hw, speed);
4446         if (ret)
4447                 return ret;
4448
4449         mac->link_speed = speed;
4450         mac->link_duplex = duplex;
4451
4452         return 0;
4453 }
4454
4455 static int
4456 hns3_update_fiber_link_info(struct hns3_hw *hw)
4457 {
4458         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4459         uint32_t speed;
4460         int ret;
4461
4462         /* If IMP do not support get SFP/qSFP speed, return directly */
4463         if (!pf->support_sfp_query)
4464                 return 0;
4465
4466         ret = hns3_get_sfp_speed(hw, &speed);
4467         if (ret == -EOPNOTSUPP) {
4468                 pf->support_sfp_query = false;
4469                 return ret;
4470         } else if (ret)
4471                 return ret;
4472
4473         if (speed == ETH_SPEED_NUM_NONE)
4474                 return 0; /* do nothing if no SFP */
4475
4476         /* Config full duplex for SFP */
4477         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4478 }
4479
4480 static void
4481 hns3_parse_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4482 {
4483         struct hns3_phy_params_bd0_cmd *req;
4484
4485         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4486         mac->link_speed = rte_le_to_cpu_32(req->speed);
4487         mac->link_duplex = hns3_get_bit(req->duplex,
4488                                            HNS3_PHY_DUPLEX_CFG_B);
4489         mac->link_autoneg = hns3_get_bit(req->autoneg,
4490                                            HNS3_PHY_AUTONEG_CFG_B);
4491         mac->supported_capa = rte_le_to_cpu_32(req->supported);
4492         mac->advertising = rte_le_to_cpu_32(req->advertising);
4493         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4494         mac->support_autoneg = !!(mac->supported_capa &
4495                                 HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4496 }
4497
4498 static int
4499 hns3_get_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4500 {
4501         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4502         uint16_t i;
4503         int ret;
4504
4505         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4506                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4507                                           true);
4508                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4509         }
4510         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4511
4512         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4513         if (ret) {
4514                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4515                 return ret;
4516         }
4517
4518         hns3_parse_phy_params(desc, mac);
4519
4520         return 0;
4521 }
4522
4523 static int
4524 hns3_update_phy_link_info(struct hns3_hw *hw)
4525 {
4526         struct hns3_mac *mac = &hw->mac;
4527         struct hns3_mac mac_info;
4528         int ret;
4529
4530         memset(&mac_info, 0, sizeof(struct hns3_mac));
4531         ret = hns3_get_phy_params(hw, &mac_info);
4532         if (ret)
4533                 return ret;
4534
4535         if (mac_info.link_speed != mac->link_speed) {
4536                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4537                 if (ret)
4538                         return ret;
4539         }
4540
4541         mac->link_speed = mac_info.link_speed;
4542         mac->link_duplex = mac_info.link_duplex;
4543         mac->link_autoneg = mac_info.link_autoneg;
4544         mac->supported_capa = mac_info.supported_capa;
4545         mac->advertising = mac_info.advertising;
4546         mac->lp_advertising = mac_info.lp_advertising;
4547         mac->support_autoneg = mac_info.support_autoneg;
4548
4549         return 0;
4550 }
4551
4552 static int
4553 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4554 {
4555         struct hns3_adapter *hns = eth_dev->data->dev_private;
4556         struct hns3_hw *hw = &hns->hw;
4557         int ret = 0;
4558
4559         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4560                 ret = hns3_update_phy_link_info(hw);
4561         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4562                 ret = hns3_update_fiber_link_info(hw);
4563
4564         return ret;
4565 }
4566
4567 static int
4568 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4569 {
4570         struct hns3_config_mac_mode_cmd *req;
4571         struct hns3_cmd_desc desc;
4572         uint32_t loop_en = 0;
4573         uint8_t val = 0;
4574         int ret;
4575
4576         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4577
4578         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4579         if (enable)
4580                 val = 1;
4581         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4582         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4583         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4584         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4585         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4586         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4587         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4588         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4589         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4590         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4591
4592         /*
4593          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4594          * when receiving frames. Otherwise, CRC will be stripped.
4595          */
4596         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4597                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4598         else
4599                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4600         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4601         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4602         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4603         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4604
4605         ret = hns3_cmd_send(hw, &desc, 1);
4606         if (ret)
4607                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4608
4609         return ret;
4610 }
4611
4612 static int
4613 hns3_get_mac_link_status(struct hns3_hw *hw)
4614 {
4615         struct hns3_link_status_cmd *req;
4616         struct hns3_cmd_desc desc;
4617         int link_status;
4618         int ret;
4619
4620         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4621         ret = hns3_cmd_send(hw, &desc, 1);
4622         if (ret) {
4623                 hns3_err(hw, "get link status cmd failed %d", ret);
4624                 return ETH_LINK_DOWN;
4625         }
4626
4627         req = (struct hns3_link_status_cmd *)desc.data;
4628         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4629
4630         return !!link_status;
4631 }
4632
4633 static bool
4634 hns3_update_link_status(struct hns3_hw *hw)
4635 {
4636         int state;
4637
4638         state = hns3_get_mac_link_status(hw);
4639         if (state != hw->mac.link_status) {
4640                 hw->mac.link_status = state;
4641                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4642                 return true;
4643         }
4644
4645         return false;
4646 }
4647
4648 /*
4649  * Current, the PF driver get link status by two ways:
4650  * 1) Periodic polling in the intr thread context, driver call
4651  *    hns3_update_link_status to update link status.
4652  * 2) Firmware report async interrupt, driver process the event in the intr
4653  *    thread context, and call hns3_update_link_status to update link status.
4654  *
4655  * If detect link status changed, driver need report LSE. One method is add the
4656  * report LSE logic in hns3_update_link_status.
4657  *
4658  * But the PF driver ops(link_update) also call hns3_update_link_status to
4659  * update link status.
4660  * If we report LSE in hns3_update_link_status, it may lead to deadlock in the
4661  * bonding application.
4662  *
4663  * So add the one new API which used only in intr thread context.
4664  */
4665 void
4666 hns3_update_link_status_and_event(struct hns3_hw *hw)
4667 {
4668         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4669         bool changed = hns3_update_link_status(hw);
4670         if (changed)
4671                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4672 }
4673
4674 static void
4675 hns3_service_handler(void *param)
4676 {
4677         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4678         struct hns3_adapter *hns = eth_dev->data->dev_private;
4679         struct hns3_hw *hw = &hns->hw;
4680
4681         if (!hns3_is_reset_pending(hns)) {
4682                 hns3_update_link_status_and_event(hw);
4683                 hns3_update_link_info(eth_dev);
4684         } else {
4685                 hns3_warn(hw, "Cancel the query when reset is pending");
4686         }
4687
4688         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4689 }
4690
4691 static int
4692 hns3_init_hardware(struct hns3_adapter *hns)
4693 {
4694         struct hns3_hw *hw = &hns->hw;
4695         int ret;
4696
4697         ret = hns3_map_tqp(hw);
4698         if (ret) {
4699                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4700                 return ret;
4701         }
4702
4703         ret = hns3_init_umv_space(hw);
4704         if (ret) {
4705                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4706                 return ret;
4707         }
4708
4709         ret = hns3_mac_init(hw);
4710         if (ret) {
4711                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4712                 goto err_mac_init;
4713         }
4714
4715         ret = hns3_init_mgr_tbl(hw);
4716         if (ret) {
4717                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4718                 goto err_mac_init;
4719         }
4720
4721         ret = hns3_promisc_init(hw);
4722         if (ret) {
4723                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4724                              ret);
4725                 goto err_mac_init;
4726         }
4727
4728         ret = hns3_init_vlan_config(hns);
4729         if (ret) {
4730                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4731                 goto err_mac_init;
4732         }
4733
4734         ret = hns3_dcb_init(hw);
4735         if (ret) {
4736                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4737                 goto err_mac_init;
4738         }
4739
4740         ret = hns3_init_fd_config(hns);
4741         if (ret) {
4742                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4743                 goto err_mac_init;
4744         }
4745
4746         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4747         if (ret) {
4748                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4749                 goto err_mac_init;
4750         }
4751
4752         ret = hns3_config_gro(hw, false);
4753         if (ret) {
4754                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4755                 goto err_mac_init;
4756         }
4757
4758         /*
4759          * In the initialization clearing the all hardware mapping relationship
4760          * configurations between queues and interrupt vectors is needed, so
4761          * some error caused by the residual configurations, such as the
4762          * unexpected interrupt, can be avoid.
4763          */
4764         ret = hns3_init_ring_with_vector(hw);
4765         if (ret) {
4766                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4767                 goto err_mac_init;
4768         }
4769
4770         /*
4771          * Requiring firmware to enable some features, driver can
4772          * still work without it.
4773          */
4774         ret = hns3_firmware_compat_config(hw, true);
4775         if (ret)
4776                 PMD_INIT_LOG(WARNING, "firmware compatible features not "
4777                              "supported, ret = %d.", ret);
4778
4779         return 0;
4780
4781 err_mac_init:
4782         hns3_uninit_umv_space(hw);
4783         return ret;
4784 }
4785
4786 static int
4787 hns3_clear_hw(struct hns3_hw *hw)
4788 {
4789         struct hns3_cmd_desc desc;
4790         int ret;
4791
4792         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4793
4794         ret = hns3_cmd_send(hw, &desc, 1);
4795         if (ret && ret != -EOPNOTSUPP)
4796                 return ret;
4797
4798         return 0;
4799 }
4800
4801 static void
4802 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4803 {
4804         uint32_t val;
4805
4806         /*
4807          * The new firmware support report more hardware error types by
4808          * msix mode. These errors are defined as RAS errors in hardware
4809          * and belong to a different type from the MSI-x errors processed
4810          * by the network driver.
4811          *
4812          * Network driver should open the new error report on initialition
4813          */
4814         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4815         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4816         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4817 }
4818
4819 static int
4820 hns3_init_pf(struct rte_eth_dev *eth_dev)
4821 {
4822         struct rte_device *dev = eth_dev->device;
4823         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4824         struct hns3_adapter *hns = eth_dev->data->dev_private;
4825         struct hns3_hw *hw = &hns->hw;
4826         int ret;
4827
4828         PMD_INIT_FUNC_TRACE();
4829
4830         /* Get hardware io base address from pcie BAR2 IO space */
4831         hw->io_base = pci_dev->mem_resource[2].addr;
4832
4833         /* Firmware command queue initialize */
4834         ret = hns3_cmd_init_queue(hw);
4835         if (ret) {
4836                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4837                 goto err_cmd_init_queue;
4838         }
4839
4840         hns3_clear_all_event_cause(hw);
4841
4842         /* Firmware command initialize */
4843         ret = hns3_cmd_init(hw);
4844         if (ret) {
4845                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4846                 goto err_cmd_init;
4847         }
4848
4849         /*
4850          * To ensure that the hardware environment is clean during
4851          * initialization, the driver actively clear the hardware environment
4852          * during initialization, including PF and corresponding VFs' vlan, mac,
4853          * flow table configurations, etc.
4854          */
4855         ret = hns3_clear_hw(hw);
4856         if (ret) {
4857                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4858                 goto err_cmd_init;
4859         }
4860
4861         /* Hardware statistics of imissed registers cleared. */
4862         ret = hns3_update_imissed_stats(hw, true);
4863         if (ret) {
4864                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4865                 return ret;
4866         }
4867
4868         hns3_config_all_msix_error(hw, true);
4869
4870         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4871                                          hns3_interrupt_handler,
4872                                          eth_dev);
4873         if (ret) {
4874                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4875                 goto err_intr_callback_register;
4876         }
4877
4878         /* Enable interrupt */
4879         rte_intr_enable(&pci_dev->intr_handle);
4880         hns3_pf_enable_irq0(hw);
4881
4882         /* Get configuration */
4883         ret = hns3_get_configuration(hw);
4884         if (ret) {
4885                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4886                 goto err_get_config;
4887         }
4888
4889         ret = hns3_tqp_stats_init(hw);
4890         if (ret)
4891                 goto err_get_config;
4892
4893         ret = hns3_init_hardware(hns);
4894         if (ret) {
4895                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4896                 goto err_init_hw;
4897         }
4898
4899         /* Initialize flow director filter list & hash */
4900         ret = hns3_fdir_filter_init(hns);
4901         if (ret) {
4902                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4903                 goto err_fdir;
4904         }
4905
4906         hns3_rss_set_default_args(hw);
4907
4908         ret = hns3_enable_hw_error_intr(hns, true);
4909         if (ret) {
4910                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4911                              ret);
4912                 goto err_enable_intr;
4913         }
4914
4915         hns3_tm_conf_init(eth_dev);
4916
4917         return 0;
4918
4919 err_enable_intr:
4920         hns3_fdir_filter_uninit(hns);
4921 err_fdir:
4922         (void)hns3_firmware_compat_config(hw, false);
4923         hns3_uninit_umv_space(hw);
4924 err_init_hw:
4925         hns3_tqp_stats_uninit(hw);
4926 err_get_config:
4927         hns3_pf_disable_irq0(hw);
4928         rte_intr_disable(&pci_dev->intr_handle);
4929         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4930                              eth_dev);
4931 err_intr_callback_register:
4932 err_cmd_init:
4933         hns3_cmd_uninit(hw);
4934         hns3_cmd_destroy_queue(hw);
4935 err_cmd_init_queue:
4936         hw->io_base = NULL;
4937
4938         return ret;
4939 }
4940
4941 static void
4942 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4943 {
4944         struct hns3_adapter *hns = eth_dev->data->dev_private;
4945         struct rte_device *dev = eth_dev->device;
4946         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4947         struct hns3_hw *hw = &hns->hw;
4948
4949         PMD_INIT_FUNC_TRACE();
4950
4951         hns3_tm_conf_uninit(eth_dev);
4952         hns3_enable_hw_error_intr(hns, false);
4953         hns3_rss_uninit(hns);
4954         (void)hns3_config_gro(hw, false);
4955         hns3_promisc_uninit(hw);
4956         hns3_fdir_filter_uninit(hns);
4957         (void)hns3_firmware_compat_config(hw, false);
4958         hns3_uninit_umv_space(hw);
4959         hns3_tqp_stats_uninit(hw);
4960         hns3_pf_disable_irq0(hw);
4961         rte_intr_disable(&pci_dev->intr_handle);
4962         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4963                              eth_dev);
4964         hns3_config_all_msix_error(hw, false);
4965         hns3_cmd_uninit(hw);
4966         hns3_cmd_destroy_queue(hw);
4967         hw->io_base = NULL;
4968 }
4969
4970 static int
4971 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4972 {
4973         struct hns3_hw *hw = &hns->hw;
4974         int ret;
4975
4976         ret = hns3_dcb_cfg_update(hns);
4977         if (ret)
4978                 return ret;
4979
4980         /*
4981          * The hns3_dcb_cfg_update may configure TM module, so
4982          * hns3_tm_conf_update must called later.
4983          */
4984         ret = hns3_tm_conf_update(hw);
4985         if (ret) {
4986                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
4987                 return ret;
4988         }
4989
4990         hns3_enable_rxd_adv_layout(hw);
4991
4992         ret = hns3_init_queues(hns, reset_queue);
4993         if (ret) {
4994                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
4995                 return ret;
4996         }
4997
4998         ret = hns3_cfg_mac_mode(hw, true);
4999         if (ret) {
5000                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5001                 goto err_config_mac_mode;
5002         }
5003         return 0;
5004
5005 err_config_mac_mode:
5006         hns3_dev_release_mbufs(hns);
5007         /*
5008          * Here is exception handling, hns3_reset_all_tqps will have the
5009          * corresponding error message if it is handled incorrectly, so it is
5010          * not necessary to check hns3_reset_all_tqps return value, here keep
5011          * ret as the error code causing the exception.
5012          */
5013         (void)hns3_reset_all_tqps(hns);
5014         return ret;
5015 }
5016
5017 static int
5018 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5019 {
5020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5022         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5024         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5025         uint32_t intr_vector;
5026         uint16_t q_id;
5027         int ret;
5028
5029         /*
5030          * hns3 needs a separate interrupt to be used as event interrupt which
5031          * could not be shared with task queue pair, so KERNEL drivers need
5032          * support multiple interrupt vectors.
5033          */
5034         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5035             !rte_intr_cap_multiple(intr_handle))
5036                 return 0;
5037
5038         rte_intr_disable(intr_handle);
5039         intr_vector = hw->used_rx_queues;
5040         /* creates event fd for each intr vector when MSIX is used */
5041         if (rte_intr_efd_enable(intr_handle, intr_vector))
5042                 return -EINVAL;
5043
5044         if (intr_handle->intr_vec == NULL) {
5045                 intr_handle->intr_vec =
5046                         rte_zmalloc("intr_vec",
5047                                     hw->used_rx_queues * sizeof(int), 0);
5048                 if (intr_handle->intr_vec == NULL) {
5049                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5050                                         hw->used_rx_queues);
5051                         ret = -ENOMEM;
5052                         goto alloc_intr_vec_error;
5053                 }
5054         }
5055
5056         if (rte_intr_allow_others(intr_handle)) {
5057                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5058                 base = RTE_INTR_VEC_RXTX_OFFSET;
5059         }
5060
5061         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5062                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5063                                                  HNS3_RING_TYPE_RX, q_id);
5064                 if (ret)
5065                         goto bind_vector_error;
5066                 intr_handle->intr_vec[q_id] = vec;
5067                 /*
5068                  * If there are not enough efds (e.g. not enough interrupt),
5069                  * remaining queues will be bond to the last interrupt.
5070                  */
5071                 if (vec < base + intr_handle->nb_efd - 1)
5072                         vec++;
5073         }
5074         rte_intr_enable(intr_handle);
5075         return 0;
5076
5077 bind_vector_error:
5078         rte_free(intr_handle->intr_vec);
5079         intr_handle->intr_vec = NULL;
5080 alloc_intr_vec_error:
5081         rte_intr_efd_disable(intr_handle);
5082         return ret;
5083 }
5084
5085 static int
5086 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5087 {
5088         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5089         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5090         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5091         uint16_t q_id;
5092         int ret;
5093
5094         if (dev->data->dev_conf.intr_conf.rxq == 0)
5095                 return 0;
5096
5097         if (rte_intr_dp_is_en(intr_handle)) {
5098                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5099                         ret = hns3_bind_ring_with_vector(hw,
5100                                         intr_handle->intr_vec[q_id], true,
5101                                         HNS3_RING_TYPE_RX, q_id);
5102                         if (ret)
5103                                 return ret;
5104                 }
5105         }
5106
5107         return 0;
5108 }
5109
5110 static void
5111 hns3_restore_filter(struct rte_eth_dev *dev)
5112 {
5113         hns3_restore_rss_filter(dev);
5114 }
5115
5116 static int
5117 hns3_dev_start(struct rte_eth_dev *dev)
5118 {
5119         struct hns3_adapter *hns = dev->data->dev_private;
5120         struct hns3_hw *hw = &hns->hw;
5121         int ret;
5122
5123         PMD_INIT_FUNC_TRACE();
5124         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5125                 return -EBUSY;
5126
5127         rte_spinlock_lock(&hw->lock);
5128         hw->adapter_state = HNS3_NIC_STARTING;
5129
5130         ret = hns3_do_start(hns, true);
5131         if (ret) {
5132                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5133                 rte_spinlock_unlock(&hw->lock);
5134                 return ret;
5135         }
5136         ret = hns3_map_rx_interrupt(dev);
5137         if (ret)
5138                 goto map_rx_inter_err;
5139
5140         /*
5141          * There are three register used to control the status of a TQP
5142          * (contains a pair of Tx queue and Rx queue) in the new version network
5143          * engine. One is used to control the enabling of Tx queue, the other is
5144          * used to control the enabling of Rx queue, and the last is the master
5145          * switch used to control the enabling of the tqp. The Tx register and
5146          * TQP register must be enabled at the same time to enable a Tx queue.
5147          * The same applies to the Rx queue. For the older network engine, this
5148          * function only refresh the enabled flag, and it is used to update the
5149          * status of queue in the dpdk framework.
5150          */
5151         ret = hns3_start_all_txqs(dev);
5152         if (ret)
5153                 goto map_rx_inter_err;
5154
5155         ret = hns3_start_all_rxqs(dev);
5156         if (ret)
5157                 goto start_all_rxqs_fail;
5158
5159         hw->adapter_state = HNS3_NIC_STARTED;
5160         rte_spinlock_unlock(&hw->lock);
5161
5162         hns3_rx_scattered_calc(dev);
5163         hns3_set_rxtx_function(dev);
5164         hns3_mp_req_start_rxtx(dev);
5165         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5166
5167         hns3_restore_filter(dev);
5168
5169         /* Enable interrupt of all rx queues before enabling queues */
5170         hns3_dev_all_rx_queue_intr_enable(hw, true);
5171
5172         /*
5173          * After finished the initialization, enable tqps to receive/transmit
5174          * packets and refresh all queue status.
5175          */
5176         hns3_start_tqps(hw);
5177
5178         hns3_tm_dev_start_proc(hw);
5179
5180         hns3_info(hw, "hns3 dev start successful!");
5181
5182         return 0;
5183
5184 start_all_rxqs_fail:
5185         hns3_stop_all_txqs(dev);
5186 map_rx_inter_err:
5187         (void)hns3_do_stop(hns);
5188         hw->adapter_state = HNS3_NIC_CONFIGURED;
5189         rte_spinlock_unlock(&hw->lock);
5190
5191         return ret;
5192 }
5193
5194 static int
5195 hns3_do_stop(struct hns3_adapter *hns)
5196 {
5197         struct hns3_hw *hw = &hns->hw;
5198         int ret;
5199
5200         /*
5201          * The "hns3_do_stop" function will also be called by .stop_service to
5202          * prepare reset. At the time of global or IMP reset, the command cannot
5203          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5204          * accessed during the reset process. So the mbuf can not be released
5205          * during reset and is required to be released after the reset is
5206          * completed.
5207          */
5208         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5209                 hns3_dev_release_mbufs(hns);
5210
5211         ret = hns3_cfg_mac_mode(hw, false);
5212         if (ret)
5213                 return ret;
5214         hw->mac.link_status = ETH_LINK_DOWN;
5215
5216         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5217                 hns3_configure_all_mac_addr(hns, true);
5218                 ret = hns3_reset_all_tqps(hns);
5219                 if (ret) {
5220                         hns3_err(hw, "failed to reset all queues ret = %d.",
5221                                  ret);
5222                         return ret;
5223                 }
5224         }
5225         hw->mac.default_addr_setted = false;
5226         return 0;
5227 }
5228
5229 static void
5230 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5231 {
5232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5233         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5234         struct hns3_adapter *hns = dev->data->dev_private;
5235         struct hns3_hw *hw = &hns->hw;
5236         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5237         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5238         uint16_t q_id;
5239
5240         if (dev->data->dev_conf.intr_conf.rxq == 0)
5241                 return;
5242
5243         /* unmap the ring with vector */
5244         if (rte_intr_allow_others(intr_handle)) {
5245                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5246                 base = RTE_INTR_VEC_RXTX_OFFSET;
5247         }
5248         if (rte_intr_dp_is_en(intr_handle)) {
5249                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5250                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5251                                                          HNS3_RING_TYPE_RX,
5252                                                          q_id);
5253                         if (vec < base + intr_handle->nb_efd - 1)
5254                                 vec++;
5255                 }
5256         }
5257         /* Clean datapath event and queue/vec mapping */
5258         rte_intr_efd_disable(intr_handle);
5259         if (intr_handle->intr_vec) {
5260                 rte_free(intr_handle->intr_vec);
5261                 intr_handle->intr_vec = NULL;
5262         }
5263 }
5264
5265 static int
5266 hns3_dev_stop(struct rte_eth_dev *dev)
5267 {
5268         struct hns3_adapter *hns = dev->data->dev_private;
5269         struct hns3_hw *hw = &hns->hw;
5270
5271         PMD_INIT_FUNC_TRACE();
5272         dev->data->dev_started = 0;
5273
5274         hw->adapter_state = HNS3_NIC_STOPPING;
5275         hns3_set_rxtx_function(dev);
5276         rte_wmb();
5277         /* Disable datapath on secondary process. */
5278         hns3_mp_req_stop_rxtx(dev);
5279         /* Prevent crashes when queues are still in use. */
5280         rte_delay_ms(hw->tqps_num);
5281
5282         rte_spinlock_lock(&hw->lock);
5283         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5284                 hns3_tm_dev_stop_proc(hw);
5285                 hns3_stop_tqps(hw);
5286                 hns3_do_stop(hns);
5287                 hns3_unmap_rx_interrupt(dev);
5288                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5289         }
5290         hns3_rx_scattered_reset(dev);
5291         rte_eal_alarm_cancel(hns3_service_handler, dev);
5292         rte_spinlock_unlock(&hw->lock);
5293
5294         return 0;
5295 }
5296
5297 static int
5298 hns3_dev_close(struct rte_eth_dev *eth_dev)
5299 {
5300         struct hns3_adapter *hns = eth_dev->data->dev_private;
5301         struct hns3_hw *hw = &hns->hw;
5302         int ret = 0;
5303
5304         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5305                 rte_free(eth_dev->process_private);
5306                 eth_dev->process_private = NULL;
5307                 return 0;
5308         }
5309
5310         if (hw->adapter_state == HNS3_NIC_STARTED)
5311                 ret = hns3_dev_stop(eth_dev);
5312
5313         hw->adapter_state = HNS3_NIC_CLOSING;
5314         hns3_reset_abort(hns);
5315         hw->adapter_state = HNS3_NIC_CLOSED;
5316
5317         hns3_configure_all_mc_mac_addr(hns, true);
5318         hns3_remove_all_vlan_table(hns);
5319         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5320         hns3_uninit_pf(eth_dev);
5321         hns3_free_all_queues(eth_dev);
5322         rte_free(hw->reset.wait_data);
5323         rte_free(eth_dev->process_private);
5324         eth_dev->process_private = NULL;
5325         hns3_mp_uninit_primary();
5326         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5327
5328         return ret;
5329 }
5330
5331 static int
5332 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5333 {
5334         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5336
5337         fc_conf->pause_time = pf->pause_time;
5338
5339         /* return fc current mode */
5340         switch (hw->current_mode) {
5341         case HNS3_FC_FULL:
5342                 fc_conf->mode = RTE_FC_FULL;
5343                 break;
5344         case HNS3_FC_TX_PAUSE:
5345                 fc_conf->mode = RTE_FC_TX_PAUSE;
5346                 break;
5347         case HNS3_FC_RX_PAUSE:
5348                 fc_conf->mode = RTE_FC_RX_PAUSE;
5349                 break;
5350         case HNS3_FC_NONE:
5351         default:
5352                 fc_conf->mode = RTE_FC_NONE;
5353                 break;
5354         }
5355
5356         return 0;
5357 }
5358
5359 static void
5360 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
5361 {
5362         switch (mode) {
5363         case RTE_FC_NONE:
5364                 hw->requested_mode = HNS3_FC_NONE;
5365                 break;
5366         case RTE_FC_RX_PAUSE:
5367                 hw->requested_mode = HNS3_FC_RX_PAUSE;
5368                 break;
5369         case RTE_FC_TX_PAUSE:
5370                 hw->requested_mode = HNS3_FC_TX_PAUSE;
5371                 break;
5372         case RTE_FC_FULL:
5373                 hw->requested_mode = HNS3_FC_FULL;
5374                 break;
5375         default:
5376                 hw->requested_mode = HNS3_FC_NONE;
5377                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
5378                           "configured to RTE_FC_NONE", mode);
5379                 break;
5380         }
5381 }
5382
5383 static int
5384 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5385 {
5386         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5387         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5388         int ret;
5389
5390         if (fc_conf->high_water || fc_conf->low_water ||
5391             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5392                 hns3_err(hw, "Unsupported flow control settings specified, "
5393                          "high_water(%u), low_water(%u), send_xon(%u) and "
5394                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5395                          fc_conf->high_water, fc_conf->low_water,
5396                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5397                 return -EINVAL;
5398         }
5399         if (fc_conf->autoneg) {
5400                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5401                 return -EINVAL;
5402         }
5403         if (!fc_conf->pause_time) {
5404                 hns3_err(hw, "Invalid pause time %u setting.",
5405                          fc_conf->pause_time);
5406                 return -EINVAL;
5407         }
5408
5409         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5410             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5411                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5412                          "current_fc_status = %d", hw->current_fc_status);
5413                 return -EOPNOTSUPP;
5414         }
5415
5416         hns3_get_fc_mode(hw, fc_conf->mode);
5417         if (hw->requested_mode == hw->current_mode &&
5418             pf->pause_time == fc_conf->pause_time)
5419                 return 0;
5420
5421         rte_spinlock_lock(&hw->lock);
5422         ret = hns3_fc_enable(dev, fc_conf);
5423         rte_spinlock_unlock(&hw->lock);
5424
5425         return ret;
5426 }
5427
5428 static int
5429 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5430                             struct rte_eth_pfc_conf *pfc_conf)
5431 {
5432         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5433         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5434         uint8_t priority;
5435         int ret;
5436
5437         if (!hns3_dev_dcb_supported(hw)) {
5438                 hns3_err(hw, "This port does not support dcb configurations.");
5439                 return -EOPNOTSUPP;
5440         }
5441
5442         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5443             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5444                 hns3_err(hw, "Unsupported flow control settings specified, "
5445                          "high_water(%u), low_water(%u), send_xon(%u) and "
5446                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5447                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5448                          pfc_conf->fc.send_xon,
5449                          pfc_conf->fc.mac_ctrl_frame_fwd);
5450                 return -EINVAL;
5451         }
5452         if (pfc_conf->fc.autoneg) {
5453                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5454                 return -EINVAL;
5455         }
5456         if (pfc_conf->fc.pause_time == 0) {
5457                 hns3_err(hw, "Invalid pause time %u setting.",
5458                          pfc_conf->fc.pause_time);
5459                 return -EINVAL;
5460         }
5461
5462         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5463             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5464                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5465                              "current_fc_status = %d", hw->current_fc_status);
5466                 return -EOPNOTSUPP;
5467         }
5468
5469         priority = pfc_conf->priority;
5470         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
5471         if (hw->dcb_info.pfc_en & BIT(priority) &&
5472             hw->requested_mode == hw->current_mode &&
5473             pfc_conf->fc.pause_time == pf->pause_time)
5474                 return 0;
5475
5476         rte_spinlock_lock(&hw->lock);
5477         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5478         rte_spinlock_unlock(&hw->lock);
5479
5480         return ret;
5481 }
5482
5483 static int
5484 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5485 {
5486         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5487         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5488         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5489         int i;
5490
5491         rte_spinlock_lock(&hw->lock);
5492         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
5493                 dcb_info->nb_tcs = pf->local_max_tc;
5494         else
5495                 dcb_info->nb_tcs = 1;
5496
5497         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5498                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5499         for (i = 0; i < dcb_info->nb_tcs; i++)
5500                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5501
5502         for (i = 0; i < hw->num_tc; i++) {
5503                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5504                 dcb_info->tc_queue.tc_txq[0][i].base =
5505                                                 hw->tc_queue[i].tqp_offset;
5506                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5507                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5508                                                 hw->tc_queue[i].tqp_count;
5509         }
5510         rte_spinlock_unlock(&hw->lock);
5511
5512         return 0;
5513 }
5514
5515 static int
5516 hns3_reinit_dev(struct hns3_adapter *hns)
5517 {
5518         struct hns3_hw *hw = &hns->hw;
5519         int ret;
5520
5521         ret = hns3_cmd_init(hw);
5522         if (ret) {
5523                 hns3_err(hw, "Failed to init cmd: %d", ret);
5524                 return ret;
5525         }
5526
5527         ret = hns3_reset_all_tqps(hns);
5528         if (ret) {
5529                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5530                 return ret;
5531         }
5532
5533         ret = hns3_init_hardware(hns);
5534         if (ret) {
5535                 hns3_err(hw, "Failed to init hardware: %d", ret);
5536                 return ret;
5537         }
5538
5539         ret = hns3_enable_hw_error_intr(hns, true);
5540         if (ret) {
5541                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5542                              ret);
5543                 return ret;
5544         }
5545         hns3_info(hw, "Reset done, driver initialization finished.");
5546
5547         return 0;
5548 }
5549
5550 static bool
5551 is_pf_reset_done(struct hns3_hw *hw)
5552 {
5553         uint32_t val, reg, reg_bit;
5554
5555         switch (hw->reset.level) {
5556         case HNS3_IMP_RESET:
5557                 reg = HNS3_GLOBAL_RESET_REG;
5558                 reg_bit = HNS3_IMP_RESET_BIT;
5559                 break;
5560         case HNS3_GLOBAL_RESET:
5561                 reg = HNS3_GLOBAL_RESET_REG;
5562                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5563                 break;
5564         case HNS3_FUNC_RESET:
5565                 reg = HNS3_FUN_RST_ING;
5566                 reg_bit = HNS3_FUN_RST_ING_B;
5567                 break;
5568         case HNS3_FLR_RESET:
5569         default:
5570                 hns3_err(hw, "Wait for unsupported reset level: %d",
5571                          hw->reset.level);
5572                 return true;
5573         }
5574         val = hns3_read_dev(hw, reg);
5575         if (hns3_get_bit(val, reg_bit))
5576                 return false;
5577         else
5578                 return true;
5579 }
5580
5581 bool
5582 hns3_is_reset_pending(struct hns3_adapter *hns)
5583 {
5584         struct hns3_hw *hw = &hns->hw;
5585         enum hns3_reset_level reset;
5586
5587         hns3_check_event_cause(hns, NULL);
5588         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5589         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5590                 hns3_warn(hw, "High level reset %d is pending", reset);
5591                 return true;
5592         }
5593         reset = hns3_get_reset_level(hns, &hw->reset.request);
5594         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
5595                 hns3_warn(hw, "High level reset %d is request", reset);
5596                 return true;
5597         }
5598         return false;
5599 }
5600
5601 static int
5602 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5603 {
5604         struct hns3_hw *hw = &hns->hw;
5605         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5606         struct timeval tv;
5607
5608         if (wait_data->result == HNS3_WAIT_SUCCESS)
5609                 return 0;
5610         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5611                 gettimeofday(&tv, NULL);
5612                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5613                           tv.tv_sec, tv.tv_usec);
5614                 return -ETIME;
5615         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5616                 return -EAGAIN;
5617
5618         wait_data->hns = hns;
5619         wait_data->check_completion = is_pf_reset_done;
5620         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5621                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
5622         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5623         wait_data->count = HNS3_RESET_WAIT_CNT;
5624         wait_data->result = HNS3_WAIT_REQUEST;
5625         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5626         return -EAGAIN;
5627 }
5628
5629 static int
5630 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5631 {
5632         struct hns3_cmd_desc desc;
5633         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5634
5635         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5636         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5637         req->fun_reset_vfid = func_id;
5638
5639         return hns3_cmd_send(hw, &desc, 1);
5640 }
5641
5642 static int
5643 hns3_imp_reset_cmd(struct hns3_hw *hw)
5644 {
5645         struct hns3_cmd_desc desc;
5646
5647         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5648         desc.data[0] = 0xeedd;
5649
5650         return hns3_cmd_send(hw, &desc, 1);
5651 }
5652
5653 static void
5654 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5655 {
5656         struct hns3_hw *hw = &hns->hw;
5657         struct timeval tv;
5658         uint32_t val;
5659
5660         gettimeofday(&tv, NULL);
5661         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5662             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5663                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5664                           tv.tv_sec, tv.tv_usec);
5665                 return;
5666         }
5667
5668         switch (reset_level) {
5669         case HNS3_IMP_RESET:
5670                 hns3_imp_reset_cmd(hw);
5671                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5672                           tv.tv_sec, tv.tv_usec);
5673                 break;
5674         case HNS3_GLOBAL_RESET:
5675                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5676                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5677                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5678                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5679                           tv.tv_sec, tv.tv_usec);
5680                 break;
5681         case HNS3_FUNC_RESET:
5682                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5683                           tv.tv_sec, tv.tv_usec);
5684                 /* schedule again to check later */
5685                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5686                 hns3_schedule_reset(hns);
5687                 break;
5688         default:
5689                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5690                 return;
5691         }
5692         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5693 }
5694
5695 static enum hns3_reset_level
5696 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5697 {
5698         struct hns3_hw *hw = &hns->hw;
5699         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5700
5701         /* Return the highest priority reset level amongst all */
5702         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5703                 reset_level = HNS3_IMP_RESET;
5704         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5705                 reset_level = HNS3_GLOBAL_RESET;
5706         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5707                 reset_level = HNS3_FUNC_RESET;
5708         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5709                 reset_level = HNS3_FLR_RESET;
5710
5711         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5712                 return HNS3_NONE_RESET;
5713
5714         return reset_level;
5715 }
5716
5717 static void
5718 hns3_record_imp_error(struct hns3_adapter *hns)
5719 {
5720         struct hns3_hw *hw = &hns->hw;
5721         uint32_t reg_val;
5722
5723         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5724         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5725                 hns3_warn(hw, "Detected IMP RD poison!");
5726                 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS");
5727                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5728                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5729         }
5730
5731         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5732                 hns3_warn(hw, "Detected IMP CMDQ error!");
5733                 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS");
5734                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5735                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5736         }
5737 }
5738
5739 static int
5740 hns3_prepare_reset(struct hns3_adapter *hns)
5741 {
5742         struct hns3_hw *hw = &hns->hw;
5743         uint32_t reg_val;
5744         int ret;
5745
5746         switch (hw->reset.level) {
5747         case HNS3_FUNC_RESET:
5748                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5749                 if (ret)
5750                         return ret;
5751
5752                 /*
5753                  * After performaning pf reset, it is not necessary to do the
5754                  * mailbox handling or send any command to firmware, because
5755                  * any mailbox handling or command to firmware is only valid
5756                  * after hns3_cmd_init is called.
5757                  */
5758                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5759                 hw->reset.stats.request_cnt++;
5760                 break;
5761         case HNS3_IMP_RESET:
5762                 hns3_record_imp_error(hns);
5763                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5764                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5765                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5766                 break;
5767         default:
5768                 break;
5769         }
5770         return 0;
5771 }
5772
5773 static int
5774 hns3_set_rst_done(struct hns3_hw *hw)
5775 {
5776         struct hns3_pf_rst_done_cmd *req;
5777         struct hns3_cmd_desc desc;
5778
5779         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5780         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5781         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5782         return hns3_cmd_send(hw, &desc, 1);
5783 }
5784
5785 static int
5786 hns3_stop_service(struct hns3_adapter *hns)
5787 {
5788         struct hns3_hw *hw = &hns->hw;
5789         struct rte_eth_dev *eth_dev;
5790
5791         eth_dev = &rte_eth_devices[hw->data->port_id];
5792         if (hw->adapter_state == HNS3_NIC_STARTED) {
5793                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5794                 hns3_update_link_status_and_event(hw);
5795         }
5796         hw->mac.link_status = ETH_LINK_DOWN;
5797
5798         hns3_set_rxtx_function(eth_dev);
5799         rte_wmb();
5800         /* Disable datapath on secondary process. */
5801         hns3_mp_req_stop_rxtx(eth_dev);
5802         rte_delay_ms(hw->tqps_num);
5803
5804         rte_spinlock_lock(&hw->lock);
5805         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5806             hw->adapter_state == HNS3_NIC_STOPPING) {
5807                 hns3_enable_all_queues(hw, false);
5808                 hns3_do_stop(hns);
5809                 hw->reset.mbuf_deferred_free = true;
5810         } else
5811                 hw->reset.mbuf_deferred_free = false;
5812
5813         /*
5814          * It is cumbersome for hardware to pick-and-choose entries for deletion
5815          * from table space. Hence, for function reset software intervention is
5816          * required to delete the entries
5817          */
5818         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5819                 hns3_configure_all_mc_mac_addr(hns, true);
5820         rte_spinlock_unlock(&hw->lock);
5821
5822         return 0;
5823 }
5824
5825 static int
5826 hns3_start_service(struct hns3_adapter *hns)
5827 {
5828         struct hns3_hw *hw = &hns->hw;
5829         struct rte_eth_dev *eth_dev;
5830
5831         if (hw->reset.level == HNS3_IMP_RESET ||
5832             hw->reset.level == HNS3_GLOBAL_RESET)
5833                 hns3_set_rst_done(hw);
5834         eth_dev = &rte_eth_devices[hw->data->port_id];
5835         hns3_set_rxtx_function(eth_dev);
5836         hns3_mp_req_start_rxtx(eth_dev);
5837         if (hw->adapter_state == HNS3_NIC_STARTED) {
5838                 /*
5839                  * This API parent function already hold the hns3_hw.lock, the
5840                  * hns3_service_handler may report lse, in bonding application
5841                  * it will call driver's ops which may acquire the hns3_hw.lock
5842                  * again, thus lead to deadlock.
5843                  * We defer calls hns3_service_handler to avoid the deadlock.
5844                  */
5845                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5846                                   hns3_service_handler, eth_dev);
5847
5848                 /* Enable interrupt of all rx queues before enabling queues */
5849                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5850                 /*
5851                  * Enable state of each rxq and txq will be recovered after
5852                  * reset, so we need to restore them before enable all tqps;
5853                  */
5854                 hns3_restore_tqp_enable_state(hw);
5855                 /*
5856                  * When finished the initialization, enable queues to receive
5857                  * and transmit packets.
5858                  */
5859                 hns3_enable_all_queues(hw, true);
5860         }
5861
5862         return 0;
5863 }
5864
5865 static int
5866 hns3_restore_conf(struct hns3_adapter *hns)
5867 {
5868         struct hns3_hw *hw = &hns->hw;
5869         int ret;
5870
5871         ret = hns3_configure_all_mac_addr(hns, false);
5872         if (ret)
5873                 return ret;
5874
5875         ret = hns3_configure_all_mc_mac_addr(hns, false);
5876         if (ret)
5877                 goto err_mc_mac;
5878
5879         ret = hns3_dev_promisc_restore(hns);
5880         if (ret)
5881                 goto err_promisc;
5882
5883         ret = hns3_restore_vlan_table(hns);
5884         if (ret)
5885                 goto err_promisc;
5886
5887         ret = hns3_restore_vlan_conf(hns);
5888         if (ret)
5889                 goto err_promisc;
5890
5891         ret = hns3_restore_all_fdir_filter(hns);
5892         if (ret)
5893                 goto err_promisc;
5894
5895         ret = hns3_restore_rx_interrupt(hw);
5896         if (ret)
5897                 goto err_promisc;
5898
5899         ret = hns3_restore_gro_conf(hw);
5900         if (ret)
5901                 goto err_promisc;
5902
5903         ret = hns3_restore_fec(hw);
5904         if (ret)
5905                 goto err_promisc;
5906
5907         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5908                 ret = hns3_do_start(hns, false);
5909                 if (ret)
5910                         goto err_promisc;
5911                 hns3_info(hw, "hns3 dev restart successful!");
5912         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5913                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5914         return 0;
5915
5916 err_promisc:
5917         hns3_configure_all_mc_mac_addr(hns, true);
5918 err_mc_mac:
5919         hns3_configure_all_mac_addr(hns, true);
5920         return ret;
5921 }
5922
5923 static void
5924 hns3_reset_service(void *param)
5925 {
5926         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5927         struct hns3_hw *hw = &hns->hw;
5928         enum hns3_reset_level reset_level;
5929         struct timeval tv_delta;
5930         struct timeval tv_start;
5931         struct timeval tv;
5932         uint64_t msec;
5933         int ret;
5934
5935         /*
5936          * The interrupt is not triggered within the delay time.
5937          * The interrupt may have been lost. It is necessary to handle
5938          * the interrupt to recover from the error.
5939          */
5940         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
5941                             SCHEDULE_DEFERRED) {
5942                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
5943                                   __ATOMIC_RELAXED);
5944                 hns3_err(hw, "Handling interrupts in delayed tasks");
5945                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5946                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5947                 if (reset_level == HNS3_NONE_RESET) {
5948                         hns3_err(hw, "No reset level is set, try IMP reset");
5949                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5950                 }
5951         }
5952         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
5953
5954         /*
5955          * Check if there is any ongoing reset in the hardware. This status can
5956          * be checked from reset_pending. If there is then, we need to wait for
5957          * hardware to complete reset.
5958          *    a. If we are able to figure out in reasonable time that hardware
5959          *       has fully resetted then, we can proceed with driver, client
5960          *       reset.
5961          *    b. else, we can come back later to check this status so re-sched
5962          *       now.
5963          */
5964         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5965         if (reset_level != HNS3_NONE_RESET) {
5966                 gettimeofday(&tv_start, NULL);
5967                 ret = hns3_reset_process(hns, reset_level);
5968                 gettimeofday(&tv, NULL);
5969                 timersub(&tv, &tv_start, &tv_delta);
5970                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5971                        tv_delta.tv_usec / USEC_PER_MSEC;
5972                 if (msec > HNS3_RESET_PROCESS_MS)
5973                         hns3_err(hw, "%d handle long time delta %" PRIx64
5974                                      " ms time=%ld.%.6ld",
5975                                  hw->reset.level, msec,
5976                                  tv.tv_sec, tv.tv_usec);
5977                 if (ret == -EAGAIN)
5978                         return;
5979         }
5980
5981         /* Check if we got any *new* reset requests to be honored */
5982         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5983         if (reset_level != HNS3_NONE_RESET)
5984                 hns3_msix_process(hns, reset_level);
5985 }
5986
5987 static unsigned int
5988 hns3_get_speed_capa_num(uint16_t device_id)
5989 {
5990         unsigned int num;
5991
5992         switch (device_id) {
5993         case HNS3_DEV_ID_25GE:
5994         case HNS3_DEV_ID_25GE_RDMA:
5995                 num = 2;
5996                 break;
5997         case HNS3_DEV_ID_100G_RDMA_MACSEC:
5998         case HNS3_DEV_ID_200G_RDMA:
5999                 num = 1;
6000                 break;
6001         default:
6002                 num = 0;
6003                 break;
6004         }
6005
6006         return num;
6007 }
6008
6009 static int
6010 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6011                         uint16_t device_id)
6012 {
6013         switch (device_id) {
6014         case HNS3_DEV_ID_25GE:
6015         /* fallthrough */
6016         case HNS3_DEV_ID_25GE_RDMA:
6017                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6018                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6019
6020                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6021                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6022                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6023                 break;
6024         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6025                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6026                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6027                 break;
6028         case HNS3_DEV_ID_200G_RDMA:
6029                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6030                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6031                 break;
6032         default:
6033                 return -ENOTSUP;
6034         }
6035
6036         return 0;
6037 }
6038
6039 static int
6040 hns3_fec_get_capability(struct rte_eth_dev *dev,
6041                         struct rte_eth_fec_capa *speed_fec_capa,
6042                         unsigned int num)
6043 {
6044         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6045         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6046         uint16_t device_id = pci_dev->id.device_id;
6047         unsigned int capa_num;
6048         int ret;
6049
6050         capa_num = hns3_get_speed_capa_num(device_id);
6051         if (capa_num == 0) {
6052                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6053                          device_id);
6054                 return -ENOTSUP;
6055         }
6056
6057         if (speed_fec_capa == NULL || num < capa_num)
6058                 return capa_num;
6059
6060         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6061         if (ret)
6062                 return -ENOTSUP;
6063
6064         return capa_num;
6065 }
6066
6067 static int
6068 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6069 {
6070         struct hns3_config_fec_cmd *req;
6071         struct hns3_cmd_desc desc;
6072         int ret;
6073
6074         /*
6075          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6076          * in device of link speed
6077          * below 10 Gbps.
6078          */
6079         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6080                 *state = 0;
6081                 return 0;
6082         }
6083
6084         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6085         req = (struct hns3_config_fec_cmd *)desc.data;
6086         ret = hns3_cmd_send(hw, &desc, 1);
6087         if (ret) {
6088                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6089                          ret);
6090                 return ret;
6091         }
6092
6093         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6094         return 0;
6095 }
6096
6097 static int
6098 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6099 {
6100 #define QUERY_ACTIVE_SPEED      1
6101         struct hns3_sfp_speed_cmd *resp;
6102         uint32_t tmp_fec_capa;
6103         uint8_t auto_state;
6104         struct hns3_cmd_desc desc;
6105         int ret;
6106
6107         /*
6108          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6109          * configured FEC mode is returned.
6110          * If link is up, current FEC mode is returned.
6111          */
6112         if (hw->mac.link_status == ETH_LINK_DOWN) {
6113                 ret = get_current_fec_auto_state(hw, &auto_state);
6114                 if (ret)
6115                         return ret;
6116
6117                 if (auto_state == 0x1) {
6118                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6119                         return 0;
6120                 }
6121         }
6122
6123         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
6124         resp = (struct hns3_sfp_speed_cmd *)desc.data;
6125         resp->query_type = QUERY_ACTIVE_SPEED;
6126
6127         ret = hns3_cmd_send(hw, &desc, 1);
6128         if (ret == -EOPNOTSUPP) {
6129                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6130                 return ret;
6131         } else if (ret) {
6132                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6133                 return ret;
6134         }
6135
6136         /*
6137          * FEC mode order defined in hns3 hardware is inconsistend with
6138          * that defined in the ethdev library. So the sequence needs
6139          * to be converted.
6140          */
6141         switch (resp->active_fec) {
6142         case HNS3_HW_FEC_MODE_NOFEC:
6143                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6144                 break;
6145         case HNS3_HW_FEC_MODE_BASER:
6146                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6147                 break;
6148         case HNS3_HW_FEC_MODE_RS:
6149                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6150                 break;
6151         default:
6152                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6153                 break;
6154         }
6155
6156         *fec_capa = tmp_fec_capa;
6157         return 0;
6158 }
6159
6160 static int
6161 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6162 {
6163         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6164
6165         return hns3_fec_get_internal(hw, fec_capa);
6166 }
6167
6168 static int
6169 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6170 {
6171         struct hns3_config_fec_cmd *req;
6172         struct hns3_cmd_desc desc;
6173         int ret;
6174
6175         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6176
6177         req = (struct hns3_config_fec_cmd *)desc.data;
6178         switch (mode) {
6179         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6180                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6181                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6182                 break;
6183         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6184                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6185                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6186                 break;
6187         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6188                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6189                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6190                 break;
6191         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6192                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6193                 break;
6194         default:
6195                 return 0;
6196         }
6197         ret = hns3_cmd_send(hw, &desc, 1);
6198         if (ret)
6199                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6200
6201         return ret;
6202 }
6203
6204 static uint32_t
6205 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6206 {
6207         struct hns3_mac *mac = &hw->mac;
6208         uint32_t cur_capa;
6209
6210         switch (mac->link_speed) {
6211         case ETH_SPEED_NUM_10G:
6212                 cur_capa = fec_capa[1].capa;
6213                 break;
6214         case ETH_SPEED_NUM_25G:
6215         case ETH_SPEED_NUM_100G:
6216         case ETH_SPEED_NUM_200G:
6217                 cur_capa = fec_capa[0].capa;
6218                 break;
6219         default:
6220                 cur_capa = 0;
6221                 break;
6222         }
6223
6224         return cur_capa;
6225 }
6226
6227 static bool
6228 is_fec_mode_one_bit_set(uint32_t mode)
6229 {
6230         int cnt = 0;
6231         uint8_t i;
6232
6233         for (i = 0; i < sizeof(mode); i++)
6234                 if (mode >> i & 0x1)
6235                         cnt++;
6236
6237         return cnt == 1 ? true : false;
6238 }
6239
6240 static int
6241 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6242 {
6243 #define FEC_CAPA_NUM 2
6244         struct hns3_adapter *hns = dev->data->dev_private;
6245         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6246         struct hns3_pf *pf = &hns->pf;
6247
6248         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6249         uint32_t cur_capa;
6250         uint32_t num = FEC_CAPA_NUM;
6251         int ret;
6252
6253         ret = hns3_fec_get_capability(dev, fec_capa, num);
6254         if (ret < 0)
6255                 return ret;
6256
6257         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6258         if (!is_fec_mode_one_bit_set(mode))
6259                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6260                              "FEC mode should be only one bit set", mode);
6261
6262         /*
6263          * Check whether the configured mode is within the FEC capability.
6264          * If not, the configured mode will not be supported.
6265          */
6266         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6267         if (!(cur_capa & mode)) {
6268                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6269                 return -EINVAL;
6270         }
6271
6272         ret = hns3_set_fec_hw(hw, mode);
6273         if (ret)
6274                 return ret;
6275
6276         pf->fec_mode = mode;
6277         return 0;
6278 }
6279
6280 static int
6281 hns3_restore_fec(struct hns3_hw *hw)
6282 {
6283         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6284         struct hns3_pf *pf = &hns->pf;
6285         uint32_t mode = pf->fec_mode;
6286         int ret;
6287
6288         ret = hns3_set_fec_hw(hw, mode);
6289         if (ret)
6290                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6291                          mode, ret);
6292
6293         return ret;
6294 }
6295
6296 static int
6297 hns3_query_dev_fec_info(struct hns3_hw *hw)
6298 {
6299         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6300         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6301         int ret;
6302
6303         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6304         if (ret)
6305                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6306
6307         return ret;
6308 }
6309
6310 static bool
6311 hns3_optical_module_existed(struct hns3_hw *hw)
6312 {
6313         struct hns3_cmd_desc desc;
6314         bool existed;
6315         int ret;
6316
6317         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6318         ret = hns3_cmd_send(hw, &desc, 1);
6319         if (ret) {
6320                 hns3_err(hw,
6321                          "fail to get optical module exist state, ret = %d.\n",
6322                          ret);
6323                 return false;
6324         }
6325         existed = !!desc.data[0];
6326
6327         return existed;
6328 }
6329
6330 static int
6331 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6332                                 uint32_t len, uint8_t *data)
6333 {
6334 #define HNS3_SFP_INFO_CMD_NUM 6
6335 #define HNS3_SFP_INFO_MAX_LEN \
6336         (HNS3_SFP_INFO_BD0_LEN + \
6337         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6338         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6339         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6340         uint16_t read_len;
6341         uint16_t copy_len;
6342         int ret;
6343         int i;
6344
6345         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6346                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6347                                           true);
6348                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6349                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6350         }
6351
6352         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6353         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6354         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6355         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6356
6357         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6358         if (ret) {
6359                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6360                                 ret);
6361                 return ret;
6362         }
6363
6364         /* The data format in BD0 is different with the others. */
6365         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6366         memcpy(data, sfp_info_bd0->data, copy_len);
6367         read_len = copy_len;
6368
6369         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6370                 if (read_len >= len)
6371                         break;
6372
6373                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6374                 memcpy(data + read_len, desc[i].data, copy_len);
6375                 read_len += copy_len;
6376         }
6377
6378         return (int)read_len;
6379 }
6380
6381 static int
6382 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6383                        struct rte_dev_eeprom_info *info)
6384 {
6385         struct hns3_adapter *hns = dev->data->dev_private;
6386         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6387         uint32_t offset = info->offset;
6388         uint32_t len = info->length;
6389         uint8_t *data = info->data;
6390         uint32_t read_len = 0;
6391
6392         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6393                 return -ENOTSUP;
6394
6395         if (!hns3_optical_module_existed(hw)) {
6396                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6397                 return -EIO;
6398         }
6399
6400         while (read_len < len) {
6401                 int ret;
6402                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6403                                                   len - read_len,
6404                                                   data + read_len);
6405                 if (ret < 0)
6406                         return -EIO;
6407                 read_len += ret;
6408         }
6409
6410         return 0;
6411 }
6412
6413 static int
6414 hns3_get_module_info(struct rte_eth_dev *dev,
6415                      struct rte_eth_dev_module_info *modinfo)
6416 {
6417 #define HNS3_SFF8024_ID_SFP             0x03
6418 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6419 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6420 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6421 #define HNS3_SFF_8636_V1_3              0x03
6422         struct hns3_adapter *hns = dev->data->dev_private;
6423         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6424         struct rte_dev_eeprom_info info;
6425         struct hns3_sfp_type sfp_type;
6426         int ret;
6427
6428         memset(&sfp_type, 0, sizeof(sfp_type));
6429         memset(&info, 0, sizeof(info));
6430         info.data = (uint8_t *)&sfp_type;
6431         info.length = sizeof(sfp_type);
6432         ret = hns3_get_module_eeprom(dev, &info);
6433         if (ret)
6434                 return ret;
6435
6436         switch (sfp_type.type) {
6437         case HNS3_SFF8024_ID_SFP:
6438                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6439                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6440                 break;
6441         case HNS3_SFF8024_ID_QSFP_8438:
6442                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6443                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6444                 break;
6445         case HNS3_SFF8024_ID_QSFP_8436_8636:
6446                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6447                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6448                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6449                 } else {
6450                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6451                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6452                 }
6453                 break;
6454         case HNS3_SFF8024_ID_QSFP28_8636:
6455                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6456                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6457                 break;
6458         default:
6459                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6460                          sfp_type.type, sfp_type.ext_type);
6461                 return -EINVAL;
6462         }
6463
6464         return 0;
6465 }
6466
6467 static const struct eth_dev_ops hns3_eth_dev_ops = {
6468         .dev_configure      = hns3_dev_configure,
6469         .dev_start          = hns3_dev_start,
6470         .dev_stop           = hns3_dev_stop,
6471         .dev_close          = hns3_dev_close,
6472         .promiscuous_enable = hns3_dev_promiscuous_enable,
6473         .promiscuous_disable = hns3_dev_promiscuous_disable,
6474         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6475         .allmulticast_disable = hns3_dev_allmulticast_disable,
6476         .mtu_set            = hns3_dev_mtu_set,
6477         .stats_get          = hns3_stats_get,
6478         .stats_reset        = hns3_stats_reset,
6479         .xstats_get         = hns3_dev_xstats_get,
6480         .xstats_get_names   = hns3_dev_xstats_get_names,
6481         .xstats_reset       = hns3_dev_xstats_reset,
6482         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6483         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6484         .dev_infos_get          = hns3_dev_infos_get,
6485         .fw_version_get         = hns3_fw_version_get,
6486         .rx_queue_setup         = hns3_rx_queue_setup,
6487         .tx_queue_setup         = hns3_tx_queue_setup,
6488         .rx_queue_release       = hns3_dev_rx_queue_release,
6489         .tx_queue_release       = hns3_dev_tx_queue_release,
6490         .rx_queue_start         = hns3_dev_rx_queue_start,
6491         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6492         .tx_queue_start         = hns3_dev_tx_queue_start,
6493         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6494         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6495         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6496         .rxq_info_get           = hns3_rxq_info_get,
6497         .txq_info_get           = hns3_txq_info_get,
6498         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6499         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6500         .flow_ctrl_get          = hns3_flow_ctrl_get,
6501         .flow_ctrl_set          = hns3_flow_ctrl_set,
6502         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6503         .mac_addr_add           = hns3_add_mac_addr,
6504         .mac_addr_remove        = hns3_remove_mac_addr,
6505         .mac_addr_set           = hns3_set_default_mac_addr,
6506         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6507         .link_update            = hns3_dev_link_update,
6508         .rss_hash_update        = hns3_dev_rss_hash_update,
6509         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6510         .reta_update            = hns3_dev_rss_reta_update,
6511         .reta_query             = hns3_dev_rss_reta_query,
6512         .filter_ctrl            = hns3_dev_filter_ctrl,
6513         .vlan_filter_set        = hns3_vlan_filter_set,
6514         .vlan_tpid_set          = hns3_vlan_tpid_set,
6515         .vlan_offload_set       = hns3_vlan_offload_set,
6516         .vlan_pvid_set          = hns3_vlan_pvid_set,
6517         .get_reg                = hns3_get_regs,
6518         .get_module_info        = hns3_get_module_info,
6519         .get_module_eeprom      = hns3_get_module_eeprom,
6520         .get_dcb_info           = hns3_get_dcb_info,
6521         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6522         .fec_get_capability     = hns3_fec_get_capability,
6523         .fec_get                = hns3_fec_get,
6524         .fec_set                = hns3_fec_set,
6525         .tm_ops_get             = hns3_tm_ops_get,
6526         .tx_done_cleanup        = hns3_tx_done_cleanup,
6527 };
6528
6529 static const struct hns3_reset_ops hns3_reset_ops = {
6530         .reset_service       = hns3_reset_service,
6531         .stop_service        = hns3_stop_service,
6532         .prepare_reset       = hns3_prepare_reset,
6533         .wait_hardware_ready = hns3_wait_hardware_ready,
6534         .reinit_dev          = hns3_reinit_dev,
6535         .restore_conf        = hns3_restore_conf,
6536         .start_service       = hns3_start_service,
6537 };
6538
6539 static int
6540 hns3_dev_init(struct rte_eth_dev *eth_dev)
6541 {
6542         struct hns3_adapter *hns = eth_dev->data->dev_private;
6543         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6544         struct rte_ether_addr *eth_addr;
6545         struct hns3_hw *hw = &hns->hw;
6546         int ret;
6547
6548         PMD_INIT_FUNC_TRACE();
6549
6550         eth_dev->process_private = (struct hns3_process_private *)
6551             rte_zmalloc_socket("hns3_filter_list",
6552                                sizeof(struct hns3_process_private),
6553                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
6554         if (eth_dev->process_private == NULL) {
6555                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
6556                 return -ENOMEM;
6557         }
6558         /* initialize flow filter lists */
6559         hns3_filterlist_init(eth_dev);
6560
6561         hns3_set_rxtx_function(eth_dev);
6562         eth_dev->dev_ops = &hns3_eth_dev_ops;
6563         eth_dev->rx_queue_count = hns3_rx_queue_count;
6564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6565                 ret = hns3_mp_init_secondary();
6566                 if (ret) {
6567                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
6568                                      "process, ret = %d", ret);
6569                         goto err_mp_init_secondary;
6570                 }
6571
6572                 hw->secondary_cnt++;
6573                 return 0;
6574         }
6575
6576         ret = hns3_mp_init_primary();
6577         if (ret) {
6578                 PMD_INIT_LOG(ERR,
6579                              "Failed to init for primary process, ret = %d",
6580                              ret);
6581                 goto err_mp_init_primary;
6582         }
6583
6584         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6585         hns->is_vf = false;
6586         hw->data = eth_dev->data;
6587
6588         /*
6589          * Set default max packet size according to the mtu
6590          * default vale in DPDK frame.
6591          */
6592         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6593
6594         ret = hns3_reset_init(hw);
6595         if (ret)
6596                 goto err_init_reset;
6597         hw->reset.ops = &hns3_reset_ops;
6598
6599         ret = hns3_init_pf(eth_dev);
6600         if (ret) {
6601                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6602                 goto err_init_pf;
6603         }
6604
6605         /* Allocate memory for storing MAC addresses */
6606         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6607                                                sizeof(struct rte_ether_addr) *
6608                                                HNS3_UC_MACADDR_NUM, 0);
6609         if (eth_dev->data->mac_addrs == NULL) {
6610                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6611                              "to store MAC addresses",
6612                              sizeof(struct rte_ether_addr) *
6613                              HNS3_UC_MACADDR_NUM);
6614                 ret = -ENOMEM;
6615                 goto err_rte_zmalloc;
6616         }
6617
6618         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6619         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6620                 rte_eth_random_addr(hw->mac.mac_addr);
6621                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6622                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6623                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6624                           "unicast address, using random MAC address %s",
6625                           mac_str);
6626         }
6627         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6628                             &eth_dev->data->mac_addrs[0]);
6629
6630         hw->adapter_state = HNS3_NIC_INITIALIZED;
6631
6632         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6633                             SCHEDULE_PENDING) {
6634                 hns3_err(hw, "Reschedule reset service after dev_init");
6635                 hns3_schedule_reset(hns);
6636         } else {
6637                 /* IMP will wait ready flag before reset */
6638                 hns3_notify_reset_ready(hw, false);
6639         }
6640
6641         hns3_info(hw, "hns3 dev initialization successful!");
6642         return 0;
6643
6644 err_rte_zmalloc:
6645         hns3_uninit_pf(eth_dev);
6646
6647 err_init_pf:
6648         rte_free(hw->reset.wait_data);
6649
6650 err_init_reset:
6651         hns3_mp_uninit_primary();
6652
6653 err_mp_init_primary:
6654 err_mp_init_secondary:
6655         eth_dev->dev_ops = NULL;
6656         eth_dev->rx_pkt_burst = NULL;
6657         eth_dev->tx_pkt_burst = NULL;
6658         eth_dev->tx_pkt_prepare = NULL;
6659         rte_free(eth_dev->process_private);
6660         eth_dev->process_private = NULL;
6661         return ret;
6662 }
6663
6664 static int
6665 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6666 {
6667         struct hns3_adapter *hns = eth_dev->data->dev_private;
6668         struct hns3_hw *hw = &hns->hw;
6669
6670         PMD_INIT_FUNC_TRACE();
6671
6672         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6673                 rte_free(eth_dev->process_private);
6674                 eth_dev->process_private = NULL;
6675                 return 0;
6676         }
6677
6678         if (hw->adapter_state < HNS3_NIC_CLOSING)
6679                 hns3_dev_close(eth_dev);
6680
6681         hw->adapter_state = HNS3_NIC_REMOVED;
6682         return 0;
6683 }
6684
6685 static int
6686 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6687                    struct rte_pci_device *pci_dev)
6688 {
6689         return rte_eth_dev_pci_generic_probe(pci_dev,
6690                                              sizeof(struct hns3_adapter),
6691                                              hns3_dev_init);
6692 }
6693
6694 static int
6695 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6696 {
6697         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6698 }
6699
6700 static const struct rte_pci_id pci_id_hns3_map[] = {
6701         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6702         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6703         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6704         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6705         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6706         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6707         { .vendor_id = 0, }, /* sentinel */
6708 };
6709
6710 static struct rte_pci_driver rte_hns3_pmd = {
6711         .id_table = pci_id_hns3_map,
6712         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
6713         .probe = eth_hns3_pci_probe,
6714         .remove = eth_hns3_pci_remove,
6715 };
6716
6717 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6718 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6719 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6720 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
6721 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);