1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2019 Hisilicon Limited.
5 #ifndef _HNS3_ETHDEV_H_
6 #define _HNS3_ETHDEV_H_
14 #include "hns3_fdir.h"
15 #include "hns3_stats.h"
18 #define PCI_VENDOR_ID_HUAWEI 0x19e5
21 #define HNS3_DEV_ID_GE 0xA220
22 #define HNS3_DEV_ID_25GE 0xA221
23 #define HNS3_DEV_ID_25GE_RDMA 0xA222
24 #define HNS3_DEV_ID_50GE_RDMA 0xA224
25 #define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
26 #define HNS3_DEV_ID_200G_RDMA 0xA228
27 #define HNS3_DEV_ID_100G_VF 0xA22E
28 #define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
30 /* PCI Config offsets */
31 #define HNS3_PCI_REVISION_ID 0x08
32 #define HNS3_PCI_REVISION_ID_LEN 1
34 #define PCI_REVISION_ID_HIP08_B 0x21
35 #define PCI_REVISION_ID_HIP09_A 0x30
37 #define HNS3_PF_FUNC_ID 0
38 #define HNS3_1ST_VF_FUNC_ID 1
40 #define HNS3_UC_MACADDR_NUM 128
41 #define HNS3_VF_UC_MACADDR_NUM 48
42 #define HNS3_MC_MACADDR_NUM 128
44 #define HNS3_MAX_BD_SIZE 65535
45 #define HNS3_MAX_NON_TSO_BD_PER_PKT 8
46 #define HNS3_MAX_TSO_BD_PER_PKT 63
47 #define HNS3_MAX_FRAME_LEN 9728
48 #define HNS3_VLAN_TAG_SIZE 4
49 #define HNS3_DEFAULT_RX_BUF_LEN 2048
50 #define HNS3_MAX_BD_PAYLEN (1024 * 1024 - 1)
51 #define HNS3_MAX_TSO_HDR_SIZE 512
52 #define HNS3_MAX_TSO_HDR_BD_NUM 3
53 #define HNS3_MAX_LRO_SIZE 64512
55 #define HNS3_ETH_OVERHEAD \
56 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
57 #define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
58 #define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
59 #define HNS3_DEFAULT_MTU 1500UL
60 #define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
61 #define HNS3_HIP08_MIN_TX_PKT_LEN 33
62 #define HNS3_HIP09_MIN_TX_PKT_LEN 9
67 #define HNS3_MAX_PF_NUM 8
68 #define HNS3_UMV_TBL_SIZE 3072
69 #define HNS3_DEFAULT_UMV_SPACE_PER_PF \
70 (HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
72 #define HNS3_PF_CFG_BLOCK_SIZE 32
73 #define HNS3_PF_CFG_DESC_NUM \
74 (HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
76 #define HNS3_DEFAULT_ENABLE_PFC_NUM 0
78 #define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
79 #define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
81 #define HNS3_QUIT_RESET_CNT 10
82 #define HNS3_QUIT_RESET_DELAY_MS 100
84 #define HNS3_POLL_RESPONE_MS 1
86 #define HNS3_MAX_USER_PRIO 8
96 #define HNS3_SCH_MODE_SP 0
97 #define HNS3_SCH_MODE_DWRR 1
100 uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
103 uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
106 struct hns3_tc_info {
108 uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
111 uint8_t up_to_tc_map; /* user priority maping on the TC */
114 struct hns3_dcb_info {
116 uint8_t num_pg; /* It must be 1 if vNET-Base schd */
117 uint8_t pg_dwrr[HNS3_PG_NUM];
118 uint8_t prio_tc[HNS3_MAX_USER_PRIO];
119 struct hns3_pg_info pg_info[HNS3_PG_NUM];
120 struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
121 uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
122 uint8_t pfc_en; /* Pfc enabled or not for user priority */
125 enum hns3_fc_status {
127 HNS3_FC_STATUS_MAC_PAUSE,
131 struct hns3_tc_queue_info {
132 uint8_t tqp_offset; /* TQP offset from base TQP */
133 uint8_t tqp_count; /* Total TQPs */
134 uint8_t tc; /* TC index */
135 bool enable; /* If this TC is enable or not */
139 uint8_t vmdq_vport_num;
141 uint16_t tqp_desc_num;
143 uint16_t rss_size_max;
146 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
147 uint8_t default_speed;
148 uint32_t numa_node_map;
149 uint8_t speed_ability;
154 enum hns3_media_type {
155 HNS3_MEDIA_TYPE_UNKNOWN,
156 HNS3_MEDIA_TYPE_FIBER,
157 HNS3_MEDIA_TYPE_COPPER,
158 HNS3_MEDIA_TYPE_BACKPLANE,
159 HNS3_MEDIA_TYPE_NONE,
163 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
164 bool default_addr_setted; /* whether default addr(mac_addr) is setted */
167 uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
168 uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
169 uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
170 uint32_t link_speed; /* ETH_SPEED_NUM_ */
173 struct hns3_fake_queue_data {
174 void **rx_queues; /* Array of pointers to fake RX queues. */
175 void **tx_queues; /* Array of pointers to fake TX queues. */
176 uint16_t nb_fake_rx_queues; /* Number of fake RX queues. */
177 uint16_t nb_fake_tx_queues; /* Number of fake TX queues. */
180 #define HNS3_PORT_BASE_VLAN_DISABLE 0
181 #define HNS3_PORT_BASE_VLAN_ENABLE 1
182 struct hns3_port_base_vlan_config {
187 /* Primary process maintains driver state in main thread.
190 * | UNINITIALIZED |<-----------+
191 * +---------------+ |
192 * |.eth_dev_init |.eth_dev_uninit
194 * +---------------+------------+
196 * +---------------+<-----------<---------------+
197 * |.dev_configure | |
199 * +---------------+------------+ |
201 * +---------------+----+ |
203 * | | +---------------+
205 * | | +---------------+
207 * V |.dev_configure |
208 * +---------------+----+ |.dev_close
209 * | CONFIGURED |----------------------------+
210 * +---------------+<-----------+
213 * +---------------+ |
214 * | STARTING |------------^
215 * +---------------+ failed |
217 * | +---------------+
219 * | +---------------+
222 * +---------------+------------+
226 enum hns3_adapter_state {
227 HNS3_NIC_UNINITIALIZED = 0,
228 HNS3_NIC_INITIALIZED,
229 HNS3_NIC_CONFIGURING,
240 /* Reset various stages, execute in order */
241 enum hns3_reset_stage {
242 /* Stop query services, stop transceiver, disable MAC */
244 /* Clear reset completion flags, disable send command */
246 /* Inform IMP to start resetting */
247 RESET_STAGE_REQ_HW_RESET,
248 /* Waiting for hardware reset to complete */
250 /* Reinitialize hardware */
251 RESET_STAGE_DEV_INIT,
252 /* Restore user settings and enable MAC */
254 /* Restart query services, start transceiver */
256 /* Not in reset state */
260 enum hns3_reset_level {
262 HNS3_VF_FUNC_RESET, /* A VF function reset */
264 * All VFs under a PF perform function reset.
265 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
266 * of the reset level and the one defined in kernel driver should be
269 HNS3_VF_PF_FUNC_RESET = 2,
271 * All VFs under a PF perform FLR reset.
272 * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
273 * of the reset level and the one defined in kernel driver should be
276 HNS3_VF_FULL_RESET = 3,
277 HNS3_FLR_RESET, /* A VF perform FLR reset */
278 /* All VFs under the rootport perform a global or IMP reset */
280 HNS3_FUNC_RESET, /* A PF function reset */
281 /* All PFs under the rootport perform a global reset */
283 HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
287 enum hns3_wait_result {
294 #define HNS3_RESET_SYNC_US 100000
296 struct hns3_reset_stats {
297 uint64_t request_cnt; /* Total request reset times */
298 uint64_t global_cnt; /* Total GLOBAL reset times */
299 uint64_t imp_cnt; /* Total IMP reset times */
300 uint64_t exec_cnt; /* Total reset executive times */
301 uint64_t success_cnt; /* Total reset successful times */
302 uint64_t fail_cnt; /* Total reset failed times */
303 uint64_t merge_cnt; /* Total merged in high reset times */
306 typedef bool (*check_completion_func)(struct hns3_hw *hw);
308 struct hns3_wait_data {
313 enum hns3_wait_result result;
314 check_completion_func check_completion;
317 struct hns3_reset_ops {
318 void (*reset_service)(void *arg);
319 int (*stop_service)(struct hns3_adapter *hns);
320 int (*prepare_reset)(struct hns3_adapter *hns);
321 int (*wait_hardware_ready)(struct hns3_adapter *hns);
322 int (*reinit_dev)(struct hns3_adapter *hns);
323 int (*restore_conf)(struct hns3_adapter *hns);
324 int (*start_service)(struct hns3_adapter *hns);
334 struct hns3_reset_data {
335 enum hns3_reset_stage stage;
336 rte_atomic16_t schedule;
337 /* Reset flag, covering the entire reset process */
338 rte_atomic16_t resetting;
339 /* Used to disable sending cmds during reset */
340 rte_atomic16_t disable_cmd;
341 /* The reset level being processed */
342 enum hns3_reset_level level;
343 /* Reset level set, each bit represents a reset level */
345 /* Request reset level set, from interrupt or mailbox */
347 int attempts; /* Reset failure retry */
348 int retries; /* Timeout failure retry in reset_post */
350 * At the time of global or IMP reset, the command cannot be sent to
351 * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
352 * reset process, so the mbuf is required to be released after the reset
353 * is completed.The mbuf_deferred_free is used to mark whether mbuf
354 * needs to be released.
356 bool mbuf_deferred_free;
357 struct timeval start_time;
358 struct hns3_reset_stats stats;
359 const struct hns3_reset_ops *ops;
360 struct hns3_wait_data *wait_data;
363 #define HNS3_INTR_MAPPING_VEC_RSV_ONE 0
364 #define HNS3_INTR_MAPPING_VEC_ALL 1
366 #define HNS3_INTR_COALESCE_NON_QL 0
367 #define HNS3_INTR_COALESCE_QL 1
369 #define HNS3_INTR_COALESCE_GL_UINT_2US 0
370 #define HNS3_INTR_COALESCE_GL_UINT_1US 1
372 struct hns3_queue_intr {
374 * interrupt mapping mode.
376 * HNS3_INTR_MAPPING_VEC_RSV_ONE/HNS3_INTR_MAPPING_VEC_ALL
378 * - HNS3_INTR_MAPPING_VEC_RSV_ONE
379 * For some versions of hardware network engine, because of the
380 * hardware constraint, we need implement clearing the mapping
381 * relationship configurations by binding all queues to the last
382 * interrupt vector and reserving the last interrupt vector. This
383 * method results in a decrease of the maximum queues when upper
384 * applications call the rte_eth_dev_configure API function to
385 * enable Rx interrupt.
387 * - HNS3_INTR_MAPPING_VEC_ALL
388 * PMD driver can map/unmmap all interrupt vectors with queues When
389 * Rx interrupt in enabled.
391 uint8_t mapping_mode;
393 * interrupt coalesce mode.
395 * HNS3_INTR_COALESCE_NON_QL/HNS3_INTR_COALESCE_QL
397 * - HNS3_INTR_COALESCE_NON_QL
398 * For some versions of hardware network engine, hardware doesn't
399 * support QL(quanity limiter) algorithm for interrupt coalesce
400 * of queue's interrupt.
402 * - HNS3_INTR_COALESCE_QL
403 * In this mode, hardware support QL(quanity limiter) algorithm for
404 * interrupt coalesce of queue's interrupt.
406 uint8_t coalesce_mode;
408 * The unit of GL(gap limiter) configuration for interrupt coalesce of
411 * HNS3_INTR_COALESCE_GL_UINT_2US/HNS3_INTR_COALESCE_GL_UINT_1US
417 struct rte_eth_dev_data *data;
419 uint8_t revision; /* PCI revision, low byte of class word */
421 struct hns3_mbx_resp_status mbx_resp; /* mailbox response */
422 struct hns3_mbx_arq_ring arq; /* mailbox async rx queue */
423 pthread_t irq_thread_id;
425 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
426 struct hns3_tqp_stats tqp_stats;
427 /* Include Mac stats | Rx stats | Tx stats */
428 struct hns3_mac_stats mac_stats;
432 uint16_t total_tqps_num; /* total task queue pairs of this PF */
433 uint16_t tqps_num; /* num task queue pairs of this function */
434 uint16_t intr_tqps_num; /* num queue pairs mapping interrupt */
435 uint16_t rss_size_max; /* HW defined max RSS task queue */
436 uint16_t rx_buf_len; /* hold min hardware rx buf len */
437 uint16_t num_tx_desc; /* desc num of per tx queue */
438 uint16_t num_rx_desc; /* desc num of per rx queue */
439 uint32_t mng_entry_num; /* number of manager table entry */
440 uint32_t mac_entry_num; /* number of mac-vlan table entry */
442 struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
443 int mc_addrs_num; /* Multicast mac addresses number */
445 /* The configuration info of RSS */
446 struct hns3_rss_conf rss_info;
447 bool rss_dis_flag; /* disable rss flag. true: disable, false: enable */
448 uint16_t rss_ind_tbl_size;
449 uint16_t rss_key_size;
451 uint8_t num_tc; /* Total number of enabled TCs */
453 enum hns3_fc_mode current_mode;
454 enum hns3_fc_mode requested_mode;
455 struct hns3_dcb_info dcb_info;
456 enum hns3_fc_status current_fc_status; /* current flow control status */
457 struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
458 uint16_t used_rx_queues;
459 uint16_t used_tx_queues;
461 /* Config max queue numbers between rx and tx queues from user */
462 uint16_t cfg_max_queues;
463 struct hns3_fake_queue_data fkq_data; /* fake queue data */
464 uint16_t alloc_rss_size; /* RX queue number per TC */
465 uint16_t tx_qnum_per_tc; /* TX queue number per TC */
468 uint32_t max_tm_rate;
470 * The minimum length of the packet supported by hardware in the Tx
473 uint32_t min_tx_pkt_len;
475 struct hns3_queue_intr intr;
477 uint8_t max_non_tso_bd_num; /* max BD number of one non-TSO packet */
479 struct hns3_port_base_vlan_config port_base_vlan_cfg;
481 * PMD setup and configuration is not thread safe. Since it is not
482 * performance sensitive, it is better to guarantee thread-safety
483 * and add device level lock. Adapter control operations which
484 * change its state should acquire the lock.
487 enum hns3_adapter_state adapter_state;
488 struct hns3_reset_data reset;
491 #define HNS3_FLAG_TC_BASE_SCH_MODE 1
492 #define HNS3_FLAG_VNET_BASE_SCH_MODE 2
494 struct hns3_err_msix_intr_stats {
495 uint64_t mac_afifo_tnl_int_cnt;
496 uint64_t ppu_mpf_abn_int_st2_msix_cnt;
497 uint64_t ssu_port_based_pf_int_cnt;
498 uint64_t ppp_pf_abnormal_int_cnt;
499 uint64_t ppu_pf_abnormal_int_msix_cnt;
501 uint64_t imp_tcm_ecc_int_cnt;
502 uint64_t cmdq_mem_ecc_int_cnt;
503 uint64_t imp_rd_poison_int_cnt;
504 uint64_t tqp_int_ecc_int_cnt;
505 uint64_t msix_ecc_int_cnt;
506 uint64_t ssu_ecc_multi_bit_int_0_cnt;
507 uint64_t ssu_ecc_multi_bit_int_1_cnt;
508 uint64_t ssu_common_ecc_int_cnt;
509 uint64_t igu_int_cnt;
510 uint64_t ppp_mpf_abnormal_int_st1_cnt;
511 uint64_t ppp_mpf_abnormal_int_st3_cnt;
512 uint64_t ppu_mpf_abnormal_int_st1_cnt;
513 uint64_t ppu_mpf_abn_int_st2_ras_cnt;
514 uint64_t ppu_mpf_abnormal_int_st3_cnt;
515 uint64_t tm_sch_int_cnt;
516 uint64_t qcn_fifo_int_cnt;
517 uint64_t qcn_ecc_int_cnt;
518 uint64_t ncsi_ecc_int_cnt;
519 uint64_t ssu_port_based_err_int_cnt;
520 uint64_t ssu_fifo_overflow_int_cnt;
521 uint64_t ssu_ets_tcg_int_cnt;
522 uint64_t igu_egu_tnl_int_cnt;
523 uint64_t ppu_pf_abnormal_int_ras_cnt;
526 /* vlan entry information. */
527 struct hns3_user_vlan_table {
528 LIST_ENTRY(hns3_user_vlan_table) next;
533 /* Vlan tag configuration for RX direction */
534 struct hns3_rx_vtag_cfg {
535 uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
536 uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
537 uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
538 uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
539 uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
542 /* Vlan tag configuration for TX direction */
543 struct hns3_tx_vtag_cfg {
544 bool accept_tag1; /* Whether accept tag1 packet from host */
545 bool accept_untag1; /* Whether accept untag1 packet from host */
548 bool insert_tag1_en; /* Whether insert inner vlan tag */
549 bool insert_tag2_en; /* Whether insert outer vlan tag */
550 uint16_t default_tag1; /* The default inner vlan tag to insert */
551 uint16_t default_tag2; /* The default outer vlan tag to insert */
554 struct hns3_vtag_cfg {
555 struct hns3_rx_vtag_cfg rx_vcfg;
556 struct hns3_tx_vtag_cfg tx_vcfg;
559 /* Request types for IPC. */
560 enum hns3_mp_req_type {
561 HNS3_MP_REQ_START_RXTX = 1,
562 HNS3_MP_REQ_STOP_RXTX,
566 /* Pameters for IPC. */
567 struct hns3_mp_param {
568 enum hns3_mp_req_type type;
573 /* Request timeout for IPC. */
574 #define HNS3_MP_REQ_TIMEOUT_SEC 5
576 /* Key string for IPC. */
577 #define HNS3_MP_NAME "net_hns3_mp"
579 #define HNS3_L2TBL_NUM 4
580 #define HNS3_L3TBL_NUM 16
581 #define HNS3_L4TBL_NUM 16
582 #define HNS3_OL3TBL_NUM 16
583 #define HNS3_OL4TBL_NUM 16
585 struct hns3_ptype_table {
586 uint32_t l2table[HNS3_L2TBL_NUM];
587 uint32_t l3table[HNS3_L3TBL_NUM];
588 uint32_t l4table[HNS3_L4TBL_NUM];
589 uint32_t inner_l2table[HNS3_L2TBL_NUM];
590 uint32_t inner_l3table[HNS3_L3TBL_NUM];
591 uint32_t inner_l4table[HNS3_L4TBL_NUM];
592 uint32_t ol3table[HNS3_OL3TBL_NUM];
593 uint32_t ol4table[HNS3_OL4TBL_NUM];
597 struct hns3_adapter *adapter;
599 uint16_t func_num; /* num functions of this pf, include pf and vfs */
601 uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
602 uint32_t tx_buf_size; /* Tx buffer size for each TC */
603 uint32_t dv_buf_size; /* Dv buffer size for each TC */
605 uint16_t mps; /* Max packet size */
608 uint8_t tc_max; /* max number of tc driver supported */
609 uint8_t local_max_tc; /* max number of local tc */
611 uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
613 bool support_fc_autoneg; /* support FC autonegotiate */
615 uint16_t wanted_umv_size;
616 uint16_t max_umv_size;
617 uint16_t used_umv_size;
619 /* Statistics information for abnormal interrupt */
620 struct hns3_err_msix_intr_stats abn_int_stats;
622 bool support_sfp_query;
624 struct hns3_vtag_cfg vtag_config;
625 LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
627 struct hns3_fdir_info fdir; /* flow director info */
628 LIST_HEAD(counters, hns3_flow_counter) flow_counters;
632 struct hns3_adapter *adapter;
635 struct hns3_adapter {
638 /* Specific for PF or VF */
639 bool is_vf; /* false - PF, true - VF */
645 bool rx_simple_allowed;
646 struct hns3_ptype_table ptype_tbl __rte_cache_min_aligned;
649 #define HNS3_DEV_SUPPORT_DCB_B 0x0
650 #define HNS3_DEV_SUPPORT_COPPER_B 0x1
651 #define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
652 #define HNS3_DEV_SUPPORT_ADQ_B 0x3
653 #define HNS3_DEV_SUPPORT_PTP_B 0x4
654 #define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
655 #define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
656 #define HNS3_DEV_SUPPORT_STASH_B 0x7
658 #define hns3_dev_dcb_supported(hw) \
659 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
661 /* Support copper media type */
662 #define hns3_dev_copper_supported(hw) \
663 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
665 /* Support UDP GSO offload */
666 #define hns3_dev_udp_gso_supported(hw) \
667 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
669 /* Support Application Device Queue */
670 #define hns3_dev_adq_supported(hw) \
671 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
673 /* Support PTP timestamp offload */
674 #define hns3_dev_ptp_supported(hw) \
675 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
677 #define hns3_dev_tx_push_supported(hw) \
678 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
680 /* Support to Independently enable/disable/reset Tx or Rx queues */
681 #define hns3_dev_indep_txrx_supported(hw) \
682 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
684 #define hns3_dev_stash_supported(hw) \
685 hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
687 #define HNS3_DEV_PRIVATE_TO_HW(adapter) \
688 (&((struct hns3_adapter *)adapter)->hw)
689 #define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
690 ((struct hns3_adapter *)adapter)
691 #define HNS3_DEV_PRIVATE_TO_PF(adapter) \
692 (&((struct hns3_adapter *)adapter)->pf)
693 #define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
694 (&((struct hns3_adapter *)adapter)->vf)
695 #define HNS3_DEV_HW_TO_ADAPTER(hw) \
696 container_of(hw, struct hns3_adapter, hw)
698 #define hns3_set_field(origin, mask, shift, val) \
700 (origin) &= (~(mask)); \
701 (origin) |= ((val) << (shift)) & (mask); \
703 #define hns3_get_field(origin, mask, shift) \
704 (((origin) & (mask)) >> (shift))
705 #define hns3_set_bit(origin, shift, val) \
706 hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
707 #define hns3_get_bit(origin, shift) \
708 hns3_get_field((origin), (0x1UL << (shift)), (shift))
711 * upper_32_bits - return bits 32-63 of a number
712 * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
713 * the "right shift count >= width of type" warning when that quantity is
716 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
718 /* lower_32_bits - return bits 0-31 of a number */
719 #define lower_32_bits(n) ((uint32_t)(n))
721 #define BIT(nr) (1UL << (nr))
723 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
724 #define GENMASK(h, l) \
725 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
727 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
728 #define rounddown(x, y) ((x) - ((x) % (y)))
730 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
733 * Because hardware always access register in little-endian mode based on hns3
734 * network engine, so driver should also call rte_cpu_to_le_32 to convert data
735 * in little-endian mode before writing register and call rte_le_to_cpu_32 to
736 * convert data after reading from register.
738 * Here the driver encapsulates the data conversion operation in the register
739 * read/write operation function as below:
743 * Therefore, when calling these functions, conversion is not required again.
745 static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
747 rte_write32(rte_cpu_to_le_32(value),
748 (volatile void *)((char *)base + reg));
752 * The optimized function for writing registers used in the '.rx_pkt_burst' and
753 * '.tx_pkt_burst' ops implementation function.
755 static inline void hns3_write_reg_opt(volatile void *addr, uint32_t value)
758 rte_write32_relaxed(rte_cpu_to_le_32(value), addr);
761 static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
763 uint32_t read_val = rte_read32((volatile void *)((char *)base + reg));
764 return rte_le_to_cpu_32(read_val);
767 #define hns3_write_dev(a, reg, value) \
768 hns3_write_reg((a)->io_base, (reg), (value))
770 #define hns3_read_dev(a, reg) \
771 hns3_read_reg((a)->io_base, (reg))
773 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
775 #define NEXT_ITEM_OF_ACTION(act, actions, index) \
777 act = (actions) + (index); \
778 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
780 act = actions + index; \
784 #define MSEC_PER_SEC 1000L
785 #define USEC_PER_MSEC 1000L
787 static inline uint64_t
788 get_timeofday_ms(void)
792 (void)gettimeofday(&tv, NULL);
794 return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
797 static inline uint64_t
798 hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
802 res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
807 hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
809 __atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
813 hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
815 __atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
818 static inline int64_t
819 hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
821 uint64_t mask = (1UL << nr);
823 return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
826 int hns3_buffer_alloc(struct hns3_hw *hw);
827 int hns3_dev_filter_ctrl(struct rte_eth_dev *dev,
828 enum rte_filter_type filter_type,
829 enum rte_filter_op filter_op, void *arg);
830 bool hns3_is_reset_pending(struct hns3_adapter *hns);
831 bool hns3vf_is_reset_pending(struct hns3_adapter *hns);
832 void hns3_update_link_status(struct hns3_hw *hw);
835 is_reset_pending(struct hns3_adapter *hns)
839 ret = hns3vf_is_reset_pending(hns);
841 ret = hns3_is_reset_pending(hns);
845 static inline uint64_t
846 hns3_txvlan_cap_get(struct hns3_hw *hw)
848 if (hw->port_base_vlan_cfg.state)
849 return DEV_TX_OFFLOAD_VLAN_INSERT;
851 return DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT;
854 #endif /* _HNS3_ETHDEV_H_ */