drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 rss_conf = conf->rx_adv_conf.rss_conf;
 787                 if (rss_conf.rss_key == NULL) {
 788                         rss_conf.rss_key = rss_cfg->key;
 789                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 790                 }
 791
 792                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 793                 if (ret)
 794                         goto cfg_err;
 795         }
 796
 797         /*
 798          * If jumbo frames are enabled, MTU needs to be refreshed
 799          * according to the maximum RX packet length.
 800          */
 801         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 802                 /*
 803                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 804                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 805                  * can safely assign to "uint16_t" type variable.
 806                  */
 807                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 808                 ret = hns3vf_dev_mtu_set(dev, mtu);
 809                 if (ret)
 810                         goto cfg_err;
 811                 dev->data->mtu = mtu;
 812         }
 813
 814         ret = hns3vf_dev_configure_vlan(dev);
 815         if (ret)
 816                 goto cfg_err;
 817
 818         /* config hardware GRO */
 819         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 820         ret = hns3_config_gro(hw, gro_en);
 821         if (ret)
 822                 goto cfg_err;
 823
 824         hns->rx_simple_allowed = true;
 825         hns->rx_vec_allowed = true;
 826         hns->tx_simple_allowed = true;
 827         hns->tx_vec_allowed = true;
 828
 829         hns3_init_rx_ptype_tble(dev);
 830
 831         hw->adapter_state = HNS3_NIC_CONFIGURED;
 832         return 0;
 833
 834 cfg_err:
 835         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 836         hw->adapter_state = HNS3_NIC_INITIALIZED;
 837
 838         return ret;
 839 }
 840
 841 static int
 842 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 843 {
 844         int ret;
 845
 846         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 847                                 sizeof(mtu), true, NULL, 0);
 848         if (ret)
 849                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 850
 851         return ret;
 852 }
 853
 854 static int
 855 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 856 {
 857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 858         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 859         int ret;
 860
 861         /*
 862          * The hns3 PF/VF devices on the same port share the hardware MTU
 863          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 864          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 865          * driver, there is no need to stop the port for hns3 VF device, and the
 866          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 867          * PF's MTU.
 868          */
 869         if (rte_atomic16_read(&hw->reset.resetting)) {
 870                 hns3_err(hw, "Failed to set mtu during resetting");
 871                 return -EIO;
 872         }
 873
 874         /*
 875          * when Rx of scattered packets is off, we have some possibility of
 876          * using vector Rx process function or simple Rx functions in hns3 PMD
 877          * driver. If the input MTU is increased and the maximum length of
 878          * received packets is greater than the length of a buffer for Rx
 879          * packet, the hardware network engine needs to use multiple BDs and
 880          * buffers to store these packets. This will cause problems when still
 881          * using vector Rx process function or simple Rx function to receiving
 882          * packets. So, when Rx of scattered packets is off and device is
 883          * started, it is not permitted to increase MTU so that the maximum
 884          * length of Rx packets is greater than Rx buffer length.
 885          */
 886         if (dev->data->dev_started && !dev->data->scattered_rx &&
 887             frame_size > hw->rx_buf_len) {
 888                 hns3_err(hw, "failed to set mtu because current is "
 889                         "not scattered rx mode");
 890                 return -EOPNOTSUPP;
 891         }
 892
 893         rte_spinlock_lock(&hw->lock);
 894         ret = hns3vf_config_mtu(hw, mtu);
 895         if (ret) {
 896                 rte_spinlock_unlock(&hw->lock);
 897                 return ret;
 898         }
 899         if (frame_size > RTE_ETHER_MAX_LEN)
 900                 dev->data->dev_conf.rxmode.offloads |=
 901                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 902         else
 903                 dev->data->dev_conf.rxmode.offloads &=
 904                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 905         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 906         rte_spinlock_unlock(&hw->lock);
 907
 908         return 0;
 909 }
 910
 911 static int
 912 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 913 {
 914         struct hns3_adapter *hns = eth_dev->data->dev_private;
 915         struct hns3_hw *hw = &hns->hw;
 916         uint16_t q_num = hw->tqps_num;
 917
 918         /*
 919          * In interrupt mode, 'max_rx_queues' is set based on the number of
 920          * MSI-X interrupt resources of the hardware.
 921          */
 922         if (hw->data->dev_conf.intr_conf.rxq == 1)
 923                 q_num = hw->intr_tqps_num;
 924
 925         info->max_rx_queues = q_num;
 926         info->max_tx_queues = hw->tqps_num;
 927         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 928         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 929         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 930         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 931         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 932
 933         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 934                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 935                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 936                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 937                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 938                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 939                                  DEV_RX_OFFLOAD_SCATTER |
 940                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 941                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 942                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 943                                  DEV_RX_OFFLOAD_RSS_HASH |
 944                                  DEV_RX_OFFLOAD_TCP_LRO);
 945         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 946                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 947                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 948                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 949                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 950                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 951                                  DEV_TX_OFFLOAD_TCP_TSO |
 952                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 953                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 954                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 955                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 956                                  hns3_txvlan_cap_get(hw));
 957
 958         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 959                 .nb_max = HNS3_MAX_RING_DESC,
 960                 .nb_min = HNS3_MIN_RING_DESC,
 961                 .nb_align = HNS3_ALIGN_RING_DESC,
 962         };
 963
 964         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 965                 .nb_max = HNS3_MAX_RING_DESC,
 966                 .nb_min = HNS3_MIN_RING_DESC,
 967                 .nb_align = HNS3_ALIGN_RING_DESC,
 968                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 969                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 970         };
 971
 972         info->default_rxconf = (struct rte_eth_rxconf) {
 973                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 974                 /*
 975                  * If there are no available Rx buffer descriptors, incoming
 976                  * packets are always dropped by hardware based on hns3 network
 977                  * engine.
 978                  */
 979                 .rx_drop_en = 1,
 980                 .offloads = 0,
 981         };
 982         info->default_txconf = (struct rte_eth_txconf) {
 983                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 984                 .offloads = 0,
 985         };
 986
 987         info->vmdq_queue_num = 0;
 988
 989         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 990         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 991         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 992         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 993         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 994
 995         return 0;
 996 }
 997
 998 static void
 999 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1000 {
1001         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1002 }
1003
1004 static void
1005 hns3vf_disable_irq0(struct hns3_hw *hw)
1006 {
1007         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1008 }
1009
1010 static void
1011 hns3vf_enable_irq0(struct hns3_hw *hw)
1012 {
1013         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1014 }
1015
1016 static enum hns3vf_evt_cause
1017 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1018 {
1019         struct hns3_hw *hw = &hns->hw;
1020         enum hns3vf_evt_cause ret;
1021         uint32_t cmdq_stat_reg;
1022         uint32_t rst_ing_reg;
1023         uint32_t val;
1024
1025         /* Fetch the events from their corresponding regs */
1026         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1027
1028         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1029                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1030                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1031                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1032                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1033                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1034                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1035                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1036                 if (clearval) {
1037                         hw->reset.stats.global_cnt++;
1038                         hns3_warn(hw, "Global reset detected, clear reset status");
1039                 } else {
1040                         hns3_schedule_delayed_reset(hns);
1041                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1042                 }
1043
1044                 ret = HNS3VF_VECTOR0_EVENT_RST;
1045                 goto out;
1046         }
1047
1048         /* Check for vector0 mailbox(=CMDQ RX) event source */
1049         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1050                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1051                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1052                 goto out;
1053         }
1054
1055         val = 0;
1056         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1057 out:
1058         if (clearval)
1059                 *clearval = val;
1060         return ret;
1061 }
1062
1063 static void
1064 hns3vf_interrupt_handler(void *param)
1065 {
1066         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1067         struct hns3_adapter *hns = dev->data->dev_private;
1068         struct hns3_hw *hw = &hns->hw;
1069         enum hns3vf_evt_cause event_cause;
1070         uint32_t clearval;
1071
1072         if (hw->irq_thread_id == 0)
1073                 hw->irq_thread_id = pthread_self();
1074
1075         /* Disable interrupt */
1076         hns3vf_disable_irq0(hw);
1077
1078         /* Read out interrupt causes */
1079         event_cause = hns3vf_check_event_cause(hns, &clearval);
1080
1081         switch (event_cause) {
1082         case HNS3VF_VECTOR0_EVENT_RST:
1083                 hns3_schedule_reset(hns);
1084                 break;
1085         case HNS3VF_VECTOR0_EVENT_MBX:
1086                 hns3_dev_handle_mbx_msg(hw);
1087                 break;
1088         default:
1089                 break;
1090         }
1091
1092         /* Clear interrupt causes */
1093         hns3vf_clear_event_cause(hw, clearval);
1094
1095         /* Enable interrupt */
1096         hns3vf_enable_irq0(hw);
1097 }
1098
1099 static void
1100 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1101 {
1102         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1103         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1104         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1105 }
1106
1107 static void
1108 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1109 {
1110         struct hns3_dev_specs_0_cmd *req0;
1111
1112         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1113
1114         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1115         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1116         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1117 }
1118
1119 static int
1120 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1121 {
1122         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1123         int ret;
1124         int i;
1125
1126         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1127                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1128                                           true);
1129                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1130         }
1131         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1132
1133         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1134         if (ret)
1135                 return ret;
1136
1137         hns3vf_parse_dev_specifications(hw, desc);
1138
1139         return 0;
1140 }
1141
1142 static int
1143 hns3vf_get_capability(struct hns3_hw *hw)
1144 {
1145         struct rte_pci_device *pci_dev;
1146         struct rte_eth_dev *eth_dev;
1147         uint8_t revision;
1148         int ret;
1149
1150         eth_dev = &rte_eth_devices[hw->data->port_id];
1151         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1152
1153         /* Get PCI revision id */
1154         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1155                                   HNS3_PCI_REVISION_ID);
1156         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1157                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1158                              ret);
1159                 return -EIO;
1160         }
1161         hw->revision = revision;
1162
1163         if (revision < PCI_REVISION_ID_HIP09_A) {
1164                 hns3vf_set_default_dev_specifications(hw);
1165                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1166                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1167                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1168                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1169                 return 0;
1170         }
1171
1172         ret = hns3vf_query_dev_specifications(hw);
1173         if (ret) {
1174                 PMD_INIT_LOG(ERR,
1175                              "failed to query dev specifications, ret = %d",
1176                              ret);
1177                 return ret;
1178         }
1179
1180         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1181         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1182         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1183         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1184
1185         return 0;
1186 }
1187
1188 static int
1189 hns3vf_check_tqp_info(struct hns3_hw *hw)
1190 {
1191         uint16_t tqps_num;
1192
1193         tqps_num = hw->tqps_num;
1194         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1195                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1196                                   "range: 1~%d",
1197                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1198                 return -EINVAL;
1199         }
1200
1201         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1202
1203         return 0;
1204 }
1205 static int
1206 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1207 {
1208         uint8_t resp_msg;
1209         int ret;
1210
1211         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1212                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1213                                 true, &resp_msg, sizeof(resp_msg));
1214         if (ret) {
1215                 if (ret == -ETIME) {
1216                         /*
1217                          * Getting current port based VLAN state from PF driver
1218                          * will not affect VF driver's basic function. Because
1219                          * the VF driver relies on hns3 PF kernel ether driver,
1220                          * to avoid introducing compatibility issues with older
1221                          * version of PF driver, no failure will be returned
1222                          * when the return value is ETIME. This return value has
1223                          * the following scenarios:
1224                          * 1) Firmware didn't return the results in time
1225                          * 2) the result return by firmware is timeout
1226                          * 3) the older version of kernel side PF driver does
1227                          *    not support this mailbox message.
1228                          * For scenarios 1 and 2, it is most likely that a
1229                          * hardware error has occurred, or a hardware reset has
1230                          * occurred. In this case, these errors will be caught
1231                          * by other functions.
1232                          */
1233                         PMD_INIT_LOG(WARNING,
1234                                 "failed to get PVID state for timeout, maybe "
1235                                 "kernel side PF driver doesn't support this "
1236                                 "mailbox message, or firmware didn't respond.");
1237                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1238                 } else {
1239                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1240                                 " ret = %d", ret);
1241                         return ret;
1242                 }
1243         }
1244         hw->port_base_vlan_cfg.state = resp_msg ?
1245                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1246         return 0;
1247 }
1248
1249 static int
1250 hns3vf_get_queue_info(struct hns3_hw *hw)
1251 {
1252 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1253         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1254         int ret;
1255
1256         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1257                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1258         if (ret) {
1259                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1260                 return ret;
1261         }
1262
1263         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1264         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1265
1266         return hns3vf_check_tqp_info(hw);
1267 }
1268
1269 static int
1270 hns3vf_get_queue_depth(struct hns3_hw *hw)
1271 {
1272 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1273         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1274         int ret;
1275
1276         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1277                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1278         if (ret) {
1279                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1280                              ret);
1281                 return ret;
1282         }
1283
1284         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1285         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1286
1287         return 0;
1288 }
1289
1290 static int
1291 hns3vf_get_tc_info(struct hns3_hw *hw)
1292 {
1293         uint8_t resp_msg;
1294         int ret;
1295
1296         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1297                                 true, &resp_msg, sizeof(resp_msg));
1298         if (ret) {
1299                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1300                          ret);
1301                 return ret;
1302         }
1303
1304         hw->hw_tc_map = resp_msg;
1305
1306         return 0;
1307 }
1308
1309 static int
1310 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1311 {
1312         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1313         int ret;
1314
1315         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1316                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1317         if (ret) {
1318                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1319                 return ret;
1320         }
1321
1322         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1323
1324         return 0;
1325 }
1326
1327 static int
1328 hns3vf_get_configuration(struct hns3_hw *hw)
1329 {
1330         int ret;
1331
1332         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1333         hw->rss_dis_flag = false;
1334
1335         /* Get device capability */
1336         ret = hns3vf_get_capability(hw);
1337         if (ret) {
1338                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1339                 return ret;
1340         }
1341
1342         /* Get queue configuration from PF */
1343         ret = hns3vf_get_queue_info(hw);
1344         if (ret)
1345                 return ret;
1346
1347         /* Get queue depth info from PF */
1348         ret = hns3vf_get_queue_depth(hw);
1349         if (ret)
1350                 return ret;
1351
1352         /* Get user defined VF MAC addr from PF */
1353         ret = hns3vf_get_host_mac_addr(hw);
1354         if (ret)
1355                 return ret;
1356
1357         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1358         if (ret)
1359                 return ret;
1360
1361         /* Get tc configuration from PF */
1362         return hns3vf_get_tc_info(hw);
1363 }
1364
1365 static int
1366 hns3vf_set_tc_info(struct hns3_adapter *hns)
1367 {
1368         struct hns3_hw *hw = &hns->hw;
1369         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1370         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1371         uint8_t i;
1372
1373         hw->num_tc = 0;
1374         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1375                 if (hw->hw_tc_map & BIT(i))
1376                         hw->num_tc++;
1377
1378         if (nb_rx_q < hw->num_tc) {
1379                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1380                          nb_rx_q, hw->num_tc);
1381                 return -EINVAL;
1382         }
1383
1384         if (nb_tx_q < hw->num_tc) {
1385                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1386                          nb_tx_q, hw->num_tc);
1387                 return -EINVAL;
1388         }
1389
1390         hns3_set_rss_size(hw, nb_rx_q);
1391         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1392
1393         return 0;
1394 }
1395
1396 static void
1397 hns3vf_request_link_info(struct hns3_hw *hw)
1398 {
1399         uint8_t resp_msg;
1400         int ret;
1401
1402         if (rte_atomic16_read(&hw->reset.resetting))
1403                 return;
1404         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1405                                 &resp_msg, sizeof(resp_msg));
1406         if (ret)
1407                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1408 }
1409
1410 static int
1411 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1412 {
1413 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1414         struct hns3_hw *hw = &hns->hw;
1415         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1416         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1417         uint8_t is_kill = on ? 0 : 1;
1418
1419         msg_data[0] = is_kill;
1420         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1421         memcpy(&msg_data[3], &proto, sizeof(proto));
1422
1423         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1424                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1425                                  0);
1426 }
1427
1428 static int
1429 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1430 {
1431         struct hns3_adapter *hns = dev->data->dev_private;
1432         struct hns3_hw *hw = &hns->hw;
1433         int ret;
1434
1435         if (rte_atomic16_read(&hw->reset.resetting)) {
1436                 hns3_err(hw,
1437                          "vf set vlan id failed during resetting, vlan_id =%u",
1438                          vlan_id);
1439                 return -EIO;
1440         }
1441         rte_spinlock_lock(&hw->lock);
1442         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1443         rte_spinlock_unlock(&hw->lock);
1444         if (ret)
1445                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1446                          vlan_id, ret);
1447
1448         return ret;
1449 }
1450
1451 static int
1452 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1453 {
1454         uint8_t msg_data;
1455         int ret;
1456
1457         msg_data = enable ? 1 : 0;
1458         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1459                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1460         if (ret)
1461                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1462
1463         return ret;
1464 }
1465
1466 static int
1467 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1468 {
1469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1471         unsigned int tmp_mask;
1472         int ret = 0;
1473
1474         if (rte_atomic16_read(&hw->reset.resetting)) {
1475                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1476                              "mask = 0x%x", mask);
1477                 return -EIO;
1478         }
1479
1480         tmp_mask = (unsigned int)mask;
1481         /* Vlan stripping setting */
1482         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1483                 rte_spinlock_lock(&hw->lock);
1484                 /* Enable or disable VLAN stripping */
1485                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1486                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1487                 else
1488                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1489                 rte_spinlock_unlock(&hw->lock);
1490         }
1491
1492         return ret;
1493 }
1494
1495 static int
1496 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1497 {
1498         struct rte_vlan_filter_conf *vfc;
1499         struct hns3_hw *hw = &hns->hw;
1500         uint16_t vlan_id;
1501         uint64_t vbit;
1502         uint64_t ids;
1503         int ret = 0;
1504         uint32_t i;
1505
1506         vfc = &hw->data->vlan_filter_conf;
1507         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1508                 if (vfc->ids[i] == 0)
1509                         continue;
1510                 ids = vfc->ids[i];
1511                 while (ids) {
1512                         /*
1513                          * 64 means the num bits of ids, one bit corresponds to
1514                          * one vlan id
1515                          */
1516                         vlan_id = 64 * i;
1517                         /* count trailing zeroes */
1518                         vbit = ~ids & (ids - 1);
1519                         /* clear least significant bit set */
1520                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1521                         for (; vbit;) {
1522                                 vbit >>= 1;
1523                                 vlan_id++;
1524                         }
1525                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1526                         if (ret) {
1527                                 hns3_err(hw,
1528                                          "VF handle vlan table failed, ret =%d, on = %d",
1529                                          ret, on);
1530                                 return ret;
1531                         }
1532                 }
1533         }
1534
1535         return ret;
1536 }
1537
1538 static int
1539 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1540 {
1541         return hns3vf_handle_all_vlan_table(hns, 0);
1542 }
1543
1544 static int
1545 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1546 {
1547         struct hns3_hw *hw = &hns->hw;
1548         struct rte_eth_conf *dev_conf;
1549         bool en;
1550         int ret;
1551
1552         dev_conf = &hw->data->dev_conf;
1553         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1554                                                                    : false;
1555         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1556         if (ret)
1557                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1558                          ret);
1559         return ret;
1560 }
1561
1562 static int
1563 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1564 {
1565         struct hns3_adapter *hns = dev->data->dev_private;
1566         struct rte_eth_dev_data *data = dev->data;
1567         struct hns3_hw *hw = &hns->hw;
1568         int ret;
1569
1570         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1571             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1572             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1573                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1574                               "or hw_vlan_insert_pvid is not support!");
1575         }
1576
1577         /* Apply vlan offload setting */
1578         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1579         if (ret)
1580                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1581
1582         return ret;
1583 }
1584
1585 static int
1586 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1587 {
1588         uint8_t msg_data;
1589
1590         msg_data = alive ? 1 : 0;
1591         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1592                                  sizeof(msg_data), false, NULL, 0);
1593 }
1594
1595 static void
1596 hns3vf_keep_alive_handler(void *param)
1597 {
1598         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1599         struct hns3_adapter *hns = eth_dev->data->dev_private;
1600         struct hns3_hw *hw = &hns->hw;
1601         uint8_t respmsg;
1602         int ret;
1603
1604         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1605                                 false, &respmsg, sizeof(uint8_t));
1606         if (ret)
1607                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1608                          ret);
1609
1610         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1611                           eth_dev);
1612 }
1613
1614 static void
1615 hns3vf_service_handler(void *param)
1616 {
1617         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1618         struct hns3_adapter *hns = eth_dev->data->dev_private;
1619         struct hns3_hw *hw = &hns->hw;
1620
1621         /*
1622          * The query link status and reset processing are executed in the
1623          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1624          * and the query operation will time out after 30ms. In the case of
1625          * multiple PF/VFs, each query failure timeout causes the IMP reset
1626          * interrupt to fail to respond within 100ms.
1627          * Before querying the link status, check whether there is a reset
1628          * pending, and if so, abandon the query.
1629          */
1630         if (!hns3vf_is_reset_pending(hns))
1631                 hns3vf_request_link_info(hw);
1632         else
1633                 hns3_warn(hw, "Cancel the query when reset is pending");
1634
1635         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1636                           eth_dev);
1637 }
1638
1639 static int
1640 hns3_query_vf_resource(struct hns3_hw *hw)
1641 {
1642         struct hns3_vf_res_cmd *req;
1643         struct hns3_cmd_desc desc;
1644         uint16_t num_msi;
1645         int ret;
1646
1647         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1648         ret = hns3_cmd_send(hw, &desc, 1);
1649         if (ret) {
1650                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1651                 return ret;
1652         }
1653
1654         req = (struct hns3_vf_res_cmd *)desc.data;
1655         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1656                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1657         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1658                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1659                          num_msi, HNS3_MIN_VECTOR_NUM);
1660                 return -EINVAL;
1661         }
1662
1663         hw->num_msi = num_msi;
1664
1665         return 0;
1666 }
1667
1668 static int
1669 hns3vf_init_hardware(struct hns3_adapter *hns)
1670 {
1671         struct hns3_hw *hw = &hns->hw;
1672         uint16_t mtu = hw->data->mtu;
1673         int ret;
1674
1675         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1676         if (ret)
1677                 return ret;
1678
1679         ret = hns3vf_config_mtu(hw, mtu);
1680         if (ret)
1681                 goto err_init_hardware;
1682
1683         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1684         if (ret) {
1685                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1686                 goto err_init_hardware;
1687         }
1688
1689         ret = hns3_config_gro(hw, false);
1690         if (ret) {
1691                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1692                 goto err_init_hardware;
1693         }
1694
1695         /*
1696          * In the initialization clearing the all hardware mapping relationship
1697          * configurations between queues and interrupt vectors is needed, so
1698          * some error caused by the residual configurations, such as the
1699          * unexpected interrupt, can be avoid.
1700          */
1701         ret = hns3vf_init_ring_with_vector(hw);
1702         if (ret) {
1703                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1704                 goto err_init_hardware;
1705         }
1706
1707         ret = hns3vf_set_alive(hw, true);
1708         if (ret) {
1709                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1710                 goto err_init_hardware;
1711         }
1712
1713         hns3vf_request_link_info(hw);
1714         return 0;
1715
1716 err_init_hardware:
1717         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1718         return ret;
1719 }
1720
1721 static int
1722 hns3vf_clear_vport_list(struct hns3_hw *hw)
1723 {
1724         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1725                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1726                                  NULL, 0);
1727 }
1728
1729 static int
1730 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1731 {
1732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1733         struct hns3_adapter *hns = eth_dev->data->dev_private;
1734         struct hns3_hw *hw = &hns->hw;
1735         int ret;
1736
1737         PMD_INIT_FUNC_TRACE();
1738
1739         /* Get hardware io base address from pcie BAR2 IO space */
1740         hw->io_base = pci_dev->mem_resource[2].addr;
1741
1742         /* Firmware command queue initialize */
1743         ret = hns3_cmd_init_queue(hw);
1744         if (ret) {
1745                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1746                 goto err_cmd_init_queue;
1747         }
1748
1749         /* Firmware command initialize */
1750         ret = hns3_cmd_init(hw);
1751         if (ret) {
1752                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1753                 goto err_cmd_init;
1754         }
1755
1756         /* Get VF resource */
1757         ret = hns3_query_vf_resource(hw);
1758         if (ret)
1759                 goto err_cmd_init;
1760
1761         rte_spinlock_init(&hw->mbx_resp.lock);
1762
1763         hns3vf_clear_event_cause(hw, 0);
1764
1765         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1766                                          hns3vf_interrupt_handler, eth_dev);
1767         if (ret) {
1768                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1769                 goto err_intr_callback_register;
1770         }
1771
1772         /* Enable interrupt */
1773         rte_intr_enable(&pci_dev->intr_handle);
1774         hns3vf_enable_irq0(hw);
1775
1776         /* Get configuration from PF */
1777         ret = hns3vf_get_configuration(hw);
1778         if (ret) {
1779                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1780                 goto err_get_config;
1781         }
1782
1783         ret = hns3vf_clear_vport_list(hw);
1784         if (ret) {
1785                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1786                 goto err_get_config;
1787         }
1788
1789         ret = hns3vf_init_hardware(hns);
1790         if (ret)
1791                 goto err_get_config;
1792
1793         hns3_set_default_rss_args(hw);
1794
1795         return 0;
1796
1797 err_get_config:
1798         hns3vf_disable_irq0(hw);
1799         rte_intr_disable(&pci_dev->intr_handle);
1800         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1801                              eth_dev);
1802 err_intr_callback_register:
1803 err_cmd_init:
1804         hns3_cmd_uninit(hw);
1805         hns3_cmd_destroy_queue(hw);
1806 err_cmd_init_queue:
1807         hw->io_base = NULL;
1808
1809         return ret;
1810 }
1811
1812 static void
1813 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1814 {
1815         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1816         struct hns3_adapter *hns = eth_dev->data->dev_private;
1817         struct hns3_hw *hw = &hns->hw;
1818
1819         PMD_INIT_FUNC_TRACE();
1820
1821         hns3_rss_uninit(hns);
1822         (void)hns3_config_gro(hw, false);
1823         (void)hns3vf_set_alive(hw, false);
1824         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1825         hns3vf_disable_irq0(hw);
1826         rte_intr_disable(&pci_dev->intr_handle);
1827         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1828                              eth_dev);
1829         hns3_cmd_uninit(hw);
1830         hns3_cmd_destroy_queue(hw);
1831         hw->io_base = NULL;
1832 }
1833
1834 static int
1835 hns3vf_do_stop(struct hns3_adapter *hns)
1836 {
1837         struct hns3_hw *hw = &hns->hw;
1838         bool reset_queue;
1839
1840         hw->mac.link_status = ETH_LINK_DOWN;
1841
1842         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1843                 hns3vf_configure_mac_addr(hns, true);
1844                 reset_queue = true;
1845         } else
1846                 reset_queue = false;
1847         return hns3_stop_queues(hns, reset_queue);
1848 }
1849
1850 static void
1851 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1852 {
1853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1855         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1856         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1857         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1858         uint16_t q_id;
1859
1860         if (dev->data->dev_conf.intr_conf.rxq == 0)
1861                 return;
1862
1863         /* unmap the ring with vector */
1864         if (rte_intr_allow_others(intr_handle)) {
1865                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1866                 base = RTE_INTR_VEC_RXTX_OFFSET;
1867         }
1868         if (rte_intr_dp_is_en(intr_handle)) {
1869                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1870                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1871                                                            HNS3_RING_TYPE_RX,
1872                                                            q_id);
1873                         if (vec < base + intr_handle->nb_efd - 1)
1874                                 vec++;
1875                 }
1876         }
1877         /* Clean datapath event and queue/vec mapping */
1878         rte_intr_efd_disable(intr_handle);
1879         if (intr_handle->intr_vec) {
1880                 rte_free(intr_handle->intr_vec);
1881                 intr_handle->intr_vec = NULL;
1882         }
1883 }
1884
1885 static void
1886 hns3vf_dev_stop(struct rte_eth_dev *dev)
1887 {
1888         struct hns3_adapter *hns = dev->data->dev_private;
1889         struct hns3_hw *hw = &hns->hw;
1890
1891         PMD_INIT_FUNC_TRACE();
1892
1893         hw->adapter_state = HNS3_NIC_STOPPING;
1894         hns3_set_rxtx_function(dev);
1895         rte_wmb();
1896         /* Disable datapath on secondary process. */
1897         hns3_mp_req_stop_rxtx(dev);
1898         /* Prevent crashes when queues are still in use. */
1899         rte_delay_ms(hw->tqps_num);
1900
1901         rte_spinlock_lock(&hw->lock);
1902         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1903                 hns3vf_do_stop(hns);
1904                 hns3vf_unmap_rx_interrupt(dev);
1905                 hns3_dev_release_mbufs(hns);
1906                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1907         }
1908         hns3_rx_scattered_reset(dev);
1909         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1910         rte_spinlock_unlock(&hw->lock);
1911 }
1912
1913 static void
1914 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1915 {
1916         struct hns3_adapter *hns = eth_dev->data->dev_private;
1917         struct hns3_hw *hw = &hns->hw;
1918
1919         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1920                 return;
1921
1922         if (hw->adapter_state == HNS3_NIC_STARTED)
1923                 hns3vf_dev_stop(eth_dev);
1924
1925         hw->adapter_state = HNS3_NIC_CLOSING;
1926         hns3_reset_abort(hns);
1927         hw->adapter_state = HNS3_NIC_CLOSED;
1928         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1929         hns3vf_configure_all_mc_mac_addr(hns, true);
1930         hns3vf_remove_all_vlan_table(hns);
1931         hns3vf_uninit_vf(eth_dev);
1932         hns3_free_all_queues(eth_dev);
1933         rte_free(hw->reset.wait_data);
1934         rte_free(eth_dev->process_private);
1935         eth_dev->process_private = NULL;
1936         hns3_mp_uninit_primary();
1937         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1938 }
1939
1940 static int
1941 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1942                       size_t fw_size)
1943 {
1944         struct hns3_adapter *hns = eth_dev->data->dev_private;
1945         struct hns3_hw *hw = &hns->hw;
1946         uint32_t version = hw->fw_version;
1947         int ret;
1948
1949         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1950                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1951                                       HNS3_FW_VERSION_BYTE3_S),
1952                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1953                                       HNS3_FW_VERSION_BYTE2_S),
1954                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1955                                       HNS3_FW_VERSION_BYTE1_S),
1956                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1957                                       HNS3_FW_VERSION_BYTE0_S));
1958         ret += 1; /* add the size of '\0' */
1959         if (fw_size < (uint32_t)ret)
1960                 return ret;
1961         else
1962                 return 0;
1963 }
1964
1965 static int
1966 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1967                        __rte_unused int wait_to_complete)
1968 {
1969         struct hns3_adapter *hns = eth_dev->data->dev_private;
1970         struct hns3_hw *hw = &hns->hw;
1971         struct hns3_mac *mac = &hw->mac;
1972         struct rte_eth_link new_link;
1973
1974         memset(&new_link, 0, sizeof(new_link));
1975         switch (mac->link_speed) {
1976         case ETH_SPEED_NUM_10M:
1977         case ETH_SPEED_NUM_100M:
1978         case ETH_SPEED_NUM_1G:
1979         case ETH_SPEED_NUM_10G:
1980         case ETH_SPEED_NUM_25G:
1981         case ETH_SPEED_NUM_40G:
1982         case ETH_SPEED_NUM_50G:
1983         case ETH_SPEED_NUM_100G:
1984         case ETH_SPEED_NUM_200G:
1985                 new_link.link_speed = mac->link_speed;
1986                 break;
1987         default:
1988                 new_link.link_speed = ETH_SPEED_NUM_100M;
1989                 break;
1990         }
1991
1992         new_link.link_duplex = mac->link_duplex;
1993         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1994         new_link.link_autoneg =
1995             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1996
1997         return rte_eth_linkstatus_set(eth_dev, &new_link);
1998 }
1999
2000 static int
2001 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2002 {
2003         struct hns3_hw *hw = &hns->hw;
2004         int ret;
2005
2006         ret = hns3vf_set_tc_info(hns);
2007         if (ret)
2008                 return ret;
2009
2010         ret = hns3_start_queues(hns, reset_queue);
2011         if (ret)
2012                 hns3_err(hw, "Failed to start queues: %d", ret);
2013
2014         return ret;
2015 }
2016
2017 static int
2018 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2019 {
2020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2022         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2024         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2025         uint32_t intr_vector;
2026         uint16_t q_id;
2027         int ret;
2028
2029         if (dev->data->dev_conf.intr_conf.rxq == 0)
2030                 return 0;
2031
2032         /* disable uio/vfio intr/eventfd mapping */
2033         rte_intr_disable(intr_handle);
2034
2035         /* check and configure queue intr-vector mapping */
2036         if (rte_intr_cap_multiple(intr_handle) ||
2037             !RTE_ETH_DEV_SRIOV(dev).active) {
2038                 intr_vector = hw->used_rx_queues;
2039                 /* It creates event fd for each intr vector when MSIX is used */
2040                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2041                         return -EINVAL;
2042         }
2043         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2044                 intr_handle->intr_vec =
2045                         rte_zmalloc("intr_vec",
2046                                     hw->used_rx_queues * sizeof(int), 0);
2047                 if (intr_handle->intr_vec == NULL) {
2048                         hns3_err(hw, "Failed to allocate %d rx_queues"
2049                                      " intr_vec", hw->used_rx_queues);
2050                         ret = -ENOMEM;
2051                         goto vf_alloc_intr_vec_error;
2052                 }
2053         }
2054
2055         if (rte_intr_allow_others(intr_handle)) {
2056                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2057                 base = RTE_INTR_VEC_RXTX_OFFSET;
2058         }
2059         if (rte_intr_dp_is_en(intr_handle)) {
2060                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2061                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2062                                                            HNS3_RING_TYPE_RX,
2063                                                            q_id);
2064                         if (ret)
2065                                 goto vf_bind_vector_error;
2066                         intr_handle->intr_vec[q_id] = vec;
2067                         if (vec < base + intr_handle->nb_efd - 1)
2068                                 vec++;
2069                 }
2070         }
2071         rte_intr_enable(intr_handle);
2072         return 0;
2073
2074 vf_bind_vector_error:
2075         rte_intr_efd_disable(intr_handle);
2076         if (intr_handle->intr_vec) {
2077                 free(intr_handle->intr_vec);
2078                 intr_handle->intr_vec = NULL;
2079         }
2080         return ret;
2081 vf_alloc_intr_vec_error:
2082         rte_intr_efd_disable(intr_handle);
2083         return ret;
2084 }
2085
2086 static int
2087 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2088 {
2089         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2090         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2091         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2092         uint16_t q_id;
2093         int ret;
2094
2095         if (dev->data->dev_conf.intr_conf.rxq == 0)
2096                 return 0;
2097
2098         if (rte_intr_dp_is_en(intr_handle)) {
2099                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2100                         ret = hns3vf_bind_ring_with_vector(hw,
2101                                         intr_handle->intr_vec[q_id], true,
2102                                         HNS3_RING_TYPE_RX, q_id);
2103                         if (ret)
2104                                 return ret;
2105                 }
2106         }
2107
2108         return 0;
2109 }
2110
2111 static void
2112 hns3vf_restore_filter(struct rte_eth_dev *dev)
2113 {
2114         hns3_restore_rss_filter(dev);
2115 }
2116
2117 static int
2118 hns3vf_dev_start(struct rte_eth_dev *dev)
2119 {
2120         struct hns3_adapter *hns = dev->data->dev_private;
2121         struct hns3_hw *hw = &hns->hw;
2122         int ret;
2123
2124         PMD_INIT_FUNC_TRACE();
2125         if (rte_atomic16_read(&hw->reset.resetting))
2126                 return -EBUSY;
2127
2128         rte_spinlock_lock(&hw->lock);
2129         hw->adapter_state = HNS3_NIC_STARTING;
2130         ret = hns3vf_do_start(hns, true);
2131         if (ret) {
2132                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2133                 rte_spinlock_unlock(&hw->lock);
2134                 return ret;
2135         }
2136         ret = hns3vf_map_rx_interrupt(dev);
2137         if (ret) {
2138                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2139                 rte_spinlock_unlock(&hw->lock);
2140                 return ret;
2141         }
2142         hw->adapter_state = HNS3_NIC_STARTED;
2143         rte_spinlock_unlock(&hw->lock);
2144
2145         hns3_rx_scattered_calc(dev);
2146         hns3_set_rxtx_function(dev);
2147         hns3_mp_req_start_rxtx(dev);
2148         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2149
2150         hns3vf_restore_filter(dev);
2151
2152         /* Enable interrupt of all rx queues before enabling queues */
2153         hns3_dev_all_rx_queue_intr_enable(hw, true);
2154         /*
2155          * When finished the initialization, enable queues to receive/transmit
2156          * packets.
2157          */
2158         hns3_enable_all_queues(hw, true);
2159
2160         return ret;
2161 }
2162
2163 static bool
2164 is_vf_reset_done(struct hns3_hw *hw)
2165 {
2166 #define HNS3_FUN_RST_ING_BITS \
2167         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2168          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2169          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2170          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2171
2172         uint32_t val;
2173
2174         if (hw->reset.level == HNS3_VF_RESET) {
2175                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2176                 if (val & HNS3_VF_RST_ING_BIT)
2177                         return false;
2178         } else {
2179                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2180                 if (val & HNS3_FUN_RST_ING_BITS)
2181                         return false;
2182         }
2183         return true;
2184 }
2185
2186 bool
2187 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2188 {
2189         struct hns3_hw *hw = &hns->hw;
2190         enum hns3_reset_level reset;
2191
2192         hns3vf_check_event_cause(hns, NULL);
2193         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2194         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2195                 hns3_warn(hw, "High level reset %d is pending", reset);
2196                 return true;
2197         }
2198         return false;
2199 }
2200
2201 static int
2202 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2203 {
2204         struct hns3_hw *hw = &hns->hw;
2205         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2206         struct timeval tv;
2207
2208         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2209                 /*
2210                  * After vf reset is ready, the PF may not have completed
2211                  * the reset processing. The vf sending mbox to PF may fail
2212                  * during the pf reset, so it is better to add extra delay.
2213                  */
2214                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2215                     hw->reset.level == HNS3_FLR_RESET)
2216                         return 0;
2217                 /* Reset retry process, no need to add extra delay. */
2218                 if (hw->reset.attempts)
2219                         return 0;
2220                 if (wait_data->check_completion == NULL)
2221                         return 0;
2222
2223                 wait_data->check_completion = NULL;
2224                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2225                 wait_data->count = 1;
2226                 wait_data->result = HNS3_WAIT_REQUEST;
2227                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2228                                   wait_data);
2229                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2230                 return -EAGAIN;
2231         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2232                 gettimeofday(&tv, NULL);
2233                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2234                           tv.tv_sec, tv.tv_usec);
2235                 return -ETIME;
2236         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2237                 return -EAGAIN;
2238
2239         wait_data->hns = hns;
2240         wait_data->check_completion = is_vf_reset_done;
2241         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2242                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2243         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2244         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2245         wait_data->result = HNS3_WAIT_REQUEST;
2246         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2247         return -EAGAIN;
2248 }
2249
2250 static int
2251 hns3vf_prepare_reset(struct hns3_adapter *hns)
2252 {
2253         struct hns3_hw *hw = &hns->hw;
2254         int ret = 0;
2255
2256         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2257                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2258                                         0, true, NULL, 0);
2259         }
2260         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2261
2262         return ret;
2263 }
2264
2265 static int
2266 hns3vf_stop_service(struct hns3_adapter *hns)
2267 {
2268         struct hns3_hw *hw = &hns->hw;
2269         struct rte_eth_dev *eth_dev;
2270
2271         eth_dev = &rte_eth_devices[hw->data->port_id];
2272         if (hw->adapter_state == HNS3_NIC_STARTED)
2273                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2274         hw->mac.link_status = ETH_LINK_DOWN;
2275
2276         hns3_set_rxtx_function(eth_dev);
2277         rte_wmb();
2278         /* Disable datapath on secondary process. */
2279         hns3_mp_req_stop_rxtx(eth_dev);
2280         rte_delay_ms(hw->tqps_num);
2281
2282         rte_spinlock_lock(&hw->lock);
2283         if (hw->adapter_state == HNS3_NIC_STARTED ||
2284             hw->adapter_state == HNS3_NIC_STOPPING) {
2285                 hns3vf_do_stop(hns);
2286                 hw->reset.mbuf_deferred_free = true;
2287         } else
2288                 hw->reset.mbuf_deferred_free = false;
2289
2290         /*
2291          * It is cumbersome for hardware to pick-and-choose entries for deletion
2292          * from table space. Hence, for function reset software intervention is
2293          * required to delete the entries.
2294          */
2295         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2296                 hns3vf_configure_all_mc_mac_addr(hns, true);
2297         rte_spinlock_unlock(&hw->lock);
2298
2299         return 0;
2300 }
2301
2302 static int
2303 hns3vf_start_service(struct hns3_adapter *hns)
2304 {
2305         struct hns3_hw *hw = &hns->hw;
2306         struct rte_eth_dev *eth_dev;
2307
2308         eth_dev = &rte_eth_devices[hw->data->port_id];
2309         hns3_set_rxtx_function(eth_dev);
2310         hns3_mp_req_start_rxtx(eth_dev);
2311         if (hw->adapter_state == HNS3_NIC_STARTED) {
2312                 hns3vf_service_handler(eth_dev);
2313
2314                 /* Enable interrupt of all rx queues before enabling queues */
2315                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2316                 /*
2317                  * When finished the initialization, enable queues to receive
2318                  * and transmit packets.
2319                  */
2320                 hns3_enable_all_queues(hw, true);
2321         }
2322
2323         return 0;
2324 }
2325
2326 static int
2327 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2328 {
2329         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2330         struct rte_ether_addr *hw_mac;
2331         int ret;
2332
2333         /*
2334          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2335          * on the host by "ip link set ..." command. If the hns3 PF kernel
2336          * ethdev driver sets the MAC address for VF device after the
2337          * initialization of the related VF device, the PF driver will notify
2338          * VF driver to reset VF device to make the new MAC address effective
2339          * immediately. The hns3 VF PMD driver should check whether the MAC
2340          * address has been changed by the PF kernel ethdev driver, if changed
2341          * VF driver should configure hardware using the new MAC address in the
2342          * recovering hardware configuration stage of the reset process.
2343          */
2344         ret = hns3vf_get_host_mac_addr(hw);
2345         if (ret)
2346                 return ret;
2347
2348         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2349         ret = rte_is_zero_ether_addr(hw_mac);
2350         if (ret) {
2351                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2352         } else {
2353                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2354                 if (!ret) {
2355                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2356                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2357                                               &hw->data->mac_addrs[0]);
2358                         hns3_warn(hw, "Default MAC address has been changed to:"
2359                                   " %s by the host PF kernel ethdev driver",
2360                                   mac_str);
2361                 }
2362         }
2363
2364         return 0;
2365 }
2366
2367 static int
2368 hns3vf_restore_conf(struct hns3_adapter *hns)
2369 {
2370         struct hns3_hw *hw = &hns->hw;
2371         int ret;
2372
2373         ret = hns3vf_check_default_mac_change(hw);
2374         if (ret)
2375                 return ret;
2376
2377         ret = hns3vf_configure_mac_addr(hns, false);
2378         if (ret)
2379                 return ret;
2380
2381         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2382         if (ret)
2383                 goto err_mc_mac;
2384
2385         ret = hns3vf_restore_promisc(hns);
2386         if (ret)
2387                 goto err_vlan_table;
2388
2389         ret = hns3vf_restore_vlan_conf(hns);
2390         if (ret)
2391                 goto err_vlan_table;
2392
2393         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2394         if (ret)
2395                 goto err_vlan_table;
2396
2397         ret = hns3vf_restore_rx_interrupt(hw);
2398         if (ret)
2399                 goto err_vlan_table;
2400
2401         ret = hns3_restore_gro_conf(hw);
2402         if (ret)
2403                 goto err_vlan_table;
2404
2405         if (hw->adapter_state == HNS3_NIC_STARTED) {
2406                 ret = hns3vf_do_start(hns, false);
2407                 if (ret)
2408                         goto err_vlan_table;
2409                 hns3_info(hw, "hns3vf dev restart successful!");
2410         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2411                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2412         return 0;
2413
2414 err_vlan_table:
2415         hns3vf_configure_all_mc_mac_addr(hns, true);
2416 err_mc_mac:
2417         hns3vf_configure_mac_addr(hns, true);
2418         return ret;
2419 }
2420
2421 static enum hns3_reset_level
2422 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2423 {
2424         enum hns3_reset_level reset_level;
2425
2426         /* return the highest priority reset level amongst all */
2427         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2428                 reset_level = HNS3_VF_RESET;
2429         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2430                 reset_level = HNS3_VF_FULL_RESET;
2431         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2432                 reset_level = HNS3_VF_PF_FUNC_RESET;
2433         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2434                 reset_level = HNS3_VF_FUNC_RESET;
2435         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2436                 reset_level = HNS3_FLR_RESET;
2437         else
2438                 reset_level = HNS3_NONE_RESET;
2439
2440         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2441                 return HNS3_NONE_RESET;
2442
2443         return reset_level;
2444 }
2445
2446 static void
2447 hns3vf_reset_service(void *param)
2448 {
2449         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2450         struct hns3_hw *hw = &hns->hw;
2451         enum hns3_reset_level reset_level;
2452         struct timeval tv_delta;
2453         struct timeval tv_start;
2454         struct timeval tv;
2455         uint64_t msec;
2456
2457         /*
2458          * The interrupt is not triggered within the delay time.
2459          * The interrupt may have been lost. It is necessary to handle
2460          * the interrupt to recover from the error.
2461          */
2462         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2463                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2464                 hns3_err(hw, "Handling interrupts in delayed tasks");
2465                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2466                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2467                 if (reset_level == HNS3_NONE_RESET) {
2468                         hns3_err(hw, "No reset level is set, try global reset");
2469                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2470                 }
2471         }
2472         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2473
2474         /*
2475          * Hardware reset has been notified, we now have to poll & check if
2476          * hardware has actually completed the reset sequence.
2477          */
2478         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2479         if (reset_level != HNS3_NONE_RESET) {
2480                 gettimeofday(&tv_start, NULL);
2481                 hns3_reset_process(hns, reset_level);
2482                 gettimeofday(&tv, NULL);
2483                 timersub(&tv, &tv_start, &tv_delta);
2484                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2485                        tv_delta.tv_usec / USEC_PER_MSEC;
2486                 if (msec > HNS3_RESET_PROCESS_MS)
2487                         hns3_err(hw, "%d handle long time delta %" PRIx64
2488                                  " ms time=%ld.%.6ld",
2489                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2490         }
2491 }
2492
2493 static int
2494 hns3vf_reinit_dev(struct hns3_adapter *hns)
2495 {
2496         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2497         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2498         struct hns3_hw *hw = &hns->hw;
2499         int ret;
2500
2501         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2502                 rte_intr_disable(&pci_dev->intr_handle);
2503                 hns3vf_set_bus_master(pci_dev, true);
2504         }
2505
2506         /* Firmware command initialize */
2507         ret = hns3_cmd_init(hw);
2508         if (ret) {
2509                 hns3_err(hw, "Failed to init cmd: %d", ret);
2510                 return ret;
2511         }
2512
2513         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2514                 /*
2515                  * UIO enables msix by writing the pcie configuration space
2516                  * vfio_pci enables msix in rte_intr_enable.
2517                  */
2518                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2519                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2520                         if (hns3vf_enable_msix(pci_dev, true))
2521                                 hns3_err(hw, "Failed to enable msix");
2522                 }
2523
2524                 rte_intr_enable(&pci_dev->intr_handle);
2525         }
2526
2527         ret = hns3_reset_all_queues(hns);
2528         if (ret) {
2529                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2530                 return ret;
2531         }
2532
2533         ret = hns3vf_init_hardware(hns);
2534         if (ret) {
2535                 hns3_err(hw, "Failed to init hardware: %d", ret);
2536                 return ret;
2537         }
2538
2539         return 0;
2540 }
2541
2542 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2543         .dev_configure      = hns3vf_dev_configure,
2544         .dev_start          = hns3vf_dev_start,
2545         .dev_stop           = hns3vf_dev_stop,
2546         .dev_close          = hns3vf_dev_close,
2547         .mtu_set            = hns3vf_dev_mtu_set,
2548         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2549         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2550         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2551         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2552         .stats_get          = hns3_stats_get,
2553         .stats_reset        = hns3_stats_reset,
2554         .xstats_get         = hns3_dev_xstats_get,
2555         .xstats_get_names   = hns3_dev_xstats_get_names,
2556         .xstats_reset       = hns3_dev_xstats_reset,
2557         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2558         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2559         .dev_infos_get      = hns3vf_dev_infos_get,
2560         .fw_version_get     = hns3vf_fw_version_get,
2561         .rx_queue_setup     = hns3_rx_queue_setup,
2562         .tx_queue_setup     = hns3_tx_queue_setup,
2563         .rx_queue_release   = hns3_dev_rx_queue_release,
2564         .tx_queue_release   = hns3_dev_tx_queue_release,
2565         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2566         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2567         .rxq_info_get       = hns3_rxq_info_get,
2568         .txq_info_get       = hns3_txq_info_get,
2569         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2570         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2571         .mac_addr_add       = hns3vf_add_mac_addr,
2572         .mac_addr_remove    = hns3vf_remove_mac_addr,
2573         .mac_addr_set       = hns3vf_set_default_mac_addr,
2574         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2575         .link_update        = hns3vf_dev_link_update,
2576         .rss_hash_update    = hns3_dev_rss_hash_update,
2577         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2578         .reta_update        = hns3_dev_rss_reta_update,
2579         .reta_query         = hns3_dev_rss_reta_query,
2580         .filter_ctrl        = hns3_dev_filter_ctrl,
2581         .vlan_filter_set    = hns3vf_vlan_filter_set,
2582         .vlan_offload_set   = hns3vf_vlan_offload_set,
2583         .get_reg            = hns3_get_regs,
2584         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2585 };
2586
2587 static const struct hns3_reset_ops hns3vf_reset_ops = {
2588         .reset_service       = hns3vf_reset_service,
2589         .stop_service        = hns3vf_stop_service,
2590         .prepare_reset       = hns3vf_prepare_reset,
2591         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2592         .reinit_dev          = hns3vf_reinit_dev,
2593         .restore_conf        = hns3vf_restore_conf,
2594         .start_service       = hns3vf_start_service,
2595 };
2596
2597 static int
2598 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2599 {
2600         struct hns3_adapter *hns = eth_dev->data->dev_private;
2601         struct hns3_hw *hw = &hns->hw;
2602         int ret;
2603
2604         PMD_INIT_FUNC_TRACE();
2605
2606         eth_dev->process_private = (struct hns3_process_private *)
2607             rte_zmalloc_socket("hns3_filter_list",
2608                                sizeof(struct hns3_process_private),
2609                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2610         if (eth_dev->process_private == NULL) {
2611                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2612                 return -ENOMEM;
2613         }
2614
2615         /* initialize flow filter lists */
2616         hns3_filterlist_init(eth_dev);
2617
2618         hns3_set_rxtx_function(eth_dev);
2619         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2620         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2621                 ret = hns3_mp_init_secondary();
2622                 if (ret) {
2623                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2624                                           "process, ret = %d", ret);
2625                         goto err_mp_init_secondary;
2626                 }
2627
2628                 hw->secondary_cnt++;
2629                 return 0;
2630         }
2631
2632         ret = hns3_mp_init_primary();
2633         if (ret) {
2634                 PMD_INIT_LOG(ERR,
2635                              "Failed to init for primary process, ret = %d",
2636                              ret);
2637                 goto err_mp_init_primary;
2638         }
2639
2640         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2641         hns->is_vf = true;
2642         hw->data = eth_dev->data;
2643
2644         ret = hns3_reset_init(hw);
2645         if (ret)
2646                 goto err_init_reset;
2647         hw->reset.ops = &hns3vf_reset_ops;
2648
2649         ret = hns3vf_init_vf(eth_dev);
2650         if (ret) {
2651                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2652                 goto err_init_vf;
2653         }
2654
2655         /* Allocate memory for storing MAC addresses */
2656         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2657                                                sizeof(struct rte_ether_addr) *
2658                                                HNS3_VF_UC_MACADDR_NUM, 0);
2659         if (eth_dev->data->mac_addrs == NULL) {
2660                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2661                              "to store MAC addresses",
2662                              sizeof(struct rte_ether_addr) *
2663                              HNS3_VF_UC_MACADDR_NUM);
2664                 ret = -ENOMEM;
2665                 goto err_rte_zmalloc;
2666         }
2667
2668         /*
2669          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2670          * on the host by "ip link set ..." command. To avoid some incorrect
2671          * scenes, for example, hns3 VF PMD driver fails to receive and send
2672          * packets after user configure the MAC address by using the
2673          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2674          * address strategy as the hns3 kernel ethdev driver in the
2675          * initialization. If user configure a MAC address by the ip command
2676          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2677          * start with a random MAC address in the initialization.
2678          */
2679         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2680                 rte_eth_random_addr(hw->mac.mac_addr);
2681         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2682                             &eth_dev->data->mac_addrs[0]);
2683
2684         hw->adapter_state = HNS3_NIC_INITIALIZED;
2685         /*
2686          * Pass the information to the rte_eth_dev_close() that it should also
2687          * release the private port resources.
2688          */
2689         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2690
2691         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2692                 hns3_err(hw, "Reschedule reset service after dev_init");
2693                 hns3_schedule_reset(hns);
2694         } else {
2695                 /* IMP will wait ready flag before reset */
2696                 hns3_notify_reset_ready(hw, false);
2697         }
2698         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2699                           eth_dev);
2700         return 0;
2701
2702 err_rte_zmalloc:
2703         hns3vf_uninit_vf(eth_dev);
2704
2705 err_init_vf:
2706         rte_free(hw->reset.wait_data);
2707
2708 err_init_reset:
2709         hns3_mp_uninit_primary();
2710
2711 err_mp_init_primary:
2712 err_mp_init_secondary:
2713         eth_dev->dev_ops = NULL;
2714         eth_dev->rx_pkt_burst = NULL;
2715         eth_dev->tx_pkt_burst = NULL;
2716         eth_dev->tx_pkt_prepare = NULL;
2717         rte_free(eth_dev->process_private);
2718         eth_dev->process_private = NULL;
2719
2720         return ret;
2721 }
2722
2723 static int
2724 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2725 {
2726         struct hns3_adapter *hns = eth_dev->data->dev_private;
2727         struct hns3_hw *hw = &hns->hw;
2728
2729         PMD_INIT_FUNC_TRACE();
2730
2731         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2732                 return -EPERM;
2733
2734         eth_dev->dev_ops = NULL;
2735         eth_dev->rx_pkt_burst = NULL;
2736         eth_dev->tx_pkt_burst = NULL;
2737         eth_dev->tx_pkt_prepare = NULL;
2738
2739         if (hw->adapter_state < HNS3_NIC_CLOSING)
2740                 hns3vf_dev_close(eth_dev);
2741
2742         hw->adapter_state = HNS3_NIC_REMOVED;
2743         return 0;
2744 }
2745
2746 static int
2747 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2748                      struct rte_pci_device *pci_dev)
2749 {
2750         return rte_eth_dev_pci_generic_probe(pci_dev,
2751                                              sizeof(struct hns3_adapter),
2752                                              hns3vf_dev_init);
2753 }
2754
2755 static int
2756 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2757 {
2758         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2759 }
2760
2761 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2762         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2763         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2764         { .vendor_id = 0, /* sentinel */ },
2765 };
2766
2767 static struct rte_pci_driver rte_hns3vf_pmd = {
2768         .id_table = pci_id_hns3vf_map,
2769         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2770         .probe = eth_hns3vf_pci_probe,
2771         .remove = eth_hns3vf_pci_remove,
2772 };
2773
2774 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2775 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2776 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");