drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                 }
 160                 return 0;
 161         }
 162         return -ENXIO;
 163 }
 164
 165 static int
 166 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 167 {
 168         /* mac address was checked by upper level interface */
 169         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 170         int ret;
 171
 172         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 173                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 174                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 175         if (ret) {
 176                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 177                                       mac_addr);
 178                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 179                          mac_str, ret);
 180         }
 181         return ret;
 182 }
 183
 184 static int
 185 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 186 {
 187         /* mac address was checked by upper level interface */
 188         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 189         int ret;
 190
 191         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 192                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 193                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 194                                 false, NULL, 0);
 195         if (ret) {
 196                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 197                                       mac_addr);
 198                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 199                          mac_str, ret);
 200         }
 201         return ret;
 202 }
 203
 204 static int
 205 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 206 {
 207         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 208         struct rte_ether_addr *addr;
 209         int ret;
 210         int i;
 211
 212         for (i = 0; i < hw->mc_addrs_num; i++) {
 213                 addr = &hw->mc_addrs[i];
 214                 /* Check if there are duplicate addresses */
 215                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 216                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 217                                               addr);
 218                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 219                                  "(%s) is added by the set_mc_mac_addr_list "
 220                                  "API", mac_str);
 221                         return -EINVAL;
 222                 }
 223         }
 224
 225         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 226         if (ret) {
 227                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 228                                       mac_addr);
 229                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 230                          mac_str, ret);
 231         }
 232         return ret;
 233 }
 234
 235 static int
 236 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 237                     __rte_unused uint32_t idx,
 238                     __rte_unused uint32_t pool)
 239 {
 240         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 241         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 242         int ret;
 243
 244         rte_spinlock_lock(&hw->lock);
 245
 246         /*
 247          * In hns3 network engine adding UC and MC mac address with different
 248          * commands with firmware. We need to determine whether the input
 249          * address is a UC or a MC address to call different commands.
 250          * By the way, it is recommended calling the API function named
 251          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 252          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 253          * may affect the specifications of UC mac addresses.
 254          */
 255         if (rte_is_multicast_ether_addr(mac_addr))
 256                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 257         else
 258                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 259
 260         rte_spinlock_unlock(&hw->lock);
 261         if (ret) {
 262                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 263                                       mac_addr);
 264                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 265                          ret);
 266         }
 267
 268         return ret;
 269 }
 270
 271 static void
 272 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 273 {
 274         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 275         /* index will be checked by upper level rte interface */
 276         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 277         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 278         int ret;
 279
 280         rte_spinlock_lock(&hw->lock);
 281
 282         if (rte_is_multicast_ether_addr(mac_addr))
 283                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 284         else
 285                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 286
 287         rte_spinlock_unlock(&hw->lock);
 288         if (ret) {
 289                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 290                                       mac_addr);
 291                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 292                          mac_str, ret);
 293         }
 294 }
 295
 296 static int
 297 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 298                             struct rte_ether_addr *mac_addr)
 299 {
 300 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 301         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 302         struct rte_ether_addr *old_addr;
 303         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 304         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 305         int ret;
 306
 307         /*
 308          * It has been guaranteed that input parameter named mac_addr is valid
 309          * address in the rte layer of DPDK framework.
 310          */
 311         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 312         rte_spinlock_lock(&hw->lock);
 313         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 314         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 315                RTE_ETHER_ADDR_LEN);
 316
 317         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 318                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 319                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 320         if (ret) {
 321                 /*
 322                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 323                  * driver. When user has configured a MAC address for VF device
 324                  * by "ip link set ..." command based on the PF device, the hns3
 325                  * PF kernel ethdev driver does not allow VF driver to request
 326                  * reconfiguring a different default MAC address, and return
 327                  * -EPREM to VF driver through mailbox.
 328                  */
 329                 if (ret == -EPERM) {
 330                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 331                                               old_addr);
 332                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 333                                   mac_str);
 334                 } else {
 335                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 336                                               mac_addr);
 337                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 338                                  mac_str, ret);
 339                 }
 340         }
 341
 342         rte_ether_addr_copy(mac_addr,
 343                             (struct rte_ether_addr *)hw->mac.mac_addr);
 344         rte_spinlock_unlock(&hw->lock);
 345
 346         return ret;
 347 }
 348
 349 static int
 350 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 351 {
 352         struct hns3_hw *hw = &hns->hw;
 353         struct rte_ether_addr *addr;
 354         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 355         int err = 0;
 356         int ret;
 357         int i;
 358
 359         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 360                 addr = &hw->data->mac_addrs[i];
 361                 if (rte_is_zero_ether_addr(addr))
 362                         continue;
 363                 if (rte_is_multicast_ether_addr(addr))
 364                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 365                               hns3vf_add_mc_mac_addr(hw, addr);
 366                 else
 367                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 368                               hns3vf_add_uc_mac_addr(hw, addr);
 369
 370                 if (ret) {
 371                         err = ret;
 372                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 373                                               addr);
 374                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 375                                  "ret = %d.", del ? "remove" : "restore",
 376                                  mac_str, i, ret);
 377                 }
 378         }
 379         return err;
 380 }
 381
 382 static int
 383 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 384                        struct rte_ether_addr *mac_addr)
 385 {
 386         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 387         int ret;
 388
 389         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 390                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 391                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 392                                 NULL, 0);
 393         if (ret) {
 394                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 395                                       mac_addr);
 396                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 397                          mac_str, ret);
 398         }
 399
 400         return ret;
 401 }
 402
 403 static int
 404 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 405                           struct rte_ether_addr *mac_addr)
 406 {
 407         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 408         int ret;
 409
 410         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 411                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 412                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 413                                 NULL, 0);
 414         if (ret) {
 415                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 416                                       mac_addr);
 417                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 418                          mac_str, ret);
 419         }
 420
 421         return ret;
 422 }
 423
 424 static int
 425 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 426                              struct rte_ether_addr *mc_addr_set,
 427                              uint32_t nb_mc_addr)
 428 {
 429         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 430         struct rte_ether_addr *addr;
 431         uint32_t i;
 432         uint32_t j;
 433
 434         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 435                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 436                          "invalid. valid range: 0~%d",
 437                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 438                 return -EINVAL;
 439         }
 440
 441         /* Check if input mac addresses are valid */
 442         for (i = 0; i < nb_mc_addr; i++) {
 443                 addr = &mc_addr_set[i];
 444                 if (!rte_is_multicast_ether_addr(addr)) {
 445                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 446                                               addr);
 447                         hns3_err(hw,
 448                                  "failed to set mc mac addr, addr(%s) invalid.",
 449                                  mac_str);
 450                         return -EINVAL;
 451                 }
 452
 453                 /* Check if there are duplicate addresses */
 454                 for (j = i + 1; j < nb_mc_addr; j++) {
 455                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 456                                 hns3_ether_format_addr(mac_str,
 457                                                       RTE_ETHER_ADDR_FMT_SIZE,
 458                                                       addr);
 459                                 hns3_err(hw, "failed to set mc mac addr, "
 460                                          "addrs invalid. two same addrs(%s).",
 461                                          mac_str);
 462                                 return -EINVAL;
 463                         }
 464                 }
 465
 466                 /*
 467                  * Check if there are duplicate addresses between mac_addrs
 468                  * and mc_addr_set
 469                  */
 470                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 471                         if (rte_is_same_ether_addr(addr,
 472                                                    &hw->data->mac_addrs[j])) {
 473                                 hns3_ether_format_addr(mac_str,
 474                                                       RTE_ETHER_ADDR_FMT_SIZE,
 475                                                       addr);
 476                                 hns3_err(hw, "failed to set mc mac addr, "
 477                                          "addrs invalid. addrs(%s) has already "
 478                                          "configured in mac_addr add API",
 479                                          mac_str);
 480                                 return -EINVAL;
 481                         }
 482                 }
 483         }
 484
 485         return 0;
 486 }
 487
 488 static int
 489 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 490                             struct rte_ether_addr *mc_addr_set,
 491                             uint32_t nb_mc_addr)
 492 {
 493         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 494         struct rte_ether_addr *addr;
 495         int cur_addr_num;
 496         int set_addr_num;
 497         int num;
 498         int ret;
 499         int i;
 500
 501         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 502         if (ret)
 503                 return ret;
 504
 505         rte_spinlock_lock(&hw->lock);
 506         cur_addr_num = hw->mc_addrs_num;
 507         for (i = 0; i < cur_addr_num; i++) {
 508                 num = cur_addr_num - i - 1;
 509                 addr = &hw->mc_addrs[num];
 510                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 511                 if (ret) {
 512                         rte_spinlock_unlock(&hw->lock);
 513                         return ret;
 514                 }
 515
 516                 hw->mc_addrs_num--;
 517         }
 518
 519         set_addr_num = (int)nb_mc_addr;
 520         for (i = 0; i < set_addr_num; i++) {
 521                 addr = &mc_addr_set[i];
 522                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 523                 if (ret) {
 524                         rte_spinlock_unlock(&hw->lock);
 525                         return ret;
 526                 }
 527
 528                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 529                 hw->mc_addrs_num++;
 530         }
 531         rte_spinlock_unlock(&hw->lock);
 532
 533         return 0;
 534 }
 535
 536 static int
 537 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 538 {
 539         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 540         struct hns3_hw *hw = &hns->hw;
 541         struct rte_ether_addr *addr;
 542         int err = 0;
 543         int ret;
 544         int i;
 545
 546         for (i = 0; i < hw->mc_addrs_num; i++) {
 547                 addr = &hw->mc_addrs[i];
 548                 if (!rte_is_multicast_ether_addr(addr))
 549                         continue;
 550                 if (del)
 551                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 552                 else
 553                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 554                 if (ret) {
 555                         err = ret;
 556                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 557                                               addr);
 558                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 559                                  del ? "Remove" : "Restore", mac_str, ret);
 560                 }
 561         }
 562         return err;
 563 }
 564
 565 static int
 566 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 567                         bool en_uc_pmc, bool en_mc_pmc)
 568 {
 569         struct hns3_mbx_vf_to_pf_cmd *req;
 570         struct hns3_cmd_desc desc;
 571         int ret;
 572
 573         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 574
 575         /*
 576          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 577          * so there are some features for promiscuous/allmulticast mode in hns3
 578          * VF PMD driver as below:
 579          * 1. The promiscuous/allmulticast mode can be configured successfully
 580          *    only based on the trusted VF device. If based on the non trusted
 581          *    VF device, configuring promiscuous/allmulticast mode will fail.
 582          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 583          *    kernel ethdev driver on the host by the following command:
 584          *      "ip link set <eth num> vf <vf id> turst on"
 585          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 586          *    driver can receive the ingress and outgoing traffic. In the words,
 587          *    all the ingress packets, all the packets sent from the PF and
 588          *    other VFs on the same physical port.
 589          * 3. Note: Because of the hardware constraints, By default vlan filter
 590          *    is enabled and couldn't be turned off based on VF device, so vlan
 591          *    filter is still effective even in promiscuous mode. If upper
 592          *    applications don't call rte_eth_dev_vlan_filter API function to
 593          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 594          *    the packets with vlan tag in promiscuoue mode.
 595          */
 596         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 597         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 598         req->msg[1] = en_bc_pmc ? 1 : 0;
 599         req->msg[2] = en_uc_pmc ? 1 : 0;
 600         req->msg[3] = en_mc_pmc ? 1 : 0;
 601         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 602
 603         ret = hns3_cmd_send(hw, &desc, 1);
 604         if (ret)
 605                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 606
 607         return ret;
 608 }
 609
 610 static int
 611 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 612 {
 613         struct hns3_adapter *hns = dev->data->dev_private;
 614         struct hns3_hw *hw = &hns->hw;
 615         int ret;
 616
 617         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 618         if (ret)
 619                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 620                         ret);
 621         return ret;
 622 }
 623
 624 static int
 625 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 626 {
 627         bool allmulti = dev->data->all_multicast ? true : false;
 628         struct hns3_adapter *hns = dev->data->dev_private;
 629         struct hns3_hw *hw = &hns->hw;
 630         int ret;
 631
 632         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 633         if (ret)
 634                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 635                         ret);
 636         return ret;
 637 }
 638
 639 static int
 640 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 641 {
 642         struct hns3_adapter *hns = dev->data->dev_private;
 643         struct hns3_hw *hw = &hns->hw;
 644         int ret;
 645
 646         if (dev->data->promiscuous)
 647                 return 0;
 648
 649         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 650         if (ret)
 651                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 652                         ret);
 653         return ret;
 654 }
 655
 656 static int
 657 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 658 {
 659         struct hns3_adapter *hns = dev->data->dev_private;
 660         struct hns3_hw *hw = &hns->hw;
 661         int ret;
 662
 663         if (dev->data->promiscuous)
 664                 return 0;
 665
 666         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 667         if (ret)
 668                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 669                         ret);
 670         return ret;
 671 }
 672
 673 static int
 674 hns3vf_restore_promisc(struct hns3_adapter *hns)
 675 {
 676         struct hns3_hw *hw = &hns->hw;
 677         bool allmulti = hw->data->all_multicast ? true : false;
 678
 679         if (hw->data->promiscuous)
 680                 return hns3vf_set_promisc_mode(hw, true, true, true);
 681
 682         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 683 }
 684
 685 static int
 686 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 687                              bool mmap, enum hns3_ring_type queue_type,
 688                              uint16_t queue_id)
 689 {
 690         struct hns3_vf_bind_vector_msg bind_msg;
 691         const char *op_str;
 692         uint16_t code;
 693         int ret;
 694
 695         memset(&bind_msg, 0, sizeof(bind_msg));
 696         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 697                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 698         bind_msg.vector_id = vector_id;
 699
 700         if (queue_type == HNS3_RING_TYPE_RX)
 701                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 702         else
 703                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 704
 705         bind_msg.param[0].ring_type = queue_type;
 706         bind_msg.ring_num = 1;
 707         bind_msg.param[0].tqp_index = queue_id;
 708         op_str = mmap ? "Map" : "Unmap";
 709         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 710                                 sizeof(bind_msg), false, NULL, 0);
 711         if (ret)
 712                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 713                          op_str, queue_id, bind_msg.vector_id, ret);
 714
 715         return ret;
 716 }
 717
 718 static int
 719 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 720 {
 721         uint16_t vec;
 722         int ret;
 723         int i;
 724
 725         /*
 726          * In hns3 network engine, vector 0 is always the misc interrupt of this
 727          * function, vector 1~N can be used respectively for the queues of the
 728          * function. Tx and Rx queues with the same number share the interrupt
 729          * vector. In the initialization clearing the all hardware mapping
 730          * relationship configurations between queues and interrupt vectors is
 731          * needed, so some error caused by the residual configurations, such as
 732          * the unexpected Tx interrupt, can be avoid.
 733          */
 734         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 735         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 736                 vec = vec - 1; /* the last interrupt is reserved */
 737         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 738         for (i = 0; i < hw->intr_tqps_num; i++) {
 739                 /*
 740                  * Set gap limiter/rate limiter/quanity limiter algorithm
 741                  * configuration for interrupt coalesce of queue's interrupt.
 742                  */
 743                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 744                                        HNS3_TQP_INTR_GL_DEFAULT);
 745                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 746                                        HNS3_TQP_INTR_GL_DEFAULT);
 747                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 748                 /*
 749                  * QL(quantity limiter) is not used currently, just set 0 to
 750                  * close it.
 751                  */
 752                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 753
 754                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 755                                                    HNS3_RING_TYPE_TX, i);
 756                 if (ret) {
 757                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 758                                           "vector: %u, ret=%d", i, vec, ret);
 759                         return ret;
 760                 }
 761
 762                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 763                                                    HNS3_RING_TYPE_RX, i);
 764                 if (ret) {
 765                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 766                                           "vector: %u, ret=%d", i, vec, ret);
 767                         return ret;
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int
 775 hns3vf_dev_configure(struct rte_eth_dev *dev)
 776 {
 777         struct hns3_adapter *hns = dev->data->dev_private;
 778         struct hns3_hw *hw = &hns->hw;
 779         struct rte_eth_conf *conf = &dev->data->dev_conf;
 780         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 781         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 782         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 783         struct rte_eth_rss_conf rss_conf;
 784         uint32_t max_rx_pkt_len;
 785         uint16_t mtu;
 786         bool gro_en;
 787         int ret;
 788
 789         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 790
 791         /*
 792          * Some versions of hardware network engine does not support
 793          * individually enable/disable/reset the Tx or Rx queue. These devices
 794          * must enable/disable/reset Tx and Rx queues at the same time. When the
 795          * numbers of Tx queues allocated by upper applications are not equal to
 796          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 797          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 798          * work as usual. But these fake queues are imperceptible, and can not
 799          * be used by upper applications.
 800          */
 801         if (!hns3_dev_indep_txrx_supported(hw)) {
 802                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 803                 if (ret) {
 804                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 805                                  ret);
 806                         return ret;
 807                 }
 808         }
 809
 810         hw->adapter_state = HNS3_NIC_CONFIGURING;
 811         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 812                 hns3_err(hw, "setting link speed/duplex not supported");
 813                 ret = -EINVAL;
 814                 goto cfg_err;
 815         }
 816
 817         /* When RSS is not configured, redirect the packet queue 0 */
 818         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 819                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 820                 hw->rss_dis_flag = false;
 821                 rss_conf = conf->rx_adv_conf.rss_conf;
 822                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 823                 if (ret)
 824                         goto cfg_err;
 825         }
 826
 827         /*
 828          * If jumbo frames are enabled, MTU needs to be refreshed
 829          * according to the maximum RX packet length.
 830          */
 831         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 832                 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
 833                 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
 834                     max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
 835                         hns3_err(hw, "maximum Rx packet length must be greater "
 836                                  "than %u and less than %u when jumbo frame enabled.",
 837                                  (uint16_t)HNS3_DEFAULT_FRAME_LEN,
 838                                  (uint16_t)HNS3_MAX_FRAME_LEN);
 839                         ret = -EINVAL;
 840                         goto cfg_err;
 841                 }
 842
 843                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
 844                 ret = hns3vf_dev_mtu_set(dev, mtu);
 845                 if (ret)
 846                         goto cfg_err;
 847                 dev->data->mtu = mtu;
 848         }
 849
 850         ret = hns3vf_dev_configure_vlan(dev);
 851         if (ret)
 852                 goto cfg_err;
 853
 854         /* config hardware GRO */
 855         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 856         ret = hns3_config_gro(hw, gro_en);
 857         if (ret)
 858                 goto cfg_err;
 859
 860         hns->rx_simple_allowed = true;
 861         hns->rx_vec_allowed = true;
 862         hns->tx_simple_allowed = true;
 863         hns->tx_vec_allowed = true;
 864
 865         hns3_init_rx_ptype_tble(dev);
 866
 867         hw->adapter_state = HNS3_NIC_CONFIGURED;
 868         return 0;
 869
 870 cfg_err:
 871         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 872         hw->adapter_state = HNS3_NIC_INITIALIZED;
 873
 874         return ret;
 875 }
 876
 877 static int
 878 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 879 {
 880         int ret;
 881
 882         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 883                                 sizeof(mtu), true, NULL, 0);
 884         if (ret)
 885                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 886
 887         return ret;
 888 }
 889
 890 static int
 891 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 892 {
 893         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 894         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 895         int ret;
 896
 897         /*
 898          * The hns3 PF/VF devices on the same port share the hardware MTU
 899          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 900          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 901          * driver, there is no need to stop the port for hns3 VF device, and the
 902          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 903          * PF's MTU.
 904          */
 905         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 906                 hns3_err(hw, "Failed to set mtu during resetting");
 907                 return -EIO;
 908         }
 909
 910         /*
 911          * when Rx of scattered packets is off, we have some possibility of
 912          * using vector Rx process function or simple Rx functions in hns3 PMD
 913          * driver. If the input MTU is increased and the maximum length of
 914          * received packets is greater than the length of a buffer for Rx
 915          * packet, the hardware network engine needs to use multiple BDs and
 916          * buffers to store these packets. This will cause problems when still
 917          * using vector Rx process function or simple Rx function to receiving
 918          * packets. So, when Rx of scattered packets is off and device is
 919          * started, it is not permitted to increase MTU so that the maximum
 920          * length of Rx packets is greater than Rx buffer length.
 921          */
 922         if (dev->data->dev_started && !dev->data->scattered_rx &&
 923             frame_size > hw->rx_buf_len) {
 924                 hns3_err(hw, "failed to set mtu because current is "
 925                         "not scattered rx mode");
 926                 return -EOPNOTSUPP;
 927         }
 928
 929         rte_spinlock_lock(&hw->lock);
 930         ret = hns3vf_config_mtu(hw, mtu);
 931         if (ret) {
 932                 rte_spinlock_unlock(&hw->lock);
 933                 return ret;
 934         }
 935         if (mtu > RTE_ETHER_MTU)
 936                 dev->data->dev_conf.rxmode.offloads |=
 937                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 938         else
 939                 dev->data->dev_conf.rxmode.offloads &=
 940                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 941         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 942         rte_spinlock_unlock(&hw->lock);
 943
 944         return 0;
 945 }
 946
 947 static int
 948 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 949 {
 950         struct hns3_adapter *hns = eth_dev->data->dev_private;
 951         struct hns3_hw *hw = &hns->hw;
 952         uint16_t q_num = hw->tqps_num;
 953
 954         /*
 955          * In interrupt mode, 'max_rx_queues' is set based on the number of
 956          * MSI-X interrupt resources of the hardware.
 957          */
 958         if (hw->data->dev_conf.intr_conf.rxq == 1)
 959                 q_num = hw->intr_tqps_num;
 960
 961         info->max_rx_queues = q_num;
 962         info->max_tx_queues = hw->tqps_num;
 963         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 964         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 965         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 966         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 967         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 968
 969         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 970                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 971                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 972                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 973                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 974                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 975                                  DEV_RX_OFFLOAD_SCATTER |
 976                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 977                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 978                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 979                                  DEV_RX_OFFLOAD_RSS_HASH |
 980                                  DEV_RX_OFFLOAD_TCP_LRO);
 981         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 982                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 983                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 984                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 985                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 986                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 987                                  DEV_TX_OFFLOAD_TCP_TSO |
 988                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 989                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 990                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 991                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 992                                  hns3_txvlan_cap_get(hw));
 993
 994         if (hns3_dev_outer_udp_cksum_supported(hw))
 995                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
 996
 997         if (hns3_dev_indep_txrx_supported(hw))
 998                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 999                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1000
1001         info->rx_desc_lim = (struct rte_eth_desc_lim) {
1002                 .nb_max = HNS3_MAX_RING_DESC,
1003                 .nb_min = HNS3_MIN_RING_DESC,
1004                 .nb_align = HNS3_ALIGN_RING_DESC,
1005         };
1006
1007         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1008                 .nb_max = HNS3_MAX_RING_DESC,
1009                 .nb_min = HNS3_MIN_RING_DESC,
1010                 .nb_align = HNS3_ALIGN_RING_DESC,
1011                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1012                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1013         };
1014
1015         info->default_rxconf = (struct rte_eth_rxconf) {
1016                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1017                 /*
1018                  * If there are no available Rx buffer descriptors, incoming
1019                  * packets are always dropped by hardware based on hns3 network
1020                  * engine.
1021                  */
1022                 .rx_drop_en = 1,
1023                 .offloads = 0,
1024         };
1025         info->default_txconf = (struct rte_eth_txconf) {
1026                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1027                 .offloads = 0,
1028         };
1029
1030         info->vmdq_queue_num = 0;
1031
1032         info->reta_size = hw->rss_ind_tbl_size;
1033         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1034         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1035         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1036         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1037
1038         return 0;
1039 }
1040
1041 static void
1042 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1043 {
1044         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1045 }
1046
1047 static void
1048 hns3vf_disable_irq0(struct hns3_hw *hw)
1049 {
1050         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1051 }
1052
1053 static void
1054 hns3vf_enable_irq0(struct hns3_hw *hw)
1055 {
1056         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1057 }
1058
1059 static enum hns3vf_evt_cause
1060 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1061 {
1062         struct hns3_hw *hw = &hns->hw;
1063         enum hns3vf_evt_cause ret;
1064         uint32_t cmdq_stat_reg;
1065         uint32_t rst_ing_reg;
1066         uint32_t val;
1067
1068         /* Fetch the events from their corresponding regs */
1069         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1070         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1071                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1072                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1073                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1074                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1075                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1076                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1077                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1078                 if (clearval) {
1079                         hw->reset.stats.global_cnt++;
1080                         hns3_warn(hw, "Global reset detected, clear reset status");
1081                 } else {
1082                         hns3_schedule_delayed_reset(hns);
1083                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1084                 }
1085
1086                 ret = HNS3VF_VECTOR0_EVENT_RST;
1087                 goto out;
1088         }
1089
1090         /* Check for vector0 mailbox(=CMDQ RX) event source */
1091         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1092                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1093                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1094                 goto out;
1095         }
1096
1097         val = 0;
1098         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1099 out:
1100         if (clearval)
1101                 *clearval = val;
1102         return ret;
1103 }
1104
1105 static void
1106 hns3vf_interrupt_handler(void *param)
1107 {
1108         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1109         struct hns3_adapter *hns = dev->data->dev_private;
1110         struct hns3_hw *hw = &hns->hw;
1111         enum hns3vf_evt_cause event_cause;
1112         uint32_t clearval;
1113
1114         /* Disable interrupt */
1115         hns3vf_disable_irq0(hw);
1116
1117         /* Read out interrupt causes */
1118         event_cause = hns3vf_check_event_cause(hns, &clearval);
1119
1120         switch (event_cause) {
1121         case HNS3VF_VECTOR0_EVENT_RST:
1122                 hns3_schedule_reset(hns);
1123                 break;
1124         case HNS3VF_VECTOR0_EVENT_MBX:
1125                 hns3_dev_handle_mbx_msg(hw);
1126                 break;
1127         default:
1128                 break;
1129         }
1130
1131         /* Clear interrupt causes */
1132         hns3vf_clear_event_cause(hw, clearval);
1133
1134         /* Enable interrupt */
1135         hns3vf_enable_irq0(hw);
1136 }
1137
1138 static void
1139 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1140 {
1141         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1142         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1143         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1144         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1145 }
1146
1147 static void
1148 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1149 {
1150         struct hns3_dev_specs_0_cmd *req0;
1151
1152         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1153
1154         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1155         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1156         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1157         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1158 }
1159
1160 static int
1161 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1162 {
1163         if (hw->rss_ind_tbl_size == 0 ||
1164             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1165                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1166                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1167                               HNS3_RSS_IND_TBL_SIZE_MAX);
1168                 return -EINVAL;
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int
1175 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1176 {
1177         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1178         int ret;
1179         int i;
1180
1181         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1182                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1183                                           true);
1184                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1185         }
1186         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1187
1188         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1189         if (ret)
1190                 return ret;
1191
1192         hns3vf_parse_dev_specifications(hw, desc);
1193
1194         return hns3vf_check_dev_specifications(hw);
1195 }
1196
1197 void
1198 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1199 {
1200         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1201                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1202         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1203         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1204
1205         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1206                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1207                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1208 }
1209
1210 static void
1211 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1212 {
1213 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1214
1215         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1216         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1217         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1218         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1219         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1220
1221         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1222                          __ATOMIC_RELEASE);
1223
1224         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1225                                 NULL, 0);
1226
1227         while (remain_ms > 0) {
1228                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1229                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1230                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1231                         break;
1232                 remain_ms--;
1233         }
1234
1235         /*
1236          * When exit above loop, the pf_push_lsc_cap could be one of the three
1237          * state: unknown (means pf not ack), not_supported, supported.
1238          * Here config it as 'not_supported' when it's 'unknown' state.
1239          */
1240         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1241                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1242
1243         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1244                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1245                 hns3_info(hw, "detect PF support push link status change!");
1246         } else {
1247                 /*
1248                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1249                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1250                  * the RTE_ETH_DEV_INTR_LSC capability.
1251                  */
1252                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1253         }
1254 }
1255
1256 static int
1257 hns3vf_get_capability(struct hns3_hw *hw)
1258 {
1259         struct rte_pci_device *pci_dev;
1260         struct rte_eth_dev *eth_dev;
1261         uint8_t revision;
1262         int ret;
1263
1264         eth_dev = &rte_eth_devices[hw->data->port_id];
1265         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1266
1267         /* Get PCI revision id */
1268         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1269                                   HNS3_PCI_REVISION_ID);
1270         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1271                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1272                              ret);
1273                 return -EIO;
1274         }
1275         hw->revision = revision;
1276
1277         if (revision < PCI_REVISION_ID_HIP09_A) {
1278                 hns3vf_set_default_dev_specifications(hw);
1279                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1280                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1281                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1282                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1283                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1284                 hw->rss_info.ipv6_sctp_offload_supported = false;
1285                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1286                 return 0;
1287         }
1288
1289         ret = hns3vf_query_dev_specifications(hw);
1290         if (ret) {
1291                 PMD_INIT_LOG(ERR,
1292                              "failed to query dev specifications, ret = %d",
1293                              ret);
1294                 return ret;
1295         }
1296
1297         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1298         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1299         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1300         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1301         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1302         hw->rss_info.ipv6_sctp_offload_supported = true;
1303         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1304
1305         return 0;
1306 }
1307
1308 static int
1309 hns3vf_check_tqp_info(struct hns3_hw *hw)
1310 {
1311         if (hw->tqps_num == 0) {
1312                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1313                 return -EINVAL;
1314         }
1315
1316         if (hw->rss_size_max == 0) {
1317                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1318                 return -EINVAL;
1319         }
1320
1321         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1322
1323         return 0;
1324 }
1325
1326 static int
1327 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1328 {
1329         uint8_t resp_msg;
1330         int ret;
1331
1332         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1333                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1334                                 true, &resp_msg, sizeof(resp_msg));
1335         if (ret) {
1336                 if (ret == -ETIME) {
1337                         /*
1338                          * Getting current port based VLAN state from PF driver
1339                          * will not affect VF driver's basic function. Because
1340                          * the VF driver relies on hns3 PF kernel ether driver,
1341                          * to avoid introducing compatibility issues with older
1342                          * version of PF driver, no failure will be returned
1343                          * when the return value is ETIME. This return value has
1344                          * the following scenarios:
1345                          * 1) Firmware didn't return the results in time
1346                          * 2) the result return by firmware is timeout
1347                          * 3) the older version of kernel side PF driver does
1348                          *    not support this mailbox message.
1349                          * For scenarios 1 and 2, it is most likely that a
1350                          * hardware error has occurred, or a hardware reset has
1351                          * occurred. In this case, these errors will be caught
1352                          * by other functions.
1353                          */
1354                         PMD_INIT_LOG(WARNING,
1355                                 "failed to get PVID state for timeout, maybe "
1356                                 "kernel side PF driver doesn't support this "
1357                                 "mailbox message, or firmware didn't respond.");
1358                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1359                 } else {
1360                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1361                                 " ret = %d", ret);
1362                         return ret;
1363                 }
1364         }
1365         hw->port_base_vlan_cfg.state = resp_msg ?
1366                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1367         return 0;
1368 }
1369
1370 static int
1371 hns3vf_get_queue_info(struct hns3_hw *hw)
1372 {
1373 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1374         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1375         int ret;
1376
1377         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1378                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1379         if (ret) {
1380                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1381                 return ret;
1382         }
1383
1384         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1385         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1386
1387         return hns3vf_check_tqp_info(hw);
1388 }
1389
1390 static int
1391 hns3vf_get_queue_depth(struct hns3_hw *hw)
1392 {
1393 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1394         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1395         int ret;
1396
1397         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1398                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1399         if (ret) {
1400                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1401                              ret);
1402                 return ret;
1403         }
1404
1405         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1406         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1407
1408         return 0;
1409 }
1410
1411 static int
1412 hns3vf_get_tc_info(struct hns3_hw *hw)
1413 {
1414         uint8_t resp_msg;
1415         int ret;
1416         uint32_t i;
1417
1418         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1419                                 true, &resp_msg, sizeof(resp_msg));
1420         if (ret) {
1421                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1422                          ret);
1423                 return ret;
1424         }
1425
1426         hw->hw_tc_map = resp_msg;
1427
1428         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1429                 if (hw->hw_tc_map & BIT(i))
1430                         hw->num_tc++;
1431         }
1432
1433         return 0;
1434 }
1435
1436 static int
1437 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1438 {
1439         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1440         int ret;
1441
1442         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1443                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1444         if (ret) {
1445                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1446                 return ret;
1447         }
1448
1449         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1450
1451         return 0;
1452 }
1453
1454 static int
1455 hns3vf_get_configuration(struct hns3_hw *hw)
1456 {
1457         int ret;
1458
1459         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1460         hw->rss_dis_flag = false;
1461
1462         /* Get device capability */
1463         ret = hns3vf_get_capability(hw);
1464         if (ret) {
1465                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1466                 return ret;
1467         }
1468
1469         hns3vf_get_push_lsc_cap(hw);
1470
1471         /* Get queue configuration from PF */
1472         ret = hns3vf_get_queue_info(hw);
1473         if (ret)
1474                 return ret;
1475
1476         /* Get queue depth info from PF */
1477         ret = hns3vf_get_queue_depth(hw);
1478         if (ret)
1479                 return ret;
1480
1481         /* Get user defined VF MAC addr from PF */
1482         ret = hns3vf_get_host_mac_addr(hw);
1483         if (ret)
1484                 return ret;
1485
1486         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1487         if (ret)
1488                 return ret;
1489
1490         /* Get tc configuration from PF */
1491         return hns3vf_get_tc_info(hw);
1492 }
1493
1494 static int
1495 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1496                             uint16_t nb_tx_q)
1497 {
1498         struct hns3_hw *hw = &hns->hw;
1499
1500         if (nb_rx_q < hw->num_tc) {
1501                 hns3_err(hw, "number of Rx queues(%u) is less than tcs(%u).",
1502                          nb_rx_q, hw->num_tc);
1503                 return -EINVAL;
1504         }
1505
1506         if (nb_tx_q < hw->num_tc) {
1507                 hns3_err(hw, "number of Tx queues(%u) is less than tcs(%u).",
1508                          nb_tx_q, hw->num_tc);
1509                 return -EINVAL;
1510         }
1511
1512         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1513 }
1514
1515 static void
1516 hns3vf_request_link_info(struct hns3_hw *hw)
1517 {
1518         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1519         uint8_t resp_msg;
1520         bool send_req;
1521         int ret;
1522
1523         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1524                 return;
1525
1526         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1527                    vf->req_link_info_cnt > 0;
1528         if (!send_req)
1529                 return;
1530
1531         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1532                                 &resp_msg, sizeof(resp_msg));
1533         if (ret) {
1534                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1535                 return;
1536         }
1537
1538         if (vf->req_link_info_cnt > 0)
1539                 vf->req_link_info_cnt--;
1540 }
1541
1542 void
1543 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1544                           uint32_t link_speed, uint8_t link_duplex)
1545 {
1546         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1547         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1548         struct hns3_mac *mac = &hw->mac;
1549         int ret;
1550
1551         /*
1552          * PF kernel driver may push link status when VF driver is in resetting,
1553          * driver will stop polling job in this case, after resetting done
1554          * driver will start polling job again.
1555          * When polling job started, driver will get initial link status by
1556          * sending request to PF kernel driver, then could update link status by
1557          * process PF kernel driver's link status mailbox message.
1558          */
1559         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1560                 return;
1561
1562         if (hw->adapter_state != HNS3_NIC_STARTED)
1563                 return;
1564
1565         mac->link_status = link_status;
1566         mac->link_speed = link_speed;
1567         mac->link_duplex = link_duplex;
1568         ret = hns3vf_dev_link_update(dev, 0);
1569         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1570                 hns3_start_report_lse(dev);
1571 }
1572
1573 static int
1574 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1575 {
1576 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1577         struct hns3_hw *hw = &hns->hw;
1578         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1579         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1580         uint8_t is_kill = on ? 0 : 1;
1581
1582         msg_data[0] = is_kill;
1583         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1584         memcpy(&msg_data[3], &proto, sizeof(proto));
1585
1586         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1587                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1588                                  0);
1589 }
1590
1591 static int
1592 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1593 {
1594         struct hns3_adapter *hns = dev->data->dev_private;
1595         struct hns3_hw *hw = &hns->hw;
1596         int ret;
1597
1598         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1599                 hns3_err(hw,
1600                          "vf set vlan id failed during resetting, vlan_id =%u",
1601                          vlan_id);
1602                 return -EIO;
1603         }
1604         rte_spinlock_lock(&hw->lock);
1605         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1606         rte_spinlock_unlock(&hw->lock);
1607         if (ret)
1608                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1609                          vlan_id, ret);
1610
1611         return ret;
1612 }
1613
1614 static int
1615 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1616 {
1617         uint8_t msg_data;
1618         int ret;
1619
1620         msg_data = enable ? 1 : 0;
1621         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1622                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1623         if (ret)
1624                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1625
1626         return ret;
1627 }
1628
1629 static int
1630 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1631 {
1632         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1634         unsigned int tmp_mask;
1635         int ret = 0;
1636
1637         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1638                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1639                              "mask = 0x%x", mask);
1640                 return -EIO;
1641         }
1642
1643         tmp_mask = (unsigned int)mask;
1644         /* Vlan stripping setting */
1645         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1646                 rte_spinlock_lock(&hw->lock);
1647                 /* Enable or disable VLAN stripping */
1648                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1649                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1650                 else
1651                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1652                 rte_spinlock_unlock(&hw->lock);
1653         }
1654
1655         return ret;
1656 }
1657
1658 static int
1659 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1660 {
1661         struct rte_vlan_filter_conf *vfc;
1662         struct hns3_hw *hw = &hns->hw;
1663         uint16_t vlan_id;
1664         uint64_t vbit;
1665         uint64_t ids;
1666         int ret = 0;
1667         uint32_t i;
1668
1669         vfc = &hw->data->vlan_filter_conf;
1670         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1671                 if (vfc->ids[i] == 0)
1672                         continue;
1673                 ids = vfc->ids[i];
1674                 while (ids) {
1675                         /*
1676                          * 64 means the num bits of ids, one bit corresponds to
1677                          * one vlan id
1678                          */
1679                         vlan_id = 64 * i;
1680                         /* count trailing zeroes */
1681                         vbit = ~ids & (ids - 1);
1682                         /* clear least significant bit set */
1683                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1684                         for (; vbit;) {
1685                                 vbit >>= 1;
1686                                 vlan_id++;
1687                         }
1688                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1689                         if (ret) {
1690                                 hns3_err(hw,
1691                                          "VF handle vlan table failed, ret =%d, on = %d",
1692                                          ret, on);
1693                                 return ret;
1694                         }
1695                 }
1696         }
1697
1698         return ret;
1699 }
1700
1701 static int
1702 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1703 {
1704         return hns3vf_handle_all_vlan_table(hns, 0);
1705 }
1706
1707 static int
1708 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1709 {
1710         struct hns3_hw *hw = &hns->hw;
1711         struct rte_eth_conf *dev_conf;
1712         bool en;
1713         int ret;
1714
1715         dev_conf = &hw->data->dev_conf;
1716         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1717                                                                    : false;
1718         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1719         if (ret)
1720                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1721                          ret);
1722         return ret;
1723 }
1724
1725 static int
1726 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1727 {
1728         struct hns3_adapter *hns = dev->data->dev_private;
1729         struct rte_eth_dev_data *data = dev->data;
1730         struct hns3_hw *hw = &hns->hw;
1731         int ret;
1732
1733         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1734             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1735             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1736                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1737                               "or hw_vlan_insert_pvid is not support!");
1738         }
1739
1740         /* Apply vlan offload setting */
1741         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1742         if (ret)
1743                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1744
1745         return ret;
1746 }
1747
1748 static int
1749 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1750 {
1751         uint8_t msg_data;
1752
1753         msg_data = alive ? 1 : 0;
1754         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1755                                  sizeof(msg_data), false, NULL, 0);
1756 }
1757
1758 static void
1759 hns3vf_keep_alive_handler(void *param)
1760 {
1761         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1762         struct hns3_adapter *hns = eth_dev->data->dev_private;
1763         struct hns3_hw *hw = &hns->hw;
1764         uint8_t respmsg;
1765         int ret;
1766
1767         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1768                                 false, &respmsg, sizeof(uint8_t));
1769         if (ret)
1770                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1771                          ret);
1772
1773         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1774                           eth_dev);
1775 }
1776
1777 static void
1778 hns3vf_service_handler(void *param)
1779 {
1780         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1781         struct hns3_adapter *hns = eth_dev->data->dev_private;
1782         struct hns3_hw *hw = &hns->hw;
1783
1784         /*
1785          * The query link status and reset processing are executed in the
1786          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1787          * and the query operation will timeout after 30ms. In the case of
1788          * multiple PF/VFs, each query failure timeout causes the IMP reset
1789          * interrupt to fail to respond within 100ms.
1790          * Before querying the link status, check whether there is a reset
1791          * pending, and if so, abandon the query.
1792          */
1793         if (!hns3vf_is_reset_pending(hns))
1794                 hns3vf_request_link_info(hw);
1795         else
1796                 hns3_warn(hw, "Cancel the query when reset is pending");
1797
1798         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1799                           eth_dev);
1800 }
1801
1802 static void
1803 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1804 {
1805 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1806
1807         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1808
1809         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1810                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1811
1812         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1813
1814         hns3vf_service_handler(dev);
1815 }
1816
1817 static void
1818 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1819 {
1820         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1821
1822         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1823
1824         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1825 }
1826
1827 static int
1828 hns3_query_vf_resource(struct hns3_hw *hw)
1829 {
1830         struct hns3_vf_res_cmd *req;
1831         struct hns3_cmd_desc desc;
1832         uint16_t num_msi;
1833         int ret;
1834
1835         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1836         ret = hns3_cmd_send(hw, &desc, 1);
1837         if (ret) {
1838                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1839                 return ret;
1840         }
1841
1842         req = (struct hns3_vf_res_cmd *)desc.data;
1843         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1844                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1845         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1846                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1847                          num_msi, HNS3_MIN_VECTOR_NUM);
1848                 return -EINVAL;
1849         }
1850
1851         hw->num_msi = num_msi;
1852
1853         return 0;
1854 }
1855
1856 static int
1857 hns3vf_init_hardware(struct hns3_adapter *hns)
1858 {
1859         struct hns3_hw *hw = &hns->hw;
1860         uint16_t mtu = hw->data->mtu;
1861         int ret;
1862
1863         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1864         if (ret)
1865                 return ret;
1866
1867         ret = hns3vf_config_mtu(hw, mtu);
1868         if (ret)
1869                 goto err_init_hardware;
1870
1871         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1872         if (ret) {
1873                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1874                 goto err_init_hardware;
1875         }
1876
1877         ret = hns3_config_gro(hw, false);
1878         if (ret) {
1879                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1880                 goto err_init_hardware;
1881         }
1882
1883         /*
1884          * In the initialization clearing the all hardware mapping relationship
1885          * configurations between queues and interrupt vectors is needed, so
1886          * some error caused by the residual configurations, such as the
1887          * unexpected interrupt, can be avoid.
1888          */
1889         ret = hns3vf_init_ring_with_vector(hw);
1890         if (ret) {
1891                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1892                 goto err_init_hardware;
1893         }
1894
1895         ret = hns3vf_set_alive(hw, true);
1896         if (ret) {
1897                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1898                 goto err_init_hardware;
1899         }
1900
1901         return 0;
1902
1903 err_init_hardware:
1904         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1905         return ret;
1906 }
1907
1908 static int
1909 hns3vf_clear_vport_list(struct hns3_hw *hw)
1910 {
1911         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1912                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1913                                  NULL, 0);
1914 }
1915
1916 static int
1917 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1918 {
1919         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1920         struct hns3_adapter *hns = eth_dev->data->dev_private;
1921         struct hns3_hw *hw = &hns->hw;
1922         int ret;
1923
1924         PMD_INIT_FUNC_TRACE();
1925
1926         /* Get hardware io base address from pcie BAR2 IO space */
1927         hw->io_base = pci_dev->mem_resource[2].addr;
1928
1929         /* Firmware command queue initialize */
1930         ret = hns3_cmd_init_queue(hw);
1931         if (ret) {
1932                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1933                 goto err_cmd_init_queue;
1934         }
1935
1936         /* Firmware command initialize */
1937         ret = hns3_cmd_init(hw);
1938         if (ret) {
1939                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1940                 goto err_cmd_init;
1941         }
1942
1943         /* Get VF resource */
1944         ret = hns3_query_vf_resource(hw);
1945         if (ret)
1946                 goto err_cmd_init;
1947
1948         rte_spinlock_init(&hw->mbx_resp.lock);
1949
1950         hns3vf_clear_event_cause(hw, 0);
1951
1952         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1953                                          hns3vf_interrupt_handler, eth_dev);
1954         if (ret) {
1955                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1956                 goto err_intr_callback_register;
1957         }
1958
1959         /* Enable interrupt */
1960         rte_intr_enable(&pci_dev->intr_handle);
1961         hns3vf_enable_irq0(hw);
1962
1963         /* Get configuration from PF */
1964         ret = hns3vf_get_configuration(hw);
1965         if (ret) {
1966                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1967                 goto err_get_config;
1968         }
1969
1970         ret = hns3_tqp_stats_init(hw);
1971         if (ret)
1972                 goto err_get_config;
1973
1974         /* Hardware statistics of imissed registers cleared. */
1975         ret = hns3_update_imissed_stats(hw, true);
1976         if (ret) {
1977                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1978                 goto err_set_tc_queue;
1979         }
1980
1981         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1982         if (ret) {
1983                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1984                 goto err_set_tc_queue;
1985         }
1986
1987         ret = hns3vf_clear_vport_list(hw);
1988         if (ret) {
1989                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1990                 goto err_set_tc_queue;
1991         }
1992
1993         ret = hns3vf_init_hardware(hns);
1994         if (ret)
1995                 goto err_set_tc_queue;
1996
1997         hns3_rss_set_default_args(hw);
1998
1999         return 0;
2000
2001 err_set_tc_queue:
2002         hns3_tqp_stats_uninit(hw);
2003
2004 err_get_config:
2005         hns3vf_disable_irq0(hw);
2006         rte_intr_disable(&pci_dev->intr_handle);
2007         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2008                              eth_dev);
2009 err_intr_callback_register:
2010 err_cmd_init:
2011         hns3_cmd_uninit(hw);
2012         hns3_cmd_destroy_queue(hw);
2013 err_cmd_init_queue:
2014         hw->io_base = NULL;
2015
2016         return ret;
2017 }
2018
2019 static void
2020 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2021 {
2022         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2023         struct hns3_adapter *hns = eth_dev->data->dev_private;
2024         struct hns3_hw *hw = &hns->hw;
2025
2026         PMD_INIT_FUNC_TRACE();
2027
2028         hns3_rss_uninit(hns);
2029         (void)hns3_config_gro(hw, false);
2030         (void)hns3vf_set_alive(hw, false);
2031         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2032         hns3_tqp_stats_uninit(hw);
2033         hns3vf_disable_irq0(hw);
2034         rte_intr_disable(&pci_dev->intr_handle);
2035         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2036                              eth_dev);
2037         hns3_cmd_uninit(hw);
2038         hns3_cmd_destroy_queue(hw);
2039         hw->io_base = NULL;
2040 }
2041
2042 static int
2043 hns3vf_do_stop(struct hns3_adapter *hns)
2044 {
2045         struct hns3_hw *hw = &hns->hw;
2046         int ret;
2047
2048         hw->mac.link_status = ETH_LINK_DOWN;
2049
2050         /*
2051          * The "hns3vf_do_stop" function will also be called by .stop_service to
2052          * prepare reset. At the time of global or IMP reset, the command cannot
2053          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2054          * accessed during the reset process. So the mbuf can not be released
2055          * during reset and is required to be released after the reset is
2056          * completed.
2057          */
2058         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2059                 hns3_dev_release_mbufs(hns);
2060
2061         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2062                 hns3vf_configure_mac_addr(hns, true);
2063                 ret = hns3_reset_all_tqps(hns);
2064                 if (ret) {
2065                         hns3_err(hw, "failed to reset all queues ret = %d",
2066                                  ret);
2067                         return ret;
2068                 }
2069         }
2070         return 0;
2071 }
2072
2073 static void
2074 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2075 {
2076         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2078         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2079         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2080         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2081         uint16_t q_id;
2082
2083         if (dev->data->dev_conf.intr_conf.rxq == 0)
2084                 return;
2085
2086         /* unmap the ring with vector */
2087         if (rte_intr_allow_others(intr_handle)) {
2088                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2089                 base = RTE_INTR_VEC_RXTX_OFFSET;
2090         }
2091         if (rte_intr_dp_is_en(intr_handle)) {
2092                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2093                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2094                                                            HNS3_RING_TYPE_RX,
2095                                                            q_id);
2096                         if (vec < base + intr_handle->nb_efd - 1)
2097                                 vec++;
2098                 }
2099         }
2100         /* Clean datapath event and queue/vec mapping */
2101         rte_intr_efd_disable(intr_handle);
2102         if (intr_handle->intr_vec) {
2103                 rte_free(intr_handle->intr_vec);
2104                 intr_handle->intr_vec = NULL;
2105         }
2106 }
2107
2108 static int
2109 hns3vf_dev_stop(struct rte_eth_dev *dev)
2110 {
2111         struct hns3_adapter *hns = dev->data->dev_private;
2112         struct hns3_hw *hw = &hns->hw;
2113
2114         PMD_INIT_FUNC_TRACE();
2115         dev->data->dev_started = 0;
2116
2117         hw->adapter_state = HNS3_NIC_STOPPING;
2118         hns3_set_rxtx_function(dev);
2119         rte_wmb();
2120         /* Disable datapath on secondary process. */
2121         hns3_mp_req_stop_rxtx(dev);
2122         /* Prevent crashes when queues are still in use. */
2123         rte_delay_ms(hw->tqps_num);
2124
2125         rte_spinlock_lock(&hw->lock);
2126         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2127                 hns3_stop_tqps(hw);
2128                 hns3vf_do_stop(hns);
2129                 hns3vf_unmap_rx_interrupt(dev);
2130                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2131         }
2132         hns3_rx_scattered_reset(dev);
2133         hns3vf_stop_poll_job(dev);
2134         hns3_stop_report_lse(dev);
2135         rte_spinlock_unlock(&hw->lock);
2136
2137         return 0;
2138 }
2139
2140 static int
2141 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2142 {
2143         struct hns3_adapter *hns = eth_dev->data->dev_private;
2144         struct hns3_hw *hw = &hns->hw;
2145         int ret = 0;
2146
2147         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2148                 rte_free(eth_dev->process_private);
2149                 eth_dev->process_private = NULL;
2150                 return 0;
2151         }
2152
2153         if (hw->adapter_state == HNS3_NIC_STARTED)
2154                 ret = hns3vf_dev_stop(eth_dev);
2155
2156         hw->adapter_state = HNS3_NIC_CLOSING;
2157         hns3_reset_abort(hns);
2158         hw->adapter_state = HNS3_NIC_CLOSED;
2159         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2160         hns3vf_configure_all_mc_mac_addr(hns, true);
2161         hns3vf_remove_all_vlan_table(hns);
2162         hns3vf_uninit_vf(eth_dev);
2163         hns3_free_all_queues(eth_dev);
2164         rte_free(hw->reset.wait_data);
2165         rte_free(eth_dev->process_private);
2166         eth_dev->process_private = NULL;
2167         hns3_mp_uninit_primary();
2168         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2169
2170         return ret;
2171 }
2172
2173 static int
2174 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2175                       size_t fw_size)
2176 {
2177         struct hns3_adapter *hns = eth_dev->data->dev_private;
2178         struct hns3_hw *hw = &hns->hw;
2179         uint32_t version = hw->fw_version;
2180         int ret;
2181
2182         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2183                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2184                                       HNS3_FW_VERSION_BYTE3_S),
2185                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2186                                       HNS3_FW_VERSION_BYTE2_S),
2187                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2188                                       HNS3_FW_VERSION_BYTE1_S),
2189                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2190                                       HNS3_FW_VERSION_BYTE0_S));
2191         ret += 1; /* add the size of '\0' */
2192         if (fw_size < (uint32_t)ret)
2193                 return ret;
2194         else
2195                 return 0;
2196 }
2197
2198 static int
2199 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2200                        __rte_unused int wait_to_complete)
2201 {
2202         struct hns3_adapter *hns = eth_dev->data->dev_private;
2203         struct hns3_hw *hw = &hns->hw;
2204         struct hns3_mac *mac = &hw->mac;
2205         struct rte_eth_link new_link;
2206
2207         memset(&new_link, 0, sizeof(new_link));
2208         switch (mac->link_speed) {
2209         case ETH_SPEED_NUM_10M:
2210         case ETH_SPEED_NUM_100M:
2211         case ETH_SPEED_NUM_1G:
2212         case ETH_SPEED_NUM_10G:
2213         case ETH_SPEED_NUM_25G:
2214         case ETH_SPEED_NUM_40G:
2215         case ETH_SPEED_NUM_50G:
2216         case ETH_SPEED_NUM_100G:
2217         case ETH_SPEED_NUM_200G:
2218                 new_link.link_speed = mac->link_speed;
2219                 break;
2220         default:
2221                 if (mac->link_status)
2222                         new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2223                 else
2224                         new_link.link_speed = ETH_SPEED_NUM_NONE;
2225                 break;
2226         }
2227
2228         new_link.link_duplex = mac->link_duplex;
2229         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2230         new_link.link_autoneg =
2231             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2232
2233         return rte_eth_linkstatus_set(eth_dev, &new_link);
2234 }
2235
2236 static int
2237 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2238 {
2239         struct hns3_hw *hw = &hns->hw;
2240         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2241         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2242         int ret;
2243
2244         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2245         if (ret)
2246                 return ret;
2247
2248         hns3_enable_rxd_adv_layout(hw);
2249
2250         ret = hns3_init_queues(hns, reset_queue);
2251         if (ret)
2252                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2253
2254         return ret;
2255 }
2256
2257 static int
2258 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2259 {
2260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2262         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2264         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2265         uint32_t intr_vector;
2266         uint16_t q_id;
2267         int ret;
2268
2269         /*
2270          * hns3 needs a separate interrupt to be used as event interrupt which
2271          * could not be shared with task queue pair, so KERNEL drivers need
2272          * support multiple interrupt vectors.
2273          */
2274         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2275             !rte_intr_cap_multiple(intr_handle))
2276                 return 0;
2277
2278         rte_intr_disable(intr_handle);
2279         intr_vector = hw->used_rx_queues;
2280         /* It creates event fd for each intr vector when MSIX is used */
2281         if (rte_intr_efd_enable(intr_handle, intr_vector))
2282                 return -EINVAL;
2283
2284         if (intr_handle->intr_vec == NULL) {
2285                 intr_handle->intr_vec =
2286                         rte_zmalloc("intr_vec",
2287                                     hw->used_rx_queues * sizeof(int), 0);
2288                 if (intr_handle->intr_vec == NULL) {
2289                         hns3_err(hw, "Failed to allocate %u rx_queues"
2290                                      " intr_vec", hw->used_rx_queues);
2291                         ret = -ENOMEM;
2292                         goto vf_alloc_intr_vec_error;
2293                 }
2294         }
2295
2296         if (rte_intr_allow_others(intr_handle)) {
2297                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2298                 base = RTE_INTR_VEC_RXTX_OFFSET;
2299         }
2300
2301         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2302                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2303                                                    HNS3_RING_TYPE_RX, q_id);
2304                 if (ret)
2305                         goto vf_bind_vector_error;
2306                 intr_handle->intr_vec[q_id] = vec;
2307                 /*
2308                  * If there are not enough efds (e.g. not enough interrupt),
2309                  * remaining queues will be bond to the last interrupt.
2310                  */
2311                 if (vec < base + intr_handle->nb_efd - 1)
2312                         vec++;
2313         }
2314         rte_intr_enable(intr_handle);
2315         return 0;
2316
2317 vf_bind_vector_error:
2318         free(intr_handle->intr_vec);
2319         intr_handle->intr_vec = NULL;
2320 vf_alloc_intr_vec_error:
2321         rte_intr_efd_disable(intr_handle);
2322         return ret;
2323 }
2324
2325 static int
2326 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2327 {
2328         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2330         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2331         uint16_t q_id;
2332         int ret;
2333
2334         if (dev->data->dev_conf.intr_conf.rxq == 0)
2335                 return 0;
2336
2337         if (rte_intr_dp_is_en(intr_handle)) {
2338                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2339                         ret = hns3vf_bind_ring_with_vector(hw,
2340                                         intr_handle->intr_vec[q_id], true,
2341                                         HNS3_RING_TYPE_RX, q_id);
2342                         if (ret)
2343                                 return ret;
2344                 }
2345         }
2346
2347         return 0;
2348 }
2349
2350 static void
2351 hns3vf_restore_filter(struct rte_eth_dev *dev)
2352 {
2353         hns3_restore_rss_filter(dev);
2354 }
2355
2356 static int
2357 hns3vf_dev_start(struct rte_eth_dev *dev)
2358 {
2359         struct hns3_adapter *hns = dev->data->dev_private;
2360         struct hns3_hw *hw = &hns->hw;
2361         int ret;
2362
2363         PMD_INIT_FUNC_TRACE();
2364         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2365                 return -EBUSY;
2366
2367         rte_spinlock_lock(&hw->lock);
2368         hw->adapter_state = HNS3_NIC_STARTING;
2369         ret = hns3vf_do_start(hns, true);
2370         if (ret) {
2371                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2372                 rte_spinlock_unlock(&hw->lock);
2373                 return ret;
2374         }
2375         ret = hns3vf_map_rx_interrupt(dev);
2376         if (ret)
2377                 goto map_rx_inter_err;
2378
2379         /*
2380          * There are three register used to control the status of a TQP
2381          * (contains a pair of Tx queue and Rx queue) in the new version network
2382          * engine. One is used to control the enabling of Tx queue, the other is
2383          * used to control the enabling of Rx queue, and the last is the master
2384          * switch used to control the enabling of the tqp. The Tx register and
2385          * TQP register must be enabled at the same time to enable a Tx queue.
2386          * The same applies to the Rx queue. For the older network enginem, this
2387          * function only refresh the enabled flag, and it is used to update the
2388          * status of queue in the dpdk framework.
2389          */
2390         ret = hns3_start_all_txqs(dev);
2391         if (ret)
2392                 goto map_rx_inter_err;
2393
2394         ret = hns3_start_all_rxqs(dev);
2395         if (ret)
2396                 goto start_all_rxqs_fail;
2397
2398         hw->adapter_state = HNS3_NIC_STARTED;
2399         rte_spinlock_unlock(&hw->lock);
2400
2401         hns3_rx_scattered_calc(dev);
2402         hns3_set_rxtx_function(dev);
2403         hns3_mp_req_start_rxtx(dev);
2404
2405         hns3vf_restore_filter(dev);
2406
2407         /* Enable interrupt of all rx queues before enabling queues */
2408         hns3_dev_all_rx_queue_intr_enable(hw, true);
2409         hns3_start_tqps(hw);
2410
2411         if (dev->data->dev_conf.intr_conf.lsc != 0)
2412                 hns3vf_dev_link_update(dev, 0);
2413         hns3vf_start_poll_job(dev);
2414
2415         return ret;
2416
2417 start_all_rxqs_fail:
2418         hns3_stop_all_txqs(dev);
2419 map_rx_inter_err:
2420         (void)hns3vf_do_stop(hns);
2421         hw->adapter_state = HNS3_NIC_CONFIGURED;
2422         rte_spinlock_unlock(&hw->lock);
2423
2424         return ret;
2425 }
2426
2427 static bool
2428 is_vf_reset_done(struct hns3_hw *hw)
2429 {
2430 #define HNS3_FUN_RST_ING_BITS \
2431         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2432          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2433          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2434          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2435
2436         uint32_t val;
2437
2438         if (hw->reset.level == HNS3_VF_RESET) {
2439                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2440                 if (val & HNS3_VF_RST_ING_BIT)
2441                         return false;
2442         } else {
2443                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2444                 if (val & HNS3_FUN_RST_ING_BITS)
2445                         return false;
2446         }
2447         return true;
2448 }
2449
2450 bool
2451 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2452 {
2453         struct hns3_hw *hw = &hns->hw;
2454         enum hns3_reset_level reset;
2455
2456         /*
2457          * According to the protocol of PCIe, FLR to a PF device resets the PF
2458          * state as well as the SR-IOV extended capability including VF Enable
2459          * which means that VFs no longer exist.
2460          *
2461          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2462          * is in FLR stage, the register state of VF device is not reliable,
2463          * so register states detection can not be carried out. In this case,
2464          * we just ignore the register states and return false to indicate that
2465          * there are no other reset states that need to be processed by driver.
2466          */
2467         if (hw->reset.level == HNS3_VF_FULL_RESET)
2468                 return false;
2469
2470         /* Check the registers to confirm whether there is reset pending */
2471         hns3vf_check_event_cause(hns, NULL);
2472         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2473         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2474                 hns3_warn(hw, "High level reset %d is pending", reset);
2475                 return true;
2476         }
2477         return false;
2478 }
2479
2480 static int
2481 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2482 {
2483         struct hns3_hw *hw = &hns->hw;
2484         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2485         struct timeval tv;
2486
2487         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2488                 /*
2489                  * After vf reset is ready, the PF may not have completed
2490                  * the reset processing. The vf sending mbox to PF may fail
2491                  * during the pf reset, so it is better to add extra delay.
2492                  */
2493                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2494                     hw->reset.level == HNS3_FLR_RESET)
2495                         return 0;
2496                 /* Reset retry process, no need to add extra delay. */
2497                 if (hw->reset.attempts)
2498                         return 0;
2499                 if (wait_data->check_completion == NULL)
2500                         return 0;
2501
2502                 wait_data->check_completion = NULL;
2503                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2504                 wait_data->count = 1;
2505                 wait_data->result = HNS3_WAIT_REQUEST;
2506                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2507                                   wait_data);
2508                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2509                 return -EAGAIN;
2510         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2511                 gettimeofday(&tv, NULL);
2512                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2513                           tv.tv_sec, tv.tv_usec);
2514                 return -ETIME;
2515         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2516                 return -EAGAIN;
2517
2518         wait_data->hns = hns;
2519         wait_data->check_completion = is_vf_reset_done;
2520         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2521                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2522         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2523         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2524         wait_data->result = HNS3_WAIT_REQUEST;
2525         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2526         return -EAGAIN;
2527 }
2528
2529 static int
2530 hns3vf_prepare_reset(struct hns3_adapter *hns)
2531 {
2532         struct hns3_hw *hw = &hns->hw;
2533         int ret;
2534
2535         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2536                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2537                                         0, true, NULL, 0);
2538                 if (ret)
2539                         return ret;
2540         }
2541         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2542
2543         return 0;
2544 }
2545
2546 static int
2547 hns3vf_stop_service(struct hns3_adapter *hns)
2548 {
2549         struct hns3_hw *hw = &hns->hw;
2550         struct rte_eth_dev *eth_dev;
2551
2552         eth_dev = &rte_eth_devices[hw->data->port_id];
2553         if (hw->adapter_state == HNS3_NIC_STARTED) {
2554                 /*
2555                  * Make sure call update link status before hns3vf_stop_poll_job
2556                  * because update link status depend on polling job exist.
2557                  */
2558                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2559                                           hw->mac.link_duplex);
2560                 hns3vf_stop_poll_job(eth_dev);
2561         }
2562         hw->mac.link_status = ETH_LINK_DOWN;
2563
2564         hns3_set_rxtx_function(eth_dev);
2565         rte_wmb();
2566         /* Disable datapath on secondary process. */
2567         hns3_mp_req_stop_rxtx(eth_dev);
2568         rte_delay_ms(hw->tqps_num);
2569
2570         rte_spinlock_lock(&hw->lock);
2571         if (hw->adapter_state == HNS3_NIC_STARTED ||
2572             hw->adapter_state == HNS3_NIC_STOPPING) {
2573                 hns3_enable_all_queues(hw, false);
2574                 hns3vf_do_stop(hns);
2575                 hw->reset.mbuf_deferred_free = true;
2576         } else
2577                 hw->reset.mbuf_deferred_free = false;
2578
2579         /*
2580          * It is cumbersome for hardware to pick-and-choose entries for deletion
2581          * from table space. Hence, for function reset software intervention is
2582          * required to delete the entries.
2583          */
2584         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2585                 hns3vf_configure_all_mc_mac_addr(hns, true);
2586         rte_spinlock_unlock(&hw->lock);
2587
2588         return 0;
2589 }
2590
2591 static int
2592 hns3vf_start_service(struct hns3_adapter *hns)
2593 {
2594         struct hns3_hw *hw = &hns->hw;
2595         struct rte_eth_dev *eth_dev;
2596
2597         eth_dev = &rte_eth_devices[hw->data->port_id];
2598         hns3_set_rxtx_function(eth_dev);
2599         hns3_mp_req_start_rxtx(eth_dev);
2600         if (hw->adapter_state == HNS3_NIC_STARTED) {
2601                 hns3vf_start_poll_job(eth_dev);
2602
2603                 /* Enable interrupt of all rx queues before enabling queues */
2604                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2605                 /*
2606                  * Enable state of each rxq and txq will be recovered after
2607                  * reset, so we need to restore them before enable all tqps;
2608                  */
2609                 hns3_restore_tqp_enable_state(hw);
2610                 /*
2611                  * When finished the initialization, enable queues to receive
2612                  * and transmit packets.
2613                  */
2614                 hns3_enable_all_queues(hw, true);
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int
2621 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2622 {
2623         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2624         struct rte_ether_addr *hw_mac;
2625         int ret;
2626
2627         /*
2628          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2629          * on the host by "ip link set ..." command. If the hns3 PF kernel
2630          * ethdev driver sets the MAC address for VF device after the
2631          * initialization of the related VF device, the PF driver will notify
2632          * VF driver to reset VF device to make the new MAC address effective
2633          * immediately. The hns3 VF PMD driver should check whether the MAC
2634          * address has been changed by the PF kernel ethdev driver, if changed
2635          * VF driver should configure hardware using the new MAC address in the
2636          * recovering hardware configuration stage of the reset process.
2637          */
2638         ret = hns3vf_get_host_mac_addr(hw);
2639         if (ret)
2640                 return ret;
2641
2642         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2643         ret = rte_is_zero_ether_addr(hw_mac);
2644         if (ret) {
2645                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2646         } else {
2647                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2648                 if (!ret) {
2649                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2650                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2651                                               &hw->data->mac_addrs[0]);
2652                         hns3_warn(hw, "Default MAC address has been changed to:"
2653                                   " %s by the host PF kernel ethdev driver",
2654                                   mac_str);
2655                 }
2656         }
2657
2658         return 0;
2659 }
2660
2661 static int
2662 hns3vf_restore_conf(struct hns3_adapter *hns)
2663 {
2664         struct hns3_hw *hw = &hns->hw;
2665         int ret;
2666
2667         ret = hns3vf_check_default_mac_change(hw);
2668         if (ret)
2669                 return ret;
2670
2671         ret = hns3vf_configure_mac_addr(hns, false);
2672         if (ret)
2673                 return ret;
2674
2675         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2676         if (ret)
2677                 goto err_mc_mac;
2678
2679         ret = hns3vf_restore_promisc(hns);
2680         if (ret)
2681                 goto err_vlan_table;
2682
2683         ret = hns3vf_restore_vlan_conf(hns);
2684         if (ret)
2685                 goto err_vlan_table;
2686
2687         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2688         if (ret)
2689                 goto err_vlan_table;
2690
2691         ret = hns3vf_restore_rx_interrupt(hw);
2692         if (ret)
2693                 goto err_vlan_table;
2694
2695         ret = hns3_restore_gro_conf(hw);
2696         if (ret)
2697                 goto err_vlan_table;
2698
2699         if (hw->adapter_state == HNS3_NIC_STARTED) {
2700                 ret = hns3vf_do_start(hns, false);
2701                 if (ret)
2702                         goto err_vlan_table;
2703                 hns3_info(hw, "hns3vf dev restart successful!");
2704         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2705                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2706         return 0;
2707
2708 err_vlan_table:
2709         hns3vf_configure_all_mc_mac_addr(hns, true);
2710 err_mc_mac:
2711         hns3vf_configure_mac_addr(hns, true);
2712         return ret;
2713 }
2714
2715 static enum hns3_reset_level
2716 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2717 {
2718         enum hns3_reset_level reset_level;
2719
2720         /* return the highest priority reset level amongst all */
2721         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2722                 reset_level = HNS3_VF_RESET;
2723         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2724                 reset_level = HNS3_VF_FULL_RESET;
2725         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2726                 reset_level = HNS3_VF_PF_FUNC_RESET;
2727         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2728                 reset_level = HNS3_VF_FUNC_RESET;
2729         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2730                 reset_level = HNS3_FLR_RESET;
2731         else
2732                 reset_level = HNS3_NONE_RESET;
2733
2734         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2735                 return HNS3_NONE_RESET;
2736
2737         return reset_level;
2738 }
2739
2740 static void
2741 hns3vf_reset_service(void *param)
2742 {
2743         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2744         struct hns3_hw *hw = &hns->hw;
2745         enum hns3_reset_level reset_level;
2746         struct timeval tv_delta;
2747         struct timeval tv_start;
2748         struct timeval tv;
2749         uint64_t msec;
2750
2751         /*
2752          * The interrupt is not triggered within the delay time.
2753          * The interrupt may have been lost. It is necessary to handle
2754          * the interrupt to recover from the error.
2755          */
2756         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2757                             SCHEDULE_DEFERRED) {
2758                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2759                                  __ATOMIC_RELAXED);
2760                 hns3_err(hw, "Handling interrupts in delayed tasks");
2761                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2762                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2763                 if (reset_level == HNS3_NONE_RESET) {
2764                         hns3_err(hw, "No reset level is set, try global reset");
2765                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2766                 }
2767         }
2768         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2769
2770         /*
2771          * Hardware reset has been notified, we now have to poll & check if
2772          * hardware has actually completed the reset sequence.
2773          */
2774         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2775         if (reset_level != HNS3_NONE_RESET) {
2776                 gettimeofday(&tv_start, NULL);
2777                 hns3_reset_process(hns, reset_level);
2778                 gettimeofday(&tv, NULL);
2779                 timersub(&tv, &tv_start, &tv_delta);
2780                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2781                        tv_delta.tv_usec / USEC_PER_MSEC;
2782                 if (msec > HNS3_RESET_PROCESS_MS)
2783                         hns3_err(hw, "%d handle long time delta %" PRIx64
2784                                  " ms time=%ld.%.6ld",
2785                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2786         }
2787 }
2788
2789 static int
2790 hns3vf_reinit_dev(struct hns3_adapter *hns)
2791 {
2792         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2793         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2794         struct hns3_hw *hw = &hns->hw;
2795         int ret;
2796
2797         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2798                 rte_intr_disable(&pci_dev->intr_handle);
2799                 ret = hns3vf_set_bus_master(pci_dev, true);
2800                 if (ret < 0) {
2801                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2802                         return ret;
2803                 }
2804         }
2805
2806         /* Firmware command initialize */
2807         ret = hns3_cmd_init(hw);
2808         if (ret) {
2809                 hns3_err(hw, "Failed to init cmd: %d", ret);
2810                 return ret;
2811         }
2812
2813         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2814                 /*
2815                  * UIO enables msix by writing the pcie configuration space
2816                  * vfio_pci enables msix in rte_intr_enable.
2817                  */
2818                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2819                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2820                         if (hns3vf_enable_msix(pci_dev, true))
2821                                 hns3_err(hw, "Failed to enable msix");
2822                 }
2823
2824                 rte_intr_enable(&pci_dev->intr_handle);
2825         }
2826
2827         ret = hns3_reset_all_tqps(hns);
2828         if (ret) {
2829                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2830                 return ret;
2831         }
2832
2833         ret = hns3vf_init_hardware(hns);
2834         if (ret) {
2835                 hns3_err(hw, "Failed to init hardware: %d", ret);
2836                 return ret;
2837         }
2838
2839         return 0;
2840 }
2841
2842 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2843         .dev_configure      = hns3vf_dev_configure,
2844         .dev_start          = hns3vf_dev_start,
2845         .dev_stop           = hns3vf_dev_stop,
2846         .dev_close          = hns3vf_dev_close,
2847         .mtu_set            = hns3vf_dev_mtu_set,
2848         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2849         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2850         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2851         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2852         .stats_get          = hns3_stats_get,
2853         .stats_reset        = hns3_stats_reset,
2854         .xstats_get         = hns3_dev_xstats_get,
2855         .xstats_get_names   = hns3_dev_xstats_get_names,
2856         .xstats_reset       = hns3_dev_xstats_reset,
2857         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2858         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2859         .dev_infos_get      = hns3vf_dev_infos_get,
2860         .fw_version_get     = hns3vf_fw_version_get,
2861         .rx_queue_setup     = hns3_rx_queue_setup,
2862         .tx_queue_setup     = hns3_tx_queue_setup,
2863         .rx_queue_release   = hns3_dev_rx_queue_release,
2864         .tx_queue_release   = hns3_dev_tx_queue_release,
2865         .rx_queue_start     = hns3_dev_rx_queue_start,
2866         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2867         .tx_queue_start     = hns3_dev_tx_queue_start,
2868         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2869         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2870         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2871         .rxq_info_get       = hns3_rxq_info_get,
2872         .txq_info_get       = hns3_txq_info_get,
2873         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2874         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2875         .mac_addr_add       = hns3vf_add_mac_addr,
2876         .mac_addr_remove    = hns3vf_remove_mac_addr,
2877         .mac_addr_set       = hns3vf_set_default_mac_addr,
2878         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2879         .link_update        = hns3vf_dev_link_update,
2880         .rss_hash_update    = hns3_dev_rss_hash_update,
2881         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2882         .reta_update        = hns3_dev_rss_reta_update,
2883         .reta_query         = hns3_dev_rss_reta_query,
2884         .flow_ops_get       = hns3_dev_flow_ops_get,
2885         .vlan_filter_set    = hns3vf_vlan_filter_set,
2886         .vlan_offload_set   = hns3vf_vlan_offload_set,
2887         .get_reg            = hns3_get_regs,
2888         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2889         .tx_done_cleanup    = hns3_tx_done_cleanup,
2890 };
2891
2892 static const struct hns3_reset_ops hns3vf_reset_ops = {
2893         .reset_service       = hns3vf_reset_service,
2894         .stop_service        = hns3vf_stop_service,
2895         .prepare_reset       = hns3vf_prepare_reset,
2896         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2897         .reinit_dev          = hns3vf_reinit_dev,
2898         .restore_conf        = hns3vf_restore_conf,
2899         .start_service       = hns3vf_start_service,
2900 };
2901
2902 static int
2903 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2904 {
2905         struct hns3_adapter *hns = eth_dev->data->dev_private;
2906         struct hns3_hw *hw = &hns->hw;
2907         int ret;
2908
2909         PMD_INIT_FUNC_TRACE();
2910
2911         eth_dev->process_private = (struct hns3_process_private *)
2912             rte_zmalloc_socket("hns3_filter_list",
2913                                sizeof(struct hns3_process_private),
2914                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2915         if (eth_dev->process_private == NULL) {
2916                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2917                 return -ENOMEM;
2918         }
2919
2920         /* initialize flow filter lists */
2921         hns3_filterlist_init(eth_dev);
2922
2923         hns3_set_rxtx_function(eth_dev);
2924         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2925         eth_dev->rx_queue_count = hns3_rx_queue_count;
2926         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2927                 ret = hns3_mp_init_secondary();
2928                 if (ret) {
2929                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2930                                           "process, ret = %d", ret);
2931                         goto err_mp_init_secondary;
2932                 }
2933
2934                 hw->secondary_cnt++;
2935                 return 0;
2936         }
2937
2938         ret = hns3_mp_init_primary();
2939         if (ret) {
2940                 PMD_INIT_LOG(ERR,
2941                              "Failed to init for primary process, ret = %d",
2942                              ret);
2943                 goto err_mp_init_primary;
2944         }
2945
2946         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2947         hns->is_vf = true;
2948         hw->data = eth_dev->data;
2949         hns3_parse_devargs(eth_dev);
2950
2951         ret = hns3_reset_init(hw);
2952         if (ret)
2953                 goto err_init_reset;
2954         hw->reset.ops = &hns3vf_reset_ops;
2955
2956         ret = hns3vf_init_vf(eth_dev);
2957         if (ret) {
2958                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2959                 goto err_init_vf;
2960         }
2961
2962         /* Allocate memory for storing MAC addresses */
2963         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2964                                                sizeof(struct rte_ether_addr) *
2965                                                HNS3_VF_UC_MACADDR_NUM, 0);
2966         if (eth_dev->data->mac_addrs == NULL) {
2967                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2968                              "to store MAC addresses",
2969                              sizeof(struct rte_ether_addr) *
2970                              HNS3_VF_UC_MACADDR_NUM);
2971                 ret = -ENOMEM;
2972                 goto err_rte_zmalloc;
2973         }
2974
2975         /*
2976          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2977          * on the host by "ip link set ..." command. To avoid some incorrect
2978          * scenes, for example, hns3 VF PMD driver fails to receive and send
2979          * packets after user configure the MAC address by using the
2980          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2981          * address strategy as the hns3 kernel ethdev driver in the
2982          * initialization. If user configure a MAC address by the ip command
2983          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2984          * start with a random MAC address in the initialization.
2985          */
2986         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2987                 rte_eth_random_addr(hw->mac.mac_addr);
2988         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2989                             &eth_dev->data->mac_addrs[0]);
2990
2991         hw->adapter_state = HNS3_NIC_INITIALIZED;
2992
2993         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2994                             SCHEDULE_PENDING) {
2995                 hns3_err(hw, "Reschedule reset service after dev_init");
2996                 hns3_schedule_reset(hns);
2997         } else {
2998                 /* IMP will wait ready flag before reset */
2999                 hns3_notify_reset_ready(hw, false);
3000         }
3001         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3002                           eth_dev);
3003         return 0;
3004
3005 err_rte_zmalloc:
3006         hns3vf_uninit_vf(eth_dev);
3007
3008 err_init_vf:
3009         rte_free(hw->reset.wait_data);
3010
3011 err_init_reset:
3012         hns3_mp_uninit_primary();
3013
3014 err_mp_init_primary:
3015 err_mp_init_secondary:
3016         eth_dev->dev_ops = NULL;
3017         eth_dev->rx_pkt_burst = NULL;
3018         eth_dev->rx_descriptor_status = NULL;
3019         eth_dev->tx_pkt_burst = NULL;
3020         eth_dev->tx_pkt_prepare = NULL;
3021         eth_dev->tx_descriptor_status = NULL;
3022         rte_free(eth_dev->process_private);
3023         eth_dev->process_private = NULL;
3024
3025         return ret;
3026 }
3027
3028 static int
3029 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3030 {
3031         struct hns3_adapter *hns = eth_dev->data->dev_private;
3032         struct hns3_hw *hw = &hns->hw;
3033
3034         PMD_INIT_FUNC_TRACE();
3035
3036         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3037                 rte_free(eth_dev->process_private);
3038                 eth_dev->process_private = NULL;
3039                 return 0;
3040         }
3041
3042         if (hw->adapter_state < HNS3_NIC_CLOSING)
3043                 hns3vf_dev_close(eth_dev);
3044
3045         hw->adapter_state = HNS3_NIC_REMOVED;
3046         return 0;
3047 }
3048
3049 static int
3050 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3051                      struct rte_pci_device *pci_dev)
3052 {
3053         return rte_eth_dev_pci_generic_probe(pci_dev,
3054                                              sizeof(struct hns3_adapter),
3055                                              hns3vf_dev_init);
3056 }
3057
3058 static int
3059 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3060 {
3061         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3062 }
3063
3064 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3065         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3066         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3067         { .vendor_id = 0, }, /* sentinel */
3068 };
3069
3070 static struct rte_pci_driver rte_hns3vf_pmd = {
3071         .id_table = pci_id_hns3vf_map,
3072         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3073         .probe = eth_hns3vf_pci_probe,
3074         .remove = eth_hns3vf_pci_remove,
3075 };
3076
3077 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3078 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3079 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3080 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3081                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3082                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");