drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         int ret;
 761
 762         /*
 763          * Hardware does not support individually enable/disable/reset the Tx or
 764          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 765          * and Rx queues at the same time. When the numbers of Tx queues
 766          * allocated by upper applications are not equal to the numbers of Rx
 767          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 768          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 769          * these fake queues are imperceptible, and can not be used by upper
 770          * applications.
 771          */
 772         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 773         if (ret) {
 774                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 775                 return ret;
 776         }
 777
 778         hw->adapter_state = HNS3_NIC_CONFIGURING;
 779         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 780                 hns3_err(hw, "setting link speed/duplex not supported");
 781                 ret = -EINVAL;
 782                 goto cfg_err;
 783         }
 784
 785         /* When RSS is not configured, redirect the packet queue 0 */
 786         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 787                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 788                 rss_conf = conf->rx_adv_conf.rss_conf;
 789                 if (rss_conf.rss_key == NULL) {
 790                         rss_conf.rss_key = rss_cfg->key;
 791                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 792                 }
 793
 794                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 795                 if (ret)
 796                         goto cfg_err;
 797         }
 798
 799         /*
 800          * If jumbo frames are enabled, MTU needs to be refreshed
 801          * according to the maximum RX packet length.
 802          */
 803         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 804                 /*
 805                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 806                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 807                  * can safely assign to "uint16_t" type variable.
 808                  */
 809                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 810                 ret = hns3vf_dev_mtu_set(dev, mtu);
 811                 if (ret)
 812                         goto cfg_err;
 813                 dev->data->mtu = mtu;
 814         }
 815
 816         ret = hns3vf_dev_configure_vlan(dev);
 817         if (ret)
 818                 goto cfg_err;
 819
 820         hw->adapter_state = HNS3_NIC_CONFIGURED;
 821         return 0;
 822
 823 cfg_err:
 824         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 825         hw->adapter_state = HNS3_NIC_INITIALIZED;
 826
 827         return ret;
 828 }
 829
 830 static int
 831 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 832 {
 833         int ret;
 834
 835         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 836                                 sizeof(mtu), true, NULL, 0);
 837         if (ret)
 838                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 839
 840         return ret;
 841 }
 842
 843 static int
 844 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 845 {
 846         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 847         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 848         int ret;
 849
 850         /*
 851          * The hns3 PF/VF devices on the same port share the hardware MTU
 852          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 853          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 854          * driver, there is no need to stop the port for hns3 VF device, and the
 855          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 856          * PF's MTU.
 857          */
 858         if (rte_atomic16_read(&hw->reset.resetting)) {
 859                 hns3_err(hw, "Failed to set mtu during resetting");
 860                 return -EIO;
 861         }
 862
 863         rte_spinlock_lock(&hw->lock);
 864         ret = hns3vf_config_mtu(hw, mtu);
 865         if (ret) {
 866                 rte_spinlock_unlock(&hw->lock);
 867                 return ret;
 868         }
 869         if (frame_size > RTE_ETHER_MAX_LEN)
 870                 dev->data->dev_conf.rxmode.offloads |=
 871                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 872         else
 873                 dev->data->dev_conf.rxmode.offloads &=
 874                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 875         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 876         rte_spinlock_unlock(&hw->lock);
 877
 878         return 0;
 879 }
 880
 881 static int
 882 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 883 {
 884         struct hns3_adapter *hns = eth_dev->data->dev_private;
 885         struct hns3_hw *hw = &hns->hw;
 886         uint16_t q_num = hw->tqps_num;
 887
 888         /*
 889          * In interrupt mode, 'max_rx_queues' is set based on the number of
 890          * MSI-X interrupt resources of the hardware.
 891          */
 892         if (hw->data->dev_conf.intr_conf.rxq == 1)
 893                 q_num = hw->intr_tqps_num;
 894
 895         info->max_rx_queues = q_num;
 896         info->max_tx_queues = hw->tqps_num;
 897         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 898         info->min_rx_bufsize = hw->rx_buf_len;
 899         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 900         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 901
 902         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 903                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 904                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 905                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 906                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 907                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 908                                  DEV_RX_OFFLOAD_KEEP_CRC |
 909                                  DEV_RX_OFFLOAD_SCATTER |
 910                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 911                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 912                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 913                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 914                                  DEV_RX_OFFLOAD_RSS_HASH);
 915         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 916         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 917                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 918                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 919                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 920                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 921                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 922                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 923                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 924                                  DEV_TX_OFFLOAD_TCP_TSO |
 925                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 926                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 927                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 928                                  info->tx_queue_offload_capa);
 929
 930         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 931                 .nb_max = HNS3_MAX_RING_DESC,
 932                 .nb_min = HNS3_MIN_RING_DESC,
 933                 .nb_align = HNS3_ALIGN_RING_DESC,
 934         };
 935
 936         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 937                 .nb_max = HNS3_MAX_RING_DESC,
 938                 .nb_min = HNS3_MIN_RING_DESC,
 939                 .nb_align = HNS3_ALIGN_RING_DESC,
 940         };
 941
 942         info->vmdq_queue_num = 0;
 943
 944         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 945         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 946         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 947         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 948         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 949
 950         return 0;
 951 }
 952
 953 static void
 954 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 955 {
 956         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 957 }
 958
 959 static void
 960 hns3vf_disable_irq0(struct hns3_hw *hw)
 961 {
 962         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 963 }
 964
 965 static void
 966 hns3vf_enable_irq0(struct hns3_hw *hw)
 967 {
 968         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 969 }
 970
 971 static enum hns3vf_evt_cause
 972 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 973 {
 974         struct hns3_hw *hw = &hns->hw;
 975         enum hns3vf_evt_cause ret;
 976         uint32_t cmdq_stat_reg;
 977         uint32_t rst_ing_reg;
 978         uint32_t val;
 979
 980         /* Fetch the events from their corresponding regs */
 981         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 982
 983         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 984                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 985                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 986                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 987                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 988                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 989                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 990                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 991                 if (clearval) {
 992                         hw->reset.stats.global_cnt++;
 993                         hns3_warn(hw, "Global reset detected, clear reset status");
 994                 } else {
 995                         hns3_schedule_delayed_reset(hns);
 996                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 997                 }
 998
 999                 ret = HNS3VF_VECTOR0_EVENT_RST;
1000                 goto out;
1001         }
1002
1003         /* Check for vector0 mailbox(=CMDQ RX) event source */
1004         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1005                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1006                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1007                 goto out;
1008         }
1009
1010         val = 0;
1011         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1012 out:
1013         if (clearval)
1014                 *clearval = val;
1015         return ret;
1016 }
1017
1018 static void
1019 hns3vf_interrupt_handler(void *param)
1020 {
1021         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1022         struct hns3_adapter *hns = dev->data->dev_private;
1023         struct hns3_hw *hw = &hns->hw;
1024         enum hns3vf_evt_cause event_cause;
1025         uint32_t clearval;
1026
1027         if (hw->irq_thread_id == 0)
1028                 hw->irq_thread_id = pthread_self();
1029
1030         /* Disable interrupt */
1031         hns3vf_disable_irq0(hw);
1032
1033         /* Read out interrupt causes */
1034         event_cause = hns3vf_check_event_cause(hns, &clearval);
1035
1036         switch (event_cause) {
1037         case HNS3VF_VECTOR0_EVENT_RST:
1038                 hns3_schedule_reset(hns);
1039                 break;
1040         case HNS3VF_VECTOR0_EVENT_MBX:
1041                 hns3_dev_handle_mbx_msg(hw);
1042                 break;
1043         default:
1044                 break;
1045         }
1046
1047         /* Clear interrupt causes */
1048         hns3vf_clear_event_cause(hw, clearval);
1049
1050         /* Enable interrupt */
1051         hns3vf_enable_irq0(hw);
1052 }
1053
1054 static int
1055 hns3vf_check_tqp_info(struct hns3_hw *hw)
1056 {
1057         uint16_t tqps_num;
1058
1059         tqps_num = hw->tqps_num;
1060         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1061                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1062                                   "range: 1~%d",
1063                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1064                 return -EINVAL;
1065         }
1066
1067         if (hw->rx_buf_len == 0)
1068                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1069         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1070
1071         return 0;
1072 }
1073
1074 static int
1075 hns3vf_get_queue_info(struct hns3_hw *hw)
1076 {
1077 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1078         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1079         int ret;
1080
1081         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1082                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1083         if (ret) {
1084                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1085                 return ret;
1086         }
1087
1088         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1089         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1090         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1091
1092         return hns3vf_check_tqp_info(hw);
1093 }
1094
1095 static int
1096 hns3vf_get_queue_depth(struct hns3_hw *hw)
1097 {
1098 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1099         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1100         int ret;
1101
1102         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1103                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1106                              ret);
1107                 return ret;
1108         }
1109
1110         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1111         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1112
1113         return 0;
1114 }
1115
1116 static int
1117 hns3vf_get_tc_info(struct hns3_hw *hw)
1118 {
1119         uint8_t resp_msg;
1120         int ret;
1121
1122         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1123                                 true, &resp_msg, sizeof(resp_msg));
1124         if (ret) {
1125                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1126                          ret);
1127                 return ret;
1128         }
1129
1130         hw->hw_tc_map = resp_msg;
1131
1132         return 0;
1133 }
1134
1135 static int
1136 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1137 {
1138         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1139         int ret;
1140
1141         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1142                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1143         if (ret) {
1144                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1145                 return ret;
1146         }
1147
1148         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1149
1150         return 0;
1151 }
1152
1153 static int
1154 hns3vf_get_configuration(struct hns3_hw *hw)
1155 {
1156         int ret;
1157
1158         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1159         hw->rss_dis_flag = false;
1160
1161         /* Get queue configuration from PF */
1162         ret = hns3vf_get_queue_info(hw);
1163         if (ret)
1164                 return ret;
1165
1166         /* Get queue depth info from PF */
1167         ret = hns3vf_get_queue_depth(hw);
1168         if (ret)
1169                 return ret;
1170
1171         /* Get user defined VF MAC addr from PF */
1172         ret = hns3vf_get_host_mac_addr(hw);
1173         if (ret)
1174                 return ret;
1175
1176         /* Get tc configuration from PF */
1177         return hns3vf_get_tc_info(hw);
1178 }
1179
1180 static int
1181 hns3vf_set_tc_info(struct hns3_adapter *hns)
1182 {
1183         struct hns3_hw *hw = &hns->hw;
1184         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1185         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1186         uint8_t i;
1187
1188         hw->num_tc = 0;
1189         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1190                 if (hw->hw_tc_map & BIT(i))
1191                         hw->num_tc++;
1192
1193         if (nb_rx_q < hw->num_tc) {
1194                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1195                          nb_rx_q, hw->num_tc);
1196                 return -EINVAL;
1197         }
1198
1199         if (nb_tx_q < hw->num_tc) {
1200                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1201                          nb_tx_q, hw->num_tc);
1202                 return -EINVAL;
1203         }
1204
1205         hns3_set_rss_size(hw, nb_rx_q);
1206         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1207
1208         return 0;
1209 }
1210
1211 static void
1212 hns3vf_request_link_info(struct hns3_hw *hw)
1213 {
1214         uint8_t resp_msg;
1215         int ret;
1216
1217         if (rte_atomic16_read(&hw->reset.resetting))
1218                 return;
1219         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1220                                 &resp_msg, sizeof(resp_msg));
1221         if (ret)
1222                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1223 }
1224
1225 static int
1226 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1227 {
1228 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1229         struct hns3_hw *hw = &hns->hw;
1230         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1231         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1232         uint8_t is_kill = on ? 0 : 1;
1233
1234         msg_data[0] = is_kill;
1235         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1236         memcpy(&msg_data[3], &proto, sizeof(proto));
1237
1238         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1239                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1240                                  0);
1241 }
1242
1243 static int
1244 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1245 {
1246         struct hns3_adapter *hns = dev->data->dev_private;
1247         struct hns3_hw *hw = &hns->hw;
1248         int ret;
1249
1250         if (rte_atomic16_read(&hw->reset.resetting)) {
1251                 hns3_err(hw,
1252                          "vf set vlan id failed during resetting, vlan_id =%u",
1253                          vlan_id);
1254                 return -EIO;
1255         }
1256         rte_spinlock_lock(&hw->lock);
1257         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1258         rte_spinlock_unlock(&hw->lock);
1259         if (ret)
1260                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1261                          vlan_id, ret);
1262
1263         return ret;
1264 }
1265
1266 static int
1267 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1268 {
1269         uint8_t msg_data;
1270         int ret;
1271
1272         msg_data = enable ? 1 : 0;
1273         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1274                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1275         if (ret)
1276                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1277
1278         return ret;
1279 }
1280
1281 static int
1282 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1283 {
1284         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1286         unsigned int tmp_mask;
1287         int ret = 0;
1288
1289         if (rte_atomic16_read(&hw->reset.resetting)) {
1290                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1291                              "mask = 0x%x", mask);
1292                 return -EIO;
1293         }
1294
1295         tmp_mask = (unsigned int)mask;
1296         /* Vlan stripping setting */
1297         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1298                 rte_spinlock_lock(&hw->lock);
1299                 /* Enable or disable VLAN stripping */
1300                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1301                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1302                 else
1303                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1304                 rte_spinlock_unlock(&hw->lock);
1305         }
1306
1307         return ret;
1308 }
1309
1310 static int
1311 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1312 {
1313         struct rte_vlan_filter_conf *vfc;
1314         struct hns3_hw *hw = &hns->hw;
1315         uint16_t vlan_id;
1316         uint64_t vbit;
1317         uint64_t ids;
1318         int ret = 0;
1319         uint32_t i;
1320
1321         vfc = &hw->data->vlan_filter_conf;
1322         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1323                 if (vfc->ids[i] == 0)
1324                         continue;
1325                 ids = vfc->ids[i];
1326                 while (ids) {
1327                         /*
1328                          * 64 means the num bits of ids, one bit corresponds to
1329                          * one vlan id
1330                          */
1331                         vlan_id = 64 * i;
1332                         /* count trailing zeroes */
1333                         vbit = ~ids & (ids - 1);
1334                         /* clear least significant bit set */
1335                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1336                         for (; vbit;) {
1337                                 vbit >>= 1;
1338                                 vlan_id++;
1339                         }
1340                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1341                         if (ret) {
1342                                 hns3_err(hw,
1343                                          "VF handle vlan table failed, ret =%d, on = %d",
1344                                          ret, on);
1345                                 return ret;
1346                         }
1347                 }
1348         }
1349
1350         return ret;
1351 }
1352
1353 static int
1354 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1355 {
1356         return hns3vf_handle_all_vlan_table(hns, 0);
1357 }
1358
1359 static int
1360 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1361 {
1362         struct hns3_hw *hw = &hns->hw;
1363         struct rte_eth_conf *dev_conf;
1364         bool en;
1365         int ret;
1366
1367         dev_conf = &hw->data->dev_conf;
1368         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1369                                                                    : false;
1370         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1371         if (ret)
1372                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1373                          ret);
1374         return ret;
1375 }
1376
1377 static int
1378 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1379 {
1380         struct hns3_adapter *hns = dev->data->dev_private;
1381         struct rte_eth_dev_data *data = dev->data;
1382         struct hns3_hw *hw = &hns->hw;
1383         int ret;
1384
1385         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1386             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1387             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1388                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1389                               "or hw_vlan_insert_pvid is not support!");
1390         }
1391
1392         /* Apply vlan offload setting */
1393         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1394         if (ret)
1395                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1396
1397         return ret;
1398 }
1399
1400 static int
1401 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1402 {
1403         uint8_t msg_data;
1404
1405         msg_data = alive ? 1 : 0;
1406         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1407                                  sizeof(msg_data), false, NULL, 0);
1408 }
1409
1410 static void
1411 hns3vf_keep_alive_handler(void *param)
1412 {
1413         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1414         struct hns3_adapter *hns = eth_dev->data->dev_private;
1415         struct hns3_hw *hw = &hns->hw;
1416         uint8_t respmsg;
1417         int ret;
1418
1419         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1420                                 false, &respmsg, sizeof(uint8_t));
1421         if (ret)
1422                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1423                          ret);
1424
1425         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1426                           eth_dev);
1427 }
1428
1429 static void
1430 hns3vf_service_handler(void *param)
1431 {
1432         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1433         struct hns3_adapter *hns = eth_dev->data->dev_private;
1434         struct hns3_hw *hw = &hns->hw;
1435
1436         /*
1437          * The query link status and reset processing are executed in the
1438          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1439          * and the query operation will time out after 30ms. In the case of
1440          * multiple PF/VFs, each query failure timeout causes the IMP reset
1441          * interrupt to fail to respond within 100ms.
1442          * Before querying the link status, check whether there is a reset
1443          * pending, and if so, abandon the query.
1444          */
1445         if (!hns3vf_is_reset_pending(hns))
1446                 hns3vf_request_link_info(hw);
1447         else
1448                 hns3_warn(hw, "Cancel the query when reset is pending");
1449
1450         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1451                           eth_dev);
1452 }
1453
1454 static int
1455 hns3_query_vf_resource(struct hns3_hw *hw)
1456 {
1457         struct hns3_vf_res_cmd *req;
1458         struct hns3_cmd_desc desc;
1459         uint16_t num_msi;
1460         int ret;
1461
1462         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1463         ret = hns3_cmd_send(hw, &desc, 1);
1464         if (ret) {
1465                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1466                 return ret;
1467         }
1468
1469         req = (struct hns3_vf_res_cmd *)desc.data;
1470         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1471                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1472         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1473                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1474                          num_msi, HNS3_MIN_VECTOR_NUM);
1475                 return -EINVAL;
1476         }
1477
1478         hw->num_msi = num_msi;
1479
1480         return 0;
1481 }
1482
1483 static int
1484 hns3vf_init_hardware(struct hns3_adapter *hns)
1485 {
1486         struct hns3_hw *hw = &hns->hw;
1487         uint16_t mtu = hw->data->mtu;
1488         int ret;
1489
1490         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1491         if (ret)
1492                 return ret;
1493
1494         ret = hns3vf_config_mtu(hw, mtu);
1495         if (ret)
1496                 goto err_init_hardware;
1497
1498         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1499         if (ret) {
1500                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1501                 goto err_init_hardware;
1502         }
1503
1504         ret = hns3_config_gro(hw, false);
1505         if (ret) {
1506                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1507                 goto err_init_hardware;
1508         }
1509
1510         /*
1511          * In the initialization clearing the all hardware mapping relationship
1512          * configurations between queues and interrupt vectors is needed, so
1513          * some error caused by the residual configurations, such as the
1514          * unexpected interrupt, can be avoid.
1515          */
1516         ret = hns3vf_init_ring_with_vector(hw);
1517         if (ret) {
1518                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1519                 goto err_init_hardware;
1520         }
1521
1522         ret = hns3vf_set_alive(hw, true);
1523         if (ret) {
1524                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1525                 goto err_init_hardware;
1526         }
1527
1528         hns3vf_request_link_info(hw);
1529         return 0;
1530
1531 err_init_hardware:
1532         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1533         return ret;
1534 }
1535
1536 static int
1537 hns3vf_clear_vport_list(struct hns3_hw *hw)
1538 {
1539         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1540                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1541                                  NULL, 0);
1542 }
1543
1544 static int
1545 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1546 {
1547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1548         struct hns3_adapter *hns = eth_dev->data->dev_private;
1549         struct hns3_hw *hw = &hns->hw;
1550         int ret;
1551
1552         PMD_INIT_FUNC_TRACE();
1553
1554         /* Get hardware io base address from pcie BAR2 IO space */
1555         hw->io_base = pci_dev->mem_resource[2].addr;
1556
1557         /* Firmware command queue initialize */
1558         ret = hns3_cmd_init_queue(hw);
1559         if (ret) {
1560                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1561                 goto err_cmd_init_queue;
1562         }
1563
1564         /* Firmware command initialize */
1565         ret = hns3_cmd_init(hw);
1566         if (ret) {
1567                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1568                 goto err_cmd_init;
1569         }
1570
1571         /* Get VF resource */
1572         ret = hns3_query_vf_resource(hw);
1573         if (ret)
1574                 goto err_cmd_init;
1575
1576         rte_spinlock_init(&hw->mbx_resp.lock);
1577
1578         hns3vf_clear_event_cause(hw, 0);
1579
1580         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1581                                          hns3vf_interrupt_handler, eth_dev);
1582         if (ret) {
1583                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1584                 goto err_intr_callback_register;
1585         }
1586
1587         /* Enable interrupt */
1588         rte_intr_enable(&pci_dev->intr_handle);
1589         hns3vf_enable_irq0(hw);
1590
1591         /* Get configuration from PF */
1592         ret = hns3vf_get_configuration(hw);
1593         if (ret) {
1594                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1595                 goto err_get_config;
1596         }
1597
1598         /*
1599          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1600          * on the host by "ip link set ..." command. To avoid some incorrect
1601          * scenes, for example, hns3 VF PMD driver fails to receive and send
1602          * packets after user configure the MAC address by using the
1603          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1604          * address strategy as the hns3 kernel ethdev driver in the
1605          * initialization. If user configure a MAC address by the ip command
1606          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1607          * start with a random MAC address in the initialization.
1608          */
1609         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1610         if (ret)
1611                 rte_eth_random_addr(hw->mac.mac_addr);
1612
1613         ret = hns3vf_clear_vport_list(hw);
1614         if (ret) {
1615                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1616                 goto err_get_config;
1617         }
1618
1619         ret = hns3vf_init_hardware(hns);
1620         if (ret)
1621                 goto err_get_config;
1622
1623         hns3_set_default_rss_args(hw);
1624
1625         return 0;
1626
1627 err_get_config:
1628         hns3vf_disable_irq0(hw);
1629         rte_intr_disable(&pci_dev->intr_handle);
1630         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1631                              eth_dev);
1632 err_intr_callback_register:
1633 err_cmd_init:
1634         hns3_cmd_uninit(hw);
1635         hns3_cmd_destroy_queue(hw);
1636 err_cmd_init_queue:
1637         hw->io_base = NULL;
1638
1639         return ret;
1640 }
1641
1642 static void
1643 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1644 {
1645         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1646         struct hns3_adapter *hns = eth_dev->data->dev_private;
1647         struct hns3_hw *hw = &hns->hw;
1648
1649         PMD_INIT_FUNC_TRACE();
1650
1651         hns3_rss_uninit(hns);
1652         (void)hns3vf_set_alive(hw, false);
1653         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1654         hns3vf_disable_irq0(hw);
1655         rte_intr_disable(&pci_dev->intr_handle);
1656         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1657                              eth_dev);
1658         hns3_cmd_uninit(hw);
1659         hns3_cmd_destroy_queue(hw);
1660         hw->io_base = NULL;
1661 }
1662
1663 static int
1664 hns3vf_do_stop(struct hns3_adapter *hns)
1665 {
1666         struct hns3_hw *hw = &hns->hw;
1667         bool reset_queue;
1668
1669         hw->mac.link_status = ETH_LINK_DOWN;
1670
1671         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1672                 hns3vf_configure_mac_addr(hns, true);
1673                 reset_queue = true;
1674         } else
1675                 reset_queue = false;
1676         return hns3_stop_queues(hns, reset_queue);
1677 }
1678
1679 static void
1680 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1681 {
1682         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1684         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1685         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1686         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1687         uint16_t q_id;
1688
1689         if (dev->data->dev_conf.intr_conf.rxq == 0)
1690                 return;
1691
1692         /* unmap the ring with vector */
1693         if (rte_intr_allow_others(intr_handle)) {
1694                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1695                 base = RTE_INTR_VEC_RXTX_OFFSET;
1696         }
1697         if (rte_intr_dp_is_en(intr_handle)) {
1698                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1699                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1700                                                            HNS3_RING_TYPE_RX,
1701                                                            q_id);
1702                         if (vec < base + intr_handle->nb_efd - 1)
1703                                 vec++;
1704                 }
1705         }
1706         /* Clean datapath event and queue/vec mapping */
1707         rte_intr_efd_disable(intr_handle);
1708         if (intr_handle->intr_vec) {
1709                 rte_free(intr_handle->intr_vec);
1710                 intr_handle->intr_vec = NULL;
1711         }
1712 }
1713
1714 static void
1715 hns3vf_dev_stop(struct rte_eth_dev *dev)
1716 {
1717         struct hns3_adapter *hns = dev->data->dev_private;
1718         struct hns3_hw *hw = &hns->hw;
1719
1720         PMD_INIT_FUNC_TRACE();
1721
1722         hw->adapter_state = HNS3_NIC_STOPPING;
1723         hns3_set_rxtx_function(dev);
1724         rte_wmb();
1725         /* Disable datapath on secondary process. */
1726         hns3_mp_req_stop_rxtx(dev);
1727         /* Prevent crashes when queues are still in use. */
1728         rte_delay_ms(hw->tqps_num);
1729
1730         rte_spinlock_lock(&hw->lock);
1731         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1732                 hns3vf_do_stop(hns);
1733                 hns3vf_unmap_rx_interrupt(dev);
1734                 hns3_dev_release_mbufs(hns);
1735                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1736         }
1737         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1738         rte_spinlock_unlock(&hw->lock);
1739 }
1740
1741 static void
1742 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1743 {
1744         struct hns3_adapter *hns = eth_dev->data->dev_private;
1745         struct hns3_hw *hw = &hns->hw;
1746
1747         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748                 return;
1749
1750         if (hw->adapter_state == HNS3_NIC_STARTED)
1751                 hns3vf_dev_stop(eth_dev);
1752
1753         hw->adapter_state = HNS3_NIC_CLOSING;
1754         hns3_reset_abort(hns);
1755         hw->adapter_state = HNS3_NIC_CLOSED;
1756         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1757         hns3vf_configure_all_mc_mac_addr(hns, true);
1758         hns3vf_remove_all_vlan_table(hns);
1759         hns3vf_uninit_vf(eth_dev);
1760         hns3_free_all_queues(eth_dev);
1761         rte_free(hw->reset.wait_data);
1762         rte_free(eth_dev->process_private);
1763         eth_dev->process_private = NULL;
1764         hns3_mp_uninit_primary();
1765         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1766 }
1767
1768 static int
1769 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1770                       size_t fw_size)
1771 {
1772         struct hns3_adapter *hns = eth_dev->data->dev_private;
1773         struct hns3_hw *hw = &hns->hw;
1774         uint32_t version = hw->fw_version;
1775         int ret;
1776
1777         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1778                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1779                                       HNS3_FW_VERSION_BYTE3_S),
1780                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1781                                       HNS3_FW_VERSION_BYTE2_S),
1782                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1783                                       HNS3_FW_VERSION_BYTE1_S),
1784                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1785                                       HNS3_FW_VERSION_BYTE0_S));
1786         ret += 1; /* add the size of '\0' */
1787         if (fw_size < (uint32_t)ret)
1788                 return ret;
1789         else
1790                 return 0;
1791 }
1792
1793 static int
1794 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1795                        __rte_unused int wait_to_complete)
1796 {
1797         struct hns3_adapter *hns = eth_dev->data->dev_private;
1798         struct hns3_hw *hw = &hns->hw;
1799         struct hns3_mac *mac = &hw->mac;
1800         struct rte_eth_link new_link;
1801
1802         memset(&new_link, 0, sizeof(new_link));
1803         switch (mac->link_speed) {
1804         case ETH_SPEED_NUM_10M:
1805         case ETH_SPEED_NUM_100M:
1806         case ETH_SPEED_NUM_1G:
1807         case ETH_SPEED_NUM_10G:
1808         case ETH_SPEED_NUM_25G:
1809         case ETH_SPEED_NUM_40G:
1810         case ETH_SPEED_NUM_50G:
1811         case ETH_SPEED_NUM_100G:
1812                 new_link.link_speed = mac->link_speed;
1813                 break;
1814         default:
1815                 new_link.link_speed = ETH_SPEED_NUM_100M;
1816                 break;
1817         }
1818
1819         new_link.link_duplex = mac->link_duplex;
1820         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1821         new_link.link_autoneg =
1822             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1823
1824         return rte_eth_linkstatus_set(eth_dev, &new_link);
1825 }
1826
1827 static int
1828 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1829 {
1830         struct hns3_hw *hw = &hns->hw;
1831         int ret;
1832
1833         ret = hns3vf_set_tc_info(hns);
1834         if (ret)
1835                 return ret;
1836
1837         ret = hns3_start_queues(hns, reset_queue);
1838         if (ret)
1839                 hns3_err(hw, "Failed to start queues: %d", ret);
1840
1841         return ret;
1842 }
1843
1844 static int
1845 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1846 {
1847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1849         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1851         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1852         uint32_t intr_vector;
1853         uint16_t q_id;
1854         int ret;
1855
1856         if (dev->data->dev_conf.intr_conf.rxq == 0)
1857                 return 0;
1858
1859         /* disable uio/vfio intr/eventfd mapping */
1860         rte_intr_disable(intr_handle);
1861
1862         /* check and configure queue intr-vector mapping */
1863         if (rte_intr_cap_multiple(intr_handle) ||
1864             !RTE_ETH_DEV_SRIOV(dev).active) {
1865                 intr_vector = hw->used_rx_queues;
1866                 /* It creates event fd for each intr vector when MSIX is used */
1867                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1868                         return -EINVAL;
1869         }
1870         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1871                 intr_handle->intr_vec =
1872                         rte_zmalloc("intr_vec",
1873                                     hw->used_rx_queues * sizeof(int), 0);
1874                 if (intr_handle->intr_vec == NULL) {
1875                         hns3_err(hw, "Failed to allocate %d rx_queues"
1876                                      " intr_vec", hw->used_rx_queues);
1877                         ret = -ENOMEM;
1878                         goto vf_alloc_intr_vec_error;
1879                 }
1880         }
1881
1882         if (rte_intr_allow_others(intr_handle)) {
1883                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1884                 base = RTE_INTR_VEC_RXTX_OFFSET;
1885         }
1886         if (rte_intr_dp_is_en(intr_handle)) {
1887                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1888                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1889                                                            HNS3_RING_TYPE_RX,
1890                                                            q_id);
1891                         if (ret)
1892                                 goto vf_bind_vector_error;
1893                         intr_handle->intr_vec[q_id] = vec;
1894                         if (vec < base + intr_handle->nb_efd - 1)
1895                                 vec++;
1896                 }
1897         }
1898         rte_intr_enable(intr_handle);
1899         return 0;
1900
1901 vf_bind_vector_error:
1902         rte_intr_efd_disable(intr_handle);
1903         if (intr_handle->intr_vec) {
1904                 free(intr_handle->intr_vec);
1905                 intr_handle->intr_vec = NULL;
1906         }
1907         return ret;
1908 vf_alloc_intr_vec_error:
1909         rte_intr_efd_disable(intr_handle);
1910         return ret;
1911 }
1912
1913 static int
1914 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
1915 {
1916         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1918         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1919         uint16_t q_id;
1920         int ret;
1921
1922         if (dev->data->dev_conf.intr_conf.rxq == 0)
1923                 return 0;
1924
1925         if (rte_intr_dp_is_en(intr_handle)) {
1926                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1927                         ret = hns3vf_bind_ring_with_vector(hw,
1928                                         intr_handle->intr_vec[q_id], true,
1929                                         HNS3_RING_TYPE_RX, q_id);
1930                         if (ret)
1931                                 return ret;
1932                 }
1933         }
1934
1935         return 0;
1936 }
1937
1938 static void
1939 hns3vf_restore_filter(struct rte_eth_dev *dev)
1940 {
1941         hns3_restore_rss_filter(dev);
1942 }
1943
1944 static int
1945 hns3vf_dev_start(struct rte_eth_dev *dev)
1946 {
1947         struct hns3_adapter *hns = dev->data->dev_private;
1948         struct hns3_hw *hw = &hns->hw;
1949         int ret;
1950
1951         PMD_INIT_FUNC_TRACE();
1952         if (rte_atomic16_read(&hw->reset.resetting))
1953                 return -EBUSY;
1954
1955         rte_spinlock_lock(&hw->lock);
1956         hw->adapter_state = HNS3_NIC_STARTING;
1957         ret = hns3vf_do_start(hns, true);
1958         if (ret) {
1959                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1960                 rte_spinlock_unlock(&hw->lock);
1961                 return ret;
1962         }
1963         ret = hns3vf_map_rx_interrupt(dev);
1964         if (ret) {
1965                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1966                 rte_spinlock_unlock(&hw->lock);
1967                 return ret;
1968         }
1969         hw->adapter_state = HNS3_NIC_STARTED;
1970         rte_spinlock_unlock(&hw->lock);
1971
1972         hns3_set_rxtx_function(dev);
1973         hns3_mp_req_start_rxtx(dev);
1974         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1975
1976         hns3vf_restore_filter(dev);
1977
1978         /* Enable interrupt of all rx queues before enabling queues */
1979         hns3_dev_all_rx_queue_intr_enable(hw, true);
1980         /*
1981          * When finished the initialization, enable queues to receive/transmit
1982          * packets.
1983          */
1984         hns3_enable_all_queues(hw, true);
1985
1986         return ret;
1987 }
1988
1989 static bool
1990 is_vf_reset_done(struct hns3_hw *hw)
1991 {
1992 #define HNS3_FUN_RST_ING_BITS \
1993         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1994          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1995          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1996          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1997
1998         uint32_t val;
1999
2000         if (hw->reset.level == HNS3_VF_RESET) {
2001                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2002                 if (val & HNS3_VF_RST_ING_BIT)
2003                         return false;
2004         } else {
2005                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2006                 if (val & HNS3_FUN_RST_ING_BITS)
2007                         return false;
2008         }
2009         return true;
2010 }
2011
2012 bool
2013 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2014 {
2015         struct hns3_hw *hw = &hns->hw;
2016         enum hns3_reset_level reset;
2017
2018         hns3vf_check_event_cause(hns, NULL);
2019         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2020         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2021                 hns3_warn(hw, "High level reset %d is pending", reset);
2022                 return true;
2023         }
2024         return false;
2025 }
2026
2027 static int
2028 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2029 {
2030         struct hns3_hw *hw = &hns->hw;
2031         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2032         struct timeval tv;
2033
2034         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2035                 /*
2036                  * After vf reset is ready, the PF may not have completed
2037                  * the reset processing. The vf sending mbox to PF may fail
2038                  * during the pf reset, so it is better to add extra delay.
2039                  */
2040                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2041                     hw->reset.level == HNS3_FLR_RESET)
2042                         return 0;
2043                 /* Reset retry process, no need to add extra delay. */
2044                 if (hw->reset.attempts)
2045                         return 0;
2046                 if (wait_data->check_completion == NULL)
2047                         return 0;
2048
2049                 wait_data->check_completion = NULL;
2050                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2051                 wait_data->count = 1;
2052                 wait_data->result = HNS3_WAIT_REQUEST;
2053                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2054                                   wait_data);
2055                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2056                 return -EAGAIN;
2057         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2058                 gettimeofday(&tv, NULL);
2059                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2060                           tv.tv_sec, tv.tv_usec);
2061                 return -ETIME;
2062         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2063                 return -EAGAIN;
2064
2065         wait_data->hns = hns;
2066         wait_data->check_completion = is_vf_reset_done;
2067         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2068                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2069         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2070         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2071         wait_data->result = HNS3_WAIT_REQUEST;
2072         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2073         return -EAGAIN;
2074 }
2075
2076 static int
2077 hns3vf_prepare_reset(struct hns3_adapter *hns)
2078 {
2079         struct hns3_hw *hw = &hns->hw;
2080         int ret = 0;
2081
2082         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2083                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2084                                         0, true, NULL, 0);
2085         }
2086         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2087
2088         return ret;
2089 }
2090
2091 static int
2092 hns3vf_stop_service(struct hns3_adapter *hns)
2093 {
2094         struct hns3_hw *hw = &hns->hw;
2095         struct rte_eth_dev *eth_dev;
2096
2097         eth_dev = &rte_eth_devices[hw->data->port_id];
2098         if (hw->adapter_state == HNS3_NIC_STARTED)
2099                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2100         hw->mac.link_status = ETH_LINK_DOWN;
2101
2102         hns3_set_rxtx_function(eth_dev);
2103         rte_wmb();
2104         /* Disable datapath on secondary process. */
2105         hns3_mp_req_stop_rxtx(eth_dev);
2106         rte_delay_ms(hw->tqps_num);
2107
2108         rte_spinlock_lock(&hw->lock);
2109         if (hw->adapter_state == HNS3_NIC_STARTED ||
2110             hw->adapter_state == HNS3_NIC_STOPPING) {
2111                 hns3vf_do_stop(hns);
2112                 hw->reset.mbuf_deferred_free = true;
2113         } else
2114                 hw->reset.mbuf_deferred_free = false;
2115
2116         /*
2117          * It is cumbersome for hardware to pick-and-choose entries for deletion
2118          * from table space. Hence, for function reset software intervention is
2119          * required to delete the entries.
2120          */
2121         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2122                 hns3vf_configure_all_mc_mac_addr(hns, true);
2123         rte_spinlock_unlock(&hw->lock);
2124
2125         return 0;
2126 }
2127
2128 static int
2129 hns3vf_start_service(struct hns3_adapter *hns)
2130 {
2131         struct hns3_hw *hw = &hns->hw;
2132         struct rte_eth_dev *eth_dev;
2133
2134         eth_dev = &rte_eth_devices[hw->data->port_id];
2135         hns3_set_rxtx_function(eth_dev);
2136         hns3_mp_req_start_rxtx(eth_dev);
2137         if (hw->adapter_state == HNS3_NIC_STARTED) {
2138                 hns3vf_service_handler(eth_dev);
2139
2140                 /* Enable interrupt of all rx queues before enabling queues */
2141                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2142                 /*
2143                  * When finished the initialization, enable queues to receive
2144                  * and transmit packets.
2145                  */
2146                 hns3_enable_all_queues(hw, true);
2147         }
2148
2149         return 0;
2150 }
2151
2152 static int
2153 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2154 {
2155         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2156         struct rte_ether_addr *hw_mac;
2157         int ret;
2158
2159         /*
2160          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2161          * on the host by "ip link set ..." command. If the hns3 PF kernel
2162          * ethdev driver sets the MAC address for VF device after the
2163          * initialization of the related VF device, the PF driver will notify
2164          * VF driver to reset VF device to make the new MAC address effective
2165          * immediately. The hns3 VF PMD driver should check whether the MAC
2166          * address has been changed by the PF kernel ethdev driver, if changed
2167          * VF driver should configure hardware using the new MAC address in the
2168          * recovering hardware configuration stage of the reset process.
2169          */
2170         ret = hns3vf_get_host_mac_addr(hw);
2171         if (ret)
2172                 return ret;
2173
2174         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2175         ret = rte_is_zero_ether_addr(hw_mac);
2176         if (ret) {
2177                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2178         } else {
2179                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2180                 if (!ret) {
2181                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2182                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2183                                               &hw->data->mac_addrs[0]);
2184                         hns3_warn(hw, "Default MAC address has been changed to:"
2185                                   " %s by the host PF kernel ethdev driver",
2186                                   mac_str);
2187                 }
2188         }
2189
2190         return 0;
2191 }
2192
2193 static int
2194 hns3vf_restore_conf(struct hns3_adapter *hns)
2195 {
2196         struct hns3_hw *hw = &hns->hw;
2197         int ret;
2198
2199         ret = hns3vf_check_default_mac_change(hw);
2200         if (ret)
2201                 return ret;
2202
2203         ret = hns3vf_configure_mac_addr(hns, false);
2204         if (ret)
2205                 return ret;
2206
2207         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2208         if (ret)
2209                 goto err_mc_mac;
2210
2211         ret = hns3vf_restore_promisc(hns);
2212         if (ret)
2213                 goto err_vlan_table;
2214
2215         ret = hns3vf_restore_vlan_conf(hns);
2216         if (ret)
2217                 goto err_vlan_table;
2218
2219         ret = hns3vf_restore_rx_interrupt(hw);
2220         if (ret)
2221                 goto err_vlan_table;
2222
2223         if (hw->adapter_state == HNS3_NIC_STARTED) {
2224                 ret = hns3vf_do_start(hns, false);
2225                 if (ret)
2226                         goto err_vlan_table;
2227                 hns3_info(hw, "hns3vf dev restart successful!");
2228         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2229                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2230         return 0;
2231
2232 err_vlan_table:
2233         hns3vf_configure_all_mc_mac_addr(hns, true);
2234 err_mc_mac:
2235         hns3vf_configure_mac_addr(hns, true);
2236         return ret;
2237 }
2238
2239 static enum hns3_reset_level
2240 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2241 {
2242         enum hns3_reset_level reset_level;
2243
2244         /* return the highest priority reset level amongst all */
2245         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2246                 reset_level = HNS3_VF_RESET;
2247         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2248                 reset_level = HNS3_VF_FULL_RESET;
2249         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2250                 reset_level = HNS3_VF_PF_FUNC_RESET;
2251         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2252                 reset_level = HNS3_VF_FUNC_RESET;
2253         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2254                 reset_level = HNS3_FLR_RESET;
2255         else
2256                 reset_level = HNS3_NONE_RESET;
2257
2258         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2259                 return HNS3_NONE_RESET;
2260
2261         return reset_level;
2262 }
2263
2264 static void
2265 hns3vf_reset_service(void *param)
2266 {
2267         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2268         struct hns3_hw *hw = &hns->hw;
2269         enum hns3_reset_level reset_level;
2270         struct timeval tv_delta;
2271         struct timeval tv_start;
2272         struct timeval tv;
2273         uint64_t msec;
2274
2275         /*
2276          * The interrupt is not triggered within the delay time.
2277          * The interrupt may have been lost. It is necessary to handle
2278          * the interrupt to recover from the error.
2279          */
2280         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2281                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2282                 hns3_err(hw, "Handling interrupts in delayed tasks");
2283                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2284                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2285                 if (reset_level == HNS3_NONE_RESET) {
2286                         hns3_err(hw, "No reset level is set, try global reset");
2287                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2288                 }
2289         }
2290         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2291
2292         /*
2293          * Hardware reset has been notified, we now have to poll & check if
2294          * hardware has actually completed the reset sequence.
2295          */
2296         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2297         if (reset_level != HNS3_NONE_RESET) {
2298                 gettimeofday(&tv_start, NULL);
2299                 hns3_reset_process(hns, reset_level);
2300                 gettimeofday(&tv, NULL);
2301                 timersub(&tv, &tv_start, &tv_delta);
2302                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2303                        tv_delta.tv_usec / USEC_PER_MSEC;
2304                 if (msec > HNS3_RESET_PROCESS_MS)
2305                         hns3_err(hw, "%d handle long time delta %" PRIx64
2306                                  " ms time=%ld.%.6ld",
2307                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2308         }
2309 }
2310
2311 static int
2312 hns3vf_reinit_dev(struct hns3_adapter *hns)
2313 {
2314         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2315         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2316         struct hns3_hw *hw = &hns->hw;
2317         int ret;
2318
2319         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2320                 rte_intr_disable(&pci_dev->intr_handle);
2321                 hns3vf_set_bus_master(pci_dev, true);
2322         }
2323
2324         /* Firmware command initialize */
2325         ret = hns3_cmd_init(hw);
2326         if (ret) {
2327                 hns3_err(hw, "Failed to init cmd: %d", ret);
2328                 return ret;
2329         }
2330
2331         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2332                 /*
2333                  * UIO enables msix by writing the pcie configuration space
2334                  * vfio_pci enables msix in rte_intr_enable.
2335                  */
2336                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2337                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2338                         if (hns3vf_enable_msix(pci_dev, true))
2339                                 hns3_err(hw, "Failed to enable msix");
2340                 }
2341
2342                 rte_intr_enable(&pci_dev->intr_handle);
2343         }
2344
2345         ret = hns3_reset_all_queues(hns);
2346         if (ret) {
2347                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2348                 return ret;
2349         }
2350
2351         ret = hns3vf_init_hardware(hns);
2352         if (ret) {
2353                 hns3_err(hw, "Failed to init hardware: %d", ret);
2354                 return ret;
2355         }
2356
2357         return 0;
2358 }
2359
2360 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2361         .dev_start          = hns3vf_dev_start,
2362         .dev_stop           = hns3vf_dev_stop,
2363         .dev_close          = hns3vf_dev_close,
2364         .mtu_set            = hns3vf_dev_mtu_set,
2365         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2366         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2367         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2368         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2369         .stats_get          = hns3_stats_get,
2370         .stats_reset        = hns3_stats_reset,
2371         .xstats_get         = hns3_dev_xstats_get,
2372         .xstats_get_names   = hns3_dev_xstats_get_names,
2373         .xstats_reset       = hns3_dev_xstats_reset,
2374         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2375         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2376         .dev_infos_get      = hns3vf_dev_infos_get,
2377         .fw_version_get     = hns3vf_fw_version_get,
2378         .rx_queue_setup     = hns3_rx_queue_setup,
2379         .tx_queue_setup     = hns3_tx_queue_setup,
2380         .rx_queue_release   = hns3_dev_rx_queue_release,
2381         .tx_queue_release   = hns3_dev_tx_queue_release,
2382         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2383         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2384         .dev_configure      = hns3vf_dev_configure,
2385         .mac_addr_add       = hns3vf_add_mac_addr,
2386         .mac_addr_remove    = hns3vf_remove_mac_addr,
2387         .mac_addr_set       = hns3vf_set_default_mac_addr,
2388         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2389         .link_update        = hns3vf_dev_link_update,
2390         .rss_hash_update    = hns3_dev_rss_hash_update,
2391         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2392         .reta_update        = hns3_dev_rss_reta_update,
2393         .reta_query         = hns3_dev_rss_reta_query,
2394         .filter_ctrl        = hns3_dev_filter_ctrl,
2395         .vlan_filter_set    = hns3vf_vlan_filter_set,
2396         .vlan_offload_set   = hns3vf_vlan_offload_set,
2397         .get_reg            = hns3_get_regs,
2398         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2399 };
2400
2401 static const struct hns3_reset_ops hns3vf_reset_ops = {
2402         .reset_service       = hns3vf_reset_service,
2403         .stop_service        = hns3vf_stop_service,
2404         .prepare_reset       = hns3vf_prepare_reset,
2405         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2406         .reinit_dev          = hns3vf_reinit_dev,
2407         .restore_conf        = hns3vf_restore_conf,
2408         .start_service       = hns3vf_start_service,
2409 };
2410
2411 static int
2412 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2413 {
2414         struct rte_device *dev = eth_dev->device;
2415         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2416         struct hns3_adapter *hns = eth_dev->data->dev_private;
2417         struct hns3_hw *hw = &hns->hw;
2418         uint8_t revision;
2419         int ret;
2420
2421         PMD_INIT_FUNC_TRACE();
2422
2423         /* Get PCI revision id */
2424         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2425                                   HNS3_PCI_REVISION_ID);
2426         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2427                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
2428                              ret);
2429                 return -EIO;
2430         }
2431         hw->revision = revision;
2432
2433         eth_dev->process_private = (struct hns3_process_private *)
2434             rte_zmalloc_socket("hns3_filter_list",
2435                                sizeof(struct hns3_process_private),
2436                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2437         if (eth_dev->process_private == NULL) {
2438                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2439                 return -ENOMEM;
2440         }
2441
2442         /* initialize flow filter lists */
2443         hns3_filterlist_init(eth_dev);
2444
2445         hns3_set_rxtx_function(eth_dev);
2446         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2447         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2448                 hns3_mp_init_secondary();
2449                 hw->secondary_cnt++;
2450                 return 0;
2451         }
2452
2453         hns3_mp_init_primary();
2454
2455         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2456         hns->is_vf = true;
2457         hw->data = eth_dev->data;
2458
2459         ret = hns3_reset_init(hw);
2460         if (ret)
2461                 goto err_init_reset;
2462         hw->reset.ops = &hns3vf_reset_ops;
2463
2464         ret = hns3vf_init_vf(eth_dev);
2465         if (ret) {
2466                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2467                 goto err_init_vf;
2468         }
2469
2470         /* Allocate memory for storing MAC addresses */
2471         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2472                                                sizeof(struct rte_ether_addr) *
2473                                                HNS3_VF_UC_MACADDR_NUM, 0);
2474         if (eth_dev->data->mac_addrs == NULL) {
2475                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2476                              "to store MAC addresses",
2477                              sizeof(struct rte_ether_addr) *
2478                              HNS3_VF_UC_MACADDR_NUM);
2479                 ret = -ENOMEM;
2480                 goto err_rte_zmalloc;
2481         }
2482
2483         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2484                             &eth_dev->data->mac_addrs[0]);
2485         hw->adapter_state = HNS3_NIC_INITIALIZED;
2486         /*
2487          * Pass the information to the rte_eth_dev_close() that it should also
2488          * release the private port resources.
2489          */
2490         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2491
2492         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2493                 hns3_err(hw, "Reschedule reset service after dev_init");
2494                 hns3_schedule_reset(hns);
2495         } else {
2496                 /* IMP will wait ready flag before reset */
2497                 hns3_notify_reset_ready(hw, false);
2498         }
2499         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2500                           eth_dev);
2501         return 0;
2502
2503 err_rte_zmalloc:
2504         hns3vf_uninit_vf(eth_dev);
2505
2506 err_init_vf:
2507         rte_free(hw->reset.wait_data);
2508
2509 err_init_reset:
2510         eth_dev->dev_ops = NULL;
2511         eth_dev->rx_pkt_burst = NULL;
2512         eth_dev->tx_pkt_burst = NULL;
2513         eth_dev->tx_pkt_prepare = NULL;
2514         rte_free(eth_dev->process_private);
2515         eth_dev->process_private = NULL;
2516
2517         return ret;
2518 }
2519
2520 static int
2521 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2522 {
2523         struct hns3_adapter *hns = eth_dev->data->dev_private;
2524         struct hns3_hw *hw = &hns->hw;
2525
2526         PMD_INIT_FUNC_TRACE();
2527
2528         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2529                 return -EPERM;
2530
2531         eth_dev->dev_ops = NULL;
2532         eth_dev->rx_pkt_burst = NULL;
2533         eth_dev->tx_pkt_burst = NULL;
2534         eth_dev->tx_pkt_prepare = NULL;
2535
2536         if (hw->adapter_state < HNS3_NIC_CLOSING)
2537                 hns3vf_dev_close(eth_dev);
2538
2539         hw->adapter_state = HNS3_NIC_REMOVED;
2540         return 0;
2541 }
2542
2543 static int
2544 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2545                      struct rte_pci_device *pci_dev)
2546 {
2547         return rte_eth_dev_pci_generic_probe(pci_dev,
2548                                              sizeof(struct hns3_adapter),
2549                                              hns3vf_dev_init);
2550 }
2551
2552 static int
2553 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2554 {
2555         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2556 }
2557
2558 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2559         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2560         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2561         { .vendor_id = 0, /* sentinel */ },
2562 };
2563
2564 static struct rte_pci_driver rte_hns3vf_pmd = {
2565         .id_table = pci_id_hns3vf_map,
2566         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2567         .probe = eth_hns3vf_pci_probe,
2568         .remove = eth_hns3vf_pci_remove,
2569 };
2570
2571 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2572 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2573 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");