drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static int
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71         int ret;
  72
  73         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  74         if (ret < 0) {
  75                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  76                              PCI_COMMAND);
  77                 return ret;
  78         }
  79
  80         if (op)
  81                 /* set the master bit */
  82                 reg |= PCI_COMMAND_MASTER;
  83         else
  84                 reg &= ~(PCI_COMMAND_MASTER);
  85
  86         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  87 }
  88
  89 /**
  90  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  91  * @cap: the capability
  92  *
  93  * Return the address of the given capability within the PCI capability list.
  94  */
  95 static int
  96 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  97 {
  98 #define MAX_PCIE_CAPABILITY 48
  99         uint16_t status;
 100         uint8_t pos;
 101         uint8_t id;
 102         int ttl;
 103         int ret;
 104
 105         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
 106         if (ret < 0) {
 107                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
 108                 return 0;
 109         }
 110
 111         if (!(status & PCI_STATUS_CAP_LIST))
 112                 return 0;
 113
 114         ttl = MAX_PCIE_CAPABILITY;
 115         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 116                                   PCI_CAPABILITY_LIST);
 117         if (ret < 0) {
 118                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 119                              PCI_CAPABILITY_LIST);
 120                 return 0;
 121         }
 122
 123         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 124                 ret = rte_pci_read_config(device, &id, sizeof(id),
 125                                           (pos + PCI_CAP_LIST_ID));
 126                 if (ret < 0) {
 127                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 128                                      (pos + PCI_CAP_LIST_ID));
 129                         break;
 130                 }
 131
 132                 if (id == 0xFF)
 133                         break;
 134
 135                 if (id == cap)
 136                         return (int)pos;
 137
 138                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 139                                           (pos + PCI_CAP_LIST_NEXT));
 140                 if (ret < 0) {
 141                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 142                                      (pos + PCI_CAP_LIST_NEXT));
 143                         break;
 144                 }
 145         }
 146         return 0;
 147 }
 148
 149 static int
 150 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 151 {
 152         uint16_t control;
 153         int pos;
 154         int ret;
 155
 156         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 157         if (pos) {
 158                 ret = rte_pci_read_config(device, &control, sizeof(control),
 159                                     (pos + PCI_MSIX_FLAGS));
 160                 if (ret < 0) {
 161                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 162                                      (pos + PCI_MSIX_FLAGS));
 163                         return -ENXIO;
 164                 }
 165
 166                 if (op)
 167                         control |= PCI_MSIX_FLAGS_ENABLE;
 168                 else
 169                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 170                 rte_pci_write_config(device, &control, sizeof(control),
 171                                      (pos + PCI_MSIX_FLAGS));
 172                 return 0;
 173         }
 174         return -ENXIO;
 175 }
 176
 177 static int
 178 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 179 {
 180         /* mac address was checked by upper level interface */
 181         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 182         int ret;
 183
 184         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 185                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 186                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 187         if (ret) {
 188                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 189                                       mac_addr);
 190                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 191                          mac_str, ret);
 192         }
 193         return ret;
 194 }
 195
 196 static int
 197 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 198 {
 199         /* mac address was checked by upper level interface */
 200         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 201         int ret;
 202
 203         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 204                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 205                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 206                                 false, NULL, 0);
 207         if (ret) {
 208                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 209                                       mac_addr);
 210                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 211                          mac_str, ret);
 212         }
 213         return ret;
 214 }
 215
 216 static int
 217 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 218 {
 219         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 220         struct rte_ether_addr *addr;
 221         int ret;
 222         int i;
 223
 224         for (i = 0; i < hw->mc_addrs_num; i++) {
 225                 addr = &hw->mc_addrs[i];
 226                 /* Check if there are duplicate addresses */
 227                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 228                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 229                                               addr);
 230                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 231                                  "(%s) is added by the set_mc_mac_addr_list "
 232                                  "API", mac_str);
 233                         return -EINVAL;
 234                 }
 235         }
 236
 237         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 238         if (ret) {
 239                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 240                                       mac_addr);
 241                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 242                          mac_str, ret);
 243         }
 244         return ret;
 245 }
 246
 247 static int
 248 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 249                     __rte_unused uint32_t idx,
 250                     __rte_unused uint32_t pool)
 251 {
 252         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         /*
 259          * In hns3 network engine adding UC and MC mac address with different
 260          * commands with firmware. We need to determine whether the input
 261          * address is a UC or a MC address to call different commands.
 262          * By the way, it is recommended calling the API function named
 263          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 264          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 265          * may affect the specifications of UC mac addresses.
 266          */
 267         if (rte_is_multicast_ether_addr(mac_addr))
 268                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 269         else
 270                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 271
 272         rte_spinlock_unlock(&hw->lock);
 273         if (ret) {
 274                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 275                                       mac_addr);
 276                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 277                          ret);
 278         }
 279
 280         return ret;
 281 }
 282
 283 static void
 284 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 285 {
 286         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 287         /* index will be checked by upper level rte interface */
 288         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 289         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 290         int ret;
 291
 292         rte_spinlock_lock(&hw->lock);
 293
 294         if (rte_is_multicast_ether_addr(mac_addr))
 295                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 296         else
 297                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 298
 299         rte_spinlock_unlock(&hw->lock);
 300         if (ret) {
 301                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 302                                       mac_addr);
 303                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 304                          mac_str, ret);
 305         }
 306 }
 307
 308 static int
 309 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 310                             struct rte_ether_addr *mac_addr)
 311 {
 312 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 313         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 314         struct rte_ether_addr *old_addr;
 315         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 316         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 317         int ret;
 318
 319         /*
 320          * It has been guaranteed that input parameter named mac_addr is valid
 321          * address in the rte layer of DPDK framework.
 322          */
 323         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 324         rte_spinlock_lock(&hw->lock);
 325         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 326         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 327                RTE_ETHER_ADDR_LEN);
 328
 329         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 330                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 331                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 332         if (ret) {
 333                 /*
 334                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 335                  * driver. When user has configured a MAC address for VF device
 336                  * by "ip link set ..." command based on the PF device, the hns3
 337                  * PF kernel ethdev driver does not allow VF driver to request
 338                  * reconfiguring a different default MAC address, and return
 339                  * -EPREM to VF driver through mailbox.
 340                  */
 341                 if (ret == -EPERM) {
 342                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 343                                               old_addr);
 344                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 345                                   mac_str);
 346                 } else {
 347                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 348                                               mac_addr);
 349                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 350                                  mac_str, ret);
 351                 }
 352         }
 353
 354         rte_ether_addr_copy(mac_addr,
 355                             (struct rte_ether_addr *)hw->mac.mac_addr);
 356         rte_spinlock_unlock(&hw->lock);
 357
 358         return ret;
 359 }
 360
 361 static int
 362 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 363 {
 364         struct hns3_hw *hw = &hns->hw;
 365         struct rte_ether_addr *addr;
 366         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 367         int err = 0;
 368         int ret;
 369         int i;
 370
 371         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 372                 addr = &hw->data->mac_addrs[i];
 373                 if (rte_is_zero_ether_addr(addr))
 374                         continue;
 375                 if (rte_is_multicast_ether_addr(addr))
 376                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 377                               hns3vf_add_mc_mac_addr(hw, addr);
 378                 else
 379                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 380                               hns3vf_add_uc_mac_addr(hw, addr);
 381
 382                 if (ret) {
 383                         err = ret;
 384                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 385                                               addr);
 386                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 387                                  "ret = %d.", del ? "remove" : "restore",
 388                                  mac_str, i, ret);
 389                 }
 390         }
 391         return err;
 392 }
 393
 394 static int
 395 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 396                        struct rte_ether_addr *mac_addr)
 397 {
 398         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 399         int ret;
 400
 401         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 402                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 403                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 404                                 NULL, 0);
 405         if (ret) {
 406                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 407                                       mac_addr);
 408                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 409                          mac_str, ret);
 410         }
 411
 412         return ret;
 413 }
 414
 415 static int
 416 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 417                           struct rte_ether_addr *mac_addr)
 418 {
 419         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 420         int ret;
 421
 422         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 423                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 424                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 425                                 NULL, 0);
 426         if (ret) {
 427                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 428                                       mac_addr);
 429                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 430                          mac_str, ret);
 431         }
 432
 433         return ret;
 434 }
 435
 436 static int
 437 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 438                              struct rte_ether_addr *mc_addr_set,
 439                              uint32_t nb_mc_addr)
 440 {
 441         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 442         struct rte_ether_addr *addr;
 443         uint32_t i;
 444         uint32_t j;
 445
 446         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 447                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 448                          "invalid. valid range: 0~%d",
 449                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 450                 return -EINVAL;
 451         }
 452
 453         /* Check if input mac addresses are valid */
 454         for (i = 0; i < nb_mc_addr; i++) {
 455                 addr = &mc_addr_set[i];
 456                 if (!rte_is_multicast_ether_addr(addr)) {
 457                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 458                                               addr);
 459                         hns3_err(hw,
 460                                  "failed to set mc mac addr, addr(%s) invalid.",
 461                                  mac_str);
 462                         return -EINVAL;
 463                 }
 464
 465                 /* Check if there are duplicate addresses */
 466                 for (j = i + 1; j < nb_mc_addr; j++) {
 467                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 468                                 rte_ether_format_addr(mac_str,
 469                                                       RTE_ETHER_ADDR_FMT_SIZE,
 470                                                       addr);
 471                                 hns3_err(hw, "failed to set mc mac addr, "
 472                                          "addrs invalid. two same addrs(%s).",
 473                                          mac_str);
 474                                 return -EINVAL;
 475                         }
 476                 }
 477
 478                 /*
 479                  * Check if there are duplicate addresses between mac_addrs
 480                  * and mc_addr_set
 481                  */
 482                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 483                         if (rte_is_same_ether_addr(addr,
 484                                                    &hw->data->mac_addrs[j])) {
 485                                 rte_ether_format_addr(mac_str,
 486                                                       RTE_ETHER_ADDR_FMT_SIZE,
 487                                                       addr);
 488                                 hns3_err(hw, "failed to set mc mac addr, "
 489                                          "addrs invalid. addrs(%s) has already "
 490                                          "configured in mac_addr add API",
 491                                          mac_str);
 492                                 return -EINVAL;
 493                         }
 494                 }
 495         }
 496
 497         return 0;
 498 }
 499
 500 static int
 501 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 502                             struct rte_ether_addr *mc_addr_set,
 503                             uint32_t nb_mc_addr)
 504 {
 505         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506         struct rte_ether_addr *addr;
 507         int cur_addr_num;
 508         int set_addr_num;
 509         int num;
 510         int ret;
 511         int i;
 512
 513         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 514         if (ret)
 515                 return ret;
 516
 517         rte_spinlock_lock(&hw->lock);
 518         cur_addr_num = hw->mc_addrs_num;
 519         for (i = 0; i < cur_addr_num; i++) {
 520                 num = cur_addr_num - i - 1;
 521                 addr = &hw->mc_addrs[num];
 522                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 523                 if (ret) {
 524                         rte_spinlock_unlock(&hw->lock);
 525                         return ret;
 526                 }
 527
 528                 hw->mc_addrs_num--;
 529         }
 530
 531         set_addr_num = (int)nb_mc_addr;
 532         for (i = 0; i < set_addr_num; i++) {
 533                 addr = &mc_addr_set[i];
 534                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 535                 if (ret) {
 536                         rte_spinlock_unlock(&hw->lock);
 537                         return ret;
 538                 }
 539
 540                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 541                 hw->mc_addrs_num++;
 542         }
 543         rte_spinlock_unlock(&hw->lock);
 544
 545         return 0;
 546 }
 547
 548 static int
 549 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 550 {
 551         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 552         struct hns3_hw *hw = &hns->hw;
 553         struct rte_ether_addr *addr;
 554         int err = 0;
 555         int ret;
 556         int i;
 557
 558         for (i = 0; i < hw->mc_addrs_num; i++) {
 559                 addr = &hw->mc_addrs[i];
 560                 if (!rte_is_multicast_ether_addr(addr))
 561                         continue;
 562                 if (del)
 563                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 564                 else
 565                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 566                 if (ret) {
 567                         err = ret;
 568                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 569                                               addr);
 570                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 571                                  del ? "Remove" : "Restore", mac_str, ret);
 572                 }
 573         }
 574         return err;
 575 }
 576
 577 static int
 578 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 579                         bool en_uc_pmc, bool en_mc_pmc)
 580 {
 581         struct hns3_mbx_vf_to_pf_cmd *req;
 582         struct hns3_cmd_desc desc;
 583         int ret;
 584
 585         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 586
 587         /*
 588          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 589          * so there are some features for promiscuous/allmulticast mode in hns3
 590          * VF PMD driver as below:
 591          * 1. The promiscuous/allmulticast mode can be configured successfully
 592          *    only based on the trusted VF device. If based on the non trusted
 593          *    VF device, configuring promiscuous/allmulticast mode will fail.
 594          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 595          *    kernel ethdev driver on the host by the following command:
 596          *      "ip link set <eth num> vf <vf id> turst on"
 597          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 598          *    driver can receive the ingress and outgoing traffic. In the words,
 599          *    all the ingress packets, all the packets sent from the PF and
 600          *    other VFs on the same physical port.
 601          * 3. Note: Because of the hardware constraints, By default vlan filter
 602          *    is enabled and couldn't be turned off based on VF device, so vlan
 603          *    filter is still effective even in promiscuous mode. If upper
 604          *    applications don't call rte_eth_dev_vlan_filter API function to
 605          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 606          *    the packets with vlan tag in promiscuoue mode.
 607          */
 608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 609         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 610         req->msg[1] = en_bc_pmc ? 1 : 0;
 611         req->msg[2] = en_uc_pmc ? 1 : 0;
 612         req->msg[3] = en_mc_pmc ? 1 : 0;
 613
 614         ret = hns3_cmd_send(hw, &desc, 1);
 615         if (ret)
 616                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 617
 618         return ret;
 619 }
 620
 621 static int
 622 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 623 {
 624         struct hns3_adapter *hns = dev->data->dev_private;
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 629         if (ret)
 630                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 631                         ret);
 632         return ret;
 633 }
 634
 635 static int
 636 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 637 {
 638         bool allmulti = dev->data->all_multicast ? true : false;
 639         struct hns3_adapter *hns = dev->data->dev_private;
 640         struct hns3_hw *hw = &hns->hw;
 641         int ret;
 642
 643         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 644         if (ret)
 645                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 646                         ret);
 647         return ret;
 648 }
 649
 650 static int
 651 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 652 {
 653         struct hns3_adapter *hns = dev->data->dev_private;
 654         struct hns3_hw *hw = &hns->hw;
 655         int ret;
 656
 657         if (dev->data->promiscuous)
 658                 return 0;
 659
 660         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 661         if (ret)
 662                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 663                         ret);
 664         return ret;
 665 }
 666
 667 static int
 668 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 669 {
 670         struct hns3_adapter *hns = dev->data->dev_private;
 671         struct hns3_hw *hw = &hns->hw;
 672         int ret;
 673
 674         if (dev->data->promiscuous)
 675                 return 0;
 676
 677         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 678         if (ret)
 679                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 680                         ret);
 681         return ret;
 682 }
 683
 684 static int
 685 hns3vf_restore_promisc(struct hns3_adapter *hns)
 686 {
 687         struct hns3_hw *hw = &hns->hw;
 688         bool allmulti = hw->data->all_multicast ? true : false;
 689
 690         if (hw->data->promiscuous)
 691                 return hns3vf_set_promisc_mode(hw, true, true, true);
 692
 693         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 694 }
 695
 696 static int
 697 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 698                              bool mmap, enum hns3_ring_type queue_type,
 699                              uint16_t queue_id)
 700 {
 701         struct hns3_vf_bind_vector_msg bind_msg;
 702         const char *op_str;
 703         uint16_t code;
 704         int ret;
 705
 706         memset(&bind_msg, 0, sizeof(bind_msg));
 707         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 708                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 709         bind_msg.vector_id = vector_id;
 710
 711         if (queue_type == HNS3_RING_TYPE_RX)
 712                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 713         else
 714                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 715
 716         bind_msg.param[0].ring_type = queue_type;
 717         bind_msg.ring_num = 1;
 718         bind_msg.param[0].tqp_index = queue_id;
 719         op_str = mmap ? "Map" : "Unmap";
 720         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 721                                 sizeof(bind_msg), false, NULL, 0);
 722         if (ret)
 723                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 724                          op_str, queue_id, bind_msg.vector_id, ret);
 725
 726         return ret;
 727 }
 728
 729 static int
 730 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 731 {
 732         uint16_t vec;
 733         int ret;
 734         int i;
 735
 736         /*
 737          * In hns3 network engine, vector 0 is always the misc interrupt of this
 738          * function, vector 1~N can be used respectively for the queues of the
 739          * function. Tx and Rx queues with the same number share the interrupt
 740          * vector. In the initialization clearing the all hardware mapping
 741          * relationship configurations between queues and interrupt vectors is
 742          * needed, so some error caused by the residual configurations, such as
 743          * the unexpected Tx interrupt, can be avoid.
 744          */
 745         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 746         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 747                 vec = vec - 1; /* the last interrupt is reserved */
 748         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 749         for (i = 0; i < hw->intr_tqps_num; i++) {
 750                 /*
 751                  * Set gap limiter/rate limiter/quanity limiter algorithm
 752                  * configuration for interrupt coalesce of queue's interrupt.
 753                  */
 754                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 755                                        HNS3_TQP_INTR_GL_DEFAULT);
 756                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 757                                        HNS3_TQP_INTR_GL_DEFAULT);
 758                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 759                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 760
 761                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 762                                                    HNS3_RING_TYPE_TX, i);
 763                 if (ret) {
 764                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 765                                           "vector: %d, ret=%d", i, vec, ret);
 766                         return ret;
 767                 }
 768
 769                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 770                                                    HNS3_RING_TYPE_RX, i);
 771                 if (ret) {
 772                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 773                                           "vector: %d, ret=%d", i, vec, ret);
 774                         return ret;
 775                 }
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int
 782 hns3vf_dev_configure(struct rte_eth_dev *dev)
 783 {
 784         struct hns3_adapter *hns = dev->data->dev_private;
 785         struct hns3_hw *hw = &hns->hw;
 786         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 787         struct rte_eth_conf *conf = &dev->data->dev_conf;
 788         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 789         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 790         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 791         struct rte_eth_rss_conf rss_conf;
 792         uint16_t mtu;
 793         bool gro_en;
 794         int ret;
 795
 796         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 797
 798         /*
 799          * Some versions of hardware network engine does not support
 800          * individually enable/disable/reset the Tx or Rx queue. These devices
 801          * must enable/disable/reset Tx and Rx queues at the same time. When the
 802          * numbers of Tx queues allocated by upper applications are not equal to
 803          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 804          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 805          * work as usual. But these fake queues are imperceptible, and can not
 806          * be used by upper applications.
 807          */
 808         if (!hns3_dev_indep_txrx_supported(hw)) {
 809                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 810                 if (ret) {
 811                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
 812                                  ret);
 813                         return ret;
 814                 }
 815         }
 816
 817         hw->adapter_state = HNS3_NIC_CONFIGURING;
 818         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 819                 hns3_err(hw, "setting link speed/duplex not supported");
 820                 ret = -EINVAL;
 821                 goto cfg_err;
 822         }
 823
 824         /* When RSS is not configured, redirect the packet queue 0 */
 825         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 826                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 827                 hw->rss_dis_flag = false;
 828                 rss_conf = conf->rx_adv_conf.rss_conf;
 829                 if (rss_conf.rss_key == NULL) {
 830                         rss_conf.rss_key = rss_cfg->key;
 831                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 832                 }
 833
 834                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 835                 if (ret)
 836                         goto cfg_err;
 837         }
 838
 839         /*
 840          * If jumbo frames are enabled, MTU needs to be refreshed
 841          * according to the maximum RX packet length.
 842          */
 843         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 844                 /*
 845                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 846                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 847                  * can safely assign to "uint16_t" type variable.
 848                  */
 849                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 850                 ret = hns3vf_dev_mtu_set(dev, mtu);
 851                 if (ret)
 852                         goto cfg_err;
 853                 dev->data->mtu = mtu;
 854         }
 855
 856         ret = hns3vf_dev_configure_vlan(dev);
 857         if (ret)
 858                 goto cfg_err;
 859
 860         /* config hardware GRO */
 861         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 862         ret = hns3_config_gro(hw, gro_en);
 863         if (ret)
 864                 goto cfg_err;
 865
 866         hns->rx_simple_allowed = true;
 867         hns->rx_vec_allowed = true;
 868         hns->tx_simple_allowed = true;
 869         hns->tx_vec_allowed = true;
 870
 871         hns3_init_rx_ptype_tble(dev);
 872
 873         hw->adapter_state = HNS3_NIC_CONFIGURED;
 874         return 0;
 875
 876 cfg_err:
 877         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 878         hw->adapter_state = HNS3_NIC_INITIALIZED;
 879
 880         return ret;
 881 }
 882
 883 static int
 884 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 885 {
 886         int ret;
 887
 888         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 889                                 sizeof(mtu), true, NULL, 0);
 890         if (ret)
 891                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 892
 893         return ret;
 894 }
 895
 896 static int
 897 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 898 {
 899         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 900         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 901         int ret;
 902
 903         /*
 904          * The hns3 PF/VF devices on the same port share the hardware MTU
 905          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 906          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 907          * driver, there is no need to stop the port for hns3 VF device, and the
 908          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 909          * PF's MTU.
 910          */
 911         if (rte_atomic16_read(&hw->reset.resetting)) {
 912                 hns3_err(hw, "Failed to set mtu during resetting");
 913                 return -EIO;
 914         }
 915
 916         /*
 917          * when Rx of scattered packets is off, we have some possibility of
 918          * using vector Rx process function or simple Rx functions in hns3 PMD
 919          * driver. If the input MTU is increased and the maximum length of
 920          * received packets is greater than the length of a buffer for Rx
 921          * packet, the hardware network engine needs to use multiple BDs and
 922          * buffers to store these packets. This will cause problems when still
 923          * using vector Rx process function or simple Rx function to receiving
 924          * packets. So, when Rx of scattered packets is off and device is
 925          * started, it is not permitted to increase MTU so that the maximum
 926          * length of Rx packets is greater than Rx buffer length.
 927          */
 928         if (dev->data->dev_started && !dev->data->scattered_rx &&
 929             frame_size > hw->rx_buf_len) {
 930                 hns3_err(hw, "failed to set mtu because current is "
 931                         "not scattered rx mode");
 932                 return -EOPNOTSUPP;
 933         }
 934
 935         rte_spinlock_lock(&hw->lock);
 936         ret = hns3vf_config_mtu(hw, mtu);
 937         if (ret) {
 938                 rte_spinlock_unlock(&hw->lock);
 939                 return ret;
 940         }
 941         if (frame_size > RTE_ETHER_MAX_LEN)
 942                 dev->data->dev_conf.rxmode.offloads |=
 943                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 944         else
 945                 dev->data->dev_conf.rxmode.offloads &=
 946                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 947         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 948         rte_spinlock_unlock(&hw->lock);
 949
 950         return 0;
 951 }
 952
 953 static int
 954 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 955 {
 956         struct hns3_adapter *hns = eth_dev->data->dev_private;
 957         struct hns3_hw *hw = &hns->hw;
 958         uint16_t q_num = hw->tqps_num;
 959
 960         /*
 961          * In interrupt mode, 'max_rx_queues' is set based on the number of
 962          * MSI-X interrupt resources of the hardware.
 963          */
 964         if (hw->data->dev_conf.intr_conf.rxq == 1)
 965                 q_num = hw->intr_tqps_num;
 966
 967         info->max_rx_queues = q_num;
 968         info->max_tx_queues = hw->tqps_num;
 969         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 970         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 971         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 972         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 973         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 974
 975         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 976                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 977                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 978                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 979                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 980                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 981                                  DEV_RX_OFFLOAD_SCATTER |
 982                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 983                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 984                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 985                                  DEV_RX_OFFLOAD_RSS_HASH |
 986                                  DEV_RX_OFFLOAD_TCP_LRO);
 987         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 988                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 989                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 990                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 991                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 992                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 993                                  DEV_TX_OFFLOAD_TCP_TSO |
 994                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 995                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 996                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 997                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 998                                  hns3_txvlan_cap_get(hw));
 999
1000         if (hns3_dev_indep_txrx_supported(hw))
1001                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1002                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1003
1004         info->rx_desc_lim = (struct rte_eth_desc_lim) {
1005                 .nb_max = HNS3_MAX_RING_DESC,
1006                 .nb_min = HNS3_MIN_RING_DESC,
1007                 .nb_align = HNS3_ALIGN_RING_DESC,
1008         };
1009
1010         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1011                 .nb_max = HNS3_MAX_RING_DESC,
1012                 .nb_min = HNS3_MIN_RING_DESC,
1013                 .nb_align = HNS3_ALIGN_RING_DESC,
1014                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
1015                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
1016         };
1017
1018         info->default_rxconf = (struct rte_eth_rxconf) {
1019                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
1020                 /*
1021                  * If there are no available Rx buffer descriptors, incoming
1022                  * packets are always dropped by hardware based on hns3 network
1023                  * engine.
1024                  */
1025                 .rx_drop_en = 1,
1026                 .offloads = 0,
1027         };
1028         info->default_txconf = (struct rte_eth_txconf) {
1029                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1030                 .offloads = 0,
1031         };
1032
1033         info->vmdq_queue_num = 0;
1034
1035         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1036         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1037         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1038         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1039         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1040
1041         return 0;
1042 }
1043
1044 static void
1045 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1046 {
1047         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1048 }
1049
1050 static void
1051 hns3vf_disable_irq0(struct hns3_hw *hw)
1052 {
1053         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1054 }
1055
1056 static void
1057 hns3vf_enable_irq0(struct hns3_hw *hw)
1058 {
1059         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1060 }
1061
1062 static enum hns3vf_evt_cause
1063 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1064 {
1065         struct hns3_hw *hw = &hns->hw;
1066         enum hns3vf_evt_cause ret;
1067         uint32_t cmdq_stat_reg;
1068         uint32_t rst_ing_reg;
1069         uint32_t val;
1070
1071         /* Fetch the events from their corresponding regs */
1072         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1073
1074         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1075                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1076                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1077                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1078                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1079                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1080                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1081                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1082                 if (clearval) {
1083                         hw->reset.stats.global_cnt++;
1084                         hns3_warn(hw, "Global reset detected, clear reset status");
1085                 } else {
1086                         hns3_schedule_delayed_reset(hns);
1087                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1088                 }
1089
1090                 ret = HNS3VF_VECTOR0_EVENT_RST;
1091                 goto out;
1092         }
1093
1094         /* Check for vector0 mailbox(=CMDQ RX) event source */
1095         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1096                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1097                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1098                 goto out;
1099         }
1100
1101         val = 0;
1102         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1103 out:
1104         if (clearval)
1105                 *clearval = val;
1106         return ret;
1107 }
1108
1109 static void
1110 hns3vf_interrupt_handler(void *param)
1111 {
1112         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1113         struct hns3_adapter *hns = dev->data->dev_private;
1114         struct hns3_hw *hw = &hns->hw;
1115         enum hns3vf_evt_cause event_cause;
1116         uint32_t clearval;
1117
1118         if (hw->irq_thread_id == 0)
1119                 hw->irq_thread_id = pthread_self();
1120
1121         /* Disable interrupt */
1122         hns3vf_disable_irq0(hw);
1123
1124         /* Read out interrupt causes */
1125         event_cause = hns3vf_check_event_cause(hns, &clearval);
1126
1127         switch (event_cause) {
1128         case HNS3VF_VECTOR0_EVENT_RST:
1129                 hns3_schedule_reset(hns);
1130                 break;
1131         case HNS3VF_VECTOR0_EVENT_MBX:
1132                 hns3_dev_handle_mbx_msg(hw);
1133                 break;
1134         default:
1135                 break;
1136         }
1137
1138         /* Clear interrupt causes */
1139         hns3vf_clear_event_cause(hw, clearval);
1140
1141         /* Enable interrupt */
1142         hns3vf_enable_irq0(hw);
1143 }
1144
1145 static void
1146 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1147 {
1148         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1149         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1150         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1151 }
1152
1153 static void
1154 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1155 {
1156         struct hns3_dev_specs_0_cmd *req0;
1157
1158         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1159
1160         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1161         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1162         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1163 }
1164
1165 static int
1166 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1167 {
1168         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1169         int ret;
1170         int i;
1171
1172         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1173                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1174                                           true);
1175                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1176         }
1177         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1178
1179         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1180         if (ret)
1181                 return ret;
1182
1183         hns3vf_parse_dev_specifications(hw, desc);
1184
1185         return 0;
1186 }
1187
1188 static int
1189 hns3vf_get_capability(struct hns3_hw *hw)
1190 {
1191         struct rte_pci_device *pci_dev;
1192         struct rte_eth_dev *eth_dev;
1193         uint8_t revision;
1194         int ret;
1195
1196         eth_dev = &rte_eth_devices[hw->data->port_id];
1197         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1198
1199         /* Get PCI revision id */
1200         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1201                                   HNS3_PCI_REVISION_ID);
1202         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1203                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1204                              ret);
1205                 return -EIO;
1206         }
1207         hw->revision = revision;
1208
1209         if (revision < PCI_REVISION_ID_HIP09_A) {
1210                 hns3vf_set_default_dev_specifications(hw);
1211                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1212                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1213                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1214                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1215                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1216                 return 0;
1217         }
1218
1219         ret = hns3vf_query_dev_specifications(hw);
1220         if (ret) {
1221                 PMD_INIT_LOG(ERR,
1222                              "failed to query dev specifications, ret = %d",
1223                              ret);
1224                 return ret;
1225         }
1226
1227         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1228         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1229         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1230         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1231         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1232
1233         return 0;
1234 }
1235
1236 static int
1237 hns3vf_check_tqp_info(struct hns3_hw *hw)
1238 {
1239         if (hw->tqps_num == 0) {
1240                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1241                 return -EINVAL;
1242         }
1243
1244         if (hw->rss_size_max == 0) {
1245                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1246                 return -EINVAL;
1247         }
1248
1249         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1250
1251         return 0;
1252 }
1253
1254 static int
1255 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1256 {
1257         uint8_t resp_msg;
1258         int ret;
1259
1260         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1261                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1262                                 true, &resp_msg, sizeof(resp_msg));
1263         if (ret) {
1264                 if (ret == -ETIME) {
1265                         /*
1266                          * Getting current port based VLAN state from PF driver
1267                          * will not affect VF driver's basic function. Because
1268                          * the VF driver relies on hns3 PF kernel ether driver,
1269                          * to avoid introducing compatibility issues with older
1270                          * version of PF driver, no failure will be returned
1271                          * when the return value is ETIME. This return value has
1272                          * the following scenarios:
1273                          * 1) Firmware didn't return the results in time
1274                          * 2) the result return by firmware is timeout
1275                          * 3) the older version of kernel side PF driver does
1276                          *    not support this mailbox message.
1277                          * For scenarios 1 and 2, it is most likely that a
1278                          * hardware error has occurred, or a hardware reset has
1279                          * occurred. In this case, these errors will be caught
1280                          * by other functions.
1281                          */
1282                         PMD_INIT_LOG(WARNING,
1283                                 "failed to get PVID state for timeout, maybe "
1284                                 "kernel side PF driver doesn't support this "
1285                                 "mailbox message, or firmware didn't respond.");
1286                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1287                 } else {
1288                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1289                                 " ret = %d", ret);
1290                         return ret;
1291                 }
1292         }
1293         hw->port_base_vlan_cfg.state = resp_msg ?
1294                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1295         return 0;
1296 }
1297
1298 static int
1299 hns3vf_get_queue_info(struct hns3_hw *hw)
1300 {
1301 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1302         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1303         int ret;
1304
1305         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1306                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1307         if (ret) {
1308                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1309                 return ret;
1310         }
1311
1312         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1313         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1314
1315         return hns3vf_check_tqp_info(hw);
1316 }
1317
1318 static int
1319 hns3vf_get_queue_depth(struct hns3_hw *hw)
1320 {
1321 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1322         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1323         int ret;
1324
1325         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1326                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1327         if (ret) {
1328                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1329                              ret);
1330                 return ret;
1331         }
1332
1333         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1334         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1335
1336         return 0;
1337 }
1338
1339 static int
1340 hns3vf_get_tc_info(struct hns3_hw *hw)
1341 {
1342         uint8_t resp_msg;
1343         int ret;
1344         int i;
1345
1346         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1347                                 true, &resp_msg, sizeof(resp_msg));
1348         if (ret) {
1349                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1350                          ret);
1351                 return ret;
1352         }
1353
1354         hw->hw_tc_map = resp_msg;
1355
1356         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1357                 if (hw->hw_tc_map & BIT(i))
1358                         hw->num_tc++;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int
1365 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1366 {
1367         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1368         int ret;
1369
1370         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1371                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1372         if (ret) {
1373                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1374                 return ret;
1375         }
1376
1377         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1378
1379         return 0;
1380 }
1381
1382 static int
1383 hns3vf_get_configuration(struct hns3_hw *hw)
1384 {
1385         int ret;
1386
1387         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1388         hw->rss_dis_flag = false;
1389
1390         /* Get device capability */
1391         ret = hns3vf_get_capability(hw);
1392         if (ret) {
1393                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1394                 return ret;
1395         }
1396
1397         /* Get queue configuration from PF */
1398         ret = hns3vf_get_queue_info(hw);
1399         if (ret)
1400                 return ret;
1401
1402         /* Get queue depth info from PF */
1403         ret = hns3vf_get_queue_depth(hw);
1404         if (ret)
1405                 return ret;
1406
1407         /* Get user defined VF MAC addr from PF */
1408         ret = hns3vf_get_host_mac_addr(hw);
1409         if (ret)
1410                 return ret;
1411
1412         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1413         if (ret)
1414                 return ret;
1415
1416         /* Get tc configuration from PF */
1417         return hns3vf_get_tc_info(hw);
1418 }
1419
1420 static int
1421 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1422                             uint16_t nb_tx_q)
1423 {
1424         struct hns3_hw *hw = &hns->hw;
1425
1426         if (nb_rx_q < hw->num_tc) {
1427                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1428                          nb_rx_q, hw->num_tc);
1429                 return -EINVAL;
1430         }
1431
1432         if (nb_tx_q < hw->num_tc) {
1433                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1434                          nb_tx_q, hw->num_tc);
1435                 return -EINVAL;
1436         }
1437
1438         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1439 }
1440
1441 static void
1442 hns3vf_request_link_info(struct hns3_hw *hw)
1443 {
1444         uint8_t resp_msg;
1445         int ret;
1446
1447         if (rte_atomic16_read(&hw->reset.resetting))
1448                 return;
1449         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1450                                 &resp_msg, sizeof(resp_msg));
1451         if (ret)
1452                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1453 }
1454
1455 static int
1456 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1457 {
1458 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1459         struct hns3_hw *hw = &hns->hw;
1460         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1461         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1462         uint8_t is_kill = on ? 0 : 1;
1463
1464         msg_data[0] = is_kill;
1465         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1466         memcpy(&msg_data[3], &proto, sizeof(proto));
1467
1468         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1469                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1470                                  0);
1471 }
1472
1473 static int
1474 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1475 {
1476         struct hns3_adapter *hns = dev->data->dev_private;
1477         struct hns3_hw *hw = &hns->hw;
1478         int ret;
1479
1480         if (rte_atomic16_read(&hw->reset.resetting)) {
1481                 hns3_err(hw,
1482                          "vf set vlan id failed during resetting, vlan_id =%u",
1483                          vlan_id);
1484                 return -EIO;
1485         }
1486         rte_spinlock_lock(&hw->lock);
1487         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1488         rte_spinlock_unlock(&hw->lock);
1489         if (ret)
1490                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1491                          vlan_id, ret);
1492
1493         return ret;
1494 }
1495
1496 static int
1497 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1498 {
1499         uint8_t msg_data;
1500         int ret;
1501
1502         msg_data = enable ? 1 : 0;
1503         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1504                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1505         if (ret)
1506                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1507
1508         return ret;
1509 }
1510
1511 static int
1512 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1513 {
1514         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1515         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1516         unsigned int tmp_mask;
1517         int ret = 0;
1518
1519         if (rte_atomic16_read(&hw->reset.resetting)) {
1520                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1521                              "mask = 0x%x", mask);
1522                 return -EIO;
1523         }
1524
1525         tmp_mask = (unsigned int)mask;
1526         /* Vlan stripping setting */
1527         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1528                 rte_spinlock_lock(&hw->lock);
1529                 /* Enable or disable VLAN stripping */
1530                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1531                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1532                 else
1533                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1534                 rte_spinlock_unlock(&hw->lock);
1535         }
1536
1537         return ret;
1538 }
1539
1540 static int
1541 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1542 {
1543         struct rte_vlan_filter_conf *vfc;
1544         struct hns3_hw *hw = &hns->hw;
1545         uint16_t vlan_id;
1546         uint64_t vbit;
1547         uint64_t ids;
1548         int ret = 0;
1549         uint32_t i;
1550
1551         vfc = &hw->data->vlan_filter_conf;
1552         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1553                 if (vfc->ids[i] == 0)
1554                         continue;
1555                 ids = vfc->ids[i];
1556                 while (ids) {
1557                         /*
1558                          * 64 means the num bits of ids, one bit corresponds to
1559                          * one vlan id
1560                          */
1561                         vlan_id = 64 * i;
1562                         /* count trailing zeroes */
1563                         vbit = ~ids & (ids - 1);
1564                         /* clear least significant bit set */
1565                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1566                         for (; vbit;) {
1567                                 vbit >>= 1;
1568                                 vlan_id++;
1569                         }
1570                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1571                         if (ret) {
1572                                 hns3_err(hw,
1573                                          "VF handle vlan table failed, ret =%d, on = %d",
1574                                          ret, on);
1575                                 return ret;
1576                         }
1577                 }
1578         }
1579
1580         return ret;
1581 }
1582
1583 static int
1584 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1585 {
1586         return hns3vf_handle_all_vlan_table(hns, 0);
1587 }
1588
1589 static int
1590 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1591 {
1592         struct hns3_hw *hw = &hns->hw;
1593         struct rte_eth_conf *dev_conf;
1594         bool en;
1595         int ret;
1596
1597         dev_conf = &hw->data->dev_conf;
1598         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1599                                                                    : false;
1600         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1601         if (ret)
1602                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1603                          ret);
1604         return ret;
1605 }
1606
1607 static int
1608 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1609 {
1610         struct hns3_adapter *hns = dev->data->dev_private;
1611         struct rte_eth_dev_data *data = dev->data;
1612         struct hns3_hw *hw = &hns->hw;
1613         int ret;
1614
1615         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1616             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1617             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1618                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1619                               "or hw_vlan_insert_pvid is not support!");
1620         }
1621
1622         /* Apply vlan offload setting */
1623         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1624         if (ret)
1625                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1626
1627         return ret;
1628 }
1629
1630 static int
1631 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1632 {
1633         uint8_t msg_data;
1634
1635         msg_data = alive ? 1 : 0;
1636         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1637                                  sizeof(msg_data), false, NULL, 0);
1638 }
1639
1640 static void
1641 hns3vf_keep_alive_handler(void *param)
1642 {
1643         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1644         struct hns3_adapter *hns = eth_dev->data->dev_private;
1645         struct hns3_hw *hw = &hns->hw;
1646         uint8_t respmsg;
1647         int ret;
1648
1649         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1650                                 false, &respmsg, sizeof(uint8_t));
1651         if (ret)
1652                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1653                          ret);
1654
1655         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1656                           eth_dev);
1657 }
1658
1659 static void
1660 hns3vf_service_handler(void *param)
1661 {
1662         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1663         struct hns3_adapter *hns = eth_dev->data->dev_private;
1664         struct hns3_hw *hw = &hns->hw;
1665
1666         /*
1667          * The query link status and reset processing are executed in the
1668          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1669          * and the query operation will time out after 30ms. In the case of
1670          * multiple PF/VFs, each query failure timeout causes the IMP reset
1671          * interrupt to fail to respond within 100ms.
1672          * Before querying the link status, check whether there is a reset
1673          * pending, and if so, abandon the query.
1674          */
1675         if (!hns3vf_is_reset_pending(hns))
1676                 hns3vf_request_link_info(hw);
1677         else
1678                 hns3_warn(hw, "Cancel the query when reset is pending");
1679
1680         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1681                           eth_dev);
1682 }
1683
1684 static int
1685 hns3_query_vf_resource(struct hns3_hw *hw)
1686 {
1687         struct hns3_vf_res_cmd *req;
1688         struct hns3_cmd_desc desc;
1689         uint16_t num_msi;
1690         int ret;
1691
1692         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1693         ret = hns3_cmd_send(hw, &desc, 1);
1694         if (ret) {
1695                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1696                 return ret;
1697         }
1698
1699         req = (struct hns3_vf_res_cmd *)desc.data;
1700         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1701                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1702         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1703                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1704                          num_msi, HNS3_MIN_VECTOR_NUM);
1705                 return -EINVAL;
1706         }
1707
1708         hw->num_msi = num_msi;
1709
1710         return 0;
1711 }
1712
1713 static int
1714 hns3vf_init_hardware(struct hns3_adapter *hns)
1715 {
1716         struct hns3_hw *hw = &hns->hw;
1717         uint16_t mtu = hw->data->mtu;
1718         int ret;
1719
1720         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1721         if (ret)
1722                 return ret;
1723
1724         ret = hns3vf_config_mtu(hw, mtu);
1725         if (ret)
1726                 goto err_init_hardware;
1727
1728         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1729         if (ret) {
1730                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1731                 goto err_init_hardware;
1732         }
1733
1734         ret = hns3_config_gro(hw, false);
1735         if (ret) {
1736                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1737                 goto err_init_hardware;
1738         }
1739
1740         /*
1741          * In the initialization clearing the all hardware mapping relationship
1742          * configurations between queues and interrupt vectors is needed, so
1743          * some error caused by the residual configurations, such as the
1744          * unexpected interrupt, can be avoid.
1745          */
1746         ret = hns3vf_init_ring_with_vector(hw);
1747         if (ret) {
1748                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1749                 goto err_init_hardware;
1750         }
1751
1752         ret = hns3vf_set_alive(hw, true);
1753         if (ret) {
1754                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1755                 goto err_init_hardware;
1756         }
1757
1758         hns3vf_request_link_info(hw);
1759         return 0;
1760
1761 err_init_hardware:
1762         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1763         return ret;
1764 }
1765
1766 static int
1767 hns3vf_clear_vport_list(struct hns3_hw *hw)
1768 {
1769         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1770                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1771                                  NULL, 0);
1772 }
1773
1774 static int
1775 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1776 {
1777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1778         struct hns3_adapter *hns = eth_dev->data->dev_private;
1779         struct hns3_hw *hw = &hns->hw;
1780         int ret;
1781
1782         PMD_INIT_FUNC_TRACE();
1783
1784         /* Get hardware io base address from pcie BAR2 IO space */
1785         hw->io_base = pci_dev->mem_resource[2].addr;
1786
1787         /* Firmware command queue initialize */
1788         ret = hns3_cmd_init_queue(hw);
1789         if (ret) {
1790                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1791                 goto err_cmd_init_queue;
1792         }
1793
1794         /* Firmware command initialize */
1795         ret = hns3_cmd_init(hw);
1796         if (ret) {
1797                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1798                 goto err_cmd_init;
1799         }
1800
1801         /* Get VF resource */
1802         ret = hns3_query_vf_resource(hw);
1803         if (ret)
1804                 goto err_cmd_init;
1805
1806         rte_spinlock_init(&hw->mbx_resp.lock);
1807
1808         hns3vf_clear_event_cause(hw, 0);
1809
1810         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1811                                          hns3vf_interrupt_handler, eth_dev);
1812         if (ret) {
1813                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1814                 goto err_intr_callback_register;
1815         }
1816
1817         /* Enable interrupt */
1818         rte_intr_enable(&pci_dev->intr_handle);
1819         hns3vf_enable_irq0(hw);
1820
1821         /* Get configuration from PF */
1822         ret = hns3vf_get_configuration(hw);
1823         if (ret) {
1824                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1825                 goto err_get_config;
1826         }
1827
1828         ret = hns3_tqp_stats_init(hw);
1829         if (ret)
1830                 goto err_get_config;
1831
1832         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1833         if (ret) {
1834                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1835                 goto err_set_tc_queue;
1836         }
1837
1838         ret = hns3vf_clear_vport_list(hw);
1839         if (ret) {
1840                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1841                 goto err_set_tc_queue;
1842         }
1843
1844         ret = hns3vf_init_hardware(hns);
1845         if (ret)
1846                 goto err_set_tc_queue;
1847
1848         hns3_set_default_rss_args(hw);
1849
1850         return 0;
1851
1852 err_set_tc_queue:
1853         hns3_tqp_stats_uninit(hw);
1854
1855 err_get_config:
1856         hns3vf_disable_irq0(hw);
1857         rte_intr_disable(&pci_dev->intr_handle);
1858         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1859                              eth_dev);
1860 err_intr_callback_register:
1861 err_cmd_init:
1862         hns3_cmd_uninit(hw);
1863         hns3_cmd_destroy_queue(hw);
1864 err_cmd_init_queue:
1865         hw->io_base = NULL;
1866
1867         return ret;
1868 }
1869
1870 static void
1871 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1872 {
1873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1874         struct hns3_adapter *hns = eth_dev->data->dev_private;
1875         struct hns3_hw *hw = &hns->hw;
1876
1877         PMD_INIT_FUNC_TRACE();
1878
1879         hns3_rss_uninit(hns);
1880         (void)hns3_config_gro(hw, false);
1881         (void)hns3vf_set_alive(hw, false);
1882         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1883         hns3_tqp_stats_uninit(hw);
1884         hns3vf_disable_irq0(hw);
1885         rte_intr_disable(&pci_dev->intr_handle);
1886         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1887                              eth_dev);
1888         hns3_cmd_uninit(hw);
1889         hns3_cmd_destroy_queue(hw);
1890         hw->io_base = NULL;
1891 }
1892
1893 static int
1894 hns3vf_do_stop(struct hns3_adapter *hns)
1895 {
1896         struct hns3_hw *hw = &hns->hw;
1897         int ret;
1898
1899         hw->mac.link_status = ETH_LINK_DOWN;
1900
1901         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1902                 hns3vf_configure_mac_addr(hns, true);
1903                 ret = hns3_reset_all_tqps(hns);
1904                 if (ret) {
1905                         hns3_err(hw, "failed to reset all queues ret = %d",
1906                                  ret);
1907                         return ret;
1908                 }
1909         }
1910         return 0;
1911 }
1912
1913 static void
1914 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1915 {
1916         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1918         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1919         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1920         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1921         uint16_t q_id;
1922
1923         if (dev->data->dev_conf.intr_conf.rxq == 0)
1924                 return;
1925
1926         /* unmap the ring with vector */
1927         if (rte_intr_allow_others(intr_handle)) {
1928                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1929                 base = RTE_INTR_VEC_RXTX_OFFSET;
1930         }
1931         if (rte_intr_dp_is_en(intr_handle)) {
1932                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1933                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1934                                                            HNS3_RING_TYPE_RX,
1935                                                            q_id);
1936                         if (vec < base + intr_handle->nb_efd - 1)
1937                                 vec++;
1938                 }
1939         }
1940         /* Clean datapath event and queue/vec mapping */
1941         rte_intr_efd_disable(intr_handle);
1942         if (intr_handle->intr_vec) {
1943                 rte_free(intr_handle->intr_vec);
1944                 intr_handle->intr_vec = NULL;
1945         }
1946 }
1947
1948 static void
1949 hns3vf_dev_stop(struct rte_eth_dev *dev)
1950 {
1951         struct hns3_adapter *hns = dev->data->dev_private;
1952         struct hns3_hw *hw = &hns->hw;
1953
1954         PMD_INIT_FUNC_TRACE();
1955
1956         hw->adapter_state = HNS3_NIC_STOPPING;
1957         hns3_set_rxtx_function(dev);
1958         rte_wmb();
1959         /* Disable datapath on secondary process. */
1960         hns3_mp_req_stop_rxtx(dev);
1961         /* Prevent crashes when queues are still in use. */
1962         rte_delay_ms(hw->tqps_num);
1963
1964         rte_spinlock_lock(&hw->lock);
1965         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1966                 hns3_stop_tqps(hw);
1967                 hns3vf_do_stop(hns);
1968                 hns3vf_unmap_rx_interrupt(dev);
1969                 hns3_dev_release_mbufs(hns);
1970                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1971         }
1972         hns3_rx_scattered_reset(dev);
1973         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1974         rte_spinlock_unlock(&hw->lock);
1975 }
1976
1977 static int
1978 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1979 {
1980         struct hns3_adapter *hns = eth_dev->data->dev_private;
1981         struct hns3_hw *hw = &hns->hw;
1982
1983         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1984                 return 0;
1985
1986         if (hw->adapter_state == HNS3_NIC_STARTED)
1987                 hns3vf_dev_stop(eth_dev);
1988
1989         hw->adapter_state = HNS3_NIC_CLOSING;
1990         hns3_reset_abort(hns);
1991         hw->adapter_state = HNS3_NIC_CLOSED;
1992         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1993         hns3vf_configure_all_mc_mac_addr(hns, true);
1994         hns3vf_remove_all_vlan_table(hns);
1995         hns3vf_uninit_vf(eth_dev);
1996         hns3_free_all_queues(eth_dev);
1997         rte_free(hw->reset.wait_data);
1998         rte_free(eth_dev->process_private);
1999         eth_dev->process_private = NULL;
2000         hns3_mp_uninit_primary();
2001         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
2002
2003         return 0;
2004 }
2005
2006 static int
2007 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2008                       size_t fw_size)
2009 {
2010         struct hns3_adapter *hns = eth_dev->data->dev_private;
2011         struct hns3_hw *hw = &hns->hw;
2012         uint32_t version = hw->fw_version;
2013         int ret;
2014
2015         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2016                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2017                                       HNS3_FW_VERSION_BYTE3_S),
2018                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2019                                       HNS3_FW_VERSION_BYTE2_S),
2020                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2021                                       HNS3_FW_VERSION_BYTE1_S),
2022                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2023                                       HNS3_FW_VERSION_BYTE0_S));
2024         ret += 1; /* add the size of '\0' */
2025         if (fw_size < (uint32_t)ret)
2026                 return ret;
2027         else
2028                 return 0;
2029 }
2030
2031 static int
2032 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2033                        __rte_unused int wait_to_complete)
2034 {
2035         struct hns3_adapter *hns = eth_dev->data->dev_private;
2036         struct hns3_hw *hw = &hns->hw;
2037         struct hns3_mac *mac = &hw->mac;
2038         struct rte_eth_link new_link;
2039
2040         memset(&new_link, 0, sizeof(new_link));
2041         switch (mac->link_speed) {
2042         case ETH_SPEED_NUM_10M:
2043         case ETH_SPEED_NUM_100M:
2044         case ETH_SPEED_NUM_1G:
2045         case ETH_SPEED_NUM_10G:
2046         case ETH_SPEED_NUM_25G:
2047         case ETH_SPEED_NUM_40G:
2048         case ETH_SPEED_NUM_50G:
2049         case ETH_SPEED_NUM_100G:
2050         case ETH_SPEED_NUM_200G:
2051                 new_link.link_speed = mac->link_speed;
2052                 break;
2053         default:
2054                 new_link.link_speed = ETH_SPEED_NUM_100M;
2055                 break;
2056         }
2057
2058         new_link.link_duplex = mac->link_duplex;
2059         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2060         new_link.link_autoneg =
2061             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2062
2063         return rte_eth_linkstatus_set(eth_dev, &new_link);
2064 }
2065
2066 static int
2067 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2068 {
2069         struct hns3_hw *hw = &hns->hw;
2070         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2071         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2072         int ret;
2073
2074         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2075         if (ret)
2076                 return ret;
2077
2078         ret = hns3_init_queues(hns, reset_queue);
2079         if (ret)
2080                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2081
2082         return ret;
2083 }
2084
2085 static int
2086 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2087 {
2088         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2089         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2090         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2092         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2093         uint32_t intr_vector;
2094         uint16_t q_id;
2095         int ret;
2096
2097         if (dev->data->dev_conf.intr_conf.rxq == 0)
2098                 return 0;
2099
2100         /* disable uio/vfio intr/eventfd mapping */
2101         rte_intr_disable(intr_handle);
2102
2103         /* check and configure queue intr-vector mapping */
2104         if (rte_intr_cap_multiple(intr_handle) ||
2105             !RTE_ETH_DEV_SRIOV(dev).active) {
2106                 intr_vector = hw->used_rx_queues;
2107                 /* It creates event fd for each intr vector when MSIX is used */
2108                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2109                         return -EINVAL;
2110         }
2111         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2112                 intr_handle->intr_vec =
2113                         rte_zmalloc("intr_vec",
2114                                     hw->used_rx_queues * sizeof(int), 0);
2115                 if (intr_handle->intr_vec == NULL) {
2116                         hns3_err(hw, "Failed to allocate %d rx_queues"
2117                                      " intr_vec", hw->used_rx_queues);
2118                         ret = -ENOMEM;
2119                         goto vf_alloc_intr_vec_error;
2120                 }
2121         }
2122
2123         if (rte_intr_allow_others(intr_handle)) {
2124                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2125                 base = RTE_INTR_VEC_RXTX_OFFSET;
2126         }
2127         if (rte_intr_dp_is_en(intr_handle)) {
2128                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2129                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2130                                                            HNS3_RING_TYPE_RX,
2131                                                            q_id);
2132                         if (ret)
2133                                 goto vf_bind_vector_error;
2134                         intr_handle->intr_vec[q_id] = vec;
2135                         if (vec < base + intr_handle->nb_efd - 1)
2136                                 vec++;
2137                 }
2138         }
2139         rte_intr_enable(intr_handle);
2140         return 0;
2141
2142 vf_bind_vector_error:
2143         rte_intr_efd_disable(intr_handle);
2144         if (intr_handle->intr_vec) {
2145                 free(intr_handle->intr_vec);
2146                 intr_handle->intr_vec = NULL;
2147         }
2148         return ret;
2149 vf_alloc_intr_vec_error:
2150         rte_intr_efd_disable(intr_handle);
2151         return ret;
2152 }
2153
2154 static int
2155 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2156 {
2157         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2158         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2159         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2160         uint16_t q_id;
2161         int ret;
2162
2163         if (dev->data->dev_conf.intr_conf.rxq == 0)
2164                 return 0;
2165
2166         if (rte_intr_dp_is_en(intr_handle)) {
2167                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2168                         ret = hns3vf_bind_ring_with_vector(hw,
2169                                         intr_handle->intr_vec[q_id], true,
2170                                         HNS3_RING_TYPE_RX, q_id);
2171                         if (ret)
2172                                 return ret;
2173                 }
2174         }
2175
2176         return 0;
2177 }
2178
2179 static void
2180 hns3vf_restore_filter(struct rte_eth_dev *dev)
2181 {
2182         hns3_restore_rss_filter(dev);
2183 }
2184
2185 static int
2186 hns3vf_dev_start(struct rte_eth_dev *dev)
2187 {
2188         struct hns3_adapter *hns = dev->data->dev_private;
2189         struct hns3_hw *hw = &hns->hw;
2190         int ret;
2191
2192         PMD_INIT_FUNC_TRACE();
2193         if (rte_atomic16_read(&hw->reset.resetting))
2194                 return -EBUSY;
2195
2196         rte_spinlock_lock(&hw->lock);
2197         hw->adapter_state = HNS3_NIC_STARTING;
2198         ret = hns3vf_do_start(hns, true);
2199         if (ret) {
2200                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2201                 rte_spinlock_unlock(&hw->lock);
2202                 return ret;
2203         }
2204         ret = hns3vf_map_rx_interrupt(dev);
2205         if (ret) {
2206                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2207                 rte_spinlock_unlock(&hw->lock);
2208                 return ret;
2209         }
2210
2211         /*
2212          * There are three register used to control the status of a TQP
2213          * (contains a pair of Tx queue and Rx queue) in the new version network
2214          * engine. One is used to control the enabling of Tx queue, the other is
2215          * used to control the enabling of Rx queue, and the last is the master
2216          * switch used to control the enabling of the tqp. The Tx register and
2217          * TQP register must be enabled at the same time to enable a Tx queue.
2218          * The same applies to the Rx queue. For the older network enginem, this
2219          * function only refresh the enabled flag, and it is used to update the
2220          * status of queue in the dpdk framework.
2221          */
2222         ret = hns3_start_all_txqs(dev);
2223         if (ret) {
2224                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2225                 rte_spinlock_unlock(&hw->lock);
2226                 return ret;
2227         }
2228
2229         ret = hns3_start_all_rxqs(dev);
2230         if (ret) {
2231                 hns3_stop_all_txqs(dev);
2232                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2233                 rte_spinlock_unlock(&hw->lock);
2234                 return ret;
2235         }
2236
2237         hw->adapter_state = HNS3_NIC_STARTED;
2238         rte_spinlock_unlock(&hw->lock);
2239
2240         hns3_rx_scattered_calc(dev);
2241         hns3_set_rxtx_function(dev);
2242         hns3_mp_req_start_rxtx(dev);
2243         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2244
2245         hns3vf_restore_filter(dev);
2246
2247         /* Enable interrupt of all rx queues before enabling queues */
2248         hns3_dev_all_rx_queue_intr_enable(hw, true);
2249
2250         /*
2251          * After finished the initialization, start all tqps to receive/transmit
2252          * packets and refresh all queue status.
2253          */
2254         hns3_start_tqps(hw);
2255
2256         return ret;
2257 }
2258
2259 static bool
2260 is_vf_reset_done(struct hns3_hw *hw)
2261 {
2262 #define HNS3_FUN_RST_ING_BITS \
2263         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2264          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2265          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2266          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2267
2268         uint32_t val;
2269
2270         if (hw->reset.level == HNS3_VF_RESET) {
2271                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2272                 if (val & HNS3_VF_RST_ING_BIT)
2273                         return false;
2274         } else {
2275                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2276                 if (val & HNS3_FUN_RST_ING_BITS)
2277                         return false;
2278         }
2279         return true;
2280 }
2281
2282 bool
2283 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2284 {
2285         struct hns3_hw *hw = &hns->hw;
2286         enum hns3_reset_level reset;
2287
2288         /*
2289          * According to the protocol of PCIe, FLR to a PF device resets the PF
2290          * state as well as the SR-IOV extended capability including VF Enable
2291          * which means that VFs no longer exist.
2292          *
2293          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2294          * is in FLR stage, the register state of VF device is not reliable,
2295          * so register states detection can not be carried out. In this case,
2296          * we just ignore the register states and return false to indicate that
2297          * there are no other reset states that need to be processed by driver.
2298          */
2299         if (hw->reset.level == HNS3_VF_FULL_RESET)
2300                 return false;
2301
2302         /* Check the registers to confirm whether there is reset pending */
2303         hns3vf_check_event_cause(hns, NULL);
2304         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2305         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2306                 hns3_warn(hw, "High level reset %d is pending", reset);
2307                 return true;
2308         }
2309         return false;
2310 }
2311
2312 static int
2313 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2314 {
2315         struct hns3_hw *hw = &hns->hw;
2316         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2317         struct timeval tv;
2318
2319         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2320                 /*
2321                  * After vf reset is ready, the PF may not have completed
2322                  * the reset processing. The vf sending mbox to PF may fail
2323                  * during the pf reset, so it is better to add extra delay.
2324                  */
2325                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2326                     hw->reset.level == HNS3_FLR_RESET)
2327                         return 0;
2328                 /* Reset retry process, no need to add extra delay. */
2329                 if (hw->reset.attempts)
2330                         return 0;
2331                 if (wait_data->check_completion == NULL)
2332                         return 0;
2333
2334                 wait_data->check_completion = NULL;
2335                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2336                 wait_data->count = 1;
2337                 wait_data->result = HNS3_WAIT_REQUEST;
2338                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2339                                   wait_data);
2340                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2341                 return -EAGAIN;
2342         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2343                 gettimeofday(&tv, NULL);
2344                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2345                           tv.tv_sec, tv.tv_usec);
2346                 return -ETIME;
2347         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2348                 return -EAGAIN;
2349
2350         wait_data->hns = hns;
2351         wait_data->check_completion = is_vf_reset_done;
2352         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2353                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2354         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2355         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2356         wait_data->result = HNS3_WAIT_REQUEST;
2357         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2358         return -EAGAIN;
2359 }
2360
2361 static int
2362 hns3vf_prepare_reset(struct hns3_adapter *hns)
2363 {
2364         struct hns3_hw *hw = &hns->hw;
2365         int ret = 0;
2366
2367         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2368                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2369                                         0, true, NULL, 0);
2370         }
2371         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2372
2373         return ret;
2374 }
2375
2376 static int
2377 hns3vf_stop_service(struct hns3_adapter *hns)
2378 {
2379         struct hns3_hw *hw = &hns->hw;
2380         struct rte_eth_dev *eth_dev;
2381
2382         eth_dev = &rte_eth_devices[hw->data->port_id];
2383         if (hw->adapter_state == HNS3_NIC_STARTED)
2384                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2385         hw->mac.link_status = ETH_LINK_DOWN;
2386
2387         hns3_set_rxtx_function(eth_dev);
2388         rte_wmb();
2389         /* Disable datapath on secondary process. */
2390         hns3_mp_req_stop_rxtx(eth_dev);
2391         rte_delay_ms(hw->tqps_num);
2392
2393         rte_spinlock_lock(&hw->lock);
2394         if (hw->adapter_state == HNS3_NIC_STARTED ||
2395             hw->adapter_state == HNS3_NIC_STOPPING) {
2396                 hns3_enable_all_queues(hw, false);
2397                 hns3vf_do_stop(hns);
2398                 hw->reset.mbuf_deferred_free = true;
2399         } else
2400                 hw->reset.mbuf_deferred_free = false;
2401
2402         /*
2403          * It is cumbersome for hardware to pick-and-choose entries for deletion
2404          * from table space. Hence, for function reset software intervention is
2405          * required to delete the entries.
2406          */
2407         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2408                 hns3vf_configure_all_mc_mac_addr(hns, true);
2409         rte_spinlock_unlock(&hw->lock);
2410
2411         return 0;
2412 }
2413
2414 static int
2415 hns3vf_start_service(struct hns3_adapter *hns)
2416 {
2417         struct hns3_hw *hw = &hns->hw;
2418         struct rte_eth_dev *eth_dev;
2419
2420         eth_dev = &rte_eth_devices[hw->data->port_id];
2421         hns3_set_rxtx_function(eth_dev);
2422         hns3_mp_req_start_rxtx(eth_dev);
2423         if (hw->adapter_state == HNS3_NIC_STARTED) {
2424                 hns3vf_service_handler(eth_dev);
2425
2426                 /* Enable interrupt of all rx queues before enabling queues */
2427                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2428                 /*
2429                  * When finished the initialization, enable queues to receive
2430                  * and transmit packets.
2431                  */
2432                 hns3_enable_all_queues(hw, true);
2433         }
2434
2435         return 0;
2436 }
2437
2438 static int
2439 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2440 {
2441         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2442         struct rte_ether_addr *hw_mac;
2443         int ret;
2444
2445         /*
2446          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2447          * on the host by "ip link set ..." command. If the hns3 PF kernel
2448          * ethdev driver sets the MAC address for VF device after the
2449          * initialization of the related VF device, the PF driver will notify
2450          * VF driver to reset VF device to make the new MAC address effective
2451          * immediately. The hns3 VF PMD driver should check whether the MAC
2452          * address has been changed by the PF kernel ethdev driver, if changed
2453          * VF driver should configure hardware using the new MAC address in the
2454          * recovering hardware configuration stage of the reset process.
2455          */
2456         ret = hns3vf_get_host_mac_addr(hw);
2457         if (ret)
2458                 return ret;
2459
2460         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2461         ret = rte_is_zero_ether_addr(hw_mac);
2462         if (ret) {
2463                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2464         } else {
2465                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2466                 if (!ret) {
2467                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2468                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2469                                               &hw->data->mac_addrs[0]);
2470                         hns3_warn(hw, "Default MAC address has been changed to:"
2471                                   " %s by the host PF kernel ethdev driver",
2472                                   mac_str);
2473                 }
2474         }
2475
2476         return 0;
2477 }
2478
2479 static int
2480 hns3vf_restore_conf(struct hns3_adapter *hns)
2481 {
2482         struct hns3_hw *hw = &hns->hw;
2483         int ret;
2484
2485         ret = hns3vf_check_default_mac_change(hw);
2486         if (ret)
2487                 return ret;
2488
2489         ret = hns3vf_configure_mac_addr(hns, false);
2490         if (ret)
2491                 return ret;
2492
2493         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2494         if (ret)
2495                 goto err_mc_mac;
2496
2497         ret = hns3vf_restore_promisc(hns);
2498         if (ret)
2499                 goto err_vlan_table;
2500
2501         ret = hns3vf_restore_vlan_conf(hns);
2502         if (ret)
2503                 goto err_vlan_table;
2504
2505         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2506         if (ret)
2507                 goto err_vlan_table;
2508
2509         ret = hns3vf_restore_rx_interrupt(hw);
2510         if (ret)
2511                 goto err_vlan_table;
2512
2513         ret = hns3_restore_gro_conf(hw);
2514         if (ret)
2515                 goto err_vlan_table;
2516
2517         if (hw->adapter_state == HNS3_NIC_STARTED) {
2518                 ret = hns3vf_do_start(hns, false);
2519                 if (ret)
2520                         goto err_vlan_table;
2521                 hns3_info(hw, "hns3vf dev restart successful!");
2522         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2523                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2524         return 0;
2525
2526 err_vlan_table:
2527         hns3vf_configure_all_mc_mac_addr(hns, true);
2528 err_mc_mac:
2529         hns3vf_configure_mac_addr(hns, true);
2530         return ret;
2531 }
2532
2533 static enum hns3_reset_level
2534 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2535 {
2536         enum hns3_reset_level reset_level;
2537
2538         /* return the highest priority reset level amongst all */
2539         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2540                 reset_level = HNS3_VF_RESET;
2541         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2542                 reset_level = HNS3_VF_FULL_RESET;
2543         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2544                 reset_level = HNS3_VF_PF_FUNC_RESET;
2545         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2546                 reset_level = HNS3_VF_FUNC_RESET;
2547         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2548                 reset_level = HNS3_FLR_RESET;
2549         else
2550                 reset_level = HNS3_NONE_RESET;
2551
2552         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2553                 return HNS3_NONE_RESET;
2554
2555         return reset_level;
2556 }
2557
2558 static void
2559 hns3vf_reset_service(void *param)
2560 {
2561         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2562         struct hns3_hw *hw = &hns->hw;
2563         enum hns3_reset_level reset_level;
2564         struct timeval tv_delta;
2565         struct timeval tv_start;
2566         struct timeval tv;
2567         uint64_t msec;
2568
2569         /*
2570          * The interrupt is not triggered within the delay time.
2571          * The interrupt may have been lost. It is necessary to handle
2572          * the interrupt to recover from the error.
2573          */
2574         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2575                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2576                 hns3_err(hw, "Handling interrupts in delayed tasks");
2577                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2578                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2579                 if (reset_level == HNS3_NONE_RESET) {
2580                         hns3_err(hw, "No reset level is set, try global reset");
2581                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2582                 }
2583         }
2584         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2585
2586         /*
2587          * Hardware reset has been notified, we now have to poll & check if
2588          * hardware has actually completed the reset sequence.
2589          */
2590         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2591         if (reset_level != HNS3_NONE_RESET) {
2592                 gettimeofday(&tv_start, NULL);
2593                 hns3_reset_process(hns, reset_level);
2594                 gettimeofday(&tv, NULL);
2595                 timersub(&tv, &tv_start, &tv_delta);
2596                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2597                        tv_delta.tv_usec / USEC_PER_MSEC;
2598                 if (msec > HNS3_RESET_PROCESS_MS)
2599                         hns3_err(hw, "%d handle long time delta %" PRIx64
2600                                  " ms time=%ld.%.6ld",
2601                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2602         }
2603 }
2604
2605 static int
2606 hns3vf_reinit_dev(struct hns3_adapter *hns)
2607 {
2608         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2610         struct hns3_hw *hw = &hns->hw;
2611         int ret;
2612
2613         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2614                 rte_intr_disable(&pci_dev->intr_handle);
2615                 ret = hns3vf_set_bus_master(pci_dev, true);
2616                 if (ret) {
2617                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2618                         return ret;
2619                 }
2620         }
2621
2622         /* Firmware command initialize */
2623         ret = hns3_cmd_init(hw);
2624         if (ret) {
2625                 hns3_err(hw, "Failed to init cmd: %d", ret);
2626                 return ret;
2627         }
2628
2629         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2630                 /*
2631                  * UIO enables msix by writing the pcie configuration space
2632                  * vfio_pci enables msix in rte_intr_enable.
2633                  */
2634                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2635                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2636                         if (hns3vf_enable_msix(pci_dev, true))
2637                                 hns3_err(hw, "Failed to enable msix");
2638                 }
2639
2640                 rte_intr_enable(&pci_dev->intr_handle);
2641         }
2642
2643         ret = hns3_reset_all_tqps(hns);
2644         if (ret) {
2645                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2646                 return ret;
2647         }
2648
2649         ret = hns3vf_init_hardware(hns);
2650         if (ret) {
2651                 hns3_err(hw, "Failed to init hardware: %d", ret);
2652                 return ret;
2653         }
2654
2655         return 0;
2656 }
2657
2658 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2659         .dev_configure      = hns3vf_dev_configure,
2660         .dev_start          = hns3vf_dev_start,
2661         .dev_stop           = hns3vf_dev_stop,
2662         .dev_close          = hns3vf_dev_close,
2663         .mtu_set            = hns3vf_dev_mtu_set,
2664         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2665         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2666         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2667         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2668         .stats_get          = hns3_stats_get,
2669         .stats_reset        = hns3_stats_reset,
2670         .xstats_get         = hns3_dev_xstats_get,
2671         .xstats_get_names   = hns3_dev_xstats_get_names,
2672         .xstats_reset       = hns3_dev_xstats_reset,
2673         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2674         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2675         .dev_infos_get      = hns3vf_dev_infos_get,
2676         .fw_version_get     = hns3vf_fw_version_get,
2677         .rx_queue_setup     = hns3_rx_queue_setup,
2678         .tx_queue_setup     = hns3_tx_queue_setup,
2679         .rx_queue_release   = hns3_dev_rx_queue_release,
2680         .tx_queue_release   = hns3_dev_tx_queue_release,
2681         .rx_queue_start     = hns3_dev_rx_queue_start,
2682         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2683         .tx_queue_start     = hns3_dev_tx_queue_start,
2684         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2685         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2686         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2687         .rxq_info_get       = hns3_rxq_info_get,
2688         .txq_info_get       = hns3_txq_info_get,
2689         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2690         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2691         .mac_addr_add       = hns3vf_add_mac_addr,
2692         .mac_addr_remove    = hns3vf_remove_mac_addr,
2693         .mac_addr_set       = hns3vf_set_default_mac_addr,
2694         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2695         .link_update        = hns3vf_dev_link_update,
2696         .rss_hash_update    = hns3_dev_rss_hash_update,
2697         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2698         .reta_update        = hns3_dev_rss_reta_update,
2699         .reta_query         = hns3_dev_rss_reta_query,
2700         .filter_ctrl        = hns3_dev_filter_ctrl,
2701         .vlan_filter_set    = hns3vf_vlan_filter_set,
2702         .vlan_offload_set   = hns3vf_vlan_offload_set,
2703         .get_reg            = hns3_get_regs,
2704         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2705 };
2706
2707 static const struct hns3_reset_ops hns3vf_reset_ops = {
2708         .reset_service       = hns3vf_reset_service,
2709         .stop_service        = hns3vf_stop_service,
2710         .prepare_reset       = hns3vf_prepare_reset,
2711         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2712         .reinit_dev          = hns3vf_reinit_dev,
2713         .restore_conf        = hns3vf_restore_conf,
2714         .start_service       = hns3vf_start_service,
2715 };
2716
2717 static int
2718 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2719 {
2720         struct hns3_adapter *hns = eth_dev->data->dev_private;
2721         struct hns3_hw *hw = &hns->hw;
2722         int ret;
2723
2724         PMD_INIT_FUNC_TRACE();
2725
2726         eth_dev->process_private = (struct hns3_process_private *)
2727             rte_zmalloc_socket("hns3_filter_list",
2728                                sizeof(struct hns3_process_private),
2729                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2730         if (eth_dev->process_private == NULL) {
2731                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2732                 return -ENOMEM;
2733         }
2734
2735         /* initialize flow filter lists */
2736         hns3_filterlist_init(eth_dev);
2737
2738         hns3_set_rxtx_function(eth_dev);
2739         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2740         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2741                 ret = hns3_mp_init_secondary();
2742                 if (ret) {
2743                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2744                                           "process, ret = %d", ret);
2745                         goto err_mp_init_secondary;
2746                 }
2747
2748                 hw->secondary_cnt++;
2749                 return 0;
2750         }
2751
2752         ret = hns3_mp_init_primary();
2753         if (ret) {
2754                 PMD_INIT_LOG(ERR,
2755                              "Failed to init for primary process, ret = %d",
2756                              ret);
2757                 goto err_mp_init_primary;
2758         }
2759
2760         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2761         hns->is_vf = true;
2762         hw->data = eth_dev->data;
2763
2764         ret = hns3_reset_init(hw);
2765         if (ret)
2766                 goto err_init_reset;
2767         hw->reset.ops = &hns3vf_reset_ops;
2768
2769         ret = hns3vf_init_vf(eth_dev);
2770         if (ret) {
2771                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2772                 goto err_init_vf;
2773         }
2774
2775         /* Allocate memory for storing MAC addresses */
2776         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2777                                                sizeof(struct rte_ether_addr) *
2778                                                HNS3_VF_UC_MACADDR_NUM, 0);
2779         if (eth_dev->data->mac_addrs == NULL) {
2780                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2781                              "to store MAC addresses",
2782                              sizeof(struct rte_ether_addr) *
2783                              HNS3_VF_UC_MACADDR_NUM);
2784                 ret = -ENOMEM;
2785                 goto err_rte_zmalloc;
2786         }
2787
2788         /*
2789          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2790          * on the host by "ip link set ..." command. To avoid some incorrect
2791          * scenes, for example, hns3 VF PMD driver fails to receive and send
2792          * packets after user configure the MAC address by using the
2793          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2794          * address strategy as the hns3 kernel ethdev driver in the
2795          * initialization. If user configure a MAC address by the ip command
2796          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2797          * start with a random MAC address in the initialization.
2798          */
2799         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2800                 rte_eth_random_addr(hw->mac.mac_addr);
2801         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2802                             &eth_dev->data->mac_addrs[0]);
2803
2804         hw->adapter_state = HNS3_NIC_INITIALIZED;
2805
2806         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2807                 hns3_err(hw, "Reschedule reset service after dev_init");
2808                 hns3_schedule_reset(hns);
2809         } else {
2810                 /* IMP will wait ready flag before reset */
2811                 hns3_notify_reset_ready(hw, false);
2812         }
2813         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2814                           eth_dev);
2815         return 0;
2816
2817 err_rte_zmalloc:
2818         hns3vf_uninit_vf(eth_dev);
2819
2820 err_init_vf:
2821         rte_free(hw->reset.wait_data);
2822
2823 err_init_reset:
2824         hns3_mp_uninit_primary();
2825
2826 err_mp_init_primary:
2827 err_mp_init_secondary:
2828         eth_dev->dev_ops = NULL;
2829         eth_dev->rx_pkt_burst = NULL;
2830         eth_dev->tx_pkt_burst = NULL;
2831         eth_dev->tx_pkt_prepare = NULL;
2832         rte_free(eth_dev->process_private);
2833         eth_dev->process_private = NULL;
2834
2835         return ret;
2836 }
2837
2838 static int
2839 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2840 {
2841         struct hns3_adapter *hns = eth_dev->data->dev_private;
2842         struct hns3_hw *hw = &hns->hw;
2843
2844         PMD_INIT_FUNC_TRACE();
2845
2846         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2847                 return -EPERM;
2848
2849         eth_dev->dev_ops = NULL;
2850         eth_dev->rx_pkt_burst = NULL;
2851         eth_dev->tx_pkt_burst = NULL;
2852         eth_dev->tx_pkt_prepare = NULL;
2853
2854         if (hw->adapter_state < HNS3_NIC_CLOSING)
2855                 hns3vf_dev_close(eth_dev);
2856
2857         hw->adapter_state = HNS3_NIC_REMOVED;
2858         return 0;
2859 }
2860
2861 static int
2862 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2863                      struct rte_pci_device *pci_dev)
2864 {
2865         return rte_eth_dev_pci_generic_probe(pci_dev,
2866                                              sizeof(struct hns3_adapter),
2867                                              hns3vf_dev_init);
2868 }
2869
2870 static int
2871 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2872 {
2873         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2874 }
2875
2876 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2877         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2878         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2879         { .vendor_id = 0, /* sentinel */ },
2880 };
2881
2882 static struct rte_pci_driver rte_hns3vf_pmd = {
2883         .id_table = pci_id_hns3vf_map,
2884         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2885         .probe = eth_hns3vf_pci_probe,
2886         .remove = eth_hns3vf_pci_remove,
2887 };
2888
2889 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2890 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2891 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");