drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 hw->rss_dis_flag = false;
 787                 rss_conf = conf->rx_adv_conf.rss_conf;
 788                 if (rss_conf.rss_key == NULL) {
 789                         rss_conf.rss_key = rss_cfg->key;
 790                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 791                 }
 792
 793                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 794                 if (ret)
 795                         goto cfg_err;
 796         }
 797
 798         /*
 799          * If jumbo frames are enabled, MTU needs to be refreshed
 800          * according to the maximum RX packet length.
 801          */
 802         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 803                 /*
 804                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 805                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 806                  * can safely assign to "uint16_t" type variable.
 807                  */
 808                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 809                 ret = hns3vf_dev_mtu_set(dev, mtu);
 810                 if (ret)
 811                         goto cfg_err;
 812                 dev->data->mtu = mtu;
 813         }
 814
 815         ret = hns3vf_dev_configure_vlan(dev);
 816         if (ret)
 817                 goto cfg_err;
 818
 819         /* config hardware GRO */
 820         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 821         ret = hns3_config_gro(hw, gro_en);
 822         if (ret)
 823                 goto cfg_err;
 824
 825         hns->rx_simple_allowed = true;
 826         hns->rx_vec_allowed = true;
 827         hns->tx_simple_allowed = true;
 828         hns->tx_vec_allowed = true;
 829
 830         hns3_init_rx_ptype_tble(dev);
 831
 832         hw->adapter_state = HNS3_NIC_CONFIGURED;
 833         return 0;
 834
 835 cfg_err:
 836         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 837         hw->adapter_state = HNS3_NIC_INITIALIZED;
 838
 839         return ret;
 840 }
 841
 842 static int
 843 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 844 {
 845         int ret;
 846
 847         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 848                                 sizeof(mtu), true, NULL, 0);
 849         if (ret)
 850                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 851
 852         return ret;
 853 }
 854
 855 static int
 856 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 857 {
 858         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 859         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 860         int ret;
 861
 862         /*
 863          * The hns3 PF/VF devices on the same port share the hardware MTU
 864          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 865          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 866          * driver, there is no need to stop the port for hns3 VF device, and the
 867          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 868          * PF's MTU.
 869          */
 870         if (rte_atomic16_read(&hw->reset.resetting)) {
 871                 hns3_err(hw, "Failed to set mtu during resetting");
 872                 return -EIO;
 873         }
 874
 875         /*
 876          * when Rx of scattered packets is off, we have some possibility of
 877          * using vector Rx process function or simple Rx functions in hns3 PMD
 878          * driver. If the input MTU is increased and the maximum length of
 879          * received packets is greater than the length of a buffer for Rx
 880          * packet, the hardware network engine needs to use multiple BDs and
 881          * buffers to store these packets. This will cause problems when still
 882          * using vector Rx process function or simple Rx function to receiving
 883          * packets. So, when Rx of scattered packets is off and device is
 884          * started, it is not permitted to increase MTU so that the maximum
 885          * length of Rx packets is greater than Rx buffer length.
 886          */
 887         if (dev->data->dev_started && !dev->data->scattered_rx &&
 888             frame_size > hw->rx_buf_len) {
 889                 hns3_err(hw, "failed to set mtu because current is "
 890                         "not scattered rx mode");
 891                 return -EOPNOTSUPP;
 892         }
 893
 894         rte_spinlock_lock(&hw->lock);
 895         ret = hns3vf_config_mtu(hw, mtu);
 896         if (ret) {
 897                 rte_spinlock_unlock(&hw->lock);
 898                 return ret;
 899         }
 900         if (frame_size > RTE_ETHER_MAX_LEN)
 901                 dev->data->dev_conf.rxmode.offloads |=
 902                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 903         else
 904                 dev->data->dev_conf.rxmode.offloads &=
 905                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 906         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 907         rte_spinlock_unlock(&hw->lock);
 908
 909         return 0;
 910 }
 911
 912 static int
 913 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 914 {
 915         struct hns3_adapter *hns = eth_dev->data->dev_private;
 916         struct hns3_hw *hw = &hns->hw;
 917         uint16_t q_num = hw->tqps_num;
 918
 919         /*
 920          * In interrupt mode, 'max_rx_queues' is set based on the number of
 921          * MSI-X interrupt resources of the hardware.
 922          */
 923         if (hw->data->dev_conf.intr_conf.rxq == 1)
 924                 q_num = hw->intr_tqps_num;
 925
 926         info->max_rx_queues = q_num;
 927         info->max_tx_queues = hw->tqps_num;
 928         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 929         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 930         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 931         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 932         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 933
 934         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 935                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 936                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 937                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 938                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 939                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 940                                  DEV_RX_OFFLOAD_SCATTER |
 941                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 942                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 943                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 944                                  DEV_RX_OFFLOAD_RSS_HASH |
 945                                  DEV_RX_OFFLOAD_TCP_LRO);
 946         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 947                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 948                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 949                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 950                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 951                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 952                                  DEV_TX_OFFLOAD_TCP_TSO |
 953                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 954                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 955                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 956                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 957                                  hns3_txvlan_cap_get(hw));
 958
 959         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 960                 .nb_max = HNS3_MAX_RING_DESC,
 961                 .nb_min = HNS3_MIN_RING_DESC,
 962                 .nb_align = HNS3_ALIGN_RING_DESC,
 963         };
 964
 965         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 966                 .nb_max = HNS3_MAX_RING_DESC,
 967                 .nb_min = HNS3_MIN_RING_DESC,
 968                 .nb_align = HNS3_ALIGN_RING_DESC,
 969                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 970                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 971         };
 972
 973         info->default_rxconf = (struct rte_eth_rxconf) {
 974                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 975                 /*
 976                  * If there are no available Rx buffer descriptors, incoming
 977                  * packets are always dropped by hardware based on hns3 network
 978                  * engine.
 979                  */
 980                 .rx_drop_en = 1,
 981                 .offloads = 0,
 982         };
 983         info->default_txconf = (struct rte_eth_txconf) {
 984                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 985                 .offloads = 0,
 986         };
 987
 988         info->vmdq_queue_num = 0;
 989
 990         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 991         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 992         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 993         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 994         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 995
 996         return 0;
 997 }
 998
 999 static void
1000 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1001 {
1002         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1003 }
1004
1005 static void
1006 hns3vf_disable_irq0(struct hns3_hw *hw)
1007 {
1008         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1009 }
1010
1011 static void
1012 hns3vf_enable_irq0(struct hns3_hw *hw)
1013 {
1014         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1015 }
1016
1017 static enum hns3vf_evt_cause
1018 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1019 {
1020         struct hns3_hw *hw = &hns->hw;
1021         enum hns3vf_evt_cause ret;
1022         uint32_t cmdq_stat_reg;
1023         uint32_t rst_ing_reg;
1024         uint32_t val;
1025
1026         /* Fetch the events from their corresponding regs */
1027         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1028
1029         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1030                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1031                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1032                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1033                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1034                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1035                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1036                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1037                 if (clearval) {
1038                         hw->reset.stats.global_cnt++;
1039                         hns3_warn(hw, "Global reset detected, clear reset status");
1040                 } else {
1041                         hns3_schedule_delayed_reset(hns);
1042                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1043                 }
1044
1045                 ret = HNS3VF_VECTOR0_EVENT_RST;
1046                 goto out;
1047         }
1048
1049         /* Check for vector0 mailbox(=CMDQ RX) event source */
1050         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1051                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1052                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1053                 goto out;
1054         }
1055
1056         val = 0;
1057         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1058 out:
1059         if (clearval)
1060                 *clearval = val;
1061         return ret;
1062 }
1063
1064 static void
1065 hns3vf_interrupt_handler(void *param)
1066 {
1067         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1068         struct hns3_adapter *hns = dev->data->dev_private;
1069         struct hns3_hw *hw = &hns->hw;
1070         enum hns3vf_evt_cause event_cause;
1071         uint32_t clearval;
1072
1073         if (hw->irq_thread_id == 0)
1074                 hw->irq_thread_id = pthread_self();
1075
1076         /* Disable interrupt */
1077         hns3vf_disable_irq0(hw);
1078
1079         /* Read out interrupt causes */
1080         event_cause = hns3vf_check_event_cause(hns, &clearval);
1081
1082         switch (event_cause) {
1083         case HNS3VF_VECTOR0_EVENT_RST:
1084                 hns3_schedule_reset(hns);
1085                 break;
1086         case HNS3VF_VECTOR0_EVENT_MBX:
1087                 hns3_dev_handle_mbx_msg(hw);
1088                 break;
1089         default:
1090                 break;
1091         }
1092
1093         /* Clear interrupt causes */
1094         hns3vf_clear_event_cause(hw, clearval);
1095
1096         /* Enable interrupt */
1097         hns3vf_enable_irq0(hw);
1098 }
1099
1100 static void
1101 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1102 {
1103         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1104         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1105         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1106 }
1107
1108 static void
1109 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1110 {
1111         struct hns3_dev_specs_0_cmd *req0;
1112
1113         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1114
1115         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1116         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1117         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1118 }
1119
1120 static int
1121 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1122 {
1123         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1124         int ret;
1125         int i;
1126
1127         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1128                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1129                                           true);
1130                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1131         }
1132         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1133
1134         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1135         if (ret)
1136                 return ret;
1137
1138         hns3vf_parse_dev_specifications(hw, desc);
1139
1140         return 0;
1141 }
1142
1143 static int
1144 hns3vf_get_capability(struct hns3_hw *hw)
1145 {
1146         struct rte_pci_device *pci_dev;
1147         struct rte_eth_dev *eth_dev;
1148         uint8_t revision;
1149         int ret;
1150
1151         eth_dev = &rte_eth_devices[hw->data->port_id];
1152         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1153
1154         /* Get PCI revision id */
1155         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1156                                   HNS3_PCI_REVISION_ID);
1157         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1158                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1159                              ret);
1160                 return -EIO;
1161         }
1162         hw->revision = revision;
1163
1164         if (revision < PCI_REVISION_ID_HIP09_A) {
1165                 hns3vf_set_default_dev_specifications(hw);
1166                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1167                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1168                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1169                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1170                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1171                 return 0;
1172         }
1173
1174         ret = hns3vf_query_dev_specifications(hw);
1175         if (ret) {
1176                 PMD_INIT_LOG(ERR,
1177                              "failed to query dev specifications, ret = %d",
1178                              ret);
1179                 return ret;
1180         }
1181
1182         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1183         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1184         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1185         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1186         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1187
1188         return 0;
1189 }
1190
1191 static int
1192 hns3vf_check_tqp_info(struct hns3_hw *hw)
1193 {
1194         uint16_t tqps_num;
1195
1196         tqps_num = hw->tqps_num;
1197         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1198                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1199                                   "range: 1~%d",
1200                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1201                 return -EINVAL;
1202         }
1203
1204         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1205
1206         return 0;
1207 }
1208 static int
1209 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1210 {
1211         uint8_t resp_msg;
1212         int ret;
1213
1214         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1215                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1216                                 true, &resp_msg, sizeof(resp_msg));
1217         if (ret) {
1218                 if (ret == -ETIME) {
1219                         /*
1220                          * Getting current port based VLAN state from PF driver
1221                          * will not affect VF driver's basic function. Because
1222                          * the VF driver relies on hns3 PF kernel ether driver,
1223                          * to avoid introducing compatibility issues with older
1224                          * version of PF driver, no failure will be returned
1225                          * when the return value is ETIME. This return value has
1226                          * the following scenarios:
1227                          * 1) Firmware didn't return the results in time
1228                          * 2) the result return by firmware is timeout
1229                          * 3) the older version of kernel side PF driver does
1230                          *    not support this mailbox message.
1231                          * For scenarios 1 and 2, it is most likely that a
1232                          * hardware error has occurred, or a hardware reset has
1233                          * occurred. In this case, these errors will be caught
1234                          * by other functions.
1235                          */
1236                         PMD_INIT_LOG(WARNING,
1237                                 "failed to get PVID state for timeout, maybe "
1238                                 "kernel side PF driver doesn't support this "
1239                                 "mailbox message, or firmware didn't respond.");
1240                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1241                 } else {
1242                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1243                                 " ret = %d", ret);
1244                         return ret;
1245                 }
1246         }
1247         hw->port_base_vlan_cfg.state = resp_msg ?
1248                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1249         return 0;
1250 }
1251
1252 static int
1253 hns3vf_get_queue_info(struct hns3_hw *hw)
1254 {
1255 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1256         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1257         int ret;
1258
1259         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1260                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1261         if (ret) {
1262                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1263                 return ret;
1264         }
1265
1266         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1267         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1268
1269         return hns3vf_check_tqp_info(hw);
1270 }
1271
1272 static int
1273 hns3vf_get_queue_depth(struct hns3_hw *hw)
1274 {
1275 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1276         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1277         int ret;
1278
1279         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1280                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1281         if (ret) {
1282                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1283                              ret);
1284                 return ret;
1285         }
1286
1287         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1288         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1289
1290         return 0;
1291 }
1292
1293 static int
1294 hns3vf_get_tc_info(struct hns3_hw *hw)
1295 {
1296         uint8_t resp_msg;
1297         int ret;
1298
1299         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1300                                 true, &resp_msg, sizeof(resp_msg));
1301         if (ret) {
1302                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1303                          ret);
1304                 return ret;
1305         }
1306
1307         hw->hw_tc_map = resp_msg;
1308
1309         return 0;
1310 }
1311
1312 static int
1313 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1314 {
1315         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1316         int ret;
1317
1318         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1319                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1320         if (ret) {
1321                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1322                 return ret;
1323         }
1324
1325         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1326
1327         return 0;
1328 }
1329
1330 static int
1331 hns3vf_get_configuration(struct hns3_hw *hw)
1332 {
1333         int ret;
1334
1335         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1336         hw->rss_dis_flag = false;
1337
1338         /* Get device capability */
1339         ret = hns3vf_get_capability(hw);
1340         if (ret) {
1341                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1342                 return ret;
1343         }
1344
1345         /* Get queue configuration from PF */
1346         ret = hns3vf_get_queue_info(hw);
1347         if (ret)
1348                 return ret;
1349
1350         /* Get queue depth info from PF */
1351         ret = hns3vf_get_queue_depth(hw);
1352         if (ret)
1353                 return ret;
1354
1355         /* Get user defined VF MAC addr from PF */
1356         ret = hns3vf_get_host_mac_addr(hw);
1357         if (ret)
1358                 return ret;
1359
1360         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1361         if (ret)
1362                 return ret;
1363
1364         /* Get tc configuration from PF */
1365         return hns3vf_get_tc_info(hw);
1366 }
1367
1368 static int
1369 hns3vf_set_tc_info(struct hns3_adapter *hns)
1370 {
1371         struct hns3_hw *hw = &hns->hw;
1372         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1373         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1374         uint8_t i;
1375
1376         hw->num_tc = 0;
1377         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1378                 if (hw->hw_tc_map & BIT(i))
1379                         hw->num_tc++;
1380
1381         if (nb_rx_q < hw->num_tc) {
1382                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1383                          nb_rx_q, hw->num_tc);
1384                 return -EINVAL;
1385         }
1386
1387         if (nb_tx_q < hw->num_tc) {
1388                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1389                          nb_tx_q, hw->num_tc);
1390                 return -EINVAL;
1391         }
1392
1393         hns3_set_rss_size(hw, nb_rx_q);
1394         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1395
1396         return 0;
1397 }
1398
1399 static void
1400 hns3vf_request_link_info(struct hns3_hw *hw)
1401 {
1402         uint8_t resp_msg;
1403         int ret;
1404
1405         if (rte_atomic16_read(&hw->reset.resetting))
1406                 return;
1407         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1408                                 &resp_msg, sizeof(resp_msg));
1409         if (ret)
1410                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1411 }
1412
1413 static int
1414 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1415 {
1416 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1417         struct hns3_hw *hw = &hns->hw;
1418         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1419         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1420         uint8_t is_kill = on ? 0 : 1;
1421
1422         msg_data[0] = is_kill;
1423         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1424         memcpy(&msg_data[3], &proto, sizeof(proto));
1425
1426         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1427                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1428                                  0);
1429 }
1430
1431 static int
1432 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1433 {
1434         struct hns3_adapter *hns = dev->data->dev_private;
1435         struct hns3_hw *hw = &hns->hw;
1436         int ret;
1437
1438         if (rte_atomic16_read(&hw->reset.resetting)) {
1439                 hns3_err(hw,
1440                          "vf set vlan id failed during resetting, vlan_id =%u",
1441                          vlan_id);
1442                 return -EIO;
1443         }
1444         rte_spinlock_lock(&hw->lock);
1445         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1446         rte_spinlock_unlock(&hw->lock);
1447         if (ret)
1448                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1449                          vlan_id, ret);
1450
1451         return ret;
1452 }
1453
1454 static int
1455 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1456 {
1457         uint8_t msg_data;
1458         int ret;
1459
1460         msg_data = enable ? 1 : 0;
1461         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1462                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1463         if (ret)
1464                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1465
1466         return ret;
1467 }
1468
1469 static int
1470 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1471 {
1472         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1473         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1474         unsigned int tmp_mask;
1475         int ret = 0;
1476
1477         if (rte_atomic16_read(&hw->reset.resetting)) {
1478                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1479                              "mask = 0x%x", mask);
1480                 return -EIO;
1481         }
1482
1483         tmp_mask = (unsigned int)mask;
1484         /* Vlan stripping setting */
1485         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1486                 rte_spinlock_lock(&hw->lock);
1487                 /* Enable or disable VLAN stripping */
1488                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1489                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1490                 else
1491                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1492                 rte_spinlock_unlock(&hw->lock);
1493         }
1494
1495         return ret;
1496 }
1497
1498 static int
1499 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1500 {
1501         struct rte_vlan_filter_conf *vfc;
1502         struct hns3_hw *hw = &hns->hw;
1503         uint16_t vlan_id;
1504         uint64_t vbit;
1505         uint64_t ids;
1506         int ret = 0;
1507         uint32_t i;
1508
1509         vfc = &hw->data->vlan_filter_conf;
1510         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1511                 if (vfc->ids[i] == 0)
1512                         continue;
1513                 ids = vfc->ids[i];
1514                 while (ids) {
1515                         /*
1516                          * 64 means the num bits of ids, one bit corresponds to
1517                          * one vlan id
1518                          */
1519                         vlan_id = 64 * i;
1520                         /* count trailing zeroes */
1521                         vbit = ~ids & (ids - 1);
1522                         /* clear least significant bit set */
1523                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1524                         for (; vbit;) {
1525                                 vbit >>= 1;
1526                                 vlan_id++;
1527                         }
1528                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1529                         if (ret) {
1530                                 hns3_err(hw,
1531                                          "VF handle vlan table failed, ret =%d, on = %d",
1532                                          ret, on);
1533                                 return ret;
1534                         }
1535                 }
1536         }
1537
1538         return ret;
1539 }
1540
1541 static int
1542 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1543 {
1544         return hns3vf_handle_all_vlan_table(hns, 0);
1545 }
1546
1547 static int
1548 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1549 {
1550         struct hns3_hw *hw = &hns->hw;
1551         struct rte_eth_conf *dev_conf;
1552         bool en;
1553         int ret;
1554
1555         dev_conf = &hw->data->dev_conf;
1556         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1557                                                                    : false;
1558         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1559         if (ret)
1560                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1561                          ret);
1562         return ret;
1563 }
1564
1565 static int
1566 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1567 {
1568         struct hns3_adapter *hns = dev->data->dev_private;
1569         struct rte_eth_dev_data *data = dev->data;
1570         struct hns3_hw *hw = &hns->hw;
1571         int ret;
1572
1573         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1574             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1575             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1576                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1577                               "or hw_vlan_insert_pvid is not support!");
1578         }
1579
1580         /* Apply vlan offload setting */
1581         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1582         if (ret)
1583                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1584
1585         return ret;
1586 }
1587
1588 static int
1589 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1590 {
1591         uint8_t msg_data;
1592
1593         msg_data = alive ? 1 : 0;
1594         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1595                                  sizeof(msg_data), false, NULL, 0);
1596 }
1597
1598 static void
1599 hns3vf_keep_alive_handler(void *param)
1600 {
1601         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1602         struct hns3_adapter *hns = eth_dev->data->dev_private;
1603         struct hns3_hw *hw = &hns->hw;
1604         uint8_t respmsg;
1605         int ret;
1606
1607         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1608                                 false, &respmsg, sizeof(uint8_t));
1609         if (ret)
1610                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1611                          ret);
1612
1613         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1614                           eth_dev);
1615 }
1616
1617 static void
1618 hns3vf_service_handler(void *param)
1619 {
1620         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1621         struct hns3_adapter *hns = eth_dev->data->dev_private;
1622         struct hns3_hw *hw = &hns->hw;
1623
1624         /*
1625          * The query link status and reset processing are executed in the
1626          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1627          * and the query operation will time out after 30ms. In the case of
1628          * multiple PF/VFs, each query failure timeout causes the IMP reset
1629          * interrupt to fail to respond within 100ms.
1630          * Before querying the link status, check whether there is a reset
1631          * pending, and if so, abandon the query.
1632          */
1633         if (!hns3vf_is_reset_pending(hns))
1634                 hns3vf_request_link_info(hw);
1635         else
1636                 hns3_warn(hw, "Cancel the query when reset is pending");
1637
1638         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1639                           eth_dev);
1640 }
1641
1642 static int
1643 hns3_query_vf_resource(struct hns3_hw *hw)
1644 {
1645         struct hns3_vf_res_cmd *req;
1646         struct hns3_cmd_desc desc;
1647         uint16_t num_msi;
1648         int ret;
1649
1650         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1651         ret = hns3_cmd_send(hw, &desc, 1);
1652         if (ret) {
1653                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1654                 return ret;
1655         }
1656
1657         req = (struct hns3_vf_res_cmd *)desc.data;
1658         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1659                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1660         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1661                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1662                          num_msi, HNS3_MIN_VECTOR_NUM);
1663                 return -EINVAL;
1664         }
1665
1666         hw->num_msi = num_msi;
1667
1668         return 0;
1669 }
1670
1671 static int
1672 hns3vf_init_hardware(struct hns3_adapter *hns)
1673 {
1674         struct hns3_hw *hw = &hns->hw;
1675         uint16_t mtu = hw->data->mtu;
1676         int ret;
1677
1678         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1679         if (ret)
1680                 return ret;
1681
1682         ret = hns3vf_config_mtu(hw, mtu);
1683         if (ret)
1684                 goto err_init_hardware;
1685
1686         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1687         if (ret) {
1688                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1689                 goto err_init_hardware;
1690         }
1691
1692         ret = hns3_config_gro(hw, false);
1693         if (ret) {
1694                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1695                 goto err_init_hardware;
1696         }
1697
1698         /*
1699          * In the initialization clearing the all hardware mapping relationship
1700          * configurations between queues and interrupt vectors is needed, so
1701          * some error caused by the residual configurations, such as the
1702          * unexpected interrupt, can be avoid.
1703          */
1704         ret = hns3vf_init_ring_with_vector(hw);
1705         if (ret) {
1706                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1707                 goto err_init_hardware;
1708         }
1709
1710         ret = hns3vf_set_alive(hw, true);
1711         if (ret) {
1712                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1713                 goto err_init_hardware;
1714         }
1715
1716         hns3vf_request_link_info(hw);
1717         return 0;
1718
1719 err_init_hardware:
1720         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1721         return ret;
1722 }
1723
1724 static int
1725 hns3vf_clear_vport_list(struct hns3_hw *hw)
1726 {
1727         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1728                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1729                                  NULL, 0);
1730 }
1731
1732 static int
1733 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1734 {
1735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1736         struct hns3_adapter *hns = eth_dev->data->dev_private;
1737         struct hns3_hw *hw = &hns->hw;
1738         int ret;
1739
1740         PMD_INIT_FUNC_TRACE();
1741
1742         /* Get hardware io base address from pcie BAR2 IO space */
1743         hw->io_base = pci_dev->mem_resource[2].addr;
1744
1745         /* Firmware command queue initialize */
1746         ret = hns3_cmd_init_queue(hw);
1747         if (ret) {
1748                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1749                 goto err_cmd_init_queue;
1750         }
1751
1752         /* Firmware command initialize */
1753         ret = hns3_cmd_init(hw);
1754         if (ret) {
1755                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1756                 goto err_cmd_init;
1757         }
1758
1759         /* Get VF resource */
1760         ret = hns3_query_vf_resource(hw);
1761         if (ret)
1762                 goto err_cmd_init;
1763
1764         rte_spinlock_init(&hw->mbx_resp.lock);
1765
1766         hns3vf_clear_event_cause(hw, 0);
1767
1768         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1769                                          hns3vf_interrupt_handler, eth_dev);
1770         if (ret) {
1771                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1772                 goto err_intr_callback_register;
1773         }
1774
1775         /* Enable interrupt */
1776         rte_intr_enable(&pci_dev->intr_handle);
1777         hns3vf_enable_irq0(hw);
1778
1779         /* Get configuration from PF */
1780         ret = hns3vf_get_configuration(hw);
1781         if (ret) {
1782                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1783                 goto err_get_config;
1784         }
1785
1786         ret = hns3vf_clear_vport_list(hw);
1787         if (ret) {
1788                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1789                 goto err_get_config;
1790         }
1791
1792         ret = hns3vf_init_hardware(hns);
1793         if (ret)
1794                 goto err_get_config;
1795
1796         hns3_set_default_rss_args(hw);
1797
1798         return 0;
1799
1800 err_get_config:
1801         hns3vf_disable_irq0(hw);
1802         rte_intr_disable(&pci_dev->intr_handle);
1803         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1804                              eth_dev);
1805 err_intr_callback_register:
1806 err_cmd_init:
1807         hns3_cmd_uninit(hw);
1808         hns3_cmd_destroy_queue(hw);
1809 err_cmd_init_queue:
1810         hw->io_base = NULL;
1811
1812         return ret;
1813 }
1814
1815 static void
1816 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1817 {
1818         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1819         struct hns3_adapter *hns = eth_dev->data->dev_private;
1820         struct hns3_hw *hw = &hns->hw;
1821
1822         PMD_INIT_FUNC_TRACE();
1823
1824         hns3_rss_uninit(hns);
1825         (void)hns3_config_gro(hw, false);
1826         (void)hns3vf_set_alive(hw, false);
1827         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1828         hns3vf_disable_irq0(hw);
1829         rte_intr_disable(&pci_dev->intr_handle);
1830         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1831                              eth_dev);
1832         hns3_cmd_uninit(hw);
1833         hns3_cmd_destroy_queue(hw);
1834         hw->io_base = NULL;
1835 }
1836
1837 static int
1838 hns3vf_do_stop(struct hns3_adapter *hns)
1839 {
1840         struct hns3_hw *hw = &hns->hw;
1841         bool reset_queue;
1842
1843         hw->mac.link_status = ETH_LINK_DOWN;
1844
1845         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1846                 hns3vf_configure_mac_addr(hns, true);
1847                 reset_queue = true;
1848         } else
1849                 reset_queue = false;
1850         return hns3_stop_queues(hns, reset_queue);
1851 }
1852
1853 static void
1854 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1855 {
1856         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1859         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1860         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1861         uint16_t q_id;
1862
1863         if (dev->data->dev_conf.intr_conf.rxq == 0)
1864                 return;
1865
1866         /* unmap the ring with vector */
1867         if (rte_intr_allow_others(intr_handle)) {
1868                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1869                 base = RTE_INTR_VEC_RXTX_OFFSET;
1870         }
1871         if (rte_intr_dp_is_en(intr_handle)) {
1872                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1873                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1874                                                            HNS3_RING_TYPE_RX,
1875                                                            q_id);
1876                         if (vec < base + intr_handle->nb_efd - 1)
1877                                 vec++;
1878                 }
1879         }
1880         /* Clean datapath event and queue/vec mapping */
1881         rte_intr_efd_disable(intr_handle);
1882         if (intr_handle->intr_vec) {
1883                 rte_free(intr_handle->intr_vec);
1884                 intr_handle->intr_vec = NULL;
1885         }
1886 }
1887
1888 static void
1889 hns3vf_dev_stop(struct rte_eth_dev *dev)
1890 {
1891         struct hns3_adapter *hns = dev->data->dev_private;
1892         struct hns3_hw *hw = &hns->hw;
1893
1894         PMD_INIT_FUNC_TRACE();
1895
1896         hw->adapter_state = HNS3_NIC_STOPPING;
1897         hns3_set_rxtx_function(dev);
1898         rte_wmb();
1899         /* Disable datapath on secondary process. */
1900         hns3_mp_req_stop_rxtx(dev);
1901         /* Prevent crashes when queues are still in use. */
1902         rte_delay_ms(hw->tqps_num);
1903
1904         rte_spinlock_lock(&hw->lock);
1905         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1906                 hns3vf_do_stop(hns);
1907                 hns3vf_unmap_rx_interrupt(dev);
1908                 hns3_dev_release_mbufs(hns);
1909                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1910         }
1911         hns3_rx_scattered_reset(dev);
1912         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1913         rte_spinlock_unlock(&hw->lock);
1914 }
1915
1916 static int
1917 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1918 {
1919         struct hns3_adapter *hns = eth_dev->data->dev_private;
1920         struct hns3_hw *hw = &hns->hw;
1921
1922         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1923                 return 0;
1924
1925         if (hw->adapter_state == HNS3_NIC_STARTED)
1926                 hns3vf_dev_stop(eth_dev);
1927
1928         hw->adapter_state = HNS3_NIC_CLOSING;
1929         hns3_reset_abort(hns);
1930         hw->adapter_state = HNS3_NIC_CLOSED;
1931         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1932         hns3vf_configure_all_mc_mac_addr(hns, true);
1933         hns3vf_remove_all_vlan_table(hns);
1934         hns3vf_uninit_vf(eth_dev);
1935         hns3_free_all_queues(eth_dev);
1936         rte_free(hw->reset.wait_data);
1937         rte_free(eth_dev->process_private);
1938         eth_dev->process_private = NULL;
1939         hns3_mp_uninit_primary();
1940         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1941
1942         return 0;
1943 }
1944
1945 static int
1946 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1947                       size_t fw_size)
1948 {
1949         struct hns3_adapter *hns = eth_dev->data->dev_private;
1950         struct hns3_hw *hw = &hns->hw;
1951         uint32_t version = hw->fw_version;
1952         int ret;
1953
1954         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1955                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1956                                       HNS3_FW_VERSION_BYTE3_S),
1957                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1958                                       HNS3_FW_VERSION_BYTE2_S),
1959                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1960                                       HNS3_FW_VERSION_BYTE1_S),
1961                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1962                                       HNS3_FW_VERSION_BYTE0_S));
1963         ret += 1; /* add the size of '\0' */
1964         if (fw_size < (uint32_t)ret)
1965                 return ret;
1966         else
1967                 return 0;
1968 }
1969
1970 static int
1971 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1972                        __rte_unused int wait_to_complete)
1973 {
1974         struct hns3_adapter *hns = eth_dev->data->dev_private;
1975         struct hns3_hw *hw = &hns->hw;
1976         struct hns3_mac *mac = &hw->mac;
1977         struct rte_eth_link new_link;
1978
1979         memset(&new_link, 0, sizeof(new_link));
1980         switch (mac->link_speed) {
1981         case ETH_SPEED_NUM_10M:
1982         case ETH_SPEED_NUM_100M:
1983         case ETH_SPEED_NUM_1G:
1984         case ETH_SPEED_NUM_10G:
1985         case ETH_SPEED_NUM_25G:
1986         case ETH_SPEED_NUM_40G:
1987         case ETH_SPEED_NUM_50G:
1988         case ETH_SPEED_NUM_100G:
1989         case ETH_SPEED_NUM_200G:
1990                 new_link.link_speed = mac->link_speed;
1991                 break;
1992         default:
1993                 new_link.link_speed = ETH_SPEED_NUM_100M;
1994                 break;
1995         }
1996
1997         new_link.link_duplex = mac->link_duplex;
1998         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1999         new_link.link_autoneg =
2000             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2001
2002         return rte_eth_linkstatus_set(eth_dev, &new_link);
2003 }
2004
2005 static int
2006 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2007 {
2008         struct hns3_hw *hw = &hns->hw;
2009         int ret;
2010
2011         ret = hns3vf_set_tc_info(hns);
2012         if (ret)
2013                 return ret;
2014
2015         ret = hns3_start_queues(hns, reset_queue);
2016         if (ret)
2017                 hns3_err(hw, "Failed to start queues: %d", ret);
2018
2019         return ret;
2020 }
2021
2022 static int
2023 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2024 {
2025         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2026         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2027         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2029         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2030         uint32_t intr_vector;
2031         uint16_t q_id;
2032         int ret;
2033
2034         if (dev->data->dev_conf.intr_conf.rxq == 0)
2035                 return 0;
2036
2037         /* disable uio/vfio intr/eventfd mapping */
2038         rte_intr_disable(intr_handle);
2039
2040         /* check and configure queue intr-vector mapping */
2041         if (rte_intr_cap_multiple(intr_handle) ||
2042             !RTE_ETH_DEV_SRIOV(dev).active) {
2043                 intr_vector = hw->used_rx_queues;
2044                 /* It creates event fd for each intr vector when MSIX is used */
2045                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2046                         return -EINVAL;
2047         }
2048         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2049                 intr_handle->intr_vec =
2050                         rte_zmalloc("intr_vec",
2051                                     hw->used_rx_queues * sizeof(int), 0);
2052                 if (intr_handle->intr_vec == NULL) {
2053                         hns3_err(hw, "Failed to allocate %d rx_queues"
2054                                      " intr_vec", hw->used_rx_queues);
2055                         ret = -ENOMEM;
2056                         goto vf_alloc_intr_vec_error;
2057                 }
2058         }
2059
2060         if (rte_intr_allow_others(intr_handle)) {
2061                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2062                 base = RTE_INTR_VEC_RXTX_OFFSET;
2063         }
2064         if (rte_intr_dp_is_en(intr_handle)) {
2065                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2066                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2067                                                            HNS3_RING_TYPE_RX,
2068                                                            q_id);
2069                         if (ret)
2070                                 goto vf_bind_vector_error;
2071                         intr_handle->intr_vec[q_id] = vec;
2072                         if (vec < base + intr_handle->nb_efd - 1)
2073                                 vec++;
2074                 }
2075         }
2076         rte_intr_enable(intr_handle);
2077         return 0;
2078
2079 vf_bind_vector_error:
2080         rte_intr_efd_disable(intr_handle);
2081         if (intr_handle->intr_vec) {
2082                 free(intr_handle->intr_vec);
2083                 intr_handle->intr_vec = NULL;
2084         }
2085         return ret;
2086 vf_alloc_intr_vec_error:
2087         rte_intr_efd_disable(intr_handle);
2088         return ret;
2089 }
2090
2091 static int
2092 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2093 {
2094         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2095         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2096         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2097         uint16_t q_id;
2098         int ret;
2099
2100         if (dev->data->dev_conf.intr_conf.rxq == 0)
2101                 return 0;
2102
2103         if (rte_intr_dp_is_en(intr_handle)) {
2104                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2105                         ret = hns3vf_bind_ring_with_vector(hw,
2106                                         intr_handle->intr_vec[q_id], true,
2107                                         HNS3_RING_TYPE_RX, q_id);
2108                         if (ret)
2109                                 return ret;
2110                 }
2111         }
2112
2113         return 0;
2114 }
2115
2116 static void
2117 hns3vf_restore_filter(struct rte_eth_dev *dev)
2118 {
2119         hns3_restore_rss_filter(dev);
2120 }
2121
2122 static int
2123 hns3vf_dev_start(struct rte_eth_dev *dev)
2124 {
2125         struct hns3_adapter *hns = dev->data->dev_private;
2126         struct hns3_hw *hw = &hns->hw;
2127         int ret;
2128
2129         PMD_INIT_FUNC_TRACE();
2130         if (rte_atomic16_read(&hw->reset.resetting))
2131                 return -EBUSY;
2132
2133         rte_spinlock_lock(&hw->lock);
2134         hw->adapter_state = HNS3_NIC_STARTING;
2135         ret = hns3vf_do_start(hns, true);
2136         if (ret) {
2137                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2138                 rte_spinlock_unlock(&hw->lock);
2139                 return ret;
2140         }
2141         ret = hns3vf_map_rx_interrupt(dev);
2142         if (ret) {
2143                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2144                 rte_spinlock_unlock(&hw->lock);
2145                 return ret;
2146         }
2147         hw->adapter_state = HNS3_NIC_STARTED;
2148         rte_spinlock_unlock(&hw->lock);
2149
2150         hns3_rx_scattered_calc(dev);
2151         hns3_set_rxtx_function(dev);
2152         hns3_mp_req_start_rxtx(dev);
2153         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2154
2155         hns3vf_restore_filter(dev);
2156
2157         /* Enable interrupt of all rx queues before enabling queues */
2158         hns3_dev_all_rx_queue_intr_enable(hw, true);
2159         /*
2160          * When finished the initialization, enable queues to receive/transmit
2161          * packets.
2162          */
2163         hns3_enable_all_queues(hw, true);
2164
2165         return ret;
2166 }
2167
2168 static bool
2169 is_vf_reset_done(struct hns3_hw *hw)
2170 {
2171 #define HNS3_FUN_RST_ING_BITS \
2172         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2173          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2174          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2175          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2176
2177         uint32_t val;
2178
2179         if (hw->reset.level == HNS3_VF_RESET) {
2180                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2181                 if (val & HNS3_VF_RST_ING_BIT)
2182                         return false;
2183         } else {
2184                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2185                 if (val & HNS3_FUN_RST_ING_BITS)
2186                         return false;
2187         }
2188         return true;
2189 }
2190
2191 bool
2192 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2193 {
2194         struct hns3_hw *hw = &hns->hw;
2195         enum hns3_reset_level reset;
2196
2197         /*
2198          * According to the protocol of PCIe, FLR to a PF device resets the PF
2199          * state as well as the SR-IOV extended capability including VF Enable
2200          * which means that VFs no longer exist.
2201          *
2202          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2203          * is in FLR stage, the register state of VF device is not reliable,
2204          * so register states detection can not be carried out. In this case,
2205          * we just ignore the register states and return false to indicate that
2206          * there are no other reset states that need to be processed by driver.
2207          */
2208         if (hw->reset.level == HNS3_VF_FULL_RESET)
2209                 return false;
2210
2211         /* Check the registers to confirm whether there is reset pending */
2212         hns3vf_check_event_cause(hns, NULL);
2213         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2214         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2215                 hns3_warn(hw, "High level reset %d is pending", reset);
2216                 return true;
2217         }
2218         return false;
2219 }
2220
2221 static int
2222 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2223 {
2224         struct hns3_hw *hw = &hns->hw;
2225         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2226         struct timeval tv;
2227
2228         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2229                 /*
2230                  * After vf reset is ready, the PF may not have completed
2231                  * the reset processing. The vf sending mbox to PF may fail
2232                  * during the pf reset, so it is better to add extra delay.
2233                  */
2234                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2235                     hw->reset.level == HNS3_FLR_RESET)
2236                         return 0;
2237                 /* Reset retry process, no need to add extra delay. */
2238                 if (hw->reset.attempts)
2239                         return 0;
2240                 if (wait_data->check_completion == NULL)
2241                         return 0;
2242
2243                 wait_data->check_completion = NULL;
2244                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2245                 wait_data->count = 1;
2246                 wait_data->result = HNS3_WAIT_REQUEST;
2247                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2248                                   wait_data);
2249                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2250                 return -EAGAIN;
2251         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2252                 gettimeofday(&tv, NULL);
2253                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2254                           tv.tv_sec, tv.tv_usec);
2255                 return -ETIME;
2256         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2257                 return -EAGAIN;
2258
2259         wait_data->hns = hns;
2260         wait_data->check_completion = is_vf_reset_done;
2261         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2262                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2263         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2264         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2265         wait_data->result = HNS3_WAIT_REQUEST;
2266         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2267         return -EAGAIN;
2268 }
2269
2270 static int
2271 hns3vf_prepare_reset(struct hns3_adapter *hns)
2272 {
2273         struct hns3_hw *hw = &hns->hw;
2274         int ret = 0;
2275
2276         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2277                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2278                                         0, true, NULL, 0);
2279         }
2280         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2281
2282         return ret;
2283 }
2284
2285 static int
2286 hns3vf_stop_service(struct hns3_adapter *hns)
2287 {
2288         struct hns3_hw *hw = &hns->hw;
2289         struct rte_eth_dev *eth_dev;
2290
2291         eth_dev = &rte_eth_devices[hw->data->port_id];
2292         if (hw->adapter_state == HNS3_NIC_STARTED)
2293                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2294         hw->mac.link_status = ETH_LINK_DOWN;
2295
2296         hns3_set_rxtx_function(eth_dev);
2297         rte_wmb();
2298         /* Disable datapath on secondary process. */
2299         hns3_mp_req_stop_rxtx(eth_dev);
2300         rte_delay_ms(hw->tqps_num);
2301
2302         rte_spinlock_lock(&hw->lock);
2303         if (hw->adapter_state == HNS3_NIC_STARTED ||
2304             hw->adapter_state == HNS3_NIC_STOPPING) {
2305                 hns3vf_do_stop(hns);
2306                 hw->reset.mbuf_deferred_free = true;
2307         } else
2308                 hw->reset.mbuf_deferred_free = false;
2309
2310         /*
2311          * It is cumbersome for hardware to pick-and-choose entries for deletion
2312          * from table space. Hence, for function reset software intervention is
2313          * required to delete the entries.
2314          */
2315         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2316                 hns3vf_configure_all_mc_mac_addr(hns, true);
2317         rte_spinlock_unlock(&hw->lock);
2318
2319         return 0;
2320 }
2321
2322 static int
2323 hns3vf_start_service(struct hns3_adapter *hns)
2324 {
2325         struct hns3_hw *hw = &hns->hw;
2326         struct rte_eth_dev *eth_dev;
2327
2328         eth_dev = &rte_eth_devices[hw->data->port_id];
2329         hns3_set_rxtx_function(eth_dev);
2330         hns3_mp_req_start_rxtx(eth_dev);
2331         if (hw->adapter_state == HNS3_NIC_STARTED) {
2332                 hns3vf_service_handler(eth_dev);
2333
2334                 /* Enable interrupt of all rx queues before enabling queues */
2335                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2336                 /*
2337                  * When finished the initialization, enable queues to receive
2338                  * and transmit packets.
2339                  */
2340                 hns3_enable_all_queues(hw, true);
2341         }
2342
2343         return 0;
2344 }
2345
2346 static int
2347 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2348 {
2349         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2350         struct rte_ether_addr *hw_mac;
2351         int ret;
2352
2353         /*
2354          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2355          * on the host by "ip link set ..." command. If the hns3 PF kernel
2356          * ethdev driver sets the MAC address for VF device after the
2357          * initialization of the related VF device, the PF driver will notify
2358          * VF driver to reset VF device to make the new MAC address effective
2359          * immediately. The hns3 VF PMD driver should check whether the MAC
2360          * address has been changed by the PF kernel ethdev driver, if changed
2361          * VF driver should configure hardware using the new MAC address in the
2362          * recovering hardware configuration stage of the reset process.
2363          */
2364         ret = hns3vf_get_host_mac_addr(hw);
2365         if (ret)
2366                 return ret;
2367
2368         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2369         ret = rte_is_zero_ether_addr(hw_mac);
2370         if (ret) {
2371                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2372         } else {
2373                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2374                 if (!ret) {
2375                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2376                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2377                                               &hw->data->mac_addrs[0]);
2378                         hns3_warn(hw, "Default MAC address has been changed to:"
2379                                   " %s by the host PF kernel ethdev driver",
2380                                   mac_str);
2381                 }
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int
2388 hns3vf_restore_conf(struct hns3_adapter *hns)
2389 {
2390         struct hns3_hw *hw = &hns->hw;
2391         int ret;
2392
2393         ret = hns3vf_check_default_mac_change(hw);
2394         if (ret)
2395                 return ret;
2396
2397         ret = hns3vf_configure_mac_addr(hns, false);
2398         if (ret)
2399                 return ret;
2400
2401         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2402         if (ret)
2403                 goto err_mc_mac;
2404
2405         ret = hns3vf_restore_promisc(hns);
2406         if (ret)
2407                 goto err_vlan_table;
2408
2409         ret = hns3vf_restore_vlan_conf(hns);
2410         if (ret)
2411                 goto err_vlan_table;
2412
2413         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2414         if (ret)
2415                 goto err_vlan_table;
2416
2417         ret = hns3vf_restore_rx_interrupt(hw);
2418         if (ret)
2419                 goto err_vlan_table;
2420
2421         ret = hns3_restore_gro_conf(hw);
2422         if (ret)
2423                 goto err_vlan_table;
2424
2425         if (hw->adapter_state == HNS3_NIC_STARTED) {
2426                 ret = hns3vf_do_start(hns, false);
2427                 if (ret)
2428                         goto err_vlan_table;
2429                 hns3_info(hw, "hns3vf dev restart successful!");
2430         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2431                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2432         return 0;
2433
2434 err_vlan_table:
2435         hns3vf_configure_all_mc_mac_addr(hns, true);
2436 err_mc_mac:
2437         hns3vf_configure_mac_addr(hns, true);
2438         return ret;
2439 }
2440
2441 static enum hns3_reset_level
2442 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2443 {
2444         enum hns3_reset_level reset_level;
2445
2446         /* return the highest priority reset level amongst all */
2447         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2448                 reset_level = HNS3_VF_RESET;
2449         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2450                 reset_level = HNS3_VF_FULL_RESET;
2451         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2452                 reset_level = HNS3_VF_PF_FUNC_RESET;
2453         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2454                 reset_level = HNS3_VF_FUNC_RESET;
2455         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2456                 reset_level = HNS3_FLR_RESET;
2457         else
2458                 reset_level = HNS3_NONE_RESET;
2459
2460         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2461                 return HNS3_NONE_RESET;
2462
2463         return reset_level;
2464 }
2465
2466 static void
2467 hns3vf_reset_service(void *param)
2468 {
2469         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2470         struct hns3_hw *hw = &hns->hw;
2471         enum hns3_reset_level reset_level;
2472         struct timeval tv_delta;
2473         struct timeval tv_start;
2474         struct timeval tv;
2475         uint64_t msec;
2476
2477         /*
2478          * The interrupt is not triggered within the delay time.
2479          * The interrupt may have been lost. It is necessary to handle
2480          * the interrupt to recover from the error.
2481          */
2482         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2483                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2484                 hns3_err(hw, "Handling interrupts in delayed tasks");
2485                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2486                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2487                 if (reset_level == HNS3_NONE_RESET) {
2488                         hns3_err(hw, "No reset level is set, try global reset");
2489                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2490                 }
2491         }
2492         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2493
2494         /*
2495          * Hardware reset has been notified, we now have to poll & check if
2496          * hardware has actually completed the reset sequence.
2497          */
2498         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2499         if (reset_level != HNS3_NONE_RESET) {
2500                 gettimeofday(&tv_start, NULL);
2501                 hns3_reset_process(hns, reset_level);
2502                 gettimeofday(&tv, NULL);
2503                 timersub(&tv, &tv_start, &tv_delta);
2504                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2505                        tv_delta.tv_usec / USEC_PER_MSEC;
2506                 if (msec > HNS3_RESET_PROCESS_MS)
2507                         hns3_err(hw, "%d handle long time delta %" PRIx64
2508                                  " ms time=%ld.%.6ld",
2509                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2510         }
2511 }
2512
2513 static int
2514 hns3vf_reinit_dev(struct hns3_adapter *hns)
2515 {
2516         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2518         struct hns3_hw *hw = &hns->hw;
2519         int ret;
2520
2521         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2522                 rte_intr_disable(&pci_dev->intr_handle);
2523                 hns3vf_set_bus_master(pci_dev, true);
2524         }
2525
2526         /* Firmware command initialize */
2527         ret = hns3_cmd_init(hw);
2528         if (ret) {
2529                 hns3_err(hw, "Failed to init cmd: %d", ret);
2530                 return ret;
2531         }
2532
2533         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2534                 /*
2535                  * UIO enables msix by writing the pcie configuration space
2536                  * vfio_pci enables msix in rte_intr_enable.
2537                  */
2538                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2539                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2540                         if (hns3vf_enable_msix(pci_dev, true))
2541                                 hns3_err(hw, "Failed to enable msix");
2542                 }
2543
2544                 rte_intr_enable(&pci_dev->intr_handle);
2545         }
2546
2547         ret = hns3_reset_all_queues(hns);
2548         if (ret) {
2549                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2550                 return ret;
2551         }
2552
2553         ret = hns3vf_init_hardware(hns);
2554         if (ret) {
2555                 hns3_err(hw, "Failed to init hardware: %d", ret);
2556                 return ret;
2557         }
2558
2559         return 0;
2560 }
2561
2562 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2563         .dev_configure      = hns3vf_dev_configure,
2564         .dev_start          = hns3vf_dev_start,
2565         .dev_stop           = hns3vf_dev_stop,
2566         .dev_close          = hns3vf_dev_close,
2567         .mtu_set            = hns3vf_dev_mtu_set,
2568         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2569         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2570         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2571         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2572         .stats_get          = hns3_stats_get,
2573         .stats_reset        = hns3_stats_reset,
2574         .xstats_get         = hns3_dev_xstats_get,
2575         .xstats_get_names   = hns3_dev_xstats_get_names,
2576         .xstats_reset       = hns3_dev_xstats_reset,
2577         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2578         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2579         .dev_infos_get      = hns3vf_dev_infos_get,
2580         .fw_version_get     = hns3vf_fw_version_get,
2581         .rx_queue_setup     = hns3_rx_queue_setup,
2582         .tx_queue_setup     = hns3_tx_queue_setup,
2583         .rx_queue_release   = hns3_dev_rx_queue_release,
2584         .tx_queue_release   = hns3_dev_tx_queue_release,
2585         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2586         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2587         .rxq_info_get       = hns3_rxq_info_get,
2588         .txq_info_get       = hns3_txq_info_get,
2589         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2590         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2591         .mac_addr_add       = hns3vf_add_mac_addr,
2592         .mac_addr_remove    = hns3vf_remove_mac_addr,
2593         .mac_addr_set       = hns3vf_set_default_mac_addr,
2594         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2595         .link_update        = hns3vf_dev_link_update,
2596         .rss_hash_update    = hns3_dev_rss_hash_update,
2597         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2598         .reta_update        = hns3_dev_rss_reta_update,
2599         .reta_query         = hns3_dev_rss_reta_query,
2600         .filter_ctrl        = hns3_dev_filter_ctrl,
2601         .vlan_filter_set    = hns3vf_vlan_filter_set,
2602         .vlan_offload_set   = hns3vf_vlan_offload_set,
2603         .get_reg            = hns3_get_regs,
2604         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2605 };
2606
2607 static const struct hns3_reset_ops hns3vf_reset_ops = {
2608         .reset_service       = hns3vf_reset_service,
2609         .stop_service        = hns3vf_stop_service,
2610         .prepare_reset       = hns3vf_prepare_reset,
2611         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2612         .reinit_dev          = hns3vf_reinit_dev,
2613         .restore_conf        = hns3vf_restore_conf,
2614         .start_service       = hns3vf_start_service,
2615 };
2616
2617 static int
2618 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2619 {
2620         struct hns3_adapter *hns = eth_dev->data->dev_private;
2621         struct hns3_hw *hw = &hns->hw;
2622         int ret;
2623
2624         PMD_INIT_FUNC_TRACE();
2625
2626         eth_dev->process_private = (struct hns3_process_private *)
2627             rte_zmalloc_socket("hns3_filter_list",
2628                                sizeof(struct hns3_process_private),
2629                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2630         if (eth_dev->process_private == NULL) {
2631                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2632                 return -ENOMEM;
2633         }
2634
2635         /* initialize flow filter lists */
2636         hns3_filterlist_init(eth_dev);
2637
2638         hns3_set_rxtx_function(eth_dev);
2639         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2640         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2641                 ret = hns3_mp_init_secondary();
2642                 if (ret) {
2643                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2644                                           "process, ret = %d", ret);
2645                         goto err_mp_init_secondary;
2646                 }
2647
2648                 hw->secondary_cnt++;
2649                 return 0;
2650         }
2651
2652         ret = hns3_mp_init_primary();
2653         if (ret) {
2654                 PMD_INIT_LOG(ERR,
2655                              "Failed to init for primary process, ret = %d",
2656                              ret);
2657                 goto err_mp_init_primary;
2658         }
2659
2660         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2661         hns->is_vf = true;
2662         hw->data = eth_dev->data;
2663
2664         ret = hns3_reset_init(hw);
2665         if (ret)
2666                 goto err_init_reset;
2667         hw->reset.ops = &hns3vf_reset_ops;
2668
2669         ret = hns3vf_init_vf(eth_dev);
2670         if (ret) {
2671                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2672                 goto err_init_vf;
2673         }
2674
2675         /* Allocate memory for storing MAC addresses */
2676         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2677                                                sizeof(struct rte_ether_addr) *
2678                                                HNS3_VF_UC_MACADDR_NUM, 0);
2679         if (eth_dev->data->mac_addrs == NULL) {
2680                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2681                              "to store MAC addresses",
2682                              sizeof(struct rte_ether_addr) *
2683                              HNS3_VF_UC_MACADDR_NUM);
2684                 ret = -ENOMEM;
2685                 goto err_rte_zmalloc;
2686         }
2687
2688         /*
2689          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2690          * on the host by "ip link set ..." command. To avoid some incorrect
2691          * scenes, for example, hns3 VF PMD driver fails to receive and send
2692          * packets after user configure the MAC address by using the
2693          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2694          * address strategy as the hns3 kernel ethdev driver in the
2695          * initialization. If user configure a MAC address by the ip command
2696          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2697          * start with a random MAC address in the initialization.
2698          */
2699         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2700                 rte_eth_random_addr(hw->mac.mac_addr);
2701         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2702                             &eth_dev->data->mac_addrs[0]);
2703
2704         hw->adapter_state = HNS3_NIC_INITIALIZED;
2705         /*
2706          * Pass the information to the rte_eth_dev_close() that it should also
2707          * release the private port resources.
2708          */
2709         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2710
2711         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2712                 hns3_err(hw, "Reschedule reset service after dev_init");
2713                 hns3_schedule_reset(hns);
2714         } else {
2715                 /* IMP will wait ready flag before reset */
2716                 hns3_notify_reset_ready(hw, false);
2717         }
2718         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2719                           eth_dev);
2720         return 0;
2721
2722 err_rte_zmalloc:
2723         hns3vf_uninit_vf(eth_dev);
2724
2725 err_init_vf:
2726         rte_free(hw->reset.wait_data);
2727
2728 err_init_reset:
2729         hns3_mp_uninit_primary();
2730
2731 err_mp_init_primary:
2732 err_mp_init_secondary:
2733         eth_dev->dev_ops = NULL;
2734         eth_dev->rx_pkt_burst = NULL;
2735         eth_dev->tx_pkt_burst = NULL;
2736         eth_dev->tx_pkt_prepare = NULL;
2737         rte_free(eth_dev->process_private);
2738         eth_dev->process_private = NULL;
2739
2740         return ret;
2741 }
2742
2743 static int
2744 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2745 {
2746         struct hns3_adapter *hns = eth_dev->data->dev_private;
2747         struct hns3_hw *hw = &hns->hw;
2748
2749         PMD_INIT_FUNC_TRACE();
2750
2751         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2752                 return -EPERM;
2753
2754         eth_dev->dev_ops = NULL;
2755         eth_dev->rx_pkt_burst = NULL;
2756         eth_dev->tx_pkt_burst = NULL;
2757         eth_dev->tx_pkt_prepare = NULL;
2758
2759         if (hw->adapter_state < HNS3_NIC_CLOSING)
2760                 hns3vf_dev_close(eth_dev);
2761
2762         hw->adapter_state = HNS3_NIC_REMOVED;
2763         return 0;
2764 }
2765
2766 static int
2767 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2768                      struct rte_pci_device *pci_dev)
2769 {
2770         return rte_eth_dev_pci_generic_probe(pci_dev,
2771                                              sizeof(struct hns3_adapter),
2772                                              hns3vf_dev_init);
2773 }
2774
2775 static int
2776 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2777 {
2778         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2779 }
2780
2781 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2782         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2783         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2784         { .vendor_id = 0, /* sentinel */ },
2785 };
2786
2787 static struct rte_pci_driver rte_hns3vf_pmd = {
2788         .id_table = pci_id_hns3vf_map,
2789         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2790         .probe = eth_hns3vf_pci_probe,
2791         .remove = eth_hns3vf_pci_remove,
2792 };
2793
2794 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2795 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2796 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");