drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 209                             struct rte_ether_addr *mac_addr)
 210 {
 211 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 212         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 213         struct rte_ether_addr *old_addr;
 214         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 215         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 216         int ret;
 217
 218         /*
 219          * It has been guaranteed that input parameter named mac_addr is valid
 220          * address in the rte layer of DPDK framework.
 221          */
 222         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 223         rte_spinlock_lock(&hw->lock);
 224         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 225         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 226                RTE_ETHER_ADDR_LEN);
 227
 228         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 229                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 230                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 231         if (ret) {
 232                 /*
 233                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 234                  * driver. When user has configured a MAC address for VF device
 235                  * by "ip link set ..." command based on the PF device, the hns3
 236                  * PF kernel ethdev driver does not allow VF driver to request
 237                  * reconfiguring a different default MAC address, and return
 238                  * -EPREM to VF driver through mailbox.
 239                  */
 240                 if (ret == -EPERM) {
 241                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 242                                               old_addr);
 243                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 244                                   mac_str);
 245                 } else {
 246                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 247                                               mac_addr);
 248                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 249                                  mac_str, ret);
 250                 }
 251         }
 252
 253         rte_ether_addr_copy(mac_addr,
 254                             (struct rte_ether_addr *)hw->mac.mac_addr);
 255         rte_spinlock_unlock(&hw->lock);
 256
 257         return ret;
 258 }
 259
 260 static int
 261 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 262                        struct rte_ether_addr *mac_addr)
 263 {
 264         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 265         int ret;
 266
 267         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 268                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 269                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 270                                 NULL, 0);
 271         if (ret) {
 272                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 273                                       mac_addr);
 274                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 275                          mac_str, ret);
 276         }
 277
 278         return ret;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         int ret;
 287
 288         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 289                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 290                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 291                                 NULL, 0);
 292         if (ret) {
 293                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 294                                       mac_addr);
 295                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 296                          mac_str, ret);
 297         }
 298
 299         return ret;
 300 }
 301
 302 static int
 303 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 304                             struct rte_ether_addr *mc_addr_set,
 305                             uint32_t nb_mc_addr)
 306 {
 307         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 308         struct rte_ether_addr *addr;
 309         int cur_addr_num;
 310         int set_addr_num;
 311         int num;
 312         int ret;
 313         int i;
 314
 315         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 316         if (ret)
 317                 return ret;
 318
 319         rte_spinlock_lock(&hw->lock);
 320         cur_addr_num = hw->mc_addrs_num;
 321         for (i = 0; i < cur_addr_num; i++) {
 322                 num = cur_addr_num - i - 1;
 323                 addr = &hw->mc_addrs[num];
 324                 ret = hw->ops.del_mc_mac_addr(hw, addr);
 325                 if (ret) {
 326                         rte_spinlock_unlock(&hw->lock);
 327                         return ret;
 328                 }
 329
 330                 hw->mc_addrs_num--;
 331         }
 332
 333         set_addr_num = (int)nb_mc_addr;
 334         for (i = 0; i < set_addr_num; i++) {
 335                 addr = &mc_addr_set[i];
 336                 ret = hw->ops.add_mc_mac_addr(hw, addr);
 337                 if (ret) {
 338                         rte_spinlock_unlock(&hw->lock);
 339                         return ret;
 340                 }
 341
 342                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 343                 hw->mc_addrs_num++;
 344         }
 345         rte_spinlock_unlock(&hw->lock);
 346
 347         return 0;
 348 }
 349
 350 static int
 351 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 352                         bool en_uc_pmc, bool en_mc_pmc)
 353 {
 354         struct hns3_mbx_vf_to_pf_cmd *req;
 355         struct hns3_cmd_desc desc;
 356         int ret;
 357
 358         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 359
 360         /*
 361          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 362          * so there are some features for promiscuous/allmulticast mode in hns3
 363          * VF PMD driver as below:
 364          * 1. The promiscuous/allmulticast mode can be configured successfully
 365          *    only based on the trusted VF device. If based on the non trusted
 366          *    VF device, configuring promiscuous/allmulticast mode will fail.
 367          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 368          *    kernel ethdev driver on the host by the following command:
 369          *      "ip link set <eth num> vf <vf id> turst on"
 370          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 371          *    driver can receive the ingress and outgoing traffic. In the words,
 372          *    all the ingress packets, all the packets sent from the PF and
 373          *    other VFs on the same physical port.
 374          * 3. Note: Because of the hardware constraints, By default vlan filter
 375          *    is enabled and couldn't be turned off based on VF device, so vlan
 376          *    filter is still effective even in promiscuous mode. If upper
 377          *    applications don't call rte_eth_dev_vlan_filter API function to
 378          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 379          *    the packets with vlan tag in promiscuoue mode.
 380          */
 381         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 382         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 383         req->msg[1] = en_bc_pmc ? 1 : 0;
 384         req->msg[2] = en_uc_pmc ? 1 : 0;
 385         req->msg[3] = en_mc_pmc ? 1 : 0;
 386         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 387
 388         ret = hns3_cmd_send(hw, &desc, 1);
 389         if (ret)
 390                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 391
 392         return ret;
 393 }
 394
 395 static int
 396 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 397 {
 398         struct hns3_adapter *hns = dev->data->dev_private;
 399         struct hns3_hw *hw = &hns->hw;
 400         int ret;
 401
 402         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 403         if (ret)
 404                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 405                         ret);
 406         return ret;
 407 }
 408
 409 static int
 410 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 411 {
 412         bool allmulti = dev->data->all_multicast ? true : false;
 413         struct hns3_adapter *hns = dev->data->dev_private;
 414         struct hns3_hw *hw = &hns->hw;
 415         int ret;
 416
 417         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 418         if (ret)
 419                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 420                         ret);
 421         return ret;
 422 }
 423
 424 static int
 425 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 426 {
 427         struct hns3_adapter *hns = dev->data->dev_private;
 428         struct hns3_hw *hw = &hns->hw;
 429         int ret;
 430
 431         if (dev->data->promiscuous)
 432                 return 0;
 433
 434         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 435         if (ret)
 436                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 437                         ret);
 438         return ret;
 439 }
 440
 441 static int
 442 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 443 {
 444         struct hns3_adapter *hns = dev->data->dev_private;
 445         struct hns3_hw *hw = &hns->hw;
 446         int ret;
 447
 448         if (dev->data->promiscuous)
 449                 return 0;
 450
 451         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 452         if (ret)
 453                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 454                         ret);
 455         return ret;
 456 }
 457
 458 static int
 459 hns3vf_restore_promisc(struct hns3_adapter *hns)
 460 {
 461         struct hns3_hw *hw = &hns->hw;
 462         bool allmulti = hw->data->all_multicast ? true : false;
 463
 464         if (hw->data->promiscuous)
 465                 return hns3vf_set_promisc_mode(hw, true, true, true);
 466
 467         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 468 }
 469
 470 static int
 471 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 472                              bool mmap, enum hns3_ring_type queue_type,
 473                              uint16_t queue_id)
 474 {
 475         struct hns3_vf_bind_vector_msg bind_msg;
 476         const char *op_str;
 477         uint16_t code;
 478         int ret;
 479
 480         memset(&bind_msg, 0, sizeof(bind_msg));
 481         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 482                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 483         bind_msg.vector_id = vector_id;
 484
 485         if (queue_type == HNS3_RING_TYPE_RX)
 486                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 487         else
 488                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 489
 490         bind_msg.param[0].ring_type = queue_type;
 491         bind_msg.ring_num = 1;
 492         bind_msg.param[0].tqp_index = queue_id;
 493         op_str = mmap ? "Map" : "Unmap";
 494         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 495                                 sizeof(bind_msg), false, NULL, 0);
 496         if (ret)
 497                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 498                          op_str, queue_id, bind_msg.vector_id, ret);
 499
 500         return ret;
 501 }
 502
 503 static int
 504 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 505 {
 506         uint16_t vec;
 507         int ret;
 508         int i;
 509
 510         /*
 511          * In hns3 network engine, vector 0 is always the misc interrupt of this
 512          * function, vector 1~N can be used respectively for the queues of the
 513          * function. Tx and Rx queues with the same number share the interrupt
 514          * vector. In the initialization clearing the all hardware mapping
 515          * relationship configurations between queues and interrupt vectors is
 516          * needed, so some error caused by the residual configurations, such as
 517          * the unexpected Tx interrupt, can be avoid.
 518          */
 519         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 520         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 521                 vec = vec - 1; /* the last interrupt is reserved */
 522         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 523         for (i = 0; i < hw->intr_tqps_num; i++) {
 524                 /*
 525                  * Set gap limiter/rate limiter/quanity limiter algorithm
 526                  * configuration for interrupt coalesce of queue's interrupt.
 527                  */
 528                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 529                                        HNS3_TQP_INTR_GL_DEFAULT);
 530                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 531                                        HNS3_TQP_INTR_GL_DEFAULT);
 532                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 533                 /*
 534                  * QL(quantity limiter) is not used currently, just set 0 to
 535                  * close it.
 536                  */
 537                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 538
 539                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 540                                                    HNS3_RING_TYPE_TX, i);
 541                 if (ret) {
 542                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 543                                           "vector: %u, ret=%d", i, vec, ret);
 544                         return ret;
 545                 }
 546
 547                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 548                                                    HNS3_RING_TYPE_RX, i);
 549                 if (ret) {
 550                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 551                                           "vector: %u, ret=%d", i, vec, ret);
 552                         return ret;
 553                 }
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int
 560 hns3vf_dev_configure(struct rte_eth_dev *dev)
 561 {
 562         struct hns3_adapter *hns = dev->data->dev_private;
 563         struct hns3_hw *hw = &hns->hw;
 564         struct rte_eth_conf *conf = &dev->data->dev_conf;
 565         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 566         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 567         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 568         struct rte_eth_rss_conf rss_conf;
 569         bool gro_en;
 570         int ret;
 571
 572         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 573
 574         /*
 575          * Some versions of hardware network engine does not support
 576          * individually enable/disable/reset the Tx or Rx queue. These devices
 577          * must enable/disable/reset Tx and Rx queues at the same time. When the
 578          * numbers of Tx queues allocated by upper applications are not equal to
 579          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 580          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 581          * work as usual. But these fake queues are imperceptible, and can not
 582          * be used by upper applications.
 583          */
 584         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 585         if (ret) {
 586                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 587                 hw->cfg_max_queues = 0;
 588                 return ret;
 589         }
 590
 591         hw->adapter_state = HNS3_NIC_CONFIGURING;
 592         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 593                 hns3_err(hw, "setting link speed/duplex not supported");
 594                 ret = -EINVAL;
 595                 goto cfg_err;
 596         }
 597
 598         /* When RSS is not configured, redirect the packet queue 0 */
 599         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 600                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 601                 hw->rss_dis_flag = false;
 602                 rss_conf = conf->rx_adv_conf.rss_conf;
 603                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 604                 if (ret)
 605                         goto cfg_err;
 606         }
 607
 608         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 609         if (ret != 0)
 610                 goto cfg_err;
 611
 612         ret = hns3vf_dev_configure_vlan(dev);
 613         if (ret)
 614                 goto cfg_err;
 615
 616         /* config hardware GRO */
 617         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 618         ret = hns3_config_gro(hw, gro_en);
 619         if (ret)
 620                 goto cfg_err;
 621
 622         hns3_init_rx_ptype_tble(dev);
 623
 624         hw->adapter_state = HNS3_NIC_CONFIGURED;
 625         return 0;
 626
 627 cfg_err:
 628         hw->cfg_max_queues = 0;
 629         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 630         hw->adapter_state = HNS3_NIC_INITIALIZED;
 631
 632         return ret;
 633 }
 634
 635 static int
 636 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 637 {
 638         int ret;
 639
 640         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 641                                 sizeof(mtu), true, NULL, 0);
 642         if (ret)
 643                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 644
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 650 {
 651         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 652         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 653         int ret;
 654
 655         /*
 656          * The hns3 PF/VF devices on the same port share the hardware MTU
 657          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 658          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 659          * driver, there is no need to stop the port for hns3 VF device, and the
 660          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 661          * PF's MTU.
 662          */
 663         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 664                 hns3_err(hw, "Failed to set mtu during resetting");
 665                 return -EIO;
 666         }
 667
 668         /*
 669          * when Rx of scattered packets is off, we have some possibility of
 670          * using vector Rx process function or simple Rx functions in hns3 PMD
 671          * driver. If the input MTU is increased and the maximum length of
 672          * received packets is greater than the length of a buffer for Rx
 673          * packet, the hardware network engine needs to use multiple BDs and
 674          * buffers to store these packets. This will cause problems when still
 675          * using vector Rx process function or simple Rx function to receiving
 676          * packets. So, when Rx of scattered packets is off and device is
 677          * started, it is not permitted to increase MTU so that the maximum
 678          * length of Rx packets is greater than Rx buffer length.
 679          */
 680         if (dev->data->dev_started && !dev->data->scattered_rx &&
 681             frame_size > hw->rx_buf_len) {
 682                 hns3_err(hw, "failed to set mtu because current is "
 683                         "not scattered rx mode");
 684                 return -EOPNOTSUPP;
 685         }
 686
 687         rte_spinlock_lock(&hw->lock);
 688         ret = hns3vf_config_mtu(hw, mtu);
 689         if (ret) {
 690                 rte_spinlock_unlock(&hw->lock);
 691                 return ret;
 692         }
 693         rte_spinlock_unlock(&hw->lock);
 694
 695         return 0;
 696 }
 697
 698 static int
 699 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 700 {
 701         struct hns3_adapter *hns = eth_dev->data->dev_private;
 702         struct hns3_hw *hw = &hns->hw;
 703         uint16_t q_num = hw->tqps_num;
 704
 705         /*
 706          * In interrupt mode, 'max_rx_queues' is set based on the number of
 707          * MSI-X interrupt resources of the hardware.
 708          */
 709         if (hw->data->dev_conf.intr_conf.rxq == 1)
 710                 q_num = hw->intr_tqps_num;
 711
 712         info->max_rx_queues = q_num;
 713         info->max_tx_queues = hw->tqps_num;
 714         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 715         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 716         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 717         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 718         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 719
 720         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 721                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 722                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 723                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 724                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 725                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 726                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 727                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 728                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 729                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 730                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 731         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 732                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 733                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 734                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 735                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 736                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 737                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 738                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 739                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 740                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 741                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 742                                  hns3_txvlan_cap_get(hw));
 743
 744         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 745                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 746
 747         if (hns3_dev_get_support(hw, INDEP_TXRX))
 748                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 749                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 750
 751         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 752                 .nb_max = HNS3_MAX_RING_DESC,
 753                 .nb_min = HNS3_MIN_RING_DESC,
 754                 .nb_align = HNS3_ALIGN_RING_DESC,
 755         };
 756
 757         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 758                 .nb_max = HNS3_MAX_RING_DESC,
 759                 .nb_min = HNS3_MIN_RING_DESC,
 760                 .nb_align = HNS3_ALIGN_RING_DESC,
 761                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 762                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 763         };
 764
 765         info->default_rxconf = (struct rte_eth_rxconf) {
 766                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 767                 /*
 768                  * If there are no available Rx buffer descriptors, incoming
 769                  * packets are always dropped by hardware based on hns3 network
 770                  * engine.
 771                  */
 772                 .rx_drop_en = 1,
 773                 .offloads = 0,
 774         };
 775         info->default_txconf = (struct rte_eth_txconf) {
 776                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 777                 .offloads = 0,
 778         };
 779
 780         info->reta_size = hw->rss_ind_tbl_size;
 781         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 782         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 783
 784         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 785         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
 786         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 787         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
 788         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 789         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 790
 791         return 0;
 792 }
 793
 794 static void
 795 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 796 {
 797         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 798 }
 799
 800 static void
 801 hns3vf_disable_irq0(struct hns3_hw *hw)
 802 {
 803         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 804 }
 805
 806 static void
 807 hns3vf_enable_irq0(struct hns3_hw *hw)
 808 {
 809         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 810 }
 811
 812 static enum hns3vf_evt_cause
 813 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 814 {
 815         struct hns3_hw *hw = &hns->hw;
 816         enum hns3vf_evt_cause ret;
 817         uint32_t cmdq_stat_reg;
 818         uint32_t rst_ing_reg;
 819         uint32_t val;
 820
 821         /* Fetch the events from their corresponding regs */
 822         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 823         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 824                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 825                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 826                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 827                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 828                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 829                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 830                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 831                 if (clearval) {
 832                         hw->reset.stats.global_cnt++;
 833                         hns3_warn(hw, "Global reset detected, clear reset status");
 834                 } else {
 835                         hns3_schedule_delayed_reset(hns);
 836                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 837                 }
 838
 839                 ret = HNS3VF_VECTOR0_EVENT_RST;
 840                 goto out;
 841         }
 842
 843         /* Check for vector0 mailbox(=CMDQ RX) event source */
 844         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 845                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 846                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 847                 goto out;
 848         }
 849
 850         val = 0;
 851         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 852 out:
 853         if (clearval)
 854                 *clearval = val;
 855         return ret;
 856 }
 857
 858 static void
 859 hns3vf_interrupt_handler(void *param)
 860 {
 861         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 862         struct hns3_adapter *hns = dev->data->dev_private;
 863         struct hns3_hw *hw = &hns->hw;
 864         enum hns3vf_evt_cause event_cause;
 865         uint32_t clearval;
 866
 867         /* Disable interrupt */
 868         hns3vf_disable_irq0(hw);
 869
 870         /* Read out interrupt causes */
 871         event_cause = hns3vf_check_event_cause(hns, &clearval);
 872         /* Clear interrupt causes */
 873         hns3vf_clear_event_cause(hw, clearval);
 874
 875         switch (event_cause) {
 876         case HNS3VF_VECTOR0_EVENT_RST:
 877                 hns3_schedule_reset(hns);
 878                 break;
 879         case HNS3VF_VECTOR0_EVENT_MBX:
 880                 hns3_dev_handle_mbx_msg(hw);
 881                 break;
 882         default:
 883                 break;
 884         }
 885
 886         /* Enable interrupt */
 887         hns3vf_enable_irq0(hw);
 888 }
 889
 890 static void
 891 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
 892 {
 893         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
 894         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
 895         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
 896         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
 897 }
 898
 899 static void
 900 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
 901 {
 902         struct hns3_dev_specs_0_cmd *req0;
 903
 904         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
 905
 906         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
 907         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
 908         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
 909         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
 910 }
 911
 912 static int
 913 hns3vf_check_dev_specifications(struct hns3_hw *hw)
 914 {
 915         if (hw->rss_ind_tbl_size == 0 ||
 916             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
 917                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
 918                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
 919                               HNS3_RSS_IND_TBL_SIZE_MAX);
 920                 return -EINVAL;
 921         }
 922
 923         return 0;
 924 }
 925
 926 static int
 927 hns3vf_query_dev_specifications(struct hns3_hw *hw)
 928 {
 929         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
 930         int ret;
 931         int i;
 932
 933         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
 934                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
 935                                           true);
 936                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 937         }
 938         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
 939
 940         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
 941         if (ret)
 942                 return ret;
 943
 944         hns3vf_parse_dev_specifications(hw, desc);
 945
 946         return hns3vf_check_dev_specifications(hw);
 947 }
 948
 949 void
 950 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
 951 {
 952         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
 953                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 954         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 955         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 956
 957         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 958                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 959                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 960 }
 961
 962 static void
 963 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
 964 {
 965 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
 966
 967         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
 968         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
 969         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
 970         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
 971         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
 972
 973         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
 974                          __ATOMIC_RELEASE);
 975
 976         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 977                                 NULL, 0);
 978
 979         while (remain_ms > 0) {
 980                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
 981                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
 982                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
 983                         break;
 984                 remain_ms--;
 985         }
 986
 987         /*
 988          * When exit above loop, the pf_push_lsc_cap could be one of the three
 989          * state: unknown (means pf not ack), not_supported, supported.
 990          * Here config it as 'not_supported' when it's 'unknown' state.
 991          */
 992         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
 993                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
 994
 995         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
 996                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
 997                 hns3_info(hw, "detect PF support push link status change!");
 998         } else {
 999                 /*
1000                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1001                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1002                  * the RTE_ETH_DEV_INTR_LSC capability.
1003                  */
1004                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1005         }
1006 }
1007
1008 static int
1009 hns3vf_get_capability(struct hns3_hw *hw)
1010 {
1011         struct rte_pci_device *pci_dev;
1012         struct rte_eth_dev *eth_dev;
1013         uint8_t revision;
1014         int ret;
1015
1016         eth_dev = &rte_eth_devices[hw->data->port_id];
1017         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1018
1019         /* Get PCI revision id */
1020         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1021                                   HNS3_PCI_REVISION_ID);
1022         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1023                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1024                              ret);
1025                 return -EIO;
1026         }
1027         hw->revision = revision;
1028
1029         if (revision < PCI_REVISION_ID_HIP09_A) {
1030                 hns3vf_set_default_dev_specifications(hw);
1031                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1032                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1033                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1034                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1035                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1036                 hw->rss_info.ipv6_sctp_offload_supported = false;
1037                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1038                 return 0;
1039         }
1040
1041         ret = hns3vf_query_dev_specifications(hw);
1042         if (ret) {
1043                 PMD_INIT_LOG(ERR,
1044                              "failed to query dev specifications, ret = %d",
1045                              ret);
1046                 return ret;
1047         }
1048
1049         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1050         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1051         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1052         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1053         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1054         hw->rss_info.ipv6_sctp_offload_supported = true;
1055         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1056
1057         return 0;
1058 }
1059
1060 static int
1061 hns3vf_check_tqp_info(struct hns3_hw *hw)
1062 {
1063         if (hw->tqps_num == 0) {
1064                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1065                 return -EINVAL;
1066         }
1067
1068         if (hw->rss_size_max == 0) {
1069                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1070                 return -EINVAL;
1071         }
1072
1073         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1074
1075         return 0;
1076 }
1077
1078 static int
1079 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1080 {
1081         uint8_t resp_msg;
1082         int ret;
1083
1084         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1085                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1086                                 true, &resp_msg, sizeof(resp_msg));
1087         if (ret) {
1088                 if (ret == -ETIME) {
1089                         /*
1090                          * Getting current port based VLAN state from PF driver
1091                          * will not affect VF driver's basic function. Because
1092                          * the VF driver relies on hns3 PF kernel ether driver,
1093                          * to avoid introducing compatibility issues with older
1094                          * version of PF driver, no failure will be returned
1095                          * when the return value is ETIME. This return value has
1096                          * the following scenarios:
1097                          * 1) Firmware didn't return the results in time
1098                          * 2) the result return by firmware is timeout
1099                          * 3) the older version of kernel side PF driver does
1100                          *    not support this mailbox message.
1101                          * For scenarios 1 and 2, it is most likely that a
1102                          * hardware error has occurred, or a hardware reset has
1103                          * occurred. In this case, these errors will be caught
1104                          * by other functions.
1105                          */
1106                         PMD_INIT_LOG(WARNING,
1107                                 "failed to get PVID state for timeout, maybe "
1108                                 "kernel side PF driver doesn't support this "
1109                                 "mailbox message, or firmware didn't respond.");
1110                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1111                 } else {
1112                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1113                                 " ret = %d", ret);
1114                         return ret;
1115                 }
1116         }
1117         hw->port_base_vlan_cfg.state = resp_msg ?
1118                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1119         return 0;
1120 }
1121
1122 static int
1123 hns3vf_get_queue_info(struct hns3_hw *hw)
1124 {
1125 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1126         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1127         int ret;
1128
1129         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1130                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1131         if (ret) {
1132                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1133                 return ret;
1134         }
1135
1136         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1137         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1138
1139         return hns3vf_check_tqp_info(hw);
1140 }
1141
1142 static int
1143 hns3vf_get_queue_depth(struct hns3_hw *hw)
1144 {
1145 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1146         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1147         int ret;
1148
1149         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1150                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1151         if (ret) {
1152                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1153                              ret);
1154                 return ret;
1155         }
1156
1157         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1158         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1159
1160         return 0;
1161 }
1162
1163 static void
1164 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1165 {
1166         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1167                 hns3_set_bit(hw->capability,
1168                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1169 }
1170
1171 static int
1172 hns3vf_get_num_tc(struct hns3_hw *hw)
1173 {
1174         uint8_t num_tc = 0;
1175         uint32_t i;
1176
1177         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1178                 if (hw->hw_tc_map & BIT(i))
1179                         num_tc++;
1180         }
1181         return num_tc;
1182 }
1183
1184 static int
1185 hns3vf_get_basic_info(struct hns3_hw *hw)
1186 {
1187         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1188         struct hns3_basic_info *basic_info;
1189         int ret;
1190
1191         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1192                                 true, resp_msg, sizeof(resp_msg));
1193         if (ret) {
1194                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1195                                 ret);
1196                 return ret;
1197         }
1198
1199         basic_info = (struct hns3_basic_info *)resp_msg;
1200         hw->hw_tc_map = basic_info->hw_tc_map;
1201         hw->num_tc = hns3vf_get_num_tc(hw);
1202         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1203         hns3vf_update_caps(hw, basic_info->caps);
1204
1205         return 0;
1206 }
1207
1208 static int
1209 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1210 {
1211         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1212         int ret;
1213
1214         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1215                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1216         if (ret) {
1217                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1218                 return ret;
1219         }
1220
1221         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1222
1223         return 0;
1224 }
1225
1226 static int
1227 hns3vf_get_configuration(struct hns3_hw *hw)
1228 {
1229         int ret;
1230
1231         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1232         hw->rss_dis_flag = false;
1233
1234         /* Get device capability */
1235         ret = hns3vf_get_capability(hw);
1236         if (ret) {
1237                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1238                 return ret;
1239         }
1240
1241         hns3vf_get_push_lsc_cap(hw);
1242
1243         /* Get basic info from PF */
1244         ret = hns3vf_get_basic_info(hw);
1245         if (ret)
1246                 return ret;
1247
1248         /* Get queue configuration from PF */
1249         ret = hns3vf_get_queue_info(hw);
1250         if (ret)
1251                 return ret;
1252
1253         /* Get queue depth info from PF */
1254         ret = hns3vf_get_queue_depth(hw);
1255         if (ret)
1256                 return ret;
1257
1258         /* Get user defined VF MAC addr from PF */
1259         ret = hns3vf_get_host_mac_addr(hw);
1260         if (ret)
1261                 return ret;
1262
1263         return hns3vf_get_port_base_vlan_filter_state(hw);
1264 }
1265
1266 static int
1267 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1268                             uint16_t nb_tx_q)
1269 {
1270         struct hns3_hw *hw = &hns->hw;
1271
1272         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1273 }
1274
1275 static void
1276 hns3vf_request_link_info(struct hns3_hw *hw)
1277 {
1278         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1279         bool send_req;
1280         int ret;
1281
1282         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1283                 return;
1284
1285         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1286                    vf->req_link_info_cnt > 0;
1287         if (!send_req)
1288                 return;
1289
1290         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1291                                 NULL, 0);
1292         if (ret) {
1293                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1294                 return;
1295         }
1296
1297         if (vf->req_link_info_cnt > 0)
1298                 vf->req_link_info_cnt--;
1299 }
1300
1301 void
1302 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1303                           uint32_t link_speed, uint8_t link_duplex)
1304 {
1305         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1306         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1307         struct hns3_mac *mac = &hw->mac;
1308         int ret;
1309
1310         /*
1311          * PF kernel driver may push link status when VF driver is in resetting,
1312          * driver will stop polling job in this case, after resetting done
1313          * driver will start polling job again.
1314          * When polling job started, driver will get initial link status by
1315          * sending request to PF kernel driver, then could update link status by
1316          * process PF kernel driver's link status mailbox message.
1317          */
1318         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1319                 return;
1320
1321         if (hw->adapter_state != HNS3_NIC_STARTED)
1322                 return;
1323
1324         mac->link_status = link_status;
1325         mac->link_speed = link_speed;
1326         mac->link_duplex = link_duplex;
1327         ret = hns3vf_dev_link_update(dev, 0);
1328         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1329                 hns3_start_report_lse(dev);
1330 }
1331
1332 static int
1333 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1334 {
1335 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1336         struct hns3_hw *hw = &hns->hw;
1337         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1338         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1339         uint8_t is_kill = on ? 0 : 1;
1340
1341         msg_data[0] = is_kill;
1342         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1343         memcpy(&msg_data[3], &proto, sizeof(proto));
1344
1345         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1346                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1347                                  0);
1348 }
1349
1350 static int
1351 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1352 {
1353         struct hns3_adapter *hns = dev->data->dev_private;
1354         struct hns3_hw *hw = &hns->hw;
1355         int ret;
1356
1357         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1358                 hns3_err(hw,
1359                          "vf set vlan id failed during resetting, vlan_id =%u",
1360                          vlan_id);
1361                 return -EIO;
1362         }
1363         rte_spinlock_lock(&hw->lock);
1364         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1365         rte_spinlock_unlock(&hw->lock);
1366         if (ret)
1367                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1368                          vlan_id, ret);
1369
1370         return ret;
1371 }
1372
1373 static int
1374 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1375 {
1376         uint8_t msg_data;
1377         int ret;
1378
1379         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1380                 return 0;
1381
1382         msg_data = enable ? 1 : 0;
1383         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1384                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1385                         sizeof(msg_data), true, NULL, 0);
1386         if (ret)
1387                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1388                                 enable ? "enable" : "disable", ret);
1389
1390         return ret;
1391 }
1392
1393 static int
1394 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1395 {
1396         uint8_t msg_data;
1397         int ret;
1398
1399         msg_data = enable ? 1 : 0;
1400         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1401                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1402         if (ret)
1403                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1404                                 enable ? "enable" : "disable", ret);
1405
1406         return ret;
1407 }
1408
1409 static int
1410 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1411 {
1412         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1414         unsigned int tmp_mask;
1415         int ret = 0;
1416
1417         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1418                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1419                              "mask = 0x%x", mask);
1420                 return -EIO;
1421         }
1422
1423         tmp_mask = (unsigned int)mask;
1424
1425         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1426                 rte_spinlock_lock(&hw->lock);
1427                 /* Enable or disable VLAN filter */
1428                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1429                         ret = hns3vf_en_vlan_filter(hw, true);
1430                 else
1431                         ret = hns3vf_en_vlan_filter(hw, false);
1432                 rte_spinlock_unlock(&hw->lock);
1433                 if (ret)
1434                         return ret;
1435         }
1436
1437         /* Vlan stripping setting */
1438         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1439                 rte_spinlock_lock(&hw->lock);
1440                 /* Enable or disable VLAN stripping */
1441                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1442                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1443                 else
1444                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1445                 rte_spinlock_unlock(&hw->lock);
1446         }
1447
1448         return ret;
1449 }
1450
1451 static int
1452 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1453 {
1454         struct rte_vlan_filter_conf *vfc;
1455         struct hns3_hw *hw = &hns->hw;
1456         uint16_t vlan_id;
1457         uint64_t vbit;
1458         uint64_t ids;
1459         int ret = 0;
1460         uint32_t i;
1461
1462         vfc = &hw->data->vlan_filter_conf;
1463         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1464                 if (vfc->ids[i] == 0)
1465                         continue;
1466                 ids = vfc->ids[i];
1467                 while (ids) {
1468                         /*
1469                          * 64 means the num bits of ids, one bit corresponds to
1470                          * one vlan id
1471                          */
1472                         vlan_id = 64 * i;
1473                         /* count trailing zeroes */
1474                         vbit = ~ids & (ids - 1);
1475                         /* clear least significant bit set */
1476                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1477                         for (; vbit;) {
1478                                 vbit >>= 1;
1479                                 vlan_id++;
1480                         }
1481                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1482                         if (ret) {
1483                                 hns3_err(hw,
1484                                          "VF handle vlan table failed, ret =%d, on = %d",
1485                                          ret, on);
1486                                 return ret;
1487                         }
1488                 }
1489         }
1490
1491         return ret;
1492 }
1493
1494 static int
1495 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1496 {
1497         return hns3vf_handle_all_vlan_table(hns, 0);
1498 }
1499
1500 static int
1501 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1502 {
1503         struct hns3_hw *hw = &hns->hw;
1504         struct rte_eth_conf *dev_conf;
1505         bool en;
1506         int ret;
1507
1508         dev_conf = &hw->data->dev_conf;
1509         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1510                                                                    : false;
1511         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1512         if (ret)
1513                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1514                          ret);
1515         return ret;
1516 }
1517
1518 static int
1519 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1520 {
1521         struct hns3_adapter *hns = dev->data->dev_private;
1522         struct rte_eth_dev_data *data = dev->data;
1523         struct hns3_hw *hw = &hns->hw;
1524         int ret;
1525
1526         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1527             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1528             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1529                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1530                               "or hw_vlan_insert_pvid is not support!");
1531         }
1532
1533         /* Apply vlan offload setting */
1534         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1535                                         RTE_ETH_VLAN_FILTER_MASK);
1536         if (ret)
1537                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1538
1539         return ret;
1540 }
1541
1542 static int
1543 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1544 {
1545         uint8_t msg_data;
1546
1547         msg_data = alive ? 1 : 0;
1548         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1549                                  sizeof(msg_data), false, NULL, 0);
1550 }
1551
1552 static void
1553 hns3vf_keep_alive_handler(void *param)
1554 {
1555         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1556         struct hns3_adapter *hns = eth_dev->data->dev_private;
1557         struct hns3_hw *hw = &hns->hw;
1558         int ret;
1559
1560         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1561                                 false, NULL, 0);
1562         if (ret)
1563                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1564                          ret);
1565
1566         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1567                           eth_dev);
1568 }
1569
1570 static void
1571 hns3vf_service_handler(void *param)
1572 {
1573         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1574         struct hns3_adapter *hns = eth_dev->data->dev_private;
1575         struct hns3_hw *hw = &hns->hw;
1576
1577         /*
1578          * The query link status and reset processing are executed in the
1579          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1580          * and the query operation will timeout after 30ms. In the case of
1581          * multiple PF/VFs, each query failure timeout causes the IMP reset
1582          * interrupt to fail to respond within 100ms.
1583          * Before querying the link status, check whether there is a reset
1584          * pending, and if so, abandon the query.
1585          */
1586         if (!hns3vf_is_reset_pending(hns))
1587                 hns3vf_request_link_info(hw);
1588         else
1589                 hns3_warn(hw, "Cancel the query when reset is pending");
1590
1591         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1592                           eth_dev);
1593 }
1594
1595 static void
1596 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1597 {
1598 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1599
1600         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1601
1602         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1603                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1604
1605         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1606
1607         hns3vf_service_handler(dev);
1608 }
1609
1610 static void
1611 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1612 {
1613         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1614
1615         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1616
1617         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1618 }
1619
1620 static int
1621 hns3_query_vf_resource(struct hns3_hw *hw)
1622 {
1623         struct hns3_vf_res_cmd *req;
1624         struct hns3_cmd_desc desc;
1625         uint16_t num_msi;
1626         int ret;
1627
1628         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1629         ret = hns3_cmd_send(hw, &desc, 1);
1630         if (ret) {
1631                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1632                 return ret;
1633         }
1634
1635         req = (struct hns3_vf_res_cmd *)desc.data;
1636         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1637                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1638         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1639                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1640                          num_msi, HNS3_MIN_VECTOR_NUM);
1641                 return -EINVAL;
1642         }
1643
1644         hw->num_msi = num_msi;
1645
1646         return 0;
1647 }
1648
1649 static int
1650 hns3vf_init_hardware(struct hns3_adapter *hns)
1651 {
1652         struct hns3_hw *hw = &hns->hw;
1653         uint16_t mtu = hw->data->mtu;
1654         int ret;
1655
1656         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1657         if (ret)
1658                 return ret;
1659
1660         ret = hns3vf_config_mtu(hw, mtu);
1661         if (ret)
1662                 goto err_init_hardware;
1663
1664         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1665         if (ret) {
1666                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1667                 goto err_init_hardware;
1668         }
1669
1670         ret = hns3_config_gro(hw, false);
1671         if (ret) {
1672                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1673                 goto err_init_hardware;
1674         }
1675
1676         /*
1677          * In the initialization clearing the all hardware mapping relationship
1678          * configurations between queues and interrupt vectors is needed, so
1679          * some error caused by the residual configurations, such as the
1680          * unexpected interrupt, can be avoid.
1681          */
1682         ret = hns3vf_init_ring_with_vector(hw);
1683         if (ret) {
1684                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1685                 goto err_init_hardware;
1686         }
1687
1688         return 0;
1689
1690 err_init_hardware:
1691         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1692         return ret;
1693 }
1694
1695 static int
1696 hns3vf_clear_vport_list(struct hns3_hw *hw)
1697 {
1698         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1699                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1700                                  NULL, 0);
1701 }
1702
1703 static int
1704 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1705 {
1706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1707         struct hns3_adapter *hns = eth_dev->data->dev_private;
1708         struct hns3_hw *hw = &hns->hw;
1709         int ret;
1710
1711         PMD_INIT_FUNC_TRACE();
1712
1713         /* Get hardware io base address from pcie BAR2 IO space */
1714         hw->io_base = pci_dev->mem_resource[2].addr;
1715
1716         /* Firmware command queue initialize */
1717         ret = hns3_cmd_init_queue(hw);
1718         if (ret) {
1719                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1720                 goto err_cmd_init_queue;
1721         }
1722
1723         /* Firmware command initialize */
1724         ret = hns3_cmd_init(hw);
1725         if (ret) {
1726                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1727                 goto err_cmd_init;
1728         }
1729
1730         hns3_tx_push_init(eth_dev);
1731
1732         /* Get VF resource */
1733         ret = hns3_query_vf_resource(hw);
1734         if (ret)
1735                 goto err_cmd_init;
1736
1737         rte_spinlock_init(&hw->mbx_resp.lock);
1738
1739         hns3vf_clear_event_cause(hw, 0);
1740
1741         ret = rte_intr_callback_register(pci_dev->intr_handle,
1742                                          hns3vf_interrupt_handler, eth_dev);
1743         if (ret) {
1744                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1745                 goto err_intr_callback_register;
1746         }
1747
1748         /* Enable interrupt */
1749         rte_intr_enable(pci_dev->intr_handle);
1750         hns3vf_enable_irq0(hw);
1751
1752         /* Get configuration from PF */
1753         ret = hns3vf_get_configuration(hw);
1754         if (ret) {
1755                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1756                 goto err_get_config;
1757         }
1758
1759         ret = hns3_tqp_stats_init(hw);
1760         if (ret)
1761                 goto err_get_config;
1762
1763         /* Hardware statistics of imissed registers cleared. */
1764         ret = hns3_update_imissed_stats(hw, true);
1765         if (ret) {
1766                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1767                 goto err_set_tc_queue;
1768         }
1769
1770         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1771         if (ret) {
1772                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1773                 goto err_set_tc_queue;
1774         }
1775
1776         ret = hns3vf_clear_vport_list(hw);
1777         if (ret) {
1778                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1779                 goto err_set_tc_queue;
1780         }
1781
1782         ret = hns3vf_init_hardware(hns);
1783         if (ret)
1784                 goto err_set_tc_queue;
1785
1786         hns3_rss_set_default_args(hw);
1787
1788         ret = hns3vf_set_alive(hw, true);
1789         if (ret) {
1790                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1791                 goto err_set_tc_queue;
1792         }
1793
1794         return 0;
1795
1796 err_set_tc_queue:
1797         hns3_tqp_stats_uninit(hw);
1798
1799 err_get_config:
1800         hns3vf_disable_irq0(hw);
1801         rte_intr_disable(pci_dev->intr_handle);
1802         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1803                              eth_dev);
1804 err_intr_callback_register:
1805 err_cmd_init:
1806         hns3_cmd_uninit(hw);
1807         hns3_cmd_destroy_queue(hw);
1808 err_cmd_init_queue:
1809         hw->io_base = NULL;
1810
1811         return ret;
1812 }
1813
1814 static void
1815 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1816 {
1817         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1818         struct hns3_adapter *hns = eth_dev->data->dev_private;
1819         struct hns3_hw *hw = &hns->hw;
1820
1821         PMD_INIT_FUNC_TRACE();
1822
1823         hns3_rss_uninit(hns);
1824         (void)hns3_config_gro(hw, false);
1825         (void)hns3vf_set_alive(hw, false);
1826         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1827         hns3_flow_uninit(eth_dev);
1828         hns3_tqp_stats_uninit(hw);
1829         hns3vf_disable_irq0(hw);
1830         rte_intr_disable(pci_dev->intr_handle);
1831         hns3_intr_unregister(pci_dev->intr_handle, hns3vf_interrupt_handler,
1832                              eth_dev);
1833         hns3_cmd_uninit(hw);
1834         hns3_cmd_destroy_queue(hw);
1835         hw->io_base = NULL;
1836 }
1837
1838 static int
1839 hns3vf_do_stop(struct hns3_adapter *hns)
1840 {
1841         struct hns3_hw *hw = &hns->hw;
1842         int ret;
1843
1844         hw->mac.link_status = RTE_ETH_LINK_DOWN;
1845
1846         /*
1847          * The "hns3vf_do_stop" function will also be called by .stop_service to
1848          * prepare reset. At the time of global or IMP reset, the command cannot
1849          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
1850          * accessed during the reset process. So the mbuf can not be released
1851          * during reset and is required to be released after the reset is
1852          * completed.
1853          */
1854         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
1855                 hns3_dev_release_mbufs(hns);
1856
1857         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
1858                 hns3_configure_all_mac_addr(hns, true);
1859                 ret = hns3_reset_all_tqps(hns);
1860                 if (ret) {
1861                         hns3_err(hw, "failed to reset all queues ret = %d",
1862                                  ret);
1863                         return ret;
1864                 }
1865         }
1866         return 0;
1867 }
1868
1869 static void
1870 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1871 {
1872         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1875         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1876         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1877         uint16_t q_id;
1878
1879         if (dev->data->dev_conf.intr_conf.rxq == 0)
1880                 return;
1881
1882         /* unmap the ring with vector */
1883         if (rte_intr_allow_others(intr_handle)) {
1884                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1885                 base = RTE_INTR_VEC_RXTX_OFFSET;
1886         }
1887         if (rte_intr_dp_is_en(intr_handle)) {
1888                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1889                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1890                                                            HNS3_RING_TYPE_RX,
1891                                                            q_id);
1892                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
1893                             - 1)
1894                                 vec++;
1895                 }
1896         }
1897         /* Clean datapath event and queue/vec mapping */
1898         rte_intr_efd_disable(intr_handle);
1899
1900         /* Cleanup vector list */
1901         rte_intr_vec_list_free(intr_handle);
1902 }
1903
1904 static int
1905 hns3vf_dev_stop(struct rte_eth_dev *dev)
1906 {
1907         struct hns3_adapter *hns = dev->data->dev_private;
1908         struct hns3_hw *hw = &hns->hw;
1909
1910         PMD_INIT_FUNC_TRACE();
1911         dev->data->dev_started = 0;
1912
1913         hw->adapter_state = HNS3_NIC_STOPPING;
1914         hns3_set_rxtx_function(dev);
1915         rte_wmb();
1916         /* Disable datapath on secondary process. */
1917         hns3_mp_req_stop_rxtx(dev);
1918         /* Prevent crashes when queues are still in use. */
1919         rte_delay_ms(hw->cfg_max_queues);
1920
1921         rte_spinlock_lock(&hw->lock);
1922         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1923                 hns3_stop_tqps(hw);
1924                 hns3vf_do_stop(hns);
1925                 hns3vf_unmap_rx_interrupt(dev);
1926                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1927         }
1928         hns3_rx_scattered_reset(dev);
1929         hns3vf_stop_poll_job(dev);
1930         hns3_stop_report_lse(dev);
1931         rte_spinlock_unlock(&hw->lock);
1932
1933         return 0;
1934 }
1935
1936 static int
1937 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1938 {
1939         struct hns3_adapter *hns = eth_dev->data->dev_private;
1940         struct hns3_hw *hw = &hns->hw;
1941         int ret = 0;
1942
1943         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1944                 return 0;
1945
1946         if (hw->adapter_state == HNS3_NIC_STARTED)
1947                 ret = hns3vf_dev_stop(eth_dev);
1948
1949         hw->adapter_state = HNS3_NIC_CLOSING;
1950         hns3_reset_abort(hns);
1951         hw->adapter_state = HNS3_NIC_CLOSED;
1952         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1953         hns3_configure_all_mc_mac_addr(hns, true);
1954         hns3vf_remove_all_vlan_table(hns);
1955         hns3vf_uninit_vf(eth_dev);
1956         hns3_free_all_queues(eth_dev);
1957         rte_free(hw->reset.wait_data);
1958         hns3_mp_uninit_primary();
1959         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
1960
1961         return ret;
1962 }
1963
1964 static int
1965 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1966                       size_t fw_size)
1967 {
1968         struct hns3_adapter *hns = eth_dev->data->dev_private;
1969         struct hns3_hw *hw = &hns->hw;
1970         uint32_t version = hw->fw_version;
1971         int ret;
1972
1973         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1974                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1975                                       HNS3_FW_VERSION_BYTE3_S),
1976                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1977                                       HNS3_FW_VERSION_BYTE2_S),
1978                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1979                                       HNS3_FW_VERSION_BYTE1_S),
1980                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1981                                       HNS3_FW_VERSION_BYTE0_S));
1982         if (ret < 0)
1983                 return -EINVAL;
1984
1985         ret += 1; /* add the size of '\0' */
1986         if (fw_size < (size_t)ret)
1987                 return ret;
1988         else
1989                 return 0;
1990 }
1991
1992 static int
1993 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1994                        __rte_unused int wait_to_complete)
1995 {
1996         struct hns3_adapter *hns = eth_dev->data->dev_private;
1997         struct hns3_hw *hw = &hns->hw;
1998         struct hns3_mac *mac = &hw->mac;
1999         struct rte_eth_link new_link;
2000
2001         memset(&new_link, 0, sizeof(new_link));
2002         switch (mac->link_speed) {
2003         case RTE_ETH_SPEED_NUM_10M:
2004         case RTE_ETH_SPEED_NUM_100M:
2005         case RTE_ETH_SPEED_NUM_1G:
2006         case RTE_ETH_SPEED_NUM_10G:
2007         case RTE_ETH_SPEED_NUM_25G:
2008         case RTE_ETH_SPEED_NUM_40G:
2009         case RTE_ETH_SPEED_NUM_50G:
2010         case RTE_ETH_SPEED_NUM_100G:
2011         case RTE_ETH_SPEED_NUM_200G:
2012                 if (mac->link_status)
2013                         new_link.link_speed = mac->link_speed;
2014                 break;
2015         default:
2016                 if (mac->link_status)
2017                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2018                 break;
2019         }
2020
2021         if (!mac->link_status)
2022                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2023
2024         new_link.link_duplex = mac->link_duplex;
2025         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2026         new_link.link_autoneg =
2027             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2028
2029         return rte_eth_linkstatus_set(eth_dev, &new_link);
2030 }
2031
2032 static int
2033 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2034 {
2035         struct hns3_hw *hw = &hns->hw;
2036         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2037         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2038         int ret;
2039
2040         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2041         if (ret)
2042                 return ret;
2043
2044         hns3_enable_rxd_adv_layout(hw);
2045
2046         ret = hns3_init_queues(hns, reset_queue);
2047         if (ret)
2048                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2049
2050         return ret;
2051 }
2052
2053 static int
2054 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2055 {
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2058         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2060         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2061         uint32_t intr_vector;
2062         uint16_t q_id;
2063         int ret;
2064
2065         /*
2066          * hns3 needs a separate interrupt to be used as event interrupt which
2067          * could not be shared with task queue pair, so KERNEL drivers need
2068          * support multiple interrupt vectors.
2069          */
2070         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2071             !rte_intr_cap_multiple(intr_handle))
2072                 return 0;
2073
2074         rte_intr_disable(intr_handle);
2075         intr_vector = hw->used_rx_queues;
2076         /* It creates event fd for each intr vector when MSIX is used */
2077         if (rte_intr_efd_enable(intr_handle, intr_vector))
2078                 return -EINVAL;
2079
2080         /* Allocate vector list */
2081         if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2082                                     hw->used_rx_queues)) {
2083                 hns3_err(hw, "Failed to allocate %u rx_queues"
2084                          " intr_vec", hw->used_rx_queues);
2085                 ret = -ENOMEM;
2086                 goto vf_alloc_intr_vec_error;
2087         }
2088
2089         if (rte_intr_allow_others(intr_handle)) {
2090                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2091                 base = RTE_INTR_VEC_RXTX_OFFSET;
2092         }
2093
2094         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2095                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2096                                                    HNS3_RING_TYPE_RX, q_id);
2097                 if (ret)
2098                         goto vf_bind_vector_error;
2099
2100                 if (rte_intr_vec_list_index_set(intr_handle, q_id, vec))
2101                         goto vf_bind_vector_error;
2102
2103                 /*
2104                  * If there are not enough efds (e.g. not enough interrupt),
2105                  * remaining queues will be bond to the last interrupt.
2106                  */
2107                 if (vec < base + rte_intr_nb_efd_get(intr_handle) - 1)
2108                         vec++;
2109         }
2110         rte_intr_enable(intr_handle);
2111         return 0;
2112
2113 vf_bind_vector_error:
2114         rte_intr_vec_list_free(intr_handle);
2115 vf_alloc_intr_vec_error:
2116         rte_intr_efd_disable(intr_handle);
2117         return ret;
2118 }
2119
2120 static int
2121 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2122 {
2123         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2124         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2126         uint16_t q_id;
2127         int ret;
2128
2129         if (dev->data->dev_conf.intr_conf.rxq == 0)
2130                 return 0;
2131
2132         if (rte_intr_dp_is_en(intr_handle)) {
2133                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2134                         ret = hns3vf_bind_ring_with_vector(hw,
2135                                 rte_intr_vec_list_index_get(intr_handle,
2136                                                                    q_id),
2137                                 true, HNS3_RING_TYPE_RX, q_id);
2138                         if (ret)
2139                                 return ret;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static void
2147 hns3vf_restore_filter(struct rte_eth_dev *dev)
2148 {
2149         hns3_restore_rss_filter(dev);
2150 }
2151
2152 static int
2153 hns3vf_dev_start(struct rte_eth_dev *dev)
2154 {
2155         struct hns3_adapter *hns = dev->data->dev_private;
2156         struct hns3_hw *hw = &hns->hw;
2157         int ret;
2158
2159         PMD_INIT_FUNC_TRACE();
2160         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2161                 return -EBUSY;
2162
2163         rte_spinlock_lock(&hw->lock);
2164         hw->adapter_state = HNS3_NIC_STARTING;
2165         ret = hns3vf_do_start(hns, true);
2166         if (ret) {
2167                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2168                 rte_spinlock_unlock(&hw->lock);
2169                 return ret;
2170         }
2171         ret = hns3vf_map_rx_interrupt(dev);
2172         if (ret)
2173                 goto map_rx_inter_err;
2174
2175         /*
2176          * There are three register used to control the status of a TQP
2177          * (contains a pair of Tx queue and Rx queue) in the new version network
2178          * engine. One is used to control the enabling of Tx queue, the other is
2179          * used to control the enabling of Rx queue, and the last is the master
2180          * switch used to control the enabling of the tqp. The Tx register and
2181          * TQP register must be enabled at the same time to enable a Tx queue.
2182          * The same applies to the Rx queue. For the older network enginem, this
2183          * function only refresh the enabled flag, and it is used to update the
2184          * status of queue in the dpdk framework.
2185          */
2186         ret = hns3_start_all_txqs(dev);
2187         if (ret)
2188                 goto map_rx_inter_err;
2189
2190         ret = hns3_start_all_rxqs(dev);
2191         if (ret)
2192                 goto start_all_rxqs_fail;
2193
2194         hw->adapter_state = HNS3_NIC_STARTED;
2195         rte_spinlock_unlock(&hw->lock);
2196
2197         hns3_rx_scattered_calc(dev);
2198         hns3_set_rxtx_function(dev);
2199         hns3_mp_req_start_rxtx(dev);
2200
2201         hns3vf_restore_filter(dev);
2202
2203         /* Enable interrupt of all rx queues before enabling queues */
2204         hns3_dev_all_rx_queue_intr_enable(hw, true);
2205         hns3_start_tqps(hw);
2206
2207         if (dev->data->dev_conf.intr_conf.lsc != 0)
2208                 hns3vf_dev_link_update(dev, 0);
2209         hns3vf_start_poll_job(dev);
2210
2211         return ret;
2212
2213 start_all_rxqs_fail:
2214         hns3_stop_all_txqs(dev);
2215 map_rx_inter_err:
2216         (void)hns3vf_do_stop(hns);
2217         hw->adapter_state = HNS3_NIC_CONFIGURED;
2218         rte_spinlock_unlock(&hw->lock);
2219
2220         return ret;
2221 }
2222
2223 static bool
2224 is_vf_reset_done(struct hns3_hw *hw)
2225 {
2226 #define HNS3_FUN_RST_ING_BITS \
2227         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2228          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2229          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2230          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2231
2232         uint32_t val;
2233
2234         if (hw->reset.level == HNS3_VF_RESET) {
2235                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2236                 if (val & HNS3_VF_RST_ING_BIT)
2237                         return false;
2238         } else {
2239                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2240                 if (val & HNS3_FUN_RST_ING_BITS)
2241                         return false;
2242         }
2243         return true;
2244 }
2245
2246 bool
2247 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2248 {
2249         struct hns3_hw *hw = &hns->hw;
2250         enum hns3_reset_level reset;
2251
2252         /*
2253          * According to the protocol of PCIe, FLR to a PF device resets the PF
2254          * state as well as the SR-IOV extended capability including VF Enable
2255          * which means that VFs no longer exist.
2256          *
2257          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2258          * is in FLR stage, the register state of VF device is not reliable,
2259          * so register states detection can not be carried out. In this case,
2260          * we just ignore the register states and return false to indicate that
2261          * there are no other reset states that need to be processed by driver.
2262          */
2263         if (hw->reset.level == HNS3_VF_FULL_RESET)
2264                 return false;
2265
2266         /* Check the registers to confirm whether there is reset pending */
2267         hns3vf_check_event_cause(hns, NULL);
2268         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2269         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2270             hw->reset.level < reset) {
2271                 hns3_warn(hw, "High level reset %d is pending", reset);
2272                 return true;
2273         }
2274         return false;
2275 }
2276
2277 static int
2278 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2279 {
2280         struct hns3_hw *hw = &hns->hw;
2281         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2282         struct timeval tv;
2283
2284         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2285                 /*
2286                  * After vf reset is ready, the PF may not have completed
2287                  * the reset processing. The vf sending mbox to PF may fail
2288                  * during the pf reset, so it is better to add extra delay.
2289                  */
2290                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2291                     hw->reset.level == HNS3_FLR_RESET)
2292                         return 0;
2293                 /* Reset retry process, no need to add extra delay. */
2294                 if (hw->reset.attempts)
2295                         return 0;
2296                 if (wait_data->check_completion == NULL)
2297                         return 0;
2298
2299                 wait_data->check_completion = NULL;
2300                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2301                 wait_data->count = 1;
2302                 wait_data->result = HNS3_WAIT_REQUEST;
2303                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2304                                   wait_data);
2305                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2306                 return -EAGAIN;
2307         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2308                 hns3_clock_gettime(&tv);
2309                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2310                           tv.tv_sec, tv.tv_usec);
2311                 return -ETIME;
2312         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2313                 return -EAGAIN;
2314
2315         wait_data->hns = hns;
2316         wait_data->check_completion = is_vf_reset_done;
2317         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2318                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2319         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2320         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2321         wait_data->result = HNS3_WAIT_REQUEST;
2322         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2323         return -EAGAIN;
2324 }
2325
2326 static int
2327 hns3vf_prepare_reset(struct hns3_adapter *hns)
2328 {
2329         struct hns3_hw *hw = &hns->hw;
2330         int ret;
2331
2332         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2333                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2334                                         0, true, NULL, 0);
2335                 if (ret)
2336                         return ret;
2337         }
2338         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2339
2340         return 0;
2341 }
2342
2343 static int
2344 hns3vf_stop_service(struct hns3_adapter *hns)
2345 {
2346         struct hns3_hw *hw = &hns->hw;
2347         struct rte_eth_dev *eth_dev;
2348
2349         eth_dev = &rte_eth_devices[hw->data->port_id];
2350         if (hw->adapter_state == HNS3_NIC_STARTED) {
2351                 /*
2352                  * Make sure call update link status before hns3vf_stop_poll_job
2353                  * because update link status depend on polling job exist.
2354                  */
2355                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2356                                           hw->mac.link_duplex);
2357                 hns3vf_stop_poll_job(eth_dev);
2358         }
2359         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2360
2361         hns3_set_rxtx_function(eth_dev);
2362         rte_wmb();
2363         /* Disable datapath on secondary process. */
2364         hns3_mp_req_stop_rxtx(eth_dev);
2365         rte_delay_ms(hw->cfg_max_queues);
2366
2367         rte_spinlock_lock(&hw->lock);
2368         if (hw->adapter_state == HNS3_NIC_STARTED ||
2369             hw->adapter_state == HNS3_NIC_STOPPING) {
2370                 hns3_enable_all_queues(hw, false);
2371                 hns3vf_do_stop(hns);
2372                 hw->reset.mbuf_deferred_free = true;
2373         } else
2374                 hw->reset.mbuf_deferred_free = false;
2375
2376         /*
2377          * It is cumbersome for hardware to pick-and-choose entries for deletion
2378          * from table space. Hence, for function reset software intervention is
2379          * required to delete the entries.
2380          */
2381         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2382                 hns3_configure_all_mc_mac_addr(hns, true);
2383         rte_spinlock_unlock(&hw->lock);
2384
2385         return 0;
2386 }
2387
2388 static int
2389 hns3vf_start_service(struct hns3_adapter *hns)
2390 {
2391         struct hns3_hw *hw = &hns->hw;
2392         struct rte_eth_dev *eth_dev;
2393
2394         eth_dev = &rte_eth_devices[hw->data->port_id];
2395         hns3_set_rxtx_function(eth_dev);
2396         hns3_mp_req_start_rxtx(eth_dev);
2397         if (hw->adapter_state == HNS3_NIC_STARTED) {
2398                 hns3vf_start_poll_job(eth_dev);
2399
2400                 /* Enable interrupt of all rx queues before enabling queues */
2401                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2402                 /*
2403                  * Enable state of each rxq and txq will be recovered after
2404                  * reset, so we need to restore them before enable all tqps;
2405                  */
2406                 hns3_restore_tqp_enable_state(hw);
2407                 /*
2408                  * When finished the initialization, enable queues to receive
2409                  * and transmit packets.
2410                  */
2411                 hns3_enable_all_queues(hw, true);
2412         }
2413
2414         return 0;
2415 }
2416
2417 static int
2418 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2419 {
2420         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2421         struct rte_ether_addr *hw_mac;
2422         int ret;
2423
2424         /*
2425          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2426          * on the host by "ip link set ..." command. If the hns3 PF kernel
2427          * ethdev driver sets the MAC address for VF device after the
2428          * initialization of the related VF device, the PF driver will notify
2429          * VF driver to reset VF device to make the new MAC address effective
2430          * immediately. The hns3 VF PMD driver should check whether the MAC
2431          * address has been changed by the PF kernel ethdev driver, if changed
2432          * VF driver should configure hardware using the new MAC address in the
2433          * recovering hardware configuration stage of the reset process.
2434          */
2435         ret = hns3vf_get_host_mac_addr(hw);
2436         if (ret)
2437                 return ret;
2438
2439         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2440         ret = rte_is_zero_ether_addr(hw_mac);
2441         if (ret) {
2442                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2443         } else {
2444                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2445                 if (!ret) {
2446                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2447                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2448                                               &hw->data->mac_addrs[0]);
2449                         hns3_warn(hw, "Default MAC address has been changed to:"
2450                                   " %s by the host PF kernel ethdev driver",
2451                                   mac_str);
2452                 }
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 hns3vf_restore_conf(struct hns3_adapter *hns)
2460 {
2461         struct hns3_hw *hw = &hns->hw;
2462         int ret;
2463
2464         ret = hns3vf_check_default_mac_change(hw);
2465         if (ret)
2466                 return ret;
2467
2468         ret = hns3_configure_all_mac_addr(hns, false);
2469         if (ret)
2470                 return ret;
2471
2472         ret = hns3_configure_all_mc_mac_addr(hns, false);
2473         if (ret)
2474                 goto err_mc_mac;
2475
2476         ret = hns3vf_restore_promisc(hns);
2477         if (ret)
2478                 goto err_vlan_table;
2479
2480         ret = hns3vf_restore_vlan_conf(hns);
2481         if (ret)
2482                 goto err_vlan_table;
2483
2484         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2485         if (ret)
2486                 goto err_vlan_table;
2487
2488         ret = hns3vf_restore_rx_interrupt(hw);
2489         if (ret)
2490                 goto err_vlan_table;
2491
2492         ret = hns3_restore_gro_conf(hw);
2493         if (ret)
2494                 goto err_vlan_table;
2495
2496         if (hw->adapter_state == HNS3_NIC_STARTED) {
2497                 ret = hns3vf_do_start(hns, false);
2498                 if (ret)
2499                         goto err_vlan_table;
2500                 hns3_info(hw, "hns3vf dev restart successful!");
2501         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2502                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2503
2504         ret = hns3vf_set_alive(hw, true);
2505         if (ret) {
2506                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2507                 goto err_vlan_table;
2508         }
2509
2510         return 0;
2511
2512 err_vlan_table:
2513         hns3_configure_all_mc_mac_addr(hns, true);
2514 err_mc_mac:
2515         hns3_configure_all_mac_addr(hns, true);
2516         return ret;
2517 }
2518
2519 static enum hns3_reset_level
2520 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2521 {
2522         enum hns3_reset_level reset_level;
2523
2524         /* return the highest priority reset level amongst all */
2525         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2526                 reset_level = HNS3_VF_RESET;
2527         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2528                 reset_level = HNS3_VF_FULL_RESET;
2529         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2530                 reset_level = HNS3_VF_PF_FUNC_RESET;
2531         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2532                 reset_level = HNS3_VF_FUNC_RESET;
2533         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2534                 reset_level = HNS3_FLR_RESET;
2535         else
2536                 reset_level = HNS3_NONE_RESET;
2537
2538         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2539                 return HNS3_NONE_RESET;
2540
2541         return reset_level;
2542 }
2543
2544 static void
2545 hns3vf_reset_service(void *param)
2546 {
2547         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2548         struct hns3_hw *hw = &hns->hw;
2549         enum hns3_reset_level reset_level;
2550         struct timeval tv_delta;
2551         struct timeval tv_start;
2552         struct timeval tv;
2553         uint64_t msec;
2554
2555         /*
2556          * The interrupt is not triggered within the delay time.
2557          * The interrupt may have been lost. It is necessary to handle
2558          * the interrupt to recover from the error.
2559          */
2560         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2561                             SCHEDULE_DEFERRED) {
2562                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2563                                  __ATOMIC_RELAXED);
2564                 hns3_err(hw, "Handling interrupts in delayed tasks");
2565                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2566                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2567                 if (reset_level == HNS3_NONE_RESET) {
2568                         hns3_err(hw, "No reset level is set, try global reset");
2569                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2570                 }
2571         }
2572         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2573
2574         /*
2575          * Hardware reset has been notified, we now have to poll & check if
2576          * hardware has actually completed the reset sequence.
2577          */
2578         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2579         if (reset_level != HNS3_NONE_RESET) {
2580                 hns3_clock_gettime(&tv_start);
2581                 hns3_reset_process(hns, reset_level);
2582                 hns3_clock_gettime(&tv);
2583                 timersub(&tv, &tv_start, &tv_delta);
2584                 msec = hns3_clock_calctime_ms(&tv_delta);
2585                 if (msec > HNS3_RESET_PROCESS_MS)
2586                         hns3_err(hw, "%d handle long time delta %" PRIu64
2587                                  " ms time=%ld.%.6ld",
2588                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2589         }
2590 }
2591
2592 static int
2593 hns3vf_reinit_dev(struct hns3_adapter *hns)
2594 {
2595         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2596         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2597         struct hns3_hw *hw = &hns->hw;
2598         int ret;
2599
2600         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2601                 rte_intr_disable(pci_dev->intr_handle);
2602                 ret = hns3vf_set_bus_master(pci_dev, true);
2603                 if (ret < 0) {
2604                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2605                         return ret;
2606                 }
2607         }
2608
2609         /* Firmware command initialize */
2610         ret = hns3_cmd_init(hw);
2611         if (ret) {
2612                 hns3_err(hw, "Failed to init cmd: %d", ret);
2613                 return ret;
2614         }
2615
2616         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2617                 /*
2618                  * UIO enables msix by writing the pcie configuration space
2619                  * vfio_pci enables msix in rte_intr_enable.
2620                  */
2621                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2622                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2623                         if (hns3vf_enable_msix(pci_dev, true))
2624                                 hns3_err(hw, "Failed to enable msix");
2625                 }
2626
2627                 rte_intr_enable(pci_dev->intr_handle);
2628         }
2629
2630         ret = hns3_reset_all_tqps(hns);
2631         if (ret) {
2632                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2633                 return ret;
2634         }
2635
2636         ret = hns3vf_init_hardware(hns);
2637         if (ret) {
2638                 hns3_err(hw, "Failed to init hardware: %d", ret);
2639                 return ret;
2640         }
2641
2642         return 0;
2643 }
2644
2645 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2646         .dev_configure      = hns3vf_dev_configure,
2647         .dev_start          = hns3vf_dev_start,
2648         .dev_stop           = hns3vf_dev_stop,
2649         .dev_close          = hns3vf_dev_close,
2650         .mtu_set            = hns3vf_dev_mtu_set,
2651         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2652         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2653         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2654         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2655         .stats_get          = hns3_stats_get,
2656         .stats_reset        = hns3_stats_reset,
2657         .xstats_get         = hns3_dev_xstats_get,
2658         .xstats_get_names   = hns3_dev_xstats_get_names,
2659         .xstats_reset       = hns3_dev_xstats_reset,
2660         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2661         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2662         .dev_infos_get      = hns3vf_dev_infos_get,
2663         .fw_version_get     = hns3vf_fw_version_get,
2664         .rx_queue_setup     = hns3_rx_queue_setup,
2665         .tx_queue_setup     = hns3_tx_queue_setup,
2666         .rx_queue_release   = hns3_dev_rx_queue_release,
2667         .tx_queue_release   = hns3_dev_tx_queue_release,
2668         .rx_queue_start     = hns3_dev_rx_queue_start,
2669         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2670         .tx_queue_start     = hns3_dev_tx_queue_start,
2671         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2672         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2673         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2674         .rxq_info_get       = hns3_rxq_info_get,
2675         .txq_info_get       = hns3_txq_info_get,
2676         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2677         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2678         .mac_addr_add       = hns3_add_mac_addr,
2679         .mac_addr_remove    = hns3_remove_mac_addr,
2680         .mac_addr_set       = hns3vf_set_default_mac_addr,
2681         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2682         .link_update        = hns3vf_dev_link_update,
2683         .rss_hash_update    = hns3_dev_rss_hash_update,
2684         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2685         .reta_update        = hns3_dev_rss_reta_update,
2686         .reta_query         = hns3_dev_rss_reta_query,
2687         .flow_ops_get       = hns3_dev_flow_ops_get,
2688         .vlan_filter_set    = hns3vf_vlan_filter_set,
2689         .vlan_offload_set   = hns3vf_vlan_offload_set,
2690         .get_reg            = hns3_get_regs,
2691         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2692         .tx_done_cleanup    = hns3_tx_done_cleanup,
2693 };
2694
2695 static const struct hns3_reset_ops hns3vf_reset_ops = {
2696         .reset_service       = hns3vf_reset_service,
2697         .stop_service        = hns3vf_stop_service,
2698         .prepare_reset       = hns3vf_prepare_reset,
2699         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2700         .reinit_dev          = hns3vf_reinit_dev,
2701         .restore_conf        = hns3vf_restore_conf,
2702         .start_service       = hns3vf_start_service,
2703 };
2704
2705 static void
2706 hns3vf_init_hw_ops(struct hns3_hw *hw)
2707 {
2708         hw->ops.add_mc_mac_addr = hns3vf_add_mc_mac_addr;
2709         hw->ops.del_mc_mac_addr = hns3vf_remove_mc_mac_addr;
2710         hw->ops.add_uc_mac_addr = hns3vf_add_uc_mac_addr;
2711         hw->ops.del_uc_mac_addr = hns3vf_remove_uc_mac_addr;
2712 }
2713
2714 static int
2715 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2716 {
2717         struct hns3_adapter *hns = eth_dev->data->dev_private;
2718         struct hns3_hw *hw = &hns->hw;
2719         int ret;
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         hns3_flow_init(eth_dev);
2724
2725         hns3_set_rxtx_function(eth_dev);
2726         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2727         eth_dev->rx_queue_count = hns3_rx_queue_count;
2728         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2729                 ret = hns3_mp_init_secondary();
2730                 if (ret) {
2731                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2732                                           "process, ret = %d", ret);
2733                         goto err_mp_init_secondary;
2734                 }
2735                 hw->secondary_cnt++;
2736                 hns3_tx_push_init(eth_dev);
2737                 return 0;
2738         }
2739
2740         ret = hns3_mp_init_primary();
2741         if (ret) {
2742                 PMD_INIT_LOG(ERR,
2743                              "Failed to init for primary process, ret = %d",
2744                              ret);
2745                 goto err_mp_init_primary;
2746         }
2747
2748         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2749         hns->is_vf = true;
2750         hw->data = eth_dev->data;
2751         hns3_parse_devargs(eth_dev);
2752
2753         ret = hns3_reset_init(hw);
2754         if (ret)
2755                 goto err_init_reset;
2756         hw->reset.ops = &hns3vf_reset_ops;
2757
2758         hns3vf_init_hw_ops(hw);
2759         ret = hns3vf_init_vf(eth_dev);
2760         if (ret) {
2761                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2762                 goto err_init_vf;
2763         }
2764
2765         /* Allocate memory for storing MAC addresses */
2766         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2767                                                sizeof(struct rte_ether_addr) *
2768                                                HNS3_VF_UC_MACADDR_NUM, 0);
2769         if (eth_dev->data->mac_addrs == NULL) {
2770                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2771                              "to store MAC addresses",
2772                              sizeof(struct rte_ether_addr) *
2773                              HNS3_VF_UC_MACADDR_NUM);
2774                 ret = -ENOMEM;
2775                 goto err_rte_zmalloc;
2776         }
2777
2778         /*
2779          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2780          * on the host by "ip link set ..." command. To avoid some incorrect
2781          * scenes, for example, hns3 VF PMD driver fails to receive and send
2782          * packets after user configure the MAC address by using the
2783          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2784          * address strategy as the hns3 kernel ethdev driver in the
2785          * initialization. If user configure a MAC address by the ip command
2786          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2787          * start with a random MAC address in the initialization.
2788          */
2789         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2790                 rte_eth_random_addr(hw->mac.mac_addr);
2791         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2792                             &eth_dev->data->mac_addrs[0]);
2793
2794         hw->adapter_state = HNS3_NIC_INITIALIZED;
2795
2796         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2797                             SCHEDULE_PENDING) {
2798                 hns3_err(hw, "Reschedule reset service after dev_init");
2799                 hns3_schedule_reset(hns);
2800         } else {
2801                 /* IMP will wait ready flag before reset */
2802                 hns3_notify_reset_ready(hw, false);
2803         }
2804         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2805                           eth_dev);
2806         return 0;
2807
2808 err_rte_zmalloc:
2809         hns3vf_uninit_vf(eth_dev);
2810
2811 err_init_vf:
2812         rte_free(hw->reset.wait_data);
2813
2814 err_init_reset:
2815         hns3_mp_uninit_primary();
2816
2817 err_mp_init_primary:
2818 err_mp_init_secondary:
2819         eth_dev->dev_ops = NULL;
2820         eth_dev->rx_pkt_burst = NULL;
2821         eth_dev->rx_descriptor_status = NULL;
2822         eth_dev->tx_pkt_burst = NULL;
2823         eth_dev->tx_pkt_prepare = NULL;
2824         eth_dev->tx_descriptor_status = NULL;
2825
2826         return ret;
2827 }
2828
2829 static int
2830 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2831 {
2832         struct hns3_adapter *hns = eth_dev->data->dev_private;
2833         struct hns3_hw *hw = &hns->hw;
2834
2835         PMD_INIT_FUNC_TRACE();
2836
2837         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2838                 return 0;
2839
2840         if (hw->adapter_state < HNS3_NIC_CLOSING)
2841                 hns3vf_dev_close(eth_dev);
2842
2843         hw->adapter_state = HNS3_NIC_REMOVED;
2844         return 0;
2845 }
2846
2847 static int
2848 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2849                      struct rte_pci_device *pci_dev)
2850 {
2851         return rte_eth_dev_pci_generic_probe(pci_dev,
2852                                              sizeof(struct hns3_adapter),
2853                                              hns3vf_dev_init);
2854 }
2855
2856 static int
2857 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2858 {
2859         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2860 }
2861
2862 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2863         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2864         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2865         { .vendor_id = 0, }, /* sentinel */
2866 };
2867
2868 static struct rte_pci_driver rte_hns3vf_pmd = {
2869         .id_table = pci_id_hns3vf_map,
2870         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2871         .probe = eth_hns3vf_pci_probe,
2872         .remove = eth_hns3vf_pci_remove,
2873 };
2874
2875 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2876 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2877 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
2878 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
2879                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
2880                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
2881                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
2882                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");