drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint16_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid.
 708          */
 709         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 710         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 711                 vec = vec - 1; /* the last interrupt is reserved */
 712         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 713         for (i = 0; i < hw->intr_tqps_num; i++) {
 714                 /*
 715                  * Set gap limiter/rate limiter/quanity limiter algorithm
 716                  * configuration for interrupt coalesce of queue's interrupt.
 717                  */
 718                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 719                                        HNS3_TQP_INTR_GL_DEFAULT);
 720                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 721                                        HNS3_TQP_INTR_GL_DEFAULT);
 722                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 723                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 724
 725                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 726                                                    HNS3_RING_TYPE_TX, i);
 727                 if (ret) {
 728                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 729                                           "vector: %d, ret=%d", i, vec, ret);
 730                         return ret;
 731                 }
 732
 733                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 734                                                    HNS3_RING_TYPE_RX, i);
 735                 if (ret) {
 736                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 737                                           "vector: %d, ret=%d", i, vec, ret);
 738                         return ret;
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744
 745 static int
 746 hns3vf_dev_configure(struct rte_eth_dev *dev)
 747 {
 748         struct hns3_adapter *hns = dev->data->dev_private;
 749         struct hns3_hw *hw = &hns->hw;
 750         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 751         struct rte_eth_conf *conf = &dev->data->dev_conf;
 752         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 753         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 754         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 755         struct rte_eth_rss_conf rss_conf;
 756         uint16_t mtu;
 757         bool gro_en;
 758         int ret;
 759
 760         /*
 761          * Hardware does not support individually enable/disable/reset the Tx or
 762          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 763          * and Rx queues at the same time. When the numbers of Tx queues
 764          * allocated by upper applications are not equal to the numbers of Rx
 765          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 766          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 767          * these fake queues are imperceptible, and can not be used by upper
 768          * applications.
 769          */
 770         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 771         if (ret) {
 772                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 773                 return ret;
 774         }
 775
 776         hw->adapter_state = HNS3_NIC_CONFIGURING;
 777         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 778                 hns3_err(hw, "setting link speed/duplex not supported");
 779                 ret = -EINVAL;
 780                 goto cfg_err;
 781         }
 782
 783         /* When RSS is not configured, redirect the packet queue 0 */
 784         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 785                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 786                 rss_conf = conf->rx_adv_conf.rss_conf;
 787                 if (rss_conf.rss_key == NULL) {
 788                         rss_conf.rss_key = rss_cfg->key;
 789                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 790                 }
 791
 792                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 793                 if (ret)
 794                         goto cfg_err;
 795         }
 796
 797         /*
 798          * If jumbo frames are enabled, MTU needs to be refreshed
 799          * according to the maximum RX packet length.
 800          */
 801         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 802                 /*
 803                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 804                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 805                  * can safely assign to "uint16_t" type variable.
 806                  */
 807                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 808                 ret = hns3vf_dev_mtu_set(dev, mtu);
 809                 if (ret)
 810                         goto cfg_err;
 811                 dev->data->mtu = mtu;
 812         }
 813
 814         ret = hns3vf_dev_configure_vlan(dev);
 815         if (ret)
 816                 goto cfg_err;
 817
 818         /* config hardware GRO */
 819         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 820         ret = hns3_config_gro(hw, gro_en);
 821         if (ret)
 822                 goto cfg_err;
 823
 824         hns->rx_simple_allowed = true;
 825         hns->rx_vec_allowed = true;
 826         hns->tx_simple_allowed = true;
 827         hns->tx_vec_allowed = true;
 828
 829         hns3_init_rx_ptype_tble(dev);
 830
 831         hw->adapter_state = HNS3_NIC_CONFIGURED;
 832         return 0;
 833
 834 cfg_err:
 835         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 836         hw->adapter_state = HNS3_NIC_INITIALIZED;
 837
 838         return ret;
 839 }
 840
 841 static int
 842 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 843 {
 844         int ret;
 845
 846         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 847                                 sizeof(mtu), true, NULL, 0);
 848         if (ret)
 849                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 850
 851         return ret;
 852 }
 853
 854 static int
 855 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 856 {
 857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 858         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 859         int ret;
 860
 861         /*
 862          * The hns3 PF/VF devices on the same port share the hardware MTU
 863          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 864          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 865          * driver, there is no need to stop the port for hns3 VF device, and the
 866          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 867          * PF's MTU.
 868          */
 869         if (rte_atomic16_read(&hw->reset.resetting)) {
 870                 hns3_err(hw, "Failed to set mtu during resetting");
 871                 return -EIO;
 872         }
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3vf_config_mtu(hw, mtu);
 876         if (ret) {
 877                 rte_spinlock_unlock(&hw->lock);
 878                 return ret;
 879         }
 880         if (frame_size > RTE_ETHER_MAX_LEN)
 881                 dev->data->dev_conf.rxmode.offloads |=
 882                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 883         else
 884                 dev->data->dev_conf.rxmode.offloads &=
 885                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 886         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 887         rte_spinlock_unlock(&hw->lock);
 888
 889         return 0;
 890 }
 891
 892 static int
 893 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 894 {
 895         struct hns3_adapter *hns = eth_dev->data->dev_private;
 896         struct hns3_hw *hw = &hns->hw;
 897         uint16_t q_num = hw->tqps_num;
 898
 899         /*
 900          * In interrupt mode, 'max_rx_queues' is set based on the number of
 901          * MSI-X interrupt resources of the hardware.
 902          */
 903         if (hw->data->dev_conf.intr_conf.rxq == 1)
 904                 q_num = hw->intr_tqps_num;
 905
 906         info->max_rx_queues = q_num;
 907         info->max_tx_queues = hw->tqps_num;
 908         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 909         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 910         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 911         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 912         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 913
 914         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 917                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 918                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 919                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 920                                  DEV_RX_OFFLOAD_SCATTER |
 921                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 922                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 923                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 924                                  DEV_RX_OFFLOAD_RSS_HASH |
 925                                  DEV_RX_OFFLOAD_TCP_LRO);
 926         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 927                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 928                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 929                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 930                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 931                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 932                                  DEV_TX_OFFLOAD_TCP_TSO |
 933                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 934                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 935                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 936                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 937                                  hns3_txvlan_cap_get(hw));
 938
 939         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 940                 .nb_max = HNS3_MAX_RING_DESC,
 941                 .nb_min = HNS3_MIN_RING_DESC,
 942                 .nb_align = HNS3_ALIGN_RING_DESC,
 943         };
 944
 945         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 946                 .nb_max = HNS3_MAX_RING_DESC,
 947                 .nb_min = HNS3_MIN_RING_DESC,
 948                 .nb_align = HNS3_ALIGN_RING_DESC,
 949                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 950                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 951         };
 952
 953         info->default_rxconf = (struct rte_eth_rxconf) {
 954                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 955                 /*
 956                  * If there are no available Rx buffer descriptors, incoming
 957                  * packets are always dropped by hardware based on hns3 network
 958                  * engine.
 959                  */
 960                 .rx_drop_en = 1,
 961                 .offloads = 0,
 962         };
 963         info->default_txconf = (struct rte_eth_txconf) {
 964                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 965                 .offloads = 0,
 966         };
 967
 968         info->vmdq_queue_num = 0;
 969
 970         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 971         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 972         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 973         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 974         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 975
 976         return 0;
 977 }
 978
 979 static void
 980 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 981 {
 982         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 983 }
 984
 985 static void
 986 hns3vf_disable_irq0(struct hns3_hw *hw)
 987 {
 988         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 989 }
 990
 991 static void
 992 hns3vf_enable_irq0(struct hns3_hw *hw)
 993 {
 994         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 995 }
 996
 997 static enum hns3vf_evt_cause
 998 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 999 {
1000         struct hns3_hw *hw = &hns->hw;
1001         enum hns3vf_evt_cause ret;
1002         uint32_t cmdq_stat_reg;
1003         uint32_t rst_ing_reg;
1004         uint32_t val;
1005
1006         /* Fetch the events from their corresponding regs */
1007         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1008
1009         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1010                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1011                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1012                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1013                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1014                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1015                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1016                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1017                 if (clearval) {
1018                         hw->reset.stats.global_cnt++;
1019                         hns3_warn(hw, "Global reset detected, clear reset status");
1020                 } else {
1021                         hns3_schedule_delayed_reset(hns);
1022                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1023                 }
1024
1025                 ret = HNS3VF_VECTOR0_EVENT_RST;
1026                 goto out;
1027         }
1028
1029         /* Check for vector0 mailbox(=CMDQ RX) event source */
1030         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1031                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1032                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1033                 goto out;
1034         }
1035
1036         val = 0;
1037         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1038 out:
1039         if (clearval)
1040                 *clearval = val;
1041         return ret;
1042 }
1043
1044 static void
1045 hns3vf_interrupt_handler(void *param)
1046 {
1047         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1048         struct hns3_adapter *hns = dev->data->dev_private;
1049         struct hns3_hw *hw = &hns->hw;
1050         enum hns3vf_evt_cause event_cause;
1051         uint32_t clearval;
1052
1053         if (hw->irq_thread_id == 0)
1054                 hw->irq_thread_id = pthread_self();
1055
1056         /* Disable interrupt */
1057         hns3vf_disable_irq0(hw);
1058
1059         /* Read out interrupt causes */
1060         event_cause = hns3vf_check_event_cause(hns, &clearval);
1061
1062         switch (event_cause) {
1063         case HNS3VF_VECTOR0_EVENT_RST:
1064                 hns3_schedule_reset(hns);
1065                 break;
1066         case HNS3VF_VECTOR0_EVENT_MBX:
1067                 hns3_dev_handle_mbx_msg(hw);
1068                 break;
1069         default:
1070                 break;
1071         }
1072
1073         /* Clear interrupt causes */
1074         hns3vf_clear_event_cause(hw, clearval);
1075
1076         /* Enable interrupt */
1077         hns3vf_enable_irq0(hw);
1078 }
1079
1080 static void
1081 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1082 {
1083         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1084         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1085         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1086 }
1087
1088 static void
1089 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1090 {
1091         struct hns3_dev_specs_0_cmd *req0;
1092
1093         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1094
1095         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1096         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1097         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1098 }
1099
1100 static int
1101 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1102 {
1103         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1104         int ret;
1105         int i;
1106
1107         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1108                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1109                                           true);
1110                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1111         }
1112         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1113
1114         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1115         if (ret)
1116                 return ret;
1117
1118         hns3vf_parse_dev_specifications(hw, desc);
1119
1120         return 0;
1121 }
1122
1123 static int
1124 hns3vf_get_capability(struct hns3_hw *hw)
1125 {
1126         struct rte_pci_device *pci_dev;
1127         struct rte_eth_dev *eth_dev;
1128         uint8_t revision;
1129         int ret;
1130
1131         eth_dev = &rte_eth_devices[hw->data->port_id];
1132         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1133
1134         /* Get PCI revision id */
1135         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1136                                   HNS3_PCI_REVISION_ID);
1137         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1138                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1139                              ret);
1140                 return -EIO;
1141         }
1142         hw->revision = revision;
1143
1144         if (revision < PCI_REVISION_ID_HIP09_A) {
1145                 hns3vf_set_default_dev_specifications(hw);
1146                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1147                 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL;
1148                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1149                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1150                 return 0;
1151         }
1152
1153         ret = hns3vf_query_dev_specifications(hw);
1154         if (ret) {
1155                 PMD_INIT_LOG(ERR,
1156                              "failed to query dev specifications, ret = %d",
1157                              ret);
1158                 return ret;
1159         }
1160
1161         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1162         hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL;
1163         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1164         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1165
1166         return 0;
1167 }
1168
1169 static int
1170 hns3vf_check_tqp_info(struct hns3_hw *hw)
1171 {
1172         uint16_t tqps_num;
1173
1174         tqps_num = hw->tqps_num;
1175         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1176                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1177                                   "range: 1~%d",
1178                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1179                 return -EINVAL;
1180         }
1181
1182         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1183
1184         return 0;
1185 }
1186 static int
1187 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1188 {
1189         uint8_t resp_msg;
1190         int ret;
1191
1192         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1193                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1194                                 true, &resp_msg, sizeof(resp_msg));
1195         if (ret) {
1196                 if (ret == -ETIME) {
1197                         /*
1198                          * Getting current port based VLAN state from PF driver
1199                          * will not affect VF driver's basic function. Because
1200                          * the VF driver relies on hns3 PF kernel ether driver,
1201                          * to avoid introducing compatibility issues with older
1202                          * version of PF driver, no failure will be returned
1203                          * when the return value is ETIME. This return value has
1204                          * the following scenarios:
1205                          * 1) Firmware didn't return the results in time
1206                          * 2) the result return by firmware is timeout
1207                          * 3) the older version of kernel side PF driver does
1208                          *    not support this mailbox message.
1209                          * For scenarios 1 and 2, it is most likely that a
1210                          * hardware error has occurred, or a hardware reset has
1211                          * occurred. In this case, these errors will be caught
1212                          * by other functions.
1213                          */
1214                         PMD_INIT_LOG(WARNING,
1215                                 "failed to get PVID state for timeout, maybe "
1216                                 "kernel side PF driver doesn't support this "
1217                                 "mailbox message, or firmware didn't respond.");
1218                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1219                 } else {
1220                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1221                                 " ret = %d", ret);
1222                         return ret;
1223                 }
1224         }
1225         hw->port_base_vlan_cfg.state = resp_msg ?
1226                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1227         return 0;
1228 }
1229
1230 static int
1231 hns3vf_get_queue_info(struct hns3_hw *hw)
1232 {
1233 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1234         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1235         int ret;
1236
1237         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1238                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1239         if (ret) {
1240                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1241                 return ret;
1242         }
1243
1244         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1245         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1246
1247         return hns3vf_check_tqp_info(hw);
1248 }
1249
1250 static int
1251 hns3vf_get_queue_depth(struct hns3_hw *hw)
1252 {
1253 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1254         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1255         int ret;
1256
1257         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1258                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1259         if (ret) {
1260                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1261                              ret);
1262                 return ret;
1263         }
1264
1265         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1266         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1267
1268         return 0;
1269 }
1270
1271 static int
1272 hns3vf_get_tc_info(struct hns3_hw *hw)
1273 {
1274         uint8_t resp_msg;
1275         int ret;
1276
1277         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1278                                 true, &resp_msg, sizeof(resp_msg));
1279         if (ret) {
1280                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1281                          ret);
1282                 return ret;
1283         }
1284
1285         hw->hw_tc_map = resp_msg;
1286
1287         return 0;
1288 }
1289
1290 static int
1291 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1292 {
1293         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1294         int ret;
1295
1296         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1297                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1298         if (ret) {
1299                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1300                 return ret;
1301         }
1302
1303         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1304
1305         return 0;
1306 }
1307
1308 static int
1309 hns3vf_get_configuration(struct hns3_hw *hw)
1310 {
1311         int ret;
1312
1313         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1314         hw->rss_dis_flag = false;
1315
1316         /* Get device capability */
1317         ret = hns3vf_get_capability(hw);
1318         if (ret) {
1319                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1320                 return ret;
1321         }
1322
1323         /* Get queue configuration from PF */
1324         ret = hns3vf_get_queue_info(hw);
1325         if (ret)
1326                 return ret;
1327
1328         /* Get queue depth info from PF */
1329         ret = hns3vf_get_queue_depth(hw);
1330         if (ret)
1331                 return ret;
1332
1333         /* Get user defined VF MAC addr from PF */
1334         ret = hns3vf_get_host_mac_addr(hw);
1335         if (ret)
1336                 return ret;
1337
1338         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1339         if (ret)
1340                 return ret;
1341
1342         /* Get tc configuration from PF */
1343         return hns3vf_get_tc_info(hw);
1344 }
1345
1346 static int
1347 hns3vf_set_tc_info(struct hns3_adapter *hns)
1348 {
1349         struct hns3_hw *hw = &hns->hw;
1350         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1351         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1352         uint8_t i;
1353
1354         hw->num_tc = 0;
1355         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1356                 if (hw->hw_tc_map & BIT(i))
1357                         hw->num_tc++;
1358
1359         if (nb_rx_q < hw->num_tc) {
1360                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1361                          nb_rx_q, hw->num_tc);
1362                 return -EINVAL;
1363         }
1364
1365         if (nb_tx_q < hw->num_tc) {
1366                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1367                          nb_tx_q, hw->num_tc);
1368                 return -EINVAL;
1369         }
1370
1371         hns3_set_rss_size(hw, nb_rx_q);
1372         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1373
1374         return 0;
1375 }
1376
1377 static void
1378 hns3vf_request_link_info(struct hns3_hw *hw)
1379 {
1380         uint8_t resp_msg;
1381         int ret;
1382
1383         if (rte_atomic16_read(&hw->reset.resetting))
1384                 return;
1385         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1386                                 &resp_msg, sizeof(resp_msg));
1387         if (ret)
1388                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1389 }
1390
1391 static int
1392 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1393 {
1394 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1395         struct hns3_hw *hw = &hns->hw;
1396         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1397         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1398         uint8_t is_kill = on ? 0 : 1;
1399
1400         msg_data[0] = is_kill;
1401         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1402         memcpy(&msg_data[3], &proto, sizeof(proto));
1403
1404         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1405                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1406                                  0);
1407 }
1408
1409 static int
1410 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1411 {
1412         struct hns3_adapter *hns = dev->data->dev_private;
1413         struct hns3_hw *hw = &hns->hw;
1414         int ret;
1415
1416         if (rte_atomic16_read(&hw->reset.resetting)) {
1417                 hns3_err(hw,
1418                          "vf set vlan id failed during resetting, vlan_id =%u",
1419                          vlan_id);
1420                 return -EIO;
1421         }
1422         rte_spinlock_lock(&hw->lock);
1423         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1424         rte_spinlock_unlock(&hw->lock);
1425         if (ret)
1426                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1427                          vlan_id, ret);
1428
1429         return ret;
1430 }
1431
1432 static int
1433 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1434 {
1435         uint8_t msg_data;
1436         int ret;
1437
1438         msg_data = enable ? 1 : 0;
1439         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1440                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1441         if (ret)
1442                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1443
1444         return ret;
1445 }
1446
1447 static int
1448 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1449 {
1450         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1452         unsigned int tmp_mask;
1453         int ret = 0;
1454
1455         if (rte_atomic16_read(&hw->reset.resetting)) {
1456                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1457                              "mask = 0x%x", mask);
1458                 return -EIO;
1459         }
1460
1461         tmp_mask = (unsigned int)mask;
1462         /* Vlan stripping setting */
1463         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1464                 rte_spinlock_lock(&hw->lock);
1465                 /* Enable or disable VLAN stripping */
1466                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1467                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1468                 else
1469                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1470                 rte_spinlock_unlock(&hw->lock);
1471         }
1472
1473         return ret;
1474 }
1475
1476 static int
1477 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1478 {
1479         struct rte_vlan_filter_conf *vfc;
1480         struct hns3_hw *hw = &hns->hw;
1481         uint16_t vlan_id;
1482         uint64_t vbit;
1483         uint64_t ids;
1484         int ret = 0;
1485         uint32_t i;
1486
1487         vfc = &hw->data->vlan_filter_conf;
1488         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1489                 if (vfc->ids[i] == 0)
1490                         continue;
1491                 ids = vfc->ids[i];
1492                 while (ids) {
1493                         /*
1494                          * 64 means the num bits of ids, one bit corresponds to
1495                          * one vlan id
1496                          */
1497                         vlan_id = 64 * i;
1498                         /* count trailing zeroes */
1499                         vbit = ~ids & (ids - 1);
1500                         /* clear least significant bit set */
1501                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1502                         for (; vbit;) {
1503                                 vbit >>= 1;
1504                                 vlan_id++;
1505                         }
1506                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1507                         if (ret) {
1508                                 hns3_err(hw,
1509                                          "VF handle vlan table failed, ret =%d, on = %d",
1510                                          ret, on);
1511                                 return ret;
1512                         }
1513                 }
1514         }
1515
1516         return ret;
1517 }
1518
1519 static int
1520 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1521 {
1522         return hns3vf_handle_all_vlan_table(hns, 0);
1523 }
1524
1525 static int
1526 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1527 {
1528         struct hns3_hw *hw = &hns->hw;
1529         struct rte_eth_conf *dev_conf;
1530         bool en;
1531         int ret;
1532
1533         dev_conf = &hw->data->dev_conf;
1534         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1535                                                                    : false;
1536         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1537         if (ret)
1538                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1539                          ret);
1540         return ret;
1541 }
1542
1543 static int
1544 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1545 {
1546         struct hns3_adapter *hns = dev->data->dev_private;
1547         struct rte_eth_dev_data *data = dev->data;
1548         struct hns3_hw *hw = &hns->hw;
1549         int ret;
1550
1551         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1552             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1553             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1554                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1555                               "or hw_vlan_insert_pvid is not support!");
1556         }
1557
1558         /* Apply vlan offload setting */
1559         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1560         if (ret)
1561                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1562
1563         return ret;
1564 }
1565
1566 static int
1567 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1568 {
1569         uint8_t msg_data;
1570
1571         msg_data = alive ? 1 : 0;
1572         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1573                                  sizeof(msg_data), false, NULL, 0);
1574 }
1575
1576 static void
1577 hns3vf_keep_alive_handler(void *param)
1578 {
1579         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1580         struct hns3_adapter *hns = eth_dev->data->dev_private;
1581         struct hns3_hw *hw = &hns->hw;
1582         uint8_t respmsg;
1583         int ret;
1584
1585         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1586                                 false, &respmsg, sizeof(uint8_t));
1587         if (ret)
1588                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1589                          ret);
1590
1591         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1592                           eth_dev);
1593 }
1594
1595 static void
1596 hns3vf_service_handler(void *param)
1597 {
1598         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1599         struct hns3_adapter *hns = eth_dev->data->dev_private;
1600         struct hns3_hw *hw = &hns->hw;
1601
1602         /*
1603          * The query link status and reset processing are executed in the
1604          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1605          * and the query operation will time out after 30ms. In the case of
1606          * multiple PF/VFs, each query failure timeout causes the IMP reset
1607          * interrupt to fail to respond within 100ms.
1608          * Before querying the link status, check whether there is a reset
1609          * pending, and if so, abandon the query.
1610          */
1611         if (!hns3vf_is_reset_pending(hns))
1612                 hns3vf_request_link_info(hw);
1613         else
1614                 hns3_warn(hw, "Cancel the query when reset is pending");
1615
1616         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1617                           eth_dev);
1618 }
1619
1620 static int
1621 hns3_query_vf_resource(struct hns3_hw *hw)
1622 {
1623         struct hns3_vf_res_cmd *req;
1624         struct hns3_cmd_desc desc;
1625         uint16_t num_msi;
1626         int ret;
1627
1628         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1629         ret = hns3_cmd_send(hw, &desc, 1);
1630         if (ret) {
1631                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1632                 return ret;
1633         }
1634
1635         req = (struct hns3_vf_res_cmd *)desc.data;
1636         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1637                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1638         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1639                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1640                          num_msi, HNS3_MIN_VECTOR_NUM);
1641                 return -EINVAL;
1642         }
1643
1644         hw->num_msi = num_msi;
1645
1646         return 0;
1647 }
1648
1649 static int
1650 hns3vf_init_hardware(struct hns3_adapter *hns)
1651 {
1652         struct hns3_hw *hw = &hns->hw;
1653         uint16_t mtu = hw->data->mtu;
1654         int ret;
1655
1656         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1657         if (ret)
1658                 return ret;
1659
1660         ret = hns3vf_config_mtu(hw, mtu);
1661         if (ret)
1662                 goto err_init_hardware;
1663
1664         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1665         if (ret) {
1666                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1667                 goto err_init_hardware;
1668         }
1669
1670         ret = hns3_config_gro(hw, false);
1671         if (ret) {
1672                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1673                 goto err_init_hardware;
1674         }
1675
1676         /*
1677          * In the initialization clearing the all hardware mapping relationship
1678          * configurations between queues and interrupt vectors is needed, so
1679          * some error caused by the residual configurations, such as the
1680          * unexpected interrupt, can be avoid.
1681          */
1682         ret = hns3vf_init_ring_with_vector(hw);
1683         if (ret) {
1684                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1685                 goto err_init_hardware;
1686         }
1687
1688         ret = hns3vf_set_alive(hw, true);
1689         if (ret) {
1690                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1691                 goto err_init_hardware;
1692         }
1693
1694         hns3vf_request_link_info(hw);
1695         return 0;
1696
1697 err_init_hardware:
1698         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1699         return ret;
1700 }
1701
1702 static int
1703 hns3vf_clear_vport_list(struct hns3_hw *hw)
1704 {
1705         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1706                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1707                                  NULL, 0);
1708 }
1709
1710 static int
1711 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1712 {
1713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1714         struct hns3_adapter *hns = eth_dev->data->dev_private;
1715         struct hns3_hw *hw = &hns->hw;
1716         int ret;
1717
1718         PMD_INIT_FUNC_TRACE();
1719
1720         /* Get hardware io base address from pcie BAR2 IO space */
1721         hw->io_base = pci_dev->mem_resource[2].addr;
1722
1723         /* Firmware command queue initialize */
1724         ret = hns3_cmd_init_queue(hw);
1725         if (ret) {
1726                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1727                 goto err_cmd_init_queue;
1728         }
1729
1730         /* Firmware command initialize */
1731         ret = hns3_cmd_init(hw);
1732         if (ret) {
1733                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1734                 goto err_cmd_init;
1735         }
1736
1737         /* Get VF resource */
1738         ret = hns3_query_vf_resource(hw);
1739         if (ret)
1740                 goto err_cmd_init;
1741
1742         rte_spinlock_init(&hw->mbx_resp.lock);
1743
1744         hns3vf_clear_event_cause(hw, 0);
1745
1746         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1747                                          hns3vf_interrupt_handler, eth_dev);
1748         if (ret) {
1749                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1750                 goto err_intr_callback_register;
1751         }
1752
1753         /* Enable interrupt */
1754         rte_intr_enable(&pci_dev->intr_handle);
1755         hns3vf_enable_irq0(hw);
1756
1757         /* Get configuration from PF */
1758         ret = hns3vf_get_configuration(hw);
1759         if (ret) {
1760                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1761                 goto err_get_config;
1762         }
1763
1764         ret = hns3vf_clear_vport_list(hw);
1765         if (ret) {
1766                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1767                 goto err_get_config;
1768         }
1769
1770         ret = hns3vf_init_hardware(hns);
1771         if (ret)
1772                 goto err_get_config;
1773
1774         hns3_set_default_rss_args(hw);
1775
1776         return 0;
1777
1778 err_get_config:
1779         hns3vf_disable_irq0(hw);
1780         rte_intr_disable(&pci_dev->intr_handle);
1781         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1782                              eth_dev);
1783 err_intr_callback_register:
1784 err_cmd_init:
1785         hns3_cmd_uninit(hw);
1786         hns3_cmd_destroy_queue(hw);
1787 err_cmd_init_queue:
1788         hw->io_base = NULL;
1789
1790         return ret;
1791 }
1792
1793 static void
1794 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1795 {
1796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1797         struct hns3_adapter *hns = eth_dev->data->dev_private;
1798         struct hns3_hw *hw = &hns->hw;
1799
1800         PMD_INIT_FUNC_TRACE();
1801
1802         hns3_rss_uninit(hns);
1803         (void)hns3_config_gro(hw, false);
1804         (void)hns3vf_set_alive(hw, false);
1805         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1806         hns3vf_disable_irq0(hw);
1807         rte_intr_disable(&pci_dev->intr_handle);
1808         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1809                              eth_dev);
1810         hns3_cmd_uninit(hw);
1811         hns3_cmd_destroy_queue(hw);
1812         hw->io_base = NULL;
1813 }
1814
1815 static int
1816 hns3vf_do_stop(struct hns3_adapter *hns)
1817 {
1818         struct hns3_hw *hw = &hns->hw;
1819         bool reset_queue;
1820
1821         hw->mac.link_status = ETH_LINK_DOWN;
1822
1823         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1824                 hns3vf_configure_mac_addr(hns, true);
1825                 reset_queue = true;
1826         } else
1827                 reset_queue = false;
1828         return hns3_stop_queues(hns, reset_queue);
1829 }
1830
1831 static void
1832 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1833 {
1834         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1836         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1837         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1838         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1839         uint16_t q_id;
1840
1841         if (dev->data->dev_conf.intr_conf.rxq == 0)
1842                 return;
1843
1844         /* unmap the ring with vector */
1845         if (rte_intr_allow_others(intr_handle)) {
1846                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1847                 base = RTE_INTR_VEC_RXTX_OFFSET;
1848         }
1849         if (rte_intr_dp_is_en(intr_handle)) {
1850                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1851                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1852                                                            HNS3_RING_TYPE_RX,
1853                                                            q_id);
1854                         if (vec < base + intr_handle->nb_efd - 1)
1855                                 vec++;
1856                 }
1857         }
1858         /* Clean datapath event and queue/vec mapping */
1859         rte_intr_efd_disable(intr_handle);
1860         if (intr_handle->intr_vec) {
1861                 rte_free(intr_handle->intr_vec);
1862                 intr_handle->intr_vec = NULL;
1863         }
1864 }
1865
1866 static void
1867 hns3vf_dev_stop(struct rte_eth_dev *dev)
1868 {
1869         struct hns3_adapter *hns = dev->data->dev_private;
1870         struct hns3_hw *hw = &hns->hw;
1871
1872         PMD_INIT_FUNC_TRACE();
1873
1874         hw->adapter_state = HNS3_NIC_STOPPING;
1875         hns3_set_rxtx_function(dev);
1876         rte_wmb();
1877         /* Disable datapath on secondary process. */
1878         hns3_mp_req_stop_rxtx(dev);
1879         /* Prevent crashes when queues are still in use. */
1880         rte_delay_ms(hw->tqps_num);
1881
1882         rte_spinlock_lock(&hw->lock);
1883         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1884                 hns3vf_do_stop(hns);
1885                 hns3vf_unmap_rx_interrupt(dev);
1886                 hns3_dev_release_mbufs(hns);
1887                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1888         }
1889         hns3_rx_scattered_reset(dev);
1890         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1891         rte_spinlock_unlock(&hw->lock);
1892 }
1893
1894 static void
1895 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1896 {
1897         struct hns3_adapter *hns = eth_dev->data->dev_private;
1898         struct hns3_hw *hw = &hns->hw;
1899
1900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901                 return;
1902
1903         if (hw->adapter_state == HNS3_NIC_STARTED)
1904                 hns3vf_dev_stop(eth_dev);
1905
1906         hw->adapter_state = HNS3_NIC_CLOSING;
1907         hns3_reset_abort(hns);
1908         hw->adapter_state = HNS3_NIC_CLOSED;
1909         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1910         hns3vf_configure_all_mc_mac_addr(hns, true);
1911         hns3vf_remove_all_vlan_table(hns);
1912         hns3vf_uninit_vf(eth_dev);
1913         hns3_free_all_queues(eth_dev);
1914         rte_free(hw->reset.wait_data);
1915         rte_free(eth_dev->process_private);
1916         eth_dev->process_private = NULL;
1917         hns3_mp_uninit_primary();
1918         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1919 }
1920
1921 static int
1922 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1923                       size_t fw_size)
1924 {
1925         struct hns3_adapter *hns = eth_dev->data->dev_private;
1926         struct hns3_hw *hw = &hns->hw;
1927         uint32_t version = hw->fw_version;
1928         int ret;
1929
1930         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1931                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1932                                       HNS3_FW_VERSION_BYTE3_S),
1933                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1934                                       HNS3_FW_VERSION_BYTE2_S),
1935                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1936                                       HNS3_FW_VERSION_BYTE1_S),
1937                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1938                                       HNS3_FW_VERSION_BYTE0_S));
1939         ret += 1; /* add the size of '\0' */
1940         if (fw_size < (uint32_t)ret)
1941                 return ret;
1942         else
1943                 return 0;
1944 }
1945
1946 static int
1947 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1948                        __rte_unused int wait_to_complete)
1949 {
1950         struct hns3_adapter *hns = eth_dev->data->dev_private;
1951         struct hns3_hw *hw = &hns->hw;
1952         struct hns3_mac *mac = &hw->mac;
1953         struct rte_eth_link new_link;
1954
1955         memset(&new_link, 0, sizeof(new_link));
1956         switch (mac->link_speed) {
1957         case ETH_SPEED_NUM_10M:
1958         case ETH_SPEED_NUM_100M:
1959         case ETH_SPEED_NUM_1G:
1960         case ETH_SPEED_NUM_10G:
1961         case ETH_SPEED_NUM_25G:
1962         case ETH_SPEED_NUM_40G:
1963         case ETH_SPEED_NUM_50G:
1964         case ETH_SPEED_NUM_100G:
1965         case ETH_SPEED_NUM_200G:
1966                 new_link.link_speed = mac->link_speed;
1967                 break;
1968         default:
1969                 new_link.link_speed = ETH_SPEED_NUM_100M;
1970                 break;
1971         }
1972
1973         new_link.link_duplex = mac->link_duplex;
1974         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1975         new_link.link_autoneg =
1976             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1977
1978         return rte_eth_linkstatus_set(eth_dev, &new_link);
1979 }
1980
1981 static int
1982 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1983 {
1984         struct hns3_hw *hw = &hns->hw;
1985         int ret;
1986
1987         ret = hns3vf_set_tc_info(hns);
1988         if (ret)
1989                 return ret;
1990
1991         ret = hns3_start_queues(hns, reset_queue);
1992         if (ret)
1993                 hns3_err(hw, "Failed to start queues: %d", ret);
1994
1995         return ret;
1996 }
1997
1998 static int
1999 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2000 {
2001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2003         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2005         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2006         uint32_t intr_vector;
2007         uint16_t q_id;
2008         int ret;
2009
2010         if (dev->data->dev_conf.intr_conf.rxq == 0)
2011                 return 0;
2012
2013         /* disable uio/vfio intr/eventfd mapping */
2014         rte_intr_disable(intr_handle);
2015
2016         /* check and configure queue intr-vector mapping */
2017         if (rte_intr_cap_multiple(intr_handle) ||
2018             !RTE_ETH_DEV_SRIOV(dev).active) {
2019                 intr_vector = hw->used_rx_queues;
2020                 /* It creates event fd for each intr vector when MSIX is used */
2021                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2022                         return -EINVAL;
2023         }
2024         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2025                 intr_handle->intr_vec =
2026                         rte_zmalloc("intr_vec",
2027                                     hw->used_rx_queues * sizeof(int), 0);
2028                 if (intr_handle->intr_vec == NULL) {
2029                         hns3_err(hw, "Failed to allocate %d rx_queues"
2030                                      " intr_vec", hw->used_rx_queues);
2031                         ret = -ENOMEM;
2032                         goto vf_alloc_intr_vec_error;
2033                 }
2034         }
2035
2036         if (rte_intr_allow_others(intr_handle)) {
2037                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2038                 base = RTE_INTR_VEC_RXTX_OFFSET;
2039         }
2040         if (rte_intr_dp_is_en(intr_handle)) {
2041                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2042                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2043                                                            HNS3_RING_TYPE_RX,
2044                                                            q_id);
2045                         if (ret)
2046                                 goto vf_bind_vector_error;
2047                         intr_handle->intr_vec[q_id] = vec;
2048                         if (vec < base + intr_handle->nb_efd - 1)
2049                                 vec++;
2050                 }
2051         }
2052         rte_intr_enable(intr_handle);
2053         return 0;
2054
2055 vf_bind_vector_error:
2056         rte_intr_efd_disable(intr_handle);
2057         if (intr_handle->intr_vec) {
2058                 free(intr_handle->intr_vec);
2059                 intr_handle->intr_vec = NULL;
2060         }
2061         return ret;
2062 vf_alloc_intr_vec_error:
2063         rte_intr_efd_disable(intr_handle);
2064         return ret;
2065 }
2066
2067 static int
2068 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2069 {
2070         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2073         uint16_t q_id;
2074         int ret;
2075
2076         if (dev->data->dev_conf.intr_conf.rxq == 0)
2077                 return 0;
2078
2079         if (rte_intr_dp_is_en(intr_handle)) {
2080                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2081                         ret = hns3vf_bind_ring_with_vector(hw,
2082                                         intr_handle->intr_vec[q_id], true,
2083                                         HNS3_RING_TYPE_RX, q_id);
2084                         if (ret)
2085                                 return ret;
2086                 }
2087         }
2088
2089         return 0;
2090 }
2091
2092 static void
2093 hns3vf_restore_filter(struct rte_eth_dev *dev)
2094 {
2095         hns3_restore_rss_filter(dev);
2096 }
2097
2098 static int
2099 hns3vf_dev_start(struct rte_eth_dev *dev)
2100 {
2101         struct hns3_adapter *hns = dev->data->dev_private;
2102         struct hns3_hw *hw = &hns->hw;
2103         int ret;
2104
2105         PMD_INIT_FUNC_TRACE();
2106         if (rte_atomic16_read(&hw->reset.resetting))
2107                 return -EBUSY;
2108
2109         rte_spinlock_lock(&hw->lock);
2110         hw->adapter_state = HNS3_NIC_STARTING;
2111         ret = hns3vf_do_start(hns, true);
2112         if (ret) {
2113                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2114                 rte_spinlock_unlock(&hw->lock);
2115                 return ret;
2116         }
2117         ret = hns3vf_map_rx_interrupt(dev);
2118         if (ret) {
2119                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2120                 rte_spinlock_unlock(&hw->lock);
2121                 return ret;
2122         }
2123         hw->adapter_state = HNS3_NIC_STARTED;
2124         rte_spinlock_unlock(&hw->lock);
2125
2126         hns3_rx_scattered_calc(dev);
2127         hns3_set_rxtx_function(dev);
2128         hns3_mp_req_start_rxtx(dev);
2129         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2130
2131         hns3vf_restore_filter(dev);
2132
2133         /* Enable interrupt of all rx queues before enabling queues */
2134         hns3_dev_all_rx_queue_intr_enable(hw, true);
2135         /*
2136          * When finished the initialization, enable queues to receive/transmit
2137          * packets.
2138          */
2139         hns3_enable_all_queues(hw, true);
2140
2141         return ret;
2142 }
2143
2144 static bool
2145 is_vf_reset_done(struct hns3_hw *hw)
2146 {
2147 #define HNS3_FUN_RST_ING_BITS \
2148         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2149          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2150          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2151          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2152
2153         uint32_t val;
2154
2155         if (hw->reset.level == HNS3_VF_RESET) {
2156                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2157                 if (val & HNS3_VF_RST_ING_BIT)
2158                         return false;
2159         } else {
2160                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2161                 if (val & HNS3_FUN_RST_ING_BITS)
2162                         return false;
2163         }
2164         return true;
2165 }
2166
2167 bool
2168 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2169 {
2170         struct hns3_hw *hw = &hns->hw;
2171         enum hns3_reset_level reset;
2172
2173         hns3vf_check_event_cause(hns, NULL);
2174         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2175         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2176                 hns3_warn(hw, "High level reset %d is pending", reset);
2177                 return true;
2178         }
2179         return false;
2180 }
2181
2182 static int
2183 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2184 {
2185         struct hns3_hw *hw = &hns->hw;
2186         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2187         struct timeval tv;
2188
2189         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2190                 /*
2191                  * After vf reset is ready, the PF may not have completed
2192                  * the reset processing. The vf sending mbox to PF may fail
2193                  * during the pf reset, so it is better to add extra delay.
2194                  */
2195                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2196                     hw->reset.level == HNS3_FLR_RESET)
2197                         return 0;
2198                 /* Reset retry process, no need to add extra delay. */
2199                 if (hw->reset.attempts)
2200                         return 0;
2201                 if (wait_data->check_completion == NULL)
2202                         return 0;
2203
2204                 wait_data->check_completion = NULL;
2205                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2206                 wait_data->count = 1;
2207                 wait_data->result = HNS3_WAIT_REQUEST;
2208                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2209                                   wait_data);
2210                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2211                 return -EAGAIN;
2212         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2213                 gettimeofday(&tv, NULL);
2214                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2215                           tv.tv_sec, tv.tv_usec);
2216                 return -ETIME;
2217         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2218                 return -EAGAIN;
2219
2220         wait_data->hns = hns;
2221         wait_data->check_completion = is_vf_reset_done;
2222         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2223                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2224         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2225         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2226         wait_data->result = HNS3_WAIT_REQUEST;
2227         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2228         return -EAGAIN;
2229 }
2230
2231 static int
2232 hns3vf_prepare_reset(struct hns3_adapter *hns)
2233 {
2234         struct hns3_hw *hw = &hns->hw;
2235         int ret = 0;
2236
2237         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2238                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2239                                         0, true, NULL, 0);
2240         }
2241         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2242
2243         return ret;
2244 }
2245
2246 static int
2247 hns3vf_stop_service(struct hns3_adapter *hns)
2248 {
2249         struct hns3_hw *hw = &hns->hw;
2250         struct rte_eth_dev *eth_dev;
2251
2252         eth_dev = &rte_eth_devices[hw->data->port_id];
2253         if (hw->adapter_state == HNS3_NIC_STARTED)
2254                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2255         hw->mac.link_status = ETH_LINK_DOWN;
2256
2257         hns3_set_rxtx_function(eth_dev);
2258         rte_wmb();
2259         /* Disable datapath on secondary process. */
2260         hns3_mp_req_stop_rxtx(eth_dev);
2261         rte_delay_ms(hw->tqps_num);
2262
2263         rte_spinlock_lock(&hw->lock);
2264         if (hw->adapter_state == HNS3_NIC_STARTED ||
2265             hw->adapter_state == HNS3_NIC_STOPPING) {
2266                 hns3vf_do_stop(hns);
2267                 hw->reset.mbuf_deferred_free = true;
2268         } else
2269                 hw->reset.mbuf_deferred_free = false;
2270
2271         /*
2272          * It is cumbersome for hardware to pick-and-choose entries for deletion
2273          * from table space. Hence, for function reset software intervention is
2274          * required to delete the entries.
2275          */
2276         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2277                 hns3vf_configure_all_mc_mac_addr(hns, true);
2278         rte_spinlock_unlock(&hw->lock);
2279
2280         return 0;
2281 }
2282
2283 static int
2284 hns3vf_start_service(struct hns3_adapter *hns)
2285 {
2286         struct hns3_hw *hw = &hns->hw;
2287         struct rte_eth_dev *eth_dev;
2288
2289         eth_dev = &rte_eth_devices[hw->data->port_id];
2290         hns3_set_rxtx_function(eth_dev);
2291         hns3_mp_req_start_rxtx(eth_dev);
2292         if (hw->adapter_state == HNS3_NIC_STARTED) {
2293                 hns3vf_service_handler(eth_dev);
2294
2295                 /* Enable interrupt of all rx queues before enabling queues */
2296                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2297                 /*
2298                  * When finished the initialization, enable queues to receive
2299                  * and transmit packets.
2300                  */
2301                 hns3_enable_all_queues(hw, true);
2302         }
2303
2304         return 0;
2305 }
2306
2307 static int
2308 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2309 {
2310         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2311         struct rte_ether_addr *hw_mac;
2312         int ret;
2313
2314         /*
2315          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2316          * on the host by "ip link set ..." command. If the hns3 PF kernel
2317          * ethdev driver sets the MAC address for VF device after the
2318          * initialization of the related VF device, the PF driver will notify
2319          * VF driver to reset VF device to make the new MAC address effective
2320          * immediately. The hns3 VF PMD driver should check whether the MAC
2321          * address has been changed by the PF kernel ethdev driver, if changed
2322          * VF driver should configure hardware using the new MAC address in the
2323          * recovering hardware configuration stage of the reset process.
2324          */
2325         ret = hns3vf_get_host_mac_addr(hw);
2326         if (ret)
2327                 return ret;
2328
2329         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2330         ret = rte_is_zero_ether_addr(hw_mac);
2331         if (ret) {
2332                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2333         } else {
2334                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2335                 if (!ret) {
2336                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2337                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2338                                               &hw->data->mac_addrs[0]);
2339                         hns3_warn(hw, "Default MAC address has been changed to:"
2340                                   " %s by the host PF kernel ethdev driver",
2341                                   mac_str);
2342                 }
2343         }
2344
2345         return 0;
2346 }
2347
2348 static int
2349 hns3vf_restore_conf(struct hns3_adapter *hns)
2350 {
2351         struct hns3_hw *hw = &hns->hw;
2352         int ret;
2353
2354         ret = hns3vf_check_default_mac_change(hw);
2355         if (ret)
2356                 return ret;
2357
2358         ret = hns3vf_configure_mac_addr(hns, false);
2359         if (ret)
2360                 return ret;
2361
2362         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2363         if (ret)
2364                 goto err_mc_mac;
2365
2366         ret = hns3vf_restore_promisc(hns);
2367         if (ret)
2368                 goto err_vlan_table;
2369
2370         ret = hns3vf_restore_vlan_conf(hns);
2371         if (ret)
2372                 goto err_vlan_table;
2373
2374         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2375         if (ret)
2376                 goto err_vlan_table;
2377
2378         ret = hns3vf_restore_rx_interrupt(hw);
2379         if (ret)
2380                 goto err_vlan_table;
2381
2382         ret = hns3_restore_gro_conf(hw);
2383         if (ret)
2384                 goto err_vlan_table;
2385
2386         if (hw->adapter_state == HNS3_NIC_STARTED) {
2387                 ret = hns3vf_do_start(hns, false);
2388                 if (ret)
2389                         goto err_vlan_table;
2390                 hns3_info(hw, "hns3vf dev restart successful!");
2391         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2392                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2393         return 0;
2394
2395 err_vlan_table:
2396         hns3vf_configure_all_mc_mac_addr(hns, true);
2397 err_mc_mac:
2398         hns3vf_configure_mac_addr(hns, true);
2399         return ret;
2400 }
2401
2402 static enum hns3_reset_level
2403 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2404 {
2405         enum hns3_reset_level reset_level;
2406
2407         /* return the highest priority reset level amongst all */
2408         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2409                 reset_level = HNS3_VF_RESET;
2410         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2411                 reset_level = HNS3_VF_FULL_RESET;
2412         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2413                 reset_level = HNS3_VF_PF_FUNC_RESET;
2414         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2415                 reset_level = HNS3_VF_FUNC_RESET;
2416         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2417                 reset_level = HNS3_FLR_RESET;
2418         else
2419                 reset_level = HNS3_NONE_RESET;
2420
2421         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2422                 return HNS3_NONE_RESET;
2423
2424         return reset_level;
2425 }
2426
2427 static void
2428 hns3vf_reset_service(void *param)
2429 {
2430         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2431         struct hns3_hw *hw = &hns->hw;
2432         enum hns3_reset_level reset_level;
2433         struct timeval tv_delta;
2434         struct timeval tv_start;
2435         struct timeval tv;
2436         uint64_t msec;
2437
2438         /*
2439          * The interrupt is not triggered within the delay time.
2440          * The interrupt may have been lost. It is necessary to handle
2441          * the interrupt to recover from the error.
2442          */
2443         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2444                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2445                 hns3_err(hw, "Handling interrupts in delayed tasks");
2446                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2447                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2448                 if (reset_level == HNS3_NONE_RESET) {
2449                         hns3_err(hw, "No reset level is set, try global reset");
2450                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2451                 }
2452         }
2453         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2454
2455         /*
2456          * Hardware reset has been notified, we now have to poll & check if
2457          * hardware has actually completed the reset sequence.
2458          */
2459         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2460         if (reset_level != HNS3_NONE_RESET) {
2461                 gettimeofday(&tv_start, NULL);
2462                 hns3_reset_process(hns, reset_level);
2463                 gettimeofday(&tv, NULL);
2464                 timersub(&tv, &tv_start, &tv_delta);
2465                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2466                        tv_delta.tv_usec / USEC_PER_MSEC;
2467                 if (msec > HNS3_RESET_PROCESS_MS)
2468                         hns3_err(hw, "%d handle long time delta %" PRIx64
2469                                  " ms time=%ld.%.6ld",
2470                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2471         }
2472 }
2473
2474 static int
2475 hns3vf_reinit_dev(struct hns3_adapter *hns)
2476 {
2477         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2478         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2479         struct hns3_hw *hw = &hns->hw;
2480         int ret;
2481
2482         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2483                 rte_intr_disable(&pci_dev->intr_handle);
2484                 hns3vf_set_bus_master(pci_dev, true);
2485         }
2486
2487         /* Firmware command initialize */
2488         ret = hns3_cmd_init(hw);
2489         if (ret) {
2490                 hns3_err(hw, "Failed to init cmd: %d", ret);
2491                 return ret;
2492         }
2493
2494         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2495                 /*
2496                  * UIO enables msix by writing the pcie configuration space
2497                  * vfio_pci enables msix in rte_intr_enable.
2498                  */
2499                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2500                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2501                         if (hns3vf_enable_msix(pci_dev, true))
2502                                 hns3_err(hw, "Failed to enable msix");
2503                 }
2504
2505                 rte_intr_enable(&pci_dev->intr_handle);
2506         }
2507
2508         ret = hns3_reset_all_queues(hns);
2509         if (ret) {
2510                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2511                 return ret;
2512         }
2513
2514         ret = hns3vf_init_hardware(hns);
2515         if (ret) {
2516                 hns3_err(hw, "Failed to init hardware: %d", ret);
2517                 return ret;
2518         }
2519
2520         return 0;
2521 }
2522
2523 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2524         .dev_configure      = hns3vf_dev_configure,
2525         .dev_start          = hns3vf_dev_start,
2526         .dev_stop           = hns3vf_dev_stop,
2527         .dev_close          = hns3vf_dev_close,
2528         .mtu_set            = hns3vf_dev_mtu_set,
2529         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2530         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2531         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2532         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2533         .stats_get          = hns3_stats_get,
2534         .stats_reset        = hns3_stats_reset,
2535         .xstats_get         = hns3_dev_xstats_get,
2536         .xstats_get_names   = hns3_dev_xstats_get_names,
2537         .xstats_reset       = hns3_dev_xstats_reset,
2538         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2539         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2540         .dev_infos_get      = hns3vf_dev_infos_get,
2541         .fw_version_get     = hns3vf_fw_version_get,
2542         .rx_queue_setup     = hns3_rx_queue_setup,
2543         .tx_queue_setup     = hns3_tx_queue_setup,
2544         .rx_queue_release   = hns3_dev_rx_queue_release,
2545         .tx_queue_release   = hns3_dev_tx_queue_release,
2546         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2547         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2548         .rxq_info_get       = hns3_rxq_info_get,
2549         .txq_info_get       = hns3_txq_info_get,
2550         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2551         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2552         .mac_addr_add       = hns3vf_add_mac_addr,
2553         .mac_addr_remove    = hns3vf_remove_mac_addr,
2554         .mac_addr_set       = hns3vf_set_default_mac_addr,
2555         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2556         .link_update        = hns3vf_dev_link_update,
2557         .rss_hash_update    = hns3_dev_rss_hash_update,
2558         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2559         .reta_update        = hns3_dev_rss_reta_update,
2560         .reta_query         = hns3_dev_rss_reta_query,
2561         .filter_ctrl        = hns3_dev_filter_ctrl,
2562         .vlan_filter_set    = hns3vf_vlan_filter_set,
2563         .vlan_offload_set   = hns3vf_vlan_offload_set,
2564         .get_reg            = hns3_get_regs,
2565         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2566 };
2567
2568 static const struct hns3_reset_ops hns3vf_reset_ops = {
2569         .reset_service       = hns3vf_reset_service,
2570         .stop_service        = hns3vf_stop_service,
2571         .prepare_reset       = hns3vf_prepare_reset,
2572         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2573         .reinit_dev          = hns3vf_reinit_dev,
2574         .restore_conf        = hns3vf_restore_conf,
2575         .start_service       = hns3vf_start_service,
2576 };
2577
2578 static int
2579 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2580 {
2581         struct hns3_adapter *hns = eth_dev->data->dev_private;
2582         struct hns3_hw *hw = &hns->hw;
2583         int ret;
2584
2585         PMD_INIT_FUNC_TRACE();
2586
2587         eth_dev->process_private = (struct hns3_process_private *)
2588             rte_zmalloc_socket("hns3_filter_list",
2589                                sizeof(struct hns3_process_private),
2590                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2591         if (eth_dev->process_private == NULL) {
2592                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2593                 return -ENOMEM;
2594         }
2595
2596         /* initialize flow filter lists */
2597         hns3_filterlist_init(eth_dev);
2598
2599         hns3_set_rxtx_function(eth_dev);
2600         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2601         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2602                 ret = hns3_mp_init_secondary();
2603                 if (ret) {
2604                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2605                                           "process, ret = %d", ret);
2606                         goto err_mp_init_secondary;
2607                 }
2608
2609                 hw->secondary_cnt++;
2610                 return 0;
2611         }
2612
2613         ret = hns3_mp_init_primary();
2614         if (ret) {
2615                 PMD_INIT_LOG(ERR,
2616                              "Failed to init for primary process, ret = %d",
2617                              ret);
2618                 goto err_mp_init_primary;
2619         }
2620
2621         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2622         hns->is_vf = true;
2623         hw->data = eth_dev->data;
2624
2625         ret = hns3_reset_init(hw);
2626         if (ret)
2627                 goto err_init_reset;
2628         hw->reset.ops = &hns3vf_reset_ops;
2629
2630         ret = hns3vf_init_vf(eth_dev);
2631         if (ret) {
2632                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2633                 goto err_init_vf;
2634         }
2635
2636         /* Allocate memory for storing MAC addresses */
2637         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2638                                                sizeof(struct rte_ether_addr) *
2639                                                HNS3_VF_UC_MACADDR_NUM, 0);
2640         if (eth_dev->data->mac_addrs == NULL) {
2641                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2642                              "to store MAC addresses",
2643                              sizeof(struct rte_ether_addr) *
2644                              HNS3_VF_UC_MACADDR_NUM);
2645                 ret = -ENOMEM;
2646                 goto err_rte_zmalloc;
2647         }
2648
2649         /*
2650          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2651          * on the host by "ip link set ..." command. To avoid some incorrect
2652          * scenes, for example, hns3 VF PMD driver fails to receive and send
2653          * packets after user configure the MAC address by using the
2654          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2655          * address strategy as the hns3 kernel ethdev driver in the
2656          * initialization. If user configure a MAC address by the ip command
2657          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2658          * start with a random MAC address in the initialization.
2659          */
2660         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2661                 rte_eth_random_addr(hw->mac.mac_addr);
2662         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2663                             &eth_dev->data->mac_addrs[0]);
2664
2665         hw->adapter_state = HNS3_NIC_INITIALIZED;
2666         /*
2667          * Pass the information to the rte_eth_dev_close() that it should also
2668          * release the private port resources.
2669          */
2670         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2671
2672         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2673                 hns3_err(hw, "Reschedule reset service after dev_init");
2674                 hns3_schedule_reset(hns);
2675         } else {
2676                 /* IMP will wait ready flag before reset */
2677                 hns3_notify_reset_ready(hw, false);
2678         }
2679         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2680                           eth_dev);
2681         return 0;
2682
2683 err_rte_zmalloc:
2684         hns3vf_uninit_vf(eth_dev);
2685
2686 err_init_vf:
2687         rte_free(hw->reset.wait_data);
2688
2689 err_init_reset:
2690         hns3_mp_uninit_primary();
2691
2692 err_mp_init_primary:
2693 err_mp_init_secondary:
2694         eth_dev->dev_ops = NULL;
2695         eth_dev->rx_pkt_burst = NULL;
2696         eth_dev->tx_pkt_burst = NULL;
2697         eth_dev->tx_pkt_prepare = NULL;
2698         rte_free(eth_dev->process_private);
2699         eth_dev->process_private = NULL;
2700
2701         return ret;
2702 }
2703
2704 static int
2705 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2706 {
2707         struct hns3_adapter *hns = eth_dev->data->dev_private;
2708         struct hns3_hw *hw = &hns->hw;
2709
2710         PMD_INIT_FUNC_TRACE();
2711
2712         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2713                 return -EPERM;
2714
2715         eth_dev->dev_ops = NULL;
2716         eth_dev->rx_pkt_burst = NULL;
2717         eth_dev->tx_pkt_burst = NULL;
2718         eth_dev->tx_pkt_prepare = NULL;
2719
2720         if (hw->adapter_state < HNS3_NIC_CLOSING)
2721                 hns3vf_dev_close(eth_dev);
2722
2723         hw->adapter_state = HNS3_NIC_REMOVED;
2724         return 0;
2725 }
2726
2727 static int
2728 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2729                      struct rte_pci_device *pci_dev)
2730 {
2731         return rte_eth_dev_pci_generic_probe(pci_dev,
2732                                              sizeof(struct hns3_adapter),
2733                                              hns3vf_dev_init);
2734 }
2735
2736 static int
2737 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2738 {
2739         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2740 }
2741
2742 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2743         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2744         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2745         { .vendor_id = 0, /* sentinel */ },
2746 };
2747
2748 static struct rte_pci_driver rte_hns3vf_pmd = {
2749         .id_table = pci_id_hns3vf_map,
2750         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2751         .probe = eth_hns3vf_pci_probe,
2752         .remove = eth_hns3vf_pci_remove,
2753 };
2754
2755 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2756 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2757 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");