drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         bool gro_en;
 761         int ret;
 762
 763         /*
 764          * Hardware does not support individually enable/disable/reset the Tx or
 765          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 766          * and Rx queues at the same time. When the numbers of Tx queues
 767          * allocated by upper applications are not equal to the numbers of Rx
 768          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 769          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 770          * these fake queues are imperceptible, and can not be used by upper
 771          * applications.
 772          */
 773         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774         if (ret) {
 775                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 776                 return ret;
 777         }
 778
 779         hw->adapter_state = HNS3_NIC_CONFIGURING;
 780         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 781                 hns3_err(hw, "setting link speed/duplex not supported");
 782                 ret = -EINVAL;
 783                 goto cfg_err;
 784         }
 785
 786         /* When RSS is not configured, redirect the packet queue 0 */
 787         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 788                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 789                 rss_conf = conf->rx_adv_conf.rss_conf;
 790                 if (rss_conf.rss_key == NULL) {
 791                         rss_conf.rss_key = rss_cfg->key;
 792                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 793                 }
 794
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         /*
 801          * If jumbo frames are enabled, MTU needs to be refreshed
 802          * according to the maximum RX packet length.
 803          */
 804         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 805                 /*
 806                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 807                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 808                  * can safely assign to "uint16_t" type variable.
 809                  */
 810                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 811                 ret = hns3vf_dev_mtu_set(dev, mtu);
 812                 if (ret)
 813                         goto cfg_err;
 814                 dev->data->mtu = mtu;
 815         }
 816
 817         ret = hns3vf_dev_configure_vlan(dev);
 818         if (ret)
 819                 goto cfg_err;
 820
 821         /* config hardware GRO */
 822         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 823         ret = hns3_config_gro(hw, gro_en);
 824         if (ret)
 825                 goto cfg_err;
 826
 827         hw->adapter_state = HNS3_NIC_CONFIGURED;
 828         return 0;
 829
 830 cfg_err:
 831         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 832         hw->adapter_state = HNS3_NIC_INITIALIZED;
 833
 834         return ret;
 835 }
 836
 837 static int
 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 839 {
 840         int ret;
 841
 842         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 843                                 sizeof(mtu), true, NULL, 0);
 844         if (ret)
 845                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 855         int ret;
 856
 857         /*
 858          * The hns3 PF/VF devices on the same port share the hardware MTU
 859          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 860          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 861          * driver, there is no need to stop the port for hns3 VF device, and the
 862          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 863          * PF's MTU.
 864          */
 865         if (rte_atomic16_read(&hw->reset.resetting)) {
 866                 hns3_err(hw, "Failed to set mtu during resetting");
 867                 return -EIO;
 868         }
 869
 870         rte_spinlock_lock(&hw->lock);
 871         ret = hns3vf_config_mtu(hw, mtu);
 872         if (ret) {
 873                 rte_spinlock_unlock(&hw->lock);
 874                 return ret;
 875         }
 876         if (frame_size > RTE_ETHER_MAX_LEN)
 877                 dev->data->dev_conf.rxmode.offloads |=
 878                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 879         else
 880                 dev->data->dev_conf.rxmode.offloads &=
 881                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 883         rte_spinlock_unlock(&hw->lock);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 890 {
 891         struct hns3_adapter *hns = eth_dev->data->dev_private;
 892         struct hns3_hw *hw = &hns->hw;
 893         uint16_t q_num = hw->tqps_num;
 894
 895         /*
 896          * In interrupt mode, 'max_rx_queues' is set based on the number of
 897          * MSI-X interrupt resources of the hardware.
 898          */
 899         if (hw->data->dev_conf.intr_conf.rxq == 1)
 900                 q_num = hw->intr_tqps_num;
 901
 902         info->max_rx_queues = q_num;
 903         info->max_tx_queues = hw->tqps_num;
 904         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 905         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 906         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 907         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 908         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 909
 910         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 913                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 914                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_SCATTER |
 917                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 918                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 919                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 920                                  DEV_RX_OFFLOAD_RSS_HASH |
 921                                  DEV_RX_OFFLOAD_TCP_LRO);
 922         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 923         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 924                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 926                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 927                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 928                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 929                                  DEV_TX_OFFLOAD_TCP_TSO |
 930                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 931                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 932                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 933                                  info->tx_queue_offload_capa |
 934                                  hns3_txvlan_cap_get(hw));
 935
 936         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 937                 .nb_max = HNS3_MAX_RING_DESC,
 938                 .nb_min = HNS3_MIN_RING_DESC,
 939                 .nb_align = HNS3_ALIGN_RING_DESC,
 940         };
 941
 942         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 943                 .nb_max = HNS3_MAX_RING_DESC,
 944                 .nb_min = HNS3_MIN_RING_DESC,
 945                 .nb_align = HNS3_ALIGN_RING_DESC,
 946                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 947                 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT,
 948         };
 949
 950         info->default_rxconf = (struct rte_eth_rxconf) {
 951                 /*
 952                  * If there are no available Rx buffer descriptors, incoming
 953                  * packets are always dropped by hardware based on hns3 network
 954                  * engine.
 955                  */
 956                 .rx_drop_en = 1,
 957         };
 958
 959         info->vmdq_queue_num = 0;
 960
 961         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 962         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 963         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 964         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 965         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 966
 967         return 0;
 968 }
 969
 970 static void
 971 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 972 {
 973         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 974 }
 975
 976 static void
 977 hns3vf_disable_irq0(struct hns3_hw *hw)
 978 {
 979         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 980 }
 981
 982 static void
 983 hns3vf_enable_irq0(struct hns3_hw *hw)
 984 {
 985         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 986 }
 987
 988 static enum hns3vf_evt_cause
 989 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 990 {
 991         struct hns3_hw *hw = &hns->hw;
 992         enum hns3vf_evt_cause ret;
 993         uint32_t cmdq_stat_reg;
 994         uint32_t rst_ing_reg;
 995         uint32_t val;
 996
 997         /* Fetch the events from their corresponding regs */
 998         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 999
1000         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1001                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1002                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1003                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1004                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
1005                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1006                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1007                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1008                 if (clearval) {
1009                         hw->reset.stats.global_cnt++;
1010                         hns3_warn(hw, "Global reset detected, clear reset status");
1011                 } else {
1012                         hns3_schedule_delayed_reset(hns);
1013                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1014                 }
1015
1016                 ret = HNS3VF_VECTOR0_EVENT_RST;
1017                 goto out;
1018         }
1019
1020         /* Check for vector0 mailbox(=CMDQ RX) event source */
1021         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1022                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1023                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1024                 goto out;
1025         }
1026
1027         val = 0;
1028         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1029 out:
1030         if (clearval)
1031                 *clearval = val;
1032         return ret;
1033 }
1034
1035 static void
1036 hns3vf_interrupt_handler(void *param)
1037 {
1038         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1039         struct hns3_adapter *hns = dev->data->dev_private;
1040         struct hns3_hw *hw = &hns->hw;
1041         enum hns3vf_evt_cause event_cause;
1042         uint32_t clearval;
1043
1044         if (hw->irq_thread_id == 0)
1045                 hw->irq_thread_id = pthread_self();
1046
1047         /* Disable interrupt */
1048         hns3vf_disable_irq0(hw);
1049
1050         /* Read out interrupt causes */
1051         event_cause = hns3vf_check_event_cause(hns, &clearval);
1052
1053         switch (event_cause) {
1054         case HNS3VF_VECTOR0_EVENT_RST:
1055                 hns3_schedule_reset(hns);
1056                 break;
1057         case HNS3VF_VECTOR0_EVENT_MBX:
1058                 hns3_dev_handle_mbx_msg(hw);
1059                 break;
1060         default:
1061                 break;
1062         }
1063
1064         /* Clear interrupt causes */
1065         hns3vf_clear_event_cause(hw, clearval);
1066
1067         /* Enable interrupt */
1068         hns3vf_enable_irq0(hw);
1069 }
1070
1071 static int
1072 hns3vf_get_capability(struct hns3_hw *hw)
1073 {
1074         struct rte_pci_device *pci_dev;
1075         struct rte_eth_dev *eth_dev;
1076         uint8_t revision;
1077         int ret;
1078
1079         eth_dev = &rte_eth_devices[hw->data->port_id];
1080         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1081
1082         /* Get PCI revision id */
1083         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1084                                   HNS3_PCI_REVISION_ID);
1085         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1086                 PMD_INIT_LOG(ERR, "failed to read pci revision id: %d", ret);
1087                 return -EIO;
1088         }
1089         hw->revision = revision;
1090
1091         return 0;
1092 }
1093
1094 static int
1095 hns3vf_check_tqp_info(struct hns3_hw *hw)
1096 {
1097         uint16_t tqps_num;
1098
1099         tqps_num = hw->tqps_num;
1100         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1101                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1102                                   "range: 1~%d",
1103                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1104                 return -EINVAL;
1105         }
1106
1107         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1108
1109         return 0;
1110 }
1111 static int
1112 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1113 {
1114         uint8_t resp_msg;
1115         int ret;
1116
1117         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1118                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1119                                 true, &resp_msg, sizeof(resp_msg));
1120         if (ret) {
1121                 if (ret == -ETIME) {
1122                         /*
1123                          * Getting current port based VLAN state from PF driver
1124                          * will not affect VF driver's basic function. Because
1125                          * the VF driver relies on hns3 PF kernel ether driver,
1126                          * to avoid introducing compatibility issues with older
1127                          * version of PF driver, no failure will be returned
1128                          * when the return value is ETIME. This return value has
1129                          * the following scenarios:
1130                          * 1) Firmware didn't return the results in time
1131                          * 2) the result return by firmware is timeout
1132                          * 3) the older version of kernel side PF driver does
1133                          *    not support this mailbox message.
1134                          * For scenarios 1 and 2, it is most likely that a
1135                          * hardware error has occurred, or a hardware reset has
1136                          * occurred. In this case, these errors will be caught
1137                          * by other functions.
1138                          */
1139                         PMD_INIT_LOG(WARNING,
1140                                 "failed to get PVID state for timeout, maybe "
1141                                 "kernel side PF driver doesn't support this "
1142                                 "mailbox message, or firmware didn't respond.");
1143                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1144                 } else {
1145                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1146                                 " ret = %d", ret);
1147                         return ret;
1148                 }
1149         }
1150         hw->port_base_vlan_cfg.state = resp_msg ?
1151                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1152         return 0;
1153 }
1154
1155 static int
1156 hns3vf_get_queue_info(struct hns3_hw *hw)
1157 {
1158 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1159         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1160         int ret;
1161
1162         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1163                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1164         if (ret) {
1165                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1166                 return ret;
1167         }
1168
1169         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1170         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1171
1172         return hns3vf_check_tqp_info(hw);
1173 }
1174
1175 static int
1176 hns3vf_get_queue_depth(struct hns3_hw *hw)
1177 {
1178 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1179         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1180         int ret;
1181
1182         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1183                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1184         if (ret) {
1185                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1186                              ret);
1187                 return ret;
1188         }
1189
1190         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1191         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1192
1193         return 0;
1194 }
1195
1196 static int
1197 hns3vf_get_tc_info(struct hns3_hw *hw)
1198 {
1199         uint8_t resp_msg;
1200         int ret;
1201
1202         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1203                                 true, &resp_msg, sizeof(resp_msg));
1204         if (ret) {
1205                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1206                          ret);
1207                 return ret;
1208         }
1209
1210         hw->hw_tc_map = resp_msg;
1211
1212         return 0;
1213 }
1214
1215 static int
1216 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1217 {
1218         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1219         int ret;
1220
1221         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1222                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1223         if (ret) {
1224                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1225                 return ret;
1226         }
1227
1228         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1229
1230         return 0;
1231 }
1232
1233 static int
1234 hns3vf_get_configuration(struct hns3_hw *hw)
1235 {
1236         int ret;
1237
1238         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1239         hw->rss_dis_flag = false;
1240
1241         /* Get device capability */
1242         ret = hns3vf_get_capability(hw);
1243         if (ret) {
1244                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1245                 return ret;
1246         }
1247
1248         /* Get queue configuration from PF */
1249         ret = hns3vf_get_queue_info(hw);
1250         if (ret)
1251                 return ret;
1252
1253         /* Get queue depth info from PF */
1254         ret = hns3vf_get_queue_depth(hw);
1255         if (ret)
1256                 return ret;
1257
1258         /* Get user defined VF MAC addr from PF */
1259         ret = hns3vf_get_host_mac_addr(hw);
1260         if (ret)
1261                 return ret;
1262
1263         ret = hns3vf_get_port_base_vlan_filter_state(hw);
1264         if (ret)
1265                 return ret;
1266
1267         /* Get tc configuration from PF */
1268         return hns3vf_get_tc_info(hw);
1269 }
1270
1271 static int
1272 hns3vf_set_tc_info(struct hns3_adapter *hns)
1273 {
1274         struct hns3_hw *hw = &hns->hw;
1275         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1276         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1277         uint8_t i;
1278
1279         hw->num_tc = 0;
1280         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1281                 if (hw->hw_tc_map & BIT(i))
1282                         hw->num_tc++;
1283
1284         if (nb_rx_q < hw->num_tc) {
1285                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1286                          nb_rx_q, hw->num_tc);
1287                 return -EINVAL;
1288         }
1289
1290         if (nb_tx_q < hw->num_tc) {
1291                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1292                          nb_tx_q, hw->num_tc);
1293                 return -EINVAL;
1294         }
1295
1296         hns3_set_rss_size(hw, nb_rx_q);
1297         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1298
1299         return 0;
1300 }
1301
1302 static void
1303 hns3vf_request_link_info(struct hns3_hw *hw)
1304 {
1305         uint8_t resp_msg;
1306         int ret;
1307
1308         if (rte_atomic16_read(&hw->reset.resetting))
1309                 return;
1310         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1311                                 &resp_msg, sizeof(resp_msg));
1312         if (ret)
1313                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1314 }
1315
1316 static int
1317 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1318 {
1319 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1320         struct hns3_hw *hw = &hns->hw;
1321         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1322         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1323         uint8_t is_kill = on ? 0 : 1;
1324
1325         msg_data[0] = is_kill;
1326         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1327         memcpy(&msg_data[3], &proto, sizeof(proto));
1328
1329         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1330                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1331                                  0);
1332 }
1333
1334 static int
1335 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1336 {
1337         struct hns3_adapter *hns = dev->data->dev_private;
1338         struct hns3_hw *hw = &hns->hw;
1339         int ret;
1340
1341         if (rte_atomic16_read(&hw->reset.resetting)) {
1342                 hns3_err(hw,
1343                          "vf set vlan id failed during resetting, vlan_id =%u",
1344                          vlan_id);
1345                 return -EIO;
1346         }
1347         rte_spinlock_lock(&hw->lock);
1348         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1349         rte_spinlock_unlock(&hw->lock);
1350         if (ret)
1351                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1352                          vlan_id, ret);
1353
1354         return ret;
1355 }
1356
1357 static int
1358 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1359 {
1360         uint8_t msg_data;
1361         int ret;
1362
1363         msg_data = enable ? 1 : 0;
1364         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1365                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1366         if (ret)
1367                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1368
1369         return ret;
1370 }
1371
1372 static int
1373 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1374 {
1375         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1377         unsigned int tmp_mask;
1378         int ret = 0;
1379
1380         if (rte_atomic16_read(&hw->reset.resetting)) {
1381                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1382                              "mask = 0x%x", mask);
1383                 return -EIO;
1384         }
1385
1386         tmp_mask = (unsigned int)mask;
1387         /* Vlan stripping setting */
1388         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1389                 rte_spinlock_lock(&hw->lock);
1390                 /* Enable or disable VLAN stripping */
1391                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1392                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1393                 else
1394                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1395                 rte_spinlock_unlock(&hw->lock);
1396         }
1397
1398         return ret;
1399 }
1400
1401 static int
1402 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1403 {
1404         struct rte_vlan_filter_conf *vfc;
1405         struct hns3_hw *hw = &hns->hw;
1406         uint16_t vlan_id;
1407         uint64_t vbit;
1408         uint64_t ids;
1409         int ret = 0;
1410         uint32_t i;
1411
1412         vfc = &hw->data->vlan_filter_conf;
1413         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1414                 if (vfc->ids[i] == 0)
1415                         continue;
1416                 ids = vfc->ids[i];
1417                 while (ids) {
1418                         /*
1419                          * 64 means the num bits of ids, one bit corresponds to
1420                          * one vlan id
1421                          */
1422                         vlan_id = 64 * i;
1423                         /* count trailing zeroes */
1424                         vbit = ~ids & (ids - 1);
1425                         /* clear least significant bit set */
1426                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1427                         for (; vbit;) {
1428                                 vbit >>= 1;
1429                                 vlan_id++;
1430                         }
1431                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1432                         if (ret) {
1433                                 hns3_err(hw,
1434                                          "VF handle vlan table failed, ret =%d, on = %d",
1435                                          ret, on);
1436                                 return ret;
1437                         }
1438                 }
1439         }
1440
1441         return ret;
1442 }
1443
1444 static int
1445 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1446 {
1447         return hns3vf_handle_all_vlan_table(hns, 0);
1448 }
1449
1450 static int
1451 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1452 {
1453         struct hns3_hw *hw = &hns->hw;
1454         struct rte_eth_conf *dev_conf;
1455         bool en;
1456         int ret;
1457
1458         dev_conf = &hw->data->dev_conf;
1459         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1460                                                                    : false;
1461         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1462         if (ret)
1463                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1464                          ret);
1465         return ret;
1466 }
1467
1468 static int
1469 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1470 {
1471         struct hns3_adapter *hns = dev->data->dev_private;
1472         struct rte_eth_dev_data *data = dev->data;
1473         struct hns3_hw *hw = &hns->hw;
1474         int ret;
1475
1476         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1477             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1478             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1479                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1480                               "or hw_vlan_insert_pvid is not support!");
1481         }
1482
1483         /* Apply vlan offload setting */
1484         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1485         if (ret)
1486                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1487
1488         return ret;
1489 }
1490
1491 static int
1492 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1493 {
1494         uint8_t msg_data;
1495
1496         msg_data = alive ? 1 : 0;
1497         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1498                                  sizeof(msg_data), false, NULL, 0);
1499 }
1500
1501 static void
1502 hns3vf_keep_alive_handler(void *param)
1503 {
1504         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1505         struct hns3_adapter *hns = eth_dev->data->dev_private;
1506         struct hns3_hw *hw = &hns->hw;
1507         uint8_t respmsg;
1508         int ret;
1509
1510         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1511                                 false, &respmsg, sizeof(uint8_t));
1512         if (ret)
1513                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1514                          ret);
1515
1516         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1517                           eth_dev);
1518 }
1519
1520 static void
1521 hns3vf_service_handler(void *param)
1522 {
1523         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1524         struct hns3_adapter *hns = eth_dev->data->dev_private;
1525         struct hns3_hw *hw = &hns->hw;
1526
1527         /*
1528          * The query link status and reset processing are executed in the
1529          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1530          * and the query operation will time out after 30ms. In the case of
1531          * multiple PF/VFs, each query failure timeout causes the IMP reset
1532          * interrupt to fail to respond within 100ms.
1533          * Before querying the link status, check whether there is a reset
1534          * pending, and if so, abandon the query.
1535          */
1536         if (!hns3vf_is_reset_pending(hns))
1537                 hns3vf_request_link_info(hw);
1538         else
1539                 hns3_warn(hw, "Cancel the query when reset is pending");
1540
1541         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1542                           eth_dev);
1543 }
1544
1545 static int
1546 hns3_query_vf_resource(struct hns3_hw *hw)
1547 {
1548         struct hns3_vf_res_cmd *req;
1549         struct hns3_cmd_desc desc;
1550         uint16_t num_msi;
1551         int ret;
1552
1553         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1554         ret = hns3_cmd_send(hw, &desc, 1);
1555         if (ret) {
1556                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1557                 return ret;
1558         }
1559
1560         req = (struct hns3_vf_res_cmd *)desc.data;
1561         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1562                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1563         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1564                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1565                          num_msi, HNS3_MIN_VECTOR_NUM);
1566                 return -EINVAL;
1567         }
1568
1569         hw->num_msi = num_msi;
1570
1571         return 0;
1572 }
1573
1574 static int
1575 hns3vf_init_hardware(struct hns3_adapter *hns)
1576 {
1577         struct hns3_hw *hw = &hns->hw;
1578         uint16_t mtu = hw->data->mtu;
1579         int ret;
1580
1581         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1582         if (ret)
1583                 return ret;
1584
1585         ret = hns3vf_config_mtu(hw, mtu);
1586         if (ret)
1587                 goto err_init_hardware;
1588
1589         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1590         if (ret) {
1591                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1592                 goto err_init_hardware;
1593         }
1594
1595         ret = hns3_config_gro(hw, false);
1596         if (ret) {
1597                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1598                 goto err_init_hardware;
1599         }
1600
1601         /*
1602          * In the initialization clearing the all hardware mapping relationship
1603          * configurations between queues and interrupt vectors is needed, so
1604          * some error caused by the residual configurations, such as the
1605          * unexpected interrupt, can be avoid.
1606          */
1607         ret = hns3vf_init_ring_with_vector(hw);
1608         if (ret) {
1609                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1610                 goto err_init_hardware;
1611         }
1612
1613         ret = hns3vf_set_alive(hw, true);
1614         if (ret) {
1615                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1616                 goto err_init_hardware;
1617         }
1618
1619         hns3vf_request_link_info(hw);
1620         return 0;
1621
1622 err_init_hardware:
1623         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1624         return ret;
1625 }
1626
1627 static int
1628 hns3vf_clear_vport_list(struct hns3_hw *hw)
1629 {
1630         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1631                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1632                                  NULL, 0);
1633 }
1634
1635 static int
1636 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1637 {
1638         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1639         struct hns3_adapter *hns = eth_dev->data->dev_private;
1640         struct hns3_hw *hw = &hns->hw;
1641         int ret;
1642
1643         PMD_INIT_FUNC_TRACE();
1644
1645         /* Get hardware io base address from pcie BAR2 IO space */
1646         hw->io_base = pci_dev->mem_resource[2].addr;
1647
1648         /* Firmware command queue initialize */
1649         ret = hns3_cmd_init_queue(hw);
1650         if (ret) {
1651                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1652                 goto err_cmd_init_queue;
1653         }
1654
1655         /* Firmware command initialize */
1656         ret = hns3_cmd_init(hw);
1657         if (ret) {
1658                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1659                 goto err_cmd_init;
1660         }
1661
1662         /* Get VF resource */
1663         ret = hns3_query_vf_resource(hw);
1664         if (ret)
1665                 goto err_cmd_init;
1666
1667         rte_spinlock_init(&hw->mbx_resp.lock);
1668
1669         hns3vf_clear_event_cause(hw, 0);
1670
1671         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1672                                          hns3vf_interrupt_handler, eth_dev);
1673         if (ret) {
1674                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1675                 goto err_intr_callback_register;
1676         }
1677
1678         /* Enable interrupt */
1679         rte_intr_enable(&pci_dev->intr_handle);
1680         hns3vf_enable_irq0(hw);
1681
1682         /* Get configuration from PF */
1683         ret = hns3vf_get_configuration(hw);
1684         if (ret) {
1685                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1686                 goto err_get_config;
1687         }
1688
1689         /*
1690          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1691          * on the host by "ip link set ..." command. To avoid some incorrect
1692          * scenes, for example, hns3 VF PMD driver fails to receive and send
1693          * packets after user configure the MAC address by using the
1694          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1695          * address strategy as the hns3 kernel ethdev driver in the
1696          * initialization. If user configure a MAC address by the ip command
1697          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1698          * start with a random MAC address in the initialization.
1699          */
1700         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1701         if (ret)
1702                 rte_eth_random_addr(hw->mac.mac_addr);
1703
1704         ret = hns3vf_clear_vport_list(hw);
1705         if (ret) {
1706                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1707                 goto err_get_config;
1708         }
1709
1710         ret = hns3vf_init_hardware(hns);
1711         if (ret)
1712                 goto err_get_config;
1713
1714         hns3_set_default_rss_args(hw);
1715
1716         return 0;
1717
1718 err_get_config:
1719         hns3vf_disable_irq0(hw);
1720         rte_intr_disable(&pci_dev->intr_handle);
1721         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1722                              eth_dev);
1723 err_intr_callback_register:
1724 err_cmd_init:
1725         hns3_cmd_uninit(hw);
1726         hns3_cmd_destroy_queue(hw);
1727 err_cmd_init_queue:
1728         hw->io_base = NULL;
1729
1730         return ret;
1731 }
1732
1733 static void
1734 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1735 {
1736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1737         struct hns3_adapter *hns = eth_dev->data->dev_private;
1738         struct hns3_hw *hw = &hns->hw;
1739
1740         PMD_INIT_FUNC_TRACE();
1741
1742         hns3_rss_uninit(hns);
1743         (void)hns3_config_gro(hw, false);
1744         (void)hns3vf_set_alive(hw, false);
1745         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1746         hns3vf_disable_irq0(hw);
1747         rte_intr_disable(&pci_dev->intr_handle);
1748         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1749                              eth_dev);
1750         hns3_cmd_uninit(hw);
1751         hns3_cmd_destroy_queue(hw);
1752         hw->io_base = NULL;
1753 }
1754
1755 static int
1756 hns3vf_do_stop(struct hns3_adapter *hns)
1757 {
1758         struct hns3_hw *hw = &hns->hw;
1759         bool reset_queue;
1760
1761         hw->mac.link_status = ETH_LINK_DOWN;
1762
1763         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1764                 hns3vf_configure_mac_addr(hns, true);
1765                 reset_queue = true;
1766         } else
1767                 reset_queue = false;
1768         return hns3_stop_queues(hns, reset_queue);
1769 }
1770
1771 static void
1772 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1773 {
1774         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1776         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1777         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1778         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1779         uint16_t q_id;
1780
1781         if (dev->data->dev_conf.intr_conf.rxq == 0)
1782                 return;
1783
1784         /* unmap the ring with vector */
1785         if (rte_intr_allow_others(intr_handle)) {
1786                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1787                 base = RTE_INTR_VEC_RXTX_OFFSET;
1788         }
1789         if (rte_intr_dp_is_en(intr_handle)) {
1790                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1791                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1792                                                            HNS3_RING_TYPE_RX,
1793                                                            q_id);
1794                         if (vec < base + intr_handle->nb_efd - 1)
1795                                 vec++;
1796                 }
1797         }
1798         /* Clean datapath event and queue/vec mapping */
1799         rte_intr_efd_disable(intr_handle);
1800         if (intr_handle->intr_vec) {
1801                 rte_free(intr_handle->intr_vec);
1802                 intr_handle->intr_vec = NULL;
1803         }
1804 }
1805
1806 static void
1807 hns3vf_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         struct hns3_adapter *hns = dev->data->dev_private;
1810         struct hns3_hw *hw = &hns->hw;
1811
1812         PMD_INIT_FUNC_TRACE();
1813
1814         hw->adapter_state = HNS3_NIC_STOPPING;
1815         hns3_set_rxtx_function(dev);
1816         rte_wmb();
1817         /* Disable datapath on secondary process. */
1818         hns3_mp_req_stop_rxtx(dev);
1819         /* Prevent crashes when queues are still in use. */
1820         rte_delay_ms(hw->tqps_num);
1821
1822         rte_spinlock_lock(&hw->lock);
1823         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1824                 hns3vf_do_stop(hns);
1825                 hns3vf_unmap_rx_interrupt(dev);
1826                 hns3_dev_release_mbufs(hns);
1827                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1828         }
1829         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1830         rte_spinlock_unlock(&hw->lock);
1831 }
1832
1833 static void
1834 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1835 {
1836         struct hns3_adapter *hns = eth_dev->data->dev_private;
1837         struct hns3_hw *hw = &hns->hw;
1838
1839         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1840                 return;
1841
1842         if (hw->adapter_state == HNS3_NIC_STARTED)
1843                 hns3vf_dev_stop(eth_dev);
1844
1845         hw->adapter_state = HNS3_NIC_CLOSING;
1846         hns3_reset_abort(hns);
1847         hw->adapter_state = HNS3_NIC_CLOSED;
1848         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1849         hns3vf_configure_all_mc_mac_addr(hns, true);
1850         hns3vf_remove_all_vlan_table(hns);
1851         hns3vf_uninit_vf(eth_dev);
1852         hns3_free_all_queues(eth_dev);
1853         rte_free(hw->reset.wait_data);
1854         rte_free(eth_dev->process_private);
1855         eth_dev->process_private = NULL;
1856         hns3_mp_uninit_primary();
1857         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1858 }
1859
1860 static int
1861 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1862                       size_t fw_size)
1863 {
1864         struct hns3_adapter *hns = eth_dev->data->dev_private;
1865         struct hns3_hw *hw = &hns->hw;
1866         uint32_t version = hw->fw_version;
1867         int ret;
1868
1869         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1870                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1871                                       HNS3_FW_VERSION_BYTE3_S),
1872                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1873                                       HNS3_FW_VERSION_BYTE2_S),
1874                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1875                                       HNS3_FW_VERSION_BYTE1_S),
1876                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1877                                       HNS3_FW_VERSION_BYTE0_S));
1878         ret += 1; /* add the size of '\0' */
1879         if (fw_size < (uint32_t)ret)
1880                 return ret;
1881         else
1882                 return 0;
1883 }
1884
1885 static int
1886 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1887                        __rte_unused int wait_to_complete)
1888 {
1889         struct hns3_adapter *hns = eth_dev->data->dev_private;
1890         struct hns3_hw *hw = &hns->hw;
1891         struct hns3_mac *mac = &hw->mac;
1892         struct rte_eth_link new_link;
1893
1894         memset(&new_link, 0, sizeof(new_link));
1895         switch (mac->link_speed) {
1896         case ETH_SPEED_NUM_10M:
1897         case ETH_SPEED_NUM_100M:
1898         case ETH_SPEED_NUM_1G:
1899         case ETH_SPEED_NUM_10G:
1900         case ETH_SPEED_NUM_25G:
1901         case ETH_SPEED_NUM_40G:
1902         case ETH_SPEED_NUM_50G:
1903         case ETH_SPEED_NUM_100G:
1904         case ETH_SPEED_NUM_200G:
1905                 new_link.link_speed = mac->link_speed;
1906                 break;
1907         default:
1908                 new_link.link_speed = ETH_SPEED_NUM_100M;
1909                 break;
1910         }
1911
1912         new_link.link_duplex = mac->link_duplex;
1913         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1914         new_link.link_autoneg =
1915             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1916
1917         return rte_eth_linkstatus_set(eth_dev, &new_link);
1918 }
1919
1920 static int
1921 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1922 {
1923         struct hns3_hw *hw = &hns->hw;
1924         int ret;
1925
1926         ret = hns3vf_set_tc_info(hns);
1927         if (ret)
1928                 return ret;
1929
1930         ret = hns3_start_queues(hns, reset_queue);
1931         if (ret)
1932                 hns3_err(hw, "Failed to start queues: %d", ret);
1933
1934         return ret;
1935 }
1936
1937 static int
1938 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1939 {
1940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1941         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1942         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1944         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1945         uint32_t intr_vector;
1946         uint16_t q_id;
1947         int ret;
1948
1949         if (dev->data->dev_conf.intr_conf.rxq == 0)
1950                 return 0;
1951
1952         /* disable uio/vfio intr/eventfd mapping */
1953         rte_intr_disable(intr_handle);
1954
1955         /* check and configure queue intr-vector mapping */
1956         if (rte_intr_cap_multiple(intr_handle) ||
1957             !RTE_ETH_DEV_SRIOV(dev).active) {
1958                 intr_vector = hw->used_rx_queues;
1959                 /* It creates event fd for each intr vector when MSIX is used */
1960                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1961                         return -EINVAL;
1962         }
1963         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1964                 intr_handle->intr_vec =
1965                         rte_zmalloc("intr_vec",
1966                                     hw->used_rx_queues * sizeof(int), 0);
1967                 if (intr_handle->intr_vec == NULL) {
1968                         hns3_err(hw, "Failed to allocate %d rx_queues"
1969                                      " intr_vec", hw->used_rx_queues);
1970                         ret = -ENOMEM;
1971                         goto vf_alloc_intr_vec_error;
1972                 }
1973         }
1974
1975         if (rte_intr_allow_others(intr_handle)) {
1976                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1977                 base = RTE_INTR_VEC_RXTX_OFFSET;
1978         }
1979         if (rte_intr_dp_is_en(intr_handle)) {
1980                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1981                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1982                                                            HNS3_RING_TYPE_RX,
1983                                                            q_id);
1984                         if (ret)
1985                                 goto vf_bind_vector_error;
1986                         intr_handle->intr_vec[q_id] = vec;
1987                         if (vec < base + intr_handle->nb_efd - 1)
1988                                 vec++;
1989                 }
1990         }
1991         rte_intr_enable(intr_handle);
1992         return 0;
1993
1994 vf_bind_vector_error:
1995         rte_intr_efd_disable(intr_handle);
1996         if (intr_handle->intr_vec) {
1997                 free(intr_handle->intr_vec);
1998                 intr_handle->intr_vec = NULL;
1999         }
2000         return ret;
2001 vf_alloc_intr_vec_error:
2002         rte_intr_efd_disable(intr_handle);
2003         return ret;
2004 }
2005
2006 static int
2007 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2008 {
2009         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2011         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2012         uint16_t q_id;
2013         int ret;
2014
2015         if (dev->data->dev_conf.intr_conf.rxq == 0)
2016                 return 0;
2017
2018         if (rte_intr_dp_is_en(intr_handle)) {
2019                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2020                         ret = hns3vf_bind_ring_with_vector(hw,
2021                                         intr_handle->intr_vec[q_id], true,
2022                                         HNS3_RING_TYPE_RX, q_id);
2023                         if (ret)
2024                                 return ret;
2025                 }
2026         }
2027
2028         return 0;
2029 }
2030
2031 static void
2032 hns3vf_restore_filter(struct rte_eth_dev *dev)
2033 {
2034         hns3_restore_rss_filter(dev);
2035 }
2036
2037 static int
2038 hns3vf_dev_start(struct rte_eth_dev *dev)
2039 {
2040         struct hns3_adapter *hns = dev->data->dev_private;
2041         struct hns3_hw *hw = &hns->hw;
2042         int ret;
2043
2044         PMD_INIT_FUNC_TRACE();
2045         if (rte_atomic16_read(&hw->reset.resetting))
2046                 return -EBUSY;
2047
2048         rte_spinlock_lock(&hw->lock);
2049         hw->adapter_state = HNS3_NIC_STARTING;
2050         ret = hns3vf_do_start(hns, true);
2051         if (ret) {
2052                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2053                 rte_spinlock_unlock(&hw->lock);
2054                 return ret;
2055         }
2056         ret = hns3vf_map_rx_interrupt(dev);
2057         if (ret) {
2058                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2059                 rte_spinlock_unlock(&hw->lock);
2060                 return ret;
2061         }
2062         hw->adapter_state = HNS3_NIC_STARTED;
2063         rte_spinlock_unlock(&hw->lock);
2064
2065         hns3_set_rxtx_function(dev);
2066         hns3_mp_req_start_rxtx(dev);
2067         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
2068
2069         hns3vf_restore_filter(dev);
2070
2071         /* Enable interrupt of all rx queues before enabling queues */
2072         hns3_dev_all_rx_queue_intr_enable(hw, true);
2073         /*
2074          * When finished the initialization, enable queues to receive/transmit
2075          * packets.
2076          */
2077         hns3_enable_all_queues(hw, true);
2078
2079         return ret;
2080 }
2081
2082 static bool
2083 is_vf_reset_done(struct hns3_hw *hw)
2084 {
2085 #define HNS3_FUN_RST_ING_BITS \
2086         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2087          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2088          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2089          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2090
2091         uint32_t val;
2092
2093         if (hw->reset.level == HNS3_VF_RESET) {
2094                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2095                 if (val & HNS3_VF_RST_ING_BIT)
2096                         return false;
2097         } else {
2098                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2099                 if (val & HNS3_FUN_RST_ING_BITS)
2100                         return false;
2101         }
2102         return true;
2103 }
2104
2105 bool
2106 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2107 {
2108         struct hns3_hw *hw = &hns->hw;
2109         enum hns3_reset_level reset;
2110
2111         hns3vf_check_event_cause(hns, NULL);
2112         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2113         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2114                 hns3_warn(hw, "High level reset %d is pending", reset);
2115                 return true;
2116         }
2117         return false;
2118 }
2119
2120 static int
2121 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2122 {
2123         struct hns3_hw *hw = &hns->hw;
2124         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2125         struct timeval tv;
2126
2127         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2128                 /*
2129                  * After vf reset is ready, the PF may not have completed
2130                  * the reset processing. The vf sending mbox to PF may fail
2131                  * during the pf reset, so it is better to add extra delay.
2132                  */
2133                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2134                     hw->reset.level == HNS3_FLR_RESET)
2135                         return 0;
2136                 /* Reset retry process, no need to add extra delay. */
2137                 if (hw->reset.attempts)
2138                         return 0;
2139                 if (wait_data->check_completion == NULL)
2140                         return 0;
2141
2142                 wait_data->check_completion = NULL;
2143                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2144                 wait_data->count = 1;
2145                 wait_data->result = HNS3_WAIT_REQUEST;
2146                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2147                                   wait_data);
2148                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2149                 return -EAGAIN;
2150         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2151                 gettimeofday(&tv, NULL);
2152                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2153                           tv.tv_sec, tv.tv_usec);
2154                 return -ETIME;
2155         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2156                 return -EAGAIN;
2157
2158         wait_data->hns = hns;
2159         wait_data->check_completion = is_vf_reset_done;
2160         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2161                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2162         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2163         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2164         wait_data->result = HNS3_WAIT_REQUEST;
2165         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2166         return -EAGAIN;
2167 }
2168
2169 static int
2170 hns3vf_prepare_reset(struct hns3_adapter *hns)
2171 {
2172         struct hns3_hw *hw = &hns->hw;
2173         int ret = 0;
2174
2175         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2176                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2177                                         0, true, NULL, 0);
2178         }
2179         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2180
2181         return ret;
2182 }
2183
2184 static int
2185 hns3vf_stop_service(struct hns3_adapter *hns)
2186 {
2187         struct hns3_hw *hw = &hns->hw;
2188         struct rte_eth_dev *eth_dev;
2189
2190         eth_dev = &rte_eth_devices[hw->data->port_id];
2191         if (hw->adapter_state == HNS3_NIC_STARTED)
2192                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2193         hw->mac.link_status = ETH_LINK_DOWN;
2194
2195         hns3_set_rxtx_function(eth_dev);
2196         rte_wmb();
2197         /* Disable datapath on secondary process. */
2198         hns3_mp_req_stop_rxtx(eth_dev);
2199         rte_delay_ms(hw->tqps_num);
2200
2201         rte_spinlock_lock(&hw->lock);
2202         if (hw->adapter_state == HNS3_NIC_STARTED ||
2203             hw->adapter_state == HNS3_NIC_STOPPING) {
2204                 hns3vf_do_stop(hns);
2205                 hw->reset.mbuf_deferred_free = true;
2206         } else
2207                 hw->reset.mbuf_deferred_free = false;
2208
2209         /*
2210          * It is cumbersome for hardware to pick-and-choose entries for deletion
2211          * from table space. Hence, for function reset software intervention is
2212          * required to delete the entries.
2213          */
2214         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2215                 hns3vf_configure_all_mc_mac_addr(hns, true);
2216         rte_spinlock_unlock(&hw->lock);
2217
2218         return 0;
2219 }
2220
2221 static int
2222 hns3vf_start_service(struct hns3_adapter *hns)
2223 {
2224         struct hns3_hw *hw = &hns->hw;
2225         struct rte_eth_dev *eth_dev;
2226
2227         eth_dev = &rte_eth_devices[hw->data->port_id];
2228         hns3_set_rxtx_function(eth_dev);
2229         hns3_mp_req_start_rxtx(eth_dev);
2230         if (hw->adapter_state == HNS3_NIC_STARTED) {
2231                 hns3vf_service_handler(eth_dev);
2232
2233                 /* Enable interrupt of all rx queues before enabling queues */
2234                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2235                 /*
2236                  * When finished the initialization, enable queues to receive
2237                  * and transmit packets.
2238                  */
2239                 hns3_enable_all_queues(hw, true);
2240         }
2241
2242         return 0;
2243 }
2244
2245 static int
2246 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2247 {
2248         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2249         struct rte_ether_addr *hw_mac;
2250         int ret;
2251
2252         /*
2253          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2254          * on the host by "ip link set ..." command. If the hns3 PF kernel
2255          * ethdev driver sets the MAC address for VF device after the
2256          * initialization of the related VF device, the PF driver will notify
2257          * VF driver to reset VF device to make the new MAC address effective
2258          * immediately. The hns3 VF PMD driver should check whether the MAC
2259          * address has been changed by the PF kernel ethdev driver, if changed
2260          * VF driver should configure hardware using the new MAC address in the
2261          * recovering hardware configuration stage of the reset process.
2262          */
2263         ret = hns3vf_get_host_mac_addr(hw);
2264         if (ret)
2265                 return ret;
2266
2267         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2268         ret = rte_is_zero_ether_addr(hw_mac);
2269         if (ret) {
2270                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2271         } else {
2272                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2273                 if (!ret) {
2274                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2275                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2276                                               &hw->data->mac_addrs[0]);
2277                         hns3_warn(hw, "Default MAC address has been changed to:"
2278                                   " %s by the host PF kernel ethdev driver",
2279                                   mac_str);
2280                 }
2281         }
2282
2283         return 0;
2284 }
2285
2286 static int
2287 hns3vf_restore_conf(struct hns3_adapter *hns)
2288 {
2289         struct hns3_hw *hw = &hns->hw;
2290         int ret;
2291
2292         ret = hns3vf_check_default_mac_change(hw);
2293         if (ret)
2294                 return ret;
2295
2296         ret = hns3vf_configure_mac_addr(hns, false);
2297         if (ret)
2298                 return ret;
2299
2300         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2301         if (ret)
2302                 goto err_mc_mac;
2303
2304         ret = hns3vf_restore_promisc(hns);
2305         if (ret)
2306                 goto err_vlan_table;
2307
2308         ret = hns3vf_restore_vlan_conf(hns);
2309         if (ret)
2310                 goto err_vlan_table;
2311
2312         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2313         if (ret)
2314                 goto err_vlan_table;
2315
2316         ret = hns3vf_restore_rx_interrupt(hw);
2317         if (ret)
2318                 goto err_vlan_table;
2319
2320         ret = hns3_restore_gro_conf(hw);
2321         if (ret)
2322                 goto err_vlan_table;
2323
2324         if (hw->adapter_state == HNS3_NIC_STARTED) {
2325                 ret = hns3vf_do_start(hns, false);
2326                 if (ret)
2327                         goto err_vlan_table;
2328                 hns3_info(hw, "hns3vf dev restart successful!");
2329         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2330                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2331         return 0;
2332
2333 err_vlan_table:
2334         hns3vf_configure_all_mc_mac_addr(hns, true);
2335 err_mc_mac:
2336         hns3vf_configure_mac_addr(hns, true);
2337         return ret;
2338 }
2339
2340 static enum hns3_reset_level
2341 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2342 {
2343         enum hns3_reset_level reset_level;
2344
2345         /* return the highest priority reset level amongst all */
2346         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2347                 reset_level = HNS3_VF_RESET;
2348         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2349                 reset_level = HNS3_VF_FULL_RESET;
2350         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2351                 reset_level = HNS3_VF_PF_FUNC_RESET;
2352         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2353                 reset_level = HNS3_VF_FUNC_RESET;
2354         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2355                 reset_level = HNS3_FLR_RESET;
2356         else
2357                 reset_level = HNS3_NONE_RESET;
2358
2359         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2360                 return HNS3_NONE_RESET;
2361
2362         return reset_level;
2363 }
2364
2365 static void
2366 hns3vf_reset_service(void *param)
2367 {
2368         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2369         struct hns3_hw *hw = &hns->hw;
2370         enum hns3_reset_level reset_level;
2371         struct timeval tv_delta;
2372         struct timeval tv_start;
2373         struct timeval tv;
2374         uint64_t msec;
2375
2376         /*
2377          * The interrupt is not triggered within the delay time.
2378          * The interrupt may have been lost. It is necessary to handle
2379          * the interrupt to recover from the error.
2380          */
2381         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2382                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2383                 hns3_err(hw, "Handling interrupts in delayed tasks");
2384                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2385                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2386                 if (reset_level == HNS3_NONE_RESET) {
2387                         hns3_err(hw, "No reset level is set, try global reset");
2388                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2389                 }
2390         }
2391         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2392
2393         /*
2394          * Hardware reset has been notified, we now have to poll & check if
2395          * hardware has actually completed the reset sequence.
2396          */
2397         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2398         if (reset_level != HNS3_NONE_RESET) {
2399                 gettimeofday(&tv_start, NULL);
2400                 hns3_reset_process(hns, reset_level);
2401                 gettimeofday(&tv, NULL);
2402                 timersub(&tv, &tv_start, &tv_delta);
2403                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2404                        tv_delta.tv_usec / USEC_PER_MSEC;
2405                 if (msec > HNS3_RESET_PROCESS_MS)
2406                         hns3_err(hw, "%d handle long time delta %" PRIx64
2407                                  " ms time=%ld.%.6ld",
2408                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2409         }
2410 }
2411
2412 static int
2413 hns3vf_reinit_dev(struct hns3_adapter *hns)
2414 {
2415         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2416         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2417         struct hns3_hw *hw = &hns->hw;
2418         int ret;
2419
2420         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2421                 rte_intr_disable(&pci_dev->intr_handle);
2422                 hns3vf_set_bus_master(pci_dev, true);
2423         }
2424
2425         /* Firmware command initialize */
2426         ret = hns3_cmd_init(hw);
2427         if (ret) {
2428                 hns3_err(hw, "Failed to init cmd: %d", ret);
2429                 return ret;
2430         }
2431
2432         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2433                 /*
2434                  * UIO enables msix by writing the pcie configuration space
2435                  * vfio_pci enables msix in rte_intr_enable.
2436                  */
2437                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2438                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2439                         if (hns3vf_enable_msix(pci_dev, true))
2440                                 hns3_err(hw, "Failed to enable msix");
2441                 }
2442
2443                 rte_intr_enable(&pci_dev->intr_handle);
2444         }
2445
2446         ret = hns3_reset_all_queues(hns);
2447         if (ret) {
2448                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2449                 return ret;
2450         }
2451
2452         ret = hns3vf_init_hardware(hns);
2453         if (ret) {
2454                 hns3_err(hw, "Failed to init hardware: %d", ret);
2455                 return ret;
2456         }
2457
2458         return 0;
2459 }
2460
2461 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2462         .dev_start          = hns3vf_dev_start,
2463         .dev_stop           = hns3vf_dev_stop,
2464         .dev_close          = hns3vf_dev_close,
2465         .mtu_set            = hns3vf_dev_mtu_set,
2466         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2467         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2468         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2469         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2470         .stats_get          = hns3_stats_get,
2471         .stats_reset        = hns3_stats_reset,
2472         .xstats_get         = hns3_dev_xstats_get,
2473         .xstats_get_names   = hns3_dev_xstats_get_names,
2474         .xstats_reset       = hns3_dev_xstats_reset,
2475         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2476         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2477         .dev_infos_get      = hns3vf_dev_infos_get,
2478         .fw_version_get     = hns3vf_fw_version_get,
2479         .rx_queue_setup     = hns3_rx_queue_setup,
2480         .tx_queue_setup     = hns3_tx_queue_setup,
2481         .rx_queue_release   = hns3_dev_rx_queue_release,
2482         .tx_queue_release   = hns3_dev_tx_queue_release,
2483         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2484         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2485         .dev_configure      = hns3vf_dev_configure,
2486         .mac_addr_add       = hns3vf_add_mac_addr,
2487         .mac_addr_remove    = hns3vf_remove_mac_addr,
2488         .mac_addr_set       = hns3vf_set_default_mac_addr,
2489         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2490         .link_update        = hns3vf_dev_link_update,
2491         .rss_hash_update    = hns3_dev_rss_hash_update,
2492         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2493         .reta_update        = hns3_dev_rss_reta_update,
2494         .reta_query         = hns3_dev_rss_reta_query,
2495         .filter_ctrl        = hns3_dev_filter_ctrl,
2496         .vlan_filter_set    = hns3vf_vlan_filter_set,
2497         .vlan_offload_set   = hns3vf_vlan_offload_set,
2498         .get_reg            = hns3_get_regs,
2499         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2500 };
2501
2502 static const struct hns3_reset_ops hns3vf_reset_ops = {
2503         .reset_service       = hns3vf_reset_service,
2504         .stop_service        = hns3vf_stop_service,
2505         .prepare_reset       = hns3vf_prepare_reset,
2506         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2507         .reinit_dev          = hns3vf_reinit_dev,
2508         .restore_conf        = hns3vf_restore_conf,
2509         .start_service       = hns3vf_start_service,
2510 };
2511
2512 static int
2513 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2514 {
2515         struct hns3_adapter *hns = eth_dev->data->dev_private;
2516         struct hns3_hw *hw = &hns->hw;
2517         int ret;
2518
2519         PMD_INIT_FUNC_TRACE();
2520
2521         eth_dev->process_private = (struct hns3_process_private *)
2522             rte_zmalloc_socket("hns3_filter_list",
2523                                sizeof(struct hns3_process_private),
2524                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2525         if (eth_dev->process_private == NULL) {
2526                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2527                 return -ENOMEM;
2528         }
2529
2530         /* initialize flow filter lists */
2531         hns3_filterlist_init(eth_dev);
2532
2533         hns3_set_rxtx_function(eth_dev);
2534         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2535         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2536                 ret = hns3_mp_init_secondary();
2537                 if (ret) {
2538                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2539                                           "process, ret = %d", ret);
2540                         goto err_mp_init_secondary;
2541                 }
2542
2543                 hw->secondary_cnt++;
2544                 return 0;
2545         }
2546
2547         ret = hns3_mp_init_primary();
2548         if (ret) {
2549                 PMD_INIT_LOG(ERR,
2550                              "Failed to init for primary process, ret = %d",
2551                              ret);
2552                 goto err_mp_init_primary;
2553         }
2554
2555         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2556         hns->is_vf = true;
2557         hw->data = eth_dev->data;
2558
2559         ret = hns3_reset_init(hw);
2560         if (ret)
2561                 goto err_init_reset;
2562         hw->reset.ops = &hns3vf_reset_ops;
2563
2564         ret = hns3vf_init_vf(eth_dev);
2565         if (ret) {
2566                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2567                 goto err_init_vf;
2568         }
2569
2570         /* Allocate memory for storing MAC addresses */
2571         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2572                                                sizeof(struct rte_ether_addr) *
2573                                                HNS3_VF_UC_MACADDR_NUM, 0);
2574         if (eth_dev->data->mac_addrs == NULL) {
2575                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2576                              "to store MAC addresses",
2577                              sizeof(struct rte_ether_addr) *
2578                              HNS3_VF_UC_MACADDR_NUM);
2579                 ret = -ENOMEM;
2580                 goto err_rte_zmalloc;
2581         }
2582
2583         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2584                             &eth_dev->data->mac_addrs[0]);
2585         hw->adapter_state = HNS3_NIC_INITIALIZED;
2586         /*
2587          * Pass the information to the rte_eth_dev_close() that it should also
2588          * release the private port resources.
2589          */
2590         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2591
2592         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2593                 hns3_err(hw, "Reschedule reset service after dev_init");
2594                 hns3_schedule_reset(hns);
2595         } else {
2596                 /* IMP will wait ready flag before reset */
2597                 hns3_notify_reset_ready(hw, false);
2598         }
2599         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2600                           eth_dev);
2601         return 0;
2602
2603 err_rte_zmalloc:
2604         hns3vf_uninit_vf(eth_dev);
2605
2606 err_init_vf:
2607         rte_free(hw->reset.wait_data);
2608
2609 err_init_reset:
2610         hns3_mp_uninit_primary();
2611
2612 err_mp_init_primary:
2613 err_mp_init_secondary:
2614         eth_dev->dev_ops = NULL;
2615         eth_dev->rx_pkt_burst = NULL;
2616         eth_dev->tx_pkt_burst = NULL;
2617         eth_dev->tx_pkt_prepare = NULL;
2618         rte_free(eth_dev->process_private);
2619         eth_dev->process_private = NULL;
2620
2621         return ret;
2622 }
2623
2624 static int
2625 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2626 {
2627         struct hns3_adapter *hns = eth_dev->data->dev_private;
2628         struct hns3_hw *hw = &hns->hw;
2629
2630         PMD_INIT_FUNC_TRACE();
2631
2632         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2633                 return -EPERM;
2634
2635         eth_dev->dev_ops = NULL;
2636         eth_dev->rx_pkt_burst = NULL;
2637         eth_dev->tx_pkt_burst = NULL;
2638         eth_dev->tx_pkt_prepare = NULL;
2639
2640         if (hw->adapter_state < HNS3_NIC_CLOSING)
2641                 hns3vf_dev_close(eth_dev);
2642
2643         hw->adapter_state = HNS3_NIC_REMOVED;
2644         return 0;
2645 }
2646
2647 static int
2648 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2649                      struct rte_pci_device *pci_dev)
2650 {
2651         return rte_eth_dev_pci_generic_probe(pci_dev,
2652                                              sizeof(struct hns3_adapter),
2653                                              hns3vf_dev_init);
2654 }
2655
2656 static int
2657 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2658 {
2659         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2660 }
2661
2662 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2663         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2664         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2665         { .vendor_id = 0, /* sentinel */ },
2666 };
2667
2668 static struct rte_pci_driver rte_hns3vf_pmd = {
2669         .id_table = pci_id_hns3vf_map,
2670         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2671         .probe = eth_hns3vf_pci_probe,
2672         .remove = eth_hns3vf_pci_remove,
2673 };
2674
2675 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2676 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2677 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");